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Talk as presented plus example source for MSP432 blinky light demo

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This commit is contained in:
Levi Pearson
2019-03-18 11:18:16 -06:00
parent a7eedbbf68
commit 4499e75a92
605 changed files with 218085 additions and 13 deletions
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33
example-source/msp432-app/.cargo/config Normal file
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#[target.thumbv7m-none-eabi]
# uncomment this to make `cargo run` execute programs on QEMU
# runner = "qemu-system-arm -cpu cortex-m3 -machine lm3s6965evb -nographic -semihosting-config enable=on,target=native -kernel"
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
# uncomment ONE of these three option to make `cargo run` start a GDB session
# which option to pick depends on your system
# runner = "arm-none-eabi-gdb -q -x openocd.gdb"
runner = "gdb-multiarch -q -x openocd.gdb"
# runner = "gdb -q -x openocd.gdb"
rustflags = [
# LLD (shipped with the Rust toolchain) is used as the default linker
"-C", "link-arg=-Tlink.x",
# if you run into problems with LLD switch to the GNU linker by commenting out
# this line
# "-C", "linker=arm-none-eabi-ld",
# if you need to link to pre-compiled C libraries provided by a C toolchain
# use GCC as the linker by commenting out both lines above and then
# uncommenting the three lines below
# "-C", "linker=arm-none-eabi-gcc",
# "-C", "link-arg=-Wl,-Tlink.x",
# "-C", "link-arg=-nostartfiles",
]
[build]
# Pick ONE of these compilation targets
# target = "thumbv6m-none-eabi" # Cortex-M0 and Cortex-M0+
# target = "thumbv7m-none-eabi" # Cortex-M3
# target = "thumbv7em-none-eabi" # Cortex-M4 and Cortex-M7 (no FPU)
target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)

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**/*.rs.bk
.#*
.gdb_history
Cargo.lock
target/

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[package]
authors = ["Levi Pearson <levipearson@gmail.com>"]
edition = "2018"
readme = "README.md"
name = "msp432-app"
version = "0.1.0"
[dependencies]
cortex-m = "0.5.8"
cortex-m-rt = "0.6.5"
cortex-m-semihosting = "0.3.2"
panic-halt = "0.2.0"
panic-semihosting = "*"
msp432p401r = { path = "../msp432p401r", features = ["rt"] }
# Uncomment for the panic example.
# panic-itm = "0.4.0"
# Uncomment for the allocator example.
# alloc-cortex-m = "0.3.5"
# this lets you use `cargo fix`!
[[bin]]
name = "msp432-app"
test = false
bench = false
[profile.release]
codegen-units = 1 # better optimizations
debug = true # symbols are nice and they don't increase the size on Flash
lto = true # better optimizations

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# `cortex-m-quickstart`
> A template for building applications for ARM Cortex-M microcontrollers
This project is developed and maintained by the [Cortex-M team][team].
## Dependencies
To build embedded programs using this template you'll need:
- Rust 1.31, 1.30-beta, nightly-2018-09-13 or a newer toolchain. e.g. `rustup
default beta`
- The `cargo generate` subcommand. [Installation
instructions](https://github.com/ashleygwilliams/cargo-generate#installation).
- `rust-std` components (pre-compiled `core` crate) for the ARM Cortex-M
targets. Run:
``` console
$ rustup target add thumbv6m-none-eabi thumbv7m-none-eabi thumbv7em-none-eabi thumbv7em-none-eabihf
```
## Using this template
**NOTE**: This is the very short version that only covers building programs. For
the long version, which additionally covers flashing, running and debugging
programs, check [the embedded Rust book][book].
[book]: https://rust-embedded.github.io/book
0. Before we begin you need to identify some characteristics of the target
device as these will be used to configure the project:
- The ARM core. e.g. Cortex-M3.
- Does the ARM core include an FPU? Cortex-M4**F** and Cortex-M7**F** cores do.
- How much Flash memory and RAM does the target device has? e.g. 256 KiB of
Flash and 32 KiB of RAM.
- Where are Flash memory and RAM mapped in the address space? e.g. RAM is
commonly located at address `0x2000_0000`.
You can find this information in the data sheet or the reference manual of your
device.
In this example we'll be using the STM32F3DISCOVERY. This board contains an
STM32F303VCT6 microcontroller. This microcontroller has:
- A Cortex-M4F core that includes a single precision FPU
- 256 KiB of Flash located at address 0x0800_0000.
- 40 KiB of RAM located at address 0x2000_0000. (There's another RAM region but
for simplicity we'll ignore it).
1. Instantiate the template.
``` console
$ cargo generate --git https://github.com/rust-embedded/cortex-m-quickstart
Project Name: app
Creating project called `app`...
Done! New project created /tmp/app
$ cd app
```
2. Set a default compilation target. There are four options as mentioned at the
bottom of `.cargo/config`. For the STM32F303VCT6, which has a Cortex-M4F
core, we'll pick the `thumbv7em-none-eabihf` target.
``` console
$ tail -n6 .cargo/config
```
``` toml
[build]
# Pick ONE of these compilation targets
# target = "thumbv6m-none-eabi" # Cortex-M0 and Cortex-M0+
# target = "thumbv7m-none-eabi" # Cortex-M3
# target = "thumbv7em-none-eabi" # Cortex-M4 and Cortex-M7 (no FPU)
target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
```
3. Enter the memory region information into the `memory.x` file.
``` console
$ cat memory.x
/* Linker script for the STM32F303VCT6 */
MEMORY
{
/* NOTE 1 K = 1 KiBi = 1024 bytes */
FLASH : ORIGIN = 0x08000000, LENGTH = 256K
RAM : ORIGIN = 0x20000000, LENGTH = 40K
}
```
4. Build the template application or one of the examples.
``` console
$ cargo build
```
# License
This template is licensed under either of
- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
http://www.apache.org/licenses/LICENSE-2.0)
- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
at your option.
## Contribution
Unless you explicitly state otherwise, any contribution intentionally submitted
for inclusion in the work by you, as defined in the Apache-2.0 license, shall be
dual licensed as above, without any additional terms or conditions.
## Code of Conduct
Contribution to this crate is organized under the terms of the [Rust Code of
Conduct][CoC], the maintainer of this crate, the [Cortex-M team][team], promises
to intervene to uphold that code of conduct.
[CoC]: https://www.rust-lang.org/policies/code-of-conduct
[team]: https://github.com/rust-embedded/wg#the-cortex-m-team

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use std::env;
use std::fs::File;
use std::io::Write;
use std::path::PathBuf;
fn main() {
// Put the linker script somewhere the linker can find it
let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
File::create(out.join("memory.x"))
.unwrap()
.write_all(include_bytes!("memory.x"))
.unwrap();
println!("cargo:rustc-link-search={}", out.display());
// Only re-run the build script when memory.x is changed,
// instead of when any part of the source code changes.
println!("cargo:rerun-if-changed=memory.x");
}

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MEMORY
{
/* NOTE 1 K = 1 KiBi = 1024 bytes */
/* Code Zone - 0x00000000 to 0x1FFFFFFF */
FLASH : ORIGIN = 0x00000000, LENGTH = 256K
RAM_ALIAS : ORIGIN = 0x01000000, LENGTH = 64K
ROM : ORIGIN = 0x02000000, LENGTH = 32K
/* SRAM Region - 0x00000000 to 0x003FFFFF */
RAM : ORIGIN = 0x20000000, LENGTH = 64K
RAM_BITBAND : ORIGIN = 0x22000000, LENGTH = 1024K
}
/* This is where the call stack will be allocated. */
/* The stack is of the full descending type. */
/* You may want to use this variable to locate the call stack and static
variables in different memory regions. Below is shown the default value */
/* _stack_start = ORIGIN(RAM) + LENGTH(RAM); */
/* You can use this symbol to customize the location of the .text section */
/* If omitted the .text section will be placed right after the .vector_table
section */
/* This is required only on microcontrollers that store some configuration right
after the vector table */
/* _stext = ORIGIN(FLASH) + 0x400; */
/* Example of putting non-initialized variables into custom RAM locations. */
/* This assumes you have defined a region RAM2 above, and in the Rust
sources added the attribute `#[link_section = ".ram2bss"]` to the data
you want to place there. */
/* Note that the section will not be zero-initialized by the runtime! */
/* SECTIONS {
.ram2bss (NOLOAD) : ALIGN(4) {
*(.ram2bss);
. = ALIGN(4);
} > RAM2
} INSERT AFTER .bss;
*/

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# OpenOCD configuration for the MSP432P401R LaunchPad
source [find interface/xds110.cfg]
adapter_khz 2500
transport select swd
source [find target/ti_msp432.cfg]

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target extended-remote :3333
# print demangled symbols
set print asm-demangle on
# set backtrace limit to not have infinite backtrace loops
set backtrace limit 32
# detect unhandled exceptions, hard faults and panics
break DefaultHandler
break HardFault
break rust_begin_unwind
# *try* to stop at the user entry point (it might be gone due to inlining)
break main
monitor arm semihosting enable
# # send captured ITM to the file itm.fifo
# # (the microcontroller SWO pin must be connected to the programmer SWO pin)
# # 8000000 must match the core clock frequency
# monitor tpiu config internal itm.txt uart off 8000000
# # OR: make the microcontroller SWO pin output compatible with UART (8N1)
# # 8000000 must match the core clock frequency
# # 2000000 is the frequency of the SWO pin
# monitor tpiu config external uart off 8000000 2000000
# # enable ITM port 0
# monitor itm port 0 on
#load
# start the process but immediately halt the processor
#stepi

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//! Debugging a crash (exception)
//!
//! Most crash conditions trigger a hard fault exception, whose handler is defined via
//! `exception!(HardFault, ..)`. The `HardFault` handler has access to the exception frame, a
//! snapshot of the CPU registers at the moment of the exception.
//!
//! This program crashes and the `HardFault` handler prints to the console the contents of the
//! `ExceptionFrame` and then triggers a breakpoint. From that breakpoint one can see the backtrace
//! that led to the exception.
//!
//! ``` text
//! (gdb) continue
//! Program received signal SIGTRAP, Trace/breakpoint trap.
//! __bkpt () at asm/bkpt.s:3
//! 3 bkpt
//!
//! (gdb) backtrace
//! #0 __bkpt () at asm/bkpt.s:3
//! #1 0x080030b4 in cortex_m::asm::bkpt () at $$/cortex-m-0.5.0/src/asm.rs:19
//! #2 rust_begin_unwind (args=..., file=..., line=99, col=5) at $$/panic-semihosting-0.2.0/src/lib.rs:87
//! #3 0x08001d06 in core::panicking::panic_fmt () at libcore/panicking.rs:71
//! #4 0x080004a6 in crash::hard_fault (ef=0x20004fa0) at examples/crash.rs:99
//! #5 0x08000548 in UserHardFault (ef=0x20004fa0) at <exception macros>:10
//! #6 0x0800093a in HardFault () at asm.s:5
//! Backtrace stopped: previous frame identical to this frame (corrupt stack?)
//! ```
//!
//! In the console output one will find the state of the Program Counter (PC) register at the time
//! of the exception.
//!
//! ``` text
//! panicked at 'HardFault at ExceptionFrame {
//! r0: 0x2fffffff,
//! r1: 0x2fffffff,
//! r2: 0x080051d4,
//! r3: 0x080051d4,
//! r12: 0x20000000,
//! lr: 0x08000435,
//! pc: 0x08000ab6,
//! xpsr: 0x61000000
//! }', examples/crash.rs:106:5
//! ```
//!
//! This register contains the address of the instruction that caused the exception. In GDB one can
//! disassemble the program around this address to observe the instruction that caused the
//! exception.
//!
//! ``` text
//! (gdb) disassemble/m 0x08000ab6
//! Dump of assembler code for function core::ptr::read_volatile:
//! 451 pub unsafe fn read_volatile<T>(src: *const T) -> T {
//! 0x08000aae <+0>: sub sp, #16
//! 0x08000ab0 <+2>: mov r1, r0
//! 0x08000ab2 <+4>: str r0, [sp, #8]
//!
//! 452 intrinsics::volatile_load(src)
//! 0x08000ab4 <+6>: ldr r0, [sp, #8]
//! -> 0x08000ab6 <+8>: ldr r0, [r0, #0]
//! 0x08000ab8 <+10>: str r0, [sp, #12]
//! 0x08000aba <+12>: ldr r0, [sp, #12]
//! 0x08000abc <+14>: str r1, [sp, #4]
//! 0x08000abe <+16>: str r0, [sp, #0]
//! 0x08000ac0 <+18>: b.n 0x8000ac2 <core::ptr::read_volatile+20>
//!
//! 453 }
//! 0x08000ac2 <+20>: ldr r0, [sp, #0]
//! 0x08000ac4 <+22>: add sp, #16
//! 0x08000ac6 <+24>: bx lr
//!
//! End of assembler dump.
//! ```
//!
//! `ldr r0, [r0, #0]` caused the exception. This instruction tried to load (read) a 32-bit word
//! from the address stored in the register `r0`. Looking again at the contents of `ExceptionFrame`
//! we see that the `r0` contained the address `0x2FFF_FFFF` when this instruction was executed.
//!
//! ---
#![no_main]
#![no_std]
extern crate panic_halt;
use core::ptr;
use cortex_m_rt::entry;
#[entry]
fn main() -> ! {
unsafe {
// read an address outside of the RAM region; this causes a HardFault exception
ptr::read_volatile(0x2FFF_FFFF as *const u32);
}
loop {}
}

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//! Overriding an exception handler
//!
//! You can override an exception handler using the [`#[exception]`][1] attribute.
//!
//! [1]: https://rust-embedded.github.io/cortex-m-rt/0.6.1/cortex_m_rt_macros/fn.exception.html
//!
//! ---
#![deny(unsafe_code)]
#![no_main]
#![no_std]
extern crate panic_halt;
use cortex_m::peripheral::syst::SystClkSource;
use cortex_m::Peripherals;
use cortex_m_rt::{entry, exception};
use cortex_m_semihosting::hprint;
#[entry]
fn main() -> ! {
let p = Peripherals::take().unwrap();
let mut syst = p.SYST;
// configures the system timer to trigger a SysTick exception every second
syst.set_clock_source(SystClkSource::Core);
syst.set_reload(8_000_000); // period = 1s
syst.enable_counter();
syst.enable_interrupt();
loop {}
}
#[exception]
fn SysTick() {
hprint!(".").unwrap();
}

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//! Prints "Hello, world!" on the host console using semihosting
#![no_main]
#![no_std]
extern crate panic_halt;
use cortex_m_rt::entry;
use cortex_m_semihosting::{debug, hprintln};
#[entry]
fn main() -> ! {
hprintln!("Hello, world!").unwrap();
// exit QEMU
// NOTE do not run this on hardware; it can corrupt OpenOCD state
debug::exit(debug::EXIT_SUCCESS);
loop {}
}

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//! Sends "Hello, world!" through the ITM port 0
//!
//! ITM is much faster than semihosting. Like 4 orders of magnitude or so.
//!
//! **NOTE** Cortex-M0 chips don't support ITM.
//!
//! You'll have to connect the microcontroller's SWO pin to the SWD interface. Note that some
//! development boards don't provide this option.
//!
//! You'll need [`itmdump`] to receive the message on the host plus you'll need to uncomment two
//! `monitor` commands in the `.gdbinit` file.
//!
//! [`itmdump`]: https://docs.rs/itm/0.2.1/itm/
//!
//! ---
#![no_main]
#![no_std]
extern crate panic_halt;
use cortex_m::{iprintln, Peripherals};
use cortex_m_rt::entry;
#[entry]
fn main() -> ! {
let mut p = Peripherals::take().unwrap();
let stim = &mut p.ITM.stim[0];
iprintln!(stim, "Hello, world!");
loop {}
}

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//! Changing the panicking behavior
//!
//! The easiest way to change the panicking behavior is to use a different [panic handler crate][0].
//!
//! [0]: https://crates.io/keywords/panic-impl
#![no_main]
#![no_std]
// Pick one of these panic handlers:
// `panic!` halts execution; the panic message is ignored
extern crate panic_halt;
// Reports panic messages to the host stderr using semihosting
// NOTE to use this you need to uncomment the `panic-semihosting` dependency in Cargo.toml
// extern crate panic_semihosting;
// Logs panic messages using the ITM (Instrumentation Trace Macrocell)
// NOTE to use this you need to uncomment the `panic-itm` dependency in Cargo.toml
// extern crate panic_itm;
use cortex_m_rt::entry;
#[entry]
fn main() -> ! {
panic!("Oops")
}

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//! Conditionally compiling tests with std and our executable with no_std.
//!
//! Rust's built in unit testing framework requires the standard library,
//! but we need to build our final executable with no_std.
//! The testing framework also generates a `main` method, so we need to only use the `#[entry]`
//! annotation when building our final image.
//! For more information on why this example works, see this excellent blog post.
//! https://os.phil-opp.com/unit-testing/
//!
//! Running this example:
//!
//! Ensure there are no targets specified under `[build]` in `.cargo/config`
//! In order to make this work, we lose the convenience of having a default target that isn't the
//! host.
//!
//! cargo build --example test_on_host --target thumbv7m-none-eabi
//! cargo test --example test_on_host
#![cfg_attr(test, allow(unused_imports))]
#![cfg_attr(not(test), no_std)]
#![cfg_attr(not(test), no_main)]
// pick a panicking behavior
#[cfg(not(test))]
extern crate panic_halt; // you can put a breakpoint on `rust_begin_unwind` to catch panics
// extern crate panic_abort; // requires nightly
// extern crate panic_itm; // logs messages over ITM; requires ITM support
// extern crate panic_semihosting; // logs messages to the host stderr; requires a debugger
use cortex_m::asm;
use cortex_m_rt::entry;
#[cfg(not(test))]
#[entry]
fn main() -> ! {
asm::nop(); // To not have main optimize to abort in release mode, remove when you add code
loop {
// your code goes here
}
}
fn add(a: i32, b: i32) -> i32 {
a + b
}
#[cfg(test)]
mod test {
use super::*;
#[test]
fn foo() {
println!("tests work!");
assert!(2 == add(1,1));
}
}

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#![no_std]
#![no_main]
// pick a panicking behavior
extern crate panic_halt; // you can put a breakpoint on `rust_begin_unwind` to catch panics
// extern crate panic_abort; // requires nightly
// extern crate panic_itm; // logs messages over ITM; requires ITM support
// extern crate panic_semihosting; // logs messages to the host stderr; requires a debugger
use cortex_m::{self, peripheral::syst::SystClkSource};
use cortex_m_rt::entry;
use msp432p401r;
use core::num::Wrapping;
const PIN0: u8 = (1u8 << 0);
const PIN1: u8 = (1u8 << 1);
const PIN2: u8 = (1u8 << 2);
//const PIN3: u8 = (1u8 << 3);
const PIN4: u8 = (1u8 << 4);
//const PIN5: u8 = (1u8 << 5);
//const PIN6: u8 = (1u8 << 6);
//const PIN7: u8 = (1u8 << 7);
const WDOG_PWORD: u8 = 0x5a;
#[entry]
fn main() -> ! {
let cp = cortex_m::Peripherals::take().unwrap();
let p = msp432p401r::Peripherals::take().unwrap();
let mut syst = cp.SYST;
let wdt = p.WDT_A;
let dio = p.DIO;
// disable watchdog timer
wdt.wdtctl.write(|w| unsafe {
w.wdtpw().bits(WDOG_PWORD)
.wdthold().wdthold_1()
});
// configure the system timer to wrap around every ~1 second
syst.set_clock_source(SystClkSource::Core);
syst.set_reload(20_000);
syst.enable_counter();
// configure digital IO pins
dio.padir.modify(|_r, w| unsafe {
w.p1dir().bits(PIN0)
.p2dir().bits(PIN0 | PIN1 | PIN2)
});
// Enable pull-up on P1.4 switch
dio.paren.modify(|_r, w| unsafe { w.p1ren().bits(PIN4) });
dio.pads.modify(|_r, w| unsafe { w.p1ds().bits(PIN4) });
// Turn on LED1 on P1.0 and enable pull-up on P1.1 switch
dio.paout.write(|w| unsafe {
w.p1out().bits(PIN0 | PIN4)
.p2out().bits(0)
});
let mut count: Wrapping<u16> = Wrapping(0);
let mut input: u8;
loop {
while !syst.has_wrapped() {}
// The button pulls the input to GND
input = (dio.pain.read().p1in().bits() & PIN4) >> 4;
count += Wrapping(1);
let _led1: u8 = ((count.0 & 0x0100) >> 8) as u8;
let led2: u8 = ((count.0 & 0b0000_0111_0000_0000) >> 8) as u8;
// toggle LEDs
dio.paout.write(|w| unsafe {
w.p1out().bits(input | PIN4)
.p2out().bits(led2)
});
}
}

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sudo /home/levi/energia-1.6.10E18/hardware/tools/DSLite/DebugServer/bin/DSLite load --config /home/levi/energia-1.6.10E18/hardware/tools/DSLite/MSP_EXP432P401R.ccxml --file ~/Projects/Rust/msp432-app/target/thumbv7em-none-eabihf/debug/msp432-app

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/target
**/*.rs.bk
Cargo.lock

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[package]
name = "msp432-hal"
version = "0.1.0"
authors = ["Levi Pearson <levipearson@gmail.com>"]
categories = ["embedded", "hardware-support", "no-std"]
description = "HAL for the TI MSP432 family of microcontrollers"
keywords = ["arm", "cortex-m", "msp432", "hal"]
edition = "2018"
[dependencies]
cortex-m = "0.5"
embedded-hal = "0.2"
nb = "0.1"
msp432p401r = { path = "../msp432p401r" }
void = { version = "1.0", default-features = false }
cast = { version = "0.2", default-features = false }
[features]
rt = ["msp432p401r/rt"]

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//! Clock System
use core::cmp;
use pac::{cs, CS};
use crate::time::Hertz;
/// Extension trait that constrains the `CS` peripheral
pub trait CsExt {
/// Constrains the `CS` peripheral so that it plays nicely with other abstractions
fn constrain(self) -> Cs;
}
impl CsExt for CS {
fn constrain(self) -> Cs {
Cs {
}
}
}
/*
+--------+-----------------------+---------------+-------------------------------------+
| Clock | Default Clock Source | Default Clock | Description |
| | | Frequency | |
+========+=======================+===============+=====================================+
| MCLK | DCO | 3 MHz | Master Clock - Sources CPU and |
| | | | peripherals |
+--------+-----------------------+---------------+-------------------------------------+
| HSMCLK | DCO | 3 MHz | Subsystem Master Clock - Sources |
| | | | peripherals |
+--------+-----------------------+---------------+-------------------------------------+
| SMCLK | DCO | 3 MHz | Low-speed subsystem master clock - |
| | | | Sources peripherals |
+--------+-----------------------+---------------+-------------------------------------+
| ACLK | LFXT (or REFO if no | 32.768 kHz | Auxiliary clock - Sources |
| | crystal present) | | peripherals |
+--------+-----------------------+---------------+-------------------------------------+
| BCLK | LFXT (or REFO if no | 32.768 kHz | Low-speed backup domain clock - |
| | crystal present) | | Sources LPM peripherals |
+--------+-----------------------+---------------+-------------------------------------+
*/
pub struct Cs {
}
/// Frozen clock frequencies
///
/// This value holds the current clocks frequencies and indicates that they can
/// no longer be changed
#[derive(Clone, Copy)]
pub struct Clocks {
sysclk: Hertz,
}
impl Clocks {
/// Returns the system (core) frequency
pub fn sysclk(&self) -> Hertz {
self.sysclk
}
}

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//! Delays
use cast::u32;
use cortex_m::peripheral::syst::SystClkSource;
use cortex_m::peripheral::SYST;
use hal::blocking::delay::{DelayMs, DelayUs};
use crate::cs::Clocks;
/// System timer (SysTick) as a delay provider
pub struct Delay {
clocks: Clocks,
syst: SYST,
}
impl Delay {
/// Configure the system timer (SysTick) as a delay provider
pub fn new(mut syst: SYST, clocks: Clocks) -> Self {
syst.set_clock_source(SystClkSource::Core);
Delay { syst, clocks }
}
/// Release the system timer (SysTick) resource
pub fn free(self) -> SYST {
self.syst
}
}
impl DelayMs<u32> for Delay {
fn delay_ms(&mut self, ms: u32) {
self.delay_us(ms * 1_000);
}
}
impl DelayMs<u16> for Delay {
fn delay_ms(&mut self, ms: u16) {
self.delay_ms(u32(ms));
}
}
impl DelayMs<u8> for Delay {
fn delay_ms(&mut self, ms: u8) {
self.delay_ms(u32(ms));
}
}
impl DelayUs<u32> for Delay {
fn delay_us(&mut self, us: u32) {
let rvr = us * (self.clocks.sysclk().0 / 1_000_000);
assert!(rvr < (1 << 24));
self.syst.set_reload(rvr);
self.syst.clear_current();
self.syst.enable_counter();
while !self.syst.has_wrapped() {}
self.syst.disable_counter();
}
}
impl DelayUs<u16> for Delay {
fn delay_us(&mut self, us: u16) {
self.delay_us(u32(us));
}
}
impl DelayUs<u8> for Delay {
fn delay_us(&mut self, us: u8) {
self.delay_us(u32(us));
}
}

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//! General Purpose Input / Output
use pac::DIO;
use core::marker::PhantomData;
use hal::digital::OutputPin;
pub trait GpioExt {
type Parts;
/// Consume and split the device into its constituent parts
fn split(self) -> Self::Parts;
}
/// Represents a pin configured for input.
pub struct Input<MODE> {
_mode: PhantomData<MODE>,
}
/// Represents a pin configured for output.
pub struct Output<MODE> {
_mode: PhantomData<MODE>,
}

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//! HAL for the MSP432 family of microcontrollers
//!
//! This is an implementation of the [`embedded-hal`] traits for the MSP432 family of
//! microcontrollers.
//!
//! [`embedded-hal`]: https://github.com/japaric/embedded-hal
//!
//! # Usage
//!
//! To build applications (binary crates) using this crate follow the [cortex-m-quickstart]
//! instructions and add this crate as a dependency in step number 5 and make sure you enable the
//! "rt" Cargo feature of this crate.
//!
//! [cortex-m-quickstart]: https://docs.rs/cortex-m-quickstart/~0.3
#![warn(missing_docs)]
#![no_std]
extern crate embedded_hal as hal;
extern crate msp432p401r as pac;
pub mod prelude;
pub mod gpio;
pub mod delay;
pub mod cs;
pub mod time;

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//! Prelude
pub use hal::prelude::*;

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//! Time units
use cortex_m::peripheral::DWT;
use crate::cs::Clocks;
/// Bits per seconds
#[derive(Clone, Copy)]
pub struct Bps(pub u32);
/// Hertz
#[derive(Clone, Copy)]
pub struct Hertz(pub u32);
/// KiloHertz
#[derive(Clone, Copy)]
pub struct KiloHertz(pub u32);
/// MegaHertz
#[derive(Clone, Copy)]
pub struct MegaHertz(pub u32);
/// Extension trait to add convenience methods to `u32`
pub trait U32Ext {
/// Wrap in `Bps`
fn bps(self) -> Bps;
/// Wrap in `Hertz`
fn hz(self) -> Hertz;
/// Wrap in `KiloHertz`
fn khz(self) -> KiloHertz;
/// Wrap in `MegaHertz`
fn mhz(self) -> MegaHertz;
}
impl U32Ext for u32 {
fn bps(self) -> Bps {
Bps(self)
}
fn hz(self) -> Hertz {
Hertz(self)
}
fn khz(self) -> KiloHertz {
KiloHertz(self)
}
fn mhz(self) -> MegaHertz {
MegaHertz(self)
}
}
impl Into<Hertz> for KiloHertz {
fn into(self) -> Hertz {
Hertz(self.0 * 1_000)
}
}
impl Into<Hertz> for MegaHertz {
fn into(self) -> Hertz {
Hertz(self.0 * 1_000_000)
}
}
impl Into<KiloHertz> for MegaHertz {
fn into(self) -> KiloHertz {
KiloHertz(self.0 * 1_000)
}
}
/// A monotonic nondecreasing timer
#[derive(Clone, Copy)]
pub struct MonoTimer {
frequency: Hertz,
}
impl MonoTimer {
/// Create a new monotonic timer
pub fn new(mut dwt: DWT, clocks: Clocks) -> Self {
dwt.enable_cycle_counter();
// can't stop or reset CYCCNT
drop(dwt);
MonoTimer {
frequency: clocks.sysclk(),
}
}
/// Return the frequency at which the timer is operating
pub fn frequency(&self) -> Hertz {
self.frequency
}
/// Returns an `Instant` corresponding to "now"
pub fn now(&self) -> Instant {
Instant {
now: DWT::get_cycle_count(),
}
}
}
/// A measurement from a monotonically nondecreasing clock
#[derive(Clone, Copy)]
pub struct Instant {
now: u32,
}
impl Instant {
/// Ticks elapsed since the `Instant` was created
pub fn elapsed(&self) -> u32 {
DWT::get_cycle_count().wrapping_sub(self.now)
}
}

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example-source/msp432p401r/.gitignore vendored Normal file
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/target
**/*.rs.bk
Cargo.lock

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example-source/msp432p401r/Cargo.toml Normal file
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[package]
name = "msp432p401r"
version = "0.1.0"
authors = ["Levi Pearson <levipearson@gmail.com>"]
edition = "2018"
[dependencies]
bare-metal = "0.2.0"
cortex-m = "0.5.8"
vcell = "0.1.0"
[dependencies.cortex-m-rt]
optional = true
version = "0.6.5"
[features]
rt = ["cortex-m-rt/device"]

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use std::env;
use std::fs::File;
use std::io::Write;
use std::path::PathBuf;
fn main() {
if env::var_os("CARGO_FEATURE_RT").is_some() {
let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
File::create(out.join("device.x"))
.unwrap()
.write_all(include_bytes!("device.x"))
.unwrap();
println!("cargo:rustc-link-search={}", out.display());
println!("cargo:rerun-if-changed=device.x");
}
println!("cargo:rerun-if-changed=build.rs");
}

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PROVIDE(PSS_IRQ = DefaultHandler);
PROVIDE(CS_IRQ = DefaultHandler);
PROVIDE(PCM_IRQ = DefaultHandler);
PROVIDE(WDT_A_IRQ = DefaultHandler);
PROVIDE(FPU_IRQ = DefaultHandler);
PROVIDE(FLCTL_IRQ = DefaultHandler);
PROVIDE(COMP_E0_IRQ = DefaultHandler);
PROVIDE(COMP_E1_IRQ = DefaultHandler);
PROVIDE(TA0_0_IRQ = DefaultHandler);
PROVIDE(TA0_N_IRQ = DefaultHandler);
PROVIDE(TA1_0_IRQ = DefaultHandler);
PROVIDE(TA1_N_IRQ = DefaultHandler);
PROVIDE(TA2_0_IRQ = DefaultHandler);
PROVIDE(TA2_N_IRQ = DefaultHandler);
PROVIDE(TA3_0_IRQ = DefaultHandler);
PROVIDE(TA3_N_IRQ = DefaultHandler);
PROVIDE(EUSCIA0_IRQ = DefaultHandler);
PROVIDE(EUSCIA1_IRQ = DefaultHandler);
PROVIDE(EUSCIA2_IRQ = DefaultHandler);
PROVIDE(EUSCIA3_IRQ = DefaultHandler);
PROVIDE(EUSCIB0_IRQ = DefaultHandler);
PROVIDE(EUSCIB1_IRQ = DefaultHandler);
PROVIDE(EUSCIB2_IRQ = DefaultHandler);
PROVIDE(EUSCIB3_IRQ = DefaultHandler);
PROVIDE(ADC14_IRQ = DefaultHandler);
PROVIDE(T32_INT1_IRQ = DefaultHandler);
PROVIDE(T32_INT2_IRQ = DefaultHandler);
PROVIDE(T32_INTC_IRQ = DefaultHandler);
PROVIDE(AES256_IRQ = DefaultHandler);
PROVIDE(RTC_C_IRQ = DefaultHandler);
PROVIDE(DMA_ERR_IRQ = DefaultHandler);
PROVIDE(DMA_INT3_IRQ = DefaultHandler);
PROVIDE(DMA_INT2_IRQ = DefaultHandler);
PROVIDE(DMA_INT1_IRQ = DefaultHandler);
PROVIDE(DMA_INT0_IRQ = DefaultHandler);
PROVIDE(PORT1_IRQ = DefaultHandler);
PROVIDE(PORT2_IRQ = DefaultHandler);
PROVIDE(PORT3_IRQ = DefaultHandler);
PROVIDE(PORT4_IRQ = DefaultHandler);
PROVIDE(PORT5_IRQ = DefaultHandler);
PROVIDE(PORT6_IRQ = DefaultHandler);

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#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Control 0 Register"]
pub adc14ctl0: ADC14CTL0,
#[doc = "0x04 - Control 1 Register"]
pub adc14ctl1: ADC14CTL1,
#[doc = "0x08 - Window Comparator Low Threshold 0 Register"]
pub adc14lo0: ADC14LO0,
#[doc = "0x0c - Window Comparator High Threshold 0 Register"]
pub adc14hi0: ADC14HI0,
#[doc = "0x10 - Window Comparator Low Threshold 1 Register"]
pub adc14lo1: ADC14LO1,
#[doc = "0x14 - Window Comparator High Threshold 1 Register"]
pub adc14hi1: ADC14HI1,
#[doc = "0x18 - Conversion Memory Control Register"]
pub adc14mctl: [ADC14MCTL; 32],
#[doc = "0x98 - Conversion Memory Register"]
pub adc14mem: [ADC14MEM; 32],
_reserved0: [u8; 36usize],
#[doc = "0x13c - Interrupt Enable 0 Register"]
pub adc14ier0: ADC14IER0,
#[doc = "0x140 - Interrupt Enable 1 Register"]
pub adc14ier1: ADC14IER1,
#[doc = "0x144 - Interrupt Flag 0 Register"]
pub adc14ifgr0: ADC14IFGR0,
#[doc = "0x148 - Interrupt Flag 1 Register"]
pub adc14ifgr1: ADC14IFGR1,
#[doc = "0x14c - Clear Interrupt Flag 0 Register"]
pub adc14clrifgr0: ADC14CLRIFGR0,
#[doc = "0x150 - Clear Interrupt Flag 1 Register"]
pub adc14clrifgr1: ADC14CLRIFGR1,
#[doc = "0x154 - Interrupt Vector Register"]
pub adc14iv: ADC14IV,
}
#[doc = "Control 0 Register"]
pub struct ADC14CTL0 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Control 0 Register"]
pub mod adc14ctl0;
#[doc = "Control 1 Register"]
pub struct ADC14CTL1 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Control 1 Register"]
pub mod adc14ctl1;
#[doc = "Window Comparator Low Threshold 0 Register"]
pub struct ADC14LO0 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Window Comparator Low Threshold 0 Register"]
pub mod adc14lo0;
#[doc = "Window Comparator High Threshold 0 Register"]
pub struct ADC14HI0 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Window Comparator High Threshold 0 Register"]
pub mod adc14hi0;
#[doc = "Window Comparator Low Threshold 1 Register"]
pub struct ADC14LO1 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Window Comparator Low Threshold 1 Register"]
pub mod adc14lo1;
#[doc = "Window Comparator High Threshold 1 Register"]
pub struct ADC14HI1 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Window Comparator High Threshold 1 Register"]
pub mod adc14hi1;
#[doc = "Conversion Memory Control Register"]
pub struct ADC14MCTL {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Conversion Memory Control Register"]
pub mod adc14mctl;
#[doc = "Conversion Memory Register"]
pub struct ADC14MEM {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Conversion Memory Register"]
pub mod adc14mem;
#[doc = "Interrupt Enable 0 Register"]
pub struct ADC14IER0 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt Enable 0 Register"]
pub mod adc14ier0;
#[doc = "Interrupt Enable 1 Register"]
pub struct ADC14IER1 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt Enable 1 Register"]
pub mod adc14ier1;
#[doc = "Interrupt Flag 0 Register"]
pub struct ADC14IFGR0 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt Flag 0 Register"]
pub mod adc14ifgr0;
#[doc = "Interrupt Flag 1 Register"]
pub struct ADC14IFGR1 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt Flag 1 Register"]
pub mod adc14ifgr1;
#[doc = "Clear Interrupt Flag 0 Register"]
pub struct ADC14CLRIFGR0 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Clear Interrupt Flag 0 Register"]
pub mod adc14clrifgr0;
#[doc = "Clear Interrupt Flag 1 Register"]
pub struct ADC14CLRIFGR1 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Clear Interrupt Flag 1 Register"]
pub mod adc14clrifgr1;
#[doc = "Interrupt Vector Register"]
pub struct ADC14IV {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt Vector Register"]
pub mod adc14iv;

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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::ADC14CLRIFGR1 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Values that can be written to the field `CLRADC14INIFG`"]
pub enum CLRADC14INIFGW {
#[doc = "no effect"]
CLRADC14INIFG_0,
#[doc = "clear pending interrupt flag"]
CLRADC14INIFG_1,
}
impl CLRADC14INIFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CLRADC14INIFGW::CLRADC14INIFG_0 => false,
CLRADC14INIFGW::CLRADC14INIFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CLRADC14INIFGW<'a> {
w: &'a mut W,
}
impl<'a> _CLRADC14INIFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CLRADC14INIFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "no effect"]
#[inline]
pub fn clradc14inifg_0(self) -> &'a mut W {
self.variant(CLRADC14INIFGW::CLRADC14INIFG_0)
}
#[doc = "clear pending interrupt flag"]
#[inline]
pub fn clradc14inifg_1(self) -> &'a mut W {
self.variant(CLRADC14INIFGW::CLRADC14INIFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CLRADC14LOIFG`"]
pub enum CLRADC14LOIFGW {
#[doc = "no effect"]
CLRADC14LOIFG_0,
#[doc = "clear pending interrupt flag"]
CLRADC14LOIFG_1,
}
impl CLRADC14LOIFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CLRADC14LOIFGW::CLRADC14LOIFG_0 => false,
CLRADC14LOIFGW::CLRADC14LOIFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CLRADC14LOIFGW<'a> {
w: &'a mut W,
}
impl<'a> _CLRADC14LOIFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CLRADC14LOIFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "no effect"]
#[inline]
pub fn clradc14loifg_0(self) -> &'a mut W {
self.variant(CLRADC14LOIFGW::CLRADC14LOIFG_0)
}
#[doc = "clear pending interrupt flag"]
#[inline]
pub fn clradc14loifg_1(self) -> &'a mut W {
self.variant(CLRADC14LOIFGW::CLRADC14LOIFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CLRADC14HIIFG`"]
pub enum CLRADC14HIIFGW {
#[doc = "no effect"]
CLRADC14HIIFG_0,
#[doc = "clear pending interrupt flag"]
CLRADC14HIIFG_1,
}
impl CLRADC14HIIFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CLRADC14HIIFGW::CLRADC14HIIFG_0 => false,
CLRADC14HIIFGW::CLRADC14HIIFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CLRADC14HIIFGW<'a> {
w: &'a mut W,
}
impl<'a> _CLRADC14HIIFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CLRADC14HIIFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "no effect"]
#[inline]
pub fn clradc14hiifg_0(self) -> &'a mut W {
self.variant(CLRADC14HIIFGW::CLRADC14HIIFG_0)
}
#[doc = "clear pending interrupt flag"]
#[inline]
pub fn clradc14hiifg_1(self) -> &'a mut W {
self.variant(CLRADC14HIIFGW::CLRADC14HIIFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CLRADC14OVIFG`"]
pub enum CLRADC14OVIFGW {
#[doc = "no effect"]
CLRADC14OVIFG_0,
#[doc = "clear pending interrupt flag"]
CLRADC14OVIFG_1,
}
impl CLRADC14OVIFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CLRADC14OVIFGW::CLRADC14OVIFG_0 => false,
CLRADC14OVIFGW::CLRADC14OVIFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CLRADC14OVIFGW<'a> {
w: &'a mut W,
}
impl<'a> _CLRADC14OVIFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CLRADC14OVIFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "no effect"]
#[inline]
pub fn clradc14ovifg_0(self) -> &'a mut W {
self.variant(CLRADC14OVIFGW::CLRADC14OVIFG_0)
}
#[doc = "clear pending interrupt flag"]
#[inline]
pub fn clradc14ovifg_1(self) -> &'a mut W {
self.variant(CLRADC14OVIFGW::CLRADC14OVIFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CLRADC14TOVIFG`"]
pub enum CLRADC14TOVIFGW {
#[doc = "no effect"]
CLRADC14TOVIFG_0,
#[doc = "clear pending interrupt flag"]
CLRADC14TOVIFG_1,
}
impl CLRADC14TOVIFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CLRADC14TOVIFGW::CLRADC14TOVIFG_0 => false,
CLRADC14TOVIFGW::CLRADC14TOVIFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CLRADC14TOVIFGW<'a> {
w: &'a mut W,
}
impl<'a> _CLRADC14TOVIFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CLRADC14TOVIFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "no effect"]
#[inline]
pub fn clradc14tovifg_0(self) -> &'a mut W {
self.variant(CLRADC14TOVIFGW::CLRADC14TOVIFG_0)
}
#[doc = "clear pending interrupt flag"]
#[inline]
pub fn clradc14tovifg_1(self) -> &'a mut W {
self.variant(CLRADC14TOVIFGW::CLRADC14TOVIFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CLRADC14RDYIFG`"]
pub enum CLRADC14RDYIFGW {
#[doc = "no effect"]
CLRADC14RDYIFG_0,
#[doc = "clear pending interrupt flag"]
CLRADC14RDYIFG_1,
}
impl CLRADC14RDYIFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CLRADC14RDYIFGW::CLRADC14RDYIFG_0 => false,
CLRADC14RDYIFGW::CLRADC14RDYIFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CLRADC14RDYIFGW<'a> {
w: &'a mut W,
}
impl<'a> _CLRADC14RDYIFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CLRADC14RDYIFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "no effect"]
#[inline]
pub fn clradc14rdyifg_0(self) -> &'a mut W {
self.variant(CLRADC14RDYIFGW::CLRADC14RDYIFG_0)
}
#[doc = "clear pending interrupt flag"]
#[inline]
pub fn clradc14rdyifg_1(self) -> &'a mut W {
self.variant(CLRADC14RDYIFGW::CLRADC14RDYIFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 1 - clear ADC14INIFG"]
#[inline]
pub fn clradc14inifg(&mut self) -> _CLRADC14INIFGW {
_CLRADC14INIFGW { w: self }
}
#[doc = "Bit 2 - clear ADC14LOIFG"]
#[inline]
pub fn clradc14loifg(&mut self) -> _CLRADC14LOIFGW {
_CLRADC14LOIFGW { w: self }
}
#[doc = "Bit 3 - clear ADC14HIIFG"]
#[inline]
pub fn clradc14hiifg(&mut self) -> _CLRADC14HIIFGW {
_CLRADC14HIIFGW { w: self }
}
#[doc = "Bit 4 - clear ADC14OVIFG"]
#[inline]
pub fn clradc14ovifg(&mut self) -> _CLRADC14OVIFGW {
_CLRADC14OVIFGW { w: self }
}
#[doc = "Bit 5 - clear ADC14TOVIFG"]
#[inline]
pub fn clradc14tovifg(&mut self) -> _CLRADC14TOVIFGW {
_CLRADC14TOVIFGW { w: self }
}
#[doc = "Bit 6 - clear ADC14RDYIFG"]
#[inline]
pub fn clradc14rdyifg(&mut self) -> _CLRADC14RDYIFGW {
_CLRADC14RDYIFGW { w: self }
}
}

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example-source/msp432p401r/src/adc14/adc14ctl1.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::ADC14HI0 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct ADC14HI0R {
bits: u16,
}
impl ADC14HI0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _ADC14HI0W<'a> {
w: &'a mut W,
}
impl<'a> _ADC14HI0W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - High threshold 0"]
#[inline]
pub fn adc14hi0(&self) -> ADC14HI0R {
let bits = {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
ADC14HI0R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 16383 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - High threshold 0"]
#[inline]
pub fn adc14hi0(&mut self) -> _ADC14HI0W {
_ADC14HI0W { w: self }
}
}

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example-source/msp432p401r/src/adc14/adc14hi1.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::ADC14HI1 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct ADC14HI1R {
bits: u16,
}
impl ADC14HI1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _ADC14HI1W<'a> {
w: &'a mut W,
}
impl<'a> _ADC14HI1W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - High threshold 1"]
#[inline]
pub fn adc14hi1(&self) -> ADC14HI1R {
let bits = {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
ADC14HI1R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 16383 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - High threshold 1"]
#[inline]
pub fn adc14hi1(&mut self) -> _ADC14HI1W {
_ADC14HI1W { w: self }
}
}

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example-source/msp432p401r/src/adc14/adc14ier1.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::ADC14IER1 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `ADC14INIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC14INIER {
#[doc = "Interrupt disabled"]
ADC14INIE_0,
#[doc = "Interrupt enabled"]
ADC14INIE_1,
}
impl ADC14INIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ADC14INIER::ADC14INIE_0 => false,
ADC14INIER::ADC14INIE_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ADC14INIER {
match value {
false => ADC14INIER::ADC14INIE_0,
true => ADC14INIER::ADC14INIE_1,
}
}
#[doc = "Checks if the value of the field is `ADC14INIE_0`"]
#[inline]
pub fn is_adc14inie_0(&self) -> bool {
*self == ADC14INIER::ADC14INIE_0
}
#[doc = "Checks if the value of the field is `ADC14INIE_1`"]
#[inline]
pub fn is_adc14inie_1(&self) -> bool {
*self == ADC14INIER::ADC14INIE_1
}
}
#[doc = "Possible values of the field `ADC14LOIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC14LOIER {
#[doc = "Interrupt disabled"]
ADC14LOIE_0,
#[doc = "Interrupt enabled"]
ADC14LOIE_1,
}
impl ADC14LOIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ADC14LOIER::ADC14LOIE_0 => false,
ADC14LOIER::ADC14LOIE_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ADC14LOIER {
match value {
false => ADC14LOIER::ADC14LOIE_0,
true => ADC14LOIER::ADC14LOIE_1,
}
}
#[doc = "Checks if the value of the field is `ADC14LOIE_0`"]
#[inline]
pub fn is_adc14loie_0(&self) -> bool {
*self == ADC14LOIER::ADC14LOIE_0
}
#[doc = "Checks if the value of the field is `ADC14LOIE_1`"]
#[inline]
pub fn is_adc14loie_1(&self) -> bool {
*self == ADC14LOIER::ADC14LOIE_1
}
}
#[doc = "Possible values of the field `ADC14HIIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC14HIIER {
#[doc = "Interrupt disabled"]
ADC14HIIE_0,
#[doc = "Interrupt enabled"]
ADC14HIIE_1,
}
impl ADC14HIIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ADC14HIIER::ADC14HIIE_0 => false,
ADC14HIIER::ADC14HIIE_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ADC14HIIER {
match value {
false => ADC14HIIER::ADC14HIIE_0,
true => ADC14HIIER::ADC14HIIE_1,
}
}
#[doc = "Checks if the value of the field is `ADC14HIIE_0`"]
#[inline]
pub fn is_adc14hiie_0(&self) -> bool {
*self == ADC14HIIER::ADC14HIIE_0
}
#[doc = "Checks if the value of the field is `ADC14HIIE_1`"]
#[inline]
pub fn is_adc14hiie_1(&self) -> bool {
*self == ADC14HIIER::ADC14HIIE_1
}
}
#[doc = "Possible values of the field `ADC14OVIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC14OVIER {
#[doc = "Interrupt disabled"]
ADC14OVIE_0,
#[doc = "Interrupt enabled"]
ADC14OVIE_1,
}
impl ADC14OVIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ADC14OVIER::ADC14OVIE_0 => false,
ADC14OVIER::ADC14OVIE_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ADC14OVIER {
match value {
false => ADC14OVIER::ADC14OVIE_0,
true => ADC14OVIER::ADC14OVIE_1,
}
}
#[doc = "Checks if the value of the field is `ADC14OVIE_0`"]
#[inline]
pub fn is_adc14ovie_0(&self) -> bool {
*self == ADC14OVIER::ADC14OVIE_0
}
#[doc = "Checks if the value of the field is `ADC14OVIE_1`"]
#[inline]
pub fn is_adc14ovie_1(&self) -> bool {
*self == ADC14OVIER::ADC14OVIE_1
}
}
#[doc = "Possible values of the field `ADC14TOVIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC14TOVIER {
#[doc = "Interrupt disabled"]
ADC14TOVIE_0,
#[doc = "Interrupt enabled"]
ADC14TOVIE_1,
}
impl ADC14TOVIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ADC14TOVIER::ADC14TOVIE_0 => false,
ADC14TOVIER::ADC14TOVIE_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ADC14TOVIER {
match value {
false => ADC14TOVIER::ADC14TOVIE_0,
true => ADC14TOVIER::ADC14TOVIE_1,
}
}
#[doc = "Checks if the value of the field is `ADC14TOVIE_0`"]
#[inline]
pub fn is_adc14tovie_0(&self) -> bool {
*self == ADC14TOVIER::ADC14TOVIE_0
}
#[doc = "Checks if the value of the field is `ADC14TOVIE_1`"]
#[inline]
pub fn is_adc14tovie_1(&self) -> bool {
*self == ADC14TOVIER::ADC14TOVIE_1
}
}
#[doc = "Possible values of the field `ADC14RDYIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC14RDYIER {
#[doc = "Interrupt disabled"]
ADC14RDYIE_0,
#[doc = "Interrupt enabled"]
ADC14RDYIE_1,
}
impl ADC14RDYIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ADC14RDYIER::ADC14RDYIE_0 => false,
ADC14RDYIER::ADC14RDYIE_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ADC14RDYIER {
match value {
false => ADC14RDYIER::ADC14RDYIE_0,
true => ADC14RDYIER::ADC14RDYIE_1,
}
}
#[doc = "Checks if the value of the field is `ADC14RDYIE_0`"]
#[inline]
pub fn is_adc14rdyie_0(&self) -> bool {
*self == ADC14RDYIER::ADC14RDYIE_0
}
#[doc = "Checks if the value of the field is `ADC14RDYIE_1`"]
#[inline]
pub fn is_adc14rdyie_1(&self) -> bool {
*self == ADC14RDYIER::ADC14RDYIE_1
}
}
#[doc = "Values that can be written to the field `ADC14INIE`"]
pub enum ADC14INIEW {
#[doc = "Interrupt disabled"]
ADC14INIE_0,
#[doc = "Interrupt enabled"]
ADC14INIE_1,
}
impl ADC14INIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ADC14INIEW::ADC14INIE_0 => false,
ADC14INIEW::ADC14INIE_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ADC14INIEW<'a> {
w: &'a mut W,
}
impl<'a> _ADC14INIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADC14INIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Interrupt disabled"]
#[inline]
pub fn adc14inie_0(self) -> &'a mut W {
self.variant(ADC14INIEW::ADC14INIE_0)
}
#[doc = "Interrupt enabled"]
#[inline]
pub fn adc14inie_1(self) -> &'a mut W {
self.variant(ADC14INIEW::ADC14INIE_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ADC14LOIE`"]
pub enum ADC14LOIEW {
#[doc = "Interrupt disabled"]
ADC14LOIE_0,
#[doc = "Interrupt enabled"]
ADC14LOIE_1,
}
impl ADC14LOIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ADC14LOIEW::ADC14LOIE_0 => false,
ADC14LOIEW::ADC14LOIE_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ADC14LOIEW<'a> {
w: &'a mut W,
}
impl<'a> _ADC14LOIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADC14LOIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Interrupt disabled"]
#[inline]
pub fn adc14loie_0(self) -> &'a mut W {
self.variant(ADC14LOIEW::ADC14LOIE_0)
}
#[doc = "Interrupt enabled"]
#[inline]
pub fn adc14loie_1(self) -> &'a mut W {
self.variant(ADC14LOIEW::ADC14LOIE_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ADC14HIIE`"]
pub enum ADC14HIIEW {
#[doc = "Interrupt disabled"]
ADC14HIIE_0,
#[doc = "Interrupt enabled"]
ADC14HIIE_1,
}
impl ADC14HIIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ADC14HIIEW::ADC14HIIE_0 => false,
ADC14HIIEW::ADC14HIIE_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ADC14HIIEW<'a> {
w: &'a mut W,
}
impl<'a> _ADC14HIIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADC14HIIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Interrupt disabled"]
#[inline]
pub fn adc14hiie_0(self) -> &'a mut W {
self.variant(ADC14HIIEW::ADC14HIIE_0)
}
#[doc = "Interrupt enabled"]
#[inline]
pub fn adc14hiie_1(self) -> &'a mut W {
self.variant(ADC14HIIEW::ADC14HIIE_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ADC14OVIE`"]
pub enum ADC14OVIEW {
#[doc = "Interrupt disabled"]
ADC14OVIE_0,
#[doc = "Interrupt enabled"]
ADC14OVIE_1,
}
impl ADC14OVIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ADC14OVIEW::ADC14OVIE_0 => false,
ADC14OVIEW::ADC14OVIE_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ADC14OVIEW<'a> {
w: &'a mut W,
}
impl<'a> _ADC14OVIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADC14OVIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Interrupt disabled"]
#[inline]
pub fn adc14ovie_0(self) -> &'a mut W {
self.variant(ADC14OVIEW::ADC14OVIE_0)
}
#[doc = "Interrupt enabled"]
#[inline]
pub fn adc14ovie_1(self) -> &'a mut W {
self.variant(ADC14OVIEW::ADC14OVIE_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ADC14TOVIE`"]
pub enum ADC14TOVIEW {
#[doc = "Interrupt disabled"]
ADC14TOVIE_0,
#[doc = "Interrupt enabled"]
ADC14TOVIE_1,
}
impl ADC14TOVIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ADC14TOVIEW::ADC14TOVIE_0 => false,
ADC14TOVIEW::ADC14TOVIE_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ADC14TOVIEW<'a> {
w: &'a mut W,
}
impl<'a> _ADC14TOVIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADC14TOVIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Interrupt disabled"]
#[inline]
pub fn adc14tovie_0(self) -> &'a mut W {
self.variant(ADC14TOVIEW::ADC14TOVIE_0)
}
#[doc = "Interrupt enabled"]
#[inline]
pub fn adc14tovie_1(self) -> &'a mut W {
self.variant(ADC14TOVIEW::ADC14TOVIE_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ADC14RDYIE`"]
pub enum ADC14RDYIEW {
#[doc = "Interrupt disabled"]
ADC14RDYIE_0,
#[doc = "Interrupt enabled"]
ADC14RDYIE_1,
}
impl ADC14RDYIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ADC14RDYIEW::ADC14RDYIE_0 => false,
ADC14RDYIEW::ADC14RDYIE_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ADC14RDYIEW<'a> {
w: &'a mut W,
}
impl<'a> _ADC14RDYIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADC14RDYIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Interrupt disabled"]
#[inline]
pub fn adc14rdyie_0(self) -> &'a mut W {
self.variant(ADC14RDYIEW::ADC14RDYIE_0)
}
#[doc = "Interrupt enabled"]
#[inline]
pub fn adc14rdyie_1(self) -> &'a mut W {
self.variant(ADC14RDYIEW::ADC14RDYIE_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 1 - Interrupt enable for ADC14MEMx within comparator window"]
#[inline]
pub fn adc14inie(&self) -> ADC14INIER {
ADC14INIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Interrupt enable for ADC14MEMx below comparator window"]
#[inline]
pub fn adc14loie(&self) -> ADC14LOIER {
ADC14LOIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Interrupt enable for ADC14MEMx above comparator window"]
#[inline]
pub fn adc14hiie(&self) -> ADC14HIIER {
ADC14HIIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - ADC14MEMx overflow-interrupt enable"]
#[inline]
pub fn adc14ovie(&self) -> ADC14OVIER {
ADC14OVIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 5 - ADC14 conversion-time-overflow interrupt enable"]
#[inline]
pub fn adc14tovie(&self) -> ADC14TOVIER {
ADC14TOVIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 6 - ADC14 local buffered reference ready interrupt enable"]
#[inline]
pub fn adc14rdyie(&self) -> ADC14RDYIER {
ADC14RDYIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 1 - Interrupt enable for ADC14MEMx within comparator window"]
#[inline]
pub fn adc14inie(&mut self) -> _ADC14INIEW {
_ADC14INIEW { w: self }
}
#[doc = "Bit 2 - Interrupt enable for ADC14MEMx below comparator window"]
#[inline]
pub fn adc14loie(&mut self) -> _ADC14LOIEW {
_ADC14LOIEW { w: self }
}
#[doc = "Bit 3 - Interrupt enable for ADC14MEMx above comparator window"]
#[inline]
pub fn adc14hiie(&mut self) -> _ADC14HIIEW {
_ADC14HIIEW { w: self }
}
#[doc = "Bit 4 - ADC14MEMx overflow-interrupt enable"]
#[inline]
pub fn adc14ovie(&mut self) -> _ADC14OVIEW {
_ADC14OVIEW { w: self }
}
#[doc = "Bit 5 - ADC14 conversion-time-overflow interrupt enable"]
#[inline]
pub fn adc14tovie(&mut self) -> _ADC14TOVIEW {
_ADC14TOVIEW { w: self }
}
#[doc = "Bit 6 - ADC14 local buffered reference ready interrupt enable"]
#[inline]
pub fn adc14rdyie(&mut self) -> _ADC14RDYIEW {
_ADC14RDYIEW { w: self }
}
}

1812
example-source/msp432p401r/src/adc14/adc14ifgr0.rs Normal file
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356
example-source/msp432p401r/src/adc14/adc14ifgr1.rs Normal file
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@@ -0,0 +1,356 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::ADC14IFGR1 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = "Possible values of the field `ADC14INIFG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC14INIFGR {
#[doc = "No interrupt pending"]
ADC14INIFG_0,
#[doc = "Interrupt pending"]
ADC14INIFG_1,
}
impl ADC14INIFGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ADC14INIFGR::ADC14INIFG_0 => false,
ADC14INIFGR::ADC14INIFG_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ADC14INIFGR {
match value {
false => ADC14INIFGR::ADC14INIFG_0,
true => ADC14INIFGR::ADC14INIFG_1,
}
}
#[doc = "Checks if the value of the field is `ADC14INIFG_0`"]
#[inline]
pub fn is_adc14inifg_0(&self) -> bool {
*self == ADC14INIFGR::ADC14INIFG_0
}
#[doc = "Checks if the value of the field is `ADC14INIFG_1`"]
#[inline]
pub fn is_adc14inifg_1(&self) -> bool {
*self == ADC14INIFGR::ADC14INIFG_1
}
}
#[doc = "Possible values of the field `ADC14LOIFG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC14LOIFGR {
#[doc = "No interrupt pending"]
ADC14LOIFG_0,
#[doc = "Interrupt pending"]
ADC14LOIFG_1,
}
impl ADC14LOIFGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ADC14LOIFGR::ADC14LOIFG_0 => false,
ADC14LOIFGR::ADC14LOIFG_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ADC14LOIFGR {
match value {
false => ADC14LOIFGR::ADC14LOIFG_0,
true => ADC14LOIFGR::ADC14LOIFG_1,
}
}
#[doc = "Checks if the value of the field is `ADC14LOIFG_0`"]
#[inline]
pub fn is_adc14loifg_0(&self) -> bool {
*self == ADC14LOIFGR::ADC14LOIFG_0
}
#[doc = "Checks if the value of the field is `ADC14LOIFG_1`"]
#[inline]
pub fn is_adc14loifg_1(&self) -> bool {
*self == ADC14LOIFGR::ADC14LOIFG_1
}
}
#[doc = "Possible values of the field `ADC14HIIFG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC14HIIFGR {
#[doc = "No interrupt pending"]
ADC14HIIFG_0,
#[doc = "Interrupt pending"]
ADC14HIIFG_1,
}
impl ADC14HIIFGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ADC14HIIFGR::ADC14HIIFG_0 => false,
ADC14HIIFGR::ADC14HIIFG_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ADC14HIIFGR {
match value {
false => ADC14HIIFGR::ADC14HIIFG_0,
true => ADC14HIIFGR::ADC14HIIFG_1,
}
}
#[doc = "Checks if the value of the field is `ADC14HIIFG_0`"]
#[inline]
pub fn is_adc14hiifg_0(&self) -> bool {
*self == ADC14HIIFGR::ADC14HIIFG_0
}
#[doc = "Checks if the value of the field is `ADC14HIIFG_1`"]
#[inline]
pub fn is_adc14hiifg_1(&self) -> bool {
*self == ADC14HIIFGR::ADC14HIIFG_1
}
}
#[doc = "Possible values of the field `ADC14OVIFG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC14OVIFGR {
#[doc = "No interrupt pending"]
ADC14OVIFG_0,
#[doc = "Interrupt pending"]
ADC14OVIFG_1,
}
impl ADC14OVIFGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ADC14OVIFGR::ADC14OVIFG_0 => false,
ADC14OVIFGR::ADC14OVIFG_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ADC14OVIFGR {
match value {
false => ADC14OVIFGR::ADC14OVIFG_0,
true => ADC14OVIFGR::ADC14OVIFG_1,
}
}
#[doc = "Checks if the value of the field is `ADC14OVIFG_0`"]
#[inline]
pub fn is_adc14ovifg_0(&self) -> bool {
*self == ADC14OVIFGR::ADC14OVIFG_0
}
#[doc = "Checks if the value of the field is `ADC14OVIFG_1`"]
#[inline]
pub fn is_adc14ovifg_1(&self) -> bool {
*self == ADC14OVIFGR::ADC14OVIFG_1
}
}
#[doc = "Possible values of the field `ADC14TOVIFG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC14TOVIFGR {
#[doc = "No interrupt pending"]
ADC14TOVIFG_0,
#[doc = "Interrupt pending"]
ADC14TOVIFG_1,
}
impl ADC14TOVIFGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ADC14TOVIFGR::ADC14TOVIFG_0 => false,
ADC14TOVIFGR::ADC14TOVIFG_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ADC14TOVIFGR {
match value {
false => ADC14TOVIFGR::ADC14TOVIFG_0,
true => ADC14TOVIFGR::ADC14TOVIFG_1,
}
}
#[doc = "Checks if the value of the field is `ADC14TOVIFG_0`"]
#[inline]
pub fn is_adc14tovifg_0(&self) -> bool {
*self == ADC14TOVIFGR::ADC14TOVIFG_0
}
#[doc = "Checks if the value of the field is `ADC14TOVIFG_1`"]
#[inline]
pub fn is_adc14tovifg_1(&self) -> bool {
*self == ADC14TOVIFGR::ADC14TOVIFG_1
}
}
#[doc = "Possible values of the field `ADC14RDYIFG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC14RDYIFGR {
#[doc = "No interrupt pending"]
ADC14RDYIFG_0,
#[doc = "Interrupt pending"]
ADC14RDYIFG_1,
}
impl ADC14RDYIFGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ADC14RDYIFGR::ADC14RDYIFG_0 => false,
ADC14RDYIFGR::ADC14RDYIFG_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ADC14RDYIFGR {
match value {
false => ADC14RDYIFGR::ADC14RDYIFG_0,
true => ADC14RDYIFGR::ADC14RDYIFG_1,
}
}
#[doc = "Checks if the value of the field is `ADC14RDYIFG_0`"]
#[inline]
pub fn is_adc14rdyifg_0(&self) -> bool {
*self == ADC14RDYIFGR::ADC14RDYIFG_0
}
#[doc = "Checks if the value of the field is `ADC14RDYIFG_1`"]
#[inline]
pub fn is_adc14rdyifg_1(&self) -> bool {
*self == ADC14RDYIFGR::ADC14RDYIFG_1
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 1 - Interrupt flag for ADC14MEMx within comparator window"]
#[inline]
pub fn adc14inifg(&self) -> ADC14INIFGR {
ADC14INIFGR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Interrupt flag for ADC14MEMx below comparator window"]
#[inline]
pub fn adc14loifg(&self) -> ADC14LOIFGR {
ADC14LOIFGR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Interrupt flag for ADC14MEMx above comparator window"]
#[inline]
pub fn adc14hiifg(&self) -> ADC14HIIFGR {
ADC14HIIFGR::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - ADC14MEMx overflow interrupt flag"]
#[inline]
pub fn adc14ovifg(&self) -> ADC14OVIFGR {
ADC14OVIFGR::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 5 - ADC14 conversion time overflow interrupt flag"]
#[inline]
pub fn adc14tovifg(&self) -> ADC14TOVIFGR {
ADC14TOVIFGR::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 6 - ADC14 local buffered reference ready interrupt flag"]
#[inline]
pub fn adc14rdyifg(&self) -> ADC14RDYIFGR {
ADC14RDYIFGR::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}

796
example-source/msp432p401r/src/adc14/adc14iv.rs Normal file
View File

@@ -0,0 +1,796 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::ADC14IV {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `ADC14IV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC14IVR {
#[doc = "No interrupt pending"]
ADC14IV_0,
#[doc = "Interrupt Source: ADC14MEMx overflow; Interrupt Flag: ADC14OVIFG; Interrupt Priority: Highest"]
ADC14IV_2,
#[doc = "Interrupt Source: Conversion time overflow; Interrupt Flag: ADC14TOVIFG"]
ADC14IV_4,
#[doc = "Interrupt Source: ADC14 window high interrupt flag; Interrupt Flag: ADC14HIIFG"]
ADC14IV_6,
#[doc = "Interrupt Source: ADC14 window low interrupt flag; Interrupt Flag: ADC14LOIFG"]
ADC14IV_8,
#[doc = "Interrupt Source: ADC14 in-window interrupt flag; Interrupt Flag: ADC14INIFG"]
ADC14IV_10,
#[doc = "Interrupt Source: ADC14MEM0 interrupt flag; Interrupt Flag: ADC14IFG0"]
ADC14IV_12,
#[doc = "Interrupt Source: ADC14MEM1 interrupt flag; Interrupt Flag: ADC14IFG1"]
ADC14IV_14,
#[doc = "Interrupt Source: ADC14MEM2 interrupt flag; Interrupt Flag: ADC14IFG2"]
ADC14IV_16,
#[doc = "Interrupt Source: ADC14MEM3 interrupt flag; Interrupt Flag: ADC14IFG3"]
ADC14IV_18,
#[doc = "Interrupt Source: ADC14MEM4 interrupt flag; Interrupt Flag: ADC14IFG4"]
ADC14IV_20,
#[doc = "Interrupt Source: ADC14MEM5 interrupt flag; Interrupt Flag: ADC14IFG5"]
ADC14IV_22,
#[doc = "Interrupt Source: ADC14MEM6 interrupt flag; Interrupt Flag: ADC14IFG6"]
ADC14IV_24,
#[doc = "Interrupt Source: ADC14MEM7 interrupt flag; Interrupt Flag: ADC14IFG7"]
ADC14IV_26,
#[doc = "Interrupt Source: ADC14MEM8 interrupt flag; Interrupt Flag: ADC14IFG8"]
ADC14IV_28,
#[doc = "Interrupt Source: ADC14MEM9 interrupt flag; Interrupt Flag: ADC14IFG9"]
ADC14IV_30,
#[doc = "Interrupt Source: ADC14MEM10 interrupt flag; Interrupt Flag: ADC14IFG10"]
ADC14IV_32,
#[doc = "Interrupt Source: ADC14MEM11 interrupt flag; Interrupt Flag: ADC14IFG11"]
ADC14IV_34,
#[doc = "Interrupt Source: ADC14MEM12 interrupt flag; Interrupt Flag: ADC14IFG12"]
ADC14IV_36,
#[doc = "Interrupt Source: ADC14MEM13 interrupt flag; Interrupt Flag: ADC14IFG13"]
ADC14IV_38,
#[doc = "Interrupt Source: ADC14MEM14 interrupt flag; Interrupt Flag: ADC14IFG14"]
ADC14IV_40,
#[doc = "Interrupt Source: ADC14MEM15 interrupt flag; Interrupt Flag: ADC14IFG15"]
ADC14IV_42,
#[doc = "Interrupt Source: ADC14MEM16 interrupt flag; Interrupt Flag: ADC14IFG16"]
ADC14IV_44,
#[doc = "Interrupt Source: ADC14MEM17 interrupt flag; Interrupt Flag: ADC14IFG17"]
ADC14IV_46,
#[doc = "Interrupt Source: ADC14MEM18 interrupt flag; Interrupt Flag: ADC14IFG18"]
ADC14IV_48,
#[doc = "Interrupt Source: ADC14MEM19 interrupt flag; Interrupt Flag: ADC14IFG19"]
ADC14IV_50,
#[doc = "Interrupt Source: ADC14MEM20 interrupt flag; Interrupt Flag: ADC14IFG20"]
ADC14IV_52,
#[doc = "Interrupt Source: ADC14MEM22 interrupt flag; Interrupt Flag: ADC14IFG22"]
ADC14IV_54,
#[doc = "Interrupt Source: ADC14MEM22 interrupt flag; Interrupt Flag: ADC14IFG22"]
ADC14IV_56,
#[doc = "Interrupt Source: ADC14MEM23 interrupt flag; Interrupt Flag: ADC14IFG23"]
ADC14IV_58,
#[doc = "Interrupt Source: ADC14MEM24 interrupt flag; Interrupt Flag: ADC14IFG24"]
ADC14IV_60,
#[doc = "Interrupt Source: ADC14MEM25 interrupt flag; Interrupt Flag: ADC14IFG25"]
ADC14IV_62,
#[doc = "Interrupt Source: ADC14MEM26 interrupt flag; Interrupt Flag: ADC14IFG26"]
ADC14IV_64,
#[doc = "Interrupt Source: ADC14MEM27 interrupt flag; Interrupt Flag: ADC14IFG27"]
ADC14IV_66,
#[doc = "Interrupt Source: ADC14MEM28 interrupt flag; Interrupt Flag: ADC14IFG28"]
ADC14IV_68,
#[doc = "Interrupt Source: ADC14MEM29 interrupt flag; Interrupt Flag: ADC14IFG29"]
ADC14IV_70,
#[doc = "Interrupt Source: ADC14MEM30 interrupt flag; Interrupt Flag: ADC14IFG30"]
ADC14IV_72,
#[doc = "Interrupt Source: ADC14MEM31 interrupt flag; Interrupt Flag: ADC14IFG31"]
ADC14IV_74,
#[doc = "Interrupt Source: ADC14RDYIFG interrupt flag; Interrupt Flag: ADC14RDYIFG; Interrupt Priority: Lowest"]
ADC14IV_76,
#[doc = r" Reserved"]
_Reserved(u32),
}
impl ADC14IVR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
match *self {
ADC14IVR::ADC14IV_0 => 0,
ADC14IVR::ADC14IV_2 => 2,
ADC14IVR::ADC14IV_4 => 4,
ADC14IVR::ADC14IV_6 => 6,
ADC14IVR::ADC14IV_8 => 8,
ADC14IVR::ADC14IV_10 => 10,
ADC14IVR::ADC14IV_12 => 12,
ADC14IVR::ADC14IV_14 => 14,
ADC14IVR::ADC14IV_16 => 16,
ADC14IVR::ADC14IV_18 => 18,
ADC14IVR::ADC14IV_20 => 20,
ADC14IVR::ADC14IV_22 => 22,
ADC14IVR::ADC14IV_24 => 24,
ADC14IVR::ADC14IV_26 => 26,
ADC14IVR::ADC14IV_28 => 28,
ADC14IVR::ADC14IV_30 => 30,
ADC14IVR::ADC14IV_32 => 32,
ADC14IVR::ADC14IV_34 => 34,
ADC14IVR::ADC14IV_36 => 36,
ADC14IVR::ADC14IV_38 => 38,
ADC14IVR::ADC14IV_40 => 40,
ADC14IVR::ADC14IV_42 => 42,
ADC14IVR::ADC14IV_44 => 44,
ADC14IVR::ADC14IV_46 => 46,
ADC14IVR::ADC14IV_48 => 48,
ADC14IVR::ADC14IV_50 => 50,
ADC14IVR::ADC14IV_52 => 52,
ADC14IVR::ADC14IV_54 => 54,
ADC14IVR::ADC14IV_56 => 56,
ADC14IVR::ADC14IV_58 => 58,
ADC14IVR::ADC14IV_60 => 60,
ADC14IVR::ADC14IV_62 => 62,
ADC14IVR::ADC14IV_64 => 64,
ADC14IVR::ADC14IV_66 => 66,
ADC14IVR::ADC14IV_68 => 68,
ADC14IVR::ADC14IV_70 => 70,
ADC14IVR::ADC14IV_72 => 72,
ADC14IVR::ADC14IV_74 => 74,
ADC14IVR::ADC14IV_76 => 76,
ADC14IVR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u32) -> ADC14IVR {
match value {
0 => ADC14IVR::ADC14IV_0,
2 => ADC14IVR::ADC14IV_2,
4 => ADC14IVR::ADC14IV_4,
6 => ADC14IVR::ADC14IV_6,
8 => ADC14IVR::ADC14IV_8,
10 => ADC14IVR::ADC14IV_10,
12 => ADC14IVR::ADC14IV_12,
14 => ADC14IVR::ADC14IV_14,
16 => ADC14IVR::ADC14IV_16,
18 => ADC14IVR::ADC14IV_18,
20 => ADC14IVR::ADC14IV_20,
22 => ADC14IVR::ADC14IV_22,
24 => ADC14IVR::ADC14IV_24,
26 => ADC14IVR::ADC14IV_26,
28 => ADC14IVR::ADC14IV_28,
30 => ADC14IVR::ADC14IV_30,
32 => ADC14IVR::ADC14IV_32,
34 => ADC14IVR::ADC14IV_34,
36 => ADC14IVR::ADC14IV_36,
38 => ADC14IVR::ADC14IV_38,
40 => ADC14IVR::ADC14IV_40,
42 => ADC14IVR::ADC14IV_42,
44 => ADC14IVR::ADC14IV_44,
46 => ADC14IVR::ADC14IV_46,
48 => ADC14IVR::ADC14IV_48,
50 => ADC14IVR::ADC14IV_50,
52 => ADC14IVR::ADC14IV_52,
54 => ADC14IVR::ADC14IV_54,
56 => ADC14IVR::ADC14IV_56,
58 => ADC14IVR::ADC14IV_58,
60 => ADC14IVR::ADC14IV_60,
62 => ADC14IVR::ADC14IV_62,
64 => ADC14IVR::ADC14IV_64,
66 => ADC14IVR::ADC14IV_66,
68 => ADC14IVR::ADC14IV_68,
70 => ADC14IVR::ADC14IV_70,
72 => ADC14IVR::ADC14IV_72,
74 => ADC14IVR::ADC14IV_74,
76 => ADC14IVR::ADC14IV_76,
i => ADC14IVR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `ADC14IV_0`"]
#[inline]
pub fn is_adc14iv_0(&self) -> bool {
*self == ADC14IVR::ADC14IV_0
}
#[doc = "Checks if the value of the field is `ADC14IV_2`"]
#[inline]
pub fn is_adc14iv_2(&self) -> bool {
*self == ADC14IVR::ADC14IV_2
}
#[doc = "Checks if the value of the field is `ADC14IV_4`"]
#[inline]
pub fn is_adc14iv_4(&self) -> bool {
*self == ADC14IVR::ADC14IV_4
}
#[doc = "Checks if the value of the field is `ADC14IV_6`"]
#[inline]
pub fn is_adc14iv_6(&self) -> bool {
*self == ADC14IVR::ADC14IV_6
}
#[doc = "Checks if the value of the field is `ADC14IV_8`"]
#[inline]
pub fn is_adc14iv_8(&self) -> bool {
*self == ADC14IVR::ADC14IV_8
}
#[doc = "Checks if the value of the field is `ADC14IV_10`"]
#[inline]
pub fn is_adc14iv_10(&self) -> bool {
*self == ADC14IVR::ADC14IV_10
}
#[doc = "Checks if the value of the field is `ADC14IV_12`"]
#[inline]
pub fn is_adc14iv_12(&self) -> bool {
*self == ADC14IVR::ADC14IV_12
}
#[doc = "Checks if the value of the field is `ADC14IV_14`"]
#[inline]
pub fn is_adc14iv_14(&self) -> bool {
*self == ADC14IVR::ADC14IV_14
}
#[doc = "Checks if the value of the field is `ADC14IV_16`"]
#[inline]
pub fn is_adc14iv_16(&self) -> bool {
*self == ADC14IVR::ADC14IV_16
}
#[doc = "Checks if the value of the field is `ADC14IV_18`"]
#[inline]
pub fn is_adc14iv_18(&self) -> bool {
*self == ADC14IVR::ADC14IV_18
}
#[doc = "Checks if the value of the field is `ADC14IV_20`"]
#[inline]
pub fn is_adc14iv_20(&self) -> bool {
*self == ADC14IVR::ADC14IV_20
}
#[doc = "Checks if the value of the field is `ADC14IV_22`"]
#[inline]
pub fn is_adc14iv_22(&self) -> bool {
*self == ADC14IVR::ADC14IV_22
}
#[doc = "Checks if the value of the field is `ADC14IV_24`"]
#[inline]
pub fn is_adc14iv_24(&self) -> bool {
*self == ADC14IVR::ADC14IV_24
}
#[doc = "Checks if the value of the field is `ADC14IV_26`"]
#[inline]
pub fn is_adc14iv_26(&self) -> bool {
*self == ADC14IVR::ADC14IV_26
}
#[doc = "Checks if the value of the field is `ADC14IV_28`"]
#[inline]
pub fn is_adc14iv_28(&self) -> bool {
*self == ADC14IVR::ADC14IV_28
}
#[doc = "Checks if the value of the field is `ADC14IV_30`"]
#[inline]
pub fn is_adc14iv_30(&self) -> bool {
*self == ADC14IVR::ADC14IV_30
}
#[doc = "Checks if the value of the field is `ADC14IV_32`"]
#[inline]
pub fn is_adc14iv_32(&self) -> bool {
*self == ADC14IVR::ADC14IV_32
}
#[doc = "Checks if the value of the field is `ADC14IV_34`"]
#[inline]
pub fn is_adc14iv_34(&self) -> bool {
*self == ADC14IVR::ADC14IV_34
}
#[doc = "Checks if the value of the field is `ADC14IV_36`"]
#[inline]
pub fn is_adc14iv_36(&self) -> bool {
*self == ADC14IVR::ADC14IV_36
}
#[doc = "Checks if the value of the field is `ADC14IV_38`"]
#[inline]
pub fn is_adc14iv_38(&self) -> bool {
*self == ADC14IVR::ADC14IV_38
}
#[doc = "Checks if the value of the field is `ADC14IV_40`"]
#[inline]
pub fn is_adc14iv_40(&self) -> bool {
*self == ADC14IVR::ADC14IV_40
}
#[doc = "Checks if the value of the field is `ADC14IV_42`"]
#[inline]
pub fn is_adc14iv_42(&self) -> bool {
*self == ADC14IVR::ADC14IV_42
}
#[doc = "Checks if the value of the field is `ADC14IV_44`"]
#[inline]
pub fn is_adc14iv_44(&self) -> bool {
*self == ADC14IVR::ADC14IV_44
}
#[doc = "Checks if the value of the field is `ADC14IV_46`"]
#[inline]
pub fn is_adc14iv_46(&self) -> bool {
*self == ADC14IVR::ADC14IV_46
}
#[doc = "Checks if the value of the field is `ADC14IV_48`"]
#[inline]
pub fn is_adc14iv_48(&self) -> bool {
*self == ADC14IVR::ADC14IV_48
}
#[doc = "Checks if the value of the field is `ADC14IV_50`"]
#[inline]
pub fn is_adc14iv_50(&self) -> bool {
*self == ADC14IVR::ADC14IV_50
}
#[doc = "Checks if the value of the field is `ADC14IV_52`"]
#[inline]
pub fn is_adc14iv_52(&self) -> bool {
*self == ADC14IVR::ADC14IV_52
}
#[doc = "Checks if the value of the field is `ADC14IV_54`"]
#[inline]
pub fn is_adc14iv_54(&self) -> bool {
*self == ADC14IVR::ADC14IV_54
}
#[doc = "Checks if the value of the field is `ADC14IV_56`"]
#[inline]
pub fn is_adc14iv_56(&self) -> bool {
*self == ADC14IVR::ADC14IV_56
}
#[doc = "Checks if the value of the field is `ADC14IV_58`"]
#[inline]
pub fn is_adc14iv_58(&self) -> bool {
*self == ADC14IVR::ADC14IV_58
}
#[doc = "Checks if the value of the field is `ADC14IV_60`"]
#[inline]
pub fn is_adc14iv_60(&self) -> bool {
*self == ADC14IVR::ADC14IV_60
}
#[doc = "Checks if the value of the field is `ADC14IV_62`"]
#[inline]
pub fn is_adc14iv_62(&self) -> bool {
*self == ADC14IVR::ADC14IV_62
}
#[doc = "Checks if the value of the field is `ADC14IV_64`"]
#[inline]
pub fn is_adc14iv_64(&self) -> bool {
*self == ADC14IVR::ADC14IV_64
}
#[doc = "Checks if the value of the field is `ADC14IV_66`"]
#[inline]
pub fn is_adc14iv_66(&self) -> bool {
*self == ADC14IVR::ADC14IV_66
}
#[doc = "Checks if the value of the field is `ADC14IV_68`"]
#[inline]
pub fn is_adc14iv_68(&self) -> bool {
*self == ADC14IVR::ADC14IV_68
}
#[doc = "Checks if the value of the field is `ADC14IV_70`"]
#[inline]
pub fn is_adc14iv_70(&self) -> bool {
*self == ADC14IVR::ADC14IV_70
}
#[doc = "Checks if the value of the field is `ADC14IV_72`"]
#[inline]
pub fn is_adc14iv_72(&self) -> bool {
*self == ADC14IVR::ADC14IV_72
}
#[doc = "Checks if the value of the field is `ADC14IV_74`"]
#[inline]
pub fn is_adc14iv_74(&self) -> bool {
*self == ADC14IVR::ADC14IV_74
}
#[doc = "Checks if the value of the field is `ADC14IV_76`"]
#[inline]
pub fn is_adc14iv_76(&self) -> bool {
*self == ADC14IVR::ADC14IV_76
}
}
#[doc = "Values that can be written to the field `ADC14IV`"]
pub enum ADC14IVW {
#[doc = "No interrupt pending"]
ADC14IV_0,
#[doc = "Interrupt Source: ADC14MEMx overflow; Interrupt Flag: ADC14OVIFG; Interrupt Priority: Highest"]
ADC14IV_2,
#[doc = "Interrupt Source: Conversion time overflow; Interrupt Flag: ADC14TOVIFG"]
ADC14IV_4,
#[doc = "Interrupt Source: ADC14 window high interrupt flag; Interrupt Flag: ADC14HIIFG"]
ADC14IV_6,
#[doc = "Interrupt Source: ADC14 window low interrupt flag; Interrupt Flag: ADC14LOIFG"]
ADC14IV_8,
#[doc = "Interrupt Source: ADC14 in-window interrupt flag; Interrupt Flag: ADC14INIFG"]
ADC14IV_10,
#[doc = "Interrupt Source: ADC14MEM0 interrupt flag; Interrupt Flag: ADC14IFG0"]
ADC14IV_12,
#[doc = "Interrupt Source: ADC14MEM1 interrupt flag; Interrupt Flag: ADC14IFG1"]
ADC14IV_14,
#[doc = "Interrupt Source: ADC14MEM2 interrupt flag; Interrupt Flag: ADC14IFG2"]
ADC14IV_16,
#[doc = "Interrupt Source: ADC14MEM3 interrupt flag; Interrupt Flag: ADC14IFG3"]
ADC14IV_18,
#[doc = "Interrupt Source: ADC14MEM4 interrupt flag; Interrupt Flag: ADC14IFG4"]
ADC14IV_20,
#[doc = "Interrupt Source: ADC14MEM5 interrupt flag; Interrupt Flag: ADC14IFG5"]
ADC14IV_22,
#[doc = "Interrupt Source: ADC14MEM6 interrupt flag; Interrupt Flag: ADC14IFG6"]
ADC14IV_24,
#[doc = "Interrupt Source: ADC14MEM7 interrupt flag; Interrupt Flag: ADC14IFG7"]
ADC14IV_26,
#[doc = "Interrupt Source: ADC14MEM8 interrupt flag; Interrupt Flag: ADC14IFG8"]
ADC14IV_28,
#[doc = "Interrupt Source: ADC14MEM9 interrupt flag; Interrupt Flag: ADC14IFG9"]
ADC14IV_30,
#[doc = "Interrupt Source: ADC14MEM10 interrupt flag; Interrupt Flag: ADC14IFG10"]
ADC14IV_32,
#[doc = "Interrupt Source: ADC14MEM11 interrupt flag; Interrupt Flag: ADC14IFG11"]
ADC14IV_34,
#[doc = "Interrupt Source: ADC14MEM12 interrupt flag; Interrupt Flag: ADC14IFG12"]
ADC14IV_36,
#[doc = "Interrupt Source: ADC14MEM13 interrupt flag; Interrupt Flag: ADC14IFG13"]
ADC14IV_38,
#[doc = "Interrupt Source: ADC14MEM14 interrupt flag; Interrupt Flag: ADC14IFG14"]
ADC14IV_40,
#[doc = "Interrupt Source: ADC14MEM15 interrupt flag; Interrupt Flag: ADC14IFG15"]
ADC14IV_42,
#[doc = "Interrupt Source: ADC14MEM16 interrupt flag; Interrupt Flag: ADC14IFG16"]
ADC14IV_44,
#[doc = "Interrupt Source: ADC14MEM17 interrupt flag; Interrupt Flag: ADC14IFG17"]
ADC14IV_46,
#[doc = "Interrupt Source: ADC14MEM18 interrupt flag; Interrupt Flag: ADC14IFG18"]
ADC14IV_48,
#[doc = "Interrupt Source: ADC14MEM19 interrupt flag; Interrupt Flag: ADC14IFG19"]
ADC14IV_50,
#[doc = "Interrupt Source: ADC14MEM20 interrupt flag; Interrupt Flag: ADC14IFG20"]
ADC14IV_52,
#[doc = "Interrupt Source: ADC14MEM22 interrupt flag; Interrupt Flag: ADC14IFG22"]
ADC14IV_54,
#[doc = "Interrupt Source: ADC14MEM22 interrupt flag; Interrupt Flag: ADC14IFG22"]
ADC14IV_56,
#[doc = "Interrupt Source: ADC14MEM23 interrupt flag; Interrupt Flag: ADC14IFG23"]
ADC14IV_58,
#[doc = "Interrupt Source: ADC14MEM24 interrupt flag; Interrupt Flag: ADC14IFG24"]
ADC14IV_60,
#[doc = "Interrupt Source: ADC14MEM25 interrupt flag; Interrupt Flag: ADC14IFG25"]
ADC14IV_62,
#[doc = "Interrupt Source: ADC14MEM26 interrupt flag; Interrupt Flag: ADC14IFG26"]
ADC14IV_64,
#[doc = "Interrupt Source: ADC14MEM27 interrupt flag; Interrupt Flag: ADC14IFG27"]
ADC14IV_66,
#[doc = "Interrupt Source: ADC14MEM28 interrupt flag; Interrupt Flag: ADC14IFG28"]
ADC14IV_68,
#[doc = "Interrupt Source: ADC14MEM29 interrupt flag; Interrupt Flag: ADC14IFG29"]
ADC14IV_70,
#[doc = "Interrupt Source: ADC14MEM30 interrupt flag; Interrupt Flag: ADC14IFG30"]
ADC14IV_72,
#[doc = "Interrupt Source: ADC14MEM31 interrupt flag; Interrupt Flag: ADC14IFG31"]
ADC14IV_74,
#[doc = "Interrupt Source: ADC14RDYIFG interrupt flag; Interrupt Flag: ADC14RDYIFG; Interrupt Priority: Lowest"]
ADC14IV_76,
}
impl ADC14IVW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u32 {
match *self {
ADC14IVW::ADC14IV_0 => 0,
ADC14IVW::ADC14IV_2 => 2,
ADC14IVW::ADC14IV_4 => 4,
ADC14IVW::ADC14IV_6 => 6,
ADC14IVW::ADC14IV_8 => 8,
ADC14IVW::ADC14IV_10 => 10,
ADC14IVW::ADC14IV_12 => 12,
ADC14IVW::ADC14IV_14 => 14,
ADC14IVW::ADC14IV_16 => 16,
ADC14IVW::ADC14IV_18 => 18,
ADC14IVW::ADC14IV_20 => 20,
ADC14IVW::ADC14IV_22 => 22,
ADC14IVW::ADC14IV_24 => 24,
ADC14IVW::ADC14IV_26 => 26,
ADC14IVW::ADC14IV_28 => 28,
ADC14IVW::ADC14IV_30 => 30,
ADC14IVW::ADC14IV_32 => 32,
ADC14IVW::ADC14IV_34 => 34,
ADC14IVW::ADC14IV_36 => 36,
ADC14IVW::ADC14IV_38 => 38,
ADC14IVW::ADC14IV_40 => 40,
ADC14IVW::ADC14IV_42 => 42,
ADC14IVW::ADC14IV_44 => 44,
ADC14IVW::ADC14IV_46 => 46,
ADC14IVW::ADC14IV_48 => 48,
ADC14IVW::ADC14IV_50 => 50,
ADC14IVW::ADC14IV_52 => 52,
ADC14IVW::ADC14IV_54 => 54,
ADC14IVW::ADC14IV_56 => 56,
ADC14IVW::ADC14IV_58 => 58,
ADC14IVW::ADC14IV_60 => 60,
ADC14IVW::ADC14IV_62 => 62,
ADC14IVW::ADC14IV_64 => 64,
ADC14IVW::ADC14IV_66 => 66,
ADC14IVW::ADC14IV_68 => 68,
ADC14IVW::ADC14IV_70 => 70,
ADC14IVW::ADC14IV_72 => 72,
ADC14IVW::ADC14IV_74 => 74,
ADC14IVW::ADC14IV_76 => 76,
}
}
}
#[doc = r" Proxy"]
pub struct _ADC14IVW<'a> {
w: &'a mut W,
}
impl<'a> _ADC14IVW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADC14IVW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "No interrupt pending"]
#[inline]
pub fn adc14iv_0(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_0)
}
#[doc = "Interrupt Source: ADC14MEMx overflow; Interrupt Flag: ADC14OVIFG; Interrupt Priority: Highest"]
#[inline]
pub fn adc14iv_2(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_2)
}
#[doc = "Interrupt Source: Conversion time overflow; Interrupt Flag: ADC14TOVIFG"]
#[inline]
pub fn adc14iv_4(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_4)
}
#[doc = "Interrupt Source: ADC14 window high interrupt flag; Interrupt Flag: ADC14HIIFG"]
#[inline]
pub fn adc14iv_6(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_6)
}
#[doc = "Interrupt Source: ADC14 window low interrupt flag; Interrupt Flag: ADC14LOIFG"]
#[inline]
pub fn adc14iv_8(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_8)
}
#[doc = "Interrupt Source: ADC14 in-window interrupt flag; Interrupt Flag: ADC14INIFG"]
#[inline]
pub fn adc14iv_10(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_10)
}
#[doc = "Interrupt Source: ADC14MEM0 interrupt flag; Interrupt Flag: ADC14IFG0"]
#[inline]
pub fn adc14iv_12(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_12)
}
#[doc = "Interrupt Source: ADC14MEM1 interrupt flag; Interrupt Flag: ADC14IFG1"]
#[inline]
pub fn adc14iv_14(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_14)
}
#[doc = "Interrupt Source: ADC14MEM2 interrupt flag; Interrupt Flag: ADC14IFG2"]
#[inline]
pub fn adc14iv_16(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_16)
}
#[doc = "Interrupt Source: ADC14MEM3 interrupt flag; Interrupt Flag: ADC14IFG3"]
#[inline]
pub fn adc14iv_18(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_18)
}
#[doc = "Interrupt Source: ADC14MEM4 interrupt flag; Interrupt Flag: ADC14IFG4"]
#[inline]
pub fn adc14iv_20(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_20)
}
#[doc = "Interrupt Source: ADC14MEM5 interrupt flag; Interrupt Flag: ADC14IFG5"]
#[inline]
pub fn adc14iv_22(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_22)
}
#[doc = "Interrupt Source: ADC14MEM6 interrupt flag; Interrupt Flag: ADC14IFG6"]
#[inline]
pub fn adc14iv_24(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_24)
}
#[doc = "Interrupt Source: ADC14MEM7 interrupt flag; Interrupt Flag: ADC14IFG7"]
#[inline]
pub fn adc14iv_26(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_26)
}
#[doc = "Interrupt Source: ADC14MEM8 interrupt flag; Interrupt Flag: ADC14IFG8"]
#[inline]
pub fn adc14iv_28(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_28)
}
#[doc = "Interrupt Source: ADC14MEM9 interrupt flag; Interrupt Flag: ADC14IFG9"]
#[inline]
pub fn adc14iv_30(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_30)
}
#[doc = "Interrupt Source: ADC14MEM10 interrupt flag; Interrupt Flag: ADC14IFG10"]
#[inline]
pub fn adc14iv_32(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_32)
}
#[doc = "Interrupt Source: ADC14MEM11 interrupt flag; Interrupt Flag: ADC14IFG11"]
#[inline]
pub fn adc14iv_34(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_34)
}
#[doc = "Interrupt Source: ADC14MEM12 interrupt flag; Interrupt Flag: ADC14IFG12"]
#[inline]
pub fn adc14iv_36(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_36)
}
#[doc = "Interrupt Source: ADC14MEM13 interrupt flag; Interrupt Flag: ADC14IFG13"]
#[inline]
pub fn adc14iv_38(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_38)
}
#[doc = "Interrupt Source: ADC14MEM14 interrupt flag; Interrupt Flag: ADC14IFG14"]
#[inline]
pub fn adc14iv_40(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_40)
}
#[doc = "Interrupt Source: ADC14MEM15 interrupt flag; Interrupt Flag: ADC14IFG15"]
#[inline]
pub fn adc14iv_42(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_42)
}
#[doc = "Interrupt Source: ADC14MEM16 interrupt flag; Interrupt Flag: ADC14IFG16"]
#[inline]
pub fn adc14iv_44(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_44)
}
#[doc = "Interrupt Source: ADC14MEM17 interrupt flag; Interrupt Flag: ADC14IFG17"]
#[inline]
pub fn adc14iv_46(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_46)
}
#[doc = "Interrupt Source: ADC14MEM18 interrupt flag; Interrupt Flag: ADC14IFG18"]
#[inline]
pub fn adc14iv_48(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_48)
}
#[doc = "Interrupt Source: ADC14MEM19 interrupt flag; Interrupt Flag: ADC14IFG19"]
#[inline]
pub fn adc14iv_50(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_50)
}
#[doc = "Interrupt Source: ADC14MEM20 interrupt flag; Interrupt Flag: ADC14IFG20"]
#[inline]
pub fn adc14iv_52(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_52)
}
#[doc = "Interrupt Source: ADC14MEM22 interrupt flag; Interrupt Flag: ADC14IFG22"]
#[inline]
pub fn adc14iv_54(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_54)
}
#[doc = "Interrupt Source: ADC14MEM22 interrupt flag; Interrupt Flag: ADC14IFG22"]
#[inline]
pub fn adc14iv_56(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_56)
}
#[doc = "Interrupt Source: ADC14MEM23 interrupt flag; Interrupt Flag: ADC14IFG23"]
#[inline]
pub fn adc14iv_58(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_58)
}
#[doc = "Interrupt Source: ADC14MEM24 interrupt flag; Interrupt Flag: ADC14IFG24"]
#[inline]
pub fn adc14iv_60(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_60)
}
#[doc = "Interrupt Source: ADC14MEM25 interrupt flag; Interrupt Flag: ADC14IFG25"]
#[inline]
pub fn adc14iv_62(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_62)
}
#[doc = "Interrupt Source: ADC14MEM26 interrupt flag; Interrupt Flag: ADC14IFG26"]
#[inline]
pub fn adc14iv_64(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_64)
}
#[doc = "Interrupt Source: ADC14MEM27 interrupt flag; Interrupt Flag: ADC14IFG27"]
#[inline]
pub fn adc14iv_66(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_66)
}
#[doc = "Interrupt Source: ADC14MEM28 interrupt flag; Interrupt Flag: ADC14IFG28"]
#[inline]
pub fn adc14iv_68(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_68)
}
#[doc = "Interrupt Source: ADC14MEM29 interrupt flag; Interrupt Flag: ADC14IFG29"]
#[inline]
pub fn adc14iv_70(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_70)
}
#[doc = "Interrupt Source: ADC14MEM30 interrupt flag; Interrupt Flag: ADC14IFG30"]
#[inline]
pub fn adc14iv_72(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_72)
}
#[doc = "Interrupt Source: ADC14MEM31 interrupt flag; Interrupt Flag: ADC14IFG31"]
#[inline]
pub fn adc14iv_74(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_74)
}
#[doc = "Interrupt Source: ADC14RDYIFG interrupt flag; Interrupt Flag: ADC14RDYIFG; Interrupt Priority: Lowest"]
#[inline]
pub fn adc14iv_76(self) -> &'a mut W {
self.variant(ADC14IVW::ADC14IV_76)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 4294967295;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - ADC14 interrupt vector value"]
#[inline]
pub fn adc14iv(&self) -> ADC14IVR {
ADC14IVR::_from({
const MASK: u32 = 4294967295;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - ADC14 interrupt vector value"]
#[inline]
pub fn adc14iv(&mut self) -> _ADC14IVW {
_ADC14IVW { w: self }
}
}

105
example-source/msp432p401r/src/adc14/adc14lo0.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::ADC14LO0 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct ADC14LO0R {
bits: u16,
}
impl ADC14LO0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _ADC14LO0W<'a> {
w: &'a mut W,
}
impl<'a> _ADC14LO0W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - Low threshold 0"]
#[inline]
pub fn adc14lo0(&self) -> ADC14LO0R {
let bits = {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
ADC14LO0R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - Low threshold 0"]
#[inline]
pub fn adc14lo0(&mut self) -> _ADC14LO0W {
_ADC14LO0W { w: self }
}
}

105
example-source/msp432p401r/src/adc14/adc14lo1.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::ADC14LO1 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct ADC14LO1R {
bits: u16,
}
impl ADC14LO1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _ADC14LO1W<'a> {
w: &'a mut W,
}
impl<'a> _ADC14LO1W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - Low threshold 1"]
#[inline]
pub fn adc14lo1(&self) -> ADC14LO1R {
let bits = {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
ADC14LO1R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - Low threshold 1"]
#[inline]
pub fn adc14lo1(&mut self) -> _ADC14LO1W {
_ADC14LO1W { w: self }
}
}

1289
example-source/msp432p401r/src/adc14/adc14mctl.rs Normal file
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105
example-source/msp432p401r/src/adc14/adc14mem.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::ADC14MEM {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CONVERSION_RESULTSR {
bits: u16,
}
impl CONVERSION_RESULTSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CONVERSION_RESULTSW<'a> {
w: &'a mut W,
}
impl<'a> _CONVERSION_RESULTSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - Conversion Result"]
#[inline]
pub fn conversion_results(&self) -> CONVERSION_RESULTSR {
let bits = {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
CONVERSION_RESULTSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - Conversion Result"]
#[inline]
pub fn conversion_results(&mut self) -> _CONVERSION_RESULTSW {
_CONVERSION_RESULTSW { w: self }
}
}

68
example-source/msp432p401r/src/aes256.rs Normal file
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#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - AES Accelerator Control Register 0"]
pub aesactl0: AESACTL0,
#[doc = "0x02 - AES Accelerator Control Register 1"]
pub aesactl1: AESACTL1,
#[doc = "0x04 - AES Accelerator Status Register"]
pub aesastat: AESASTAT,
#[doc = "0x06 - AES Accelerator Key Register"]
pub aesakey: AESAKEY,
#[doc = "0x08 - AES Accelerator Data In Register"]
pub aesadin: AESADIN,
#[doc = "0x0a - AES Accelerator Data Out Register"]
pub aesadout: AESADOUT,
#[doc = "0x0c - AES Accelerator XORed Data In Register"]
pub aesaxdin: AESAXDIN,
#[doc = "0x0e - AES Accelerator XORed Data In Register"]
pub aesaxin: AESAXIN,
}
#[doc = "AES Accelerator Control Register 0"]
pub struct AESACTL0 {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "AES Accelerator Control Register 0"]
pub mod aesactl0;
#[doc = "AES Accelerator Control Register 1"]
pub struct AESACTL1 {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "AES Accelerator Control Register 1"]
pub mod aesactl1;
#[doc = "AES Accelerator Status Register"]
pub struct AESASTAT {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "AES Accelerator Status Register"]
pub mod aesastat;
#[doc = "AES Accelerator Key Register"]
pub struct AESAKEY {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "AES Accelerator Key Register"]
pub mod aesakey;
#[doc = "AES Accelerator Data In Register"]
pub struct AESADIN {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "AES Accelerator Data In Register"]
pub mod aesadin;
#[doc = "AES Accelerator Data Out Register"]
pub struct AESADOUT {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "AES Accelerator Data Out Register"]
pub mod aesadout;
#[doc = "AES Accelerator XORed Data In Register"]
pub struct AESAXDIN {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "AES Accelerator XORed Data In Register"]
pub mod aesaxdin;
#[doc = "AES Accelerator XORed Data In Register"]
pub struct AESAXIN {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "AES Accelerator XORed Data In Register"]
pub mod aesaxin;

1051
example-source/msp432p401r/src/aes256/aesactl0.rs Normal file
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105
example-source/msp432p401r/src/aes256/aesactl1.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u16,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u16,
}
impl super::AESACTL1 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct AESBLKCNTXR {
bits: u8,
}
impl AESBLKCNTXR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _AESBLKCNTXW<'a> {
w: &'a mut W,
}
impl<'a> _AESBLKCNTXW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
#[doc = "Bits 0:7 - Cipher Block Counter"]
#[inline]
pub fn aesblkcntx(&self) -> AESBLKCNTXR {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u16) as u8
};
AESBLKCNTXR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Cipher Block Counter"]
#[inline]
pub fn aesblkcntx(&mut self) -> _AESBLKCNTXW {
_AESBLKCNTXW { w: self }
}
}

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#[doc = r" Value to write to the register"]
pub struct W {
bits: u16,
}
impl super::AESADIN {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _AESDIN0XW<'a> {
w: &'a mut W,
}
impl<'a> _AESDIN0XW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _AESDIN1XW<'a> {
w: &'a mut W,
}
impl<'a> _AESDIN1XW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - AES data in byte n when AESADIN is written as half-word"]
#[inline]
pub fn aesdin0x(&mut self) -> _AESDIN0XW {
_AESDIN0XW { w: self }
}
#[doc = "Bits 8:15 - AES data in byte n+1 when AESADIN is written as half-word"]
#[inline]
pub fn aesdin1x(&mut self) -> _AESDIN1XW {
_AESDIN1XW { w: self }
}
}

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#[doc = r" Value to write to the register"]
pub struct W {
bits: u16,
}
impl super::AESADOUT {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _AESDOUT0XW<'a> {
w: &'a mut W,
}
impl<'a> _AESDOUT0XW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _AESDOUT1XW<'a> {
w: &'a mut W,
}
impl<'a> _AESDOUT1XW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - AES data out byte n when AESADOUT is read as half-word"]
#[inline]
pub fn aesdout0x(&mut self) -> _AESDOUT0XW {
_AESDOUT0XW { w: self }
}
#[doc = "Bits 8:15 - AES data out byte n+1 when AESADOUT is read as half-word"]
#[inline]
pub fn aesdout1x(&mut self) -> _AESDOUT1XW {
_AESDOUT1XW { w: self }
}
}

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#[doc = r" Value to write to the register"]
pub struct W {
bits: u16,
}
impl super::AESAKEY {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _AESKEY0XW<'a> {
w: &'a mut W,
}
impl<'a> _AESKEY0XW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _AESKEY1XW<'a> {
w: &'a mut W,
}
impl<'a> _AESKEY1XW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - AES key byte n when AESAKEY is written as half-word"]
#[inline]
pub fn aeskey0x(&mut self) -> _AESKEY0XW {
_AESKEY0XW { w: self }
}
#[doc = "Bits 8:15 - AES key byte n+1 when AESAKEY is written as half-word"]
#[inline]
pub fn aeskey1x(&mut self) -> _AESKEY1XW {
_AESKEY1XW { w: self }
}
}

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#[doc = r" Value read from the register"]
pub struct R {
bits: u16,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u16,
}
impl super::AESASTAT {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `AESBUSY`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum AESBUSYR {
#[doc = "Not busy"]
AESBUSY_0,
#[doc = "Busy"]
AESBUSY_1,
}
impl AESBUSYR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
AESBUSYR::AESBUSY_0 => false,
AESBUSYR::AESBUSY_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> AESBUSYR {
match value {
false => AESBUSYR::AESBUSY_0,
true => AESBUSYR::AESBUSY_1,
}
}
#[doc = "Checks if the value of the field is `AESBUSY_0`"]
#[inline]
pub fn is_aesbusy_0(&self) -> bool {
*self == AESBUSYR::AESBUSY_0
}
#[doc = "Checks if the value of the field is `AESBUSY_1`"]
#[inline]
pub fn is_aesbusy_1(&self) -> bool {
*self == AESBUSYR::AESBUSY_1
}
}
#[doc = "Possible values of the field `AESKEYWR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum AESKEYWRR {
#[doc = "Not all bytes written"]
AESKEYWR_0,
#[doc = "All bytes written"]
AESKEYWR_1,
}
impl AESKEYWRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
AESKEYWRR::AESKEYWR_0 => false,
AESKEYWRR::AESKEYWR_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> AESKEYWRR {
match value {
false => AESKEYWRR::AESKEYWR_0,
true => AESKEYWRR::AESKEYWR_1,
}
}
#[doc = "Checks if the value of the field is `AESKEYWR_0`"]
#[inline]
pub fn is_aeskeywr_0(&self) -> bool {
*self == AESKEYWRR::AESKEYWR_0
}
#[doc = "Checks if the value of the field is `AESKEYWR_1`"]
#[inline]
pub fn is_aeskeywr_1(&self) -> bool {
*self == AESKEYWRR::AESKEYWR_1
}
}
#[doc = "Possible values of the field `AESDINWR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum AESDINWRR {
#[doc = "Not all bytes written"]
AESDINWR_0,
#[doc = "All bytes written"]
AESDINWR_1,
}
impl AESDINWRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
AESDINWRR::AESDINWR_0 => false,
AESDINWRR::AESDINWR_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> AESDINWRR {
match value {
false => AESDINWRR::AESDINWR_0,
true => AESDINWRR::AESDINWR_1,
}
}
#[doc = "Checks if the value of the field is `AESDINWR_0`"]
#[inline]
pub fn is_aesdinwr_0(&self) -> bool {
*self == AESDINWRR::AESDINWR_0
}
#[doc = "Checks if the value of the field is `AESDINWR_1`"]
#[inline]
pub fn is_aesdinwr_1(&self) -> bool {
*self == AESDINWRR::AESDINWR_1
}
}
#[doc = "Possible values of the field `AESDOUTRD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum AESDOUTRDR {
#[doc = "Not all bytes read"]
AESDOUTRD_0,
#[doc = "All bytes read"]
AESDOUTRD_1,
}
impl AESDOUTRDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
AESDOUTRDR::AESDOUTRD_0 => false,
AESDOUTRDR::AESDOUTRD_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> AESDOUTRDR {
match value {
false => AESDOUTRDR::AESDOUTRD_0,
true => AESDOUTRDR::AESDOUTRD_1,
}
}
#[doc = "Checks if the value of the field is `AESDOUTRD_0`"]
#[inline]
pub fn is_aesdoutrd_0(&self) -> bool {
*self == AESDOUTRDR::AESDOUTRD_0
}
#[doc = "Checks if the value of the field is `AESDOUTRD_1`"]
#[inline]
pub fn is_aesdoutrd_1(&self) -> bool {
*self == AESDOUTRDR::AESDOUTRD_1
}
}
#[doc = r" Value of the field"]
pub struct AESKEYCNTXR {
bits: u8,
}
impl AESKEYCNTXR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct AESDINCNTXR {
bits: u8,
}
impl AESDINCNTXR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct AESDOUTCNTXR {
bits: u8,
}
impl AESDOUTCNTXR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = "Values that can be written to the field `AESBUSY`"]
pub enum AESBUSYW {
#[doc = "Not busy"]
AESBUSY_0,
#[doc = "Busy"]
AESBUSY_1,
}
impl AESBUSYW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
AESBUSYW::AESBUSY_0 => false,
AESBUSYW::AESBUSY_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _AESBUSYW<'a> {
w: &'a mut W,
}
impl<'a> _AESBUSYW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: AESBUSYW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Not busy"]
#[inline]
pub fn aesbusy_0(self) -> &'a mut W {
self.variant(AESBUSYW::AESBUSY_0)
}
#[doc = "Busy"]
#[inline]
pub fn aesbusy_1(self) -> &'a mut W {
self.variant(AESBUSYW::AESBUSY_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `AESKEYWR`"]
pub enum AESKEYWRW {
#[doc = "Not all bytes written"]
AESKEYWR_0,
#[doc = "All bytes written"]
AESKEYWR_1,
}
impl AESKEYWRW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
AESKEYWRW::AESKEYWR_0 => false,
AESKEYWRW::AESKEYWR_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _AESKEYWRW<'a> {
w: &'a mut W,
}
impl<'a> _AESKEYWRW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: AESKEYWRW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Not all bytes written"]
#[inline]
pub fn aeskeywr_0(self) -> &'a mut W {
self.variant(AESKEYWRW::AESKEYWR_0)
}
#[doc = "All bytes written"]
#[inline]
pub fn aeskeywr_1(self) -> &'a mut W {
self.variant(AESKEYWRW::AESKEYWR_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `AESDINWR`"]
pub enum AESDINWRW {
#[doc = "Not all bytes written"]
AESDINWR_0,
#[doc = "All bytes written"]
AESDINWR_1,
}
impl AESDINWRW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
AESDINWRW::AESDINWR_0 => false,
AESDINWRW::AESDINWR_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _AESDINWRW<'a> {
w: &'a mut W,
}
impl<'a> _AESDINWRW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: AESDINWRW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Not all bytes written"]
#[inline]
pub fn aesdinwr_0(self) -> &'a mut W {
self.variant(AESDINWRW::AESDINWR_0)
}
#[doc = "All bytes written"]
#[inline]
pub fn aesdinwr_1(self) -> &'a mut W {
self.variant(AESDINWRW::AESDINWR_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
#[doc = "Bit 0 - AES accelerator module busy"]
#[inline]
pub fn aesbusy(&self) -> AESBUSYR {
AESBUSYR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u16) != 0
})
}
#[doc = "Bit 1 - All 16 bytes written to AESAKEY"]
#[inline]
pub fn aeskeywr(&self) -> AESKEYWRR {
AESKEYWRR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u16) != 0
})
}
#[doc = "Bit 2 - All 16 bytes written to AESADIN, AESAXDIN or AESAXIN"]
#[inline]
pub fn aesdinwr(&self) -> AESDINWRR {
AESDINWRR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u16) != 0
})
}
#[doc = "Bit 3 - All 16 bytes read from AESADOUT"]
#[inline]
pub fn aesdoutrd(&self) -> AESDOUTRDR {
AESDOUTRDR::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u16) != 0
})
}
#[doc = "Bits 4:7 - Bytes written via AESAKEY for AESKLx=00, half-words written via AESAKEY"]
#[inline]
pub fn aeskeycntx(&self) -> AESKEYCNTXR {
let bits = {
const MASK: u8 = 15;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u16) as u8
};
AESKEYCNTXR { bits }
}
#[doc = "Bits 8:11 - Bytes written via AESADIN, AESAXDIN or AESAXIN"]
#[inline]
pub fn aesdincntx(&self) -> AESDINCNTXR {
let bits = {
const MASK: u8 = 15;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u16) as u8
};
AESDINCNTXR { bits }
}
#[doc = "Bits 12:15 - Bytes read via AESADOUT"]
#[inline]
pub fn aesdoutcntx(&self) -> AESDOUTCNTXR {
let bits = {
const MASK: u8 = 15;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u16) as u8
};
AESDOUTCNTXR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - AES accelerator module busy"]
#[inline]
pub fn aesbusy(&mut self) -> _AESBUSYW {
_AESBUSYW { w: self }
}
#[doc = "Bit 1 - All 16 bytes written to AESAKEY"]
#[inline]
pub fn aeskeywr(&mut self) -> _AESKEYWRW {
_AESKEYWRW { w: self }
}
#[doc = "Bit 2 - All 16 bytes written to AESADIN, AESAXDIN or AESAXIN"]
#[inline]
pub fn aesdinwr(&mut self) -> _AESDINWRW {
_AESDINWRW { w: self }
}
}

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example-source/msp432p401r/src/aes256/aesaxdin.rs Normal file
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#[doc = r" Value to write to the register"]
pub struct W {
bits: u16,
}
impl super::AESAXDIN {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _AESXDIN0XW<'a> {
w: &'a mut W,
}
impl<'a> _AESXDIN0XW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _AESXDIN1XW<'a> {
w: &'a mut W,
}
impl<'a> _AESXDIN1XW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - AES data in byte n when AESAXDIN is written as half-word"]
#[inline]
pub fn aesxdin0x(&mut self) -> _AESXDIN0XW {
_AESXDIN0XW { w: self }
}
#[doc = "Bits 8:15 - AES data in byte n+1 when AESAXDIN is written as half-word"]
#[inline]
pub fn aesxdin1x(&mut self) -> _AESXDIN1XW {
_AESXDIN1XW { w: self }
}
}

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example-source/msp432p401r/src/aes256/aesaxin.rs Normal file
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#[doc = r" Value to write to the register"]
pub struct W {
bits: u16,
}
impl super::AESAXIN {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _AESXIN0XW<'a> {
w: &'a mut W,
}
impl<'a> _AESXIN0XW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _AESXIN1XW<'a> {
w: &'a mut W,
}
impl<'a> _AESXIN1XW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - AES data in byte n when AESAXIN is written as half-word"]
#[inline]
pub fn aesxin0x(&mut self) -> _AESXIN0XW {
_AESXIN0XW { w: self }
}
#[doc = "Bits 8:15 - AES data in byte n+1 when AESAXIN is written as half-word"]
#[inline]
pub fn aesxin1x(&mut self) -> _AESXIN1XW {
_AESXIN1XW { w: self }
}
}

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example-source/msp432p401r/src/captio0.rs Normal file
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#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
_reserved0: [u8; 14usize],
#[doc = "0x0e - Capacitive Touch IO x Control Register"]
pub captiox_ctl: CAPTIOXCTL,
}
#[doc = "Capacitive Touch IO x Control Register"]
pub struct CAPTIOXCTL {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Capacitive Touch IO x Control Register"]
pub mod captiox_ctl;

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example-source/msp432p401r/src/captio0/captiox_ctl.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u16,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u16,
}
impl super::CAPTIOXCTL {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `CAPTIOPISELx`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CAPTIOPISELXR {
#[doc = "Px.0"]
CAPTIOPISELX_0,
#[doc = "Px.1"]
CAPTIOPISELX_1,
#[doc = "Px.2"]
CAPTIOPISELX_2,
#[doc = "Px.3"]
CAPTIOPISELX_3,
#[doc = "Px.4"]
CAPTIOPISELX_4,
#[doc = "Px.5"]
CAPTIOPISELX_5,
#[doc = "Px.6"]
CAPTIOPISELX_6,
#[doc = "Px.7"]
CAPTIOPISELX_7,
}
impl CAPTIOPISELXR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
CAPTIOPISELXR::CAPTIOPISELX_0 => 0,
CAPTIOPISELXR::CAPTIOPISELX_1 => 1,
CAPTIOPISELXR::CAPTIOPISELX_2 => 2,
CAPTIOPISELXR::CAPTIOPISELX_3 => 3,
CAPTIOPISELXR::CAPTIOPISELX_4 => 4,
CAPTIOPISELXR::CAPTIOPISELX_5 => 5,
CAPTIOPISELXR::CAPTIOPISELX_6 => 6,
CAPTIOPISELXR::CAPTIOPISELX_7 => 7,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> CAPTIOPISELXR {
match value {
0 => CAPTIOPISELXR::CAPTIOPISELX_0,
1 => CAPTIOPISELXR::CAPTIOPISELX_1,
2 => CAPTIOPISELXR::CAPTIOPISELX_2,
3 => CAPTIOPISELXR::CAPTIOPISELX_3,
4 => CAPTIOPISELXR::CAPTIOPISELX_4,
5 => CAPTIOPISELXR::CAPTIOPISELX_5,
6 => CAPTIOPISELXR::CAPTIOPISELX_6,
7 => CAPTIOPISELXR::CAPTIOPISELX_7,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CAPTIOPISELX_0`"]
#[inline]
pub fn is_captiopiselx_0(&self) -> bool {
*self == CAPTIOPISELXR::CAPTIOPISELX_0
}
#[doc = "Checks if the value of the field is `CAPTIOPISELX_1`"]
#[inline]
pub fn is_captiopiselx_1(&self) -> bool {
*self == CAPTIOPISELXR::CAPTIOPISELX_1
}
#[doc = "Checks if the value of the field is `CAPTIOPISELX_2`"]
#[inline]
pub fn is_captiopiselx_2(&self) -> bool {
*self == CAPTIOPISELXR::CAPTIOPISELX_2
}
#[doc = "Checks if the value of the field is `CAPTIOPISELX_3`"]
#[inline]
pub fn is_captiopiselx_3(&self) -> bool {
*self == CAPTIOPISELXR::CAPTIOPISELX_3
}
#[doc = "Checks if the value of the field is `CAPTIOPISELX_4`"]
#[inline]
pub fn is_captiopiselx_4(&self) -> bool {
*self == CAPTIOPISELXR::CAPTIOPISELX_4
}
#[doc = "Checks if the value of the field is `CAPTIOPISELX_5`"]
#[inline]
pub fn is_captiopiselx_5(&self) -> bool {
*self == CAPTIOPISELXR::CAPTIOPISELX_5
}
#[doc = "Checks if the value of the field is `CAPTIOPISELX_6`"]
#[inline]
pub fn is_captiopiselx_6(&self) -> bool {
*self == CAPTIOPISELXR::CAPTIOPISELX_6
}
#[doc = "Checks if the value of the field is `CAPTIOPISELX_7`"]
#[inline]
pub fn is_captiopiselx_7(&self) -> bool {
*self == CAPTIOPISELXR::CAPTIOPISELX_7
}
}
#[doc = "Possible values of the field `CAPTIOPOSELx`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CAPTIOPOSELXR {
#[doc = "Px = PJ"]
CAPTIOPOSELX_0,
#[doc = "Px = P1"]
CAPTIOPOSELX_1,
#[doc = "Px = P2"]
CAPTIOPOSELX_2,
#[doc = "Px = P3"]
CAPTIOPOSELX_3,
#[doc = "Px = P4"]
CAPTIOPOSELX_4,
#[doc = "Px = P5"]
CAPTIOPOSELX_5,
#[doc = "Px = P6"]
CAPTIOPOSELX_6,
#[doc = "Px = P7"]
CAPTIOPOSELX_7,
#[doc = "Px = P8"]
CAPTIOPOSELX_8,
#[doc = "Px = P9"]
CAPTIOPOSELX_9,
#[doc = "Px = P10"]
CAPTIOPOSELX_10,
#[doc = "Px = P11"]
CAPTIOPOSELX_11,
#[doc = "Px = P12"]
CAPTIOPOSELX_12,
#[doc = "Px = P13"]
CAPTIOPOSELX_13,
#[doc = "Px = P14"]
CAPTIOPOSELX_14,
#[doc = "Px = P15"]
CAPTIOPOSELX_15,
}
impl CAPTIOPOSELXR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
CAPTIOPOSELXR::CAPTIOPOSELX_0 => 0,
CAPTIOPOSELXR::CAPTIOPOSELX_1 => 1,
CAPTIOPOSELXR::CAPTIOPOSELX_2 => 2,
CAPTIOPOSELXR::CAPTIOPOSELX_3 => 3,
CAPTIOPOSELXR::CAPTIOPOSELX_4 => 4,
CAPTIOPOSELXR::CAPTIOPOSELX_5 => 5,
CAPTIOPOSELXR::CAPTIOPOSELX_6 => 6,
CAPTIOPOSELXR::CAPTIOPOSELX_7 => 7,
CAPTIOPOSELXR::CAPTIOPOSELX_8 => 8,
CAPTIOPOSELXR::CAPTIOPOSELX_9 => 9,
CAPTIOPOSELXR::CAPTIOPOSELX_10 => 10,
CAPTIOPOSELXR::CAPTIOPOSELX_11 => 11,
CAPTIOPOSELXR::CAPTIOPOSELX_12 => 12,
CAPTIOPOSELXR::CAPTIOPOSELX_13 => 13,
CAPTIOPOSELXR::CAPTIOPOSELX_14 => 14,
CAPTIOPOSELXR::CAPTIOPOSELX_15 => 15,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> CAPTIOPOSELXR {
match value {
0 => CAPTIOPOSELXR::CAPTIOPOSELX_0,
1 => CAPTIOPOSELXR::CAPTIOPOSELX_1,
2 => CAPTIOPOSELXR::CAPTIOPOSELX_2,
3 => CAPTIOPOSELXR::CAPTIOPOSELX_3,
4 => CAPTIOPOSELXR::CAPTIOPOSELX_4,
5 => CAPTIOPOSELXR::CAPTIOPOSELX_5,
6 => CAPTIOPOSELXR::CAPTIOPOSELX_6,
7 => CAPTIOPOSELXR::CAPTIOPOSELX_7,
8 => CAPTIOPOSELXR::CAPTIOPOSELX_8,
9 => CAPTIOPOSELXR::CAPTIOPOSELX_9,
10 => CAPTIOPOSELXR::CAPTIOPOSELX_10,
11 => CAPTIOPOSELXR::CAPTIOPOSELX_11,
12 => CAPTIOPOSELXR::CAPTIOPOSELX_12,
13 => CAPTIOPOSELXR::CAPTIOPOSELX_13,
14 => CAPTIOPOSELXR::CAPTIOPOSELX_14,
15 => CAPTIOPOSELXR::CAPTIOPOSELX_15,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_0`"]
#[inline]
pub fn is_captioposelx_0(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_0
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_1`"]
#[inline]
pub fn is_captioposelx_1(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_1
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_2`"]
#[inline]
pub fn is_captioposelx_2(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_2
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_3`"]
#[inline]
pub fn is_captioposelx_3(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_3
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_4`"]
#[inline]
pub fn is_captioposelx_4(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_4
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_5`"]
#[inline]
pub fn is_captioposelx_5(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_5
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_6`"]
#[inline]
pub fn is_captioposelx_6(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_6
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_7`"]
#[inline]
pub fn is_captioposelx_7(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_7
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_8`"]
#[inline]
pub fn is_captioposelx_8(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_8
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_9`"]
#[inline]
pub fn is_captioposelx_9(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_9
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_10`"]
#[inline]
pub fn is_captioposelx_10(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_10
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_11`"]
#[inline]
pub fn is_captioposelx_11(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_11
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_12`"]
#[inline]
pub fn is_captioposelx_12(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_12
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_13`"]
#[inline]
pub fn is_captioposelx_13(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_13
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_14`"]
#[inline]
pub fn is_captioposelx_14(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_14
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_15`"]
#[inline]
pub fn is_captioposelx_15(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_15
}
}
#[doc = "Possible values of the field `CAPTIOEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CAPTIOENR {
#[doc = "All Capacitive Touch IOs are disabled. Signal towards timers is 0."]
CAPTIOEN_0,
#[doc = "Selected Capacitive Touch IO is enabled"]
CAPTIOEN_1,
}
impl CAPTIOENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CAPTIOENR::CAPTIOEN_0 => false,
CAPTIOENR::CAPTIOEN_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CAPTIOENR {
match value {
false => CAPTIOENR::CAPTIOEN_0,
true => CAPTIOENR::CAPTIOEN_1,
}
}
#[doc = "Checks if the value of the field is `CAPTIOEN_0`"]
#[inline]
pub fn is_captioen_0(&self) -> bool {
*self == CAPTIOENR::CAPTIOEN_0
}
#[doc = "Checks if the value of the field is `CAPTIOEN_1`"]
#[inline]
pub fn is_captioen_1(&self) -> bool {
*self == CAPTIOENR::CAPTIOEN_1
}
}
#[doc = "Possible values of the field `CAPTIOSTATE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CAPTIOSTATER {
#[doc = "Curent state 0 or Capacitive Touch IO is disabled"]
CAPTIOSTATE_0,
#[doc = "Current state 1"]
CAPTIOSTATE_1,
}
impl CAPTIOSTATER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CAPTIOSTATER::CAPTIOSTATE_0 => false,
CAPTIOSTATER::CAPTIOSTATE_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CAPTIOSTATER {
match value {
false => CAPTIOSTATER::CAPTIOSTATE_0,
true => CAPTIOSTATER::CAPTIOSTATE_1,
}
}
#[doc = "Checks if the value of the field is `CAPTIOSTATE_0`"]
#[inline]
pub fn is_captiostate_0(&self) -> bool {
*self == CAPTIOSTATER::CAPTIOSTATE_0
}
#[doc = "Checks if the value of the field is `CAPTIOSTATE_1`"]
#[inline]
pub fn is_captiostate_1(&self) -> bool {
*self == CAPTIOSTATER::CAPTIOSTATE_1
}
}
#[doc = "Values that can be written to the field `CAPTIOPISELx`"]
pub enum CAPTIOPISELXW {
#[doc = "Px.0"]
CAPTIOPISELX_0,
#[doc = "Px.1"]
CAPTIOPISELX_1,
#[doc = "Px.2"]
CAPTIOPISELX_2,
#[doc = "Px.3"]
CAPTIOPISELX_3,
#[doc = "Px.4"]
CAPTIOPISELX_4,
#[doc = "Px.5"]
CAPTIOPISELX_5,
#[doc = "Px.6"]
CAPTIOPISELX_6,
#[doc = "Px.7"]
CAPTIOPISELX_7,
}
impl CAPTIOPISELXW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
CAPTIOPISELXW::CAPTIOPISELX_0 => 0,
CAPTIOPISELXW::CAPTIOPISELX_1 => 1,
CAPTIOPISELXW::CAPTIOPISELX_2 => 2,
CAPTIOPISELXW::CAPTIOPISELX_3 => 3,
CAPTIOPISELXW::CAPTIOPISELX_4 => 4,
CAPTIOPISELXW::CAPTIOPISELX_5 => 5,
CAPTIOPISELXW::CAPTIOPISELX_6 => 6,
CAPTIOPISELXW::CAPTIOPISELX_7 => 7,
}
}
}
#[doc = r" Proxy"]
pub struct _CAPTIOPISELXW<'a> {
w: &'a mut W,
}
impl<'a> _CAPTIOPISELXW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CAPTIOPISELXW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Px.0"]
#[inline]
pub fn captiopiselx_0(self) -> &'a mut W {
self.variant(CAPTIOPISELXW::CAPTIOPISELX_0)
}
#[doc = "Px.1"]
#[inline]
pub fn captiopiselx_1(self) -> &'a mut W {
self.variant(CAPTIOPISELXW::CAPTIOPISELX_1)
}
#[doc = "Px.2"]
#[inline]
pub fn captiopiselx_2(self) -> &'a mut W {
self.variant(CAPTIOPISELXW::CAPTIOPISELX_2)
}
#[doc = "Px.3"]
#[inline]
pub fn captiopiselx_3(self) -> &'a mut W {
self.variant(CAPTIOPISELXW::CAPTIOPISELX_3)
}
#[doc = "Px.4"]
#[inline]
pub fn captiopiselx_4(self) -> &'a mut W {
self.variant(CAPTIOPISELXW::CAPTIOPISELX_4)
}
#[doc = "Px.5"]
#[inline]
pub fn captiopiselx_5(self) -> &'a mut W {
self.variant(CAPTIOPISELXW::CAPTIOPISELX_5)
}
#[doc = "Px.6"]
#[inline]
pub fn captiopiselx_6(self) -> &'a mut W {
self.variant(CAPTIOPISELXW::CAPTIOPISELX_6)
}
#[doc = "Px.7"]
#[inline]
pub fn captiopiselx_7(self) -> &'a mut W {
self.variant(CAPTIOPISELXW::CAPTIOPISELX_7)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 7;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CAPTIOPOSELx`"]
pub enum CAPTIOPOSELXW {
#[doc = "Px = PJ"]
CAPTIOPOSELX_0,
#[doc = "Px = P1"]
CAPTIOPOSELX_1,
#[doc = "Px = P2"]
CAPTIOPOSELX_2,
#[doc = "Px = P3"]
CAPTIOPOSELX_3,
#[doc = "Px = P4"]
CAPTIOPOSELX_4,
#[doc = "Px = P5"]
CAPTIOPOSELX_5,
#[doc = "Px = P6"]
CAPTIOPOSELX_6,
#[doc = "Px = P7"]
CAPTIOPOSELX_7,
#[doc = "Px = P8"]
CAPTIOPOSELX_8,
#[doc = "Px = P9"]
CAPTIOPOSELX_9,
#[doc = "Px = P10"]
CAPTIOPOSELX_10,
#[doc = "Px = P11"]
CAPTIOPOSELX_11,
#[doc = "Px = P12"]
CAPTIOPOSELX_12,
#[doc = "Px = P13"]
CAPTIOPOSELX_13,
#[doc = "Px = P14"]
CAPTIOPOSELX_14,
#[doc = "Px = P15"]
CAPTIOPOSELX_15,
}
impl CAPTIOPOSELXW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
CAPTIOPOSELXW::CAPTIOPOSELX_0 => 0,
CAPTIOPOSELXW::CAPTIOPOSELX_1 => 1,
CAPTIOPOSELXW::CAPTIOPOSELX_2 => 2,
CAPTIOPOSELXW::CAPTIOPOSELX_3 => 3,
CAPTIOPOSELXW::CAPTIOPOSELX_4 => 4,
CAPTIOPOSELXW::CAPTIOPOSELX_5 => 5,
CAPTIOPOSELXW::CAPTIOPOSELX_6 => 6,
CAPTIOPOSELXW::CAPTIOPOSELX_7 => 7,
CAPTIOPOSELXW::CAPTIOPOSELX_8 => 8,
CAPTIOPOSELXW::CAPTIOPOSELX_9 => 9,
CAPTIOPOSELXW::CAPTIOPOSELX_10 => 10,
CAPTIOPOSELXW::CAPTIOPOSELX_11 => 11,
CAPTIOPOSELXW::CAPTIOPOSELX_12 => 12,
CAPTIOPOSELXW::CAPTIOPOSELX_13 => 13,
CAPTIOPOSELXW::CAPTIOPOSELX_14 => 14,
CAPTIOPOSELXW::CAPTIOPOSELX_15 => 15,
}
}
}
#[doc = r" Proxy"]
pub struct _CAPTIOPOSELXW<'a> {
w: &'a mut W,
}
impl<'a> _CAPTIOPOSELXW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CAPTIOPOSELXW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Px = PJ"]
#[inline]
pub fn captioposelx_0(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_0)
}
#[doc = "Px = P1"]
#[inline]
pub fn captioposelx_1(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_1)
}
#[doc = "Px = P2"]
#[inline]
pub fn captioposelx_2(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_2)
}
#[doc = "Px = P3"]
#[inline]
pub fn captioposelx_3(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_3)
}
#[doc = "Px = P4"]
#[inline]
pub fn captioposelx_4(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_4)
}
#[doc = "Px = P5"]
#[inline]
pub fn captioposelx_5(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_5)
}
#[doc = "Px = P6"]
#[inline]
pub fn captioposelx_6(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_6)
}
#[doc = "Px = P7"]
#[inline]
pub fn captioposelx_7(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_7)
}
#[doc = "Px = P8"]
#[inline]
pub fn captioposelx_8(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_8)
}
#[doc = "Px = P9"]
#[inline]
pub fn captioposelx_9(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_9)
}
#[doc = "Px = P10"]
#[inline]
pub fn captioposelx_10(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_10)
}
#[doc = "Px = P11"]
#[inline]
pub fn captioposelx_11(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_11)
}
#[doc = "Px = P12"]
#[inline]
pub fn captioposelx_12(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_12)
}
#[doc = "Px = P13"]
#[inline]
pub fn captioposelx_13(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_13)
}
#[doc = "Px = P14"]
#[inline]
pub fn captioposelx_14(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_14)
}
#[doc = "Px = P15"]
#[inline]
pub fn captioposelx_15(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_15)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CAPTIOEN`"]
pub enum CAPTIOENW {
#[doc = "All Capacitive Touch IOs are disabled. Signal towards timers is 0."]
CAPTIOEN_0,
#[doc = "Selected Capacitive Touch IO is enabled"]
CAPTIOEN_1,
}
impl CAPTIOENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CAPTIOENW::CAPTIOEN_0 => false,
CAPTIOENW::CAPTIOEN_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CAPTIOENW<'a> {
w: &'a mut W,
}
impl<'a> _CAPTIOENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CAPTIOENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "All Capacitive Touch IOs are disabled. Signal towards timers is 0."]
#[inline]
pub fn captioen_0(self) -> &'a mut W {
self.variant(CAPTIOENW::CAPTIOEN_0)
}
#[doc = "Selected Capacitive Touch IO is enabled"]
#[inline]
pub fn captioen_1(self) -> &'a mut W {
self.variant(CAPTIOENW::CAPTIOEN_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
#[doc = "Bits 1:3 - Capacitive Touch IO pin select"]
#[inline]
pub fn captiopiselx(&self) -> CAPTIOPISELXR {
CAPTIOPISELXR::_from({
const MASK: u8 = 7;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u16) as u8
})
}
#[doc = "Bits 4:7 - Capacitive Touch IO port select"]
#[inline]
pub fn captioposelx(&self) -> CAPTIOPOSELXR {
CAPTIOPOSELXR::_from({
const MASK: u8 = 15;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u16) as u8
})
}
#[doc = "Bit 8 - Capacitive Touch IO enable"]
#[inline]
pub fn captioen(&self) -> CAPTIOENR {
CAPTIOENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u16) != 0
})
}
#[doc = "Bit 9 - Capacitive Touch IO state"]
#[inline]
pub fn captiostate(&self) -> CAPTIOSTATER {
CAPTIOSTATER::_from({
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u16) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 1:3 - Capacitive Touch IO pin select"]
#[inline]
pub fn captiopiselx(&mut self) -> _CAPTIOPISELXW {
_CAPTIOPISELXW { w: self }
}
#[doc = "Bits 4:7 - Capacitive Touch IO port select"]
#[inline]
pub fn captioposelx(&mut self) -> _CAPTIOPOSELXW {
_CAPTIOPOSELXW { w: self }
}
#[doc = "Bit 8 - Capacitive Touch IO enable"]
#[inline]
pub fn captioen(&mut self) -> _CAPTIOENW {
_CAPTIOENW { w: self }
}
}

13
example-source/msp432p401r/src/captio1.rs Normal file
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@@ -0,0 +1,13 @@
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
_reserved0: [u8; 14usize],
#[doc = "0x0e - Capacitive Touch IO x Control Register"]
pub captiox_ctl: CAPTIOXCTL,
}
#[doc = "Capacitive Touch IO x Control Register"]
pub struct CAPTIOXCTL {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Capacitive Touch IO x Control Register"]
pub mod captiox_ctl;

783
example-source/msp432p401r/src/captio1/captiox_ctl.rs Normal file
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@@ -0,0 +1,783 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u16,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u16,
}
impl super::CAPTIOXCTL {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `CAPTIOPISELx`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CAPTIOPISELXR {
#[doc = "Px.0"]
CAPTIOPISELX_0,
#[doc = "Px.1"]
CAPTIOPISELX_1,
#[doc = "Px.2"]
CAPTIOPISELX_2,
#[doc = "Px.3"]
CAPTIOPISELX_3,
#[doc = "Px.4"]
CAPTIOPISELX_4,
#[doc = "Px.5"]
CAPTIOPISELX_5,
#[doc = "Px.6"]
CAPTIOPISELX_6,
#[doc = "Px.7"]
CAPTIOPISELX_7,
}
impl CAPTIOPISELXR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
CAPTIOPISELXR::CAPTIOPISELX_0 => 0,
CAPTIOPISELXR::CAPTIOPISELX_1 => 1,
CAPTIOPISELXR::CAPTIOPISELX_2 => 2,
CAPTIOPISELXR::CAPTIOPISELX_3 => 3,
CAPTIOPISELXR::CAPTIOPISELX_4 => 4,
CAPTIOPISELXR::CAPTIOPISELX_5 => 5,
CAPTIOPISELXR::CAPTIOPISELX_6 => 6,
CAPTIOPISELXR::CAPTIOPISELX_7 => 7,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> CAPTIOPISELXR {
match value {
0 => CAPTIOPISELXR::CAPTIOPISELX_0,
1 => CAPTIOPISELXR::CAPTIOPISELX_1,
2 => CAPTIOPISELXR::CAPTIOPISELX_2,
3 => CAPTIOPISELXR::CAPTIOPISELX_3,
4 => CAPTIOPISELXR::CAPTIOPISELX_4,
5 => CAPTIOPISELXR::CAPTIOPISELX_5,
6 => CAPTIOPISELXR::CAPTIOPISELX_6,
7 => CAPTIOPISELXR::CAPTIOPISELX_7,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CAPTIOPISELX_0`"]
#[inline]
pub fn is_captiopiselx_0(&self) -> bool {
*self == CAPTIOPISELXR::CAPTIOPISELX_0
}
#[doc = "Checks if the value of the field is `CAPTIOPISELX_1`"]
#[inline]
pub fn is_captiopiselx_1(&self) -> bool {
*self == CAPTIOPISELXR::CAPTIOPISELX_1
}
#[doc = "Checks if the value of the field is `CAPTIOPISELX_2`"]
#[inline]
pub fn is_captiopiselx_2(&self) -> bool {
*self == CAPTIOPISELXR::CAPTIOPISELX_2
}
#[doc = "Checks if the value of the field is `CAPTIOPISELX_3`"]
#[inline]
pub fn is_captiopiselx_3(&self) -> bool {
*self == CAPTIOPISELXR::CAPTIOPISELX_3
}
#[doc = "Checks if the value of the field is `CAPTIOPISELX_4`"]
#[inline]
pub fn is_captiopiselx_4(&self) -> bool {
*self == CAPTIOPISELXR::CAPTIOPISELX_4
}
#[doc = "Checks if the value of the field is `CAPTIOPISELX_5`"]
#[inline]
pub fn is_captiopiselx_5(&self) -> bool {
*self == CAPTIOPISELXR::CAPTIOPISELX_5
}
#[doc = "Checks if the value of the field is `CAPTIOPISELX_6`"]
#[inline]
pub fn is_captiopiselx_6(&self) -> bool {
*self == CAPTIOPISELXR::CAPTIOPISELX_6
}
#[doc = "Checks if the value of the field is `CAPTIOPISELX_7`"]
#[inline]
pub fn is_captiopiselx_7(&self) -> bool {
*self == CAPTIOPISELXR::CAPTIOPISELX_7
}
}
#[doc = "Possible values of the field `CAPTIOPOSELx`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CAPTIOPOSELXR {
#[doc = "Px = PJ"]
CAPTIOPOSELX_0,
#[doc = "Px = P1"]
CAPTIOPOSELX_1,
#[doc = "Px = P2"]
CAPTIOPOSELX_2,
#[doc = "Px = P3"]
CAPTIOPOSELX_3,
#[doc = "Px = P4"]
CAPTIOPOSELX_4,
#[doc = "Px = P5"]
CAPTIOPOSELX_5,
#[doc = "Px = P6"]
CAPTIOPOSELX_6,
#[doc = "Px = P7"]
CAPTIOPOSELX_7,
#[doc = "Px = P8"]
CAPTIOPOSELX_8,
#[doc = "Px = P9"]
CAPTIOPOSELX_9,
#[doc = "Px = P10"]
CAPTIOPOSELX_10,
#[doc = "Px = P11"]
CAPTIOPOSELX_11,
#[doc = "Px = P12"]
CAPTIOPOSELX_12,
#[doc = "Px = P13"]
CAPTIOPOSELX_13,
#[doc = "Px = P14"]
CAPTIOPOSELX_14,
#[doc = "Px = P15"]
CAPTIOPOSELX_15,
}
impl CAPTIOPOSELXR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
CAPTIOPOSELXR::CAPTIOPOSELX_0 => 0,
CAPTIOPOSELXR::CAPTIOPOSELX_1 => 1,
CAPTIOPOSELXR::CAPTIOPOSELX_2 => 2,
CAPTIOPOSELXR::CAPTIOPOSELX_3 => 3,
CAPTIOPOSELXR::CAPTIOPOSELX_4 => 4,
CAPTIOPOSELXR::CAPTIOPOSELX_5 => 5,
CAPTIOPOSELXR::CAPTIOPOSELX_6 => 6,
CAPTIOPOSELXR::CAPTIOPOSELX_7 => 7,
CAPTIOPOSELXR::CAPTIOPOSELX_8 => 8,
CAPTIOPOSELXR::CAPTIOPOSELX_9 => 9,
CAPTIOPOSELXR::CAPTIOPOSELX_10 => 10,
CAPTIOPOSELXR::CAPTIOPOSELX_11 => 11,
CAPTIOPOSELXR::CAPTIOPOSELX_12 => 12,
CAPTIOPOSELXR::CAPTIOPOSELX_13 => 13,
CAPTIOPOSELXR::CAPTIOPOSELX_14 => 14,
CAPTIOPOSELXR::CAPTIOPOSELX_15 => 15,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> CAPTIOPOSELXR {
match value {
0 => CAPTIOPOSELXR::CAPTIOPOSELX_0,
1 => CAPTIOPOSELXR::CAPTIOPOSELX_1,
2 => CAPTIOPOSELXR::CAPTIOPOSELX_2,
3 => CAPTIOPOSELXR::CAPTIOPOSELX_3,
4 => CAPTIOPOSELXR::CAPTIOPOSELX_4,
5 => CAPTIOPOSELXR::CAPTIOPOSELX_5,
6 => CAPTIOPOSELXR::CAPTIOPOSELX_6,
7 => CAPTIOPOSELXR::CAPTIOPOSELX_7,
8 => CAPTIOPOSELXR::CAPTIOPOSELX_8,
9 => CAPTIOPOSELXR::CAPTIOPOSELX_9,
10 => CAPTIOPOSELXR::CAPTIOPOSELX_10,
11 => CAPTIOPOSELXR::CAPTIOPOSELX_11,
12 => CAPTIOPOSELXR::CAPTIOPOSELX_12,
13 => CAPTIOPOSELXR::CAPTIOPOSELX_13,
14 => CAPTIOPOSELXR::CAPTIOPOSELX_14,
15 => CAPTIOPOSELXR::CAPTIOPOSELX_15,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_0`"]
#[inline]
pub fn is_captioposelx_0(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_0
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_1`"]
#[inline]
pub fn is_captioposelx_1(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_1
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_2`"]
#[inline]
pub fn is_captioposelx_2(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_2
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_3`"]
#[inline]
pub fn is_captioposelx_3(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_3
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_4`"]
#[inline]
pub fn is_captioposelx_4(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_4
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_5`"]
#[inline]
pub fn is_captioposelx_5(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_5
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_6`"]
#[inline]
pub fn is_captioposelx_6(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_6
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_7`"]
#[inline]
pub fn is_captioposelx_7(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_7
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_8`"]
#[inline]
pub fn is_captioposelx_8(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_8
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_9`"]
#[inline]
pub fn is_captioposelx_9(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_9
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_10`"]
#[inline]
pub fn is_captioposelx_10(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_10
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_11`"]
#[inline]
pub fn is_captioposelx_11(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_11
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_12`"]
#[inline]
pub fn is_captioposelx_12(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_12
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_13`"]
#[inline]
pub fn is_captioposelx_13(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_13
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_14`"]
#[inline]
pub fn is_captioposelx_14(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_14
}
#[doc = "Checks if the value of the field is `CAPTIOPOSELX_15`"]
#[inline]
pub fn is_captioposelx_15(&self) -> bool {
*self == CAPTIOPOSELXR::CAPTIOPOSELX_15
}
}
#[doc = "Possible values of the field `CAPTIOEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CAPTIOENR {
#[doc = "All Capacitive Touch IOs are disabled. Signal towards timers is 0."]
CAPTIOEN_0,
#[doc = "Selected Capacitive Touch IO is enabled"]
CAPTIOEN_1,
}
impl CAPTIOENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CAPTIOENR::CAPTIOEN_0 => false,
CAPTIOENR::CAPTIOEN_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CAPTIOENR {
match value {
false => CAPTIOENR::CAPTIOEN_0,
true => CAPTIOENR::CAPTIOEN_1,
}
}
#[doc = "Checks if the value of the field is `CAPTIOEN_0`"]
#[inline]
pub fn is_captioen_0(&self) -> bool {
*self == CAPTIOENR::CAPTIOEN_0
}
#[doc = "Checks if the value of the field is `CAPTIOEN_1`"]
#[inline]
pub fn is_captioen_1(&self) -> bool {
*self == CAPTIOENR::CAPTIOEN_1
}
}
#[doc = "Possible values of the field `CAPTIOSTATE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CAPTIOSTATER {
#[doc = "Curent state 0 or Capacitive Touch IO is disabled"]
CAPTIOSTATE_0,
#[doc = "Current state 1"]
CAPTIOSTATE_1,
}
impl CAPTIOSTATER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CAPTIOSTATER::CAPTIOSTATE_0 => false,
CAPTIOSTATER::CAPTIOSTATE_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CAPTIOSTATER {
match value {
false => CAPTIOSTATER::CAPTIOSTATE_0,
true => CAPTIOSTATER::CAPTIOSTATE_1,
}
}
#[doc = "Checks if the value of the field is `CAPTIOSTATE_0`"]
#[inline]
pub fn is_captiostate_0(&self) -> bool {
*self == CAPTIOSTATER::CAPTIOSTATE_0
}
#[doc = "Checks if the value of the field is `CAPTIOSTATE_1`"]
#[inline]
pub fn is_captiostate_1(&self) -> bool {
*self == CAPTIOSTATER::CAPTIOSTATE_1
}
}
#[doc = "Values that can be written to the field `CAPTIOPISELx`"]
pub enum CAPTIOPISELXW {
#[doc = "Px.0"]
CAPTIOPISELX_0,
#[doc = "Px.1"]
CAPTIOPISELX_1,
#[doc = "Px.2"]
CAPTIOPISELX_2,
#[doc = "Px.3"]
CAPTIOPISELX_3,
#[doc = "Px.4"]
CAPTIOPISELX_4,
#[doc = "Px.5"]
CAPTIOPISELX_5,
#[doc = "Px.6"]
CAPTIOPISELX_6,
#[doc = "Px.7"]
CAPTIOPISELX_7,
}
impl CAPTIOPISELXW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
CAPTIOPISELXW::CAPTIOPISELX_0 => 0,
CAPTIOPISELXW::CAPTIOPISELX_1 => 1,
CAPTIOPISELXW::CAPTIOPISELX_2 => 2,
CAPTIOPISELXW::CAPTIOPISELX_3 => 3,
CAPTIOPISELXW::CAPTIOPISELX_4 => 4,
CAPTIOPISELXW::CAPTIOPISELX_5 => 5,
CAPTIOPISELXW::CAPTIOPISELX_6 => 6,
CAPTIOPISELXW::CAPTIOPISELX_7 => 7,
}
}
}
#[doc = r" Proxy"]
pub struct _CAPTIOPISELXW<'a> {
w: &'a mut W,
}
impl<'a> _CAPTIOPISELXW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CAPTIOPISELXW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Px.0"]
#[inline]
pub fn captiopiselx_0(self) -> &'a mut W {
self.variant(CAPTIOPISELXW::CAPTIOPISELX_0)
}
#[doc = "Px.1"]
#[inline]
pub fn captiopiselx_1(self) -> &'a mut W {
self.variant(CAPTIOPISELXW::CAPTIOPISELX_1)
}
#[doc = "Px.2"]
#[inline]
pub fn captiopiselx_2(self) -> &'a mut W {
self.variant(CAPTIOPISELXW::CAPTIOPISELX_2)
}
#[doc = "Px.3"]
#[inline]
pub fn captiopiselx_3(self) -> &'a mut W {
self.variant(CAPTIOPISELXW::CAPTIOPISELX_3)
}
#[doc = "Px.4"]
#[inline]
pub fn captiopiselx_4(self) -> &'a mut W {
self.variant(CAPTIOPISELXW::CAPTIOPISELX_4)
}
#[doc = "Px.5"]
#[inline]
pub fn captiopiselx_5(self) -> &'a mut W {
self.variant(CAPTIOPISELXW::CAPTIOPISELX_5)
}
#[doc = "Px.6"]
#[inline]
pub fn captiopiselx_6(self) -> &'a mut W {
self.variant(CAPTIOPISELXW::CAPTIOPISELX_6)
}
#[doc = "Px.7"]
#[inline]
pub fn captiopiselx_7(self) -> &'a mut W {
self.variant(CAPTIOPISELXW::CAPTIOPISELX_7)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 7;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CAPTIOPOSELx`"]
pub enum CAPTIOPOSELXW {
#[doc = "Px = PJ"]
CAPTIOPOSELX_0,
#[doc = "Px = P1"]
CAPTIOPOSELX_1,
#[doc = "Px = P2"]
CAPTIOPOSELX_2,
#[doc = "Px = P3"]
CAPTIOPOSELX_3,
#[doc = "Px = P4"]
CAPTIOPOSELX_4,
#[doc = "Px = P5"]
CAPTIOPOSELX_5,
#[doc = "Px = P6"]
CAPTIOPOSELX_6,
#[doc = "Px = P7"]
CAPTIOPOSELX_7,
#[doc = "Px = P8"]
CAPTIOPOSELX_8,
#[doc = "Px = P9"]
CAPTIOPOSELX_9,
#[doc = "Px = P10"]
CAPTIOPOSELX_10,
#[doc = "Px = P11"]
CAPTIOPOSELX_11,
#[doc = "Px = P12"]
CAPTIOPOSELX_12,
#[doc = "Px = P13"]
CAPTIOPOSELX_13,
#[doc = "Px = P14"]
CAPTIOPOSELX_14,
#[doc = "Px = P15"]
CAPTIOPOSELX_15,
}
impl CAPTIOPOSELXW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
CAPTIOPOSELXW::CAPTIOPOSELX_0 => 0,
CAPTIOPOSELXW::CAPTIOPOSELX_1 => 1,
CAPTIOPOSELXW::CAPTIOPOSELX_2 => 2,
CAPTIOPOSELXW::CAPTIOPOSELX_3 => 3,
CAPTIOPOSELXW::CAPTIOPOSELX_4 => 4,
CAPTIOPOSELXW::CAPTIOPOSELX_5 => 5,
CAPTIOPOSELXW::CAPTIOPOSELX_6 => 6,
CAPTIOPOSELXW::CAPTIOPOSELX_7 => 7,
CAPTIOPOSELXW::CAPTIOPOSELX_8 => 8,
CAPTIOPOSELXW::CAPTIOPOSELX_9 => 9,
CAPTIOPOSELXW::CAPTIOPOSELX_10 => 10,
CAPTIOPOSELXW::CAPTIOPOSELX_11 => 11,
CAPTIOPOSELXW::CAPTIOPOSELX_12 => 12,
CAPTIOPOSELXW::CAPTIOPOSELX_13 => 13,
CAPTIOPOSELXW::CAPTIOPOSELX_14 => 14,
CAPTIOPOSELXW::CAPTIOPOSELX_15 => 15,
}
}
}
#[doc = r" Proxy"]
pub struct _CAPTIOPOSELXW<'a> {
w: &'a mut W,
}
impl<'a> _CAPTIOPOSELXW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CAPTIOPOSELXW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Px = PJ"]
#[inline]
pub fn captioposelx_0(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_0)
}
#[doc = "Px = P1"]
#[inline]
pub fn captioposelx_1(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_1)
}
#[doc = "Px = P2"]
#[inline]
pub fn captioposelx_2(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_2)
}
#[doc = "Px = P3"]
#[inline]
pub fn captioposelx_3(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_3)
}
#[doc = "Px = P4"]
#[inline]
pub fn captioposelx_4(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_4)
}
#[doc = "Px = P5"]
#[inline]
pub fn captioposelx_5(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_5)
}
#[doc = "Px = P6"]
#[inline]
pub fn captioposelx_6(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_6)
}
#[doc = "Px = P7"]
#[inline]
pub fn captioposelx_7(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_7)
}
#[doc = "Px = P8"]
#[inline]
pub fn captioposelx_8(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_8)
}
#[doc = "Px = P9"]
#[inline]
pub fn captioposelx_9(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_9)
}
#[doc = "Px = P10"]
#[inline]
pub fn captioposelx_10(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_10)
}
#[doc = "Px = P11"]
#[inline]
pub fn captioposelx_11(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_11)
}
#[doc = "Px = P12"]
#[inline]
pub fn captioposelx_12(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_12)
}
#[doc = "Px = P13"]
#[inline]
pub fn captioposelx_13(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_13)
}
#[doc = "Px = P14"]
#[inline]
pub fn captioposelx_14(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_14)
}
#[doc = "Px = P15"]
#[inline]
pub fn captioposelx_15(self) -> &'a mut W {
self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_15)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CAPTIOEN`"]
pub enum CAPTIOENW {
#[doc = "All Capacitive Touch IOs are disabled. Signal towards timers is 0."]
CAPTIOEN_0,
#[doc = "Selected Capacitive Touch IO is enabled"]
CAPTIOEN_1,
}
impl CAPTIOENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CAPTIOENW::CAPTIOEN_0 => false,
CAPTIOENW::CAPTIOEN_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CAPTIOENW<'a> {
w: &'a mut W,
}
impl<'a> _CAPTIOENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CAPTIOENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "All Capacitive Touch IOs are disabled. Signal towards timers is 0."]
#[inline]
pub fn captioen_0(self) -> &'a mut W {
self.variant(CAPTIOENW::CAPTIOEN_0)
}
#[doc = "Selected Capacitive Touch IO is enabled"]
#[inline]
pub fn captioen_1(self) -> &'a mut W {
self.variant(CAPTIOENW::CAPTIOEN_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
#[doc = "Bits 1:3 - Capacitive Touch IO pin select"]
#[inline]
pub fn captiopiselx(&self) -> CAPTIOPISELXR {
CAPTIOPISELXR::_from({
const MASK: u8 = 7;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u16) as u8
})
}
#[doc = "Bits 4:7 - Capacitive Touch IO port select"]
#[inline]
pub fn captioposelx(&self) -> CAPTIOPOSELXR {
CAPTIOPOSELXR::_from({
const MASK: u8 = 15;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u16) as u8
})
}
#[doc = "Bit 8 - Capacitive Touch IO enable"]
#[inline]
pub fn captioen(&self) -> CAPTIOENR {
CAPTIOENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u16) != 0
})
}
#[doc = "Bit 9 - Capacitive Touch IO state"]
#[inline]
pub fn captiostate(&self) -> CAPTIOSTATER {
CAPTIOSTATER::_from({
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u16) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 1:3 - Capacitive Touch IO pin select"]
#[inline]
pub fn captiopiselx(&mut self) -> _CAPTIOPISELXW {
_CAPTIOPISELXW { w: self }
}
#[doc = "Bits 4:7 - Capacitive Touch IO port select"]
#[inline]
pub fn captioposelx(&mut self) -> _CAPTIOPOSELXW {
_CAPTIOPOSELXW { w: self }
}
#[doc = "Bit 8 - Capacitive Touch IO enable"]
#[inline]
pub fn captioen(&mut self) -> _CAPTIOENW {
_CAPTIOENW { w: self }
}
}

53
example-source/msp432p401r/src/comp_e0.rs Normal file
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@@ -0,0 +1,53 @@
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Comparator Control Register 0"]
pub cex_ctl0: CEXCTL0,
#[doc = "0x02 - Comparator Control Register 1"]
pub cex_ctl1: CEXCTL1,
#[doc = "0x04 - Comparator Control Register 2"]
pub cex_ctl2: CEXCTL2,
#[doc = "0x06 - Comparator Control Register 3"]
pub cex_ctl3: CEXCTL3,
_reserved0: [u8; 4usize],
#[doc = "0x0c - Comparator Interrupt Control Register"]
pub cex_int: CEXINT,
#[doc = "0x0e - Comparator Interrupt Vector Word Register"]
pub cex_iv: CEXIV,
}
#[doc = "Comparator Control Register 0"]
pub struct CEXCTL0 {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Comparator Control Register 0"]
pub mod cex_ctl0;
#[doc = "Comparator Control Register 1"]
pub struct CEXCTL1 {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Comparator Control Register 1"]
pub mod cex_ctl1;
#[doc = "Comparator Control Register 2"]
pub struct CEXCTL2 {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Comparator Control Register 2"]
pub mod cex_ctl2;
#[doc = "Comparator Control Register 3"]
pub struct CEXCTL3 {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Comparator Control Register 3"]
pub mod cex_ctl3;
#[doc = "Comparator Interrupt Control Register"]
pub struct CEXINT {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Comparator Interrupt Control Register"]
pub mod cex_int;
#[doc = "Comparator Interrupt Vector Word Register"]
pub struct CEXIV {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Comparator Interrupt Vector Word Register"]
pub mod cex_iv;

982
example-source/msp432p401r/src/comp_e0/cex_ctl0.rs Normal file
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@@ -0,0 +1,982 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u16,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u16,
}
impl super::CEXCTL0 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `CEIPSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CEIPSELR {
#[doc = "Channel 0 selected"]
CEIPSEL_0,
#[doc = "Channel 1 selected"]
CEIPSEL_1,
#[doc = "Channel 2 selected"]
CEIPSEL_2,
#[doc = "Channel 3 selected"]
CEIPSEL_3,
#[doc = "Channel 4 selected"]
CEIPSEL_4,
#[doc = "Channel 5 selected"]
CEIPSEL_5,
#[doc = "Channel 6 selected"]
CEIPSEL_6,
#[doc = "Channel 7 selected"]
CEIPSEL_7,
#[doc = "Channel 8 selected"]
CEIPSEL_8,
#[doc = "Channel 9 selected"]
CEIPSEL_9,
#[doc = "Channel 10 selected"]
CEIPSEL_10,
#[doc = "Channel 11 selected"]
CEIPSEL_11,
#[doc = "Channel 12 selected"]
CEIPSEL_12,
#[doc = "Channel 13 selected"]
CEIPSEL_13,
#[doc = "Channel 14 selected"]
CEIPSEL_14,
#[doc = "Channel 15 selected"]
CEIPSEL_15,
}
impl CEIPSELR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
CEIPSELR::CEIPSEL_0 => 0,
CEIPSELR::CEIPSEL_1 => 1,
CEIPSELR::CEIPSEL_2 => 2,
CEIPSELR::CEIPSEL_3 => 3,
CEIPSELR::CEIPSEL_4 => 4,
CEIPSELR::CEIPSEL_5 => 5,
CEIPSELR::CEIPSEL_6 => 6,
CEIPSELR::CEIPSEL_7 => 7,
CEIPSELR::CEIPSEL_8 => 8,
CEIPSELR::CEIPSEL_9 => 9,
CEIPSELR::CEIPSEL_10 => 10,
CEIPSELR::CEIPSEL_11 => 11,
CEIPSELR::CEIPSEL_12 => 12,
CEIPSELR::CEIPSEL_13 => 13,
CEIPSELR::CEIPSEL_14 => 14,
CEIPSELR::CEIPSEL_15 => 15,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> CEIPSELR {
match value {
0 => CEIPSELR::CEIPSEL_0,
1 => CEIPSELR::CEIPSEL_1,
2 => CEIPSELR::CEIPSEL_2,
3 => CEIPSELR::CEIPSEL_3,
4 => CEIPSELR::CEIPSEL_4,
5 => CEIPSELR::CEIPSEL_5,
6 => CEIPSELR::CEIPSEL_6,
7 => CEIPSELR::CEIPSEL_7,
8 => CEIPSELR::CEIPSEL_8,
9 => CEIPSELR::CEIPSEL_9,
10 => CEIPSELR::CEIPSEL_10,
11 => CEIPSELR::CEIPSEL_11,
12 => CEIPSELR::CEIPSEL_12,
13 => CEIPSELR::CEIPSEL_13,
14 => CEIPSELR::CEIPSEL_14,
15 => CEIPSELR::CEIPSEL_15,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CEIPSEL_0`"]
#[inline]
pub fn is_ceipsel_0(&self) -> bool {
*self == CEIPSELR::CEIPSEL_0
}
#[doc = "Checks if the value of the field is `CEIPSEL_1`"]
#[inline]
pub fn is_ceipsel_1(&self) -> bool {
*self == CEIPSELR::CEIPSEL_1
}
#[doc = "Checks if the value of the field is `CEIPSEL_2`"]
#[inline]
pub fn is_ceipsel_2(&self) -> bool {
*self == CEIPSELR::CEIPSEL_2
}
#[doc = "Checks if the value of the field is `CEIPSEL_3`"]
#[inline]
pub fn is_ceipsel_3(&self) -> bool {
*self == CEIPSELR::CEIPSEL_3
}
#[doc = "Checks if the value of the field is `CEIPSEL_4`"]
#[inline]
pub fn is_ceipsel_4(&self) -> bool {
*self == CEIPSELR::CEIPSEL_4
}
#[doc = "Checks if the value of the field is `CEIPSEL_5`"]
#[inline]
pub fn is_ceipsel_5(&self) -> bool {
*self == CEIPSELR::CEIPSEL_5
}
#[doc = "Checks if the value of the field is `CEIPSEL_6`"]
#[inline]
pub fn is_ceipsel_6(&self) -> bool {
*self == CEIPSELR::CEIPSEL_6
}
#[doc = "Checks if the value of the field is `CEIPSEL_7`"]
#[inline]
pub fn is_ceipsel_7(&self) -> bool {
*self == CEIPSELR::CEIPSEL_7
}
#[doc = "Checks if the value of the field is `CEIPSEL_8`"]
#[inline]
pub fn is_ceipsel_8(&self) -> bool {
*self == CEIPSELR::CEIPSEL_8
}
#[doc = "Checks if the value of the field is `CEIPSEL_9`"]
#[inline]
pub fn is_ceipsel_9(&self) -> bool {
*self == CEIPSELR::CEIPSEL_9
}
#[doc = "Checks if the value of the field is `CEIPSEL_10`"]
#[inline]
pub fn is_ceipsel_10(&self) -> bool {
*self == CEIPSELR::CEIPSEL_10
}
#[doc = "Checks if the value of the field is `CEIPSEL_11`"]
#[inline]
pub fn is_ceipsel_11(&self) -> bool {
*self == CEIPSELR::CEIPSEL_11
}
#[doc = "Checks if the value of the field is `CEIPSEL_12`"]
#[inline]
pub fn is_ceipsel_12(&self) -> bool {
*self == CEIPSELR::CEIPSEL_12
}
#[doc = "Checks if the value of the field is `CEIPSEL_13`"]
#[inline]
pub fn is_ceipsel_13(&self) -> bool {
*self == CEIPSELR::CEIPSEL_13
}
#[doc = "Checks if the value of the field is `CEIPSEL_14`"]
#[inline]
pub fn is_ceipsel_14(&self) -> bool {
*self == CEIPSELR::CEIPSEL_14
}
#[doc = "Checks if the value of the field is `CEIPSEL_15`"]
#[inline]
pub fn is_ceipsel_15(&self) -> bool {
*self == CEIPSELR::CEIPSEL_15
}
}
#[doc = "Possible values of the field `CEIPEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CEIPENR {
#[doc = "Selected analog input channel for V+ terminal is disabled"]
CEIPEN_0,
#[doc = "Selected analog input channel for V+ terminal is enabled"]
CEIPEN_1,
}
impl CEIPENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CEIPENR::CEIPEN_0 => false,
CEIPENR::CEIPEN_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CEIPENR {
match value {
false => CEIPENR::CEIPEN_0,
true => CEIPENR::CEIPEN_1,
}
}
#[doc = "Checks if the value of the field is `CEIPEN_0`"]
#[inline]
pub fn is_ceipen_0(&self) -> bool {
*self == CEIPENR::CEIPEN_0
}
#[doc = "Checks if the value of the field is `CEIPEN_1`"]
#[inline]
pub fn is_ceipen_1(&self) -> bool {
*self == CEIPENR::CEIPEN_1
}
}
#[doc = "Possible values of the field `CEIMSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CEIMSELR {
#[doc = "Channel 0 selected"]
CEIMSEL_0,
#[doc = "Channel 1 selected"]
CEIMSEL_1,
#[doc = "Channel 2 selected"]
CEIMSEL_2,
#[doc = "Channel 3 selected"]
CEIMSEL_3,
#[doc = "Channel 4 selected"]
CEIMSEL_4,
#[doc = "Channel 5 selected"]
CEIMSEL_5,
#[doc = "Channel 6 selected"]
CEIMSEL_6,
#[doc = "Channel 7 selected"]
CEIMSEL_7,
#[doc = "Channel 8 selected"]
CEIMSEL_8,
#[doc = "Channel 9 selected"]
CEIMSEL_9,
#[doc = "Channel 10 selected"]
CEIMSEL_10,
#[doc = "Channel 11 selected"]
CEIMSEL_11,
#[doc = "Channel 12 selected"]
CEIMSEL_12,
#[doc = "Channel 13 selected"]
CEIMSEL_13,
#[doc = "Channel 14 selected"]
CEIMSEL_14,
#[doc = "Channel 15 selected"]
CEIMSEL_15,
}
impl CEIMSELR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
CEIMSELR::CEIMSEL_0 => 0,
CEIMSELR::CEIMSEL_1 => 1,
CEIMSELR::CEIMSEL_2 => 2,
CEIMSELR::CEIMSEL_3 => 3,
CEIMSELR::CEIMSEL_4 => 4,
CEIMSELR::CEIMSEL_5 => 5,
CEIMSELR::CEIMSEL_6 => 6,
CEIMSELR::CEIMSEL_7 => 7,
CEIMSELR::CEIMSEL_8 => 8,
CEIMSELR::CEIMSEL_9 => 9,
CEIMSELR::CEIMSEL_10 => 10,
CEIMSELR::CEIMSEL_11 => 11,
CEIMSELR::CEIMSEL_12 => 12,
CEIMSELR::CEIMSEL_13 => 13,
CEIMSELR::CEIMSEL_14 => 14,
CEIMSELR::CEIMSEL_15 => 15,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> CEIMSELR {
match value {
0 => CEIMSELR::CEIMSEL_0,
1 => CEIMSELR::CEIMSEL_1,
2 => CEIMSELR::CEIMSEL_2,
3 => CEIMSELR::CEIMSEL_3,
4 => CEIMSELR::CEIMSEL_4,
5 => CEIMSELR::CEIMSEL_5,
6 => CEIMSELR::CEIMSEL_6,
7 => CEIMSELR::CEIMSEL_7,
8 => CEIMSELR::CEIMSEL_8,
9 => CEIMSELR::CEIMSEL_9,
10 => CEIMSELR::CEIMSEL_10,
11 => CEIMSELR::CEIMSEL_11,
12 => CEIMSELR::CEIMSEL_12,
13 => CEIMSELR::CEIMSEL_13,
14 => CEIMSELR::CEIMSEL_14,
15 => CEIMSELR::CEIMSEL_15,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CEIMSEL_0`"]
#[inline]
pub fn is_ceimsel_0(&self) -> bool {
*self == CEIMSELR::CEIMSEL_0
}
#[doc = "Checks if the value of the field is `CEIMSEL_1`"]
#[inline]
pub fn is_ceimsel_1(&self) -> bool {
*self == CEIMSELR::CEIMSEL_1
}
#[doc = "Checks if the value of the field is `CEIMSEL_2`"]
#[inline]
pub fn is_ceimsel_2(&self) -> bool {
*self == CEIMSELR::CEIMSEL_2
}
#[doc = "Checks if the value of the field is `CEIMSEL_3`"]
#[inline]
pub fn is_ceimsel_3(&self) -> bool {
*self == CEIMSELR::CEIMSEL_3
}
#[doc = "Checks if the value of the field is `CEIMSEL_4`"]
#[inline]
pub fn is_ceimsel_4(&self) -> bool {
*self == CEIMSELR::CEIMSEL_4
}
#[doc = "Checks if the value of the field is `CEIMSEL_5`"]
#[inline]
pub fn is_ceimsel_5(&self) -> bool {
*self == CEIMSELR::CEIMSEL_5
}
#[doc = "Checks if the value of the field is `CEIMSEL_6`"]
#[inline]
pub fn is_ceimsel_6(&self) -> bool {
*self == CEIMSELR::CEIMSEL_6
}
#[doc = "Checks if the value of the field is `CEIMSEL_7`"]
#[inline]
pub fn is_ceimsel_7(&self) -> bool {
*self == CEIMSELR::CEIMSEL_7
}
#[doc = "Checks if the value of the field is `CEIMSEL_8`"]
#[inline]
pub fn is_ceimsel_8(&self) -> bool {
*self == CEIMSELR::CEIMSEL_8
}
#[doc = "Checks if the value of the field is `CEIMSEL_9`"]
#[inline]
pub fn is_ceimsel_9(&self) -> bool {
*self == CEIMSELR::CEIMSEL_9
}
#[doc = "Checks if the value of the field is `CEIMSEL_10`"]
#[inline]
pub fn is_ceimsel_10(&self) -> bool {
*self == CEIMSELR::CEIMSEL_10
}
#[doc = "Checks if the value of the field is `CEIMSEL_11`"]
#[inline]
pub fn is_ceimsel_11(&self) -> bool {
*self == CEIMSELR::CEIMSEL_11
}
#[doc = "Checks if the value of the field is `CEIMSEL_12`"]
#[inline]
pub fn is_ceimsel_12(&self) -> bool {
*self == CEIMSELR::CEIMSEL_12
}
#[doc = "Checks if the value of the field is `CEIMSEL_13`"]
#[inline]
pub fn is_ceimsel_13(&self) -> bool {
*self == CEIMSELR::CEIMSEL_13
}
#[doc = "Checks if the value of the field is `CEIMSEL_14`"]
#[inline]
pub fn is_ceimsel_14(&self) -> bool {
*self == CEIMSELR::CEIMSEL_14
}
#[doc = "Checks if the value of the field is `CEIMSEL_15`"]
#[inline]
pub fn is_ceimsel_15(&self) -> bool {
*self == CEIMSELR::CEIMSEL_15
}
}
#[doc = "Possible values of the field `CEIMEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CEIMENR {
#[doc = "Selected analog input channel for V- terminal is disabled"]
CEIMEN_0,
#[doc = "Selected analog input channel for V- terminal is enabled"]
CEIMEN_1,
}
impl CEIMENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CEIMENR::CEIMEN_0 => false,
CEIMENR::CEIMEN_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CEIMENR {
match value {
false => CEIMENR::CEIMEN_0,
true => CEIMENR::CEIMEN_1,
}
}
#[doc = "Checks if the value of the field is `CEIMEN_0`"]
#[inline]
pub fn is_ceimen_0(&self) -> bool {
*self == CEIMENR::CEIMEN_0
}
#[doc = "Checks if the value of the field is `CEIMEN_1`"]
#[inline]
pub fn is_ceimen_1(&self) -> bool {
*self == CEIMENR::CEIMEN_1
}
}
#[doc = "Values that can be written to the field `CEIPSEL`"]
pub enum CEIPSELW {
#[doc = "Channel 0 selected"]
CEIPSEL_0,
#[doc = "Channel 1 selected"]
CEIPSEL_1,
#[doc = "Channel 2 selected"]
CEIPSEL_2,
#[doc = "Channel 3 selected"]
CEIPSEL_3,
#[doc = "Channel 4 selected"]
CEIPSEL_4,
#[doc = "Channel 5 selected"]
CEIPSEL_5,
#[doc = "Channel 6 selected"]
CEIPSEL_6,
#[doc = "Channel 7 selected"]
CEIPSEL_7,
#[doc = "Channel 8 selected"]
CEIPSEL_8,
#[doc = "Channel 9 selected"]
CEIPSEL_9,
#[doc = "Channel 10 selected"]
CEIPSEL_10,
#[doc = "Channel 11 selected"]
CEIPSEL_11,
#[doc = "Channel 12 selected"]
CEIPSEL_12,
#[doc = "Channel 13 selected"]
CEIPSEL_13,
#[doc = "Channel 14 selected"]
CEIPSEL_14,
#[doc = "Channel 15 selected"]
CEIPSEL_15,
}
impl CEIPSELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
CEIPSELW::CEIPSEL_0 => 0,
CEIPSELW::CEIPSEL_1 => 1,
CEIPSELW::CEIPSEL_2 => 2,
CEIPSELW::CEIPSEL_3 => 3,
CEIPSELW::CEIPSEL_4 => 4,
CEIPSELW::CEIPSEL_5 => 5,
CEIPSELW::CEIPSEL_6 => 6,
CEIPSELW::CEIPSEL_7 => 7,
CEIPSELW::CEIPSEL_8 => 8,
CEIPSELW::CEIPSEL_9 => 9,
CEIPSELW::CEIPSEL_10 => 10,
CEIPSELW::CEIPSEL_11 => 11,
CEIPSELW::CEIPSEL_12 => 12,
CEIPSELW::CEIPSEL_13 => 13,
CEIPSELW::CEIPSEL_14 => 14,
CEIPSELW::CEIPSEL_15 => 15,
}
}
}
#[doc = r" Proxy"]
pub struct _CEIPSELW<'a> {
w: &'a mut W,
}
impl<'a> _CEIPSELW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CEIPSELW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Channel 0 selected"]
#[inline]
pub fn ceipsel_0(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_0)
}
#[doc = "Channel 1 selected"]
#[inline]
pub fn ceipsel_1(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_1)
}
#[doc = "Channel 2 selected"]
#[inline]
pub fn ceipsel_2(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_2)
}
#[doc = "Channel 3 selected"]
#[inline]
pub fn ceipsel_3(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_3)
}
#[doc = "Channel 4 selected"]
#[inline]
pub fn ceipsel_4(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_4)
}
#[doc = "Channel 5 selected"]
#[inline]
pub fn ceipsel_5(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_5)
}
#[doc = "Channel 6 selected"]
#[inline]
pub fn ceipsel_6(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_6)
}
#[doc = "Channel 7 selected"]
#[inline]
pub fn ceipsel_7(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_7)
}
#[doc = "Channel 8 selected"]
#[inline]
pub fn ceipsel_8(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_8)
}
#[doc = "Channel 9 selected"]
#[inline]
pub fn ceipsel_9(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_9)
}
#[doc = "Channel 10 selected"]
#[inline]
pub fn ceipsel_10(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_10)
}
#[doc = "Channel 11 selected"]
#[inline]
pub fn ceipsel_11(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_11)
}
#[doc = "Channel 12 selected"]
#[inline]
pub fn ceipsel_12(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_12)
}
#[doc = "Channel 13 selected"]
#[inline]
pub fn ceipsel_13(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_13)
}
#[doc = "Channel 14 selected"]
#[inline]
pub fn ceipsel_14(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_14)
}
#[doc = "Channel 15 selected"]
#[inline]
pub fn ceipsel_15(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_15)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CEIPEN`"]
pub enum CEIPENW {
#[doc = "Selected analog input channel for V+ terminal is disabled"]
CEIPEN_0,
#[doc = "Selected analog input channel for V+ terminal is enabled"]
CEIPEN_1,
}
impl CEIPENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CEIPENW::CEIPEN_0 => false,
CEIPENW::CEIPEN_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CEIPENW<'a> {
w: &'a mut W,
}
impl<'a> _CEIPENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CEIPENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Selected analog input channel for V+ terminal is disabled"]
#[inline]
pub fn ceipen_0(self) -> &'a mut W {
self.variant(CEIPENW::CEIPEN_0)
}
#[doc = "Selected analog input channel for V+ terminal is enabled"]
#[inline]
pub fn ceipen_1(self) -> &'a mut W {
self.variant(CEIPENW::CEIPEN_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CEIMSEL`"]
pub enum CEIMSELW {
#[doc = "Channel 0 selected"]
CEIMSEL_0,
#[doc = "Channel 1 selected"]
CEIMSEL_1,
#[doc = "Channel 2 selected"]
CEIMSEL_2,
#[doc = "Channel 3 selected"]
CEIMSEL_3,
#[doc = "Channel 4 selected"]
CEIMSEL_4,
#[doc = "Channel 5 selected"]
CEIMSEL_5,
#[doc = "Channel 6 selected"]
CEIMSEL_6,
#[doc = "Channel 7 selected"]
CEIMSEL_7,
#[doc = "Channel 8 selected"]
CEIMSEL_8,
#[doc = "Channel 9 selected"]
CEIMSEL_9,
#[doc = "Channel 10 selected"]
CEIMSEL_10,
#[doc = "Channel 11 selected"]
CEIMSEL_11,
#[doc = "Channel 12 selected"]
CEIMSEL_12,
#[doc = "Channel 13 selected"]
CEIMSEL_13,
#[doc = "Channel 14 selected"]
CEIMSEL_14,
#[doc = "Channel 15 selected"]
CEIMSEL_15,
}
impl CEIMSELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
CEIMSELW::CEIMSEL_0 => 0,
CEIMSELW::CEIMSEL_1 => 1,
CEIMSELW::CEIMSEL_2 => 2,
CEIMSELW::CEIMSEL_3 => 3,
CEIMSELW::CEIMSEL_4 => 4,
CEIMSELW::CEIMSEL_5 => 5,
CEIMSELW::CEIMSEL_6 => 6,
CEIMSELW::CEIMSEL_7 => 7,
CEIMSELW::CEIMSEL_8 => 8,
CEIMSELW::CEIMSEL_9 => 9,
CEIMSELW::CEIMSEL_10 => 10,
CEIMSELW::CEIMSEL_11 => 11,
CEIMSELW::CEIMSEL_12 => 12,
CEIMSELW::CEIMSEL_13 => 13,
CEIMSELW::CEIMSEL_14 => 14,
CEIMSELW::CEIMSEL_15 => 15,
}
}
}
#[doc = r" Proxy"]
pub struct _CEIMSELW<'a> {
w: &'a mut W,
}
impl<'a> _CEIMSELW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CEIMSELW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Channel 0 selected"]
#[inline]
pub fn ceimsel_0(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_0)
}
#[doc = "Channel 1 selected"]
#[inline]
pub fn ceimsel_1(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_1)
}
#[doc = "Channel 2 selected"]
#[inline]
pub fn ceimsel_2(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_2)
}
#[doc = "Channel 3 selected"]
#[inline]
pub fn ceimsel_3(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_3)
}
#[doc = "Channel 4 selected"]
#[inline]
pub fn ceimsel_4(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_4)
}
#[doc = "Channel 5 selected"]
#[inline]
pub fn ceimsel_5(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_5)
}
#[doc = "Channel 6 selected"]
#[inline]
pub fn ceimsel_6(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_6)
}
#[doc = "Channel 7 selected"]
#[inline]
pub fn ceimsel_7(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_7)
}
#[doc = "Channel 8 selected"]
#[inline]
pub fn ceimsel_8(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_8)
}
#[doc = "Channel 9 selected"]
#[inline]
pub fn ceimsel_9(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_9)
}
#[doc = "Channel 10 selected"]
#[inline]
pub fn ceimsel_10(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_10)
}
#[doc = "Channel 11 selected"]
#[inline]
pub fn ceimsel_11(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_11)
}
#[doc = "Channel 12 selected"]
#[inline]
pub fn ceimsel_12(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_12)
}
#[doc = "Channel 13 selected"]
#[inline]
pub fn ceimsel_13(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_13)
}
#[doc = "Channel 14 selected"]
#[inline]
pub fn ceimsel_14(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_14)
}
#[doc = "Channel 15 selected"]
#[inline]
pub fn ceimsel_15(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_15)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CEIMEN`"]
pub enum CEIMENW {
#[doc = "Selected analog input channel for V- terminal is disabled"]
CEIMEN_0,
#[doc = "Selected analog input channel for V- terminal is enabled"]
CEIMEN_1,
}
impl CEIMENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CEIMENW::CEIMEN_0 => false,
CEIMENW::CEIMEN_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CEIMENW<'a> {
w: &'a mut W,
}
impl<'a> _CEIMENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CEIMENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Selected analog input channel for V- terminal is disabled"]
#[inline]
pub fn ceimen_0(self) -> &'a mut W {
self.variant(CEIMENW::CEIMEN_0)
}
#[doc = "Selected analog input channel for V- terminal is enabled"]
#[inline]
pub fn ceimen_1(self) -> &'a mut W {
self.variant(CEIMENW::CEIMEN_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
#[doc = "Bits 0:3 - Channel input selected for the V+ terminal"]
#[inline]
pub fn ceipsel(&self) -> CEIPSELR {
CEIPSELR::_from({
const MASK: u8 = 15;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u16) as u8
})
}
#[doc = "Bit 7 - Channel input enable for the V+ terminal"]
#[inline]
pub fn ceipen(&self) -> CEIPENR {
CEIPENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u16) != 0
})
}
#[doc = "Bits 8:11 - Channel input selected for the - terminal"]
#[inline]
pub fn ceimsel(&self) -> CEIMSELR {
CEIMSELR::_from({
const MASK: u8 = 15;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u16) as u8
})
}
#[doc = "Bit 15 - Channel input enable for the - terminal"]
#[inline]
pub fn ceimen(&self) -> CEIMENR {
CEIMENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u16) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - Channel input selected for the V+ terminal"]
#[inline]
pub fn ceipsel(&mut self) -> _CEIPSELW {
_CEIPSELW { w: self }
}
#[doc = "Bit 7 - Channel input enable for the V+ terminal"]
#[inline]
pub fn ceipen(&mut self) -> _CEIPENW {
_CEIPENW { w: self }
}
#[doc = "Bits 8:11 - Channel input selected for the - terminal"]
#[inline]
pub fn ceimsel(&mut self) -> _CEIMSELW {
_CEIMSELW { w: self }
}
#[doc = "Bit 15 - Channel input enable for the - terminal"]
#[inline]
pub fn ceimen(&mut self) -> _CEIMENW {
_CEIMENW { w: self }
}
}

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#[doc = r" Value read from the register"]
pub struct R {
bits: u16,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u16,
}
impl super::CEXINT {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `CEIFG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CEIFGR {
#[doc = "No interrupt pending"]
CEIFG_0,
#[doc = "Interrupt pending"]
CEIFG_1,
}
impl CEIFGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CEIFGR::CEIFG_0 => false,
CEIFGR::CEIFG_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CEIFGR {
match value {
false => CEIFGR::CEIFG_0,
true => CEIFGR::CEIFG_1,
}
}
#[doc = "Checks if the value of the field is `CEIFG_0`"]
#[inline]
pub fn is_ceifg_0(&self) -> bool {
*self == CEIFGR::CEIFG_0
}
#[doc = "Checks if the value of the field is `CEIFG_1`"]
#[inline]
pub fn is_ceifg_1(&self) -> bool {
*self == CEIFGR::CEIFG_1
}
}
#[doc = "Possible values of the field `CEIIFG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CEIIFGR {
#[doc = "No interrupt pending"]
CEIIFG_0,
#[doc = "Interrupt pending"]
CEIIFG_1,
}
impl CEIIFGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CEIIFGR::CEIIFG_0 => false,
CEIIFGR::CEIIFG_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CEIIFGR {
match value {
false => CEIIFGR::CEIIFG_0,
true => CEIIFGR::CEIIFG_1,
}
}
#[doc = "Checks if the value of the field is `CEIIFG_0`"]
#[inline]
pub fn is_ceiifg_0(&self) -> bool {
*self == CEIIFGR::CEIIFG_0
}
#[doc = "Checks if the value of the field is `CEIIFG_1`"]
#[inline]
pub fn is_ceiifg_1(&self) -> bool {
*self == CEIIFGR::CEIIFG_1
}
}
#[doc = "Possible values of the field `CERDYIFG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CERDYIFGR {
#[doc = "No interrupt pending"]
CERDYIFG_0,
#[doc = "Interrupt pending"]
CERDYIFG_1,
}
impl CERDYIFGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CERDYIFGR::CERDYIFG_0 => false,
CERDYIFGR::CERDYIFG_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CERDYIFGR {
match value {
false => CERDYIFGR::CERDYIFG_0,
true => CERDYIFGR::CERDYIFG_1,
}
}
#[doc = "Checks if the value of the field is `CERDYIFG_0`"]
#[inline]
pub fn is_cerdyifg_0(&self) -> bool {
*self == CERDYIFGR::CERDYIFG_0
}
#[doc = "Checks if the value of the field is `CERDYIFG_1`"]
#[inline]
pub fn is_cerdyifg_1(&self) -> bool {
*self == CERDYIFGR::CERDYIFG_1
}
}
#[doc = "Possible values of the field `CEIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CEIER {
#[doc = "Interrupt disabled"]
CEIE_0,
#[doc = "Interrupt enabled"]
CEIE_1,
}
impl CEIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CEIER::CEIE_0 => false,
CEIER::CEIE_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CEIER {
match value {
false => CEIER::CEIE_0,
true => CEIER::CEIE_1,
}
}
#[doc = "Checks if the value of the field is `CEIE_0`"]
#[inline]
pub fn is_ceie_0(&self) -> bool {
*self == CEIER::CEIE_0
}
#[doc = "Checks if the value of the field is `CEIE_1`"]
#[inline]
pub fn is_ceie_1(&self) -> bool {
*self == CEIER::CEIE_1
}
}
#[doc = "Possible values of the field `CEIIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CEIIER {
#[doc = "Interrupt disabled"]
CEIIE_0,
#[doc = "Interrupt enabled"]
CEIIE_1,
}
impl CEIIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CEIIER::CEIIE_0 => false,
CEIIER::CEIIE_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CEIIER {
match value {
false => CEIIER::CEIIE_0,
true => CEIIER::CEIIE_1,
}
}
#[doc = "Checks if the value of the field is `CEIIE_0`"]
#[inline]
pub fn is_ceiie_0(&self) -> bool {
*self == CEIIER::CEIIE_0
}
#[doc = "Checks if the value of the field is `CEIIE_1`"]
#[inline]
pub fn is_ceiie_1(&self) -> bool {
*self == CEIIER::CEIIE_1
}
}
#[doc = "Possible values of the field `CERDYIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CERDYIER {
#[doc = "Interrupt disabled"]
CERDYIE_0,
#[doc = "Interrupt enabled"]
CERDYIE_1,
}
impl CERDYIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CERDYIER::CERDYIE_0 => false,
CERDYIER::CERDYIE_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CERDYIER {
match value {
false => CERDYIER::CERDYIE_0,
true => CERDYIER::CERDYIE_1,
}
}
#[doc = "Checks if the value of the field is `CERDYIE_0`"]
#[inline]
pub fn is_cerdyie_0(&self) -> bool {
*self == CERDYIER::CERDYIE_0
}
#[doc = "Checks if the value of the field is `CERDYIE_1`"]
#[inline]
pub fn is_cerdyie_1(&self) -> bool {
*self == CERDYIER::CERDYIE_1
}
}
#[doc = "Values that can be written to the field `CEIFG`"]
pub enum CEIFGW {
#[doc = "No interrupt pending"]
CEIFG_0,
#[doc = "Interrupt pending"]
CEIFG_1,
}
impl CEIFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CEIFGW::CEIFG_0 => false,
CEIFGW::CEIFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CEIFGW<'a> {
w: &'a mut W,
}
impl<'a> _CEIFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CEIFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No interrupt pending"]
#[inline]
pub fn ceifg_0(self) -> &'a mut W {
self.variant(CEIFGW::CEIFG_0)
}
#[doc = "Interrupt pending"]
#[inline]
pub fn ceifg_1(self) -> &'a mut W {
self.variant(CEIFGW::CEIFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CEIIFG`"]
pub enum CEIIFGW {
#[doc = "No interrupt pending"]
CEIIFG_0,
#[doc = "Interrupt pending"]
CEIIFG_1,
}
impl CEIIFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CEIIFGW::CEIIFG_0 => false,
CEIIFGW::CEIIFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CEIIFGW<'a> {
w: &'a mut W,
}
impl<'a> _CEIIFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CEIIFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No interrupt pending"]
#[inline]
pub fn ceiifg_0(self) -> &'a mut W {
self.variant(CEIIFGW::CEIIFG_0)
}
#[doc = "Interrupt pending"]
#[inline]
pub fn ceiifg_1(self) -> &'a mut W {
self.variant(CEIIFGW::CEIIFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CERDYIFG`"]
pub enum CERDYIFGW {
#[doc = "No interrupt pending"]
CERDYIFG_0,
#[doc = "Interrupt pending"]
CERDYIFG_1,
}
impl CERDYIFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CERDYIFGW::CERDYIFG_0 => false,
CERDYIFGW::CERDYIFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CERDYIFGW<'a> {
w: &'a mut W,
}
impl<'a> _CERDYIFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CERDYIFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No interrupt pending"]
#[inline]
pub fn cerdyifg_0(self) -> &'a mut W {
self.variant(CERDYIFGW::CERDYIFG_0)
}
#[doc = "Interrupt pending"]
#[inline]
pub fn cerdyifg_1(self) -> &'a mut W {
self.variant(CERDYIFGW::CERDYIFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CEIE`"]
pub enum CEIEW {
#[doc = "Interrupt disabled"]
CEIE_0,
#[doc = "Interrupt enabled"]
CEIE_1,
}
impl CEIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CEIEW::CEIE_0 => false,
CEIEW::CEIE_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CEIEW<'a> {
w: &'a mut W,
}
impl<'a> _CEIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CEIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Interrupt disabled"]
#[inline]
pub fn ceie_0(self) -> &'a mut W {
self.variant(CEIEW::CEIE_0)
}
#[doc = "Interrupt enabled"]
#[inline]
pub fn ceie_1(self) -> &'a mut W {
self.variant(CEIEW::CEIE_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CEIIE`"]
pub enum CEIIEW {
#[doc = "Interrupt disabled"]
CEIIE_0,
#[doc = "Interrupt enabled"]
CEIIE_1,
}
impl CEIIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CEIIEW::CEIIE_0 => false,
CEIIEW::CEIIE_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CEIIEW<'a> {
w: &'a mut W,
}
impl<'a> _CEIIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CEIIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Interrupt disabled"]
#[inline]
pub fn ceiie_0(self) -> &'a mut W {
self.variant(CEIIEW::CEIIE_0)
}
#[doc = "Interrupt enabled"]
#[inline]
pub fn ceiie_1(self) -> &'a mut W {
self.variant(CEIIEW::CEIIE_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CERDYIE`"]
pub enum CERDYIEW {
#[doc = "Interrupt disabled"]
CERDYIE_0,
#[doc = "Interrupt enabled"]
CERDYIE_1,
}
impl CERDYIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CERDYIEW::CERDYIE_0 => false,
CERDYIEW::CERDYIE_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CERDYIEW<'a> {
w: &'a mut W,
}
impl<'a> _CERDYIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CERDYIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Interrupt disabled"]
#[inline]
pub fn cerdyie_0(self) -> &'a mut W {
self.variant(CERDYIEW::CERDYIE_0)
}
#[doc = "Interrupt enabled"]
#[inline]
pub fn cerdyie_1(self) -> &'a mut W {
self.variant(CERDYIEW::CERDYIE_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
#[doc = "Bit 0 - Comparator output interrupt flag"]
#[inline]
pub fn ceifg(&self) -> CEIFGR {
CEIFGR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u16) != 0
})
}
#[doc = "Bit 1 - Comparator output inverted interrupt flag"]
#[inline]
pub fn ceiifg(&self) -> CEIIFGR {
CEIIFGR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u16) != 0
})
}
#[doc = "Bit 4 - Comparator ready interrupt flag"]
#[inline]
pub fn cerdyifg(&self) -> CERDYIFGR {
CERDYIFGR::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u16) != 0
})
}
#[doc = "Bit 8 - Comparator output interrupt enable"]
#[inline]
pub fn ceie(&self) -> CEIER {
CEIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u16) != 0
})
}
#[doc = "Bit 9 - Comparator output interrupt enable inverted polarity"]
#[inline]
pub fn ceiie(&self) -> CEIIER {
CEIIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u16) != 0
})
}
#[doc = "Bit 12 - Comparator ready interrupt enable"]
#[inline]
pub fn cerdyie(&self) -> CERDYIER {
CERDYIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u16) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Comparator output interrupt flag"]
#[inline]
pub fn ceifg(&mut self) -> _CEIFGW {
_CEIFGW { w: self }
}
#[doc = "Bit 1 - Comparator output inverted interrupt flag"]
#[inline]
pub fn ceiifg(&mut self) -> _CEIIFGW {
_CEIIFGW { w: self }
}
#[doc = "Bit 4 - Comparator ready interrupt flag"]
#[inline]
pub fn cerdyifg(&mut self) -> _CERDYIFGW {
_CERDYIFGW { w: self }
}
#[doc = "Bit 8 - Comparator output interrupt enable"]
#[inline]
pub fn ceie(&mut self) -> _CEIEW {
_CEIEW { w: self }
}
#[doc = "Bit 9 - Comparator output interrupt enable inverted polarity"]
#[inline]
pub fn ceiie(&mut self) -> _CEIIEW {
_CEIIEW { w: self }
}
#[doc = "Bit 12 - Comparator ready interrupt enable"]
#[inline]
pub fn cerdyie(&mut self) -> _CERDYIEW {
_CERDYIEW { w: self }
}
}

88
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#[doc = r" Value read from the register"]
pub struct R {
bits: u16,
}
impl super::CEXIV {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = "Possible values of the field `CEIV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CEIVR {
#[doc = "No interrupt pending"]
CEIV_0,
#[doc = "Interrupt Source: CEOUT interrupt; Interrupt Flag: CEIFG; Interrupt Priority: Highest"]
CEIV_2,
#[doc = "Interrupt Source: CEOUT interrupt inverted polarity; Interrupt Flag: CEIIFG"]
CEIV_4,
#[doc = "Interrupt Source: Comparator ready interrupt; Interrupt Flag: CERDYIFG; Interrupt Priority: Lowest"]
CEIV_10,
#[doc = r" Reserved"]
_Reserved(u16),
}
impl CEIVR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
match *self {
CEIVR::CEIV_0 => 0,
CEIVR::CEIV_2 => 2,
CEIVR::CEIV_4 => 4,
CEIVR::CEIV_10 => 10,
CEIVR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u16) -> CEIVR {
match value {
0 => CEIVR::CEIV_0,
2 => CEIVR::CEIV_2,
4 => CEIVR::CEIV_4,
10 => CEIVR::CEIV_10,
i => CEIVR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `CEIV_0`"]
#[inline]
pub fn is_ceiv_0(&self) -> bool {
*self == CEIVR::CEIV_0
}
#[doc = "Checks if the value of the field is `CEIV_2`"]
#[inline]
pub fn is_ceiv_2(&self) -> bool {
*self == CEIVR::CEIV_2
}
#[doc = "Checks if the value of the field is `CEIV_4`"]
#[inline]
pub fn is_ceiv_4(&self) -> bool {
*self == CEIVR::CEIV_4
}
#[doc = "Checks if the value of the field is `CEIV_10`"]
#[inline]
pub fn is_ceiv_10(&self) -> bool {
*self == CEIVR::CEIV_10
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
#[doc = "Bits 0:15 - Comparator interrupt vector word register"]
#[inline]
pub fn ceiv(&self) -> CEIVR {
CEIVR::_from({
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u16) as u16
})
}
}

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#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Comparator Control Register 0"]
pub cex_ctl0: CEXCTL0,
#[doc = "0x02 - Comparator Control Register 1"]
pub cex_ctl1: CEXCTL1,
#[doc = "0x04 - Comparator Control Register 2"]
pub cex_ctl2: CEXCTL2,
#[doc = "0x06 - Comparator Control Register 3"]
pub cex_ctl3: CEXCTL3,
_reserved0: [u8; 4usize],
#[doc = "0x0c - Comparator Interrupt Control Register"]
pub cex_int: CEXINT,
#[doc = "0x0e - Comparator Interrupt Vector Word Register"]
pub cex_iv: CEXIV,
}
#[doc = "Comparator Control Register 0"]
pub struct CEXCTL0 {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Comparator Control Register 0"]
pub mod cex_ctl0;
#[doc = "Comparator Control Register 1"]
pub struct CEXCTL1 {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Comparator Control Register 1"]
pub mod cex_ctl1;
#[doc = "Comparator Control Register 2"]
pub struct CEXCTL2 {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Comparator Control Register 2"]
pub mod cex_ctl2;
#[doc = "Comparator Control Register 3"]
pub struct CEXCTL3 {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Comparator Control Register 3"]
pub mod cex_ctl3;
#[doc = "Comparator Interrupt Control Register"]
pub struct CEXINT {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Comparator Interrupt Control Register"]
pub mod cex_int;
#[doc = "Comparator Interrupt Vector Word Register"]
pub struct CEXIV {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Comparator Interrupt Vector Word Register"]
pub mod cex_iv;

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#[doc = r" Value read from the register"]
pub struct R {
bits: u16,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u16,
}
impl super::CEXCTL0 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `CEIPSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CEIPSELR {
#[doc = "Channel 0 selected"]
CEIPSEL_0,
#[doc = "Channel 1 selected"]
CEIPSEL_1,
#[doc = "Channel 2 selected"]
CEIPSEL_2,
#[doc = "Channel 3 selected"]
CEIPSEL_3,
#[doc = "Channel 4 selected"]
CEIPSEL_4,
#[doc = "Channel 5 selected"]
CEIPSEL_5,
#[doc = "Channel 6 selected"]
CEIPSEL_6,
#[doc = "Channel 7 selected"]
CEIPSEL_7,
#[doc = "Channel 8 selected"]
CEIPSEL_8,
#[doc = "Channel 9 selected"]
CEIPSEL_9,
#[doc = "Channel 10 selected"]
CEIPSEL_10,
#[doc = "Channel 11 selected"]
CEIPSEL_11,
#[doc = "Channel 12 selected"]
CEIPSEL_12,
#[doc = "Channel 13 selected"]
CEIPSEL_13,
#[doc = "Channel 14 selected"]
CEIPSEL_14,
#[doc = "Channel 15 selected"]
CEIPSEL_15,
}
impl CEIPSELR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
CEIPSELR::CEIPSEL_0 => 0,
CEIPSELR::CEIPSEL_1 => 1,
CEIPSELR::CEIPSEL_2 => 2,
CEIPSELR::CEIPSEL_3 => 3,
CEIPSELR::CEIPSEL_4 => 4,
CEIPSELR::CEIPSEL_5 => 5,
CEIPSELR::CEIPSEL_6 => 6,
CEIPSELR::CEIPSEL_7 => 7,
CEIPSELR::CEIPSEL_8 => 8,
CEIPSELR::CEIPSEL_9 => 9,
CEIPSELR::CEIPSEL_10 => 10,
CEIPSELR::CEIPSEL_11 => 11,
CEIPSELR::CEIPSEL_12 => 12,
CEIPSELR::CEIPSEL_13 => 13,
CEIPSELR::CEIPSEL_14 => 14,
CEIPSELR::CEIPSEL_15 => 15,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> CEIPSELR {
match value {
0 => CEIPSELR::CEIPSEL_0,
1 => CEIPSELR::CEIPSEL_1,
2 => CEIPSELR::CEIPSEL_2,
3 => CEIPSELR::CEIPSEL_3,
4 => CEIPSELR::CEIPSEL_4,
5 => CEIPSELR::CEIPSEL_5,
6 => CEIPSELR::CEIPSEL_6,
7 => CEIPSELR::CEIPSEL_7,
8 => CEIPSELR::CEIPSEL_8,
9 => CEIPSELR::CEIPSEL_9,
10 => CEIPSELR::CEIPSEL_10,
11 => CEIPSELR::CEIPSEL_11,
12 => CEIPSELR::CEIPSEL_12,
13 => CEIPSELR::CEIPSEL_13,
14 => CEIPSELR::CEIPSEL_14,
15 => CEIPSELR::CEIPSEL_15,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CEIPSEL_0`"]
#[inline]
pub fn is_ceipsel_0(&self) -> bool {
*self == CEIPSELR::CEIPSEL_0
}
#[doc = "Checks if the value of the field is `CEIPSEL_1`"]
#[inline]
pub fn is_ceipsel_1(&self) -> bool {
*self == CEIPSELR::CEIPSEL_1
}
#[doc = "Checks if the value of the field is `CEIPSEL_2`"]
#[inline]
pub fn is_ceipsel_2(&self) -> bool {
*self == CEIPSELR::CEIPSEL_2
}
#[doc = "Checks if the value of the field is `CEIPSEL_3`"]
#[inline]
pub fn is_ceipsel_3(&self) -> bool {
*self == CEIPSELR::CEIPSEL_3
}
#[doc = "Checks if the value of the field is `CEIPSEL_4`"]
#[inline]
pub fn is_ceipsel_4(&self) -> bool {
*self == CEIPSELR::CEIPSEL_4
}
#[doc = "Checks if the value of the field is `CEIPSEL_5`"]
#[inline]
pub fn is_ceipsel_5(&self) -> bool {
*self == CEIPSELR::CEIPSEL_5
}
#[doc = "Checks if the value of the field is `CEIPSEL_6`"]
#[inline]
pub fn is_ceipsel_6(&self) -> bool {
*self == CEIPSELR::CEIPSEL_6
}
#[doc = "Checks if the value of the field is `CEIPSEL_7`"]
#[inline]
pub fn is_ceipsel_7(&self) -> bool {
*self == CEIPSELR::CEIPSEL_7
}
#[doc = "Checks if the value of the field is `CEIPSEL_8`"]
#[inline]
pub fn is_ceipsel_8(&self) -> bool {
*self == CEIPSELR::CEIPSEL_8
}
#[doc = "Checks if the value of the field is `CEIPSEL_9`"]
#[inline]
pub fn is_ceipsel_9(&self) -> bool {
*self == CEIPSELR::CEIPSEL_9
}
#[doc = "Checks if the value of the field is `CEIPSEL_10`"]
#[inline]
pub fn is_ceipsel_10(&self) -> bool {
*self == CEIPSELR::CEIPSEL_10
}
#[doc = "Checks if the value of the field is `CEIPSEL_11`"]
#[inline]
pub fn is_ceipsel_11(&self) -> bool {
*self == CEIPSELR::CEIPSEL_11
}
#[doc = "Checks if the value of the field is `CEIPSEL_12`"]
#[inline]
pub fn is_ceipsel_12(&self) -> bool {
*self == CEIPSELR::CEIPSEL_12
}
#[doc = "Checks if the value of the field is `CEIPSEL_13`"]
#[inline]
pub fn is_ceipsel_13(&self) -> bool {
*self == CEIPSELR::CEIPSEL_13
}
#[doc = "Checks if the value of the field is `CEIPSEL_14`"]
#[inline]
pub fn is_ceipsel_14(&self) -> bool {
*self == CEIPSELR::CEIPSEL_14
}
#[doc = "Checks if the value of the field is `CEIPSEL_15`"]
#[inline]
pub fn is_ceipsel_15(&self) -> bool {
*self == CEIPSELR::CEIPSEL_15
}
}
#[doc = "Possible values of the field `CEIPEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CEIPENR {
#[doc = "Selected analog input channel for V+ terminal is disabled"]
CEIPEN_0,
#[doc = "Selected analog input channel for V+ terminal is enabled"]
CEIPEN_1,
}
impl CEIPENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CEIPENR::CEIPEN_0 => false,
CEIPENR::CEIPEN_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CEIPENR {
match value {
false => CEIPENR::CEIPEN_0,
true => CEIPENR::CEIPEN_1,
}
}
#[doc = "Checks if the value of the field is `CEIPEN_0`"]
#[inline]
pub fn is_ceipen_0(&self) -> bool {
*self == CEIPENR::CEIPEN_0
}
#[doc = "Checks if the value of the field is `CEIPEN_1`"]
#[inline]
pub fn is_ceipen_1(&self) -> bool {
*self == CEIPENR::CEIPEN_1
}
}
#[doc = "Possible values of the field `CEIMSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CEIMSELR {
#[doc = "Channel 0 selected"]
CEIMSEL_0,
#[doc = "Channel 1 selected"]
CEIMSEL_1,
#[doc = "Channel 2 selected"]
CEIMSEL_2,
#[doc = "Channel 3 selected"]
CEIMSEL_3,
#[doc = "Channel 4 selected"]
CEIMSEL_4,
#[doc = "Channel 5 selected"]
CEIMSEL_5,
#[doc = "Channel 6 selected"]
CEIMSEL_6,
#[doc = "Channel 7 selected"]
CEIMSEL_7,
#[doc = "Channel 8 selected"]
CEIMSEL_8,
#[doc = "Channel 9 selected"]
CEIMSEL_9,
#[doc = "Channel 10 selected"]
CEIMSEL_10,
#[doc = "Channel 11 selected"]
CEIMSEL_11,
#[doc = "Channel 12 selected"]
CEIMSEL_12,
#[doc = "Channel 13 selected"]
CEIMSEL_13,
#[doc = "Channel 14 selected"]
CEIMSEL_14,
#[doc = "Channel 15 selected"]
CEIMSEL_15,
}
impl CEIMSELR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
CEIMSELR::CEIMSEL_0 => 0,
CEIMSELR::CEIMSEL_1 => 1,
CEIMSELR::CEIMSEL_2 => 2,
CEIMSELR::CEIMSEL_3 => 3,
CEIMSELR::CEIMSEL_4 => 4,
CEIMSELR::CEIMSEL_5 => 5,
CEIMSELR::CEIMSEL_6 => 6,
CEIMSELR::CEIMSEL_7 => 7,
CEIMSELR::CEIMSEL_8 => 8,
CEIMSELR::CEIMSEL_9 => 9,
CEIMSELR::CEIMSEL_10 => 10,
CEIMSELR::CEIMSEL_11 => 11,
CEIMSELR::CEIMSEL_12 => 12,
CEIMSELR::CEIMSEL_13 => 13,
CEIMSELR::CEIMSEL_14 => 14,
CEIMSELR::CEIMSEL_15 => 15,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> CEIMSELR {
match value {
0 => CEIMSELR::CEIMSEL_0,
1 => CEIMSELR::CEIMSEL_1,
2 => CEIMSELR::CEIMSEL_2,
3 => CEIMSELR::CEIMSEL_3,
4 => CEIMSELR::CEIMSEL_4,
5 => CEIMSELR::CEIMSEL_5,
6 => CEIMSELR::CEIMSEL_6,
7 => CEIMSELR::CEIMSEL_7,
8 => CEIMSELR::CEIMSEL_8,
9 => CEIMSELR::CEIMSEL_9,
10 => CEIMSELR::CEIMSEL_10,
11 => CEIMSELR::CEIMSEL_11,
12 => CEIMSELR::CEIMSEL_12,
13 => CEIMSELR::CEIMSEL_13,
14 => CEIMSELR::CEIMSEL_14,
15 => CEIMSELR::CEIMSEL_15,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CEIMSEL_0`"]
#[inline]
pub fn is_ceimsel_0(&self) -> bool {
*self == CEIMSELR::CEIMSEL_0
}
#[doc = "Checks if the value of the field is `CEIMSEL_1`"]
#[inline]
pub fn is_ceimsel_1(&self) -> bool {
*self == CEIMSELR::CEIMSEL_1
}
#[doc = "Checks if the value of the field is `CEIMSEL_2`"]
#[inline]
pub fn is_ceimsel_2(&self) -> bool {
*self == CEIMSELR::CEIMSEL_2
}
#[doc = "Checks if the value of the field is `CEIMSEL_3`"]
#[inline]
pub fn is_ceimsel_3(&self) -> bool {
*self == CEIMSELR::CEIMSEL_3
}
#[doc = "Checks if the value of the field is `CEIMSEL_4`"]
#[inline]
pub fn is_ceimsel_4(&self) -> bool {
*self == CEIMSELR::CEIMSEL_4
}
#[doc = "Checks if the value of the field is `CEIMSEL_5`"]
#[inline]
pub fn is_ceimsel_5(&self) -> bool {
*self == CEIMSELR::CEIMSEL_5
}
#[doc = "Checks if the value of the field is `CEIMSEL_6`"]
#[inline]
pub fn is_ceimsel_6(&self) -> bool {
*self == CEIMSELR::CEIMSEL_6
}
#[doc = "Checks if the value of the field is `CEIMSEL_7`"]
#[inline]
pub fn is_ceimsel_7(&self) -> bool {
*self == CEIMSELR::CEIMSEL_7
}
#[doc = "Checks if the value of the field is `CEIMSEL_8`"]
#[inline]
pub fn is_ceimsel_8(&self) -> bool {
*self == CEIMSELR::CEIMSEL_8
}
#[doc = "Checks if the value of the field is `CEIMSEL_9`"]
#[inline]
pub fn is_ceimsel_9(&self) -> bool {
*self == CEIMSELR::CEIMSEL_9
}
#[doc = "Checks if the value of the field is `CEIMSEL_10`"]
#[inline]
pub fn is_ceimsel_10(&self) -> bool {
*self == CEIMSELR::CEIMSEL_10
}
#[doc = "Checks if the value of the field is `CEIMSEL_11`"]
#[inline]
pub fn is_ceimsel_11(&self) -> bool {
*self == CEIMSELR::CEIMSEL_11
}
#[doc = "Checks if the value of the field is `CEIMSEL_12`"]
#[inline]
pub fn is_ceimsel_12(&self) -> bool {
*self == CEIMSELR::CEIMSEL_12
}
#[doc = "Checks if the value of the field is `CEIMSEL_13`"]
#[inline]
pub fn is_ceimsel_13(&self) -> bool {
*self == CEIMSELR::CEIMSEL_13
}
#[doc = "Checks if the value of the field is `CEIMSEL_14`"]
#[inline]
pub fn is_ceimsel_14(&self) -> bool {
*self == CEIMSELR::CEIMSEL_14
}
#[doc = "Checks if the value of the field is `CEIMSEL_15`"]
#[inline]
pub fn is_ceimsel_15(&self) -> bool {
*self == CEIMSELR::CEIMSEL_15
}
}
#[doc = "Possible values of the field `CEIMEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CEIMENR {
#[doc = "Selected analog input channel for V- terminal is disabled"]
CEIMEN_0,
#[doc = "Selected analog input channel for V- terminal is enabled"]
CEIMEN_1,
}
impl CEIMENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CEIMENR::CEIMEN_0 => false,
CEIMENR::CEIMEN_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CEIMENR {
match value {
false => CEIMENR::CEIMEN_0,
true => CEIMENR::CEIMEN_1,
}
}
#[doc = "Checks if the value of the field is `CEIMEN_0`"]
#[inline]
pub fn is_ceimen_0(&self) -> bool {
*self == CEIMENR::CEIMEN_0
}
#[doc = "Checks if the value of the field is `CEIMEN_1`"]
#[inline]
pub fn is_ceimen_1(&self) -> bool {
*self == CEIMENR::CEIMEN_1
}
}
#[doc = "Values that can be written to the field `CEIPSEL`"]
pub enum CEIPSELW {
#[doc = "Channel 0 selected"]
CEIPSEL_0,
#[doc = "Channel 1 selected"]
CEIPSEL_1,
#[doc = "Channel 2 selected"]
CEIPSEL_2,
#[doc = "Channel 3 selected"]
CEIPSEL_3,
#[doc = "Channel 4 selected"]
CEIPSEL_4,
#[doc = "Channel 5 selected"]
CEIPSEL_5,
#[doc = "Channel 6 selected"]
CEIPSEL_6,
#[doc = "Channel 7 selected"]
CEIPSEL_7,
#[doc = "Channel 8 selected"]
CEIPSEL_8,
#[doc = "Channel 9 selected"]
CEIPSEL_9,
#[doc = "Channel 10 selected"]
CEIPSEL_10,
#[doc = "Channel 11 selected"]
CEIPSEL_11,
#[doc = "Channel 12 selected"]
CEIPSEL_12,
#[doc = "Channel 13 selected"]
CEIPSEL_13,
#[doc = "Channel 14 selected"]
CEIPSEL_14,
#[doc = "Channel 15 selected"]
CEIPSEL_15,
}
impl CEIPSELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
CEIPSELW::CEIPSEL_0 => 0,
CEIPSELW::CEIPSEL_1 => 1,
CEIPSELW::CEIPSEL_2 => 2,
CEIPSELW::CEIPSEL_3 => 3,
CEIPSELW::CEIPSEL_4 => 4,
CEIPSELW::CEIPSEL_5 => 5,
CEIPSELW::CEIPSEL_6 => 6,
CEIPSELW::CEIPSEL_7 => 7,
CEIPSELW::CEIPSEL_8 => 8,
CEIPSELW::CEIPSEL_9 => 9,
CEIPSELW::CEIPSEL_10 => 10,
CEIPSELW::CEIPSEL_11 => 11,
CEIPSELW::CEIPSEL_12 => 12,
CEIPSELW::CEIPSEL_13 => 13,
CEIPSELW::CEIPSEL_14 => 14,
CEIPSELW::CEIPSEL_15 => 15,
}
}
}
#[doc = r" Proxy"]
pub struct _CEIPSELW<'a> {
w: &'a mut W,
}
impl<'a> _CEIPSELW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CEIPSELW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Channel 0 selected"]
#[inline]
pub fn ceipsel_0(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_0)
}
#[doc = "Channel 1 selected"]
#[inline]
pub fn ceipsel_1(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_1)
}
#[doc = "Channel 2 selected"]
#[inline]
pub fn ceipsel_2(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_2)
}
#[doc = "Channel 3 selected"]
#[inline]
pub fn ceipsel_3(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_3)
}
#[doc = "Channel 4 selected"]
#[inline]
pub fn ceipsel_4(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_4)
}
#[doc = "Channel 5 selected"]
#[inline]
pub fn ceipsel_5(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_5)
}
#[doc = "Channel 6 selected"]
#[inline]
pub fn ceipsel_6(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_6)
}
#[doc = "Channel 7 selected"]
#[inline]
pub fn ceipsel_7(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_7)
}
#[doc = "Channel 8 selected"]
#[inline]
pub fn ceipsel_8(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_8)
}
#[doc = "Channel 9 selected"]
#[inline]
pub fn ceipsel_9(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_9)
}
#[doc = "Channel 10 selected"]
#[inline]
pub fn ceipsel_10(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_10)
}
#[doc = "Channel 11 selected"]
#[inline]
pub fn ceipsel_11(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_11)
}
#[doc = "Channel 12 selected"]
#[inline]
pub fn ceipsel_12(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_12)
}
#[doc = "Channel 13 selected"]
#[inline]
pub fn ceipsel_13(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_13)
}
#[doc = "Channel 14 selected"]
#[inline]
pub fn ceipsel_14(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_14)
}
#[doc = "Channel 15 selected"]
#[inline]
pub fn ceipsel_15(self) -> &'a mut W {
self.variant(CEIPSELW::CEIPSEL_15)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CEIPEN`"]
pub enum CEIPENW {
#[doc = "Selected analog input channel for V+ terminal is disabled"]
CEIPEN_0,
#[doc = "Selected analog input channel for V+ terminal is enabled"]
CEIPEN_1,
}
impl CEIPENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CEIPENW::CEIPEN_0 => false,
CEIPENW::CEIPEN_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CEIPENW<'a> {
w: &'a mut W,
}
impl<'a> _CEIPENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CEIPENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Selected analog input channel for V+ terminal is disabled"]
#[inline]
pub fn ceipen_0(self) -> &'a mut W {
self.variant(CEIPENW::CEIPEN_0)
}
#[doc = "Selected analog input channel for V+ terminal is enabled"]
#[inline]
pub fn ceipen_1(self) -> &'a mut W {
self.variant(CEIPENW::CEIPEN_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CEIMSEL`"]
pub enum CEIMSELW {
#[doc = "Channel 0 selected"]
CEIMSEL_0,
#[doc = "Channel 1 selected"]
CEIMSEL_1,
#[doc = "Channel 2 selected"]
CEIMSEL_2,
#[doc = "Channel 3 selected"]
CEIMSEL_3,
#[doc = "Channel 4 selected"]
CEIMSEL_4,
#[doc = "Channel 5 selected"]
CEIMSEL_5,
#[doc = "Channel 6 selected"]
CEIMSEL_6,
#[doc = "Channel 7 selected"]
CEIMSEL_7,
#[doc = "Channel 8 selected"]
CEIMSEL_8,
#[doc = "Channel 9 selected"]
CEIMSEL_9,
#[doc = "Channel 10 selected"]
CEIMSEL_10,
#[doc = "Channel 11 selected"]
CEIMSEL_11,
#[doc = "Channel 12 selected"]
CEIMSEL_12,
#[doc = "Channel 13 selected"]
CEIMSEL_13,
#[doc = "Channel 14 selected"]
CEIMSEL_14,
#[doc = "Channel 15 selected"]
CEIMSEL_15,
}
impl CEIMSELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
CEIMSELW::CEIMSEL_0 => 0,
CEIMSELW::CEIMSEL_1 => 1,
CEIMSELW::CEIMSEL_2 => 2,
CEIMSELW::CEIMSEL_3 => 3,
CEIMSELW::CEIMSEL_4 => 4,
CEIMSELW::CEIMSEL_5 => 5,
CEIMSELW::CEIMSEL_6 => 6,
CEIMSELW::CEIMSEL_7 => 7,
CEIMSELW::CEIMSEL_8 => 8,
CEIMSELW::CEIMSEL_9 => 9,
CEIMSELW::CEIMSEL_10 => 10,
CEIMSELW::CEIMSEL_11 => 11,
CEIMSELW::CEIMSEL_12 => 12,
CEIMSELW::CEIMSEL_13 => 13,
CEIMSELW::CEIMSEL_14 => 14,
CEIMSELW::CEIMSEL_15 => 15,
}
}
}
#[doc = r" Proxy"]
pub struct _CEIMSELW<'a> {
w: &'a mut W,
}
impl<'a> _CEIMSELW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CEIMSELW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Channel 0 selected"]
#[inline]
pub fn ceimsel_0(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_0)
}
#[doc = "Channel 1 selected"]
#[inline]
pub fn ceimsel_1(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_1)
}
#[doc = "Channel 2 selected"]
#[inline]
pub fn ceimsel_2(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_2)
}
#[doc = "Channel 3 selected"]
#[inline]
pub fn ceimsel_3(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_3)
}
#[doc = "Channel 4 selected"]
#[inline]
pub fn ceimsel_4(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_4)
}
#[doc = "Channel 5 selected"]
#[inline]
pub fn ceimsel_5(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_5)
}
#[doc = "Channel 6 selected"]
#[inline]
pub fn ceimsel_6(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_6)
}
#[doc = "Channel 7 selected"]
#[inline]
pub fn ceimsel_7(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_7)
}
#[doc = "Channel 8 selected"]
#[inline]
pub fn ceimsel_8(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_8)
}
#[doc = "Channel 9 selected"]
#[inline]
pub fn ceimsel_9(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_9)
}
#[doc = "Channel 10 selected"]
#[inline]
pub fn ceimsel_10(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_10)
}
#[doc = "Channel 11 selected"]
#[inline]
pub fn ceimsel_11(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_11)
}
#[doc = "Channel 12 selected"]
#[inline]
pub fn ceimsel_12(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_12)
}
#[doc = "Channel 13 selected"]
#[inline]
pub fn ceimsel_13(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_13)
}
#[doc = "Channel 14 selected"]
#[inline]
pub fn ceimsel_14(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_14)
}
#[doc = "Channel 15 selected"]
#[inline]
pub fn ceimsel_15(self) -> &'a mut W {
self.variant(CEIMSELW::CEIMSEL_15)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CEIMEN`"]
pub enum CEIMENW {
#[doc = "Selected analog input channel for V- terminal is disabled"]
CEIMEN_0,
#[doc = "Selected analog input channel for V- terminal is enabled"]
CEIMEN_1,
}
impl CEIMENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CEIMENW::CEIMEN_0 => false,
CEIMENW::CEIMEN_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CEIMENW<'a> {
w: &'a mut W,
}
impl<'a> _CEIMENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CEIMENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Selected analog input channel for V- terminal is disabled"]
#[inline]
pub fn ceimen_0(self) -> &'a mut W {
self.variant(CEIMENW::CEIMEN_0)
}
#[doc = "Selected analog input channel for V- terminal is enabled"]
#[inline]
pub fn ceimen_1(self) -> &'a mut W {
self.variant(CEIMENW::CEIMEN_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
#[doc = "Bits 0:3 - Channel input selected for the V+ terminal"]
#[inline]
pub fn ceipsel(&self) -> CEIPSELR {
CEIPSELR::_from({
const MASK: u8 = 15;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u16) as u8
})
}
#[doc = "Bit 7 - Channel input enable for the V+ terminal"]
#[inline]
pub fn ceipen(&self) -> CEIPENR {
CEIPENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u16) != 0
})
}
#[doc = "Bits 8:11 - Channel input selected for the - terminal"]
#[inline]
pub fn ceimsel(&self) -> CEIMSELR {
CEIMSELR::_from({
const MASK: u8 = 15;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u16) as u8
})
}
#[doc = "Bit 15 - Channel input enable for the - terminal"]
#[inline]
pub fn ceimen(&self) -> CEIMENR {
CEIMENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u16) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - Channel input selected for the V+ terminal"]
#[inline]
pub fn ceipsel(&mut self) -> _CEIPSELW {
_CEIPSELW { w: self }
}
#[doc = "Bit 7 - Channel input enable for the V+ terminal"]
#[inline]
pub fn ceipen(&mut self) -> _CEIPENW {
_CEIPENW { w: self }
}
#[doc = "Bits 8:11 - Channel input selected for the - terminal"]
#[inline]
pub fn ceimsel(&mut self) -> _CEIMSELW {
_CEIMSELW { w: self }
}
#[doc = "Bit 15 - Channel input enable for the - terminal"]
#[inline]
pub fn ceimen(&mut self) -> _CEIMENW {
_CEIMENW { w: self }
}
}

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example-source/msp432p401r/src/comp_e1/cex_ctl2.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u16,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u16,
}
impl super::CEXINT {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `CEIFG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CEIFGR {
#[doc = "No interrupt pending"]
CEIFG_0,
#[doc = "Interrupt pending"]
CEIFG_1,
}
impl CEIFGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CEIFGR::CEIFG_0 => false,
CEIFGR::CEIFG_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CEIFGR {
match value {
false => CEIFGR::CEIFG_0,
true => CEIFGR::CEIFG_1,
}
}
#[doc = "Checks if the value of the field is `CEIFG_0`"]
#[inline]
pub fn is_ceifg_0(&self) -> bool {
*self == CEIFGR::CEIFG_0
}
#[doc = "Checks if the value of the field is `CEIFG_1`"]
#[inline]
pub fn is_ceifg_1(&self) -> bool {
*self == CEIFGR::CEIFG_1
}
}
#[doc = "Possible values of the field `CEIIFG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CEIIFGR {
#[doc = "No interrupt pending"]
CEIIFG_0,
#[doc = "Interrupt pending"]
CEIIFG_1,
}
impl CEIIFGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CEIIFGR::CEIIFG_0 => false,
CEIIFGR::CEIIFG_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CEIIFGR {
match value {
false => CEIIFGR::CEIIFG_0,
true => CEIIFGR::CEIIFG_1,
}
}
#[doc = "Checks if the value of the field is `CEIIFG_0`"]
#[inline]
pub fn is_ceiifg_0(&self) -> bool {
*self == CEIIFGR::CEIIFG_0
}
#[doc = "Checks if the value of the field is `CEIIFG_1`"]
#[inline]
pub fn is_ceiifg_1(&self) -> bool {
*self == CEIIFGR::CEIIFG_1
}
}
#[doc = "Possible values of the field `CERDYIFG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CERDYIFGR {
#[doc = "No interrupt pending"]
CERDYIFG_0,
#[doc = "Interrupt pending"]
CERDYIFG_1,
}
impl CERDYIFGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CERDYIFGR::CERDYIFG_0 => false,
CERDYIFGR::CERDYIFG_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CERDYIFGR {
match value {
false => CERDYIFGR::CERDYIFG_0,
true => CERDYIFGR::CERDYIFG_1,
}
}
#[doc = "Checks if the value of the field is `CERDYIFG_0`"]
#[inline]
pub fn is_cerdyifg_0(&self) -> bool {
*self == CERDYIFGR::CERDYIFG_0
}
#[doc = "Checks if the value of the field is `CERDYIFG_1`"]
#[inline]
pub fn is_cerdyifg_1(&self) -> bool {
*self == CERDYIFGR::CERDYIFG_1
}
}
#[doc = "Possible values of the field `CEIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CEIER {
#[doc = "Interrupt disabled"]
CEIE_0,
#[doc = "Interrupt enabled"]
CEIE_1,
}
impl CEIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CEIER::CEIE_0 => false,
CEIER::CEIE_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CEIER {
match value {
false => CEIER::CEIE_0,
true => CEIER::CEIE_1,
}
}
#[doc = "Checks if the value of the field is `CEIE_0`"]
#[inline]
pub fn is_ceie_0(&self) -> bool {
*self == CEIER::CEIE_0
}
#[doc = "Checks if the value of the field is `CEIE_1`"]
#[inline]
pub fn is_ceie_1(&self) -> bool {
*self == CEIER::CEIE_1
}
}
#[doc = "Possible values of the field `CEIIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CEIIER {
#[doc = "Interrupt disabled"]
CEIIE_0,
#[doc = "Interrupt enabled"]
CEIIE_1,
}
impl CEIIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CEIIER::CEIIE_0 => false,
CEIIER::CEIIE_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CEIIER {
match value {
false => CEIIER::CEIIE_0,
true => CEIIER::CEIIE_1,
}
}
#[doc = "Checks if the value of the field is `CEIIE_0`"]
#[inline]
pub fn is_ceiie_0(&self) -> bool {
*self == CEIIER::CEIIE_0
}
#[doc = "Checks if the value of the field is `CEIIE_1`"]
#[inline]
pub fn is_ceiie_1(&self) -> bool {
*self == CEIIER::CEIIE_1
}
}
#[doc = "Possible values of the field `CERDYIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CERDYIER {
#[doc = "Interrupt disabled"]
CERDYIE_0,
#[doc = "Interrupt enabled"]
CERDYIE_1,
}
impl CERDYIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CERDYIER::CERDYIE_0 => false,
CERDYIER::CERDYIE_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CERDYIER {
match value {
false => CERDYIER::CERDYIE_0,
true => CERDYIER::CERDYIE_1,
}
}
#[doc = "Checks if the value of the field is `CERDYIE_0`"]
#[inline]
pub fn is_cerdyie_0(&self) -> bool {
*self == CERDYIER::CERDYIE_0
}
#[doc = "Checks if the value of the field is `CERDYIE_1`"]
#[inline]
pub fn is_cerdyie_1(&self) -> bool {
*self == CERDYIER::CERDYIE_1
}
}
#[doc = "Values that can be written to the field `CEIFG`"]
pub enum CEIFGW {
#[doc = "No interrupt pending"]
CEIFG_0,
#[doc = "Interrupt pending"]
CEIFG_1,
}
impl CEIFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CEIFGW::CEIFG_0 => false,
CEIFGW::CEIFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CEIFGW<'a> {
w: &'a mut W,
}
impl<'a> _CEIFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CEIFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No interrupt pending"]
#[inline]
pub fn ceifg_0(self) -> &'a mut W {
self.variant(CEIFGW::CEIFG_0)
}
#[doc = "Interrupt pending"]
#[inline]
pub fn ceifg_1(self) -> &'a mut W {
self.variant(CEIFGW::CEIFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CEIIFG`"]
pub enum CEIIFGW {
#[doc = "No interrupt pending"]
CEIIFG_0,
#[doc = "Interrupt pending"]
CEIIFG_1,
}
impl CEIIFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CEIIFGW::CEIIFG_0 => false,
CEIIFGW::CEIIFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CEIIFGW<'a> {
w: &'a mut W,
}
impl<'a> _CEIIFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CEIIFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No interrupt pending"]
#[inline]
pub fn ceiifg_0(self) -> &'a mut W {
self.variant(CEIIFGW::CEIIFG_0)
}
#[doc = "Interrupt pending"]
#[inline]
pub fn ceiifg_1(self) -> &'a mut W {
self.variant(CEIIFGW::CEIIFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CERDYIFG`"]
pub enum CERDYIFGW {
#[doc = "No interrupt pending"]
CERDYIFG_0,
#[doc = "Interrupt pending"]
CERDYIFG_1,
}
impl CERDYIFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CERDYIFGW::CERDYIFG_0 => false,
CERDYIFGW::CERDYIFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CERDYIFGW<'a> {
w: &'a mut W,
}
impl<'a> _CERDYIFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CERDYIFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No interrupt pending"]
#[inline]
pub fn cerdyifg_0(self) -> &'a mut W {
self.variant(CERDYIFGW::CERDYIFG_0)
}
#[doc = "Interrupt pending"]
#[inline]
pub fn cerdyifg_1(self) -> &'a mut W {
self.variant(CERDYIFGW::CERDYIFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CEIE`"]
pub enum CEIEW {
#[doc = "Interrupt disabled"]
CEIE_0,
#[doc = "Interrupt enabled"]
CEIE_1,
}
impl CEIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CEIEW::CEIE_0 => false,
CEIEW::CEIE_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CEIEW<'a> {
w: &'a mut W,
}
impl<'a> _CEIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CEIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Interrupt disabled"]
#[inline]
pub fn ceie_0(self) -> &'a mut W {
self.variant(CEIEW::CEIE_0)
}
#[doc = "Interrupt enabled"]
#[inline]
pub fn ceie_1(self) -> &'a mut W {
self.variant(CEIEW::CEIE_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CEIIE`"]
pub enum CEIIEW {
#[doc = "Interrupt disabled"]
CEIIE_0,
#[doc = "Interrupt enabled"]
CEIIE_1,
}
impl CEIIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CEIIEW::CEIIE_0 => false,
CEIIEW::CEIIE_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CEIIEW<'a> {
w: &'a mut W,
}
impl<'a> _CEIIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CEIIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Interrupt disabled"]
#[inline]
pub fn ceiie_0(self) -> &'a mut W {
self.variant(CEIIEW::CEIIE_0)
}
#[doc = "Interrupt enabled"]
#[inline]
pub fn ceiie_1(self) -> &'a mut W {
self.variant(CEIIEW::CEIIE_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CERDYIE`"]
pub enum CERDYIEW {
#[doc = "Interrupt disabled"]
CERDYIE_0,
#[doc = "Interrupt enabled"]
CERDYIE_1,
}
impl CERDYIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CERDYIEW::CERDYIE_0 => false,
CERDYIEW::CERDYIE_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CERDYIEW<'a> {
w: &'a mut W,
}
impl<'a> _CERDYIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CERDYIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Interrupt disabled"]
#[inline]
pub fn cerdyie_0(self) -> &'a mut W {
self.variant(CERDYIEW::CERDYIE_0)
}
#[doc = "Interrupt enabled"]
#[inline]
pub fn cerdyie_1(self) -> &'a mut W {
self.variant(CERDYIEW::CERDYIE_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
#[doc = "Bit 0 - Comparator output interrupt flag"]
#[inline]
pub fn ceifg(&self) -> CEIFGR {
CEIFGR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u16) != 0
})
}
#[doc = "Bit 1 - Comparator output inverted interrupt flag"]
#[inline]
pub fn ceiifg(&self) -> CEIIFGR {
CEIIFGR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u16) != 0
})
}
#[doc = "Bit 4 - Comparator ready interrupt flag"]
#[inline]
pub fn cerdyifg(&self) -> CERDYIFGR {
CERDYIFGR::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u16) != 0
})
}
#[doc = "Bit 8 - Comparator output interrupt enable"]
#[inline]
pub fn ceie(&self) -> CEIER {
CEIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u16) != 0
})
}
#[doc = "Bit 9 - Comparator output interrupt enable inverted polarity"]
#[inline]
pub fn ceiie(&self) -> CEIIER {
CEIIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u16) != 0
})
}
#[doc = "Bit 12 - Comparator ready interrupt enable"]
#[inline]
pub fn cerdyie(&self) -> CERDYIER {
CERDYIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u16) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Comparator output interrupt flag"]
#[inline]
pub fn ceifg(&mut self) -> _CEIFGW {
_CEIFGW { w: self }
}
#[doc = "Bit 1 - Comparator output inverted interrupt flag"]
#[inline]
pub fn ceiifg(&mut self) -> _CEIIFGW {
_CEIIFGW { w: self }
}
#[doc = "Bit 4 - Comparator ready interrupt flag"]
#[inline]
pub fn cerdyifg(&mut self) -> _CERDYIFGW {
_CERDYIFGW { w: self }
}
#[doc = "Bit 8 - Comparator output interrupt enable"]
#[inline]
pub fn ceie(&mut self) -> _CEIEW {
_CEIEW { w: self }
}
#[doc = "Bit 9 - Comparator output interrupt enable inverted polarity"]
#[inline]
pub fn ceiie(&mut self) -> _CEIIEW {
_CEIIEW { w: self }
}
#[doc = "Bit 12 - Comparator ready interrupt enable"]
#[inline]
pub fn cerdyie(&mut self) -> _CERDYIEW {
_CERDYIEW { w: self }
}
}

88
example-source/msp432p401r/src/comp_e1/cex_iv.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u16,
}
impl super::CEXIV {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = "Possible values of the field `CEIV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CEIVR {
#[doc = "No interrupt pending"]
CEIV_0,
#[doc = "Interrupt Source: CEOUT interrupt; Interrupt Flag: CEIFG; Interrupt Priority: Highest"]
CEIV_2,
#[doc = "Interrupt Source: CEOUT interrupt inverted polarity; Interrupt Flag: CEIIFG"]
CEIV_4,
#[doc = "Interrupt Source: Comparator ready interrupt; Interrupt Flag: CERDYIFG; Interrupt Priority: Lowest"]
CEIV_10,
#[doc = r" Reserved"]
_Reserved(u16),
}
impl CEIVR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
match *self {
CEIVR::CEIV_0 => 0,
CEIVR::CEIV_2 => 2,
CEIVR::CEIV_4 => 4,
CEIVR::CEIV_10 => 10,
CEIVR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u16) -> CEIVR {
match value {
0 => CEIVR::CEIV_0,
2 => CEIVR::CEIV_2,
4 => CEIVR::CEIV_4,
10 => CEIVR::CEIV_10,
i => CEIVR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `CEIV_0`"]
#[inline]
pub fn is_ceiv_0(&self) -> bool {
*self == CEIVR::CEIV_0
}
#[doc = "Checks if the value of the field is `CEIV_2`"]
#[inline]
pub fn is_ceiv_2(&self) -> bool {
*self == CEIVR::CEIV_2
}
#[doc = "Checks if the value of the field is `CEIV_4`"]
#[inline]
pub fn is_ceiv_4(&self) -> bool {
*self == CEIVR::CEIV_4
}
#[doc = "Checks if the value of the field is `CEIV_10`"]
#[inline]
pub fn is_ceiv_10(&self) -> bool {
*self == CEIVR::CEIV_10
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
#[doc = "Bits 0:15 - Comparator interrupt vector word register"]
#[inline]
pub fn ceiv(&self) -> CEIVR {
CEIVR::_from({
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u16) as u16
})
}
}

89
example-source/msp432p401r/src/crc32.rs Normal file
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#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Data Input for CRC32 Signature Computation"]
pub crc32di: CRC32DI,
_reserved0: [u8; 2usize],
#[doc = "0x04 - Data In Reverse for CRC32 Computation"]
pub crc32dirb: CRC32DIRB,
_reserved1: [u8; 2usize],
#[doc = "0x08 - CRC32 Initialization and Result, lower 16 bits"]
pub crc32inires_lo: CRC32INIRES_LO,
#[doc = "0x0a - CRC32 Initialization and Result, upper 16 bits"]
pub crc32inires_hi: CRC32INIRES_HI,
#[doc = "0x0c - CRC32 Result Reverse, lower 16 bits"]
pub crc32resr_lo: CRC32RESR_LO,
#[doc = "0x0e - CRC32 Result Reverse, Upper 16 bits"]
pub crc32resr_hi: CRC32RESR_HI,
#[doc = "0x10 - Data Input for CRC16 computation"]
pub crc16di: CRC16DI,
_reserved2: [u8; 2usize],
#[doc = "0x14 - CRC16 Data In Reverse"]
pub crc16dirb: CRC16DIRB,
_reserved3: [u8; 2usize],
#[doc = "0x18 - CRC16 Initialization and Result register"]
pub crc16inires: CRC16INIRES,
_reserved4: [u8; 4usize],
#[doc = "0x1e - CRC16 Result Reverse"]
pub crc16resr: CRC16RESR,
}
#[doc = "Data Input for CRC32 Signature Computation"]
pub struct CRC32DI {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Data Input for CRC32 Signature Computation"]
pub mod crc32di;
#[doc = "Data In Reverse for CRC32 Computation"]
pub struct CRC32DIRB {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Data In Reverse for CRC32 Computation"]
pub mod crc32dirb;
#[doc = "CRC32 Initialization and Result, lower 16 bits"]
pub struct CRC32INIRES_LO {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "CRC32 Initialization and Result, lower 16 bits"]
pub mod crc32inires_lo;
#[doc = "CRC32 Initialization and Result, upper 16 bits"]
pub struct CRC32INIRES_HI {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "CRC32 Initialization and Result, upper 16 bits"]
pub mod crc32inires_hi;
#[doc = "CRC32 Result Reverse, lower 16 bits"]
pub struct CRC32RESR_LO {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "CRC32 Result Reverse, lower 16 bits"]
pub mod crc32resr_lo;
#[doc = "CRC32 Result Reverse, Upper 16 bits"]
pub struct CRC32RESR_HI {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "CRC32 Result Reverse, Upper 16 bits"]
pub mod crc32resr_hi;
#[doc = "Data Input for CRC16 computation"]
pub struct CRC16DI {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Data Input for CRC16 computation"]
pub mod crc16di;
#[doc = "CRC16 Data In Reverse"]
pub struct CRC16DIRB {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "CRC16 Data In Reverse"]
pub mod crc16dirb;
#[doc = "CRC16 Initialization and Result register"]
pub struct CRC16INIRES {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "CRC16 Initialization and Result register"]
pub mod crc16inires;
#[doc = "CRC16 Result Reverse"]
pub struct CRC16RESR {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "CRC16 Result Reverse"]
pub mod crc16resr;

105
example-source/msp432p401r/src/crc32/crc16di.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u16,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u16,
}
impl super::CRC16DI {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CRC16DIR {
bits: u16,
}
impl CRC16DIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CRC16DIW<'a> {
w: &'a mut W,
}
impl<'a> _CRC16DIW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
#[doc = "Bits 0:15 - CRC16 data in"]
#[inline]
pub fn crc16di(&self) -> CRC16DIR {
let bits = {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u16) as u16
};
CRC16DIR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - CRC16 data in"]
#[inline]
pub fn crc16di(&mut self) -> _CRC16DIW {
_CRC16DIW { w: self }
}
}

105
example-source/msp432p401r/src/crc32/crc16dirb.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u16,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u16,
}
impl super::CRC16DIRB {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CRC16DIRBR {
bits: u16,
}
impl CRC16DIRBR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CRC16DIRBW<'a> {
w: &'a mut W,
}
impl<'a> _CRC16DIRBW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
#[doc = "Bits 0:15 - CRC16 data in reverse byte"]
#[inline]
pub fn crc16dirb(&self) -> CRC16DIRBR {
let bits = {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u16) as u16
};
CRC16DIRBR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - CRC16 data in reverse byte"]
#[inline]
pub fn crc16dirb(&mut self) -> _CRC16DIRBW {
_CRC16DIRBW { w: self }
}
}

105
example-source/msp432p401r/src/crc32/crc16inires.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u16,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u16,
}
impl super::CRC16INIRES {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CRC16INIRESR {
bits: u16,
}
impl CRC16INIRESR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CRC16INIRESW<'a> {
w: &'a mut W,
}
impl<'a> _CRC16INIRESW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
#[doc = "Bits 0:15 - CRC16 initialization and result"]
#[inline]
pub fn crc16inires(&self) -> CRC16INIRESR {
let bits = {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u16) as u16
};
CRC16INIRESR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 65535 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - CRC16 initialization and result"]
#[inline]
pub fn crc16inires(&mut self) -> _CRC16INIRESW {
_CRC16INIRESW { w: self }
}
}

105
example-source/msp432p401r/src/crc32/crc16resr.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u16,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u16,
}
impl super::CRC16RESR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CRC16RESRR {
bits: u16,
}
impl CRC16RESRR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CRC16RESRW<'a> {
w: &'a mut W,
}
impl<'a> _CRC16RESRW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
#[doc = "Bits 0:15 - CRC16 reverse result"]
#[inline]
pub fn crc16resr(&self) -> CRC16RESRR {
let bits = {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u16) as u16
};
CRC16RESRR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 65535 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - CRC16 reverse result"]
#[inline]
pub fn crc16resr(&mut self) -> _CRC16RESRW {
_CRC16RESRW { w: self }
}
}

105
example-source/msp432p401r/src/crc32/crc32di.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u16,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u16,
}
impl super::CRC32DI {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CRC32DIR {
bits: u16,
}
impl CRC32DIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CRC32DIW<'a> {
w: &'a mut W,
}
impl<'a> _CRC32DIW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
#[doc = "Bits 0:15 - Data input register"]
#[inline]
pub fn crc32di(&self) -> CRC32DIR {
let bits = {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u16) as u16
};
CRC32DIR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - Data input register"]
#[inline]
pub fn crc32di(&mut self) -> _CRC32DIW {
_CRC32DIW { w: self }
}
}

105
example-source/msp432p401r/src/crc32/crc32dirb.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u16,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u16,
}
impl super::CRC32DIRB {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CRC32DIRBR {
bits: u16,
}
impl CRC32DIRBR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CRC32DIRBW<'a> {
w: &'a mut W,
}
impl<'a> _CRC32DIRBW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
#[doc = "Bits 0:15 - Data input register reversed"]
#[inline]
pub fn crc32dirb(&self) -> CRC32DIRBR {
let bits = {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u16) as u16
};
CRC32DIRBR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - Data input register reversed"]
#[inline]
pub fn crc32dirb(&mut self) -> _CRC32DIRBW {
_CRC32DIRBW { w: self }
}
}

105
example-source/msp432p401r/src/crc32/crc32inires_hi.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u16,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u16,
}
impl super::CRC32INIRES_HI {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CRC32INIRES_HIR {
bits: u16,
}
impl CRC32INIRES_HIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CRC32INIRES_HIW<'a> {
w: &'a mut W,
}
impl<'a> _CRC32INIRES_HIW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
#[doc = "Bits 0:15 - CRC32 initialization and result, upper 16 bits"]
#[inline]
pub fn crc32inires_hi(&self) -> CRC32INIRES_HIR {
let bits = {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u16) as u16
};
CRC32INIRES_HIR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - CRC32 initialization and result, upper 16 bits"]
#[inline]
pub fn crc32inires_hi(&mut self) -> _CRC32INIRES_HIW {
_CRC32INIRES_HIW { w: self }
}
}

105
example-source/msp432p401r/src/crc32/crc32inires_lo.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u16,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u16,
}
impl super::CRC32INIRES_LO {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CRC32INIRES_LOR {
bits: u16,
}
impl CRC32INIRES_LOR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CRC32INIRES_LOW<'a> {
w: &'a mut W,
}
impl<'a> _CRC32INIRES_LOW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
#[doc = "Bits 0:15 - CRC32 initialization and result, lower 16 bits"]
#[inline]
pub fn crc32inires_lo(&self) -> CRC32INIRES_LOR {
let bits = {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u16) as u16
};
CRC32INIRES_LOR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - CRC32 initialization and result, lower 16 bits"]
#[inline]
pub fn crc32inires_lo(&mut self) -> _CRC32INIRES_LOW {
_CRC32INIRES_LOW { w: self }
}
}

105
example-source/msp432p401r/src/crc32/crc32resr_hi.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u16,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u16,
}
impl super::CRC32RESR_HI {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CRC32RESR_HIR {
bits: u16,
}
impl CRC32RESR_HIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CRC32RESR_HIW<'a> {
w: &'a mut W,
}
impl<'a> _CRC32RESR_HIW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
#[doc = "Bits 0:15 - CRC32 reverse result, upper 16 bits"]
#[inline]
pub fn crc32resr_hi(&self) -> CRC32RESR_HIR {
let bits = {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u16) as u16
};
CRC32RESR_HIR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 65535 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - CRC32 reverse result, upper 16 bits"]
#[inline]
pub fn crc32resr_hi(&mut self) -> _CRC32RESR_HIW {
_CRC32RESR_HIW { w: self }
}
}

105
example-source/msp432p401r/src/crc32/crc32resr_lo.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u16,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u16,
}
impl super::CRC32RESR_LO {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CRC32RESR_LOR {
bits: u16,
}
impl CRC32RESR_LOR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CRC32RESR_LOW<'a> {
w: &'a mut W,
}
impl<'a> _CRC32RESR_LOW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u16) << OFFSET);
self.w.bits |= ((value & MASK) as u16) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
#[doc = "Bits 0:15 - CRC32 reverse result, lower 16 bits"]
#[inline]
pub fn crc32resr_lo(&self) -> CRC32RESR_LOR {
let bits = {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u16) as u16
};
CRC32RESR_LOR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 65535 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - CRC32 reverse result, lower 16 bits"]
#[inline]
pub fn crc32resr_lo(&mut self) -> _CRC32RESR_LOW {
_CRC32RESR_LOW { w: self }
}
}

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#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Key Register"]
pub cskey: CSKEY,
#[doc = "0x04 - Control 0 Register"]
pub csctl0: CSCTL0,
#[doc = "0x08 - Control 1 Register"]
pub csctl1: CSCTL1,
#[doc = "0x0c - Control 2 Register"]
pub csctl2: CSCTL2,
#[doc = "0x10 - Control 3 Register"]
pub csctl3: CSCTL3,
_reserved0: [u8; 28usize],
#[doc = "0x30 - Clock Enable Register"]
pub csclken: CSCLKEN,
#[doc = "0x34 - Status Register"]
pub csstat: CSSTAT,
_reserved1: [u8; 8usize],
#[doc = "0x40 - Interrupt Enable Register"]
pub csie: CSIE,
_reserved2: [u8; 4usize],
#[doc = "0x48 - Interrupt Flag Register"]
pub csifg: CSIFG,
_reserved3: [u8; 4usize],
#[doc = "0x50 - Clear Interrupt Flag Register"]
pub csclrifg: CSCLRIFG,
_reserved4: [u8; 4usize],
#[doc = "0x58 - Set Interrupt Flag Register"]
pub cssetifg: CSSETIFG,
_reserved5: [u8; 4usize],
#[doc = "0x60 - DCO External Resistor Cailbration 0 Register"]
pub csdcoercal0: CSDCOERCAL0,
#[doc = "0x64 - DCO External Resistor Calibration 1 Register"]
pub csdcoercal1: CSDCOERCAL1,
}
#[doc = "Key Register"]
pub struct CSKEY {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Key Register"]
pub mod cskey;
#[doc = "Control 0 Register"]
pub struct CSCTL0 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Control 0 Register"]
pub mod csctl0;
#[doc = "Control 1 Register"]
pub struct CSCTL1 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Control 1 Register"]
pub mod csctl1;
#[doc = "Control 2 Register"]
pub struct CSCTL2 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Control 2 Register"]
pub mod csctl2;
#[doc = "Control 3 Register"]
pub struct CSCTL3 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Control 3 Register"]
pub mod csctl3;
#[doc = "Clock Enable Register"]
pub struct CSCLKEN {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Clock Enable Register"]
pub mod csclken;
#[doc = "Status Register"]
pub struct CSSTAT {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Status Register"]
pub mod csstat;
#[doc = "Interrupt Enable Register"]
pub struct CSIE {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt Enable Register"]
pub mod csie;
#[doc = "Interrupt Flag Register"]
pub struct CSIFG {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt Flag Register"]
pub mod csifg;
#[doc = "Clear Interrupt Flag Register"]
pub struct CSCLRIFG {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Clear Interrupt Flag Register"]
pub mod csclrifg;
#[doc = "Set Interrupt Flag Register"]
pub struct CSSETIFG {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Set Interrupt Flag Register"]
pub mod cssetifg;
#[doc = "DCO External Resistor Cailbration 0 Register"]
pub struct CSDCOERCAL0 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "DCO External Resistor Cailbration 0 Register"]
pub mod csdcoercal0;
#[doc = "DCO External Resistor Calibration 1 Register"]
pub struct CSDCOERCAL1 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "DCO External Resistor Calibration 1 Register"]
pub mod csdcoercal1;

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722
example-source/msp432p401r/src/cs/csclrifg.rs Normal file
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#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CSCLRIFG {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = "Values that can be written to the field `CLR_LFXTIFG`"]
pub enum CLR_LFXTIFGW {
#[doc = "No effect"]
CLR_LFXTIFG_0,
#[doc = "Clear pending interrupt flag"]
CLR_LFXTIFG_1,
}
impl CLR_LFXTIFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CLR_LFXTIFGW::CLR_LFXTIFG_0 => false,
CLR_LFXTIFGW::CLR_LFXTIFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CLR_LFXTIFGW<'a> {
w: &'a mut W,
}
impl<'a> _CLR_LFXTIFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CLR_LFXTIFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No effect"]
#[inline]
pub fn clr_lfxtifg_0(self) -> &'a mut W {
self.variant(CLR_LFXTIFGW::CLR_LFXTIFG_0)
}
#[doc = "Clear pending interrupt flag"]
#[inline]
pub fn clr_lfxtifg_1(self) -> &'a mut W {
self.variant(CLR_LFXTIFGW::CLR_LFXTIFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CLR_HFXTIFG`"]
pub enum CLR_HFXTIFGW {
#[doc = "No effect"]
CLR_HFXTIFG_0,
#[doc = "Clear pending interrupt flag"]
CLR_HFXTIFG_1,
}
impl CLR_HFXTIFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CLR_HFXTIFGW::CLR_HFXTIFG_0 => false,
CLR_HFXTIFGW::CLR_HFXTIFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CLR_HFXTIFGW<'a> {
w: &'a mut W,
}
impl<'a> _CLR_HFXTIFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CLR_HFXTIFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No effect"]
#[inline]
pub fn clr_hfxtifg_0(self) -> &'a mut W {
self.variant(CLR_HFXTIFGW::CLR_HFXTIFG_0)
}
#[doc = "Clear pending interrupt flag"]
#[inline]
pub fn clr_hfxtifg_1(self) -> &'a mut W {
self.variant(CLR_HFXTIFGW::CLR_HFXTIFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CLR_HFXT2IFG`"]
pub enum CLR_HFXT2IFGW {
#[doc = "No effect"]
CLR_HFXT2IFG_0,
#[doc = "Clear pending interrupt flag"]
CLR_HFXT2IFG_1,
}
impl CLR_HFXT2IFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CLR_HFXT2IFGW::CLR_HFXT2IFG_0 => false,
CLR_HFXT2IFGW::CLR_HFXT2IFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CLR_HFXT2IFGW<'a> {
w: &'a mut W,
}
impl<'a> _CLR_HFXT2IFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CLR_HFXT2IFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No effect"]
#[inline]
pub fn clr_hfxt2ifg_0(self) -> &'a mut W {
self.variant(CLR_HFXT2IFGW::CLR_HFXT2IFG_0)
}
#[doc = "Clear pending interrupt flag"]
#[inline]
pub fn clr_hfxt2ifg_1(self) -> &'a mut W {
self.variant(CLR_HFXT2IFGW::CLR_HFXT2IFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CLR_DCOR_OPNIFG`"]
pub enum CLR_DCOR_OPNIFGW {
#[doc = "No effect"]
CLR_DCOR_OPNIFG_0,
#[doc = "Clear pending interrupt flag"]
CLR_DCOR_OPNIFG_1,
}
impl CLR_DCOR_OPNIFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CLR_DCOR_OPNIFGW::CLR_DCOR_OPNIFG_0 => false,
CLR_DCOR_OPNIFGW::CLR_DCOR_OPNIFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CLR_DCOR_OPNIFGW<'a> {
w: &'a mut W,
}
impl<'a> _CLR_DCOR_OPNIFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CLR_DCOR_OPNIFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No effect"]
#[inline]
pub fn clr_dcor_opnifg_0(self) -> &'a mut W {
self.variant(CLR_DCOR_OPNIFGW::CLR_DCOR_OPNIFG_0)
}
#[doc = "Clear pending interrupt flag"]
#[inline]
pub fn clr_dcor_opnifg_1(self) -> &'a mut W {
self.variant(CLR_DCOR_OPNIFGW::CLR_DCOR_OPNIFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CLR_CALIFG`"]
pub enum CLR_CALIFGW {
#[doc = "No effect"]
CLR_CALIFG_0,
#[doc = "Clear pending interrupt flag"]
CLR_CALIFG_1,
}
impl CLR_CALIFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CLR_CALIFGW::CLR_CALIFG_0 => false,
CLR_CALIFGW::CLR_CALIFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CLR_CALIFGW<'a> {
w: &'a mut W,
}
impl<'a> _CLR_CALIFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CLR_CALIFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No effect"]
#[inline]
pub fn clr_califg_0(self) -> &'a mut W {
self.variant(CLR_CALIFGW::CLR_CALIFG_0)
}
#[doc = "Clear pending interrupt flag"]
#[inline]
pub fn clr_califg_1(self) -> &'a mut W {
self.variant(CLR_CALIFGW::CLR_CALIFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CLR_FCNTLFIFG`"]
pub enum CLR_FCNTLFIFGW {
#[doc = "No effect"]
CLR_FCNTLFIFG_0,
#[doc = "Clear pending interrupt flag"]
CLR_FCNTLFIFG_1,
}
impl CLR_FCNTLFIFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CLR_FCNTLFIFGW::CLR_FCNTLFIFG_0 => false,
CLR_FCNTLFIFGW::CLR_FCNTLFIFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CLR_FCNTLFIFGW<'a> {
w: &'a mut W,
}
impl<'a> _CLR_FCNTLFIFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CLR_FCNTLFIFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No effect"]
#[inline]
pub fn clr_fcntlfifg_0(self) -> &'a mut W {
self.variant(CLR_FCNTLFIFGW::CLR_FCNTLFIFG_0)
}
#[doc = "Clear pending interrupt flag"]
#[inline]
pub fn clr_fcntlfifg_1(self) -> &'a mut W {
self.variant(CLR_FCNTLFIFGW::CLR_FCNTLFIFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CLR_FCNTHFIFG`"]
pub enum CLR_FCNTHFIFGW {
#[doc = "No effect"]
CLR_FCNTHFIFG_0,
#[doc = "Clear pending interrupt flag"]
CLR_FCNTHFIFG_1,
}
impl CLR_FCNTHFIFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CLR_FCNTHFIFGW::CLR_FCNTHFIFG_0 => false,
CLR_FCNTHFIFGW::CLR_FCNTHFIFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CLR_FCNTHFIFGW<'a> {
w: &'a mut W,
}
impl<'a> _CLR_FCNTHFIFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CLR_FCNTHFIFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No effect"]
#[inline]
pub fn clr_fcnthfifg_0(self) -> &'a mut W {
self.variant(CLR_FCNTHFIFGW::CLR_FCNTHFIFG_0)
}
#[doc = "Clear pending interrupt flag"]
#[inline]
pub fn clr_fcnthfifg_1(self) -> &'a mut W {
self.variant(CLR_FCNTHFIFGW::CLR_FCNTHFIFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CLR_FCNTHF2IFG`"]
pub enum CLR_FCNTHF2IFGW {
#[doc = "No effect"]
CLR_FCNTHF2IFG_0,
#[doc = "Clear pending interrupt flag"]
CLR_FCNTHF2IFG_1,
}
impl CLR_FCNTHF2IFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CLR_FCNTHF2IFGW::CLR_FCNTHF2IFG_0 => false,
CLR_FCNTHF2IFGW::CLR_FCNTHF2IFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CLR_FCNTHF2IFGW<'a> {
w: &'a mut W,
}
impl<'a> _CLR_FCNTHF2IFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CLR_FCNTHF2IFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No effect"]
#[inline]
pub fn clr_fcnthf2ifg_0(self) -> &'a mut W {
self.variant(CLR_FCNTHF2IFGW::CLR_FCNTHF2IFG_0)
}
#[doc = "Clear pending interrupt flag"]
#[inline]
pub fn clr_fcnthf2ifg_1(self) -> &'a mut W {
self.variant(CLR_FCNTHF2IFGW::CLR_FCNTHF2IFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CLR_PLLOOLIFG`"]
pub enum CLR_PLLOOLIFGW {
#[doc = "No effect"]
CLR_PLLOOLIFG_0,
#[doc = "Clear pending interrupt flag"]
CLR_PLLOOLIFG_1,
}
impl CLR_PLLOOLIFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CLR_PLLOOLIFGW::CLR_PLLOOLIFG_0 => false,
CLR_PLLOOLIFGW::CLR_PLLOOLIFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CLR_PLLOOLIFGW<'a> {
w: &'a mut W,
}
impl<'a> _CLR_PLLOOLIFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CLR_PLLOOLIFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No effect"]
#[inline]
pub fn clr_plloolifg_0(self) -> &'a mut W {
self.variant(CLR_PLLOOLIFGW::CLR_PLLOOLIFG_0)
}
#[doc = "Clear pending interrupt flag"]
#[inline]
pub fn clr_plloolifg_1(self) -> &'a mut W {
self.variant(CLR_PLLOOLIFGW::CLR_PLLOOLIFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CLR_PLLLOSIFG`"]
pub enum CLR_PLLLOSIFGW {
#[doc = "No effect"]
CLR_PLLLOSIFG_0,
#[doc = "Clear pending interrupt flag"]
CLR_PLLLOSIFG_1,
}
impl CLR_PLLLOSIFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CLR_PLLLOSIFGW::CLR_PLLLOSIFG_0 => false,
CLR_PLLLOSIFGW::CLR_PLLLOSIFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CLR_PLLLOSIFGW<'a> {
w: &'a mut W,
}
impl<'a> _CLR_PLLLOSIFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CLR_PLLLOSIFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No effect"]
#[inline]
pub fn clr_plllosifg_0(self) -> &'a mut W {
self.variant(CLR_PLLLOSIFGW::CLR_PLLLOSIFG_0)
}
#[doc = "Clear pending interrupt flag"]
#[inline]
pub fn clr_plllosifg_1(self) -> &'a mut W {
self.variant(CLR_PLLLOSIFGW::CLR_PLLLOSIFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CLR_PLLOORIFG`"]
pub enum CLR_PLLOORIFGW {
#[doc = "No effect"]
CLR_PLLOORIFG_0,
#[doc = "Clear pending interrupt flag"]
CLR_PLLOORIFG_1,
}
impl CLR_PLLOORIFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CLR_PLLOORIFGW::CLR_PLLOORIFG_0 => false,
CLR_PLLOORIFGW::CLR_PLLOORIFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CLR_PLLOORIFGW<'a> {
w: &'a mut W,
}
impl<'a> _CLR_PLLOORIFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CLR_PLLOORIFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No effect"]
#[inline]
pub fn clr_plloorifg_0(self) -> &'a mut W {
self.variant(CLR_PLLOORIFGW::CLR_PLLOORIFG_0)
}
#[doc = "Clear pending interrupt flag"]
#[inline]
pub fn clr_plloorifg_1(self) -> &'a mut W {
self.variant(CLR_PLLOORIFGW::CLR_PLLOORIFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Clear LFXT oscillator fault interrupt flag"]
#[inline]
pub fn clr_lfxtifg(&mut self) -> _CLR_LFXTIFGW {
_CLR_LFXTIFGW { w: self }
}
#[doc = "Bit 1 - Clear HFXT oscillator fault interrupt flag"]
#[inline]
pub fn clr_hfxtifg(&mut self) -> _CLR_HFXTIFGW {
_CLR_HFXTIFGW { w: self }
}
#[doc = "Bit 2 - Clear HFXT2 oscillator fault interrupt flag"]
#[inline]
pub fn clr_hfxt2ifg(&mut self) -> _CLR_HFXT2IFGW {
_CLR_HFXT2IFGW { w: self }
}
#[doc = "Bit 6 - Clear DCO external resistor open circuit fault interrupt flag."]
#[inline]
pub fn clr_dcor_opnifg(&mut self) -> _CLR_DCOR_OPNIFGW {
_CLR_DCOR_OPNIFGW { w: self }
}
#[doc = "Bit 15 - REFCNT period counter clear interrupt flag"]
#[inline]
pub fn clr_califg(&mut self) -> _CLR_CALIFGW {
_CLR_CALIFGW { w: self }
}
#[doc = "Bit 8 - Start fault counter clear interrupt flag LFXT"]
#[inline]
pub fn clr_fcntlfifg(&mut self) -> _CLR_FCNTLFIFGW {
_CLR_FCNTLFIFGW { w: self }
}
#[doc = "Bit 9 - Start fault counter clear interrupt flag HFXT"]
#[inline]
pub fn clr_fcnthfifg(&mut self) -> _CLR_FCNTHFIFGW {
_CLR_FCNTHFIFGW { w: self }
}
#[doc = "Bit 10 - Start fault counter clear interrupt flag HFXT2"]
#[inline]
pub fn clr_fcnthf2ifg(&mut self) -> _CLR_FCNTHF2IFGW {
_CLR_FCNTHF2IFGW { w: self }
}
#[doc = "Bit 12 - PLL out-of-lock clear interrupt flag"]
#[inline]
pub fn clr_plloolifg(&mut self) -> _CLR_PLLOOLIFGW {
_CLR_PLLOOLIFGW { w: self }
}
#[doc = "Bit 13 - PLL loss-of-signal clear interrupt flag"]
#[inline]
pub fn clr_plllosifg(&mut self) -> _CLR_PLLLOSIFGW {
_CLR_PLLLOSIFGW { w: self }
}
#[doc = "Bit 14 - PLL out-of-range clear interrupt flag"]
#[inline]
pub fn clr_plloorifg(&mut self) -> _CLR_PLLOORIFGW {
_CLR_PLLOORIFGW { w: self }
}
}

514
example-source/msp432p401r/src/cs/csctl0.rs Normal file
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@@ -0,0 +1,514 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CSCTL0 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DCOTUNER {
bits: u16,
}
impl DCOTUNER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = "Possible values of the field `DCORSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DCORSELR {
#[doc = "Nominal DCO Frequency Range (MHz): 1 to 2"]
DCORSEL_0,
#[doc = "Nominal DCO Frequency Range (MHz): 2 to 4"]
DCORSEL_1,
#[doc = "Nominal DCO Frequency Range (MHz): 4 to 8"]
DCORSEL_2,
#[doc = "Nominal DCO Frequency Range (MHz): 8 to 16"]
DCORSEL_3,
#[doc = "Nominal DCO Frequency Range (MHz): 16 to 32"]
DCORSEL_4,
#[doc = "Nominal DCO Frequency Range (MHz): 32 to 64"]
DCORSEL_5,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl DCORSELR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
DCORSELR::DCORSEL_0 => 0,
DCORSELR::DCORSEL_1 => 1,
DCORSELR::DCORSEL_2 => 2,
DCORSELR::DCORSEL_3 => 3,
DCORSELR::DCORSEL_4 => 4,
DCORSELR::DCORSEL_5 => 5,
DCORSELR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> DCORSELR {
match value {
0 => DCORSELR::DCORSEL_0,
1 => DCORSELR::DCORSEL_1,
2 => DCORSELR::DCORSEL_2,
3 => DCORSELR::DCORSEL_3,
4 => DCORSELR::DCORSEL_4,
5 => DCORSELR::DCORSEL_5,
i => DCORSELR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `DCORSEL_0`"]
#[inline]
pub fn is_dcorsel_0(&self) -> bool {
*self == DCORSELR::DCORSEL_0
}
#[doc = "Checks if the value of the field is `DCORSEL_1`"]
#[inline]
pub fn is_dcorsel_1(&self) -> bool {
*self == DCORSELR::DCORSEL_1
}
#[doc = "Checks if the value of the field is `DCORSEL_2`"]
#[inline]
pub fn is_dcorsel_2(&self) -> bool {
*self == DCORSELR::DCORSEL_2
}
#[doc = "Checks if the value of the field is `DCORSEL_3`"]
#[inline]
pub fn is_dcorsel_3(&self) -> bool {
*self == DCORSELR::DCORSEL_3
}
#[doc = "Checks if the value of the field is `DCORSEL_4`"]
#[inline]
pub fn is_dcorsel_4(&self) -> bool {
*self == DCORSELR::DCORSEL_4
}
#[doc = "Checks if the value of the field is `DCORSEL_5`"]
#[inline]
pub fn is_dcorsel_5(&self) -> bool {
*self == DCORSELR::DCORSEL_5
}
}
#[doc = "Possible values of the field `DCORES`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DCORESR {
#[doc = "Internal resistor mode"]
DCORES_0,
#[doc = "External resistor mode"]
DCORES_1,
}
impl DCORESR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DCORESR::DCORES_0 => false,
DCORESR::DCORES_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DCORESR {
match value {
false => DCORESR::DCORES_0,
true => DCORESR::DCORES_1,
}
}
#[doc = "Checks if the value of the field is `DCORES_0`"]
#[inline]
pub fn is_dcores_0(&self) -> bool {
*self == DCORESR::DCORES_0
}
#[doc = "Checks if the value of the field is `DCORES_1`"]
#[inline]
pub fn is_dcores_1(&self) -> bool {
*self == DCORESR::DCORES_1
}
}
#[doc = "Possible values of the field `DCOEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DCOENR {
#[doc = "DCO is on if it is used as a source for MCLK, HSMCLK , or SMCLK and clock is requested, otherwise it is disabled."]
DCOEN_0,
#[doc = "DCO is on"]
DCOEN_1,
}
impl DCOENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DCOENR::DCOEN_0 => false,
DCOENR::DCOEN_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DCOENR {
match value {
false => DCOENR::DCOEN_0,
true => DCOENR::DCOEN_1,
}
}
#[doc = "Checks if the value of the field is `DCOEN_0`"]
#[inline]
pub fn is_dcoen_0(&self) -> bool {
*self == DCOENR::DCOEN_0
}
#[doc = "Checks if the value of the field is `DCOEN_1`"]
#[inline]
pub fn is_dcoen_1(&self) -> bool {
*self == DCOENR::DCOEN_1
}
}
#[doc = r" Proxy"]
pub struct _DCOTUNEW<'a> {
w: &'a mut W,
}
impl<'a> _DCOTUNEW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 1023;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `DCORSEL`"]
pub enum DCORSELW {
#[doc = "Nominal DCO Frequency Range (MHz): 1 to 2"]
DCORSEL_0,
#[doc = "Nominal DCO Frequency Range (MHz): 2 to 4"]
DCORSEL_1,
#[doc = "Nominal DCO Frequency Range (MHz): 4 to 8"]
DCORSEL_2,
#[doc = "Nominal DCO Frequency Range (MHz): 8 to 16"]
DCORSEL_3,
#[doc = "Nominal DCO Frequency Range (MHz): 16 to 32"]
DCORSEL_4,
#[doc = "Nominal DCO Frequency Range (MHz): 32 to 64"]
DCORSEL_5,
}
impl DCORSELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
DCORSELW::DCORSEL_0 => 0,
DCORSELW::DCORSEL_1 => 1,
DCORSELW::DCORSEL_2 => 2,
DCORSELW::DCORSEL_3 => 3,
DCORSELW::DCORSEL_4 => 4,
DCORSELW::DCORSEL_5 => 5,
}
}
}
#[doc = r" Proxy"]
pub struct _DCORSELW<'a> {
w: &'a mut W,
}
impl<'a> _DCORSELW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: DCORSELW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "Nominal DCO Frequency Range (MHz): 1 to 2"]
#[inline]
pub fn dcorsel_0(self) -> &'a mut W {
self.variant(DCORSELW::DCORSEL_0)
}
#[doc = "Nominal DCO Frequency Range (MHz): 2 to 4"]
#[inline]
pub fn dcorsel_1(self) -> &'a mut W {
self.variant(DCORSELW::DCORSEL_1)
}
#[doc = "Nominal DCO Frequency Range (MHz): 4 to 8"]
#[inline]
pub fn dcorsel_2(self) -> &'a mut W {
self.variant(DCORSELW::DCORSEL_2)
}
#[doc = "Nominal DCO Frequency Range (MHz): 8 to 16"]
#[inline]
pub fn dcorsel_3(self) -> &'a mut W {
self.variant(DCORSELW::DCORSEL_3)
}
#[doc = "Nominal DCO Frequency Range (MHz): 16 to 32"]
#[inline]
pub fn dcorsel_4(self) -> &'a mut W {
self.variant(DCORSELW::DCORSEL_4)
}
#[doc = "Nominal DCO Frequency Range (MHz): 32 to 64"]
#[inline]
pub fn dcorsel_5(self) -> &'a mut W {
self.variant(DCORSELW::DCORSEL_5)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 7;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `DCORES`"]
pub enum DCORESW {
#[doc = "Internal resistor mode"]
DCORES_0,
#[doc = "External resistor mode"]
DCORES_1,
}
impl DCORESW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
DCORESW::DCORES_0 => false,
DCORESW::DCORES_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _DCORESW<'a> {
w: &'a mut W,
}
impl<'a> _DCORESW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: DCORESW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Internal resistor mode"]
#[inline]
pub fn dcores_0(self) -> &'a mut W {
self.variant(DCORESW::DCORES_0)
}
#[doc = "External resistor mode"]
#[inline]
pub fn dcores_1(self) -> &'a mut W {
self.variant(DCORESW::DCORES_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `DCOEN`"]
pub enum DCOENW {
#[doc = "DCO is on if it is used as a source for MCLK, HSMCLK , or SMCLK and clock is requested, otherwise it is disabled."]
DCOEN_0,
#[doc = "DCO is on"]
DCOEN_1,
}
impl DCOENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
DCOENW::DCOEN_0 => false,
DCOENW::DCOEN_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _DCOENW<'a> {
w: &'a mut W,
}
impl<'a> _DCOENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: DCOENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "DCO is on if it is used as a source for MCLK, HSMCLK , or SMCLK and clock is requested, otherwise it is disabled."]
#[inline]
pub fn dcoen_0(self) -> &'a mut W {
self.variant(DCOENW::DCOEN_0)
}
#[doc = "DCO is on"]
#[inline]
pub fn dcoen_1(self) -> &'a mut W {
self.variant(DCOENW::DCOEN_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:9 - DCO frequency tuning select"]
#[inline]
pub fn dcotune(&self) -> DCOTUNER {
let bits = {
const MASK: u16 = 1023;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
DCOTUNER { bits }
}
#[doc = "Bits 16:18 - DCO frequency range select"]
#[inline]
pub fn dcorsel(&self) -> DCORSELR {
DCORSELR::_from({
const MASK: u8 = 7;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bit 22 - Enables the DCO external resistor mode"]
#[inline]
pub fn dcores(&self) -> DCORESR {
DCORESR::_from({
const MASK: bool = true;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 23 - Enables the DCO oscillator"]
#[inline]
pub fn dcoen(&self) -> DCOENR {
DCOENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 23;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 65536 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:9 - DCO frequency tuning select"]
#[inline]
pub fn dcotune(&mut self) -> _DCOTUNEW {
_DCOTUNEW { w: self }
}
#[doc = "Bits 16:18 - DCO frequency range select"]
#[inline]
pub fn dcorsel(&mut self) -> _DCORSELW {
_DCORSELW { w: self }
}
#[doc = "Bit 22 - Enables the DCO external resistor mode"]
#[inline]
pub fn dcores(&mut self) -> _DCORESW {
_DCORESW { w: self }
}
#[doc = "Bit 23 - Enables the DCO oscillator"]
#[inline]
pub fn dcoen(&mut self) -> _DCOENW {
_DCOENW { w: self }
}
}

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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CSDCOERCAL0 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DCO_TCCALR {
bits: u8,
}
impl DCO_TCCALR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DCO_FCAL_RSEL04R {
bits: u16,
}
impl DCO_FCAL_RSEL04R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DCO_TCCALW<'a> {
w: &'a mut W,
}
impl<'a> _DCO_TCCALW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 3;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DCO_FCAL_RSEL04W<'a> {
w: &'a mut W,
}
impl<'a> _DCO_FCAL_RSEL04W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 1023;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - DCO Temperature compensation calibration"]
#[inline]
pub fn dco_tccal(&self) -> DCO_TCCALR {
let bits = {
const MASK: u8 = 3;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DCO_TCCALR { bits }
}
#[doc = "Bits 16:25 - DCO frequency calibration for DCO frequency range (DCORSEL) 0 to 4."]
#[inline]
pub fn dco_fcal_rsel04(&self) -> DCO_FCAL_RSEL04R {
let bits = {
const MASK: u16 = 1023;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u16
};
DCO_FCAL_RSEL04R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 16777216 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - DCO Temperature compensation calibration"]
#[inline]
pub fn dco_tccal(&mut self) -> _DCO_TCCALW {
_DCO_TCCALW { w: self }
}
#[doc = "Bits 16:25 - DCO frequency calibration for DCO frequency range (DCORSEL) 0 to 4."]
#[inline]
pub fn dco_fcal_rsel04(&mut self) -> _DCO_FCAL_RSEL04W {
_DCO_FCAL_RSEL04W { w: self }
}
}

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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CSDCOERCAL1 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DCO_FCAL_RSEL5R {
bits: u16,
}
impl DCO_FCAL_RSEL5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DCO_FCAL_RSEL5W<'a> {
w: &'a mut W,
}
impl<'a> _DCO_FCAL_RSEL5W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 1023;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:9 - DCO frequency calibration for DCO frequency range (DCORSEL) 5."]
#[inline]
pub fn dco_fcal_rsel5(&self) -> DCO_FCAL_RSEL5R {
let bits = {
const MASK: u16 = 1023;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
DCO_FCAL_RSEL5R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 256 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:9 - DCO frequency calibration for DCO frequency range (DCORSEL) 5."]
#[inline]
pub fn dco_fcal_rsel5(&mut self) -> _DCO_FCAL_RSEL5W {
_DCO_FCAL_RSEL5W { w: self }
}
}

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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::CSIFG {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = "Possible values of the field `LFXTIFG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LFXTIFGR {
#[doc = "No fault condition occurred after the last reset"]
LFXTIFG_0,
#[doc = "LFXT fault. A LFXT fault occurred after the last reset"]
LFXTIFG_1,
}
impl LFXTIFGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
LFXTIFGR::LFXTIFG_0 => false,
LFXTIFGR::LFXTIFG_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> LFXTIFGR {
match value {
false => LFXTIFGR::LFXTIFG_0,
true => LFXTIFGR::LFXTIFG_1,
}
}
#[doc = "Checks if the value of the field is `LFXTIFG_0`"]
#[inline]
pub fn is_lfxtifg_0(&self) -> bool {
*self == LFXTIFGR::LFXTIFG_0
}
#[doc = "Checks if the value of the field is `LFXTIFG_1`"]
#[inline]
pub fn is_lfxtifg_1(&self) -> bool {
*self == LFXTIFGR::LFXTIFG_1
}
}
#[doc = "Possible values of the field `HFXTIFG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum HFXTIFGR {
#[doc = "No fault condition occurred after the last reset"]
HFXTIFG_0,
#[doc = "HFXT fault. A HFXT fault occurred after the last reset"]
HFXTIFG_1,
}
impl HFXTIFGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
HFXTIFGR::HFXTIFG_0 => false,
HFXTIFGR::HFXTIFG_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> HFXTIFGR {
match value {
false => HFXTIFGR::HFXTIFG_0,
true => HFXTIFGR::HFXTIFG_1,
}
}
#[doc = "Checks if the value of the field is `HFXTIFG_0`"]
#[inline]
pub fn is_hfxtifg_0(&self) -> bool {
*self == HFXTIFGR::HFXTIFG_0
}
#[doc = "Checks if the value of the field is `HFXTIFG_1`"]
#[inline]
pub fn is_hfxtifg_1(&self) -> bool {
*self == HFXTIFGR::HFXTIFG_1
}
}
#[doc = "Possible values of the field `HFXT2IFG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum HFXT2IFGR {
#[doc = "No fault condition occurred after the last reset"]
HFXT2IFG_0,
#[doc = "HFXT2 fault. A HFXT2 fault occurred after the last reset"]
HFXT2IFG_1,
}
impl HFXT2IFGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
HFXT2IFGR::HFXT2IFG_0 => false,
HFXT2IFGR::HFXT2IFG_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> HFXT2IFGR {
match value {
false => HFXT2IFGR::HFXT2IFG_0,
true => HFXT2IFGR::HFXT2IFG_1,
}
}
#[doc = "Checks if the value of the field is `HFXT2IFG_0`"]
#[inline]
pub fn is_hfxt2ifg_0(&self) -> bool {
*self == HFXT2IFGR::HFXT2IFG_0
}
#[doc = "Checks if the value of the field is `HFXT2IFG_1`"]
#[inline]
pub fn is_hfxt2ifg_1(&self) -> bool {
*self == HFXT2IFGR::HFXT2IFG_1
}
}
#[doc = "Possible values of the field `DCOR_SHTIFG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DCOR_SHTIFGR {
#[doc = "DCO external resistor present"]
DCOR_SHTIFG_0,
#[doc = "DCO external resistor short circuit fault"]
DCOR_SHTIFG_1,
}
impl DCOR_SHTIFGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DCOR_SHTIFGR::DCOR_SHTIFG_0 => false,
DCOR_SHTIFGR::DCOR_SHTIFG_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DCOR_SHTIFGR {
match value {
false => DCOR_SHTIFGR::DCOR_SHTIFG_0,
true => DCOR_SHTIFGR::DCOR_SHTIFG_1,
}
}
#[doc = "Checks if the value of the field is `DCOR_SHTIFG_0`"]
#[inline]
pub fn is_dcor_shtifg_0(&self) -> bool {
*self == DCOR_SHTIFGR::DCOR_SHTIFG_0
}
#[doc = "Checks if the value of the field is `DCOR_SHTIFG_1`"]
#[inline]
pub fn is_dcor_shtifg_1(&self) -> bool {
*self == DCOR_SHTIFGR::DCOR_SHTIFG_1
}
}
#[doc = "Possible values of the field `DCOR_OPNIFG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DCOR_OPNIFGR {
#[doc = "DCO external resistor present"]
DCOR_OPNIFG_0,
#[doc = "DCO external resistor open circuit fault"]
DCOR_OPNIFG_1,
}
impl DCOR_OPNIFGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DCOR_OPNIFGR::DCOR_OPNIFG_0 => false,
DCOR_OPNIFGR::DCOR_OPNIFG_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DCOR_OPNIFGR {
match value {
false => DCOR_OPNIFGR::DCOR_OPNIFG_0,
true => DCOR_OPNIFGR::DCOR_OPNIFG_1,
}
}
#[doc = "Checks if the value of the field is `DCOR_OPNIFG_0`"]
#[inline]
pub fn is_dcor_opnifg_0(&self) -> bool {
*self == DCOR_OPNIFGR::DCOR_OPNIFG_0
}
#[doc = "Checks if the value of the field is `DCOR_OPNIFG_1`"]
#[inline]
pub fn is_dcor_opnifg_1(&self) -> bool {
*self == DCOR_OPNIFGR::DCOR_OPNIFG_1
}
}
#[doc = "Possible values of the field `FCNTLFIFG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FCNTLFIFGR {
#[doc = "Start counter not expired"]
FCNTLFIFG_0,
#[doc = "Start counter expired"]
FCNTLFIFG_1,
}
impl FCNTLFIFGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
FCNTLFIFGR::FCNTLFIFG_0 => false,
FCNTLFIFGR::FCNTLFIFG_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> FCNTLFIFGR {
match value {
false => FCNTLFIFGR::FCNTLFIFG_0,
true => FCNTLFIFGR::FCNTLFIFG_1,
}
}
#[doc = "Checks if the value of the field is `FCNTLFIFG_0`"]
#[inline]
pub fn is_fcntlfifg_0(&self) -> bool {
*self == FCNTLFIFGR::FCNTLFIFG_0
}
#[doc = "Checks if the value of the field is `FCNTLFIFG_1`"]
#[inline]
pub fn is_fcntlfifg_1(&self) -> bool {
*self == FCNTLFIFGR::FCNTLFIFG_1
}
}
#[doc = "Possible values of the field `FCNTHFIFG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FCNTHFIFGR {
#[doc = "Start counter not expired"]
FCNTHFIFG_0,
#[doc = "Start counter expired"]
FCNTHFIFG_1,
}
impl FCNTHFIFGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
FCNTHFIFGR::FCNTHFIFG_0 => false,
FCNTHFIFGR::FCNTHFIFG_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> FCNTHFIFGR {
match value {
false => FCNTHFIFGR::FCNTHFIFG_0,
true => FCNTHFIFGR::FCNTHFIFG_1,
}
}
#[doc = "Checks if the value of the field is `FCNTHFIFG_0`"]
#[inline]
pub fn is_fcnthfifg_0(&self) -> bool {
*self == FCNTHFIFGR::FCNTHFIFG_0
}
#[doc = "Checks if the value of the field is `FCNTHFIFG_1`"]
#[inline]
pub fn is_fcnthfifg_1(&self) -> bool {
*self == FCNTHFIFGR::FCNTHFIFG_1
}
}
#[doc = "Possible values of the field `FCNTHF2IFG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FCNTHF2IFGR {
#[doc = "Start counter not expired"]
FCNTHF2IFG_0,
#[doc = "Start counter expired"]
FCNTHF2IFG_1,
}
impl FCNTHF2IFGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
FCNTHF2IFGR::FCNTHF2IFG_0 => false,
FCNTHF2IFGR::FCNTHF2IFG_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> FCNTHF2IFGR {
match value {
false => FCNTHF2IFGR::FCNTHF2IFG_0,
true => FCNTHF2IFGR::FCNTHF2IFG_1,
}
}
#[doc = "Checks if the value of the field is `FCNTHF2IFG_0`"]
#[inline]
pub fn is_fcnthf2ifg_0(&self) -> bool {
*self == FCNTHF2IFGR::FCNTHF2IFG_0
}
#[doc = "Checks if the value of the field is `FCNTHF2IFG_1`"]
#[inline]
pub fn is_fcnthf2ifg_1(&self) -> bool {
*self == FCNTHF2IFGR::FCNTHF2IFG_1
}
}
#[doc = "Possible values of the field `PLLOOLIFG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PLLOOLIFGR {
#[doc = "No interrupt pending"]
PLLOOLIFG_0,
#[doc = "Interrupt pending"]
PLLOOLIFG_1,
}
impl PLLOOLIFGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PLLOOLIFGR::PLLOOLIFG_0 => false,
PLLOOLIFGR::PLLOOLIFG_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PLLOOLIFGR {
match value {
false => PLLOOLIFGR::PLLOOLIFG_0,
true => PLLOOLIFGR::PLLOOLIFG_1,
}
}
#[doc = "Checks if the value of the field is `PLLOOLIFG_0`"]
#[inline]
pub fn is_plloolifg_0(&self) -> bool {
*self == PLLOOLIFGR::PLLOOLIFG_0
}
#[doc = "Checks if the value of the field is `PLLOOLIFG_1`"]
#[inline]
pub fn is_plloolifg_1(&self) -> bool {
*self == PLLOOLIFGR::PLLOOLIFG_1
}
}
#[doc = "Possible values of the field `PLLLOSIFG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PLLLOSIFGR {
#[doc = "No interrupt pending"]
PLLLOSIFG_0,
#[doc = "Interrupt pending"]
PLLLOSIFG_1,
}
impl PLLLOSIFGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PLLLOSIFGR::PLLLOSIFG_0 => false,
PLLLOSIFGR::PLLLOSIFG_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PLLLOSIFGR {
match value {
false => PLLLOSIFGR::PLLLOSIFG_0,
true => PLLLOSIFGR::PLLLOSIFG_1,
}
}
#[doc = "Checks if the value of the field is `PLLLOSIFG_0`"]
#[inline]
pub fn is_plllosifg_0(&self) -> bool {
*self == PLLLOSIFGR::PLLLOSIFG_0
}
#[doc = "Checks if the value of the field is `PLLLOSIFG_1`"]
#[inline]
pub fn is_plllosifg_1(&self) -> bool {
*self == PLLLOSIFGR::PLLLOSIFG_1
}
}
#[doc = "Possible values of the field `PLLOORIFG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PLLOORIFGR {
#[doc = "No interrupt pending"]
PLLOORIFG_0,
#[doc = "Interrupt pending"]
PLLOORIFG_1,
}
impl PLLOORIFGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PLLOORIFGR::PLLOORIFG_0 => false,
PLLOORIFGR::PLLOORIFG_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PLLOORIFGR {
match value {
false => PLLOORIFGR::PLLOORIFG_0,
true => PLLOORIFGR::PLLOORIFG_1,
}
}
#[doc = "Checks if the value of the field is `PLLOORIFG_0`"]
#[inline]
pub fn is_plloorifg_0(&self) -> bool {
*self == PLLOORIFGR::PLLOORIFG_0
}
#[doc = "Checks if the value of the field is `PLLOORIFG_1`"]
#[inline]
pub fn is_plloorifg_1(&self) -> bool {
*self == PLLOORIFGR::PLLOORIFG_1
}
}
#[doc = "Possible values of the field `CALIFG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CALIFGR {
#[doc = "REFCNT period counter not expired"]
CALIFG_0,
#[doc = "REFCNT period counter expired"]
CALIFG_1,
}
impl CALIFGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CALIFGR::CALIFG_0 => false,
CALIFGR::CALIFG_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CALIFGR {
match value {
false => CALIFGR::CALIFG_0,
true => CALIFGR::CALIFG_1,
}
}
#[doc = "Checks if the value of the field is `CALIFG_0`"]
#[inline]
pub fn is_califg_0(&self) -> bool {
*self == CALIFGR::CALIFG_0
}
#[doc = "Checks if the value of the field is `CALIFG_1`"]
#[inline]
pub fn is_califg_1(&self) -> bool {
*self == CALIFGR::CALIFG_1
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - LFXT oscillator fault flag"]
#[inline]
pub fn lfxtifg(&self) -> LFXTIFGR {
LFXTIFGR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - HFXT oscillator fault flag"]
#[inline]
pub fn hfxtifg(&self) -> HFXTIFGR {
HFXTIFGR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - HFXT2 oscillator fault flag"]
#[inline]
pub fn hfxt2ifg(&self) -> HFXT2IFGR {
HFXT2IFGR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 5 - DCO external resistor short circuit fault flag."]
#[inline]
pub fn dcor_shtifg(&self) -> DCOR_SHTIFGR {
DCOR_SHTIFGR::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 6 - DCO external resistor open circuit fault flag."]
#[inline]
pub fn dcor_opnifg(&self) -> DCOR_OPNIFGR {
DCOR_OPNIFGR::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 8 - Start fault counter interrupt flag LFXT"]
#[inline]
pub fn fcntlfifg(&self) -> FCNTLFIFGR {
FCNTLFIFGR::_from({
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 9 - Start fault counter interrupt flag HFXT"]
#[inline]
pub fn fcnthfifg(&self) -> FCNTHFIFGR {
FCNTHFIFGR::_from({
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 11 - Start fault counter interrupt flag HFXT2"]
#[inline]
pub fn fcnthf2ifg(&self) -> FCNTHF2IFGR {
FCNTHF2IFGR::_from({
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 12 - PLL out-of-lock interrupt flag"]
#[inline]
pub fn plloolifg(&self) -> PLLOOLIFGR {
PLLOOLIFGR::_from({
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 13 - PLL loss-of-signal interrupt flag"]
#[inline]
pub fn plllosifg(&self) -> PLLLOSIFGR {
PLLLOSIFGR::_from({
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 14 - PLL out-of-range interrupt flag"]
#[inline]
pub fn plloorifg(&self) -> PLLOORIFGR {
PLLOORIFGR::_from({
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 15 - REFCNT period counter expired"]
#[inline]
pub fn califg(&self) -> CALIFGR {
CALIFGR::_from({
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}

105
example-source/msp432p401r/src/cs/cskey.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CSKEY {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CSKEYR {
bits: u16,
}
impl CSKEYR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CSKEYW<'a> {
w: &'a mut W,
}
impl<'a> _CSKEYW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - Write xxxx_695Ah to unlock"]
#[inline]
pub fn cskey(&self) -> CSKEYR {
let bits = {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
CSKEYR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 42390 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - Write xxxx_695Ah to unlock"]
#[inline]
pub fn cskey(&mut self) -> _CSKEYW {
_CSKEYW { w: self }
}
}

722
example-source/msp432p401r/src/cs/cssetifg.rs Normal file
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@@ -0,0 +1,722 @@
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CSSETIFG {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = "Values that can be written to the field `SET_LFXTIFG`"]
pub enum SET_LFXTIFGW {
#[doc = "No effect"]
SET_LFXTIFG_0,
#[doc = "Set pending interrupt flag"]
SET_LFXTIFG_1,
}
impl SET_LFXTIFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SET_LFXTIFGW::SET_LFXTIFG_0 => false,
SET_LFXTIFGW::SET_LFXTIFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SET_LFXTIFGW<'a> {
w: &'a mut W,
}
impl<'a> _SET_LFXTIFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SET_LFXTIFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No effect"]
#[inline]
pub fn set_lfxtifg_0(self) -> &'a mut W {
self.variant(SET_LFXTIFGW::SET_LFXTIFG_0)
}
#[doc = "Set pending interrupt flag"]
#[inline]
pub fn set_lfxtifg_1(self) -> &'a mut W {
self.variant(SET_LFXTIFGW::SET_LFXTIFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SET_HFXTIFG`"]
pub enum SET_HFXTIFGW {
#[doc = "No effect"]
SET_HFXTIFG_0,
#[doc = "Set pending interrupt flag"]
SET_HFXTIFG_1,
}
impl SET_HFXTIFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SET_HFXTIFGW::SET_HFXTIFG_0 => false,
SET_HFXTIFGW::SET_HFXTIFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SET_HFXTIFGW<'a> {
w: &'a mut W,
}
impl<'a> _SET_HFXTIFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SET_HFXTIFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No effect"]
#[inline]
pub fn set_hfxtifg_0(self) -> &'a mut W {
self.variant(SET_HFXTIFGW::SET_HFXTIFG_0)
}
#[doc = "Set pending interrupt flag"]
#[inline]
pub fn set_hfxtifg_1(self) -> &'a mut W {
self.variant(SET_HFXTIFGW::SET_HFXTIFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SET_HFXT2IFG`"]
pub enum SET_HFXT2IFGW {
#[doc = "No effect"]
SET_HFXT2IFG_0,
#[doc = "Set pending interrupt flag"]
SET_HFXT2IFG_1,
}
impl SET_HFXT2IFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SET_HFXT2IFGW::SET_HFXT2IFG_0 => false,
SET_HFXT2IFGW::SET_HFXT2IFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SET_HFXT2IFGW<'a> {
w: &'a mut W,
}
impl<'a> _SET_HFXT2IFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SET_HFXT2IFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No effect"]
#[inline]
pub fn set_hfxt2ifg_0(self) -> &'a mut W {
self.variant(SET_HFXT2IFGW::SET_HFXT2IFG_0)
}
#[doc = "Set pending interrupt flag"]
#[inline]
pub fn set_hfxt2ifg_1(self) -> &'a mut W {
self.variant(SET_HFXT2IFGW::SET_HFXT2IFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SET_DCOR_OPNIFG`"]
pub enum SET_DCOR_OPNIFGW {
#[doc = "No effect"]
SET_DCOR_OPNIFG_0,
#[doc = "Set pending interrupt flag"]
SET_DCOR_OPNIFG_1,
}
impl SET_DCOR_OPNIFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SET_DCOR_OPNIFGW::SET_DCOR_OPNIFG_0 => false,
SET_DCOR_OPNIFGW::SET_DCOR_OPNIFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SET_DCOR_OPNIFGW<'a> {
w: &'a mut W,
}
impl<'a> _SET_DCOR_OPNIFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SET_DCOR_OPNIFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No effect"]
#[inline]
pub fn set_dcor_opnifg_0(self) -> &'a mut W {
self.variant(SET_DCOR_OPNIFGW::SET_DCOR_OPNIFG_0)
}
#[doc = "Set pending interrupt flag"]
#[inline]
pub fn set_dcor_opnifg_1(self) -> &'a mut W {
self.variant(SET_DCOR_OPNIFGW::SET_DCOR_OPNIFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SET_CALIFG`"]
pub enum SET_CALIFGW {
#[doc = "No effect"]
SET_CALIFG_0,
#[doc = "Set pending interrupt flag"]
SET_CALIFG_1,
}
impl SET_CALIFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SET_CALIFGW::SET_CALIFG_0 => false,
SET_CALIFGW::SET_CALIFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SET_CALIFGW<'a> {
w: &'a mut W,
}
impl<'a> _SET_CALIFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SET_CALIFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No effect"]
#[inline]
pub fn set_califg_0(self) -> &'a mut W {
self.variant(SET_CALIFGW::SET_CALIFG_0)
}
#[doc = "Set pending interrupt flag"]
#[inline]
pub fn set_califg_1(self) -> &'a mut W {
self.variant(SET_CALIFGW::SET_CALIFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SET_FCNTHFIFG`"]
pub enum SET_FCNTHFIFGW {
#[doc = "No effect"]
SET_FCNTHFIFG_0,
#[doc = "Set pending interrupt flag"]
SET_FCNTHFIFG_1,
}
impl SET_FCNTHFIFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SET_FCNTHFIFGW::SET_FCNTHFIFG_0 => false,
SET_FCNTHFIFGW::SET_FCNTHFIFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SET_FCNTHFIFGW<'a> {
w: &'a mut W,
}
impl<'a> _SET_FCNTHFIFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SET_FCNTHFIFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No effect"]
#[inline]
pub fn set_fcnthfifg_0(self) -> &'a mut W {
self.variant(SET_FCNTHFIFGW::SET_FCNTHFIFG_0)
}
#[doc = "Set pending interrupt flag"]
#[inline]
pub fn set_fcnthfifg_1(self) -> &'a mut W {
self.variant(SET_FCNTHFIFGW::SET_FCNTHFIFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SET_FCNTHF2IFG`"]
pub enum SET_FCNTHF2IFGW {
#[doc = "No effect"]
SET_FCNTHF2IFG_0,
#[doc = "Set pending interrupt flag"]
SET_FCNTHF2IFG_1,
}
impl SET_FCNTHF2IFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SET_FCNTHF2IFGW::SET_FCNTHF2IFG_0 => false,
SET_FCNTHF2IFGW::SET_FCNTHF2IFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SET_FCNTHF2IFGW<'a> {
w: &'a mut W,
}
impl<'a> _SET_FCNTHF2IFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SET_FCNTHF2IFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No effect"]
#[inline]
pub fn set_fcnthf2ifg_0(self) -> &'a mut W {
self.variant(SET_FCNTHF2IFGW::SET_FCNTHF2IFG_0)
}
#[doc = "Set pending interrupt flag"]
#[inline]
pub fn set_fcnthf2ifg_1(self) -> &'a mut W {
self.variant(SET_FCNTHF2IFGW::SET_FCNTHF2IFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SET_FCNTLFIFG`"]
pub enum SET_FCNTLFIFGW {
#[doc = "No effect"]
SET_FCNTLFIFG_0,
#[doc = "Set pending interrupt flag"]
SET_FCNTLFIFG_1,
}
impl SET_FCNTLFIFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SET_FCNTLFIFGW::SET_FCNTLFIFG_0 => false,
SET_FCNTLFIFGW::SET_FCNTLFIFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SET_FCNTLFIFGW<'a> {
w: &'a mut W,
}
impl<'a> _SET_FCNTLFIFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SET_FCNTLFIFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No effect"]
#[inline]
pub fn set_fcntlfifg_0(self) -> &'a mut W {
self.variant(SET_FCNTLFIFGW::SET_FCNTLFIFG_0)
}
#[doc = "Set pending interrupt flag"]
#[inline]
pub fn set_fcntlfifg_1(self) -> &'a mut W {
self.variant(SET_FCNTLFIFGW::SET_FCNTLFIFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SET_PLLOOLIFG`"]
pub enum SET_PLLOOLIFGW {
#[doc = "No effect"]
SET_PLLOOLIFG_0,
#[doc = "Set pending interrupt flag"]
SET_PLLOOLIFG_1,
}
impl SET_PLLOOLIFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SET_PLLOOLIFGW::SET_PLLOOLIFG_0 => false,
SET_PLLOOLIFGW::SET_PLLOOLIFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SET_PLLOOLIFGW<'a> {
w: &'a mut W,
}
impl<'a> _SET_PLLOOLIFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SET_PLLOOLIFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No effect"]
#[inline]
pub fn set_plloolifg_0(self) -> &'a mut W {
self.variant(SET_PLLOOLIFGW::SET_PLLOOLIFG_0)
}
#[doc = "Set pending interrupt flag"]
#[inline]
pub fn set_plloolifg_1(self) -> &'a mut W {
self.variant(SET_PLLOOLIFGW::SET_PLLOOLIFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SET_PLLLOSIFG`"]
pub enum SET_PLLLOSIFGW {
#[doc = "No effect"]
SET_PLLLOSIFG_0,
#[doc = "Set pending interrupt flag"]
SET_PLLLOSIFG_1,
}
impl SET_PLLLOSIFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SET_PLLLOSIFGW::SET_PLLLOSIFG_0 => false,
SET_PLLLOSIFGW::SET_PLLLOSIFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SET_PLLLOSIFGW<'a> {
w: &'a mut W,
}
impl<'a> _SET_PLLLOSIFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SET_PLLLOSIFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No effect"]
#[inline]
pub fn set_plllosifg_0(self) -> &'a mut W {
self.variant(SET_PLLLOSIFGW::SET_PLLLOSIFG_0)
}
#[doc = "Set pending interrupt flag"]
#[inline]
pub fn set_plllosifg_1(self) -> &'a mut W {
self.variant(SET_PLLLOSIFGW::SET_PLLLOSIFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SET_PLLOORIFG`"]
pub enum SET_PLLOORIFGW {
#[doc = "No effect"]
SET_PLLOORIFG_0,
#[doc = "Set pending interrupt flag"]
SET_PLLOORIFG_1,
}
impl SET_PLLOORIFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SET_PLLOORIFGW::SET_PLLOORIFG_0 => false,
SET_PLLOORIFGW::SET_PLLOORIFG_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SET_PLLOORIFGW<'a> {
w: &'a mut W,
}
impl<'a> _SET_PLLOORIFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SET_PLLOORIFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No effect"]
#[inline]
pub fn set_plloorifg_0(self) -> &'a mut W {
self.variant(SET_PLLOORIFGW::SET_PLLOORIFG_0)
}
#[doc = "Set pending interrupt flag"]
#[inline]
pub fn set_plloorifg_1(self) -> &'a mut W {
self.variant(SET_PLLOORIFGW::SET_PLLOORIFG_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Set LFXT oscillator fault interrupt flag"]
#[inline]
pub fn set_lfxtifg(&mut self) -> _SET_LFXTIFGW {
_SET_LFXTIFGW { w: self }
}
#[doc = "Bit 1 - Set HFXT oscillator fault interrupt flag"]
#[inline]
pub fn set_hfxtifg(&mut self) -> _SET_HFXTIFGW {
_SET_HFXTIFGW { w: self }
}
#[doc = "Bit 2 - Set HFXT2 oscillator fault interrupt flag"]
#[inline]
pub fn set_hfxt2ifg(&mut self) -> _SET_HFXT2IFGW {
_SET_HFXT2IFGW { w: self }
}
#[doc = "Bit 6 - Set DCO external resistor open circuit fault interrupt flag."]
#[inline]
pub fn set_dcor_opnifg(&mut self) -> _SET_DCOR_OPNIFGW {
_SET_DCOR_OPNIFGW { w: self }
}
#[doc = "Bit 15 - REFCNT period counter set interrupt flag"]
#[inline]
pub fn set_califg(&mut self) -> _SET_CALIFGW {
_SET_CALIFGW { w: self }
}
#[doc = "Bit 9 - Start fault counter set interrupt flag HFXT"]
#[inline]
pub fn set_fcnthfifg(&mut self) -> _SET_FCNTHFIFGW {
_SET_FCNTHFIFGW { w: self }
}
#[doc = "Bit 10 - Start fault counter set interrupt flag HFXT2"]
#[inline]
pub fn set_fcnthf2ifg(&mut self) -> _SET_FCNTHF2IFGW {
_SET_FCNTHF2IFGW { w: self }
}
#[doc = "Bit 8 - Start fault counter set interrupt flag LFXT"]
#[inline]
pub fn set_fcntlfifg(&mut self) -> _SET_FCNTLFIFGW {
_SET_FCNTLFIFGW { w: self }
}
#[doc = "Bit 12 - PLL out-of-lock set interrupt flag"]
#[inline]
pub fn set_plloolifg(&mut self) -> _SET_PLLOOLIFGW {
_SET_PLLOOLIFGW { w: self }
}
#[doc = "Bit 13 - PLL loss-of-signal set interrupt flag"]
#[inline]
pub fn set_plllosifg(&mut self) -> _SET_PLLLOSIFGW {
_SET_PLLLOSIFGW { w: self }
}
#[doc = "Bit 14 - PLL out-of-range set interrupt flag"]
#[inline]
pub fn set_plloorifg(&mut self) -> _SET_PLLOORIFGW {
_SET_PLLOORIFGW { w: self }
}
}

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example-source/msp432p401r/src/dio.rs Normal file
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#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Port A Input"]
pub pain: PAIN,
#[doc = "0x02 - Port A Output"]
pub paout: PAOUT,
#[doc = "0x04 - Port A Direction"]
pub padir: PADIR,
#[doc = "0x06 - Port A Resistor Enable"]
pub paren: PAREN,
#[doc = "0x08 - Port A Drive Strength"]
pub pads: PADS,
#[doc = "0x0a - Port A Select 0"]
pub pasel0: PASEL0,
#[doc = "0x0c - Port A Select 1"]
pub pasel1: PASEL1,
#[doc = "0x0e - Port 1 Interrupt Vector Register"]
pub p1iv: P1IV,
_reserved0: [u8; 6usize],
#[doc = "0x16 - Port A Complement Select"]
pub paselc: PASELC,
#[doc = "0x18 - Port A Interrupt Edge Select"]
pub paies: PAIES,
#[doc = "0x1a - Port A Interrupt Enable"]
pub paie: PAIE,
#[doc = "0x1c - Port A Interrupt Flag"]
pub paifg: PAIFG,
#[doc = "0x1e - Port 2 Interrupt Vector Register"]
pub p2iv: P2IV,
#[doc = "0x20 - Port B Input"]
pub pbin: PBIN,
#[doc = "0x22 - Port B Output"]
pub pbout: PBOUT,
#[doc = "0x24 - Port B Direction"]
pub pbdir: PBDIR,
#[doc = "0x26 - Port B Resistor Enable"]
pub pbren: PBREN,
#[doc = "0x28 - Port B Drive Strength"]
pub pbds: PBDS,
#[doc = "0x2a - Port B Select 0"]
pub pbsel0: PBSEL0,
#[doc = "0x2c - Port B Select 1"]
pub pbsel1: PBSEL1,
#[doc = "0x2e - Port 3 Interrupt Vector Register"]
pub p3iv: P3IV,
_reserved1: [u8; 6usize],
#[doc = "0x36 - Port B Complement Select"]
pub pbselc: PBSELC,
#[doc = "0x38 - Port B Interrupt Edge Select"]
pub pbies: PBIES,
#[doc = "0x3a - Port B Interrupt Enable"]
pub pbie: PBIE,
#[doc = "0x3c - Port B Interrupt Flag"]
pub pbifg: PBIFG,
#[doc = "0x3e - Port 4 Interrupt Vector Register"]
pub p4iv: P4IV,
#[doc = "0x40 - Port C Input"]
pub pcin: PCIN,
#[doc = "0x42 - Port C Output"]
pub pcout: PCOUT,
#[doc = "0x44 - Port C Direction"]
pub pcdir: PCDIR,
#[doc = "0x46 - Port C Resistor Enable"]
pub pcren: PCREN,
#[doc = "0x48 - Port C Drive Strength"]
pub pcds: PCDS,
#[doc = "0x4a - Port C Select 0"]
pub pcsel0: PCSEL0,
#[doc = "0x4c - Port C Select 1"]
pub pcsel1: PCSEL1,
#[doc = "0x4e - Port 5 Interrupt Vector Register"]
pub p5iv: P5IV,
_reserved2: [u8; 6usize],
#[doc = "0x56 - Port C Complement Select"]
pub pcselc: PCSELC,
#[doc = "0x58 - Port C Interrupt Edge Select"]
pub pcies: PCIES,
#[doc = "0x5a - Port C Interrupt Enable"]
pub pcie: PCIE,
#[doc = "0x5c - Port C Interrupt Flag"]
pub pcifg: PCIFG,
#[doc = "0x5e - Port 6 Interrupt Vector Register"]
pub p6iv: P6IV,
#[doc = "0x60 - Port D Input"]
pub pdin: PDIN,
#[doc = "0x62 - Port D Output"]
pub pdout: PDOUT,
#[doc = "0x64 - Port D Direction"]
pub pddir: PDDIR,
#[doc = "0x66 - Port D Resistor Enable"]
pub pdren: PDREN,
#[doc = "0x68 - Port D Drive Strength"]
pub pdds: PDDS,
#[doc = "0x6a - Port D Select 0"]
pub pdsel0: PDSEL0,
#[doc = "0x6c - Port D Select 1"]
pub pdsel1: PDSEL1,
#[doc = "0x6e - Port 7 Interrupt Vector Register"]
pub p7iv: P7IV,
_reserved3: [u8; 6usize],
#[doc = "0x76 - Port D Complement Select"]
pub pdselc: PDSELC,
#[doc = "0x78 - Port D Interrupt Edge Select"]
pub pdies: PDIES,
#[doc = "0x7a - Port D Interrupt Enable"]
pub pdie: PDIE,
#[doc = "0x7c - Port D Interrupt Flag"]
pub pdifg: PDIFG,
#[doc = "0x7e - Port 8 Interrupt Vector Register"]
pub p8iv: P8IV,
#[doc = "0x80 - Port E Input"]
pub pein: PEIN,
#[doc = "0x82 - Port E Output"]
pub peout: PEOUT,
#[doc = "0x84 - Port E Direction"]
pub pedir: PEDIR,
#[doc = "0x86 - Port E Resistor Enable"]
pub peren: PEREN,
#[doc = "0x88 - Port E Drive Strength"]
pub peds: PEDS,
#[doc = "0x8a - Port E Select 0"]
pub pesel0: PESEL0,
#[doc = "0x8c - Port E Select 1"]
pub pesel1: PESEL1,
#[doc = "0x8e - Port 9 Interrupt Vector Register"]
pub p9iv: P9IV,
_reserved4: [u8; 6usize],
#[doc = "0x96 - Port E Complement Select"]
pub peselc: PESELC,
#[doc = "0x98 - Port E Interrupt Edge Select"]
pub peies: PEIES,
#[doc = "0x9a - Port E Interrupt Enable"]
pub peie: PEIE,
#[doc = "0x9c - Port E Interrupt Flag"]
pub peifg: PEIFG,
#[doc = "0x9e - Port 10 Interrupt Vector Register"]
pub p10iv: P10IV,
_reserved5: [u8; 128usize],
#[doc = "0x120 - Port J Input"]
pub pjin: PJIN,
#[doc = "0x122 - Port J Output"]
pub pjout: PJOUT,
#[doc = "0x124 - Port J Direction"]
pub pjdir: PJDIR,
#[doc = "0x126 - Port J Resistor Enable"]
pub pjren: PJREN,
#[doc = "0x128 - Port J Drive Strength"]
pub pjds: PJDS,
#[doc = "0x12a - Port J Select 0"]
pub pjsel0: PJSEL0,
#[doc = "0x12c - Port J Select 1"]
pub pjsel1: PJSEL1,
_reserved6: [u8; 8usize],
#[doc = "0x136 - Port J Complement Select"]
pub pjselc: PJSELC,
}
#[doc = "Port A Input"]
pub struct PAIN {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port A Input"]
pub mod pain;
#[doc = "Port A Output"]
pub struct PAOUT {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port A Output"]
pub mod paout;
#[doc = "Port A Direction"]
pub struct PADIR {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port A Direction"]
pub mod padir;
#[doc = "Port A Resistor Enable"]
pub struct PAREN {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port A Resistor Enable"]
pub mod paren;
#[doc = "Port A Drive Strength"]
pub struct PADS {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port A Drive Strength"]
pub mod pads;
#[doc = "Port A Select 0"]
pub struct PASEL0 {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port A Select 0"]
pub mod pasel0;
#[doc = "Port A Select 1"]
pub struct PASEL1 {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port A Select 1"]
pub mod pasel1;
#[doc = "Port 1 Interrupt Vector Register"]
pub struct P1IV {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port 1 Interrupt Vector Register"]
pub mod p1iv;
#[doc = "Port A Complement Select"]
pub struct PASELC {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port A Complement Select"]
pub mod paselc;
#[doc = "Port A Interrupt Edge Select"]
pub struct PAIES {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port A Interrupt Edge Select"]
pub mod paies;
#[doc = "Port A Interrupt Enable"]
pub struct PAIE {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port A Interrupt Enable"]
pub mod paie;
#[doc = "Port A Interrupt Flag"]
pub struct PAIFG {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port A Interrupt Flag"]
pub mod paifg;
#[doc = "Port 2 Interrupt Vector Register"]
pub struct P2IV {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port 2 Interrupt Vector Register"]
pub mod p2iv;
#[doc = "Port B Input"]
pub struct PBIN {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port B Input"]
pub mod pbin;
#[doc = "Port B Output"]
pub struct PBOUT {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port B Output"]
pub mod pbout;
#[doc = "Port B Direction"]
pub struct PBDIR {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port B Direction"]
pub mod pbdir;
#[doc = "Port B Resistor Enable"]
pub struct PBREN {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port B Resistor Enable"]
pub mod pbren;
#[doc = "Port B Drive Strength"]
pub struct PBDS {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port B Drive Strength"]
pub mod pbds;
#[doc = "Port B Select 0"]
pub struct PBSEL0 {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port B Select 0"]
pub mod pbsel0;
#[doc = "Port B Select 1"]
pub struct PBSEL1 {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port B Select 1"]
pub mod pbsel1;
#[doc = "Port 3 Interrupt Vector Register"]
pub struct P3IV {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port 3 Interrupt Vector Register"]
pub mod p3iv;
#[doc = "Port B Complement Select"]
pub struct PBSELC {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port B Complement Select"]
pub mod pbselc;
#[doc = "Port B Interrupt Edge Select"]
pub struct PBIES {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port B Interrupt Edge Select"]
pub mod pbies;
#[doc = "Port B Interrupt Enable"]
pub struct PBIE {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port B Interrupt Enable"]
pub mod pbie;
#[doc = "Port B Interrupt Flag"]
pub struct PBIFG {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port B Interrupt Flag"]
pub mod pbifg;
#[doc = "Port 4 Interrupt Vector Register"]
pub struct P4IV {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port 4 Interrupt Vector Register"]
pub mod p4iv;
#[doc = "Port C Input"]
pub struct PCIN {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port C Input"]
pub mod pcin;
#[doc = "Port C Output"]
pub struct PCOUT {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port C Output"]
pub mod pcout;
#[doc = "Port C Direction"]
pub struct PCDIR {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port C Direction"]
pub mod pcdir;
#[doc = "Port C Resistor Enable"]
pub struct PCREN {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port C Resistor Enable"]
pub mod pcren;
#[doc = "Port C Drive Strength"]
pub struct PCDS {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port C Drive Strength"]
pub mod pcds;
#[doc = "Port C Select 0"]
pub struct PCSEL0 {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port C Select 0"]
pub mod pcsel0;
#[doc = "Port C Select 1"]
pub struct PCSEL1 {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port C Select 1"]
pub mod pcsel1;
#[doc = "Port 5 Interrupt Vector Register"]
pub struct P5IV {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port 5 Interrupt Vector Register"]
pub mod p5iv;
#[doc = "Port C Complement Select"]
pub struct PCSELC {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port C Complement Select"]
pub mod pcselc;
#[doc = "Port C Interrupt Edge Select"]
pub struct PCIES {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port C Interrupt Edge Select"]
pub mod pcies;
#[doc = "Port C Interrupt Enable"]
pub struct PCIE {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port C Interrupt Enable"]
pub mod pcie;
#[doc = "Port C Interrupt Flag"]
pub struct PCIFG {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port C Interrupt Flag"]
pub mod pcifg;
#[doc = "Port 6 Interrupt Vector Register"]
pub struct P6IV {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port 6 Interrupt Vector Register"]
pub mod p6iv;
#[doc = "Port D Input"]
pub struct PDIN {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port D Input"]
pub mod pdin;
#[doc = "Port D Output"]
pub struct PDOUT {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port D Output"]
pub mod pdout;
#[doc = "Port D Direction"]
pub struct PDDIR {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port D Direction"]
pub mod pddir;
#[doc = "Port D Resistor Enable"]
pub struct PDREN {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port D Resistor Enable"]
pub mod pdren;
#[doc = "Port D Drive Strength"]
pub struct PDDS {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port D Drive Strength"]
pub mod pdds;
#[doc = "Port D Select 0"]
pub struct PDSEL0 {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port D Select 0"]
pub mod pdsel0;
#[doc = "Port D Select 1"]
pub struct PDSEL1 {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port D Select 1"]
pub mod pdsel1;
#[doc = "Port 7 Interrupt Vector Register"]
pub struct P7IV {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port 7 Interrupt Vector Register"]
pub mod p7iv;
#[doc = "Port D Complement Select"]
pub struct PDSELC {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port D Complement Select"]
pub mod pdselc;
#[doc = "Port D Interrupt Edge Select"]
pub struct PDIES {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port D Interrupt Edge Select"]
pub mod pdies;
#[doc = "Port D Interrupt Enable"]
pub struct PDIE {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port D Interrupt Enable"]
pub mod pdie;
#[doc = "Port D Interrupt Flag"]
pub struct PDIFG {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port D Interrupt Flag"]
pub mod pdifg;
#[doc = "Port 8 Interrupt Vector Register"]
pub struct P8IV {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port 8 Interrupt Vector Register"]
pub mod p8iv;
#[doc = "Port E Input"]
pub struct PEIN {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port E Input"]
pub mod pein;
#[doc = "Port E Output"]
pub struct PEOUT {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port E Output"]
pub mod peout;
#[doc = "Port E Direction"]
pub struct PEDIR {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port E Direction"]
pub mod pedir;
#[doc = "Port E Resistor Enable"]
pub struct PEREN {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port E Resistor Enable"]
pub mod peren;
#[doc = "Port E Drive Strength"]
pub struct PEDS {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port E Drive Strength"]
pub mod peds;
#[doc = "Port E Select 0"]
pub struct PESEL0 {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port E Select 0"]
pub mod pesel0;
#[doc = "Port E Select 1"]
pub struct PESEL1 {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port E Select 1"]
pub mod pesel1;
#[doc = "Port 9 Interrupt Vector Register"]
pub struct P9IV {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port 9 Interrupt Vector Register"]
pub mod p9iv;
#[doc = "Port E Complement Select"]
pub struct PESELC {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port E Complement Select"]
pub mod peselc;
#[doc = "Port E Interrupt Edge Select"]
pub struct PEIES {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port E Interrupt Edge Select"]
pub mod peies;
#[doc = "Port E Interrupt Enable"]
pub struct PEIE {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port E Interrupt Enable"]
pub mod peie;
#[doc = "Port E Interrupt Flag"]
pub struct PEIFG {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port E Interrupt Flag"]
pub mod peifg;
#[doc = "Port 10 Interrupt Vector Register"]
pub struct P10IV {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port 10 Interrupt Vector Register"]
pub mod p10iv;
#[doc = "Port J Input"]
pub struct PJIN {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port J Input"]
pub mod pjin;
#[doc = "Port J Output"]
pub struct PJOUT {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port J Output"]
pub mod pjout;
#[doc = "Port J Direction"]
pub struct PJDIR {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port J Direction"]
pub mod pjdir;
#[doc = "Port J Resistor Enable"]
pub struct PJREN {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port J Resistor Enable"]
pub mod pjren;
#[doc = "Port J Drive Strength"]
pub struct PJDS {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port J Drive Strength"]
pub mod pjds;
#[doc = "Port J Select 0"]
pub struct PJSEL0 {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port J Select 0"]
pub mod pjsel0;
#[doc = "Port J Select 1"]
pub struct PJSEL1 {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port J Select 1"]
pub mod pjsel1;
#[doc = "Port J Complement Select"]
pub struct PJSELC {
register: ::vcell::VolatileCell<u16>,
}
#[doc = "Port J Complement Select"]
pub mod pjselc;

133
example-source/msp432p401r/src/dio/p10iv.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u16,
}
impl super::P10IV {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = "Possible values of the field `P10IV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P10IVR {
#[doc = "No interrupt pending"]
P10IV_0,
#[doc = "Interrupt Source: Port 10.0 interrupt; Interrupt Flag: P10IFG0; Interrupt Priority: Highest"]
P10IV_2,
#[doc = "Interrupt Source: Port 10.1 interrupt; Interrupt Flag: P10IFG1"]
P10IV_4,
#[doc = "Interrupt Source: Port 10.2 interrupt; Interrupt Flag: P10IFG2"]
P10IV_6,
#[doc = "Interrupt Source: Port 10.3 interrupt; Interrupt Flag: P10IFG3"]
P10IV_8,
#[doc = "Interrupt Source: Port 10.4 interrupt; Interrupt Flag: P10IFG4"]
P10IV_10,
#[doc = "Interrupt Source: Port 10.5 interrupt; Interrupt Flag: P10IFG5"]
P10IV_12,
#[doc = "Interrupt Source: Port 10.6 interrupt; Interrupt Flag: P10IFG6"]
P10IV_14,
#[doc = "Interrupt Source: Port 10.7 interrupt; Interrupt Flag: P10IFG7; Interrupt Priority: Lowest"]
P10IV_16,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl P10IVR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P10IVR::P10IV_0 => 0,
P10IVR::P10IV_2 => 2,
P10IVR::P10IV_4 => 4,
P10IVR::P10IV_6 => 6,
P10IVR::P10IV_8 => 8,
P10IVR::P10IV_10 => 10,
P10IVR::P10IV_12 => 12,
P10IVR::P10IV_14 => 14,
P10IVR::P10IV_16 => 16,
P10IVR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P10IVR {
match value {
0 => P10IVR::P10IV_0,
2 => P10IVR::P10IV_2,
4 => P10IVR::P10IV_4,
6 => P10IVR::P10IV_6,
8 => P10IVR::P10IV_8,
10 => P10IVR::P10IV_10,
12 => P10IVR::P10IV_12,
14 => P10IVR::P10IV_14,
16 => P10IVR::P10IV_16,
i => P10IVR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `P10IV_0`"]
#[inline]
pub fn is_p10iv_0(&self) -> bool {
*self == P10IVR::P10IV_0
}
#[doc = "Checks if the value of the field is `P10IV_2`"]
#[inline]
pub fn is_p10iv_2(&self) -> bool {
*self == P10IVR::P10IV_2
}
#[doc = "Checks if the value of the field is `P10IV_4`"]
#[inline]
pub fn is_p10iv_4(&self) -> bool {
*self == P10IVR::P10IV_4
}
#[doc = "Checks if the value of the field is `P10IV_6`"]
#[inline]
pub fn is_p10iv_6(&self) -> bool {
*self == P10IVR::P10IV_6
}
#[doc = "Checks if the value of the field is `P10IV_8`"]
#[inline]
pub fn is_p10iv_8(&self) -> bool {
*self == P10IVR::P10IV_8
}
#[doc = "Checks if the value of the field is `P10IV_10`"]
#[inline]
pub fn is_p10iv_10(&self) -> bool {
*self == P10IVR::P10IV_10
}
#[doc = "Checks if the value of the field is `P10IV_12`"]
#[inline]
pub fn is_p10iv_12(&self) -> bool {
*self == P10IVR::P10IV_12
}
#[doc = "Checks if the value of the field is `P10IV_14`"]
#[inline]
pub fn is_p10iv_14(&self) -> bool {
*self == P10IVR::P10IV_14
}
#[doc = "Checks if the value of the field is `P10IV_16`"]
#[inline]
pub fn is_p10iv_16(&self) -> bool {
*self == P10IVR::P10IV_16
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
#[doc = "Bits 0:4 - Port 10 interrupt vector value"]
#[inline]
pub fn p10iv(&self) -> P10IVR {
P10IVR::_from({
const MASK: u8 = 31;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u16) as u8
})
}
}

133
example-source/msp432p401r/src/dio/p1iv.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u16,
}
impl super::P1IV {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = "Possible values of the field `P1IV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1IVR {
#[doc = "No interrupt pending"]
P1IV_0,
#[doc = "Interrupt Source: Port 1.0 interrupt; Interrupt Flag: P1IFG0; Interrupt Priority: Highest"]
P1IV_2,
#[doc = "Interrupt Source: Port 1.1 interrupt; Interrupt Flag: P1IFG1"]
P1IV_4,
#[doc = "Interrupt Source: Port 1.2 interrupt; Interrupt Flag: P1IFG2"]
P1IV_6,
#[doc = "Interrupt Source: Port 1.3 interrupt; Interrupt Flag: P1IFG3"]
P1IV_8,
#[doc = "Interrupt Source: Port 1.4 interrupt; Interrupt Flag: P1IFG4"]
P1IV_10,
#[doc = "Interrupt Source: Port 1.5 interrupt; Interrupt Flag: P1IFG5"]
P1IV_12,
#[doc = "Interrupt Source: Port 1.6 interrupt; Interrupt Flag: P1IFG6"]
P1IV_14,
#[doc = "Interrupt Source: Port 1.7 interrupt; Interrupt Flag: P1IFG7; Interrupt Priority: Lowest"]
P1IV_16,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl P1IVR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1IVR::P1IV_0 => 0,
P1IVR::P1IV_2 => 2,
P1IVR::P1IV_4 => 4,
P1IVR::P1IV_6 => 6,
P1IVR::P1IV_8 => 8,
P1IVR::P1IV_10 => 10,
P1IVR::P1IV_12 => 12,
P1IVR::P1IV_14 => 14,
P1IVR::P1IV_16 => 16,
P1IVR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1IVR {
match value {
0 => P1IVR::P1IV_0,
2 => P1IVR::P1IV_2,
4 => P1IVR::P1IV_4,
6 => P1IVR::P1IV_6,
8 => P1IVR::P1IV_8,
10 => P1IVR::P1IV_10,
12 => P1IVR::P1IV_12,
14 => P1IVR::P1IV_14,
16 => P1IVR::P1IV_16,
i => P1IVR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `P1IV_0`"]
#[inline]
pub fn is_p1iv_0(&self) -> bool {
*self == P1IVR::P1IV_0
}
#[doc = "Checks if the value of the field is `P1IV_2`"]
#[inline]
pub fn is_p1iv_2(&self) -> bool {
*self == P1IVR::P1IV_2
}
#[doc = "Checks if the value of the field is `P1IV_4`"]
#[inline]
pub fn is_p1iv_4(&self) -> bool {
*self == P1IVR::P1IV_4
}
#[doc = "Checks if the value of the field is `P1IV_6`"]
#[inline]
pub fn is_p1iv_6(&self) -> bool {
*self == P1IVR::P1IV_6
}
#[doc = "Checks if the value of the field is `P1IV_8`"]
#[inline]
pub fn is_p1iv_8(&self) -> bool {
*self == P1IVR::P1IV_8
}
#[doc = "Checks if the value of the field is `P1IV_10`"]
#[inline]
pub fn is_p1iv_10(&self) -> bool {
*self == P1IVR::P1IV_10
}
#[doc = "Checks if the value of the field is `P1IV_12`"]
#[inline]
pub fn is_p1iv_12(&self) -> bool {
*self == P1IVR::P1IV_12
}
#[doc = "Checks if the value of the field is `P1IV_14`"]
#[inline]
pub fn is_p1iv_14(&self) -> bool {
*self == P1IVR::P1IV_14
}
#[doc = "Checks if the value of the field is `P1IV_16`"]
#[inline]
pub fn is_p1iv_16(&self) -> bool {
*self == P1IVR::P1IV_16
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
#[doc = "Bits 0:4 - Port 1 interrupt vector value"]
#[inline]
pub fn p1iv(&self) -> P1IVR {
P1IVR::_from({
const MASK: u8 = 31;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u16) as u8
})
}
}

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