515 lines
14 KiB
Rust
515 lines
14 KiB
Rust
#[doc = r" Value read from the register"]
|
|
pub struct R {
|
|
bits: u32,
|
|
}
|
|
#[doc = r" Value to write to the register"]
|
|
pub struct W {
|
|
bits: u32,
|
|
}
|
|
impl super::CSCTL0 {
|
|
#[doc = r" Modifies the contents of the register"]
|
|
#[inline]
|
|
pub fn modify<F>(&self, f: F)
|
|
where
|
|
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
|
{
|
|
let bits = self.register.get();
|
|
let r = R { bits: bits };
|
|
let mut w = W { bits: bits };
|
|
f(&r, &mut w);
|
|
self.register.set(w.bits);
|
|
}
|
|
#[doc = r" Reads the contents of the register"]
|
|
#[inline]
|
|
pub fn read(&self) -> R {
|
|
R {
|
|
bits: self.register.get(),
|
|
}
|
|
}
|
|
#[doc = r" Writes to the register"]
|
|
#[inline]
|
|
pub fn write<F>(&self, f: F)
|
|
where
|
|
F: FnOnce(&mut W) -> &mut W,
|
|
{
|
|
let mut w = W::reset_value();
|
|
f(&mut w);
|
|
self.register.set(w.bits);
|
|
}
|
|
#[doc = r" Writes the reset value to the register"]
|
|
#[inline]
|
|
pub fn reset(&self) {
|
|
self.write(|w| w)
|
|
}
|
|
}
|
|
#[doc = r" Value of the field"]
|
|
pub struct DCOTUNER {
|
|
bits: u16,
|
|
}
|
|
impl DCOTUNER {
|
|
#[doc = r" Value of the field as raw bits"]
|
|
#[inline]
|
|
pub fn bits(&self) -> u16 {
|
|
self.bits
|
|
}
|
|
}
|
|
#[doc = "Possible values of the field `DCORSEL`"]
|
|
#[derive(Clone, Copy, Debug, PartialEq)]
|
|
pub enum DCORSELR {
|
|
#[doc = "Nominal DCO Frequency Range (MHz): 1 to 2"]
|
|
DCORSEL_0,
|
|
#[doc = "Nominal DCO Frequency Range (MHz): 2 to 4"]
|
|
DCORSEL_1,
|
|
#[doc = "Nominal DCO Frequency Range (MHz): 4 to 8"]
|
|
DCORSEL_2,
|
|
#[doc = "Nominal DCO Frequency Range (MHz): 8 to 16"]
|
|
DCORSEL_3,
|
|
#[doc = "Nominal DCO Frequency Range (MHz): 16 to 32"]
|
|
DCORSEL_4,
|
|
#[doc = "Nominal DCO Frequency Range (MHz): 32 to 64"]
|
|
DCORSEL_5,
|
|
#[doc = r" Reserved"]
|
|
_Reserved(u8),
|
|
}
|
|
impl DCORSELR {
|
|
#[doc = r" Value of the field as raw bits"]
|
|
#[inline]
|
|
pub fn bits(&self) -> u8 {
|
|
match *self {
|
|
DCORSELR::DCORSEL_0 => 0,
|
|
DCORSELR::DCORSEL_1 => 1,
|
|
DCORSELR::DCORSEL_2 => 2,
|
|
DCORSELR::DCORSEL_3 => 3,
|
|
DCORSELR::DCORSEL_4 => 4,
|
|
DCORSELR::DCORSEL_5 => 5,
|
|
DCORSELR::_Reserved(bits) => bits,
|
|
}
|
|
}
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _from(value: u8) -> DCORSELR {
|
|
match value {
|
|
0 => DCORSELR::DCORSEL_0,
|
|
1 => DCORSELR::DCORSEL_1,
|
|
2 => DCORSELR::DCORSEL_2,
|
|
3 => DCORSELR::DCORSEL_3,
|
|
4 => DCORSELR::DCORSEL_4,
|
|
5 => DCORSELR::DCORSEL_5,
|
|
i => DCORSELR::_Reserved(i),
|
|
}
|
|
}
|
|
#[doc = "Checks if the value of the field is `DCORSEL_0`"]
|
|
#[inline]
|
|
pub fn is_dcorsel_0(&self) -> bool {
|
|
*self == DCORSELR::DCORSEL_0
|
|
}
|
|
#[doc = "Checks if the value of the field is `DCORSEL_1`"]
|
|
#[inline]
|
|
pub fn is_dcorsel_1(&self) -> bool {
|
|
*self == DCORSELR::DCORSEL_1
|
|
}
|
|
#[doc = "Checks if the value of the field is `DCORSEL_2`"]
|
|
#[inline]
|
|
pub fn is_dcorsel_2(&self) -> bool {
|
|
*self == DCORSELR::DCORSEL_2
|
|
}
|
|
#[doc = "Checks if the value of the field is `DCORSEL_3`"]
|
|
#[inline]
|
|
pub fn is_dcorsel_3(&self) -> bool {
|
|
*self == DCORSELR::DCORSEL_3
|
|
}
|
|
#[doc = "Checks if the value of the field is `DCORSEL_4`"]
|
|
#[inline]
|
|
pub fn is_dcorsel_4(&self) -> bool {
|
|
*self == DCORSELR::DCORSEL_4
|
|
}
|
|
#[doc = "Checks if the value of the field is `DCORSEL_5`"]
|
|
#[inline]
|
|
pub fn is_dcorsel_5(&self) -> bool {
|
|
*self == DCORSELR::DCORSEL_5
|
|
}
|
|
}
|
|
#[doc = "Possible values of the field `DCORES`"]
|
|
#[derive(Clone, Copy, Debug, PartialEq)]
|
|
pub enum DCORESR {
|
|
#[doc = "Internal resistor mode"]
|
|
DCORES_0,
|
|
#[doc = "External resistor mode"]
|
|
DCORES_1,
|
|
}
|
|
impl DCORESR {
|
|
#[doc = r" Returns `true` if the bit is clear (0)"]
|
|
#[inline]
|
|
pub fn bit_is_clear(&self) -> bool {
|
|
!self.bit()
|
|
}
|
|
#[doc = r" Returns `true` if the bit is set (1)"]
|
|
#[inline]
|
|
pub fn bit_is_set(&self) -> bool {
|
|
self.bit()
|
|
}
|
|
#[doc = r" Value of the field as raw bits"]
|
|
#[inline]
|
|
pub fn bit(&self) -> bool {
|
|
match *self {
|
|
DCORESR::DCORES_0 => false,
|
|
DCORESR::DCORES_1 => true,
|
|
}
|
|
}
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _from(value: bool) -> DCORESR {
|
|
match value {
|
|
false => DCORESR::DCORES_0,
|
|
true => DCORESR::DCORES_1,
|
|
}
|
|
}
|
|
#[doc = "Checks if the value of the field is `DCORES_0`"]
|
|
#[inline]
|
|
pub fn is_dcores_0(&self) -> bool {
|
|
*self == DCORESR::DCORES_0
|
|
}
|
|
#[doc = "Checks if the value of the field is `DCORES_1`"]
|
|
#[inline]
|
|
pub fn is_dcores_1(&self) -> bool {
|
|
*self == DCORESR::DCORES_1
|
|
}
|
|
}
|
|
#[doc = "Possible values of the field `DCOEN`"]
|
|
#[derive(Clone, Copy, Debug, PartialEq)]
|
|
pub enum DCOENR {
|
|
#[doc = "DCO is on if it is used as a source for MCLK, HSMCLK , or SMCLK and clock is requested, otherwise it is disabled."]
|
|
DCOEN_0,
|
|
#[doc = "DCO is on"]
|
|
DCOEN_1,
|
|
}
|
|
impl DCOENR {
|
|
#[doc = r" Returns `true` if the bit is clear (0)"]
|
|
#[inline]
|
|
pub fn bit_is_clear(&self) -> bool {
|
|
!self.bit()
|
|
}
|
|
#[doc = r" Returns `true` if the bit is set (1)"]
|
|
#[inline]
|
|
pub fn bit_is_set(&self) -> bool {
|
|
self.bit()
|
|
}
|
|
#[doc = r" Value of the field as raw bits"]
|
|
#[inline]
|
|
pub fn bit(&self) -> bool {
|
|
match *self {
|
|
DCOENR::DCOEN_0 => false,
|
|
DCOENR::DCOEN_1 => true,
|
|
}
|
|
}
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _from(value: bool) -> DCOENR {
|
|
match value {
|
|
false => DCOENR::DCOEN_0,
|
|
true => DCOENR::DCOEN_1,
|
|
}
|
|
}
|
|
#[doc = "Checks if the value of the field is `DCOEN_0`"]
|
|
#[inline]
|
|
pub fn is_dcoen_0(&self) -> bool {
|
|
*self == DCOENR::DCOEN_0
|
|
}
|
|
#[doc = "Checks if the value of the field is `DCOEN_1`"]
|
|
#[inline]
|
|
pub fn is_dcoen_1(&self) -> bool {
|
|
*self == DCOENR::DCOEN_1
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _DCOTUNEW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _DCOTUNEW<'a> {
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub unsafe fn bits(self, value: u16) -> &'a mut W {
|
|
const MASK: u16 = 1023;
|
|
const OFFSET: u8 = 0;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `DCORSEL`"]
|
|
pub enum DCORSELW {
|
|
#[doc = "Nominal DCO Frequency Range (MHz): 1 to 2"]
|
|
DCORSEL_0,
|
|
#[doc = "Nominal DCO Frequency Range (MHz): 2 to 4"]
|
|
DCORSEL_1,
|
|
#[doc = "Nominal DCO Frequency Range (MHz): 4 to 8"]
|
|
DCORSEL_2,
|
|
#[doc = "Nominal DCO Frequency Range (MHz): 8 to 16"]
|
|
DCORSEL_3,
|
|
#[doc = "Nominal DCO Frequency Range (MHz): 16 to 32"]
|
|
DCORSEL_4,
|
|
#[doc = "Nominal DCO Frequency Range (MHz): 32 to 64"]
|
|
DCORSEL_5,
|
|
}
|
|
impl DCORSELW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> u8 {
|
|
match *self {
|
|
DCORSELW::DCORSEL_0 => 0,
|
|
DCORSELW::DCORSEL_1 => 1,
|
|
DCORSELW::DCORSEL_2 => 2,
|
|
DCORSELW::DCORSEL_3 => 3,
|
|
DCORSELW::DCORSEL_4 => 4,
|
|
DCORSELW::DCORSEL_5 => 5,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _DCORSELW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _DCORSELW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: DCORSELW) -> &'a mut W {
|
|
unsafe { self.bits(variant._bits()) }
|
|
}
|
|
#[doc = "Nominal DCO Frequency Range (MHz): 1 to 2"]
|
|
#[inline]
|
|
pub fn dcorsel_0(self) -> &'a mut W {
|
|
self.variant(DCORSELW::DCORSEL_0)
|
|
}
|
|
#[doc = "Nominal DCO Frequency Range (MHz): 2 to 4"]
|
|
#[inline]
|
|
pub fn dcorsel_1(self) -> &'a mut W {
|
|
self.variant(DCORSELW::DCORSEL_1)
|
|
}
|
|
#[doc = "Nominal DCO Frequency Range (MHz): 4 to 8"]
|
|
#[inline]
|
|
pub fn dcorsel_2(self) -> &'a mut W {
|
|
self.variant(DCORSELW::DCORSEL_2)
|
|
}
|
|
#[doc = "Nominal DCO Frequency Range (MHz): 8 to 16"]
|
|
#[inline]
|
|
pub fn dcorsel_3(self) -> &'a mut W {
|
|
self.variant(DCORSELW::DCORSEL_3)
|
|
}
|
|
#[doc = "Nominal DCO Frequency Range (MHz): 16 to 32"]
|
|
#[inline]
|
|
pub fn dcorsel_4(self) -> &'a mut W {
|
|
self.variant(DCORSELW::DCORSEL_4)
|
|
}
|
|
#[doc = "Nominal DCO Frequency Range (MHz): 32 to 64"]
|
|
#[inline]
|
|
pub fn dcorsel_5(self) -> &'a mut W {
|
|
self.variant(DCORSELW::DCORSEL_5)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
|
const MASK: u8 = 7;
|
|
const OFFSET: u8 = 16;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `DCORES`"]
|
|
pub enum DCORESW {
|
|
#[doc = "Internal resistor mode"]
|
|
DCORES_0,
|
|
#[doc = "External resistor mode"]
|
|
DCORES_1,
|
|
}
|
|
impl DCORESW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> bool {
|
|
match *self {
|
|
DCORESW::DCORES_0 => false,
|
|
DCORESW::DCORES_1 => true,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _DCORESW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _DCORESW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: DCORESW) -> &'a mut W {
|
|
{
|
|
self.bit(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "Internal resistor mode"]
|
|
#[inline]
|
|
pub fn dcores_0(self) -> &'a mut W {
|
|
self.variant(DCORESW::DCORES_0)
|
|
}
|
|
#[doc = "External resistor mode"]
|
|
#[inline]
|
|
pub fn dcores_1(self) -> &'a mut W {
|
|
self.variant(DCORESW::DCORES_1)
|
|
}
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
|
|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 22;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `DCOEN`"]
|
|
pub enum DCOENW {
|
|
#[doc = "DCO is on if it is used as a source for MCLK, HSMCLK , or SMCLK and clock is requested, otherwise it is disabled."]
|
|
DCOEN_0,
|
|
#[doc = "DCO is on"]
|
|
DCOEN_1,
|
|
}
|
|
impl DCOENW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> bool {
|
|
match *self {
|
|
DCOENW::DCOEN_0 => false,
|
|
DCOENW::DCOEN_1 => true,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _DCOENW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _DCOENW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: DCOENW) -> &'a mut W {
|
|
{
|
|
self.bit(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "DCO is on if it is used as a source for MCLK, HSMCLK , or SMCLK and clock is requested, otherwise it is disabled."]
|
|
#[inline]
|
|
pub fn dcoen_0(self) -> &'a mut W {
|
|
self.variant(DCOENW::DCOEN_0)
|
|
}
|
|
#[doc = "DCO is on"]
|
|
#[inline]
|
|
pub fn dcoen_1(self) -> &'a mut W {
|
|
self.variant(DCOENW::DCOEN_1)
|
|
}
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
|
|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 23;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
impl R {
|
|
#[doc = r" Value of the register as raw bits"]
|
|
#[inline]
|
|
pub fn bits(&self) -> u32 {
|
|
self.bits
|
|
}
|
|
#[doc = "Bits 0:9 - DCO frequency tuning select"]
|
|
#[inline]
|
|
pub fn dcotune(&self) -> DCOTUNER {
|
|
let bits = {
|
|
const MASK: u16 = 1023;
|
|
const OFFSET: u8 = 0;
|
|
((self.bits >> OFFSET) & MASK as u32) as u16
|
|
};
|
|
DCOTUNER { bits }
|
|
}
|
|
#[doc = "Bits 16:18 - DCO frequency range select"]
|
|
#[inline]
|
|
pub fn dcorsel(&self) -> DCORSELR {
|
|
DCORSELR::_from({
|
|
const MASK: u8 = 7;
|
|
const OFFSET: u8 = 16;
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
|
})
|
|
}
|
|
#[doc = "Bit 22 - Enables the DCO external resistor mode"]
|
|
#[inline]
|
|
pub fn dcores(&self) -> DCORESR {
|
|
DCORESR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 22;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
#[doc = "Bit 23 - Enables the DCO oscillator"]
|
|
#[inline]
|
|
pub fn dcoen(&self) -> DCOENR {
|
|
DCOENR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 23;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
}
|
|
impl W {
|
|
#[doc = r" Reset value of the register"]
|
|
#[inline]
|
|
pub fn reset_value() -> W {
|
|
W { bits: 65536 }
|
|
}
|
|
#[doc = r" Writes raw bits to the register"]
|
|
#[inline]
|
|
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
|
self.bits = bits;
|
|
self
|
|
}
|
|
#[doc = "Bits 0:9 - DCO frequency tuning select"]
|
|
#[inline]
|
|
pub fn dcotune(&mut self) -> _DCOTUNEW {
|
|
_DCOTUNEW { w: self }
|
|
}
|
|
#[doc = "Bits 16:18 - DCO frequency range select"]
|
|
#[inline]
|
|
pub fn dcorsel(&mut self) -> _DCORSELW {
|
|
_DCORSELW { w: self }
|
|
}
|
|
#[doc = "Bit 22 - Enables the DCO external resistor mode"]
|
|
#[inline]
|
|
pub fn dcores(&mut self) -> _DCORESW {
|
|
_DCORESW { w: self }
|
|
}
|
|
#[doc = "Bit 23 - Enables the DCO oscillator"]
|
|
#[inline]
|
|
pub fn dcoen(&mut self) -> _DCOENW {
|
|
_DCOENW { w: self }
|
|
}
|
|
}
|