From 4499e75a9207276f2753d09b9f6239d9bb3a2ef0 Mon Sep 17 00:00:00 2001
From: Levi Pearson <levi.pearson@redcanary.com>
Date: Mon, 18 Mar 2019 11:18:16 -0600
Subject: [PATCH] Talk as presented plus example source for MSP432 blinky light
 demo

---
 .gitignore                                    |    10 +
 EmbeddedRust.md                               |    61 +-
 EmbeddedRust.pdf                              |   Bin 0 -> 39211 bytes
 example-source/msp432-app/.cargo/config       |    33 +
 example-source/msp432-app/.gitignore          |     5 +
 example-source/msp432-app/Cargo.toml          |    31 +
 example-source/msp432-app/README.md           |   129 +
 example-source/msp432-app/build.rs            |    18 +
 example-source/msp432-app/memory.x            |    37 +
 example-source/msp432-app/openocd.cfg         |     6 +
 example-source/msp432-app/openocd.gdb         |    35 +
 .../msp432-app/original-examples/crash.rs     |    96 +
 .../msp432-app/original-examples/exception.rs |    37 +
 .../msp432-app/original-examples/hello.rs     |    20 +
 .../msp432-app/original-examples/itm.rs       |    33 +
 .../msp432-app/original-examples/panic.rs     |    28 +
 .../original-examples/test_on_host.rs         |    57 +
 example-source/msp432-app/src/main.rs         |    81 +
 example-source/msp432-app/upload.sh           |     1 +
 example-source/msp432-hal/.gitignore          |     3 +
 example-source/msp432-hal/Cargo.toml          |    19 +
 example-source/msp432-hal/src/cs.rs           |    63 +
 example-source/msp432-hal/src/delay.rs        |    74 +
 example-source/msp432-hal/src/gpio.rs         |    22 +
 example-source/msp432-hal/src/lib.rs          |    26 +
 example-source/msp432-hal/src/prelude.rs      |     3 +
 example-source/msp432-hal/src/time.rs         |   117 +
 example-source/msp432p401r/.gitignore         |     3 +
 example-source/msp432p401r/Cargo.toml         |    17 +
 example-source/msp432p401r/MSP432P401R.svd    | 42237 ++++++++++++++++
 example-source/msp432p401r/build.rs           |    16 +
 example-source/msp432p401r/device.x           |    42 +
 example-source/msp432p401r/src/adc14.rs       |   125 +
 .../msp432p401r/src/adc14/adc14clrifgr0.rs    |  2045 +
 .../msp432p401r/src/adc14/adc14clrifgr1.rs    |   442 +
 .../msp432p401r/src/adc14/adc14ctl0.rs        |  2095 +
 .../msp432p401r/src/adc14/adc14ctl1.rs        |  1296 +
 .../msp432p401r/src/adc14/adc14hi0.rs         |   105 +
 .../msp432p401r/src/adc14/adc14hi1.rs         |   105 +
 .../msp432p401r/src/adc14/adc14ier0.rs        |  3872 ++
 .../msp432p401r/src/adc14/adc14ier1.rs        |   778 +
 .../msp432p401r/src/adc14/adc14ifgr0.rs       |  1812 +
 .../msp432p401r/src/adc14/adc14ifgr1.rs       |   356 +
 .../msp432p401r/src/adc14/adc14iv.rs          |   796 +
 .../msp432p401r/src/adc14/adc14lo0.rs         |   105 +
 .../msp432p401r/src/adc14/adc14lo1.rs         |   105 +
 .../msp432p401r/src/adc14/adc14mctl.rs        |  1289 +
 .../msp432p401r/src/adc14/adc14mem.rs         |   105 +
 example-source/msp432p401r/src/aes256.rs      |    68 +
 .../msp432p401r/src/aes256/aesactl0.rs        |  1051 +
 .../msp432p401r/src/aes256/aesactl1.rs        |   105 +
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 .../msp432p401r/src/aes256/aesadout.rs        |    69 +
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 .../msp432p401r/src/aes256/aesastat.rs        |   540 +
 .../msp432p401r/src/aes256/aesaxdin.rs        |    69 +
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 example-source/msp432p401r/src/captio0.rs     |    13 +
 .../msp432p401r/src/captio0/captiox_ctl.rs    |   783 +
 example-source/msp432p401r/src/captio1.rs     |    13 +
 .../msp432p401r/src/captio1/captiox_ctl.rs    |   783 +
 example-source/msp432p401r/src/comp_e0.rs     |    53 +
 .../msp432p401r/src/comp_e0/cex_ctl0.rs       |   982 +
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 .../msp432p401r/src/comp_e0/cex_int.rs        |   778 +
 .../msp432p401r/src/comp_e0/cex_iv.rs         |    88 +
 example-source/msp432p401r/src/comp_e1.rs     |    53 +
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 .../msp432p401r/src/comp_e1/cex_iv.rs         |    88 +
 example-source/msp432p401r/src/crc32.rs       |    89 +
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 .../msp432p401r/src/crc32/crc32resr_hi.rs     |   105 +
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 example-source/msp432p401r/src/cs.rs          |   114 +
 example-source/msp432p401r/src/cs/csclken.rs  |  1016 +
 example-source/msp432p401r/src/cs/csclrifg.rs |   722 +
 example-source/msp432p401r/src/cs/csctl0.rs   |   514 +
 example-source/msp432p401r/src/cs/csctl1.rs   |  1611 +
 example-source/msp432p401r/src/cs/csctl2.rs   |  1102 +
 example-source/msp432p401r/src/cs/csctl3.rs   |  1018 +
 .../msp432p401r/src/cs/csdcoercal0.rs         |   146 +
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 example-source/msp432p401r/src/cs/csie.rs     |  1373 +
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 example-source/msp432p401r/src/cs/cskey.rs    |   105 +
 example-source/msp432p401r/src/cs/cssetifg.rs |   722 +
 example-source/msp432p401r/src/cs/csstat.rs   |  1196 +
 example-source/msp432p401r/src/dio.rs         |   595 +
 example-source/msp432p401r/src/dio/p10iv.rs   |   133 +
 example-source/msp432p401r/src/dio/p1iv.rs    |   133 +
 example-source/msp432p401r/src/dio/p2iv.rs    |   133 +
 example-source/msp432p401r/src/dio/p3iv.rs    |   133 +
 example-source/msp432p401r/src/dio/p4iv.rs    |   133 +
 example-source/msp432p401r/src/dio/p5iv.rs    |   133 +
 example-source/msp432p401r/src/dio/p6iv.rs    |   133 +
 example-source/msp432p401r/src/dio/p7iv.rs    |   133 +
 example-source/msp432p401r/src/dio/p8iv.rs    |   133 +
 example-source/msp432p401r/src/dio/p9iv.rs    |   133 +
 example-source/msp432p401r/src/dio/padir.rs   |   146 +
 example-source/msp432p401r/src/dio/pads.rs    |   146 +
 example-source/msp432p401r/src/dio/paie.rs    |   146 +
 example-source/msp432p401r/src/dio/paies.rs   |   146 +
 example-source/msp432p401r/src/dio/paifg.rs   |   146 +
 example-source/msp432p401r/src/dio/pain.rs    |    62 +
 example-source/msp432p401r/src/dio/paout.rs   |   146 +
 example-source/msp432p401r/src/dio/paren.rs   |   146 +
 example-source/msp432p401r/src/dio/pasel0.rs  |   146 +
 example-source/msp432p401r/src/dio/pasel1.rs  |   146 +
 example-source/msp432p401r/src/dio/paselc.rs  |   146 +
 example-source/msp432p401r/src/dio/pbdir.rs   |   146 +
 example-source/msp432p401r/src/dio/pbds.rs    |   146 +
 example-source/msp432p401r/src/dio/pbie.rs    |   146 +
 example-source/msp432p401r/src/dio/pbies.rs   |   146 +
 example-source/msp432p401r/src/dio/pbifg.rs   |   146 +
 example-source/msp432p401r/src/dio/pbin.rs    |    62 +
 example-source/msp432p401r/src/dio/pbout.rs   |   146 +
 example-source/msp432p401r/src/dio/pbren.rs   |   146 +
 example-source/msp432p401r/src/dio/pbsel0.rs  |   146 +
 example-source/msp432p401r/src/dio/pbsel1.rs  |   146 +
 example-source/msp432p401r/src/dio/pbselc.rs  |   146 +
 example-source/msp432p401r/src/dio/pcdir.rs   |   146 +
 example-source/msp432p401r/src/dio/pcds.rs    |   146 +
 example-source/msp432p401r/src/dio/pcie.rs    |   146 +
 example-source/msp432p401r/src/dio/pcies.rs   |   146 +
 example-source/msp432p401r/src/dio/pcifg.rs   |   146 +
 example-source/msp432p401r/src/dio/pcin.rs    |    62 +
 example-source/msp432p401r/src/dio/pcout.rs   |   146 +
 example-source/msp432p401r/src/dio/pcren.rs   |   146 +
 example-source/msp432p401r/src/dio/pcsel0.rs  |   146 +
 example-source/msp432p401r/src/dio/pcsel1.rs  |   146 +
 example-source/msp432p401r/src/dio/pcselc.rs  |   146 +
 example-source/msp432p401r/src/dio/pddir.rs   |   146 +
 example-source/msp432p401r/src/dio/pdds.rs    |   146 +
 example-source/msp432p401r/src/dio/pdie.rs    |   146 +
 example-source/msp432p401r/src/dio/pdies.rs   |   146 +
 example-source/msp432p401r/src/dio/pdifg.rs   |   146 +
 example-source/msp432p401r/src/dio/pdin.rs    |    62 +
 example-source/msp432p401r/src/dio/pdout.rs   |   146 +
 example-source/msp432p401r/src/dio/pdren.rs   |   146 +
 example-source/msp432p401r/src/dio/pdsel0.rs  |   146 +
 example-source/msp432p401r/src/dio/pdsel1.rs  |   146 +
 example-source/msp432p401r/src/dio/pdselc.rs  |   146 +
 example-source/msp432p401r/src/dio/pedir.rs   |   146 +
 example-source/msp432p401r/src/dio/peds.rs    |   146 +
 example-source/msp432p401r/src/dio/peie.rs    |   146 +
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 example-source/msp432p401r/src/dio/peifg.rs   |   146 +
 example-source/msp432p401r/src/dio/pein.rs    |    62 +
 example-source/msp432p401r/src/dio/peout.rs   |   146 +
 example-source/msp432p401r/src/dio/peren.rs   |   146 +
 example-source/msp432p401r/src/dio/pesel0.rs  |   146 +
 example-source/msp432p401r/src/dio/pesel1.rs  |   146 +
 example-source/msp432p401r/src/dio/peselc.rs  |   146 +
 example-source/msp432p401r/src/dio/pjdir.rs   |   105 +
 example-source/msp432p401r/src/dio/pjds.rs    |   105 +
 example-source/msp432p401r/src/dio/pjin.rs    |    41 +
 example-source/msp432p401r/src/dio/pjout.rs   |   105 +
 example-source/msp432p401r/src/dio/pjren.rs   |   105 +
 example-source/msp432p401r/src/dio/pjsel0.rs  |   105 +
 example-source/msp432p401r/src/dio/pjsel1.rs  |   105 +
 example-source/msp432p401r/src/dio/pjselc.rs  |   105 +
 example-source/msp432p401r/src/dma.rs         |   209 +
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 example-source/msp432p401r/src/dma/dma_cfg.rs |   112 +
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 .../msp432p401r/src/dma/dma_errclr.rs         |   183 +
 .../msp432p401r/src/dma/dma_int0_clrflg.rs    |   925 +
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 example-source/msp432p401r/src/eusci_a0.rs    |   102 +
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 create mode 100644 example-source/msp432p401r/src/tlv/adc_offset.rs
 create mode 100644 example-source/msp432p401r/src/tlv/bcrev.rs
 create mode 100644 example-source/msp432p401r/src/tlv/bsl_cfg_len.rs
 create mode 100644 example-source/msp432p401r/src/tlv/bsl_cfg_tag.rs
 create mode 100644 example-source/msp432p401r/src/tlv/bsl_periphif_sel.rs
 create mode 100644 example-source/msp432p401r/src/tlv/bsl_portif_cfg_i2c.rs
 create mode 100644 example-source/msp432p401r/src/tlv/bsl_portif_cfg_spi.rs
 create mode 100644 example-source/msp432p401r/src/tlv/bsl_portif_cfg_uart.rs
 create mode 100644 example-source/msp432p401r/src/tlv/cs_cal_len.rs
 create mode 100644 example-source/msp432p401r/src/tlv/cs_cal_tag.rs
 create mode 100644 example-source/msp432p401r/src/tlv/dcoer_constk_rsel04.rs
 create mode 100644 example-source/msp432p401r/src/tlv/dcoer_constk_rsel5.rs
 create mode 100644 example-source/msp432p401r/src/tlv/dcoer_fcal_rsel04.rs
 create mode 100644 example-source/msp432p401r/src/tlv/dcoer_fcal_rsel5.rs
 create mode 100644 example-source/msp432p401r/src/tlv/dcoir_constk_rsel04.rs
 create mode 100644 example-source/msp432p401r/src/tlv/dcoir_constk_rsel5.rs
 create mode 100644 example-source/msp432p401r/src/tlv/dcoir_fcal_rsel04.rs
 create mode 100644 example-source/msp432p401r/src/tlv/dcoir_fcal_rsel5.rs
 create mode 100644 example-source/msp432p401r/src/tlv/device_id.rs
 create mode 100644 example-source/msp432p401r/src/tlv/device_info_len.rs
 create mode 100644 example-source/msp432p401r/src/tlv/device_info_tag.rs
 create mode 100644 example-source/msp432p401r/src/tlv/die_rec_len.rs
 create mode 100644 example-source/msp432p401r/src/tlv/die_rec_tag.rs
 create mode 100644 example-source/msp432p401r/src/tlv/die_xpos.rs
 create mode 100644 example-source/msp432p401r/src/tlv/die_ypos.rs
 create mode 100644 example-source/msp432p401r/src/tlv/flash_info_len.rs
 create mode 100644 example-source/msp432p401r/src/tlv/flash_info_tag.rs
 create mode 100644 example-source/msp432p401r/src/tlv/flash_max_erase_pulses.rs
 create mode 100644 example-source/msp432p401r/src/tlv/flash_max_prog_pulses.rs
 create mode 100644 example-source/msp432p401r/src/tlv/hwrev.rs
 create mode 100644 example-source/msp432p401r/src/tlv/lot_id.rs
 create mode 100644 example-source/msp432p401r/src/tlv/random_num_1.rs
 create mode 100644 example-source/msp432p401r/src/tlv/random_num_2.rs
 create mode 100644 example-source/msp432p401r/src/tlv/random_num_3.rs
 create mode 100644 example-source/msp432p401r/src/tlv/random_num_4.rs
 create mode 100644 example-source/msp432p401r/src/tlv/random_num_len.rs
 create mode 100644 example-source/msp432p401r/src/tlv/random_num_tag.rs
 create mode 100644 example-source/msp432p401r/src/tlv/ref_1p2v.rs
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 create mode 100644 example-source/msp432p401r/src/tlv/ref_cal_len.rs
 create mode 100644 example-source/msp432p401r/src/tlv/ref_cal_tag.rs
 create mode 100644 example-source/msp432p401r/src/tlv/reserved0.rs
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 create mode 100644 example-source/msp432p401r/src/tlv/reserved10.rs
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 create mode 100644 example-source/msp432p401r/src/tlv/rom_drvlib_rev.rs
 create mode 100644 example-source/msp432p401r/src/tlv/test_results.rs
 create mode 100644 example-source/msp432p401r/src/tlv/tlv_checksum.rs
 create mode 100644 example-source/msp432p401r/src/tlv/tlv_end.rs
 create mode 100644 example-source/msp432p401r/src/tlv/wafer_id.rs
 create mode 100644 example-source/msp432p401r/src/wdt_a.rs
 create mode 100644 example-source/msp432p401r/src/wdt_a/wdtctl.rs

diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..61e065e
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,10 @@
+*.aux
+*.out
+*.log
+*.toc
+*.nav
+*.vrb
+*.snm
+*.swp
+body.tex
+head.tex
diff --git a/EmbeddedRust.md b/EmbeddedRust.md
index a679650..8b0269e 100644
--- a/EmbeddedRust.md
+++ b/EmbeddedRust.md
@@ -12,7 +12,7 @@ I am:
 
 + A very experienced embedded systems programmer 
 + A moderately experienced Rustacean
-+ Relatively new at the combination
++ Pretty new at the combination
 
 ## Questions to answer
 
@@ -32,26 +32,23 @@ I am:
 ## Examples
 
 + A digital scale's control system
-
 + The engine management computer in a car
-
-+ The management controller in a hard drive
++ The disk controller in a hard drive
++ A factory process control computer
 
 ## They are everywhere
 
 + Microcontrollers start in the ~$0.01 price range
-
 + They can be as small as a grain of rice
-
 + They are in credit cards and SIM cards
-
 + They are also often off-the-shelf Windows boxes
 
 ## Microcontrollers
 
-+ Computers specialized for embedded control duty
++ Single-chip computers specialized for embedded control
 + Much wider variety of architecture
 + Integrated peripherals:
+  - Memory (RAM/Flash)
   - Timers
   - Sensors
   - Communication bus interfaces
@@ -69,12 +66,9 @@ I am:
 ## Why not other safe languages?
 
 + Real-time response requirements
-
 + Resource (often RAM/Flash) constraints
-
 + Memory layout and representation control
-
-+ Perception
++ Perception (no one thinks of Ada)
 
 ## Big wins
 
@@ -94,7 +88,7 @@ I am:
 + `gdb` built for the target arch for debugging
 + `openocd` to drive the programmer/debugger module
 
-## Embedded-wg resources
+## Embedded-wg
 
 + Embedded Rust Book
 + Awesome / Not-Yet-Awesome Lists
@@ -102,3 +96,44 @@ I am:
 + `embedded-hal` and HAL Crates
 + Board Support Crates
 + `rtfm` "Real-Time For The Masses" framework
+
+## Levels of maturity
+
++ Compiler back-ends for ARM and some other architectures are solid
++ Much work is now possible with stable Rust
++ Some patterns for safety are well-defined, others are still experimental
++ Patterns for modular, reusable code are still in progress
++ Ferrous Systems - works with **embedded-wg** and provides training/support
+
+# Where to start?
+
+## Emulation!
+
++ QEMU emulates a pair of ARM Cortex-M3 evaluation boards
++ The `ml3s6965` board has a minimal peripheral support crate
++ Both the Embedded Book and RTFM Book walk through starting with it
+
+## Development boards
+
++ Vendor-developed boards can be expensive, but have nice components
++ Many hobbyist-oriented boards are available, usually cheaper!
++ Cheap knock-offs of open-hardware boards are *really* cheap
++ Stay away from AVR-architecture Arduino-style boards for now!
++ Risc-V and MSP-430 have llvm support, but not as much community support
+
+## Sensors, actuators, etc.
+
++ Many boards have LEDs, buttons, capacitive touch, etc.
++ Adafruit, Sparkfun, Pololu have interesting, well-designed break-outs
++ Lots of cheap stuff from China, of varying quality!
++ Salvage from old electronics junk
+
+
+# Time left?
+
+## Discussion/Demos
+
++ General or rust-specific embedded Q&A
++ Walk-through tool + qemu install and first program
++ Look at some example code
++ Interest in future workshop w/real hardware?
diff --git a/EmbeddedRust.pdf b/EmbeddedRust.pdf
new file mode 100644
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diff --git a/example-source/msp432-app/.cargo/config b/example-source/msp432-app/.cargo/config
new file mode 100644
index 0000000..4d4733c
--- /dev/null
+++ b/example-source/msp432-app/.cargo/config
@@ -0,0 +1,33 @@
+#[target.thumbv7m-none-eabi]
+# uncomment this to make `cargo run` execute programs on QEMU
+# runner = "qemu-system-arm -cpu cortex-m3 -machine lm3s6965evb -nographic -semihosting-config enable=on,target=native -kernel"
+
+[target.'cfg(all(target_arch = "arm", target_os = "none"))']
+# uncomment ONE of these three option to make `cargo run` start a GDB session
+# which option to pick depends on your system
+# runner = "arm-none-eabi-gdb -q -x openocd.gdb"
+runner = "gdb-multiarch -q -x openocd.gdb"
+# runner = "gdb -q -x openocd.gdb"
+
+rustflags = [
+  # LLD (shipped with the Rust toolchain) is used as the default linker
+  "-C", "link-arg=-Tlink.x",
+
+  # if you run into problems with LLD switch to the GNU linker by commenting out
+  # this line
+  # "-C", "linker=arm-none-eabi-ld",
+
+  # if you need to link to pre-compiled C libraries provided by a C toolchain
+  # use GCC as the linker by commenting out both lines above and then
+  # uncommenting the three lines below
+  # "-C", "linker=arm-none-eabi-gcc",
+  # "-C", "link-arg=-Wl,-Tlink.x",
+  # "-C", "link-arg=-nostartfiles",
+]
+
+[build]
+# Pick ONE of these compilation targets
+# target = "thumbv6m-none-eabi"    # Cortex-M0 and Cortex-M0+
+# target = "thumbv7m-none-eabi"    # Cortex-M3
+# target = "thumbv7em-none-eabi"   # Cortex-M4 and Cortex-M7 (no FPU)
+target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
diff --git a/example-source/msp432-app/.gitignore b/example-source/msp432-app/.gitignore
new file mode 100644
index 0000000..59a4524
--- /dev/null
+++ b/example-source/msp432-app/.gitignore
@@ -0,0 +1,5 @@
+**/*.rs.bk
+.#*
+.gdb_history
+Cargo.lock
+target/
diff --git a/example-source/msp432-app/Cargo.toml b/example-source/msp432-app/Cargo.toml
new file mode 100644
index 0000000..6d721ed
--- /dev/null
+++ b/example-source/msp432-app/Cargo.toml
@@ -0,0 +1,31 @@
+[package]
+authors = ["Levi Pearson <levipearson@gmail.com>"]
+edition = "2018"
+readme = "README.md"
+name = "msp432-app"
+version = "0.1.0"
+
+[dependencies]
+cortex-m = "0.5.8"
+cortex-m-rt = "0.6.5"
+cortex-m-semihosting = "0.3.2"
+panic-halt = "0.2.0"
+panic-semihosting = "*"
+msp432p401r = { path = "../msp432p401r", features = ["rt"] }
+
+# Uncomment for the panic example.
+# panic-itm = "0.4.0"
+
+# Uncomment for the allocator example.
+# alloc-cortex-m = "0.3.5"
+
+# this lets you use `cargo fix`!
+[[bin]]
+name = "msp432-app"
+test = false
+bench = false
+
+[profile.release]
+codegen-units = 1 # better optimizations
+debug = true # symbols are nice and they don't increase the size on Flash
+lto = true # better optimizations
diff --git a/example-source/msp432-app/README.md b/example-source/msp432-app/README.md
new file mode 100644
index 0000000..4c30523
--- /dev/null
+++ b/example-source/msp432-app/README.md
@@ -0,0 +1,129 @@
+# `cortex-m-quickstart`
+
+> A template for building applications for ARM Cortex-M microcontrollers
+
+This project is developed and maintained by the [Cortex-M team][team].
+
+## Dependencies
+
+To build embedded programs using this template you'll need:
+
+- Rust 1.31, 1.30-beta, nightly-2018-09-13 or a newer toolchain. e.g. `rustup
+  default beta`
+
+- The `cargo generate` subcommand. [Installation
+  instructions](https://github.com/ashleygwilliams/cargo-generate#installation).
+
+- `rust-std` components (pre-compiled `core` crate) for the ARM Cortex-M
+  targets. Run:
+
+``` console
+$ rustup target add thumbv6m-none-eabi thumbv7m-none-eabi thumbv7em-none-eabi thumbv7em-none-eabihf
+```
+
+## Using this template
+
+**NOTE**: This is the very short version that only covers building programs. For
+the long version, which additionally covers flashing, running and debugging
+programs, check [the embedded Rust book][book].
+
+[book]: https://rust-embedded.github.io/book
+
+0. Before we begin you need to identify some characteristics of the target
+  device as these will be used to configure the project:
+
+- The ARM core. e.g. Cortex-M3.
+
+- Does the ARM core include an FPU? Cortex-M4**F** and Cortex-M7**F** cores do.
+
+- How much Flash memory and RAM does the target device has? e.g. 256 KiB of
+  Flash and 32 KiB of RAM.
+
+- Where are Flash memory and RAM mapped in the address space? e.g. RAM is
+  commonly located at address `0x2000_0000`.
+
+You can find this information in the data sheet or the reference manual of your
+device.
+
+In this example we'll be using the STM32F3DISCOVERY. This board contains an
+STM32F303VCT6 microcontroller. This microcontroller has:
+
+- A Cortex-M4F core that includes a single precision FPU
+
+- 256 KiB of Flash located at address 0x0800_0000.
+
+- 40 KiB of RAM located at address 0x2000_0000. (There's another RAM region but
+  for simplicity we'll ignore it).
+
+1. Instantiate the template.
+
+``` console
+$ cargo generate --git https://github.com/rust-embedded/cortex-m-quickstart
+ Project Name: app
+ Creating project called `app`...
+ Done! New project created /tmp/app
+
+$ cd app
+```
+
+2. Set a default compilation target. There are four options as mentioned at the
+   bottom of `.cargo/config`. For the STM32F303VCT6, which has a Cortex-M4F
+   core, we'll pick the `thumbv7em-none-eabihf` target.
+
+``` console
+$ tail -n6 .cargo/config
+```
+
+``` toml
+[build]
+# Pick ONE of these compilation targets
+# target = "thumbv6m-none-eabi"    # Cortex-M0 and Cortex-M0+
+# target = "thumbv7m-none-eabi"    # Cortex-M3
+# target = "thumbv7em-none-eabi"   # Cortex-M4 and Cortex-M7 (no FPU)
+target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
+```
+
+3. Enter the memory region information into the `memory.x` file.
+
+``` console
+$ cat memory.x
+/* Linker script for the STM32F303VCT6 */
+MEMORY
+{
+  /* NOTE 1 K = 1 KiBi = 1024 bytes */
+  FLASH : ORIGIN = 0x08000000, LENGTH = 256K
+  RAM : ORIGIN = 0x20000000, LENGTH = 40K
+}
+```
+
+4. Build the template application or one of the examples.
+
+``` console
+$ cargo build
+```
+
+# License
+
+This template is licensed under either of
+
+- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
+  http://www.apache.org/licenses/LICENSE-2.0)
+
+- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
+
+at your option.
+
+## Contribution
+
+Unless you explicitly state otherwise, any contribution intentionally submitted
+for inclusion in the work by you, as defined in the Apache-2.0 license, shall be
+dual licensed as above, without any additional terms or conditions.
+
+## Code of Conduct
+
+Contribution to this crate is organized under the terms of the [Rust Code of
+Conduct][CoC], the maintainer of this crate, the [Cortex-M team][team], promises
+to intervene to uphold that code of conduct.
+
+[CoC]: https://www.rust-lang.org/policies/code-of-conduct
+[team]: https://github.com/rust-embedded/wg#the-cortex-m-team
diff --git a/example-source/msp432-app/build.rs b/example-source/msp432-app/build.rs
new file mode 100644
index 0000000..98f603e
--- /dev/null
+++ b/example-source/msp432-app/build.rs
@@ -0,0 +1,18 @@
+use std::env;
+use std::fs::File;
+use std::io::Write;
+use std::path::PathBuf;
+
+fn main() {
+    // Put the linker script somewhere the linker can find it
+    let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+    File::create(out.join("memory.x"))
+        .unwrap()
+        .write_all(include_bytes!("memory.x"))
+        .unwrap();
+    println!("cargo:rustc-link-search={}", out.display());
+
+    // Only re-run the build script when memory.x is changed,
+    // instead of when any part of the source code changes.
+    println!("cargo:rerun-if-changed=memory.x");
+}
diff --git a/example-source/msp432-app/memory.x b/example-source/msp432-app/memory.x
new file mode 100644
index 0000000..ca8542f
--- /dev/null
+++ b/example-source/msp432-app/memory.x
@@ -0,0 +1,37 @@
+MEMORY
+{
+  /* NOTE 1 K = 1 KiBi = 1024 bytes */
+  /* Code Zone - 0x00000000 to 0x1FFFFFFF */
+  FLASH : ORIGIN = 0x00000000, LENGTH = 256K
+  RAM_ALIAS : ORIGIN = 0x01000000, LENGTH = 64K
+  ROM : ORIGIN = 0x02000000, LENGTH = 32K
+  /* SRAM Region - 0x00000000 to 0x003FFFFF */
+  RAM : ORIGIN = 0x20000000, LENGTH = 64K
+  RAM_BITBAND : ORIGIN = 0x22000000, LENGTH = 1024K
+}
+
+/* This is where the call stack will be allocated. */
+/* The stack is of the full descending type. */
+/* You may want to use this variable to locate the call stack and static
+   variables in different memory regions. Below is shown the default value */
+/* _stack_start = ORIGIN(RAM) + LENGTH(RAM); */
+
+/* You can use this symbol to customize the location of the .text section */
+/* If omitted the .text section will be placed right after the .vector_table
+   section */
+/* This is required only on microcontrollers that store some configuration right
+   after the vector table */
+/* _stext = ORIGIN(FLASH) + 0x400; */
+
+/* Example of putting non-initialized variables into custom RAM locations. */
+/* This assumes you have defined a region RAM2 above, and in the Rust
+   sources added the attribute `#[link_section = ".ram2bss"]` to the data
+   you want to place there. */
+/* Note that the section will not be zero-initialized by the runtime! */
+/* SECTIONS {
+     .ram2bss (NOLOAD) : ALIGN(4) {
+       *(.ram2bss);
+       . = ALIGN(4);
+     } > RAM2
+   } INSERT AFTER .bss;
+*/
diff --git a/example-source/msp432-app/openocd.cfg b/example-source/msp432-app/openocd.cfg
new file mode 100644
index 0000000..d150d12
--- /dev/null
+++ b/example-source/msp432-app/openocd.cfg
@@ -0,0 +1,6 @@
+# OpenOCD configuration for the MSP432P401R LaunchPad
+
+source [find interface/xds110.cfg]
+adapter_khz 2500
+transport select swd
+source [find target/ti_msp432.cfg]
diff --git a/example-source/msp432-app/openocd.gdb b/example-source/msp432-app/openocd.gdb
new file mode 100644
index 0000000..cf4ea57
--- /dev/null
+++ b/example-source/msp432-app/openocd.gdb
@@ -0,0 +1,35 @@
+target extended-remote :3333
+
+# print demangled symbols
+set print asm-demangle on
+
+# set backtrace limit to not have infinite backtrace loops
+set backtrace limit 32
+
+# detect unhandled exceptions, hard faults and panics
+break DefaultHandler
+break HardFault
+break rust_begin_unwind
+
+# *try* to stop at the user entry point (it might be gone due to inlining)
+break main
+
+monitor arm semihosting enable
+
+# # send captured ITM to the file itm.fifo
+# # (the microcontroller SWO pin must be connected to the programmer SWO pin)
+# # 8000000 must match the core clock frequency
+# monitor tpiu config internal itm.txt uart off 8000000
+
+# # OR: make the microcontroller SWO pin output compatible with UART (8N1)
+# # 8000000 must match the core clock frequency
+# # 2000000 is the frequency of the SWO pin
+# monitor tpiu config external uart off 8000000 2000000
+
+# # enable ITM port 0
+# monitor itm port 0 on
+
+#load
+
+# start the process but immediately halt the processor
+#stepi
diff --git a/example-source/msp432-app/original-examples/crash.rs b/example-source/msp432-app/original-examples/crash.rs
new file mode 100644
index 0000000..fecde7a
--- /dev/null
+++ b/example-source/msp432-app/original-examples/crash.rs
@@ -0,0 +1,96 @@
+//! Debugging a crash (exception)
+//!
+//! Most crash conditions trigger a hard fault exception, whose handler is defined via
+//! `exception!(HardFault, ..)`. The `HardFault` handler has access to the exception frame, a
+//! snapshot of the CPU registers at the moment of the exception.
+//!
+//! This program crashes and the `HardFault` handler prints to the console the contents of the
+//! `ExceptionFrame` and then triggers a breakpoint. From that breakpoint one can see the backtrace
+//! that led to the exception.
+//!
+//! ``` text
+//! (gdb) continue
+//! Program received signal SIGTRAP, Trace/breakpoint trap.
+//! __bkpt () at asm/bkpt.s:3
+//! 3         bkpt
+//!
+//! (gdb) backtrace
+//! #0  __bkpt () at asm/bkpt.s:3
+//! #1  0x080030b4 in cortex_m::asm::bkpt () at $$/cortex-m-0.5.0/src/asm.rs:19
+//! #2  rust_begin_unwind (args=..., file=..., line=99, col=5) at $$/panic-semihosting-0.2.0/src/lib.rs:87
+//! #3  0x08001d06 in core::panicking::panic_fmt () at libcore/panicking.rs:71
+//! #4  0x080004a6 in crash::hard_fault (ef=0x20004fa0) at examples/crash.rs:99
+//! #5  0x08000548 in UserHardFault (ef=0x20004fa0) at <exception macros>:10
+//! #6  0x0800093a in HardFault () at asm.s:5
+//! Backtrace stopped: previous frame identical to this frame (corrupt stack?)
+//! ```
+//!
+//! In the console output one will find the state of the Program Counter (PC) register at the time
+//! of the exception.
+//!
+//! ``` text
+//! panicked at 'HardFault at ExceptionFrame {
+//!     r0: 0x2fffffff,
+//!     r1: 0x2fffffff,
+//!     r2: 0x080051d4,
+//!     r3: 0x080051d4,
+//!     r12: 0x20000000,
+//!     lr: 0x08000435,
+//!     pc: 0x08000ab6,
+//!     xpsr: 0x61000000
+//! }', examples/crash.rs:106:5
+//! ```
+//!
+//! This register contains the address of the instruction that caused the exception. In GDB one can
+//! disassemble the program around this address to observe the instruction that caused the
+//! exception.
+//!
+//! ``` text
+//! (gdb) disassemble/m 0x08000ab6
+//! Dump of assembler code for function core::ptr::read_volatile:
+//! 451     pub unsafe fn read_volatile<T>(src: *const T) -> T {
+//!    0x08000aae <+0>:     sub     sp, #16
+//!    0x08000ab0 <+2>:     mov     r1, r0
+//!    0x08000ab2 <+4>:     str     r0, [sp, #8]
+//!
+//! 452         intrinsics::volatile_load(src)
+//!    0x08000ab4 <+6>:     ldr     r0, [sp, #8]
+//! -> 0x08000ab6 <+8>:     ldr     r0, [r0, #0]
+//!    0x08000ab8 <+10>:    str     r0, [sp, #12]
+//!    0x08000aba <+12>:    ldr     r0, [sp, #12]
+//!    0x08000abc <+14>:    str     r1, [sp, #4]
+//!    0x08000abe <+16>:    str     r0, [sp, #0]
+//!    0x08000ac0 <+18>:    b.n     0x8000ac2 <core::ptr::read_volatile+20>
+//!
+//! 453     }
+//!    0x08000ac2 <+20>:    ldr     r0, [sp, #0]
+//!    0x08000ac4 <+22>:    add     sp, #16
+//!    0x08000ac6 <+24>:    bx      lr
+//!
+//! End of assembler dump.
+//! ```
+//!
+//! `ldr r0, [r0, #0]` caused the exception. This instruction tried to load (read) a 32-bit word
+//! from the address stored in the register `r0`. Looking again at the contents of `ExceptionFrame`
+//! we see that the `r0` contained the address `0x2FFF_FFFF` when this instruction was executed.
+//!
+//! ---
+
+#![no_main]
+#![no_std]
+
+extern crate panic_halt;
+
+use core::ptr;
+
+use cortex_m_rt::entry;
+
+#[entry]
+fn main() -> ! {
+    unsafe {
+        // read an address outside of the RAM region; this causes a HardFault exception
+        ptr::read_volatile(0x2FFF_FFFF as *const u32);
+    }
+
+    loop {}
+}
diff --git a/example-source/msp432-app/original-examples/exception.rs b/example-source/msp432-app/original-examples/exception.rs
new file mode 100644
index 0000000..756b85a
--- /dev/null
+++ b/example-source/msp432-app/original-examples/exception.rs
@@ -0,0 +1,37 @@
+//! Overriding an exception handler
+//!
+//! You can override an exception handler using the [`#[exception]`][1] attribute.
+//!
+//! [1]: https://rust-embedded.github.io/cortex-m-rt/0.6.1/cortex_m_rt_macros/fn.exception.html
+//!
+//! ---
+
+#![deny(unsafe_code)]
+#![no_main]
+#![no_std]
+
+extern crate panic_halt;
+
+use cortex_m::peripheral::syst::SystClkSource;
+use cortex_m::Peripherals;
+use cortex_m_rt::{entry, exception};
+use cortex_m_semihosting::hprint;
+
+#[entry]
+fn main() -> ! {
+    let p = Peripherals::take().unwrap();
+    let mut syst = p.SYST;
+
+    // configures the system timer to trigger a SysTick exception every second
+    syst.set_clock_source(SystClkSource::Core);
+    syst.set_reload(8_000_000); // period = 1s
+    syst.enable_counter();
+    syst.enable_interrupt();
+
+    loop {}
+}
+
+#[exception]
+fn SysTick() {
+    hprint!(".").unwrap();
+}
diff --git a/example-source/msp432-app/original-examples/hello.rs b/example-source/msp432-app/original-examples/hello.rs
new file mode 100644
index 0000000..8e8586e
--- /dev/null
+++ b/example-source/msp432-app/original-examples/hello.rs
@@ -0,0 +1,20 @@
+//! Prints "Hello, world!" on the host console using semihosting
+
+#![no_main]
+#![no_std]
+
+extern crate panic_halt;
+
+use cortex_m_rt::entry;
+use cortex_m_semihosting::{debug, hprintln};
+
+#[entry]
+fn main() -> ! {
+    hprintln!("Hello, world!").unwrap();
+
+    // exit QEMU
+    // NOTE do not run this on hardware; it can corrupt OpenOCD state
+    debug::exit(debug::EXIT_SUCCESS);
+
+    loop {}
+}
diff --git a/example-source/msp432-app/original-examples/itm.rs b/example-source/msp432-app/original-examples/itm.rs
new file mode 100644
index 0000000..f82f985
--- /dev/null
+++ b/example-source/msp432-app/original-examples/itm.rs
@@ -0,0 +1,33 @@
+//! Sends "Hello, world!" through the ITM port 0
+//!
+//! ITM is much faster than semihosting. Like 4 orders of magnitude or so.
+//!
+//! **NOTE** Cortex-M0 chips don't support ITM.
+//!
+//! You'll have to connect the microcontroller's SWO pin to the SWD interface. Note that some
+//! development boards don't provide this option.
+//!
+//! You'll need [`itmdump`] to receive the message on the host plus you'll need to uncomment two
+//! `monitor` commands in the `.gdbinit` file.
+//!
+//! [`itmdump`]: https://docs.rs/itm/0.2.1/itm/
+//!
+//! ---
+
+#![no_main]
+#![no_std]
+
+extern crate panic_halt;
+
+use cortex_m::{iprintln, Peripherals};
+use cortex_m_rt::entry;
+
+#[entry]
+fn main() -> ! {
+    let mut p = Peripherals::take().unwrap();
+    let stim = &mut p.ITM.stim[0];
+
+    iprintln!(stim, "Hello, world!");
+
+    loop {}
+}
diff --git a/example-source/msp432-app/original-examples/panic.rs b/example-source/msp432-app/original-examples/panic.rs
new file mode 100644
index 0000000..a323396
--- /dev/null
+++ b/example-source/msp432-app/original-examples/panic.rs
@@ -0,0 +1,28 @@
+//! Changing the panicking behavior
+//!
+//! The easiest way to change the panicking behavior is to use a different [panic handler crate][0].
+//!
+//! [0]: https://crates.io/keywords/panic-impl
+
+#![no_main]
+#![no_std]
+
+// Pick one of these panic handlers:
+
+// `panic!` halts execution; the panic message is ignored
+extern crate panic_halt;
+
+// Reports panic messages to the host stderr using semihosting
+// NOTE to use this you need to uncomment the `panic-semihosting` dependency in Cargo.toml
+// extern crate panic_semihosting;
+
+// Logs panic messages using the ITM (Instrumentation Trace Macrocell)
+// NOTE to use this you need to uncomment the `panic-itm` dependency in Cargo.toml
+// extern crate panic_itm;
+
+use cortex_m_rt::entry;
+
+#[entry]
+fn main() -> ! {
+    panic!("Oops")
+}
diff --git a/example-source/msp432-app/original-examples/test_on_host.rs b/example-source/msp432-app/original-examples/test_on_host.rs
new file mode 100644
index 0000000..1c75ed1
--- /dev/null
+++ b/example-source/msp432-app/original-examples/test_on_host.rs
@@ -0,0 +1,57 @@
+//! Conditionally compiling tests with std and our executable with no_std.
+//!
+//! Rust's built in unit testing framework requires the standard library,
+//! but we need to build our final executable with no_std.
+//! The testing framework also generates a `main` method, so we need to only use the `#[entry]`
+//! annotation when building our final image.
+//! For more information on why this example works, see this excellent blog post.
+//! https://os.phil-opp.com/unit-testing/
+//!
+//! Running this example:
+//!
+//! Ensure there are no targets specified under `[build]` in `.cargo/config`
+//! In order to make this work, we lose the convenience of having a default target that isn't the
+//! host.
+//!
+//! cargo build --example test_on_host --target thumbv7m-none-eabi
+//! cargo test --example test_on_host
+
+#![cfg_attr(test, allow(unused_imports))]
+
+#![cfg_attr(not(test), no_std)]
+#![cfg_attr(not(test), no_main)]
+
+// pick a panicking behavior
+#[cfg(not(test))]
+extern crate panic_halt; // you can put a breakpoint on `rust_begin_unwind` to catch panics
+// extern crate panic_abort; // requires nightly
+// extern crate panic_itm; // logs messages over ITM; requires ITM support
+// extern crate panic_semihosting; // logs messages to the host stderr; requires a debugger
+
+use cortex_m::asm;
+use cortex_m_rt::entry;
+
+#[cfg(not(test))]
+#[entry]
+fn main() -> ! {
+    asm::nop(); // To not have main optimize to abort in release mode, remove when you add code
+
+    loop {
+        // your code goes here
+    }
+}
+
+fn add(a: i32, b: i32) -> i32 {
+    a + b
+}
+
+#[cfg(test)]
+mod test {
+  use super::*;
+
+  #[test]
+  fn foo() {
+    println!("tests work!");
+    assert!(2 == add(1,1));
+  }
+}
diff --git a/example-source/msp432-app/src/main.rs b/example-source/msp432-app/src/main.rs
new file mode 100644
index 0000000..f505828
--- /dev/null
+++ b/example-source/msp432-app/src/main.rs
@@ -0,0 +1,81 @@
+#![no_std]
+#![no_main]
+
+// pick a panicking behavior
+extern crate panic_halt; // you can put a breakpoint on `rust_begin_unwind` to catch panics
+// extern crate panic_abort; // requires nightly
+// extern crate panic_itm; // logs messages over ITM; requires ITM support
+// extern crate panic_semihosting; // logs messages to the host stderr; requires a debugger
+
+use cortex_m::{self, peripheral::syst::SystClkSource};
+use cortex_m_rt::entry;
+use msp432p401r;
+
+use core::num::Wrapping;
+
+const PIN0: u8 = (1u8 << 0);
+const PIN1: u8 = (1u8 << 1);
+const PIN2: u8 = (1u8 << 2);
+//const PIN3: u8 = (1u8 << 3);
+const PIN4: u8 = (1u8 << 4);
+//const PIN5: u8 = (1u8 << 5);
+//const PIN6: u8 = (1u8 << 6);
+//const PIN7: u8 = (1u8 << 7);
+
+const WDOG_PWORD: u8 = 0x5a;
+
+#[entry]
+fn main() -> ! {
+    let cp = cortex_m::Peripherals::take().unwrap();
+    let p = msp432p401r::Peripherals::take().unwrap();
+
+    let mut syst = cp.SYST;
+    let wdt = p.WDT_A;
+    let dio = p.DIO;
+
+    // disable watchdog timer
+    wdt.wdtctl.write(|w| unsafe {
+        w.wdtpw().bits(WDOG_PWORD)
+         .wdthold().wdthold_1()
+    });
+
+    // configure the system timer to wrap around every ~1 second
+    syst.set_clock_source(SystClkSource::Core);
+    syst.set_reload(20_000);
+    syst.enable_counter();
+
+    // configure digital IO pins
+    dio.padir.modify(|_r, w| unsafe {
+        w.p1dir().bits(PIN0)
+         .p2dir().bits(PIN0 | PIN1 | PIN2)
+    });
+
+    // Enable pull-up on P1.4 switch
+    dio.paren.modify(|_r, w| unsafe { w.p1ren().bits(PIN4) });
+    dio.pads.modify(|_r, w| unsafe { w.p1ds().bits(PIN4) });
+
+    // Turn on LED1 on P1.0 and enable pull-up on P1.1 switch
+    dio.paout.write(|w| unsafe {
+        w.p1out().bits(PIN0 | PIN4)
+         .p2out().bits(0)
+    });
+
+    let mut count: Wrapping<u16> = Wrapping(0);
+    let mut input: u8;
+    loop {
+        while !syst.has_wrapped() {}
+
+        // The button pulls the input to GND
+        input = (dio.pain.read().p1in().bits() & PIN4) >> 4;
+
+        count += Wrapping(1);
+        let _led1: u8 = ((count.0 & 0x0100) >> 8) as u8;
+        let led2: u8 = ((count.0 & 0b0000_0111_0000_0000) >> 8) as u8;
+
+        // toggle LEDs
+        dio.paout.write(|w| unsafe {
+            w.p1out().bits(input | PIN4)
+             .p2out().bits(led2)
+        });
+    }
+}
diff --git a/example-source/msp432-app/upload.sh b/example-source/msp432-app/upload.sh
new file mode 100644
index 0000000..303492c
--- /dev/null
+++ b/example-source/msp432-app/upload.sh
@@ -0,0 +1 @@
+sudo /home/levi/energia-1.6.10E18/hardware/tools/DSLite/DebugServer/bin/DSLite load --config /home/levi/energia-1.6.10E18/hardware/tools/DSLite/MSP_EXP432P401R.ccxml --file ~/Projects/Rust/msp432-app/target/thumbv7em-none-eabihf/debug/msp432-app
diff --git a/example-source/msp432-hal/.gitignore b/example-source/msp432-hal/.gitignore
new file mode 100644
index 0000000..2f88dba
--- /dev/null
+++ b/example-source/msp432-hal/.gitignore
@@ -0,0 +1,3 @@
+/target
+**/*.rs.bk
+Cargo.lock
\ No newline at end of file
diff --git a/example-source/msp432-hal/Cargo.toml b/example-source/msp432-hal/Cargo.toml
new file mode 100644
index 0000000..e3ab850
--- /dev/null
+++ b/example-source/msp432-hal/Cargo.toml
@@ -0,0 +1,19 @@
+[package]
+name = "msp432-hal"
+version = "0.1.0"
+authors = ["Levi Pearson <levipearson@gmail.com>"]
+categories = ["embedded", "hardware-support", "no-std"]
+description = "HAL for the TI MSP432 family of microcontrollers"
+keywords = ["arm", "cortex-m", "msp432", "hal"]
+edition = "2018"
+
+[dependencies]
+cortex-m = "0.5"
+embedded-hal = "0.2"
+nb = "0.1"
+msp432p401r = { path = "../msp432p401r" }
+void = { version = "1.0", default-features = false }
+cast = { version = "0.2", default-features = false }
+
+[features]
+rt = ["msp432p401r/rt"]
\ No newline at end of file
diff --git a/example-source/msp432-hal/src/cs.rs b/example-source/msp432-hal/src/cs.rs
new file mode 100644
index 0000000..3b2c2a3
--- /dev/null
+++ b/example-source/msp432-hal/src/cs.rs
@@ -0,0 +1,63 @@
+//! Clock System
+
+use core::cmp;
+use pac::{cs, CS};
+
+use crate::time::Hertz;
+
+
+/// Extension trait that constrains the `CS` peripheral
+pub trait CsExt {
+    /// Constrains the `CS` peripheral so that it plays nicely with other abstractions
+    fn constrain(self) -> Cs;
+}
+
+impl CsExt for CS {
+    fn constrain(self) -> Cs {
+        Cs {
+
+        }
+    }
+}
+
+/*
++--------+-----------------------+---------------+-------------------------------------+
+| Clock  | Default Clock Source  | Default Clock | Description                         |
+|        |                       | Frequency     |                                     |
++========+=======================+===============+=====================================+
+| MCLK   | DCO                   | 3 MHz         | Master Clock - Sources CPU and      |
+|        |                       |               | peripherals                         |
++--------+-----------------------+---------------+-------------------------------------+
+| HSMCLK | DCO                   | 3 MHz         | Subsystem Master Clock - Sources    |
+|        |                       |               | peripherals                         |
++--------+-----------------------+---------------+-------------------------------------+
+| SMCLK  | DCO                   | 3 MHz         | Low-speed subsystem master clock -  |
+|        |                       |               | Sources peripherals                 |
++--------+-----------------------+---------------+-------------------------------------+
+| ACLK   | LFXT (or REFO if no   | 32.768 kHz    | Auxiliary clock - Sources           |
+|        | crystal present)      |               | peripherals                         |
++--------+-----------------------+---------------+-------------------------------------+
+| BCLK   | LFXT (or REFO if no   | 32.768 kHz    | Low-speed backup domain clock -     |
+|        | crystal present)      |               | Sources LPM peripherals             |
++--------+-----------------------+---------------+-------------------------------------+
+*/
+
+pub struct Cs {
+
+}
+
+/// Frozen clock frequencies
+///
+/// This value holds the current clocks frequencies and indicates that they can
+/// no longer be changed
+#[derive(Clone, Copy)]
+pub struct Clocks {
+    sysclk: Hertz,
+}
+
+impl Clocks {
+    /// Returns the system (core) frequency
+    pub fn sysclk(&self) -> Hertz {
+        self.sysclk
+    }
+}
diff --git a/example-source/msp432-hal/src/delay.rs b/example-source/msp432-hal/src/delay.rs
new file mode 100644
index 0000000..00d8f38
--- /dev/null
+++ b/example-source/msp432-hal/src/delay.rs
@@ -0,0 +1,74 @@
+//! Delays
+
+use cast::u32;
+use cortex_m::peripheral::syst::SystClkSource;
+use cortex_m::peripheral::SYST;
+
+use hal::blocking::delay::{DelayMs, DelayUs};
+use crate::cs::Clocks;
+
+/// System timer (SysTick) as a delay provider
+pub struct Delay {
+    clocks: Clocks,
+    syst: SYST,
+}
+
+impl Delay {
+    /// Configure the system timer (SysTick) as a delay provider
+    pub fn new(mut syst: SYST, clocks: Clocks) -> Self {
+        syst.set_clock_source(SystClkSource::Core);
+
+        Delay { syst, clocks }
+    }
+
+    /// Release the system timer (SysTick) resource
+    pub fn free(self) -> SYST {
+        self.syst
+    }
+}
+
+impl DelayMs<u32> for Delay {
+    fn delay_ms(&mut self, ms: u32) {
+        self.delay_us(ms * 1_000);
+    }
+}
+
+impl DelayMs<u16> for Delay {
+    fn delay_ms(&mut self, ms: u16) {
+        self.delay_ms(u32(ms));
+    }
+}
+
+impl DelayMs<u8> for Delay {
+    fn delay_ms(&mut self, ms: u8) {
+        self.delay_ms(u32(ms));
+    }
+}
+
+impl DelayUs<u32> for Delay {
+    fn delay_us(&mut self, us: u32) {
+        let rvr = us * (self.clocks.sysclk().0 / 1_000_000);
+
+        assert!(rvr < (1 << 24));
+
+        self.syst.set_reload(rvr);
+        self.syst.clear_current();
+        self.syst.enable_counter();
+
+        while !self.syst.has_wrapped() {}
+
+        self.syst.disable_counter();
+    }
+}
+
+impl DelayUs<u16> for Delay {
+    fn delay_us(&mut self, us: u16) {
+        self.delay_us(u32(us));
+    }
+}
+
+impl DelayUs<u8> for Delay {
+    fn delay_us(&mut self, us: u8) {
+        self.delay_us(u32(us));
+    }
+}
diff --git a/example-source/msp432-hal/src/gpio.rs b/example-source/msp432-hal/src/gpio.rs
new file mode 100644
index 0000000..c76bf3e
--- /dev/null
+++ b/example-source/msp432-hal/src/gpio.rs
@@ -0,0 +1,22 @@
+//! General Purpose Input / Output
+
+use pac::DIO;
+use core::marker::PhantomData;
+use hal::digital::OutputPin;
+
+pub trait GpioExt {
+    type Parts;
+
+    /// Consume and split the device into its constituent parts
+    fn split(self) -> Self::Parts;
+}
+
+/// Represents a pin configured for input.
+pub struct Input<MODE> {
+    _mode: PhantomData<MODE>,
+}
+
+/// Represents a pin configured for output.
+pub struct Output<MODE> {
+    _mode: PhantomData<MODE>,
+}
diff --git a/example-source/msp432-hal/src/lib.rs b/example-source/msp432-hal/src/lib.rs
new file mode 100644
index 0000000..9cfa8f7
--- /dev/null
+++ b/example-source/msp432-hal/src/lib.rs
@@ -0,0 +1,26 @@
+//! HAL for the MSP432 family of microcontrollers
+//!
+//! This is an implementation of the [`embedded-hal`] traits for the MSP432 family of
+//! microcontrollers.
+//!
+//! [`embedded-hal`]: https://github.com/japaric/embedded-hal
+//!
+//! # Usage
+//!
+//! To build applications (binary crates) using this crate follow the [cortex-m-quickstart]
+//! instructions and add this crate as a dependency in step number 5 and make sure you enable the
+//! "rt" Cargo feature of this crate.
+//!
+//! [cortex-m-quickstart]: https://docs.rs/cortex-m-quickstart/~0.3
+
+#![warn(missing_docs)]
+#![no_std]
+
+extern crate embedded_hal as hal;
+extern crate msp432p401r as pac;
+
+pub mod prelude;
+pub mod gpio;
+pub mod delay;
+pub mod cs;
+pub mod time;
diff --git a/example-source/msp432-hal/src/prelude.rs b/example-source/msp432-hal/src/prelude.rs
new file mode 100644
index 0000000..5b13046
--- /dev/null
+++ b/example-source/msp432-hal/src/prelude.rs
@@ -0,0 +1,3 @@
+//! Prelude
+
+pub use hal::prelude::*;
diff --git a/example-source/msp432-hal/src/time.rs b/example-source/msp432-hal/src/time.rs
new file mode 100644
index 0000000..7c2ba15
--- /dev/null
+++ b/example-source/msp432-hal/src/time.rs
@@ -0,0 +1,117 @@
+//! Time units
+
+use cortex_m::peripheral::DWT;
+use crate::cs::Clocks;
+
+/// Bits per seconds
+#[derive(Clone, Copy)]
+pub struct Bps(pub u32);
+
+/// Hertz
+#[derive(Clone, Copy)]
+pub struct Hertz(pub u32);
+
+/// KiloHertz
+#[derive(Clone, Copy)]
+pub struct KiloHertz(pub u32);
+
+/// MegaHertz
+#[derive(Clone, Copy)]
+pub struct MegaHertz(pub u32);
+
+
+/// Extension trait to add convenience methods to `u32`
+pub trait U32Ext {
+    /// Wrap in `Bps`
+    fn bps(self) -> Bps;
+
+    /// Wrap in `Hertz`
+    fn hz(self) -> Hertz;
+
+    /// Wrap in `KiloHertz`
+    fn khz(self) -> KiloHertz;
+
+    /// Wrap in `MegaHertz`
+    fn mhz(self) -> MegaHertz;
+}
+
+impl U32Ext for u32 {
+    fn bps(self) -> Bps {
+        Bps(self)
+    }
+
+    fn hz(self) -> Hertz {
+        Hertz(self)
+    }
+
+    fn khz(self) -> KiloHertz {
+        KiloHertz(self)
+    }
+
+    fn mhz(self) -> MegaHertz {
+        MegaHertz(self)
+    }
+}
+
+impl Into<Hertz> for KiloHertz {
+    fn into(self) -> Hertz {
+        Hertz(self.0 * 1_000)
+    }
+}
+
+impl Into<Hertz> for MegaHertz {
+    fn into(self) -> Hertz {
+        Hertz(self.0 * 1_000_000)
+    }
+}
+
+impl Into<KiloHertz> for MegaHertz {
+    fn into(self) -> KiloHertz {
+        KiloHertz(self.0 * 1_000)
+    }
+}
+
+/// A monotonic nondecreasing timer
+#[derive(Clone, Copy)]
+pub struct MonoTimer {
+    frequency: Hertz,
+}
+
+impl MonoTimer {
+    /// Create a new monotonic timer
+    pub fn new(mut dwt: DWT, clocks: Clocks) -> Self {
+        dwt.enable_cycle_counter();
+
+        // can't stop or reset CYCCNT
+        drop(dwt);
+
+        MonoTimer {
+            frequency: clocks.sysclk(),
+        }
+    }
+
+    /// Return the frequency at which the timer is operating
+    pub fn frequency(&self) -> Hertz {
+        self.frequency
+    }
+
+    /// Returns an `Instant` corresponding to "now"
+    pub fn now(&self) -> Instant {
+        Instant {
+            now: DWT::get_cycle_count(),
+        }
+    }
+}
+
+/// A measurement from a monotonically nondecreasing clock
+#[derive(Clone, Copy)]
+pub struct Instant {
+    now: u32,
+}
+
+impl Instant {
+    /// Ticks elapsed since the `Instant` was created
+    pub fn elapsed(&self) -> u32 {
+        DWT::get_cycle_count().wrapping_sub(self.now)
+    }
+}
diff --git a/example-source/msp432p401r/.gitignore b/example-source/msp432p401r/.gitignore
new file mode 100644
index 0000000..2f88dba
--- /dev/null
+++ b/example-source/msp432p401r/.gitignore
@@ -0,0 +1,3 @@
+/target
+**/*.rs.bk
+Cargo.lock
\ No newline at end of file
diff --git a/example-source/msp432p401r/Cargo.toml b/example-source/msp432p401r/Cargo.toml
new file mode 100644
index 0000000..9dcc113
--- /dev/null
+++ b/example-source/msp432p401r/Cargo.toml
@@ -0,0 +1,17 @@
+[package]
+name = "msp432p401r"
+version = "0.1.0"
+authors = ["Levi Pearson <levipearson@gmail.com>"]
+edition = "2018"
+
+[dependencies]
+bare-metal = "0.2.0"
+cortex-m = "0.5.8"
+vcell = "0.1.0"
+
+[dependencies.cortex-m-rt]
+optional = true
+version = "0.6.5"
+
+[features]
+rt = ["cortex-m-rt/device"]
diff --git a/example-source/msp432p401r/MSP432P401R.svd b/example-source/msp432p401r/MSP432P401R.svd
new file mode 100644
index 0000000..17cd901
--- /dev/null
+++ b/example-source/msp432p401r/MSP432P401R.svd
@@ -0,0 +1,42237 @@
+<?xml version="1.0" encoding="utf-8"?>
+<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
+
+   <vendor>Texas Instruments</vendor>
+   <vendorID>ti.com</vendorID>
+   <name>MSP432P401R</name>
+   <version>3.230</version>
+   <description>ARM Cortex-M4 MSP432P4xx Device</description>
+   <licenseText>
+\n
+    Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/\n
+\n
+    Redistribution and use in source and binary forms, with or without\n
+    modification, are permitted provided that the following conditions\n
+    are met:
+\n
+    Redistributions of source code must retain the above copyright\n
+    notice, this list of conditions and the following disclaimer.\n
+\n
+    Redistributions in binary form must reproduce the above copyright\n
+    notice, this list of conditions and the following disclaimer in the\n
+    documentation and/or other materials provided with the\n
+    distribution.\n
+\n
+    Neither the name of Texas Instruments Incorporated nor the names of\n
+    its contributors may be used to endorse or promote products derived\n
+    from this software without specific prior written permission.\n
+\n
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n
+    "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n
+    LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n
+    A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n
+    OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n
+    SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n
+    LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n
+    DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n
+    THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n
+    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n
+    OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n
+\n
+  </licenseText>
+   <!-- Bus Interface Properties -->
+   <addressUnitBits>8</addressUnitBits> 
+   <width>32</width>
+   <!-- -->
+   <!-- Register Default Properties -->
+   <size>32</size>
+   <resetValue>0x00000000</resetValue>
+   <resetMask>0xffffffff</resetMask>
+   <!-- -->
+   <peripherals>
+    <peripheral>
+        <name>TLV</name>
+        <version>356.0</version>
+        <description>TLV</description>
+        <baseAddress>0x201000</baseAddress>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x15C</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>TLV_CHECKSUM</name>
+                  <displayName>TLV_CHECKSUM</displayName>
+                  <description>TLV Checksum</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+            </register>
+            <register>
+                  <name>DEVICE_INFO_TAG</name>
+                  <displayName>DEVICE_INFO_TAG</displayName>
+                  <description>Device Info Tag</description>
+                  <addressOffset>0x4</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x0000000b</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>DEVICE_INFO_LEN</name>
+                  <displayName>DEVICE_INFO_LEN</displayName>
+                  <description>Device Info Length</description>
+                  <addressOffset>0x8</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>DEVICE_ID</name>
+                  <displayName>DEVICE_ID</displayName>
+                  <description>Device ID</description>
+                  <addressOffset>0xC</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>HWREV</name>
+                  <displayName>HWREV</displayName>
+                  <description>HW Revision</description>
+                  <addressOffset>0x10</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>BCREV</name>
+                  <displayName>BCREV</displayName>
+                  <description>Boot Code Revision</description>
+                  <addressOffset>0x14</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>ROM_DRVLIB_REV</name>
+                  <displayName>ROM_DRVLIB_REV</displayName>
+                  <description>ROM Driver Library Revision</description>
+                  <addressOffset>0x18</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>DIE_REC_TAG</name>
+                  <displayName>DIE_REC_TAG</displayName>
+                  <description>Die Record Tag</description>
+                  <addressOffset>0x1C</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x0000000c</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>DIE_REC_LEN</name>
+                  <displayName>DIE_REC_LEN</displayName>
+                  <description>Die Record Length</description>
+                  <addressOffset>0x20</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>DIE_XPOS</name>
+                  <displayName>DIE_XPOS</displayName>
+                  <description>Die X-Position</description>
+                  <addressOffset>0x24</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>DIE_YPOS</name>
+                  <displayName>DIE_YPOS</displayName>
+                  <description>Die Y-Position</description>
+                  <addressOffset>0x28</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>WAFER_ID</name>
+                  <displayName>WAFER_ID</displayName>
+                  <description>Wafer ID</description>
+                  <addressOffset>0x2C</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>LOT_ID</name>
+                  <displayName>LOT_ID</displayName>
+                  <description>Lot ID</description>
+                  <addressOffset>0x30</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RESERVED0</name>
+                  <displayName>RESERVED0</displayName>
+                  <description>Reserved</description>
+                  <addressOffset>0x34</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RESERVED1</name>
+                  <displayName>RESERVED1</displayName>
+                  <description>Reserved</description>
+                  <addressOffset>0x38</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RESERVED2</name>
+                  <displayName>RESERVED2</displayName>
+                  <description>Reserved</description>
+                  <addressOffset>0x3C</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>TEST_RESULTS</name>
+                  <displayName>TEST_RESULTS</displayName>
+                  <description>Test Results</description>
+                  <addressOffset>0x40</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>CS_CAL_TAG</name>
+                  <displayName>CS_CAL_TAG</displayName>
+                  <description>Clock System Calibration Tag</description>
+                  <addressOffset>0x44</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000003</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>CS_CAL_LEN</name>
+                  <displayName>CS_CAL_LEN</displayName>
+                  <description>Clock System Calibration Length</description>
+                  <addressOffset>0x48</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>DCOIR_FCAL_RSEL04</name>
+                  <displayName>DCOIR_FCAL_RSEL04</displayName>
+                  <description>DCO IR mode: Frequency calibration for DCORSEL 0 to 4</description>
+                  <addressOffset>0x4C</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>DCOIR_FCAL_RSEL5</name>
+                  <displayName>DCOIR_FCAL_RSEL5</displayName>
+                  <description>DCO IR mode: Frequency calibration for DCORSEL 5</description>
+                  <addressOffset>0x50</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RESERVED3</name>
+                  <displayName>RESERVED3</displayName>
+                  <description>Reserved</description>
+                  <addressOffset>0x54</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RESERVED4</name>
+                  <displayName>RESERVED4</displayName>
+                  <description>Reserved</description>
+                  <addressOffset>0x58</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RESERVED5</name>
+                  <displayName>RESERVED5</displayName>
+                  <description>Reserved</description>
+                  <addressOffset>0x5C</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RESERVED6</name>
+                  <displayName>RESERVED6</displayName>
+                  <description>Reserved</description>
+                  <addressOffset>0x60</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>DCOIR_CONSTK_RSEL04</name>
+                  <displayName>DCOIR_CONSTK_RSEL04</displayName>
+                  <description>DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4</description>
+                  <addressOffset>0x64</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>DCOIR_CONSTK_RSEL5</name>
+                  <displayName>DCOIR_CONSTK_RSEL5</displayName>
+                  <description>DCO IR mode: DCO Constant (K) for DCORSEL 5</description>
+                  <addressOffset>0x68</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>DCOER_FCAL_RSEL04</name>
+                  <displayName>DCOER_FCAL_RSEL04</displayName>
+                  <description>DCO ER mode: Frequency calibration for DCORSEL 0 to 4</description>
+                  <addressOffset>0x6C</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>DCOER_FCAL_RSEL5</name>
+                  <displayName>DCOER_FCAL_RSEL5</displayName>
+                  <description>DCO ER mode: Frequency calibration for DCORSEL 5</description>
+                  <addressOffset>0x70</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RESERVED7</name>
+                  <displayName>RESERVED7</displayName>
+                  <description>Reserved</description>
+                  <addressOffset>0x74</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RESERVED8</name>
+                  <displayName>RESERVED8</displayName>
+                  <description>Reserved</description>
+                  <addressOffset>0x78</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RESERVED9</name>
+                  <displayName>RESERVED9</displayName>
+                  <description>Reserved</description>
+                  <addressOffset>0x7C</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RESERVED10</name>
+                  <displayName>RESERVED10</displayName>
+                  <description>Reserved</description>
+                  <addressOffset>0x80</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>DCOER_CONSTK_RSEL04</name>
+                  <displayName>DCOER_CONSTK_RSEL04</displayName>
+                  <description>DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4</description>
+                  <addressOffset>0x84</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>DCOER_CONSTK_RSEL5</name>
+                  <displayName>DCOER_CONSTK_RSEL5</displayName>
+                  <description>DCO ER mode: DCO Constant (K) for DCORSEL 5</description>
+                  <addressOffset>0x88</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>ADC14_CAL_TAG</name>
+                  <displayName>ADC14_CAL_TAG</displayName>
+                  <description>ADC14 Calibration Tag</description>
+                  <addressOffset>0x8C</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000005</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>ADC14_CAL_LEN</name>
+                  <displayName>ADC14_CAL_LEN</displayName>
+                  <description>ADC14 Calibration Length</description>
+                  <addressOffset>0x90</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>ADC_GAIN_FACTOR</name>
+                  <displayName>ADC_GAIN_FACTOR</displayName>
+                  <description>ADC Gain Factor</description>
+                  <addressOffset>0x94</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>ADC_OFFSET</name>
+                  <displayName>ADC_OFFSET</displayName>
+                  <description>ADC Offset</description>
+                  <addressOffset>0x98</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RESERVED11</name>
+                  <displayName>RESERVED11</displayName>
+                  <description>Reserved</description>
+                  <addressOffset>0x9C</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RESERVED12</name>
+                  <displayName>RESERVED12</displayName>
+                  <description>Reserved</description>
+                  <addressOffset>0xA0</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RESERVED13</name>
+                  <displayName>RESERVED13</displayName>
+                  <description>Reserved</description>
+                  <addressOffset>0xA4</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RESERVED14</name>
+                  <displayName>RESERVED14</displayName>
+                  <description>Reserved</description>
+                  <addressOffset>0xA8</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RESERVED15</name>
+                  <displayName>RESERVED15</displayName>
+                  <description>Reserved</description>
+                  <addressOffset>0xAC</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RESERVED16</name>
+                  <displayName>RESERVED16</displayName>
+                  <description>Reserved</description>
+                  <addressOffset>0xB0</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RESERVED17</name>
+                  <displayName>RESERVED17</displayName>
+                  <description>Reserved</description>
+                  <addressOffset>0xB4</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RESERVED18</name>
+                  <displayName>RESERVED18</displayName>
+                  <description>Reserved</description>
+                  <addressOffset>0xB8</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RESERVED19</name>
+                  <displayName>RESERVED19</displayName>
+                  <description>Reserved</description>
+                  <addressOffset>0xBC</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RESERVED20</name>
+                  <displayName>RESERVED20</displayName>
+                  <description>Reserved</description>
+                  <addressOffset>0xC0</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RESERVED21</name>
+                  <displayName>RESERVED21</displayName>
+                  <description>Reserved</description>
+                  <addressOffset>0xC4</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RESERVED22</name>
+                  <displayName>RESERVED22</displayName>
+                  <description>Reserved</description>
+                  <addressOffset>0xC8</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RESERVED23</name>
+                  <displayName>RESERVED23</displayName>
+                  <description>Reserved</description>
+                  <addressOffset>0xCC</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RESERVED24</name>
+                  <displayName>RESERVED24</displayName>
+                  <description>Reserved</description>
+                  <addressOffset>0xD0</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RESERVED25</name>
+                  <displayName>RESERVED25</displayName>
+                  <description>Reserved</description>
+                  <addressOffset>0xD4</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RESERVED26</name>
+                  <displayName>RESERVED26</displayName>
+                  <description>Reserved</description>
+                  <addressOffset>0xD8</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>ADC14_REF1P2V_TS30C</name>
+                  <displayName>ADC14_REF1P2V_TS30C</displayName>
+                  <description>ADC14 1.2V Reference Temp. Sensor 30C</description>
+                  <addressOffset>0xDC</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>ADC14_REF1P2V_TS85C</name>
+                  <displayName>ADC14_REF1P2V_TS85C</displayName>
+                  <description>ADC14 1.2V Reference Temp. Sensor 85C</description>
+                  <addressOffset>0xE0</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>ADC14_REF1P45V_TS30C</name>
+                  <displayName>ADC14_REF1P45V_TS30C</displayName>
+                  <description>ADC14 1.45V Reference Temp. Sensor 30C</description>
+                  <addressOffset>0xE4</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>ADC14_REF1P45V_TS85C</name>
+                  <displayName>ADC14_REF1P45V_TS85C</displayName>
+                  <description>ADC14 1.45V Reference Temp. Sensor 85C</description>
+                  <addressOffset>0xE8</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>ADC14_REF2P5V_TS30C</name>
+                  <displayName>ADC14_REF2P5V_TS30C</displayName>
+                  <description>ADC14 2.5V Reference Temp. Sensor 30C</description>
+                  <addressOffset>0xEC</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>ADC14_REF2P5V_TS85C</name>
+                  <displayName>ADC14_REF2P5V_TS85C</displayName>
+                  <description>ADC14 2.5V Reference Temp. Sensor 85C</description>
+                  <addressOffset>0xF0</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>REF_CAL_TAG</name>
+                  <displayName>REF_CAL_TAG</displayName>
+                  <description>REF Calibration Tag</description>
+                  <addressOffset>0xF4</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000008</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>REF_CAL_LEN</name>
+                  <displayName>REF_CAL_LEN</displayName>
+                  <description>REF Calibration Length</description>
+                  <addressOffset>0xF8</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>REF_1P2V</name>
+                  <displayName>REF_1P2V</displayName>
+                  <description>REF 1.2V Reference</description>
+                  <addressOffset>0xFC</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>REF_1P45V</name>
+                  <displayName>REF_1P45V</displayName>
+                  <description>REF 1.45V Reference</description>
+                  <addressOffset>0x100</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>REF_2P5V</name>
+                  <displayName>REF_2P5V</displayName>
+                  <description>REF 2.5V Reference</description>
+                  <addressOffset>0x104</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>FLASH_INFO_TAG</name>
+                  <displayName>FLASH_INFO_TAG</displayName>
+                  <description>Flash Info Tag</description>
+                  <addressOffset>0x108</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000004</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>FLASH_INFO_LEN</name>
+                  <displayName>FLASH_INFO_LEN</displayName>
+                  <description>Flash Info Length</description>
+                  <addressOffset>0x10C</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>FLASH_MAX_PROG_PULSES</name>
+                  <displayName>FLASH_MAX_PROG_PULSES</displayName>
+                  <description>Flash Maximum Programming Pulses</description>
+                  <addressOffset>0x110</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>FLASH_MAX_ERASE_PULSES</name>
+                  <displayName>FLASH_MAX_ERASE_PULSES</displayName>
+                  <description>Flash Maximum Erase Pulses</description>
+                  <addressOffset>0x114</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RANDOM_NUM_TAG</name>
+                  <displayName>RANDOM_NUM_TAG</displayName>
+                  <description>128-bit Random Number Tag</description>
+                  <addressOffset>0x118</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x0000000d</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RANDOM_NUM_LEN</name>
+                  <displayName>RANDOM_NUM_LEN</displayName>
+                  <description>128-bit Random Number Length</description>
+                  <addressOffset>0x11C</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RANDOM_NUM_1</name>
+                  <displayName>RANDOM_NUM_1</displayName>
+                  <description>32-bit Random Number 1</description>
+                  <addressOffset>0x120</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RANDOM_NUM_2</name>
+                  <displayName>RANDOM_NUM_2</displayName>
+                  <description>32-bit Random Number 2</description>
+                  <addressOffset>0x124</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RANDOM_NUM_3</name>
+                  <displayName>RANDOM_NUM_3</displayName>
+                  <description>32-bit Random Number 3</description>
+                  <addressOffset>0x128</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>RANDOM_NUM_4</name>
+                  <displayName>RANDOM_NUM_4</displayName>
+                  <description>32-bit Random Number 4</description>
+                  <addressOffset>0x12C</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>BSL_CFG_TAG</name>
+                  <displayName>BSL_CFG_TAG</displayName>
+                  <description>BSL Configuration Tag</description>
+                  <addressOffset>0x130</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x0000000f</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>BSL_CFG_LEN</name>
+                  <displayName>BSL_CFG_LEN</displayName>
+                  <description>BSL Configuration Length</description>
+                  <addressOffset>0x134</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>BSL_PERIPHIF_SEL</name>
+                  <displayName>BSL_PERIPHIF_SEL</displayName>
+                  <description>BSL Peripheral Interface Selection</description>
+                  <addressOffset>0x138</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>BSL_PORTIF_CFG_UART</name>
+                  <displayName>BSL_PORTIF_CFG_UART</displayName>
+                  <description>BSL Port Interface Configuration for UART</description>
+                  <addressOffset>0x13C</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>BSL_PORTIF_CFG_SPI</name>
+                  <displayName>BSL_PORTIF_CFG_SPI</displayName>
+                  <description>BSL Port Interface Configuration for SPI</description>
+                  <addressOffset>0x140</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>BSL_PORTIF_CFG_I2C</name>
+                  <displayName>BSL_PORTIF_CFG_I2C</displayName>
+                  <description>BSL Port Interface Configuration for I2C</description>
+                  <addressOffset>0x144</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+            <register>
+                  <name>TLV_END</name>
+                  <displayName>TLV_END</displayName>
+                  <description>TLV End Word</description>
+                  <addressOffset>0x148</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x0bd0e11d</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>TIMER_A0</name>
+        <version>356.0</version>
+        <description>TIMER_A0</description>
+        <baseAddress>0x40000000</baseAddress>
+        <interrupt>
+            <name>TA0_0_IRQ</name>
+            <description>TA0_0 Interrupt</description>
+            <value>8</value>
+        </interrupt>
+        <interrupt>
+            <name>TA0_N_IRQ</name>
+            <description>TA0_N Interrupt</description>
+            <value>9</value>
+        </interrupt>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x30</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>TAxCTL</name>
+                  <displayName>CTL</displayName>
+                  <description>TimerAx Control Register</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>TAIFG</name>
+                        <description>TimerA interrupt flag</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>TAIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TAIE</name>
+                        <description>TimerA interrupt enable</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>TAIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TACLR</name>
+                        <description>TimerA clear</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MC</name>
+                        <description>Mode control</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>MC_0</name>
+                                <description>Stop mode: Timer is halted</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>MC_1</name>
+                                <description>Up mode: Timer counts up to TAxCCR0</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>MC_2</name>
+                                <description>Continuous mode: Timer counts up to 0FFFFh</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>MC_3</name>
+                                <description>Up/down mode: Timer counts up to TAxCCR0 then down to 0000h</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ID</name>
+                        <description>Input divider</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ID_0</name>
+                                <description>/1</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ID_1</name>
+                                <description>/2</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ID_2</name>
+                                <description>/4</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ID_3</name>
+                                <description>/8</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TASSEL</name>
+                        <description>TimerA clock source select</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>TASSEL_0</name>
+                                <description>TAxCLK</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TASSEL_1</name>
+                                <description>ACLK</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TASSEL_2</name>
+                                <description>SMCLK</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TASSEL_3</name>
+                                <description>INCLK</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <dim>5</dim>
+                  <dimIncrement>2</dimIncrement>
+                  <dimIndex>0,1,2,3,4</dimIndex>
+                  <name>TAxCCTL[%s]</name>
+                  <displayName>CCTL[%s]</displayName>
+                  <description>Timer_A Capture/Compare Control Register</description>
+                  <addressOffset>0x2</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000fff7</resetMask>
+                  <fields>
+                    <field>
+                        <name>CCIFG</name>
+                        <description>Capture/compare interrupt flag</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CCIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CCIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>COV</name>
+                        <description>Capture overflow</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>COV_0</name>
+                                <description>No capture overflow occurred</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>COV_1</name>
+                                <description>Capture overflow occurred</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUT</name>
+                        <description>Output</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>OUT_0</name>
+                                <description>Output low</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUT_1</name>
+                                <description>Output high</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CCI</name>
+                        <description>Capture/compare input</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CCIE</name>
+                        <description>Capture/compare interrupt enable</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CCIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CCIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTMOD</name>
+                        <description>Output mode</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>OUTMOD_0</name>
+                                <description>OUT bit value</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUTMOD_1</name>
+                                <description>Set</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUTMOD_2</name>
+                                <description>Toggle/reset</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUTMOD_3</name>
+                                <description>Set/reset</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUTMOD_4</name>
+                                <description>Toggle</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUTMOD_5</name>
+                                <description>Reset</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUTMOD_6</name>
+                                <description>Toggle/set</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUTMOD_7</name>
+                                <description>Reset/set</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CAP</name>
+                        <description>Capture mode</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CAP_0</name>
+                                <description>Compare mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAP_1</name>
+                                <description>Capture mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SCCI</name>
+                        <description>Synchronized capture/compare input</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCS</name>
+                        <description>Synchronize capture source</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SCS_0</name>
+                                <description>Asynchronous capture</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SCS_1</name>
+                                <description>Synchronous capture</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CCIS</name>
+                        <description>Capture/compare input select</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CCIS_0</name>
+                                <description>CCIxA</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CCIS_1</name>
+                                <description>CCIxB</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CCIS_2</name>
+                                <description>GND</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CCIS_3</name>
+                                <description>VCC</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CM</name>
+                        <description>Capture mode</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CM_0</name>
+                                <description>No capture</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CM_1</name>
+                                <description>Capture on rising edge</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CM_2</name>
+                                <description>Capture on falling edge</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CM_3</name>
+                                <description>Capture on both rising and falling edges</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>TAxR</name>
+                  <displayName>R</displayName>
+                  <description>TimerA register</description>
+                  <addressOffset>0x10</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+            </register>
+            <register>
+                  <dim>5</dim>
+                  <dimIncrement>2</dimIncrement>
+                  <dimIndex>0,1,2,3,4</dimIndex>
+                  <name>TAxCCR[%s]</name>
+                  <displayName>CCR[%s]</displayName>
+                  <description>Timer_A Capture/Compare  Register</description>
+                  <addressOffset>0x12</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>TAxR</name>
+                        <description>TimerA register</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>TAxEX0</name>
+                  <displayName>EX0</displayName>
+                  <description>TimerAx Expansion 0 Register</description>
+                  <addressOffset>0x20</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>TAIDEX</name>
+                        <description>Input divider expansion</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>TAIDEX_0</name>
+                                <description>Divide by 1</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIDEX_1</name>
+                                <description>Divide by 2</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIDEX_2</name>
+                                <description>Divide by 3</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIDEX_3</name>
+                                <description>Divide by 4</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIDEX_4</name>
+                                <description>Divide by 5</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIDEX_5</name>
+                                <description>Divide by 6</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIDEX_6</name>
+                                <description>Divide by 7</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIDEX_7</name>
+                                <description>Divide by 8</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>TAxIV</name>
+                  <displayName>IV</displayName>
+                  <description>TimerAx Interrupt Vector Register</description>
+                  <addressOffset>0x2E</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>TAIV</name>
+                        <description>TimerA interrupt vector value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>TAIV_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>TAIV_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIV_2</name>
+                                <description>Interrupt Source: Capture/compare 1; Interrupt Flag: TAxCCR1 CCIFG; Interrupt Priority: Highest</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIV_4</name>
+                                <description>Interrupt Source: Capture/compare 2; Interrupt Flag: TAxCCR2 CCIFG</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIV_6</name>
+                                <description>Interrupt Source: Capture/compare 3; Interrupt Flag: TAxCCR3 CCIFG</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIV_8</name>
+                                <description>Interrupt Source: Capture/compare 4; Interrupt Flag: TAxCCR4 CCIFG</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIV_10</name>
+                                <description>Interrupt Source: Capture/compare 5; Interrupt Flag: TAxCCR5 CCIFG</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIV_12</name>
+                                <description>Interrupt Source: Capture/compare 6; Interrupt Flag: TAxCCR6 CCIFG</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIV_14</name>
+                                <description>Interrupt Source: Timer overflow; Interrupt Flag: TAxCTL TAIFG; Interrupt Priority: Lowest</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>TIMER_A1</name>
+        <version>356.0</version>
+        <description>TIMER_A1</description>
+        <baseAddress>0x40000400</baseAddress>
+        <interrupt>
+            <name>TA1_0_IRQ</name>
+            <description>TA1_0 Interrupt</description>
+            <value>10</value>
+        </interrupt>
+        <interrupt>
+            <name>TA1_N_IRQ</name>
+            <description>TA1_N Interrupt</description>
+            <value>11</value>
+        </interrupt>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x30</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>TAxCTL</name>
+                  <displayName>CTL</displayName>
+                  <description>TimerAx Control Register</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>TAIFG</name>
+                        <description>TimerA interrupt flag</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>TAIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TAIE</name>
+                        <description>TimerA interrupt enable</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>TAIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TACLR</name>
+                        <description>TimerA clear</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MC</name>
+                        <description>Mode control</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>MC_0</name>
+                                <description>Stop mode: Timer is halted</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>MC_1</name>
+                                <description>Up mode: Timer counts up to TAxCCR0</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>MC_2</name>
+                                <description>Continuous mode: Timer counts up to 0FFFFh</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>MC_3</name>
+                                <description>Up/down mode: Timer counts up to TAxCCR0 then down to 0000h</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ID</name>
+                        <description>Input divider</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ID_0</name>
+                                <description>/1</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ID_1</name>
+                                <description>/2</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ID_2</name>
+                                <description>/4</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ID_3</name>
+                                <description>/8</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TASSEL</name>
+                        <description>TimerA clock source select</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>TASSEL_0</name>
+                                <description>TAxCLK</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TASSEL_1</name>
+                                <description>ACLK</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TASSEL_2</name>
+                                <description>SMCLK</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TASSEL_3</name>
+                                <description>INCLK</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <dim>5</dim>
+                  <dimIncrement>2</dimIncrement>
+                  <dimIndex>0,1,2,3,4</dimIndex>
+                  <name>TAxCCTL[%s]</name>
+                  <displayName>CCTL[%s]</displayName>
+                  <description>Timer_A Capture/Compare Control Register</description>
+                  <addressOffset>0x2</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000fff7</resetMask>
+                  <fields>
+                    <field>
+                        <name>CCIFG</name>
+                        <description>Capture/compare interrupt flag</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CCIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CCIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>COV</name>
+                        <description>Capture overflow</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>COV_0</name>
+                                <description>No capture overflow occurred</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>COV_1</name>
+                                <description>Capture overflow occurred</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUT</name>
+                        <description>Output</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>OUT_0</name>
+                                <description>Output low</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUT_1</name>
+                                <description>Output high</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CCI</name>
+                        <description>Capture/compare input</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CCIE</name>
+                        <description>Capture/compare interrupt enable</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CCIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CCIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTMOD</name>
+                        <description>Output mode</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>OUTMOD_0</name>
+                                <description>OUT bit value</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUTMOD_1</name>
+                                <description>Set</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUTMOD_2</name>
+                                <description>Toggle/reset</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUTMOD_3</name>
+                                <description>Set/reset</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUTMOD_4</name>
+                                <description>Toggle</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUTMOD_5</name>
+                                <description>Reset</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUTMOD_6</name>
+                                <description>Toggle/set</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUTMOD_7</name>
+                                <description>Reset/set</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CAP</name>
+                        <description>Capture mode</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CAP_0</name>
+                                <description>Compare mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAP_1</name>
+                                <description>Capture mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SCCI</name>
+                        <description>Synchronized capture/compare input</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCS</name>
+                        <description>Synchronize capture source</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SCS_0</name>
+                                <description>Asynchronous capture</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SCS_1</name>
+                                <description>Synchronous capture</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CCIS</name>
+                        <description>Capture/compare input select</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CCIS_0</name>
+                                <description>CCIxA</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CCIS_1</name>
+                                <description>CCIxB</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CCIS_2</name>
+                                <description>GND</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CCIS_3</name>
+                                <description>VCC</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CM</name>
+                        <description>Capture mode</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CM_0</name>
+                                <description>No capture</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CM_1</name>
+                                <description>Capture on rising edge</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CM_2</name>
+                                <description>Capture on falling edge</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CM_3</name>
+                                <description>Capture on both rising and falling edges</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>TAxR</name>
+                  <displayName>R</displayName>
+                  <description>TimerA register</description>
+                  <addressOffset>0x10</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+            </register>
+            <register>
+                  <dim>5</dim>
+                  <dimIncrement>2</dimIncrement>
+                  <dimIndex>0,1,2,3,4</dimIndex>
+                  <name>TAxCCR[%s]</name>
+                  <displayName>CCR[%s]</displayName>
+                  <description>Timer_A Capture/Compare  Register</description>
+                  <addressOffset>0x12</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>TAxR</name>
+                        <description>TimerA register</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>TAxEX0</name>
+                  <displayName>EX0</displayName>
+                  <description>TimerAx Expansion 0 Register</description>
+                  <addressOffset>0x20</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>TAIDEX</name>
+                        <description>Input divider expansion</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>TAIDEX_0</name>
+                                <description>Divide by 1</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIDEX_1</name>
+                                <description>Divide by 2</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIDEX_2</name>
+                                <description>Divide by 3</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIDEX_3</name>
+                                <description>Divide by 4</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIDEX_4</name>
+                                <description>Divide by 5</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIDEX_5</name>
+                                <description>Divide by 6</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIDEX_6</name>
+                                <description>Divide by 7</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIDEX_7</name>
+                                <description>Divide by 8</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>TAxIV</name>
+                  <displayName>IV</displayName>
+                  <description>TimerAx Interrupt Vector Register</description>
+                  <addressOffset>0x2E</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>TAIV</name>
+                        <description>TimerA interrupt vector value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>TAIV_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>TAIV_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIV_2</name>
+                                <description>Interrupt Source: Capture/compare 1; Interrupt Flag: TAxCCR1 CCIFG; Interrupt Priority: Highest</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIV_4</name>
+                                <description>Interrupt Source: Capture/compare 2; Interrupt Flag: TAxCCR2 CCIFG</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIV_6</name>
+                                <description>Interrupt Source: Capture/compare 3; Interrupt Flag: TAxCCR3 CCIFG</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIV_8</name>
+                                <description>Interrupt Source: Capture/compare 4; Interrupt Flag: TAxCCR4 CCIFG</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIV_10</name>
+                                <description>Interrupt Source: Capture/compare 5; Interrupt Flag: TAxCCR5 CCIFG</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIV_12</name>
+                                <description>Interrupt Source: Capture/compare 6; Interrupt Flag: TAxCCR6 CCIFG</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIV_14</name>
+                                <description>Interrupt Source: Timer overflow; Interrupt Flag: TAxCTL TAIFG; Interrupt Priority: Lowest</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>TIMER_A2</name>
+        <version>356.0</version>
+        <description>TIMER_A2</description>
+        <baseAddress>0x40000800</baseAddress>
+        <interrupt>
+            <name>TA2_0_IRQ</name>
+            <description>TA2_0 Interrupt</description>
+            <value>12</value>
+        </interrupt>
+        <interrupt>
+            <name>TA2_N_IRQ</name>
+            <description>TA2_N Interrupt</description>
+            <value>13</value>
+        </interrupt>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x30</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>TAxCTL</name>
+                  <displayName>CTL</displayName>
+                  <description>TimerAx Control Register</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>TAIFG</name>
+                        <description>TimerA interrupt flag</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>TAIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TAIE</name>
+                        <description>TimerA interrupt enable</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>TAIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TACLR</name>
+                        <description>TimerA clear</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MC</name>
+                        <description>Mode control</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>MC_0</name>
+                                <description>Stop mode: Timer is halted</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>MC_1</name>
+                                <description>Up mode: Timer counts up to TAxCCR0</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>MC_2</name>
+                                <description>Continuous mode: Timer counts up to 0FFFFh</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>MC_3</name>
+                                <description>Up/down mode: Timer counts up to TAxCCR0 then down to 0000h</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ID</name>
+                        <description>Input divider</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ID_0</name>
+                                <description>/1</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ID_1</name>
+                                <description>/2</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ID_2</name>
+                                <description>/4</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ID_3</name>
+                                <description>/8</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TASSEL</name>
+                        <description>TimerA clock source select</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>TASSEL_0</name>
+                                <description>TAxCLK</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TASSEL_1</name>
+                                <description>ACLK</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TASSEL_2</name>
+                                <description>SMCLK</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TASSEL_3</name>
+                                <description>INCLK</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <dim>5</dim>
+                  <dimIncrement>2</dimIncrement>
+                  <dimIndex>0,1,2,3,4</dimIndex>
+                  <name>TAxCCTL[%s]</name>
+                  <displayName>CCTL[%s]</displayName>
+                  <description>Timer_A Capture/Compare Control Register</description>
+                  <addressOffset>0x2</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000fff7</resetMask>
+                  <fields>
+                    <field>
+                        <name>CCIFG</name>
+                        <description>Capture/compare interrupt flag</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CCIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CCIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>COV</name>
+                        <description>Capture overflow</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>COV_0</name>
+                                <description>No capture overflow occurred</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>COV_1</name>
+                                <description>Capture overflow occurred</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUT</name>
+                        <description>Output</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>OUT_0</name>
+                                <description>Output low</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUT_1</name>
+                                <description>Output high</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CCI</name>
+                        <description>Capture/compare input</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CCIE</name>
+                        <description>Capture/compare interrupt enable</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CCIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CCIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTMOD</name>
+                        <description>Output mode</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>OUTMOD_0</name>
+                                <description>OUT bit value</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUTMOD_1</name>
+                                <description>Set</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUTMOD_2</name>
+                                <description>Toggle/reset</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUTMOD_3</name>
+                                <description>Set/reset</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUTMOD_4</name>
+                                <description>Toggle</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUTMOD_5</name>
+                                <description>Reset</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUTMOD_6</name>
+                                <description>Toggle/set</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUTMOD_7</name>
+                                <description>Reset/set</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CAP</name>
+                        <description>Capture mode</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CAP_0</name>
+                                <description>Compare mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAP_1</name>
+                                <description>Capture mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SCCI</name>
+                        <description>Synchronized capture/compare input</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCS</name>
+                        <description>Synchronize capture source</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SCS_0</name>
+                                <description>Asynchronous capture</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SCS_1</name>
+                                <description>Synchronous capture</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CCIS</name>
+                        <description>Capture/compare input select</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CCIS_0</name>
+                                <description>CCIxA</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CCIS_1</name>
+                                <description>CCIxB</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CCIS_2</name>
+                                <description>GND</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CCIS_3</name>
+                                <description>VCC</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CM</name>
+                        <description>Capture mode</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CM_0</name>
+                                <description>No capture</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CM_1</name>
+                                <description>Capture on rising edge</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CM_2</name>
+                                <description>Capture on falling edge</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CM_3</name>
+                                <description>Capture on both rising and falling edges</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>TAxR</name>
+                  <displayName>R</displayName>
+                  <description>TimerA register</description>
+                  <addressOffset>0x10</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+            </register>
+            <register>
+                  <dim>5</dim>
+                  <dimIncrement>2</dimIncrement>
+                  <dimIndex>0,1,2,3,4</dimIndex>
+                  <name>TAxCCR[%s]</name>
+                  <displayName>CCR[%s]</displayName>
+                  <description>Timer_A Capture/Compare  Register</description>
+                  <addressOffset>0x12</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>TAxR</name>
+                        <description>TimerA register</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>TAxEX0</name>
+                  <displayName>EX0</displayName>
+                  <description>TimerAx Expansion 0 Register</description>
+                  <addressOffset>0x20</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>TAIDEX</name>
+                        <description>Input divider expansion</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>TAIDEX_0</name>
+                                <description>Divide by 1</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIDEX_1</name>
+                                <description>Divide by 2</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIDEX_2</name>
+                                <description>Divide by 3</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIDEX_3</name>
+                                <description>Divide by 4</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIDEX_4</name>
+                                <description>Divide by 5</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIDEX_5</name>
+                                <description>Divide by 6</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIDEX_6</name>
+                                <description>Divide by 7</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIDEX_7</name>
+                                <description>Divide by 8</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>TAxIV</name>
+                  <displayName>IV</displayName>
+                  <description>TimerAx Interrupt Vector Register</description>
+                  <addressOffset>0x2E</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>TAIV</name>
+                        <description>TimerA interrupt vector value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>TAIV_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>TAIV_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIV_2</name>
+                                <description>Interrupt Source: Capture/compare 1; Interrupt Flag: TAxCCR1 CCIFG; Interrupt Priority: Highest</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIV_4</name>
+                                <description>Interrupt Source: Capture/compare 2; Interrupt Flag: TAxCCR2 CCIFG</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIV_6</name>
+                                <description>Interrupt Source: Capture/compare 3; Interrupt Flag: TAxCCR3 CCIFG</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIV_8</name>
+                                <description>Interrupt Source: Capture/compare 4; Interrupt Flag: TAxCCR4 CCIFG</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIV_10</name>
+                                <description>Interrupt Source: Capture/compare 5; Interrupt Flag: TAxCCR5 CCIFG</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIV_12</name>
+                                <description>Interrupt Source: Capture/compare 6; Interrupt Flag: TAxCCR6 CCIFG</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIV_14</name>
+                                <description>Interrupt Source: Timer overflow; Interrupt Flag: TAxCTL TAIFG; Interrupt Priority: Lowest</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>TIMER_A3</name>
+        <version>356.0</version>
+        <description>TIMER_A3</description>
+        <baseAddress>0x40000C00</baseAddress>
+        <interrupt>
+            <name>TA3_0_IRQ</name>
+            <description>TA3_0 Interrupt</description>
+            <value>14</value>
+        </interrupt>
+        <interrupt>
+            <name>TA3_N_IRQ</name>
+            <description>TA3_N Interrupt</description>
+            <value>15</value>
+        </interrupt>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x30</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>TAxCTL</name>
+                  <displayName>CTL</displayName>
+                  <description>TimerAx Control Register</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>TAIFG</name>
+                        <description>TimerA interrupt flag</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>TAIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TAIE</name>
+                        <description>TimerA interrupt enable</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>TAIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TACLR</name>
+                        <description>TimerA clear</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MC</name>
+                        <description>Mode control</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>MC_0</name>
+                                <description>Stop mode: Timer is halted</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>MC_1</name>
+                                <description>Up mode: Timer counts up to TAxCCR0</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>MC_2</name>
+                                <description>Continuous mode: Timer counts up to 0FFFFh</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>MC_3</name>
+                                <description>Up/down mode: Timer counts up to TAxCCR0 then down to 0000h</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ID</name>
+                        <description>Input divider</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ID_0</name>
+                                <description>/1</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ID_1</name>
+                                <description>/2</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ID_2</name>
+                                <description>/4</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ID_3</name>
+                                <description>/8</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TASSEL</name>
+                        <description>TimerA clock source select</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>TASSEL_0</name>
+                                <description>TAxCLK</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TASSEL_1</name>
+                                <description>ACLK</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TASSEL_2</name>
+                                <description>SMCLK</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TASSEL_3</name>
+                                <description>INCLK</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <dim>5</dim>
+                  <dimIncrement>2</dimIncrement>
+                  <dimIndex>0,1,2,3,4</dimIndex>
+                  <name>TAxCCTL[%s]</name>
+                  <displayName>CCTL[%s]</displayName>
+                  <description>Timer_A Capture/Compare Control Register</description>
+                  <addressOffset>0x2</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000fff7</resetMask>
+                  <fields>
+                    <field>
+                        <name>CCIFG</name>
+                        <description>Capture/compare interrupt flag</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CCIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CCIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>COV</name>
+                        <description>Capture overflow</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>COV_0</name>
+                                <description>No capture overflow occurred</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>COV_1</name>
+                                <description>Capture overflow occurred</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUT</name>
+                        <description>Output</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>OUT_0</name>
+                                <description>Output low</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUT_1</name>
+                                <description>Output high</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CCI</name>
+                        <description>Capture/compare input</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CCIE</name>
+                        <description>Capture/compare interrupt enable</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CCIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CCIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTMOD</name>
+                        <description>Output mode</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>OUTMOD_0</name>
+                                <description>OUT bit value</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUTMOD_1</name>
+                                <description>Set</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUTMOD_2</name>
+                                <description>Toggle/reset</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUTMOD_3</name>
+                                <description>Set/reset</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUTMOD_4</name>
+                                <description>Toggle</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUTMOD_5</name>
+                                <description>Reset</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUTMOD_6</name>
+                                <description>Toggle/set</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>OUTMOD_7</name>
+                                <description>Reset/set</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CAP</name>
+                        <description>Capture mode</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CAP_0</name>
+                                <description>Compare mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAP_1</name>
+                                <description>Capture mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SCCI</name>
+                        <description>Synchronized capture/compare input</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCS</name>
+                        <description>Synchronize capture source</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SCS_0</name>
+                                <description>Asynchronous capture</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SCS_1</name>
+                                <description>Synchronous capture</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CCIS</name>
+                        <description>Capture/compare input select</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CCIS_0</name>
+                                <description>CCIxA</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CCIS_1</name>
+                                <description>CCIxB</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CCIS_2</name>
+                                <description>GND</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CCIS_3</name>
+                                <description>VCC</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CM</name>
+                        <description>Capture mode</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CM_0</name>
+                                <description>No capture</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CM_1</name>
+                                <description>Capture on rising edge</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CM_2</name>
+                                <description>Capture on falling edge</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CM_3</name>
+                                <description>Capture on both rising and falling edges</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>TAxR</name>
+                  <displayName>R</displayName>
+                  <description>TimerA register</description>
+                  <addressOffset>0x10</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+            </register>
+            <register>
+                  <dim>5</dim>
+                  <dimIncrement>2</dimIncrement>
+                  <dimIndex>0,1,2,3,4</dimIndex>
+                  <name>TAxCCR[%s]</name>
+                  <displayName>CCR[%s]</displayName>
+                  <description>Timer_A Capture/Compare  Register</description>
+                  <addressOffset>0x12</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>TAxR</name>
+                        <description>TimerA register</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>TAxEX0</name>
+                  <displayName>EX0</displayName>
+                  <description>TimerAx Expansion 0 Register</description>
+                  <addressOffset>0x20</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>TAIDEX</name>
+                        <description>Input divider expansion</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>TAIDEX_0</name>
+                                <description>Divide by 1</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIDEX_1</name>
+                                <description>Divide by 2</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIDEX_2</name>
+                                <description>Divide by 3</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIDEX_3</name>
+                                <description>Divide by 4</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIDEX_4</name>
+                                <description>Divide by 5</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIDEX_5</name>
+                                <description>Divide by 6</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIDEX_6</name>
+                                <description>Divide by 7</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIDEX_7</name>
+                                <description>Divide by 8</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>TAxIV</name>
+                  <displayName>IV</displayName>
+                  <description>TimerAx Interrupt Vector Register</description>
+                  <addressOffset>0x2E</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>TAIV</name>
+                        <description>TimerA interrupt vector value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>TAIV_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>TAIV_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIV_2</name>
+                                <description>Interrupt Source: Capture/compare 1; Interrupt Flag: TAxCCR1 CCIFG; Interrupt Priority: Highest</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIV_4</name>
+                                <description>Interrupt Source: Capture/compare 2; Interrupt Flag: TAxCCR2 CCIFG</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIV_6</name>
+                                <description>Interrupt Source: Capture/compare 3; Interrupt Flag: TAxCCR3 CCIFG</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIV_8</name>
+                                <description>Interrupt Source: Capture/compare 4; Interrupt Flag: TAxCCR4 CCIFG</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIV_10</name>
+                                <description>Interrupt Source: Capture/compare 5; Interrupt Flag: TAxCCR5 CCIFG</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIV_12</name>
+                                <description>Interrupt Source: Capture/compare 6; Interrupt Flag: TAxCCR6 CCIFG</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TAIV_14</name>
+                                <description>Interrupt Source: Timer overflow; Interrupt Flag: TAxCTL TAIFG; Interrupt Priority: Lowest</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>EUSCI_A0</name>
+        <version>356.0</version>
+        <description>EUSCI_A0</description>
+        <baseAddress>0x40001000</baseAddress>
+        <interrupt>
+            <name>EUSCIA0_IRQ</name>
+            <description>EUSCIA0 Interrupt</description>
+            <value>16</value>
+        </interrupt>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x20</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>UCAxCTLW0</name>
+                  <displayName>CTLW0</displayName>
+                  <description>eUSCI_Ax Control Word Register 0</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000001</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCSWRST</name>
+                        <description>Software reset enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSWRST_0</name>
+                                <description>Disabled. eUSCI_A reset released for operation</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSWRST_1</name>
+                                <description>Enabled. eUSCI_A logic held in reset state</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXBRK</name>
+                        <description>Transmit break</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXBRK_0</name>
+                                <description>Next frame transmitted is not a break</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXBRK_1</name>
+                                <description>Next frame transmitted is a break or a break/synch</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXADDR</name>
+                        <description>Transmit address</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXADDR_0</name>
+                                <description>Next frame transmitted is data</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXADDR_1</name>
+                                <description>Next frame transmitted is an address</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCDORM</name>
+                        <description>Dormant</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCDORM_0</name>
+                                <description>Not dormant. All received characters set UCRXIFG.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCDORM_1</name>
+                                <description>Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBRKIE</name>
+                        <description>Receive break character interrupt enable</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCBRKIE_0</name>
+                                <description>Received break characters do not set UCRXIFG</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBRKIE_1</name>
+                                <description>Received break characters set UCRXIFG</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCRXEIE</name>
+                        <description>Receive erroneous-character interrupt enable</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXEIE_0</name>
+                                <description>Erroneous characters rejected and UCRXIFG is not set</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXEIE_1</name>
+                                <description>Erroneous characters received set UCRXIFG</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSSEL</name>
+                        <description>eUSCI_A clock source select</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSSEL_0</name>
+                                <description>UCLK</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSSEL_1</name>
+                                <description>ACLK</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSSEL_2</name>
+                                <description>SMCLK</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSYNC</name>
+                        <description>Synchronous mode enable</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSYNC_0</name>
+                                <description>Asynchronous mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSYNC_1</name>
+                                <description>Synchronous mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCMODE</name>
+                        <description>eUSCI_A mode</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCMODE_0</name>
+                                <description>UART mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMODE_1</name>
+                                <description>Idle-line multiprocessor mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMODE_2</name>
+                                <description>Address-bit multiprocessor mode</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMODE_3</name>
+                                <description>UART mode with automatic baud-rate detection</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSPB</name>
+                        <description>Stop bit select</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSPB_0</name>
+                                <description>One stop bit</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSPB_1</name>
+                                <description>Two stop bits</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UC7BIT</name>
+                        <description>Character length</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UC7BIT_0</name>
+                                <description>8-bit data</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UC7BIT_1</name>
+                                <description>7-bit data</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCMSB</name>
+                        <description>MSB first select</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCMSB_0</name>
+                                <description>LSB first</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMSB_1</name>
+                                <description>MSB first</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCPAR</name>
+                        <description>Parity select</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCPAR_0</name>
+                                <description>Odd parity</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCPAR_1</name>
+                                <description>Even parity</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCPEN</name>
+                        <description>Parity enable</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCPEN_0</name>
+                                <description>Parity disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCPEN_1</name>
+                                <description>Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxCTLW1</name>
+                  <displayName>CTLW1</displayName>
+                  <description>eUSCI_Ax Control Word Register 1</description>
+                  <addressOffset>0x2</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000003</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCGLIT</name>
+                        <description>Deglitch time</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCGLIT_0</name>
+                                <description>Approximately 2 ns (equivalent of 1 delay element)</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGLIT_1</name>
+                                <description>Approximately 50 ns</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGLIT_2</name>
+                                <description>Approximately 100 ns</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGLIT_3</name>
+                                <description>Approximately 200 ns</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxBRW</name>
+                  <displayName>BRW</displayName>
+                  <description>eUSCI_Ax Baud Rate Control Word Register</description>
+                  <addressOffset>0x6</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x000000ff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCBR</name>
+                        <description>Clock prescaler setting of the Baud rate generator</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxMCTLW</name>
+                  <displayName>MCTLW</displayName>
+                  <description>eUSCI_Ax Modulation Control Word Register</description>
+                  <addressOffset>0x8</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCOS16</name>
+                        <description>Oversampling mode enabled</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCOS16_0</name>
+                                <description>Disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCOS16_1</name>
+                                <description>Enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBRF</name>
+                        <description>First modulation stage select</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UCBRS</name>
+                        <description>Second modulation stage select</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxSTATW</name>
+                  <displayName>STATW</displayName>
+                  <description>eUSCI_Ax Status Register</description>
+                  <addressOffset>0xA</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCBUSY</name>
+                        <description>eUSCI_A busy</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>UCBUSY_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>UCBUSY_0</name>
+                                <description>eUSCI_A inactive</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBUSY_1</name>
+                                <description>eUSCI_A transmitting or receiving</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCADDR_UCIDLE</name>
+                        <description>Address received / Idle line detected</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UCRXERR</name>
+                        <description>Receive error flag</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXERR_0</name>
+                                <description>No receive errors detected</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXERR_1</name>
+                                <description>Receive error detected</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBRK</name>
+                        <description>Break detect flag</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCBRK_0</name>
+                                <description>No break condition</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBRK_1</name>
+                                <description>Break condition occurred</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCPE</name>
+                        <description>Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read.</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCPE_0</name>
+                                <description>No error</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCPE_1</name>
+                                <description>Character received with parity error</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCOE</name>
+                        <description>Overrun error flag</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCOE_0</name>
+                                <description>No error</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCOE_1</name>
+                                <description>Overrun error occurred</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCFE</name>
+                        <description>Framing error flag</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCFE_0</name>
+                                <description>No error</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCFE_1</name>
+                                <description>Character received with low stop bit</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCLISTEN</name>
+                        <description>Listen enable</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCLISTEN_0</name>
+                                <description>Disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCLISTEN_1</name>
+                                <description>Enabled. UCAxTXD is internally fed back to the receiver</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxRXBUF</name>
+                  <displayName>RXBUF</displayName>
+                  <description>eUSCI_Ax Receive Buffer Register</description>
+                  <addressOffset>0xC</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCRXBUF</name>
+                        <description>Receive data buffer</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxTXBUF</name>
+                  <displayName>TXBUF</displayName>
+                  <description>eUSCI_Ax Transmit Buffer Register</description>
+                  <addressOffset>0xE</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCTXBUF</name>
+                        <description>Transmit data buffer</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxABCTL</name>
+                  <displayName>ABCTL</displayName>
+                  <description>eUSCI_Ax Auto Baud Rate Control Register</description>
+                  <addressOffset>0x10</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCABDEN</name>
+                        <description>Automatic baud-rate detect enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCABDEN_0</name>
+                                <description>Baud-rate detection disabled. Length of break and synch field is not measured.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCABDEN_1</name>
+                                <description>Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBTOE</name>
+                        <description>Break time out error</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCBTOE_0</name>
+                                <description>No error</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBTOE_1</name>
+                                <description>Length of break field exceeded 22 bit times</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTOE</name>
+                        <description>Synch field time out error</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTOE_0</name>
+                                <description>No error</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTOE_1</name>
+                                <description>Length of synch field exceeded measurable time</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCDELIM</name>
+                        <description>Break/synch delimiter length</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCDELIM_0</name>
+                                <description>1 bit time</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCDELIM_1</name>
+                                <description>2 bit times</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCDELIM_2</name>
+                                <description>3 bit times</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCDELIM_3</name>
+                                <description>4 bit times</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxIRCTL</name>
+                  <displayName>IRCTL</displayName>
+                  <description>eUSCI_Ax IrDA Control Word Register</description>
+                  <addressOffset>0x12</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCIREN</name>
+                        <description>IrDA encoder/decoder enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCIREN_0</name>
+                                <description>IrDA encoder/decoder disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIREN_1</name>
+                                <description>IrDA encoder/decoder enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCIRTXCLK</name>
+                        <description>IrDA transmit pulse clock select</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCIRTXCLK_0</name>
+                                <description>BRCLK</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIRTXCLK_1</name>
+                                <description>BITCLK16 when UCOS16 = 1. Otherwise, BRCLK.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCIRTXPL</name>
+                        <description>Transmit pulse length</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x6</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UCIRRXFE</name>
+                        <description>IrDA receive filter enabled</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCIRRXFE_0</name>
+                                <description>Receive filter disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIRRXFE_1</name>
+                                <description>Receive filter enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCIRRXPL</name>
+                        <description>IrDA receive input UCAxRXD polarity</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCIRRXPL_0</name>
+                                <description>IrDA transceiver delivers a high pulse when a light pulse is seen</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIRRXPL_1</name>
+                                <description>IrDA transceiver delivers a low pulse when a light pulse is seen</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCIRRXFL</name>
+                        <description>Receive filter length</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxIE</name>
+                  <displayName>IE</displayName>
+                  <description>eUSCI_Ax Interrupt Enable Register</description>
+                  <addressOffset>0x1A</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCRXIE</name>
+                        <description>Receive interrupt enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIE</name>
+                        <description>Transmit interrupt enable</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTTIE</name>
+                        <description>Start bit interrupt enable</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTTIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTTIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXCPTIE</name>
+                        <description>Transmit complete interrupt enable</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXCPTIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXCPTIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxIFG</name>
+                  <displayName>IFG</displayName>
+                  <description>eUSCI_Ax Interrupt Flag Register</description>
+                  <addressOffset>0x1C</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000002</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCRXIFG</name>
+                        <description>Receive interrupt flag</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIFG</name>
+                        <description>Transmit interrupt flag</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTTIFG</name>
+                        <description>Start bit interrupt flag</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTTIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTTIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXCPTIFG</name>
+                        <description>Transmit ready interrupt enable</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXCPTIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXCPTIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxIV</name>
+                  <displayName>IV</displayName>
+                  <description>eUSCI_Ax Interrupt Vector Register</description>
+                  <addressOffset>0x1E</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCIV</name>
+                        <description>eUSCI_A interrupt vector value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>UCIV_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>UCIV_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_2</name>
+                                <description>Interrupt Source: Receive buffer full; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_4</name>
+                                <description>Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_6</name>
+                                <description>Interrupt Source: Start bit received; Interrupt Flag: UCSTTIFG</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_8</name>
+                                <description>Interrupt Source: Transmit complete; Interrupt Flag: UCTXCPTIFG; Interrupt Priority: Lowest</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>EUSCI_A1</name>
+        <version>356.0</version>
+        <description>EUSCI_A1</description>
+        <baseAddress>0x40001400</baseAddress>
+        <interrupt>
+            <name>EUSCIA1_IRQ</name>
+            <description>EUSCIA1 Interrupt</description>
+            <value>17</value>
+        </interrupt>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x20</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>UCAxCTLW0</name>
+                  <displayName>CTLW0</displayName>
+                  <description>eUSCI_Ax Control Word Register 0</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000001</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCSWRST</name>
+                        <description>Software reset enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSWRST_0</name>
+                                <description>Disabled. eUSCI_A reset released for operation</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSWRST_1</name>
+                                <description>Enabled. eUSCI_A logic held in reset state</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXBRK</name>
+                        <description>Transmit break</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXBRK_0</name>
+                                <description>Next frame transmitted is not a break</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXBRK_1</name>
+                                <description>Next frame transmitted is a break or a break/synch</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXADDR</name>
+                        <description>Transmit address</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXADDR_0</name>
+                                <description>Next frame transmitted is data</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXADDR_1</name>
+                                <description>Next frame transmitted is an address</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCDORM</name>
+                        <description>Dormant</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCDORM_0</name>
+                                <description>Not dormant. All received characters set UCRXIFG.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCDORM_1</name>
+                                <description>Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBRKIE</name>
+                        <description>Receive break character interrupt enable</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCBRKIE_0</name>
+                                <description>Received break characters do not set UCRXIFG</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBRKIE_1</name>
+                                <description>Received break characters set UCRXIFG</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCRXEIE</name>
+                        <description>Receive erroneous-character interrupt enable</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXEIE_0</name>
+                                <description>Erroneous characters rejected and UCRXIFG is not set</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXEIE_1</name>
+                                <description>Erroneous characters received set UCRXIFG</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSSEL</name>
+                        <description>eUSCI_A clock source select</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSSEL_0</name>
+                                <description>UCLK</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSSEL_1</name>
+                                <description>ACLK</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSSEL_2</name>
+                                <description>SMCLK</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSYNC</name>
+                        <description>Synchronous mode enable</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSYNC_0</name>
+                                <description>Asynchronous mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSYNC_1</name>
+                                <description>Synchronous mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCMODE</name>
+                        <description>eUSCI_A mode</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCMODE_0</name>
+                                <description>UART mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMODE_1</name>
+                                <description>Idle-line multiprocessor mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMODE_2</name>
+                                <description>Address-bit multiprocessor mode</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMODE_3</name>
+                                <description>UART mode with automatic baud-rate detection</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSPB</name>
+                        <description>Stop bit select</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSPB_0</name>
+                                <description>One stop bit</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSPB_1</name>
+                                <description>Two stop bits</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UC7BIT</name>
+                        <description>Character length</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UC7BIT_0</name>
+                                <description>8-bit data</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UC7BIT_1</name>
+                                <description>7-bit data</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCMSB</name>
+                        <description>MSB first select</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCMSB_0</name>
+                                <description>LSB first</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMSB_1</name>
+                                <description>MSB first</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCPAR</name>
+                        <description>Parity select</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCPAR_0</name>
+                                <description>Odd parity</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCPAR_1</name>
+                                <description>Even parity</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCPEN</name>
+                        <description>Parity enable</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCPEN_0</name>
+                                <description>Parity disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCPEN_1</name>
+                                <description>Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxCTLW1</name>
+                  <displayName>CTLW1</displayName>
+                  <description>eUSCI_Ax Control Word Register 1</description>
+                  <addressOffset>0x2</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000003</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCGLIT</name>
+                        <description>Deglitch time</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCGLIT_0</name>
+                                <description>Approximately 2 ns (equivalent of 1 delay element)</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGLIT_1</name>
+                                <description>Approximately 50 ns</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGLIT_2</name>
+                                <description>Approximately 100 ns</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGLIT_3</name>
+                                <description>Approximately 200 ns</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxBRW</name>
+                  <displayName>BRW</displayName>
+                  <description>eUSCI_Ax Baud Rate Control Word Register</description>
+                  <addressOffset>0x6</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x000000ff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCBR</name>
+                        <description>Clock prescaler setting of the Baud rate generator</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxMCTLW</name>
+                  <displayName>MCTLW</displayName>
+                  <description>eUSCI_Ax Modulation Control Word Register</description>
+                  <addressOffset>0x8</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCOS16</name>
+                        <description>Oversampling mode enabled</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCOS16_0</name>
+                                <description>Disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCOS16_1</name>
+                                <description>Enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBRF</name>
+                        <description>First modulation stage select</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UCBRS</name>
+                        <description>Second modulation stage select</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxSTATW</name>
+                  <displayName>STATW</displayName>
+                  <description>eUSCI_Ax Status Register</description>
+                  <addressOffset>0xA</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCBUSY</name>
+                        <description>eUSCI_A busy</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>UCBUSY_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>UCBUSY_0</name>
+                                <description>eUSCI_A inactive</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBUSY_1</name>
+                                <description>eUSCI_A transmitting or receiving</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCADDR_UCIDLE</name>
+                        <description>Address received / Idle line detected</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UCRXERR</name>
+                        <description>Receive error flag</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXERR_0</name>
+                                <description>No receive errors detected</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXERR_1</name>
+                                <description>Receive error detected</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBRK</name>
+                        <description>Break detect flag</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCBRK_0</name>
+                                <description>No break condition</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBRK_1</name>
+                                <description>Break condition occurred</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCPE</name>
+                        <description>Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read.</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCPE_0</name>
+                                <description>No error</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCPE_1</name>
+                                <description>Character received with parity error</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCOE</name>
+                        <description>Overrun error flag</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCOE_0</name>
+                                <description>No error</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCOE_1</name>
+                                <description>Overrun error occurred</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCFE</name>
+                        <description>Framing error flag</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCFE_0</name>
+                                <description>No error</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCFE_1</name>
+                                <description>Character received with low stop bit</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCLISTEN</name>
+                        <description>Listen enable</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCLISTEN_0</name>
+                                <description>Disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCLISTEN_1</name>
+                                <description>Enabled. UCAxTXD is internally fed back to the receiver</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxRXBUF</name>
+                  <displayName>RXBUF</displayName>
+                  <description>eUSCI_Ax Receive Buffer Register</description>
+                  <addressOffset>0xC</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCRXBUF</name>
+                        <description>Receive data buffer</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxTXBUF</name>
+                  <displayName>TXBUF</displayName>
+                  <description>eUSCI_Ax Transmit Buffer Register</description>
+                  <addressOffset>0xE</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCTXBUF</name>
+                        <description>Transmit data buffer</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxABCTL</name>
+                  <displayName>ABCTL</displayName>
+                  <description>eUSCI_Ax Auto Baud Rate Control Register</description>
+                  <addressOffset>0x10</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCABDEN</name>
+                        <description>Automatic baud-rate detect enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCABDEN_0</name>
+                                <description>Baud-rate detection disabled. Length of break and synch field is not measured.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCABDEN_1</name>
+                                <description>Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBTOE</name>
+                        <description>Break time out error</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCBTOE_0</name>
+                                <description>No error</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBTOE_1</name>
+                                <description>Length of break field exceeded 22 bit times</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTOE</name>
+                        <description>Synch field time out error</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTOE_0</name>
+                                <description>No error</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTOE_1</name>
+                                <description>Length of synch field exceeded measurable time</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCDELIM</name>
+                        <description>Break/synch delimiter length</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCDELIM_0</name>
+                                <description>1 bit time</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCDELIM_1</name>
+                                <description>2 bit times</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCDELIM_2</name>
+                                <description>3 bit times</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCDELIM_3</name>
+                                <description>4 bit times</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxIRCTL</name>
+                  <displayName>IRCTL</displayName>
+                  <description>eUSCI_Ax IrDA Control Word Register</description>
+                  <addressOffset>0x12</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCIREN</name>
+                        <description>IrDA encoder/decoder enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCIREN_0</name>
+                                <description>IrDA encoder/decoder disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIREN_1</name>
+                                <description>IrDA encoder/decoder enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCIRTXCLK</name>
+                        <description>IrDA transmit pulse clock select</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCIRTXCLK_0</name>
+                                <description>BRCLK</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIRTXCLK_1</name>
+                                <description>BITCLK16 when UCOS16 = 1. Otherwise, BRCLK.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCIRTXPL</name>
+                        <description>Transmit pulse length</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x6</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UCIRRXFE</name>
+                        <description>IrDA receive filter enabled</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCIRRXFE_0</name>
+                                <description>Receive filter disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIRRXFE_1</name>
+                                <description>Receive filter enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCIRRXPL</name>
+                        <description>IrDA receive input UCAxRXD polarity</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCIRRXPL_0</name>
+                                <description>IrDA transceiver delivers a high pulse when a light pulse is seen</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIRRXPL_1</name>
+                                <description>IrDA transceiver delivers a low pulse when a light pulse is seen</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCIRRXFL</name>
+                        <description>Receive filter length</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxIE</name>
+                  <displayName>IE</displayName>
+                  <description>eUSCI_Ax Interrupt Enable Register</description>
+                  <addressOffset>0x1A</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCRXIE</name>
+                        <description>Receive interrupt enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIE</name>
+                        <description>Transmit interrupt enable</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTTIE</name>
+                        <description>Start bit interrupt enable</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTTIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTTIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXCPTIE</name>
+                        <description>Transmit complete interrupt enable</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXCPTIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXCPTIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxIFG</name>
+                  <displayName>IFG</displayName>
+                  <description>eUSCI_Ax Interrupt Flag Register</description>
+                  <addressOffset>0x1C</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000002</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCRXIFG</name>
+                        <description>Receive interrupt flag</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIFG</name>
+                        <description>Transmit interrupt flag</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTTIFG</name>
+                        <description>Start bit interrupt flag</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTTIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTTIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXCPTIFG</name>
+                        <description>Transmit ready interrupt enable</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXCPTIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXCPTIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxIV</name>
+                  <displayName>IV</displayName>
+                  <description>eUSCI_Ax Interrupt Vector Register</description>
+                  <addressOffset>0x1E</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCIV</name>
+                        <description>eUSCI_A interrupt vector value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>UCIV_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>UCIV_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_2</name>
+                                <description>Interrupt Source: Receive buffer full; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_4</name>
+                                <description>Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_6</name>
+                                <description>Interrupt Source: Start bit received; Interrupt Flag: UCSTTIFG</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_8</name>
+                                <description>Interrupt Source: Transmit complete; Interrupt Flag: UCTXCPTIFG; Interrupt Priority: Lowest</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>EUSCI_A2</name>
+        <version>356.0</version>
+        <description>EUSCI_A2</description>
+        <baseAddress>0x40001800</baseAddress>
+        <interrupt>
+            <name>EUSCIA2_IRQ</name>
+            <description>EUSCIA2 Interrupt</description>
+            <value>18</value>
+        </interrupt>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x20</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>UCAxCTLW0</name>
+                  <displayName>CTLW0</displayName>
+                  <description>eUSCI_Ax Control Word Register 0</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000001</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCSWRST</name>
+                        <description>Software reset enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSWRST_0</name>
+                                <description>Disabled. eUSCI_A reset released for operation</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSWRST_1</name>
+                                <description>Enabled. eUSCI_A logic held in reset state</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXBRK</name>
+                        <description>Transmit break</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXBRK_0</name>
+                                <description>Next frame transmitted is not a break</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXBRK_1</name>
+                                <description>Next frame transmitted is a break or a break/synch</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXADDR</name>
+                        <description>Transmit address</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXADDR_0</name>
+                                <description>Next frame transmitted is data</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXADDR_1</name>
+                                <description>Next frame transmitted is an address</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCDORM</name>
+                        <description>Dormant</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCDORM_0</name>
+                                <description>Not dormant. All received characters set UCRXIFG.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCDORM_1</name>
+                                <description>Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBRKIE</name>
+                        <description>Receive break character interrupt enable</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCBRKIE_0</name>
+                                <description>Received break characters do not set UCRXIFG</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBRKIE_1</name>
+                                <description>Received break characters set UCRXIFG</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCRXEIE</name>
+                        <description>Receive erroneous-character interrupt enable</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXEIE_0</name>
+                                <description>Erroneous characters rejected and UCRXIFG is not set</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXEIE_1</name>
+                                <description>Erroneous characters received set UCRXIFG</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSSEL</name>
+                        <description>eUSCI_A clock source select</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSSEL_0</name>
+                                <description>UCLK</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSSEL_1</name>
+                                <description>ACLK</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSSEL_2</name>
+                                <description>SMCLK</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSYNC</name>
+                        <description>Synchronous mode enable</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSYNC_0</name>
+                                <description>Asynchronous mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSYNC_1</name>
+                                <description>Synchronous mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCMODE</name>
+                        <description>eUSCI_A mode</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCMODE_0</name>
+                                <description>UART mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMODE_1</name>
+                                <description>Idle-line multiprocessor mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMODE_2</name>
+                                <description>Address-bit multiprocessor mode</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMODE_3</name>
+                                <description>UART mode with automatic baud-rate detection</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSPB</name>
+                        <description>Stop bit select</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSPB_0</name>
+                                <description>One stop bit</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSPB_1</name>
+                                <description>Two stop bits</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UC7BIT</name>
+                        <description>Character length</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UC7BIT_0</name>
+                                <description>8-bit data</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UC7BIT_1</name>
+                                <description>7-bit data</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCMSB</name>
+                        <description>MSB first select</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCMSB_0</name>
+                                <description>LSB first</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMSB_1</name>
+                                <description>MSB first</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCPAR</name>
+                        <description>Parity select</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCPAR_0</name>
+                                <description>Odd parity</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCPAR_1</name>
+                                <description>Even parity</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCPEN</name>
+                        <description>Parity enable</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCPEN_0</name>
+                                <description>Parity disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCPEN_1</name>
+                                <description>Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxCTLW1</name>
+                  <displayName>CTLW1</displayName>
+                  <description>eUSCI_Ax Control Word Register 1</description>
+                  <addressOffset>0x2</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000003</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCGLIT</name>
+                        <description>Deglitch time</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCGLIT_0</name>
+                                <description>Approximately 2 ns (equivalent of 1 delay element)</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGLIT_1</name>
+                                <description>Approximately 50 ns</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGLIT_2</name>
+                                <description>Approximately 100 ns</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGLIT_3</name>
+                                <description>Approximately 200 ns</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxBRW</name>
+                  <displayName>BRW</displayName>
+                  <description>eUSCI_Ax Baud Rate Control Word Register</description>
+                  <addressOffset>0x6</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x000000ff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCBR</name>
+                        <description>Clock prescaler setting of the Baud rate generator</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxMCTLW</name>
+                  <displayName>MCTLW</displayName>
+                  <description>eUSCI_Ax Modulation Control Word Register</description>
+                  <addressOffset>0x8</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCOS16</name>
+                        <description>Oversampling mode enabled</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCOS16_0</name>
+                                <description>Disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCOS16_1</name>
+                                <description>Enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBRF</name>
+                        <description>First modulation stage select</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UCBRS</name>
+                        <description>Second modulation stage select</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxSTATW</name>
+                  <displayName>STATW</displayName>
+                  <description>eUSCI_Ax Status Register</description>
+                  <addressOffset>0xA</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCBUSY</name>
+                        <description>eUSCI_A busy</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>UCBUSY_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>UCBUSY_0</name>
+                                <description>eUSCI_A inactive</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBUSY_1</name>
+                                <description>eUSCI_A transmitting or receiving</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCADDR_UCIDLE</name>
+                        <description>Address received / Idle line detected</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UCRXERR</name>
+                        <description>Receive error flag</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXERR_0</name>
+                                <description>No receive errors detected</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXERR_1</name>
+                                <description>Receive error detected</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBRK</name>
+                        <description>Break detect flag</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCBRK_0</name>
+                                <description>No break condition</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBRK_1</name>
+                                <description>Break condition occurred</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCPE</name>
+                        <description>Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read.</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCPE_0</name>
+                                <description>No error</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCPE_1</name>
+                                <description>Character received with parity error</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCOE</name>
+                        <description>Overrun error flag</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCOE_0</name>
+                                <description>No error</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCOE_1</name>
+                                <description>Overrun error occurred</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCFE</name>
+                        <description>Framing error flag</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCFE_0</name>
+                                <description>No error</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCFE_1</name>
+                                <description>Character received with low stop bit</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCLISTEN</name>
+                        <description>Listen enable</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCLISTEN_0</name>
+                                <description>Disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCLISTEN_1</name>
+                                <description>Enabled. UCAxTXD is internally fed back to the receiver</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxRXBUF</name>
+                  <displayName>RXBUF</displayName>
+                  <description>eUSCI_Ax Receive Buffer Register</description>
+                  <addressOffset>0xC</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCRXBUF</name>
+                        <description>Receive data buffer</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxTXBUF</name>
+                  <displayName>TXBUF</displayName>
+                  <description>eUSCI_Ax Transmit Buffer Register</description>
+                  <addressOffset>0xE</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCTXBUF</name>
+                        <description>Transmit data buffer</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxABCTL</name>
+                  <displayName>ABCTL</displayName>
+                  <description>eUSCI_Ax Auto Baud Rate Control Register</description>
+                  <addressOffset>0x10</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCABDEN</name>
+                        <description>Automatic baud-rate detect enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCABDEN_0</name>
+                                <description>Baud-rate detection disabled. Length of break and synch field is not measured.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCABDEN_1</name>
+                                <description>Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBTOE</name>
+                        <description>Break time out error</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCBTOE_0</name>
+                                <description>No error</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBTOE_1</name>
+                                <description>Length of break field exceeded 22 bit times</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTOE</name>
+                        <description>Synch field time out error</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTOE_0</name>
+                                <description>No error</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTOE_1</name>
+                                <description>Length of synch field exceeded measurable time</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCDELIM</name>
+                        <description>Break/synch delimiter length</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCDELIM_0</name>
+                                <description>1 bit time</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCDELIM_1</name>
+                                <description>2 bit times</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCDELIM_2</name>
+                                <description>3 bit times</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCDELIM_3</name>
+                                <description>4 bit times</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxIRCTL</name>
+                  <displayName>IRCTL</displayName>
+                  <description>eUSCI_Ax IrDA Control Word Register</description>
+                  <addressOffset>0x12</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCIREN</name>
+                        <description>IrDA encoder/decoder enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCIREN_0</name>
+                                <description>IrDA encoder/decoder disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIREN_1</name>
+                                <description>IrDA encoder/decoder enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCIRTXCLK</name>
+                        <description>IrDA transmit pulse clock select</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCIRTXCLK_0</name>
+                                <description>BRCLK</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIRTXCLK_1</name>
+                                <description>BITCLK16 when UCOS16 = 1. Otherwise, BRCLK.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCIRTXPL</name>
+                        <description>Transmit pulse length</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x6</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UCIRRXFE</name>
+                        <description>IrDA receive filter enabled</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCIRRXFE_0</name>
+                                <description>Receive filter disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIRRXFE_1</name>
+                                <description>Receive filter enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCIRRXPL</name>
+                        <description>IrDA receive input UCAxRXD polarity</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCIRRXPL_0</name>
+                                <description>IrDA transceiver delivers a high pulse when a light pulse is seen</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIRRXPL_1</name>
+                                <description>IrDA transceiver delivers a low pulse when a light pulse is seen</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCIRRXFL</name>
+                        <description>Receive filter length</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxIE</name>
+                  <displayName>IE</displayName>
+                  <description>eUSCI_Ax Interrupt Enable Register</description>
+                  <addressOffset>0x1A</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCRXIE</name>
+                        <description>Receive interrupt enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIE</name>
+                        <description>Transmit interrupt enable</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTTIE</name>
+                        <description>Start bit interrupt enable</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTTIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTTIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXCPTIE</name>
+                        <description>Transmit complete interrupt enable</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXCPTIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXCPTIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxIFG</name>
+                  <displayName>IFG</displayName>
+                  <description>eUSCI_Ax Interrupt Flag Register</description>
+                  <addressOffset>0x1C</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000002</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCRXIFG</name>
+                        <description>Receive interrupt flag</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIFG</name>
+                        <description>Transmit interrupt flag</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTTIFG</name>
+                        <description>Start bit interrupt flag</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTTIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTTIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXCPTIFG</name>
+                        <description>Transmit ready interrupt enable</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXCPTIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXCPTIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxIV</name>
+                  <displayName>IV</displayName>
+                  <description>eUSCI_Ax Interrupt Vector Register</description>
+                  <addressOffset>0x1E</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCIV</name>
+                        <description>eUSCI_A interrupt vector value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>UCIV_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>UCIV_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_2</name>
+                                <description>Interrupt Source: Receive buffer full; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_4</name>
+                                <description>Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_6</name>
+                                <description>Interrupt Source: Start bit received; Interrupt Flag: UCSTTIFG</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_8</name>
+                                <description>Interrupt Source: Transmit complete; Interrupt Flag: UCTXCPTIFG; Interrupt Priority: Lowest</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>EUSCI_A3</name>
+        <version>356.0</version>
+        <description>EUSCI_A3</description>
+        <baseAddress>0x40001C00</baseAddress>
+        <interrupt>
+            <name>EUSCIA3_IRQ</name>
+            <description>EUSCIA3 Interrupt</description>
+            <value>19</value>
+        </interrupt>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x20</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>UCAxCTLW0</name>
+                  <displayName>CTLW0</displayName>
+                  <description>eUSCI_Ax Control Word Register 0</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000001</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCSWRST</name>
+                        <description>Software reset enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSWRST_0</name>
+                                <description>Disabled. eUSCI_A reset released for operation</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSWRST_1</name>
+                                <description>Enabled. eUSCI_A logic held in reset state</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXBRK</name>
+                        <description>Transmit break</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXBRK_0</name>
+                                <description>Next frame transmitted is not a break</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXBRK_1</name>
+                                <description>Next frame transmitted is a break or a break/synch</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXADDR</name>
+                        <description>Transmit address</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXADDR_0</name>
+                                <description>Next frame transmitted is data</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXADDR_1</name>
+                                <description>Next frame transmitted is an address</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCDORM</name>
+                        <description>Dormant</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCDORM_0</name>
+                                <description>Not dormant. All received characters set UCRXIFG.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCDORM_1</name>
+                                <description>Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBRKIE</name>
+                        <description>Receive break character interrupt enable</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCBRKIE_0</name>
+                                <description>Received break characters do not set UCRXIFG</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBRKIE_1</name>
+                                <description>Received break characters set UCRXIFG</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCRXEIE</name>
+                        <description>Receive erroneous-character interrupt enable</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXEIE_0</name>
+                                <description>Erroneous characters rejected and UCRXIFG is not set</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXEIE_1</name>
+                                <description>Erroneous characters received set UCRXIFG</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSSEL</name>
+                        <description>eUSCI_A clock source select</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSSEL_0</name>
+                                <description>UCLK</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSSEL_1</name>
+                                <description>ACLK</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSSEL_2</name>
+                                <description>SMCLK</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSYNC</name>
+                        <description>Synchronous mode enable</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSYNC_0</name>
+                                <description>Asynchronous mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSYNC_1</name>
+                                <description>Synchronous mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCMODE</name>
+                        <description>eUSCI_A mode</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCMODE_0</name>
+                                <description>UART mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMODE_1</name>
+                                <description>Idle-line multiprocessor mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMODE_2</name>
+                                <description>Address-bit multiprocessor mode</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMODE_3</name>
+                                <description>UART mode with automatic baud-rate detection</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSPB</name>
+                        <description>Stop bit select</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSPB_0</name>
+                                <description>One stop bit</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSPB_1</name>
+                                <description>Two stop bits</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UC7BIT</name>
+                        <description>Character length</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UC7BIT_0</name>
+                                <description>8-bit data</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UC7BIT_1</name>
+                                <description>7-bit data</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCMSB</name>
+                        <description>MSB first select</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCMSB_0</name>
+                                <description>LSB first</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMSB_1</name>
+                                <description>MSB first</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCPAR</name>
+                        <description>Parity select</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCPAR_0</name>
+                                <description>Odd parity</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCPAR_1</name>
+                                <description>Even parity</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCPEN</name>
+                        <description>Parity enable</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCPEN_0</name>
+                                <description>Parity disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCPEN_1</name>
+                                <description>Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxCTLW1</name>
+                  <displayName>CTLW1</displayName>
+                  <description>eUSCI_Ax Control Word Register 1</description>
+                  <addressOffset>0x2</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000003</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCGLIT</name>
+                        <description>Deglitch time</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCGLIT_0</name>
+                                <description>Approximately 2 ns (equivalent of 1 delay element)</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGLIT_1</name>
+                                <description>Approximately 50 ns</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGLIT_2</name>
+                                <description>Approximately 100 ns</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGLIT_3</name>
+                                <description>Approximately 200 ns</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxBRW</name>
+                  <displayName>BRW</displayName>
+                  <description>eUSCI_Ax Baud Rate Control Word Register</description>
+                  <addressOffset>0x6</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x000000ff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCBR</name>
+                        <description>Clock prescaler setting of the Baud rate generator</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxMCTLW</name>
+                  <displayName>MCTLW</displayName>
+                  <description>eUSCI_Ax Modulation Control Word Register</description>
+                  <addressOffset>0x8</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCOS16</name>
+                        <description>Oversampling mode enabled</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCOS16_0</name>
+                                <description>Disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCOS16_1</name>
+                                <description>Enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBRF</name>
+                        <description>First modulation stage select</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UCBRS</name>
+                        <description>Second modulation stage select</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxSTATW</name>
+                  <displayName>STATW</displayName>
+                  <description>eUSCI_Ax Status Register</description>
+                  <addressOffset>0xA</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCBUSY</name>
+                        <description>eUSCI_A busy</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>UCBUSY_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>UCBUSY_0</name>
+                                <description>eUSCI_A inactive</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBUSY_1</name>
+                                <description>eUSCI_A transmitting or receiving</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCADDR_UCIDLE</name>
+                        <description>Address received / Idle line detected</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UCRXERR</name>
+                        <description>Receive error flag</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXERR_0</name>
+                                <description>No receive errors detected</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXERR_1</name>
+                                <description>Receive error detected</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBRK</name>
+                        <description>Break detect flag</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCBRK_0</name>
+                                <description>No break condition</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBRK_1</name>
+                                <description>Break condition occurred</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCPE</name>
+                        <description>Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read.</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCPE_0</name>
+                                <description>No error</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCPE_1</name>
+                                <description>Character received with parity error</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCOE</name>
+                        <description>Overrun error flag</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCOE_0</name>
+                                <description>No error</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCOE_1</name>
+                                <description>Overrun error occurred</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCFE</name>
+                        <description>Framing error flag</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCFE_0</name>
+                                <description>No error</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCFE_1</name>
+                                <description>Character received with low stop bit</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCLISTEN</name>
+                        <description>Listen enable</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCLISTEN_0</name>
+                                <description>Disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCLISTEN_1</name>
+                                <description>Enabled. UCAxTXD is internally fed back to the receiver</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxRXBUF</name>
+                  <displayName>RXBUF</displayName>
+                  <description>eUSCI_Ax Receive Buffer Register</description>
+                  <addressOffset>0xC</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCRXBUF</name>
+                        <description>Receive data buffer</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxTXBUF</name>
+                  <displayName>TXBUF</displayName>
+                  <description>eUSCI_Ax Transmit Buffer Register</description>
+                  <addressOffset>0xE</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCTXBUF</name>
+                        <description>Transmit data buffer</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxABCTL</name>
+                  <displayName>ABCTL</displayName>
+                  <description>eUSCI_Ax Auto Baud Rate Control Register</description>
+                  <addressOffset>0x10</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCABDEN</name>
+                        <description>Automatic baud-rate detect enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCABDEN_0</name>
+                                <description>Baud-rate detection disabled. Length of break and synch field is not measured.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCABDEN_1</name>
+                                <description>Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBTOE</name>
+                        <description>Break time out error</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCBTOE_0</name>
+                                <description>No error</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBTOE_1</name>
+                                <description>Length of break field exceeded 22 bit times</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTOE</name>
+                        <description>Synch field time out error</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTOE_0</name>
+                                <description>No error</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTOE_1</name>
+                                <description>Length of synch field exceeded measurable time</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCDELIM</name>
+                        <description>Break/synch delimiter length</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCDELIM_0</name>
+                                <description>1 bit time</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCDELIM_1</name>
+                                <description>2 bit times</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCDELIM_2</name>
+                                <description>3 bit times</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCDELIM_3</name>
+                                <description>4 bit times</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxIRCTL</name>
+                  <displayName>IRCTL</displayName>
+                  <description>eUSCI_Ax IrDA Control Word Register</description>
+                  <addressOffset>0x12</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCIREN</name>
+                        <description>IrDA encoder/decoder enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCIREN_0</name>
+                                <description>IrDA encoder/decoder disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIREN_1</name>
+                                <description>IrDA encoder/decoder enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCIRTXCLK</name>
+                        <description>IrDA transmit pulse clock select</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCIRTXCLK_0</name>
+                                <description>BRCLK</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIRTXCLK_1</name>
+                                <description>BITCLK16 when UCOS16 = 1. Otherwise, BRCLK.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCIRTXPL</name>
+                        <description>Transmit pulse length</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x6</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UCIRRXFE</name>
+                        <description>IrDA receive filter enabled</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCIRRXFE_0</name>
+                                <description>Receive filter disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIRRXFE_1</name>
+                                <description>Receive filter enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCIRRXPL</name>
+                        <description>IrDA receive input UCAxRXD polarity</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCIRRXPL_0</name>
+                                <description>IrDA transceiver delivers a high pulse when a light pulse is seen</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIRRXPL_1</name>
+                                <description>IrDA transceiver delivers a low pulse when a light pulse is seen</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCIRRXFL</name>
+                        <description>Receive filter length</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxIE</name>
+                  <displayName>IE</displayName>
+                  <description>eUSCI_Ax Interrupt Enable Register</description>
+                  <addressOffset>0x1A</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCRXIE</name>
+                        <description>Receive interrupt enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIE</name>
+                        <description>Transmit interrupt enable</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTTIE</name>
+                        <description>Start bit interrupt enable</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTTIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTTIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXCPTIE</name>
+                        <description>Transmit complete interrupt enable</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXCPTIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXCPTIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxIFG</name>
+                  <displayName>IFG</displayName>
+                  <description>eUSCI_Ax Interrupt Flag Register</description>
+                  <addressOffset>0x1C</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000002</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCRXIFG</name>
+                        <description>Receive interrupt flag</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIFG</name>
+                        <description>Transmit interrupt flag</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTTIFG</name>
+                        <description>Start bit interrupt flag</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTTIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTTIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXCPTIFG</name>
+                        <description>Transmit ready interrupt enable</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXCPTIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXCPTIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCAxIV</name>
+                  <displayName>IV</displayName>
+                  <description>eUSCI_Ax Interrupt Vector Register</description>
+                  <addressOffset>0x1E</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCIV</name>
+                        <description>eUSCI_A interrupt vector value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>UCIV_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>UCIV_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_2</name>
+                                <description>Interrupt Source: Receive buffer full; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_4</name>
+                                <description>Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_6</name>
+                                <description>Interrupt Source: Start bit received; Interrupt Flag: UCSTTIFG</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_8</name>
+                                <description>Interrupt Source: Transmit complete; Interrupt Flag: UCTXCPTIFG; Interrupt Priority: Lowest</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>EUSCI_B0</name>
+        <version>356.0</version>
+        <description>EUSCI_B0</description>
+        <baseAddress>0x40002000</baseAddress>
+        <interrupt>
+            <name>EUSCIB0_IRQ</name>
+            <description>EUSCIB0 Interrupt</description>
+            <value>20</value>
+        </interrupt>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x30</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>UCBxCTLW0</name>
+                  <displayName>CTLW0</displayName>
+                  <description>eUSCI_Bx Control Word Register 0</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x000001c1</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCSWRST</name>
+                        <description>Software reset enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSWRST_0</name>
+                                <description>Disabled. eUSCI_B reset released for operation</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSWRST_1</name>
+                                <description>Enabled. eUSCI_B logic held in reset state</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXSTT</name>
+                        <description>Transmit START condition in master mode</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXSTT_0</name>
+                                <description>Do not generate START condition</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXSTT_1</name>
+                                <description>Generate START condition</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXSTP</name>
+                        <description>Transmit STOP condition in master mode</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXSTP_0</name>
+                                <description>No STOP generated</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXSTP_1</name>
+                                <description>Generate STOP</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXNACK</name>
+                        <description>Transmit a NACK</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXNACK_0</name>
+                                <description>Acknowledge normally</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXNACK_1</name>
+                                <description>Generate NACK</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTR</name>
+                        <description>Transmitter/receiver</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTR_0</name>
+                                <description>Receiver</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTR_1</name>
+                                <description>Transmitter</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXACK</name>
+                        <description>Transmit ACK condition in slave mode</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXACK_0</name>
+                                <description>Do not acknowledge the slave address</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXACK_1</name>
+                                <description>Acknowledge the slave address</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSSEL</name>
+                        <description>eUSCI_B clock source select</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSSEL_0</name>
+                                <description>UCLKI</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSSEL_1</name>
+                                <description>ACLK</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSSEL_2</name>
+                                <description>SMCLK</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSSEL_3</name>
+                                <description>SMCLK</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSYNC</name>
+                        <description>Synchronous mode enable</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSYNC_0</name>
+                                <description>Asynchronous mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSYNC_1</name>
+                                <description>Synchronous mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCMODE</name>
+                        <description>eUSCI_B mode</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCMODE_0</name>
+                                <description>3-pin SPI</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMODE_1</name>
+                                <description>4-pin SPI (master or slave enabled if STE = 1)</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMODE_2</name>
+                                <description>4-pin SPI (master or slave enabled if STE = 0)</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMODE_3</name>
+                                <description>I2C mode</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCMST</name>
+                        <description>Master mode select</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCMST_0</name>
+                                <description>Slave mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMST_1</name>
+                                <description>Master mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCMM</name>
+                        <description>Multi-master environment select</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCMM_0</name>
+                                <description>Single master environment. There is no other master in the system. The address compare unit is disabled.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMM_1</name>
+                                <description>Multi-master environment</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSLA10</name>
+                        <description>Slave addressing mode select</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSLA10_0</name>
+                                <description>Address slave with 7-bit address</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSLA10_1</name>
+                                <description>Address slave with 10-bit address</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCA10</name>
+                        <description>Own addressing mode select</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCA10_0</name>
+                                <description>Own address is a 7-bit address</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCA10_1</name>
+                                <description>Own address is a 10-bit address</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxCTLW1</name>
+                  <displayName>CTLW1</displayName>
+                  <description>eUSCI_Bx Control Word Register 1</description>
+                  <addressOffset>0x2</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000003</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCGLIT</name>
+                        <description>Deglitch time</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCGLIT_0</name>
+                                <description>50 ns</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGLIT_1</name>
+                                <description>25 ns</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGLIT_2</name>
+                                <description>12.5 ns</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGLIT_3</name>
+                                <description>6.25 ns</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCASTP</name>
+                        <description>Automatic STOP condition generation</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCASTP_0</name>
+                                <description>No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCASTP_1</name>
+                                <description>UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCASTP_2</name>
+                                <description>A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSWACK</name>
+                        <description>SW or HW ACK control</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSWACK_0</name>
+                                <description>The address acknowledge of the slave is controlled by the eUSCI_B module</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSWACK_1</name>
+                                <description>The user needs to trigger the sending of the address ACK by issuing UCTXACK</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTPNACK</name>
+                        <description>ACK all master bytes</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTPNACK_0</name>
+                                <description>Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard)</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTPNACK_1</name>
+                                <description>All bytes are acknowledged by the eUSCI_B when configured as master receiver</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCCLTO</name>
+                        <description>Clock low timeout select</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCCLTO_0</name>
+                                <description>Disable clock low timeout counter</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCCLTO_1</name>
+                                <description>135 000 SYSCLK cycles (approximately 28 ms)</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCCLTO_2</name>
+                                <description>150 000 SYSCLK cycles (approximately 31 ms)</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCCLTO_3</name>
+                                <description>165 000 SYSCLK cycles (approximately 34 ms)</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCETXINT</name>
+                        <description>Early UCTXIFG0</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCETXINT_0</name>
+                                <description>UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCETXINT_1</name>
+                                <description>UCTXIFG0 is set for each START condition</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxBRW</name>
+                  <displayName>BRW</displayName>
+                  <description>eUSCI_Bx Baud Rate Control Word Register</description>
+                  <addressOffset>0x6</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCBR</name>
+                        <description>Bit clock prescaler</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxSTATW</name>
+                  <displayName>STATW</displayName>
+                  <description>eUSCI_Bx Status Register</description>
+                  <addressOffset>0x8</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCBBUSY</name>
+                        <description>Bus busy</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>UCBBUSY_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>UCBBUSY_0</name>
+                                <description>Bus inactive</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBBUSY_1</name>
+                                <description>Bus busy</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCGC</name>
+                        <description>General call address received</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>UCGC_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>UCGC_0</name>
+                                <description>No general call address received</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGC_1</name>
+                                <description>General call address received</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSCLLOW</name>
+                        <description>SCL low</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>UCSCLLOW_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>UCSCLLOW_0</name>
+                                <description>SCL is not held low</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSCLLOW_1</name>
+                                <description>SCL is held low</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBCNT</name>
+                        <description>Hardware byte counter value</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxTBCNT</name>
+                  <displayName>TBCNT</displayName>
+                  <description>eUSCI_Bx Byte Counter Threshold Register</description>
+                  <addressOffset>0xA</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCTBCNT</name>
+                        <description>Byte counter threshold value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxRXBUF</name>
+                  <displayName>RXBUF</displayName>
+                  <description>eUSCI_Bx Receive Buffer Register</description>
+                  <addressOffset>0xC</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCRXBUF</name>
+                        <description>Receive data buffer</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxTXBUF</name>
+                  <displayName>TXBUF</displayName>
+                  <description>eUSCI_Bx Transmit Buffer Register</description>
+                  <addressOffset>0xE</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCTXBUF</name>
+                        <description>Transmit data buffer</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxI2COA0</name>
+                  <displayName>I2COA0</displayName>
+                  <description>eUSCI_Bx I2C Own Address 0 Register</description>
+                  <addressOffset>0x14</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>I2COA0</name>
+                        <description>I2C own address</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0xA</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UCOAEN</name>
+                        <description>Own Address enable register</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCOAEN_0</name>
+                                <description>The slave address defined in I2COA0 is disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCOAEN_1</name>
+                                <description>The slave address defined in I2COA0 is enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCGCEN</name>
+                        <description>General call response enable</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCGCEN_0</name>
+                                <description>Do not respond to a general call</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGCEN_1</name>
+                                <description>Respond to a general call</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxI2COA1</name>
+                  <displayName>I2COA1</displayName>
+                  <description>eUSCI_Bx I2C Own Address 1 Register</description>
+                  <addressOffset>0x16</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>I2COA1</name>
+                        <description>I2C own address</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0xA</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UCOAEN</name>
+                        <description>Own Address enable register</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCOAEN_0</name>
+                                <description>The slave address defined in I2COA1 is disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCOAEN_1</name>
+                                <description>The slave address defined in I2COA1 is enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxI2COA2</name>
+                  <displayName>I2COA2</displayName>
+                  <description>eUSCI_Bx I2C Own Address 2 Register</description>
+                  <addressOffset>0x18</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>I2COA2</name>
+                        <description>I2C own address</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0xA</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UCOAEN</name>
+                        <description>Own Address enable register</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCOAEN_0</name>
+                                <description>The slave address defined in I2COA2 is disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCOAEN_1</name>
+                                <description>The slave address defined in I2COA2 is enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxI2COA3</name>
+                  <displayName>I2COA3</displayName>
+                  <description>eUSCI_Bx I2C Own Address 3 Register</description>
+                  <addressOffset>0x1A</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>I2COA3</name>
+                        <description>I2C own address</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0xA</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UCOAEN</name>
+                        <description>Own Address enable register</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCOAEN_0</name>
+                                <description>The slave address defined in I2COA3 is disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCOAEN_1</name>
+                                <description>The slave address defined in I2COA3 is enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxADDRX</name>
+                  <displayName>ADDRX</displayName>
+                  <description>eUSCI_Bx I2C Received Address Register</description>
+                  <addressOffset>0x1C</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>ADDRX</name>
+                        <description>Received Address Register</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0xA</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxADDMASK</name>
+                  <displayName>ADDMASK</displayName>
+                  <description>eUSCI_Bx I2C Address Mask Register</description>
+                  <addressOffset>0x1E</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x000003ff</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>ADDMASK</name>
+                        <description>Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated.

+Modify only when UCSWRST = 1.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0xA</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxI2CSA</name>
+                  <displayName>I2CSA</displayName>
+                  <description>eUSCI_Bx I2C Slave Address Register</description>
+                  <addressOffset>0x20</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>I2CSA</name>
+                        <description>I2C slave address</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0xA</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxIE</name>
+                  <displayName>IE</displayName>
+                  <description>eUSCI_Bx Interrupt Enable Register</description>
+                  <addressOffset>0x2A</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCRXIE0</name>
+                        <description>Receive interrupt enable 0</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIE0_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIE0_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIE0</name>
+                        <description>Transmit interrupt enable 0</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIE0_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIE0_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTTIE</name>
+                        <description>START condition interrupt enable</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTTIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTTIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTPIE</name>
+                        <description>STOP condition interrupt enable</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTPIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTPIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCALIE</name>
+                        <description>Arbitration lost interrupt enable</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCALIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCALIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCNACKIE</name>
+                        <description>Not-acknowledge interrupt enable</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCNACKIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCNACKIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBCNTIE</name>
+                        <description>Byte counter interrupt enable</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCBCNTIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBCNTIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCCLTOIE</name>
+                        <description>Clock low timeout interrupt enable</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCCLTOIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCCLTOIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCRXIE1</name>
+                        <description>Receive interrupt enable 1</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIE1_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIE1_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIE1</name>
+                        <description>Transmit interrupt enable 1</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIE1_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIE1_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCRXIE2</name>
+                        <description>Receive interrupt enable 2</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIE2_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIE2_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIE2</name>
+                        <description>Transmit interrupt enable 2</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIE2_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIE2_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCRXIE3</name>
+                        <description>Receive interrupt enable 3</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIE3_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIE3_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIE3</name>
+                        <description>Transmit interrupt enable 3</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIE3_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIE3_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBIT9IE</name>
+                        <description>Bit position 9 interrupt enable</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCBIT9IE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBIT9IE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxIFG</name>
+                  <displayName>IFG</displayName>
+                  <description>eUSCI_Bx Interrupt Flag Register</description>
+                  <addressOffset>0x2C</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000002</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCRXIFG0</name>
+                        <description>eUSCI_B receive interrupt flag 0</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIFG0_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIFG0_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIFG0</name>
+                        <description>eUSCI_B transmit interrupt flag 0</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIFG0_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIFG0_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTTIFG</name>
+                        <description>START condition interrupt flag</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTTIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTTIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTPIFG</name>
+                        <description>STOP condition interrupt flag</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTPIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTPIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCALIFG</name>
+                        <description>Arbitration lost interrupt flag</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCALIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCALIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCNACKIFG</name>
+                        <description>Not-acknowledge received interrupt flag</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCNACKIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCNACKIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBCNTIFG</name>
+                        <description>Byte counter interrupt flag</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCBCNTIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBCNTIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCCLTOIFG</name>
+                        <description>Clock low timeout interrupt flag</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCCLTOIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCCLTOIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCRXIFG1</name>
+                        <description>eUSCI_B receive interrupt flag 1</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIFG1_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIFG1_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIFG1</name>
+                        <description>eUSCI_B transmit interrupt flag 1</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIFG1_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIFG1_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCRXIFG2</name>
+                        <description>eUSCI_B receive interrupt flag 2</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIFG2_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIFG2_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIFG2</name>
+                        <description>eUSCI_B transmit interrupt flag 2</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIFG2_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIFG2_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCRXIFG3</name>
+                        <description>eUSCI_B receive interrupt flag 3</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIFG3_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIFG3_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIFG3</name>
+                        <description>eUSCI_B transmit interrupt flag 3</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIFG3_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIFG3_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBIT9IFG</name>
+                        <description>Bit position 9 interrupt flag</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCBIT9IFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBIT9IFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxIV</name>
+                  <displayName>IV</displayName>
+                  <description>eUSCI_Bx Interrupt Vector Register</description>
+                  <addressOffset>0x2E</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCIV</name>
+                        <description>eUSCI_B interrupt vector value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>UCIV_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>UCIV_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_2</name>
+                                <description>Interrupt Source: Arbitration lost; Interrupt Flag: UCALIFG; Interrupt Priority: Highest</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_4</name>
+                                <description>Interrupt Source: Not acknowledgment; Interrupt Flag: UCNACKIFG</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_6</name>
+                                <description>Interrupt Source: Start condition received; Interrupt Flag: UCSTTIFG</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_8</name>
+                                <description>Interrupt Source: Stop condition received; Interrupt Flag: UCSTPIFG</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_10</name>
+                                <description>Interrupt Source: Slave 3 Data received; Interrupt Flag: UCRXIFG3</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_12</name>
+                                <description>Interrupt Source: Slave 3 Transmit buffer empty; Interrupt Flag: UCTXIFG3</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_14</name>
+                                <description>Interrupt Source: Slave 2 Data received; Interrupt Flag: UCRXIFG2</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_16</name>
+                                <description>Interrupt Source: Slave 2 Transmit buffer empty; Interrupt Flag: UCTXIFG2</description>
+                                <value>16</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_18</name>
+                                <description>Interrupt Source: Slave 1 Data received; Interrupt Flag: UCRXIFG1</description>
+                                <value>18</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_20</name>
+                                <description>Interrupt Source: Slave 1 Transmit buffer empty; Interrupt Flag: UCTXIFG1</description>
+                                <value>20</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_22</name>
+                                <description>Interrupt Source: Data received; Interrupt Flag: UCRXIFG0</description>
+                                <value>22</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_24</name>
+                                <description>Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG0</description>
+                                <value>24</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_26</name>
+                                <description>Interrupt Source: Byte counter zero; Interrupt Flag: UCBCNTIFG</description>
+                                <value>26</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_28</name>
+                                <description>Interrupt Source: Clock low timeout; Interrupt Flag: UCCLTOIFG</description>
+                                <value>28</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_30</name>
+                                <description>Interrupt Source: Nineth bit position; Interrupt Flag: UCBIT9IFG; Priority: Lowest</description>
+                                <value>30</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>EUSCI_B1</name>
+        <version>356.0</version>
+        <description>EUSCI_B1</description>
+        <baseAddress>0x40002400</baseAddress>
+        <interrupt>
+            <name>EUSCIB1_IRQ</name>
+            <description>EUSCIB1 Interrupt</description>
+            <value>21</value>
+        </interrupt>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x30</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>UCBxCTLW0</name>
+                  <displayName>CTLW0</displayName>
+                  <description>eUSCI_Bx Control Word Register 0</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x000001c1</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCSWRST</name>
+                        <description>Software reset enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSWRST_0</name>
+                                <description>Disabled. eUSCI_B reset released for operation</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSWRST_1</name>
+                                <description>Enabled. eUSCI_B logic held in reset state</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXSTT</name>
+                        <description>Transmit START condition in master mode</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXSTT_0</name>
+                                <description>Do not generate START condition</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXSTT_1</name>
+                                <description>Generate START condition</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXSTP</name>
+                        <description>Transmit STOP condition in master mode</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXSTP_0</name>
+                                <description>No STOP generated</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXSTP_1</name>
+                                <description>Generate STOP</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXNACK</name>
+                        <description>Transmit a NACK</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXNACK_0</name>
+                                <description>Acknowledge normally</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXNACK_1</name>
+                                <description>Generate NACK</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTR</name>
+                        <description>Transmitter/receiver</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTR_0</name>
+                                <description>Receiver</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTR_1</name>
+                                <description>Transmitter</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXACK</name>
+                        <description>Transmit ACK condition in slave mode</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXACK_0</name>
+                                <description>Do not acknowledge the slave address</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXACK_1</name>
+                                <description>Acknowledge the slave address</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSSEL</name>
+                        <description>eUSCI_B clock source select</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSSEL_0</name>
+                                <description>UCLKI</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSSEL_1</name>
+                                <description>ACLK</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSSEL_2</name>
+                                <description>SMCLK</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSSEL_3</name>
+                                <description>SMCLK</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSYNC</name>
+                        <description>Synchronous mode enable</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSYNC_0</name>
+                                <description>Asynchronous mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSYNC_1</name>
+                                <description>Synchronous mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCMODE</name>
+                        <description>eUSCI_B mode</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCMODE_0</name>
+                                <description>3-pin SPI</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMODE_1</name>
+                                <description>4-pin SPI (master or slave enabled if STE = 1)</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMODE_2</name>
+                                <description>4-pin SPI (master or slave enabled if STE = 0)</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMODE_3</name>
+                                <description>I2C mode</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCMST</name>
+                        <description>Master mode select</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCMST_0</name>
+                                <description>Slave mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMST_1</name>
+                                <description>Master mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCMM</name>
+                        <description>Multi-master environment select</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCMM_0</name>
+                                <description>Single master environment. There is no other master in the system. The address compare unit is disabled.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMM_1</name>
+                                <description>Multi-master environment</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSLA10</name>
+                        <description>Slave addressing mode select</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSLA10_0</name>
+                                <description>Address slave with 7-bit address</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSLA10_1</name>
+                                <description>Address slave with 10-bit address</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCA10</name>
+                        <description>Own addressing mode select</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCA10_0</name>
+                                <description>Own address is a 7-bit address</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCA10_1</name>
+                                <description>Own address is a 10-bit address</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxCTLW1</name>
+                  <displayName>CTLW1</displayName>
+                  <description>eUSCI_Bx Control Word Register 1</description>
+                  <addressOffset>0x2</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000003</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCGLIT</name>
+                        <description>Deglitch time</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCGLIT_0</name>
+                                <description>50 ns</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGLIT_1</name>
+                                <description>25 ns</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGLIT_2</name>
+                                <description>12.5 ns</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGLIT_3</name>
+                                <description>6.25 ns</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCASTP</name>
+                        <description>Automatic STOP condition generation</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCASTP_0</name>
+                                <description>No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCASTP_1</name>
+                                <description>UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCASTP_2</name>
+                                <description>A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSWACK</name>
+                        <description>SW or HW ACK control</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSWACK_0</name>
+                                <description>The address acknowledge of the slave is controlled by the eUSCI_B module</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSWACK_1</name>
+                                <description>The user needs to trigger the sending of the address ACK by issuing UCTXACK</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTPNACK</name>
+                        <description>ACK all master bytes</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTPNACK_0</name>
+                                <description>Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard)</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTPNACK_1</name>
+                                <description>All bytes are acknowledged by the eUSCI_B when configured as master receiver</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCCLTO</name>
+                        <description>Clock low timeout select</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCCLTO_0</name>
+                                <description>Disable clock low timeout counter</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCCLTO_1</name>
+                                <description>135 000 SYSCLK cycles (approximately 28 ms)</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCCLTO_2</name>
+                                <description>150 000 SYSCLK cycles (approximately 31 ms)</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCCLTO_3</name>
+                                <description>165 000 SYSCLK cycles (approximately 34 ms)</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCETXINT</name>
+                        <description>Early UCTXIFG0</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCETXINT_0</name>
+                                <description>UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCETXINT_1</name>
+                                <description>UCTXIFG0 is set for each START condition</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxBRW</name>
+                  <displayName>BRW</displayName>
+                  <description>eUSCI_Bx Baud Rate Control Word Register</description>
+                  <addressOffset>0x6</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCBR</name>
+                        <description>Bit clock prescaler</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxSTATW</name>
+                  <displayName>STATW</displayName>
+                  <description>eUSCI_Bx Status Register</description>
+                  <addressOffset>0x8</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCBBUSY</name>
+                        <description>Bus busy</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>UCBBUSY_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>UCBBUSY_0</name>
+                                <description>Bus inactive</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBBUSY_1</name>
+                                <description>Bus busy</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCGC</name>
+                        <description>General call address received</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>UCGC_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>UCGC_0</name>
+                                <description>No general call address received</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGC_1</name>
+                                <description>General call address received</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSCLLOW</name>
+                        <description>SCL low</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>UCSCLLOW_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>UCSCLLOW_0</name>
+                                <description>SCL is not held low</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSCLLOW_1</name>
+                                <description>SCL is held low</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBCNT</name>
+                        <description>Hardware byte counter value</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxTBCNT</name>
+                  <displayName>TBCNT</displayName>
+                  <description>eUSCI_Bx Byte Counter Threshold Register</description>
+                  <addressOffset>0xA</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCTBCNT</name>
+                        <description>Byte counter threshold value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxRXBUF</name>
+                  <displayName>RXBUF</displayName>
+                  <description>eUSCI_Bx Receive Buffer Register</description>
+                  <addressOffset>0xC</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCRXBUF</name>
+                        <description>Receive data buffer</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxTXBUF</name>
+                  <displayName>TXBUF</displayName>
+                  <description>eUSCI_Bx Transmit Buffer Register</description>
+                  <addressOffset>0xE</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCTXBUF</name>
+                        <description>Transmit data buffer</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxI2COA0</name>
+                  <displayName>I2COA0</displayName>
+                  <description>eUSCI_Bx I2C Own Address 0 Register</description>
+                  <addressOffset>0x14</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>I2COA0</name>
+                        <description>I2C own address</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0xA</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UCOAEN</name>
+                        <description>Own Address enable register</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCOAEN_0</name>
+                                <description>The slave address defined in I2COA0 is disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCOAEN_1</name>
+                                <description>The slave address defined in I2COA0 is enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCGCEN</name>
+                        <description>General call response enable</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCGCEN_0</name>
+                                <description>Do not respond to a general call</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGCEN_1</name>
+                                <description>Respond to a general call</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxI2COA1</name>
+                  <displayName>I2COA1</displayName>
+                  <description>eUSCI_Bx I2C Own Address 1 Register</description>
+                  <addressOffset>0x16</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>I2COA1</name>
+                        <description>I2C own address</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0xA</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UCOAEN</name>
+                        <description>Own Address enable register</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCOAEN_0</name>
+                                <description>The slave address defined in I2COA1 is disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCOAEN_1</name>
+                                <description>The slave address defined in I2COA1 is enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxI2COA2</name>
+                  <displayName>I2COA2</displayName>
+                  <description>eUSCI_Bx I2C Own Address 2 Register</description>
+                  <addressOffset>0x18</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>I2COA2</name>
+                        <description>I2C own address</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0xA</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UCOAEN</name>
+                        <description>Own Address enable register</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCOAEN_0</name>
+                                <description>The slave address defined in I2COA2 is disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCOAEN_1</name>
+                                <description>The slave address defined in I2COA2 is enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxI2COA3</name>
+                  <displayName>I2COA3</displayName>
+                  <description>eUSCI_Bx I2C Own Address 3 Register</description>
+                  <addressOffset>0x1A</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>I2COA3</name>
+                        <description>I2C own address</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0xA</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UCOAEN</name>
+                        <description>Own Address enable register</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCOAEN_0</name>
+                                <description>The slave address defined in I2COA3 is disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCOAEN_1</name>
+                                <description>The slave address defined in I2COA3 is enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxADDRX</name>
+                  <displayName>ADDRX</displayName>
+                  <description>eUSCI_Bx I2C Received Address Register</description>
+                  <addressOffset>0x1C</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>ADDRX</name>
+                        <description>Received Address Register</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0xA</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxADDMASK</name>
+                  <displayName>ADDMASK</displayName>
+                  <description>eUSCI_Bx I2C Address Mask Register</description>
+                  <addressOffset>0x1E</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x000003ff</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>ADDMASK</name>
+                        <description>Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated.

+Modify only when UCSWRST = 1.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0xA</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxI2CSA</name>
+                  <displayName>I2CSA</displayName>
+                  <description>eUSCI_Bx I2C Slave Address Register</description>
+                  <addressOffset>0x20</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>I2CSA</name>
+                        <description>I2C slave address</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0xA</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxIE</name>
+                  <displayName>IE</displayName>
+                  <description>eUSCI_Bx Interrupt Enable Register</description>
+                  <addressOffset>0x2A</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCRXIE0</name>
+                        <description>Receive interrupt enable 0</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIE0_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIE0_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIE0</name>
+                        <description>Transmit interrupt enable 0</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIE0_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIE0_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTTIE</name>
+                        <description>START condition interrupt enable</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTTIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTTIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTPIE</name>
+                        <description>STOP condition interrupt enable</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTPIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTPIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCALIE</name>
+                        <description>Arbitration lost interrupt enable</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCALIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCALIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCNACKIE</name>
+                        <description>Not-acknowledge interrupt enable</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCNACKIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCNACKIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBCNTIE</name>
+                        <description>Byte counter interrupt enable</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCBCNTIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBCNTIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCCLTOIE</name>
+                        <description>Clock low timeout interrupt enable</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCCLTOIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCCLTOIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCRXIE1</name>
+                        <description>Receive interrupt enable 1</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIE1_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIE1_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIE1</name>
+                        <description>Transmit interrupt enable 1</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIE1_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIE1_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCRXIE2</name>
+                        <description>Receive interrupt enable 2</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIE2_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIE2_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIE2</name>
+                        <description>Transmit interrupt enable 2</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIE2_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIE2_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCRXIE3</name>
+                        <description>Receive interrupt enable 3</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIE3_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIE3_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIE3</name>
+                        <description>Transmit interrupt enable 3</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIE3_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIE3_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBIT9IE</name>
+                        <description>Bit position 9 interrupt enable</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCBIT9IE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBIT9IE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxIFG</name>
+                  <displayName>IFG</displayName>
+                  <description>eUSCI_Bx Interrupt Flag Register</description>
+                  <addressOffset>0x2C</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000002</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCRXIFG0</name>
+                        <description>eUSCI_B receive interrupt flag 0</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIFG0_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIFG0_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIFG0</name>
+                        <description>eUSCI_B transmit interrupt flag 0</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIFG0_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIFG0_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTTIFG</name>
+                        <description>START condition interrupt flag</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTTIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTTIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTPIFG</name>
+                        <description>STOP condition interrupt flag</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTPIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTPIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCALIFG</name>
+                        <description>Arbitration lost interrupt flag</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCALIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCALIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCNACKIFG</name>
+                        <description>Not-acknowledge received interrupt flag</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCNACKIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCNACKIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBCNTIFG</name>
+                        <description>Byte counter interrupt flag</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCBCNTIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBCNTIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCCLTOIFG</name>
+                        <description>Clock low timeout interrupt flag</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCCLTOIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCCLTOIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCRXIFG1</name>
+                        <description>eUSCI_B receive interrupt flag 1</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIFG1_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIFG1_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIFG1</name>
+                        <description>eUSCI_B transmit interrupt flag 1</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIFG1_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIFG1_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCRXIFG2</name>
+                        <description>eUSCI_B receive interrupt flag 2</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIFG2_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIFG2_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIFG2</name>
+                        <description>eUSCI_B transmit interrupt flag 2</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIFG2_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIFG2_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCRXIFG3</name>
+                        <description>eUSCI_B receive interrupt flag 3</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIFG3_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIFG3_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIFG3</name>
+                        <description>eUSCI_B transmit interrupt flag 3</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIFG3_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIFG3_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBIT9IFG</name>
+                        <description>Bit position 9 interrupt flag</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCBIT9IFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBIT9IFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxIV</name>
+                  <displayName>IV</displayName>
+                  <description>eUSCI_Bx Interrupt Vector Register</description>
+                  <addressOffset>0x2E</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCIV</name>
+                        <description>eUSCI_B interrupt vector value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>UCIV_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>UCIV_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_2</name>
+                                <description>Interrupt Source: Arbitration lost; Interrupt Flag: UCALIFG; Interrupt Priority: Highest</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_4</name>
+                                <description>Interrupt Source: Not acknowledgment; Interrupt Flag: UCNACKIFG</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_6</name>
+                                <description>Interrupt Source: Start condition received; Interrupt Flag: UCSTTIFG</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_8</name>
+                                <description>Interrupt Source: Stop condition received; Interrupt Flag: UCSTPIFG</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_10</name>
+                                <description>Interrupt Source: Slave 3 Data received; Interrupt Flag: UCRXIFG3</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_12</name>
+                                <description>Interrupt Source: Slave 3 Transmit buffer empty; Interrupt Flag: UCTXIFG3</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_14</name>
+                                <description>Interrupt Source: Slave 2 Data received; Interrupt Flag: UCRXIFG2</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_16</name>
+                                <description>Interrupt Source: Slave 2 Transmit buffer empty; Interrupt Flag: UCTXIFG2</description>
+                                <value>16</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_18</name>
+                                <description>Interrupt Source: Slave 1 Data received; Interrupt Flag: UCRXIFG1</description>
+                                <value>18</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_20</name>
+                                <description>Interrupt Source: Slave 1 Transmit buffer empty; Interrupt Flag: UCTXIFG1</description>
+                                <value>20</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_22</name>
+                                <description>Interrupt Source: Data received; Interrupt Flag: UCRXIFG0</description>
+                                <value>22</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_24</name>
+                                <description>Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG0</description>
+                                <value>24</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_26</name>
+                                <description>Interrupt Source: Byte counter zero; Interrupt Flag: UCBCNTIFG</description>
+                                <value>26</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_28</name>
+                                <description>Interrupt Source: Clock low timeout; Interrupt Flag: UCCLTOIFG</description>
+                                <value>28</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_30</name>
+                                <description>Interrupt Source: Nineth bit position; Interrupt Flag: UCBIT9IFG; Priority: Lowest</description>
+                                <value>30</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>EUSCI_B2</name>
+        <version>356.0</version>
+        <description>EUSCI_B2</description>
+        <baseAddress>0x40002800</baseAddress>
+        <interrupt>
+            <name>EUSCIB2_IRQ</name>
+            <description>EUSCIB2 Interrupt</description>
+            <value>22</value>
+        </interrupt>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x30</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>UCBxCTLW0</name>
+                  <displayName>CTLW0</displayName>
+                  <description>eUSCI_Bx Control Word Register 0</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x000001c1</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCSWRST</name>
+                        <description>Software reset enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSWRST_0</name>
+                                <description>Disabled. eUSCI_B reset released for operation</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSWRST_1</name>
+                                <description>Enabled. eUSCI_B logic held in reset state</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXSTT</name>
+                        <description>Transmit START condition in master mode</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXSTT_0</name>
+                                <description>Do not generate START condition</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXSTT_1</name>
+                                <description>Generate START condition</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXSTP</name>
+                        <description>Transmit STOP condition in master mode</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXSTP_0</name>
+                                <description>No STOP generated</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXSTP_1</name>
+                                <description>Generate STOP</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXNACK</name>
+                        <description>Transmit a NACK</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXNACK_0</name>
+                                <description>Acknowledge normally</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXNACK_1</name>
+                                <description>Generate NACK</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTR</name>
+                        <description>Transmitter/receiver</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTR_0</name>
+                                <description>Receiver</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTR_1</name>
+                                <description>Transmitter</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXACK</name>
+                        <description>Transmit ACK condition in slave mode</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXACK_0</name>
+                                <description>Do not acknowledge the slave address</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXACK_1</name>
+                                <description>Acknowledge the slave address</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSSEL</name>
+                        <description>eUSCI_B clock source select</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSSEL_0</name>
+                                <description>UCLKI</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSSEL_1</name>
+                                <description>ACLK</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSSEL_2</name>
+                                <description>SMCLK</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSSEL_3</name>
+                                <description>SMCLK</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSYNC</name>
+                        <description>Synchronous mode enable</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSYNC_0</name>
+                                <description>Asynchronous mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSYNC_1</name>
+                                <description>Synchronous mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCMODE</name>
+                        <description>eUSCI_B mode</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCMODE_0</name>
+                                <description>3-pin SPI</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMODE_1</name>
+                                <description>4-pin SPI (master or slave enabled if STE = 1)</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMODE_2</name>
+                                <description>4-pin SPI (master or slave enabled if STE = 0)</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMODE_3</name>
+                                <description>I2C mode</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCMST</name>
+                        <description>Master mode select</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCMST_0</name>
+                                <description>Slave mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMST_1</name>
+                                <description>Master mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCMM</name>
+                        <description>Multi-master environment select</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCMM_0</name>
+                                <description>Single master environment. There is no other master in the system. The address compare unit is disabled.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMM_1</name>
+                                <description>Multi-master environment</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSLA10</name>
+                        <description>Slave addressing mode select</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSLA10_0</name>
+                                <description>Address slave with 7-bit address</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSLA10_1</name>
+                                <description>Address slave with 10-bit address</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCA10</name>
+                        <description>Own addressing mode select</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCA10_0</name>
+                                <description>Own address is a 7-bit address</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCA10_1</name>
+                                <description>Own address is a 10-bit address</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxCTLW1</name>
+                  <displayName>CTLW1</displayName>
+                  <description>eUSCI_Bx Control Word Register 1</description>
+                  <addressOffset>0x2</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000003</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCGLIT</name>
+                        <description>Deglitch time</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCGLIT_0</name>
+                                <description>50 ns</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGLIT_1</name>
+                                <description>25 ns</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGLIT_2</name>
+                                <description>12.5 ns</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGLIT_3</name>
+                                <description>6.25 ns</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCASTP</name>
+                        <description>Automatic STOP condition generation</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCASTP_0</name>
+                                <description>No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCASTP_1</name>
+                                <description>UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCASTP_2</name>
+                                <description>A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSWACK</name>
+                        <description>SW or HW ACK control</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSWACK_0</name>
+                                <description>The address acknowledge of the slave is controlled by the eUSCI_B module</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSWACK_1</name>
+                                <description>The user needs to trigger the sending of the address ACK by issuing UCTXACK</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTPNACK</name>
+                        <description>ACK all master bytes</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTPNACK_0</name>
+                                <description>Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard)</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTPNACK_1</name>
+                                <description>All bytes are acknowledged by the eUSCI_B when configured as master receiver</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCCLTO</name>
+                        <description>Clock low timeout select</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCCLTO_0</name>
+                                <description>Disable clock low timeout counter</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCCLTO_1</name>
+                                <description>135 000 SYSCLK cycles (approximately 28 ms)</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCCLTO_2</name>
+                                <description>150 000 SYSCLK cycles (approximately 31 ms)</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCCLTO_3</name>
+                                <description>165 000 SYSCLK cycles (approximately 34 ms)</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCETXINT</name>
+                        <description>Early UCTXIFG0</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCETXINT_0</name>
+                                <description>UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCETXINT_1</name>
+                                <description>UCTXIFG0 is set for each START condition</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxBRW</name>
+                  <displayName>BRW</displayName>
+                  <description>eUSCI_Bx Baud Rate Control Word Register</description>
+                  <addressOffset>0x6</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCBR</name>
+                        <description>Bit clock prescaler</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxSTATW</name>
+                  <displayName>STATW</displayName>
+                  <description>eUSCI_Bx Status Register</description>
+                  <addressOffset>0x8</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCBBUSY</name>
+                        <description>Bus busy</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>UCBBUSY_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>UCBBUSY_0</name>
+                                <description>Bus inactive</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBBUSY_1</name>
+                                <description>Bus busy</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCGC</name>
+                        <description>General call address received</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>UCGC_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>UCGC_0</name>
+                                <description>No general call address received</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGC_1</name>
+                                <description>General call address received</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSCLLOW</name>
+                        <description>SCL low</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>UCSCLLOW_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>UCSCLLOW_0</name>
+                                <description>SCL is not held low</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSCLLOW_1</name>
+                                <description>SCL is held low</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBCNT</name>
+                        <description>Hardware byte counter value</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxTBCNT</name>
+                  <displayName>TBCNT</displayName>
+                  <description>eUSCI_Bx Byte Counter Threshold Register</description>
+                  <addressOffset>0xA</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCTBCNT</name>
+                        <description>Byte counter threshold value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxRXBUF</name>
+                  <displayName>RXBUF</displayName>
+                  <description>eUSCI_Bx Receive Buffer Register</description>
+                  <addressOffset>0xC</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCRXBUF</name>
+                        <description>Receive data buffer</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxTXBUF</name>
+                  <displayName>TXBUF</displayName>
+                  <description>eUSCI_Bx Transmit Buffer Register</description>
+                  <addressOffset>0xE</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCTXBUF</name>
+                        <description>Transmit data buffer</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxI2COA0</name>
+                  <displayName>I2COA0</displayName>
+                  <description>eUSCI_Bx I2C Own Address 0 Register</description>
+                  <addressOffset>0x14</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>I2COA0</name>
+                        <description>I2C own address</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0xA</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UCOAEN</name>
+                        <description>Own Address enable register</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCOAEN_0</name>
+                                <description>The slave address defined in I2COA0 is disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCOAEN_1</name>
+                                <description>The slave address defined in I2COA0 is enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCGCEN</name>
+                        <description>General call response enable</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCGCEN_0</name>
+                                <description>Do not respond to a general call</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGCEN_1</name>
+                                <description>Respond to a general call</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxI2COA1</name>
+                  <displayName>I2COA1</displayName>
+                  <description>eUSCI_Bx I2C Own Address 1 Register</description>
+                  <addressOffset>0x16</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>I2COA1</name>
+                        <description>I2C own address</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0xA</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UCOAEN</name>
+                        <description>Own Address enable register</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCOAEN_0</name>
+                                <description>The slave address defined in I2COA1 is disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCOAEN_1</name>
+                                <description>The slave address defined in I2COA1 is enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxI2COA2</name>
+                  <displayName>I2COA2</displayName>
+                  <description>eUSCI_Bx I2C Own Address 2 Register</description>
+                  <addressOffset>0x18</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>I2COA2</name>
+                        <description>I2C own address</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0xA</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UCOAEN</name>
+                        <description>Own Address enable register</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCOAEN_0</name>
+                                <description>The slave address defined in I2COA2 is disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCOAEN_1</name>
+                                <description>The slave address defined in I2COA2 is enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxI2COA3</name>
+                  <displayName>I2COA3</displayName>
+                  <description>eUSCI_Bx I2C Own Address 3 Register</description>
+                  <addressOffset>0x1A</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>I2COA3</name>
+                        <description>I2C own address</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0xA</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UCOAEN</name>
+                        <description>Own Address enable register</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCOAEN_0</name>
+                                <description>The slave address defined in I2COA3 is disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCOAEN_1</name>
+                                <description>The slave address defined in I2COA3 is enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxADDRX</name>
+                  <displayName>ADDRX</displayName>
+                  <description>eUSCI_Bx I2C Received Address Register</description>
+                  <addressOffset>0x1C</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>ADDRX</name>
+                        <description>Received Address Register</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0xA</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxADDMASK</name>
+                  <displayName>ADDMASK</displayName>
+                  <description>eUSCI_Bx I2C Address Mask Register</description>
+                  <addressOffset>0x1E</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x000003ff</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>ADDMASK</name>
+                        <description>Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated.

+Modify only when UCSWRST = 1.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0xA</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxI2CSA</name>
+                  <displayName>I2CSA</displayName>
+                  <description>eUSCI_Bx I2C Slave Address Register</description>
+                  <addressOffset>0x20</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>I2CSA</name>
+                        <description>I2C slave address</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0xA</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxIE</name>
+                  <displayName>IE</displayName>
+                  <description>eUSCI_Bx Interrupt Enable Register</description>
+                  <addressOffset>0x2A</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCRXIE0</name>
+                        <description>Receive interrupt enable 0</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIE0_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIE0_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIE0</name>
+                        <description>Transmit interrupt enable 0</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIE0_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIE0_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTTIE</name>
+                        <description>START condition interrupt enable</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTTIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTTIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTPIE</name>
+                        <description>STOP condition interrupt enable</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTPIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTPIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCALIE</name>
+                        <description>Arbitration lost interrupt enable</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCALIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCALIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCNACKIE</name>
+                        <description>Not-acknowledge interrupt enable</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCNACKIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCNACKIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBCNTIE</name>
+                        <description>Byte counter interrupt enable</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCBCNTIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBCNTIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCCLTOIE</name>
+                        <description>Clock low timeout interrupt enable</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCCLTOIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCCLTOIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCRXIE1</name>
+                        <description>Receive interrupt enable 1</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIE1_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIE1_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIE1</name>
+                        <description>Transmit interrupt enable 1</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIE1_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIE1_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCRXIE2</name>
+                        <description>Receive interrupt enable 2</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIE2_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIE2_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIE2</name>
+                        <description>Transmit interrupt enable 2</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIE2_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIE2_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCRXIE3</name>
+                        <description>Receive interrupt enable 3</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIE3_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIE3_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIE3</name>
+                        <description>Transmit interrupt enable 3</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIE3_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIE3_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBIT9IE</name>
+                        <description>Bit position 9 interrupt enable</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCBIT9IE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBIT9IE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxIFG</name>
+                  <displayName>IFG</displayName>
+                  <description>eUSCI_Bx Interrupt Flag Register</description>
+                  <addressOffset>0x2C</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000002</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCRXIFG0</name>
+                        <description>eUSCI_B receive interrupt flag 0</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIFG0_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIFG0_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIFG0</name>
+                        <description>eUSCI_B transmit interrupt flag 0</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIFG0_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIFG0_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTTIFG</name>
+                        <description>START condition interrupt flag</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTTIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTTIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTPIFG</name>
+                        <description>STOP condition interrupt flag</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTPIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTPIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCALIFG</name>
+                        <description>Arbitration lost interrupt flag</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCALIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCALIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCNACKIFG</name>
+                        <description>Not-acknowledge received interrupt flag</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCNACKIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCNACKIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBCNTIFG</name>
+                        <description>Byte counter interrupt flag</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCBCNTIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBCNTIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCCLTOIFG</name>
+                        <description>Clock low timeout interrupt flag</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCCLTOIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCCLTOIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCRXIFG1</name>
+                        <description>eUSCI_B receive interrupt flag 1</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIFG1_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIFG1_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIFG1</name>
+                        <description>eUSCI_B transmit interrupt flag 1</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIFG1_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIFG1_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCRXIFG2</name>
+                        <description>eUSCI_B receive interrupt flag 2</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIFG2_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIFG2_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIFG2</name>
+                        <description>eUSCI_B transmit interrupt flag 2</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIFG2_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIFG2_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCRXIFG3</name>
+                        <description>eUSCI_B receive interrupt flag 3</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIFG3_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIFG3_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIFG3</name>
+                        <description>eUSCI_B transmit interrupt flag 3</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIFG3_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIFG3_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBIT9IFG</name>
+                        <description>Bit position 9 interrupt flag</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCBIT9IFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBIT9IFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxIV</name>
+                  <displayName>IV</displayName>
+                  <description>eUSCI_Bx Interrupt Vector Register</description>
+                  <addressOffset>0x2E</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCIV</name>
+                        <description>eUSCI_B interrupt vector value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>UCIV_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>UCIV_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_2</name>
+                                <description>Interrupt Source: Arbitration lost; Interrupt Flag: UCALIFG; Interrupt Priority: Highest</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_4</name>
+                                <description>Interrupt Source: Not acknowledgment; Interrupt Flag: UCNACKIFG</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_6</name>
+                                <description>Interrupt Source: Start condition received; Interrupt Flag: UCSTTIFG</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_8</name>
+                                <description>Interrupt Source: Stop condition received; Interrupt Flag: UCSTPIFG</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_10</name>
+                                <description>Interrupt Source: Slave 3 Data received; Interrupt Flag: UCRXIFG3</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_12</name>
+                                <description>Interrupt Source: Slave 3 Transmit buffer empty; Interrupt Flag: UCTXIFG3</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_14</name>
+                                <description>Interrupt Source: Slave 2 Data received; Interrupt Flag: UCRXIFG2</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_16</name>
+                                <description>Interrupt Source: Slave 2 Transmit buffer empty; Interrupt Flag: UCTXIFG2</description>
+                                <value>16</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_18</name>
+                                <description>Interrupt Source: Slave 1 Data received; Interrupt Flag: UCRXIFG1</description>
+                                <value>18</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_20</name>
+                                <description>Interrupt Source: Slave 1 Transmit buffer empty; Interrupt Flag: UCTXIFG1</description>
+                                <value>20</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_22</name>
+                                <description>Interrupt Source: Data received; Interrupt Flag: UCRXIFG0</description>
+                                <value>22</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_24</name>
+                                <description>Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG0</description>
+                                <value>24</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_26</name>
+                                <description>Interrupt Source: Byte counter zero; Interrupt Flag: UCBCNTIFG</description>
+                                <value>26</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_28</name>
+                                <description>Interrupt Source: Clock low timeout; Interrupt Flag: UCCLTOIFG</description>
+                                <value>28</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_30</name>
+                                <description>Interrupt Source: Nineth bit position; Interrupt Flag: UCBIT9IFG; Priority: Lowest</description>
+                                <value>30</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>EUSCI_B3</name>
+        <version>356.0</version>
+        <description>EUSCI_B3</description>
+        <baseAddress>0x40002C00</baseAddress>
+        <interrupt>
+            <name>EUSCIB3_IRQ</name>
+            <description>EUSCIB3 Interrupt</description>
+            <value>23</value>
+        </interrupt>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x30</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>UCBxCTLW0</name>
+                  <displayName>CTLW0</displayName>
+                  <description>eUSCI_Bx Control Word Register 0</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x000001c1</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCSWRST</name>
+                        <description>Software reset enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSWRST_0</name>
+                                <description>Disabled. eUSCI_B reset released for operation</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSWRST_1</name>
+                                <description>Enabled. eUSCI_B logic held in reset state</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXSTT</name>
+                        <description>Transmit START condition in master mode</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXSTT_0</name>
+                                <description>Do not generate START condition</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXSTT_1</name>
+                                <description>Generate START condition</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXSTP</name>
+                        <description>Transmit STOP condition in master mode</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXSTP_0</name>
+                                <description>No STOP generated</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXSTP_1</name>
+                                <description>Generate STOP</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXNACK</name>
+                        <description>Transmit a NACK</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXNACK_0</name>
+                                <description>Acknowledge normally</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXNACK_1</name>
+                                <description>Generate NACK</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTR</name>
+                        <description>Transmitter/receiver</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTR_0</name>
+                                <description>Receiver</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTR_1</name>
+                                <description>Transmitter</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXACK</name>
+                        <description>Transmit ACK condition in slave mode</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXACK_0</name>
+                                <description>Do not acknowledge the slave address</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXACK_1</name>
+                                <description>Acknowledge the slave address</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSSEL</name>
+                        <description>eUSCI_B clock source select</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSSEL_0</name>
+                                <description>UCLKI</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSSEL_1</name>
+                                <description>ACLK</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSSEL_2</name>
+                                <description>SMCLK</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSSEL_3</name>
+                                <description>SMCLK</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSYNC</name>
+                        <description>Synchronous mode enable</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSYNC_0</name>
+                                <description>Asynchronous mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSYNC_1</name>
+                                <description>Synchronous mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCMODE</name>
+                        <description>eUSCI_B mode</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCMODE_0</name>
+                                <description>3-pin SPI</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMODE_1</name>
+                                <description>4-pin SPI (master or slave enabled if STE = 1)</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMODE_2</name>
+                                <description>4-pin SPI (master or slave enabled if STE = 0)</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMODE_3</name>
+                                <description>I2C mode</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCMST</name>
+                        <description>Master mode select</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCMST_0</name>
+                                <description>Slave mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMST_1</name>
+                                <description>Master mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCMM</name>
+                        <description>Multi-master environment select</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCMM_0</name>
+                                <description>Single master environment. There is no other master in the system. The address compare unit is disabled.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCMM_1</name>
+                                <description>Multi-master environment</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSLA10</name>
+                        <description>Slave addressing mode select</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSLA10_0</name>
+                                <description>Address slave with 7-bit address</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSLA10_1</name>
+                                <description>Address slave with 10-bit address</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCA10</name>
+                        <description>Own addressing mode select</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCA10_0</name>
+                                <description>Own address is a 7-bit address</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCA10_1</name>
+                                <description>Own address is a 10-bit address</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxCTLW1</name>
+                  <displayName>CTLW1</displayName>
+                  <description>eUSCI_Bx Control Word Register 1</description>
+                  <addressOffset>0x2</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000003</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCGLIT</name>
+                        <description>Deglitch time</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCGLIT_0</name>
+                                <description>50 ns</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGLIT_1</name>
+                                <description>25 ns</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGLIT_2</name>
+                                <description>12.5 ns</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGLIT_3</name>
+                                <description>6.25 ns</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCASTP</name>
+                        <description>Automatic STOP condition generation</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCASTP_0</name>
+                                <description>No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCASTP_1</name>
+                                <description>UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCASTP_2</name>
+                                <description>A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSWACK</name>
+                        <description>SW or HW ACK control</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSWACK_0</name>
+                                <description>The address acknowledge of the slave is controlled by the eUSCI_B module</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSWACK_1</name>
+                                <description>The user needs to trigger the sending of the address ACK by issuing UCTXACK</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTPNACK</name>
+                        <description>ACK all master bytes</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTPNACK_0</name>
+                                <description>Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard)</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTPNACK_1</name>
+                                <description>All bytes are acknowledged by the eUSCI_B when configured as master receiver</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCCLTO</name>
+                        <description>Clock low timeout select</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCCLTO_0</name>
+                                <description>Disable clock low timeout counter</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCCLTO_1</name>
+                                <description>135 000 SYSCLK cycles (approximately 28 ms)</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCCLTO_2</name>
+                                <description>150 000 SYSCLK cycles (approximately 31 ms)</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCCLTO_3</name>
+                                <description>165 000 SYSCLK cycles (approximately 34 ms)</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCETXINT</name>
+                        <description>Early UCTXIFG0</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCETXINT_0</name>
+                                <description>UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCETXINT_1</name>
+                                <description>UCTXIFG0 is set for each START condition</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxBRW</name>
+                  <displayName>BRW</displayName>
+                  <description>eUSCI_Bx Baud Rate Control Word Register</description>
+                  <addressOffset>0x6</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCBR</name>
+                        <description>Bit clock prescaler</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxSTATW</name>
+                  <displayName>STATW</displayName>
+                  <description>eUSCI_Bx Status Register</description>
+                  <addressOffset>0x8</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCBBUSY</name>
+                        <description>Bus busy</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>UCBBUSY_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>UCBBUSY_0</name>
+                                <description>Bus inactive</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBBUSY_1</name>
+                                <description>Bus busy</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCGC</name>
+                        <description>General call address received</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>UCGC_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>UCGC_0</name>
+                                <description>No general call address received</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGC_1</name>
+                                <description>General call address received</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSCLLOW</name>
+                        <description>SCL low</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>UCSCLLOW_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>UCSCLLOW_0</name>
+                                <description>SCL is not held low</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSCLLOW_1</name>
+                                <description>SCL is held low</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBCNT</name>
+                        <description>Hardware byte counter value</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxTBCNT</name>
+                  <displayName>TBCNT</displayName>
+                  <description>eUSCI_Bx Byte Counter Threshold Register</description>
+                  <addressOffset>0xA</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCTBCNT</name>
+                        <description>Byte counter threshold value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxRXBUF</name>
+                  <displayName>RXBUF</displayName>
+                  <description>eUSCI_Bx Receive Buffer Register</description>
+                  <addressOffset>0xC</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCRXBUF</name>
+                        <description>Receive data buffer</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxTXBUF</name>
+                  <displayName>TXBUF</displayName>
+                  <description>eUSCI_Bx Transmit Buffer Register</description>
+                  <addressOffset>0xE</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCTXBUF</name>
+                        <description>Transmit data buffer</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxI2COA0</name>
+                  <displayName>I2COA0</displayName>
+                  <description>eUSCI_Bx I2C Own Address 0 Register</description>
+                  <addressOffset>0x14</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>I2COA0</name>
+                        <description>I2C own address</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0xA</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UCOAEN</name>
+                        <description>Own Address enable register</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCOAEN_0</name>
+                                <description>The slave address defined in I2COA0 is disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCOAEN_1</name>
+                                <description>The slave address defined in I2COA0 is enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCGCEN</name>
+                        <description>General call response enable</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCGCEN_0</name>
+                                <description>Do not respond to a general call</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCGCEN_1</name>
+                                <description>Respond to a general call</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxI2COA1</name>
+                  <displayName>I2COA1</displayName>
+                  <description>eUSCI_Bx I2C Own Address 1 Register</description>
+                  <addressOffset>0x16</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>I2COA1</name>
+                        <description>I2C own address</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0xA</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UCOAEN</name>
+                        <description>Own Address enable register</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCOAEN_0</name>
+                                <description>The slave address defined in I2COA1 is disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCOAEN_1</name>
+                                <description>The slave address defined in I2COA1 is enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxI2COA2</name>
+                  <displayName>I2COA2</displayName>
+                  <description>eUSCI_Bx I2C Own Address 2 Register</description>
+                  <addressOffset>0x18</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>I2COA2</name>
+                        <description>I2C own address</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0xA</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UCOAEN</name>
+                        <description>Own Address enable register</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCOAEN_0</name>
+                                <description>The slave address defined in I2COA2 is disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCOAEN_1</name>
+                                <description>The slave address defined in I2COA2 is enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxI2COA3</name>
+                  <displayName>I2COA3</displayName>
+                  <description>eUSCI_Bx I2C Own Address 3 Register</description>
+                  <addressOffset>0x1A</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>I2COA3</name>
+                        <description>I2C own address</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0xA</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UCOAEN</name>
+                        <description>Own Address enable register</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCOAEN_0</name>
+                                <description>The slave address defined in I2COA3 is disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCOAEN_1</name>
+                                <description>The slave address defined in I2COA3 is enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxADDRX</name>
+                  <displayName>ADDRX</displayName>
+                  <description>eUSCI_Bx I2C Received Address Register</description>
+                  <addressOffset>0x1C</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>ADDRX</name>
+                        <description>Received Address Register</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0xA</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxADDMASK</name>
+                  <displayName>ADDMASK</displayName>
+                  <description>eUSCI_Bx I2C Address Mask Register</description>
+                  <addressOffset>0x1E</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x000003ff</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>ADDMASK</name>
+                        <description>Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated.

+Modify only when UCSWRST = 1.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0xA</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxI2CSA</name>
+                  <displayName>I2CSA</displayName>
+                  <description>eUSCI_Bx I2C Slave Address Register</description>
+                  <addressOffset>0x20</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>I2CSA</name>
+                        <description>I2C slave address</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0xA</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxIE</name>
+                  <displayName>IE</displayName>
+                  <description>eUSCI_Bx Interrupt Enable Register</description>
+                  <addressOffset>0x2A</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCRXIE0</name>
+                        <description>Receive interrupt enable 0</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIE0_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIE0_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIE0</name>
+                        <description>Transmit interrupt enable 0</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIE0_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIE0_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTTIE</name>
+                        <description>START condition interrupt enable</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTTIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTTIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTPIE</name>
+                        <description>STOP condition interrupt enable</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTPIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTPIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCALIE</name>
+                        <description>Arbitration lost interrupt enable</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCALIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCALIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCNACKIE</name>
+                        <description>Not-acknowledge interrupt enable</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCNACKIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCNACKIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBCNTIE</name>
+                        <description>Byte counter interrupt enable</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCBCNTIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBCNTIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCCLTOIE</name>
+                        <description>Clock low timeout interrupt enable</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCCLTOIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCCLTOIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCRXIE1</name>
+                        <description>Receive interrupt enable 1</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIE1_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIE1_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIE1</name>
+                        <description>Transmit interrupt enable 1</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIE1_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIE1_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCRXIE2</name>
+                        <description>Receive interrupt enable 2</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIE2_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIE2_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIE2</name>
+                        <description>Transmit interrupt enable 2</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIE2_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIE2_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCRXIE3</name>
+                        <description>Receive interrupt enable 3</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIE3_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIE3_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIE3</name>
+                        <description>Transmit interrupt enable 3</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIE3_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIE3_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBIT9IE</name>
+                        <description>Bit position 9 interrupt enable</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCBIT9IE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBIT9IE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxIFG</name>
+                  <displayName>IFG</displayName>
+                  <description>eUSCI_Bx Interrupt Flag Register</description>
+                  <addressOffset>0x2C</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000002</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCRXIFG0</name>
+                        <description>eUSCI_B receive interrupt flag 0</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIFG0_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIFG0_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIFG0</name>
+                        <description>eUSCI_B transmit interrupt flag 0</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIFG0_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIFG0_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTTIFG</name>
+                        <description>START condition interrupt flag</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTTIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTTIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCSTPIFG</name>
+                        <description>STOP condition interrupt flag</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCSTPIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCSTPIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCALIFG</name>
+                        <description>Arbitration lost interrupt flag</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCALIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCALIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCNACKIFG</name>
+                        <description>Not-acknowledge received interrupt flag</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCNACKIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCNACKIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBCNTIFG</name>
+                        <description>Byte counter interrupt flag</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCBCNTIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBCNTIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCCLTOIFG</name>
+                        <description>Clock low timeout interrupt flag</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCCLTOIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCCLTOIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCRXIFG1</name>
+                        <description>eUSCI_B receive interrupt flag 1</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIFG1_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIFG1_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIFG1</name>
+                        <description>eUSCI_B transmit interrupt flag 1</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIFG1_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIFG1_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCRXIFG2</name>
+                        <description>eUSCI_B receive interrupt flag 2</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIFG2_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIFG2_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIFG2</name>
+                        <description>eUSCI_B transmit interrupt flag 2</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIFG2_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIFG2_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCRXIFG3</name>
+                        <description>eUSCI_B receive interrupt flag 3</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCRXIFG3_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCRXIFG3_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCTXIFG3</name>
+                        <description>eUSCI_B transmit interrupt flag 3</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCTXIFG3_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCTXIFG3_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>UCBIT9IFG</name>
+                        <description>Bit position 9 interrupt flag</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>UCBIT9IFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCBIT9IFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>UCBxIV</name>
+                  <displayName>IV</displayName>
+                  <description>eUSCI_Bx Interrupt Vector Register</description>
+                  <addressOffset>0x2E</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UCIV</name>
+                        <description>eUSCI_B interrupt vector value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>UCIV_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>UCIV_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_2</name>
+                                <description>Interrupt Source: Arbitration lost; Interrupt Flag: UCALIFG; Interrupt Priority: Highest</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_4</name>
+                                <description>Interrupt Source: Not acknowledgment; Interrupt Flag: UCNACKIFG</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_6</name>
+                                <description>Interrupt Source: Start condition received; Interrupt Flag: UCSTTIFG</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_8</name>
+                                <description>Interrupt Source: Stop condition received; Interrupt Flag: UCSTPIFG</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_10</name>
+                                <description>Interrupt Source: Slave 3 Data received; Interrupt Flag: UCRXIFG3</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_12</name>
+                                <description>Interrupt Source: Slave 3 Transmit buffer empty; Interrupt Flag: UCTXIFG3</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_14</name>
+                                <description>Interrupt Source: Slave 2 Data received; Interrupt Flag: UCRXIFG2</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_16</name>
+                                <description>Interrupt Source: Slave 2 Transmit buffer empty; Interrupt Flag: UCTXIFG2</description>
+                                <value>16</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_18</name>
+                                <description>Interrupt Source: Slave 1 Data received; Interrupt Flag: UCRXIFG1</description>
+                                <value>18</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_20</name>
+                                <description>Interrupt Source: Slave 1 Transmit buffer empty; Interrupt Flag: UCTXIFG1</description>
+                                <value>20</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_22</name>
+                                <description>Interrupt Source: Data received; Interrupt Flag: UCRXIFG0</description>
+                                <value>22</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_24</name>
+                                <description>Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG0</description>
+                                <value>24</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_26</name>
+                                <description>Interrupt Source: Byte counter zero; Interrupt Flag: UCBCNTIFG</description>
+                                <value>26</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_28</name>
+                                <description>Interrupt Source: Clock low timeout; Interrupt Flag: UCCLTOIFG</description>
+                                <value>28</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UCIV_30</name>
+                                <description>Interrupt Source: Nineth bit position; Interrupt Flag: UCBIT9IFG; Priority: Lowest</description>
+                                <value>30</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>REF_A</name>
+        <version>356.0</version>
+        <description>REF_A</description>
+        <baseAddress>0x40003000</baseAddress>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0xC</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>REFCTL0</name>
+                  <displayName>CTL0</displayName>
+                  <description>REF Control Register 0</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>REFON</name>
+                        <description>Reference enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>REFON_0</name>
+                                <description>Disables reference if no other reference requests are pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>REFON_1</name>
+                                <description>Enables reference in static mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>REFOUT</name>
+                        <description>Reference output buffer</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>REFOUT_0</name>
+                                <description>Reference output not available externally</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>REFOUT_1</name>
+                                <description>Reference output available externally. If ADC14REFBURST = 0, output is available continuously. If ADC14REFBURST = 1, output is available only during an ADC14 conversion.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>REFTCOFF</name>
+                        <description>Temperature sensor disabled</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>REFTCOFF_0</name>
+                                <description>Temperature sensor enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>REFTCOFF_1</name>
+                                <description>Temperature sensor disabled to save power</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>REFVSEL</name>
+                        <description>Reference voltage level select</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>REFVSEL_0</name>
+                                <description>1.2 V available when reference requested or REFON = 1</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>REFVSEL_1</name>
+                                <description>1.45 V available when reference requested or REFON = 1</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>REFVSEL_3</name>
+                                <description>2.5 V available when reference requested or REFON = 1</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>REFGENOT</name>
+                        <description>Reference generator one-time trigger</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>REFGENOT_0</name>
+                                <description>No trigger</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>REFGENOT_1</name>
+                                <description>Generation of the reference voltage is started by writing 1 or by a hardware trigger</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>REFBGOT</name>
+                        <description>Bandgap and bandgap buffer one-time trigger</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>REFBGOT_0</name>
+                                <description>No trigger</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>REFBGOT_1</name>
+                                <description>Generation of the bandgap voltage is started by writing 1 or by a hardware trigger</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>REFGENACT</name>
+                        <description>Reference generator active</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>REFGENACT_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>REFGENACT_0</name>
+                                <description>Reference generator not active</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>REFGENACT_1</name>
+                                <description>Reference generator active</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>REFBGACT</name>
+                        <description>Reference bandgap active</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>REFBGACT_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>REFBGACT_0</name>
+                                <description>Reference bandgap buffer not active</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>REFBGACT_1</name>
+                                <description>Reference bandgap buffer active</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>REFGENBUSY</name>
+                        <description>Reference generator busy</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>REFGENBUSY_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>REFGENBUSY_0</name>
+                                <description>Reference generator not busy</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>REFGENBUSY_1</name>
+                                <description>Reference generator busy</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>BGMODE</name>
+                        <description>Bandgap mode</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>BGMODE_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>BGMODE_0</name>
+                                <description>Static mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>BGMODE_1</name>
+                                <description>Sampled mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>REFGENRDY</name>
+                        <description>Variable reference voltage ready status</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>REFGENRDY_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>REFGENRDY_0</name>
+                                <description>Reference voltage output is not ready to be used</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>REFGENRDY_1</name>
+                                <description>Reference voltage output is ready to be used</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>REFBGRDY</name>
+                        <description>Buffered bandgap voltage ready status</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>REFBGRDY_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>REFBGRDY_0</name>
+                                <description>Buffered bandgap voltage is not ready to be used</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>REFBGRDY_1</name>
+                                <description>Buffered bandgap voltage is ready to be used</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>COMP_E0</name>
+        <version>356.0</version>
+        <description>COMP_E0</description>
+        <baseAddress>0x40003400</baseAddress>
+        <interrupt>
+            <name>COMP_E0_IRQ</name>
+            <description>COMP_E0 Interrupt</description>
+            <value>6</value>
+        </interrupt>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x10</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>CExCTL0</name>
+                  <displayName>CTL0</displayName>
+                  <description>Comparator Control Register 0</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CEIPSEL</name>
+                        <description>Channel input selected for the V+ terminal</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEIPSEL_0</name>
+                                <description>Channel 0 selected</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPSEL_1</name>
+                                <description>Channel 1 selected</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPSEL_2</name>
+                                <description>Channel 2 selected</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPSEL_3</name>
+                                <description>Channel 3 selected</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPSEL_4</name>
+                                <description>Channel 4 selected</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPSEL_5</name>
+                                <description>Channel 5 selected</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPSEL_6</name>
+                                <description>Channel 6 selected</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPSEL_7</name>
+                                <description>Channel 7 selected</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPSEL_8</name>
+                                <description>Channel 8 selected</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPSEL_9</name>
+                                <description>Channel 9 selected</description>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPSEL_10</name>
+                                <description>Channel 10 selected</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPSEL_11</name>
+                                <description>Channel 11 selected</description>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPSEL_12</name>
+                                <description>Channel 12 selected</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPSEL_13</name>
+                                <description>Channel 13 selected</description>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPSEL_14</name>
+                                <description>Channel 14 selected</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPSEL_15</name>
+                                <description>Channel 15 selected</description>
+                                <value>15</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEIPEN</name>
+                        <description>Channel input enable for the V+ terminal</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEIPEN_0</name>
+                                <description>Selected analog input channel for V+ terminal is disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPEN_1</name>
+                                <description>Selected analog input channel for V+ terminal is enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEIMSEL</name>
+                        <description>Channel input selected for the - terminal</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEIMSEL_0</name>
+                                <description>Channel 0 selected</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMSEL_1</name>
+                                <description>Channel 1 selected</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMSEL_2</name>
+                                <description>Channel 2 selected</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMSEL_3</name>
+                                <description>Channel 3 selected</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMSEL_4</name>
+                                <description>Channel 4 selected</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMSEL_5</name>
+                                <description>Channel 5 selected</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMSEL_6</name>
+                                <description>Channel 6 selected</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMSEL_7</name>
+                                <description>Channel 7 selected</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMSEL_8</name>
+                                <description>Channel 8 selected</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMSEL_9</name>
+                                <description>Channel 9 selected</description>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMSEL_10</name>
+                                <description>Channel 10 selected</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMSEL_11</name>
+                                <description>Channel 11 selected</description>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMSEL_12</name>
+                                <description>Channel 12 selected</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMSEL_13</name>
+                                <description>Channel 13 selected</description>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMSEL_14</name>
+                                <description>Channel 14 selected</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMSEL_15</name>
+                                <description>Channel 15 selected</description>
+                                <value>15</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEIMEN</name>
+                        <description>Channel input enable for the - terminal</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEIMEN_0</name>
+                                <description>Selected analog input channel for V- terminal is disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMEN_1</name>
+                                <description>Selected analog input channel for V- terminal is enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CExCTL1</name>
+                  <displayName>CTL1</displayName>
+                  <description>Comparator Control Register 1</description>
+                  <addressOffset>0x2</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CEOUT</name>
+                        <description>Comparator output value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CEOUTPOL</name>
+                        <description>Comparator output polarity</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEOUTPOL_0</name>
+                                <description>Noninverted</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEOUTPOL_1</name>
+                                <description>Inverted</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEF</name>
+                        <description>Comparator output filter</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEF_0</name>
+                                <description>Comparator output is not filtered</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEF_1</name>
+                                <description>Comparator output is filtered</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEIES</name>
+                        <description>Interrupt edge select for CEIIFG and CEIFG</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEIES_0</name>
+                                <description>Rising edge for CEIFG, falling edge for CEIIFG</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIES_1</name>
+                                <description>Falling edge for CEIFG, rising edge for CEIIFG</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CESHORT</name>
+                        <description>Input short</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CESHORT_0</name>
+                                <description>Inputs not shorted</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CESHORT_1</name>
+                                <description>Inputs shorted</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEEX</name>
+                        <description>Exchange</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CEFDLY</name>
+                        <description>Filter delay</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEFDLY_0</name>
+                                <description>Typical filter delay of TBD (450) ns</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEFDLY_1</name>
+                                <description>Typical filter delay of TBD (900) ns</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEFDLY_2</name>
+                                <description>Typical filter delay of TBD (1800) ns</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEFDLY_3</name>
+                                <description>Typical filter delay of TBD (3600) ns</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPWRMD</name>
+                        <description>Power Mode</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPWRMD_0</name>
+                                <description>High-speed mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPWRMD_1</name>
+                                <description>Normal mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPWRMD_2</name>
+                                <description>Ultra-low power mode</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEON</name>
+                        <description>Comparator On</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEON_0</name>
+                                <description>Off</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEON_1</name>
+                                <description>On</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEMRVL</name>
+                        <description>This bit is valid of CEMRVS is set to 1</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEMRVL_0</name>
+                                <description>VREF0 is selected if CERS = 00, 01, or 10</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEMRVL_1</name>
+                                <description>VREF1 is selected if CERS = 00, 01, or 10</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEMRVS</name>
+                        <description>This bit defines if the comparator output selects between VREF0 or VREF1 if CERS = 00, 01, or 10.</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEMRVS_0</name>
+                                <description>Comparator output state selects between VREF0 or VREF1</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEMRVS_1</name>
+                                <description>CEMRVL selects between VREF0 or VREF1</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CExCTL2</name>
+                  <displayName>CTL2</displayName>
+                  <description>Comparator Control Register 2</description>
+                  <addressOffset>0x4</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CEREF0</name>
+                        <description>Reference resistor tap 0</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x5</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEREF0_0</name>
+                                <description>Reference resistor tap for setting 0.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_1</name>
+                                <description>Reference resistor tap for setting 1.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_2</name>
+                                <description>Reference resistor tap for setting 2.</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_3</name>
+                                <description>Reference resistor tap for setting 3.</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_4</name>
+                                <description>Reference resistor tap for setting 4.</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_5</name>
+                                <description>Reference resistor tap for setting 5.</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_6</name>
+                                <description>Reference resistor tap for setting 6.</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_7</name>
+                                <description>Reference resistor tap for setting 7.</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_8</name>
+                                <description>Reference resistor tap for setting 8.</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_9</name>
+                                <description>Reference resistor tap for setting 9.</description>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_10</name>
+                                <description>Reference resistor tap for setting 10.</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_11</name>
+                                <description>Reference resistor tap for setting 11.</description>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_12</name>
+                                <description>Reference resistor tap for setting 12.</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_13</name>
+                                <description>Reference resistor tap for setting 13.</description>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_14</name>
+                                <description>Reference resistor tap for setting 14.</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_15</name>
+                                <description>Reference resistor tap for setting 15.</description>
+                                <value>15</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_16</name>
+                                <description>Reference resistor tap for setting 16.</description>
+                                <value>16</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_17</name>
+                                <description>Reference resistor tap for setting 17.</description>
+                                <value>17</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_18</name>
+                                <description>Reference resistor tap for setting 18.</description>
+                                <value>18</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_19</name>
+                                <description>Reference resistor tap for setting 19.</description>
+                                <value>19</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_20</name>
+                                <description>Reference resistor tap for setting 20.</description>
+                                <value>20</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_21</name>
+                                <description>Reference resistor tap for setting 21.</description>
+                                <value>21</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_22</name>
+                                <description>Reference resistor tap for setting 22.</description>
+                                <value>22</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_23</name>
+                                <description>Reference resistor tap for setting 23.</description>
+                                <value>23</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_24</name>
+                                <description>Reference resistor tap for setting 24.</description>
+                                <value>24</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_25</name>
+                                <description>Reference resistor tap for setting 25.</description>
+                                <value>25</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_26</name>
+                                <description>Reference resistor tap for setting 26.</description>
+                                <value>26</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_27</name>
+                                <description>Reference resistor tap for setting 27.</description>
+                                <value>27</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_28</name>
+                                <description>Reference resistor tap for setting 28.</description>
+                                <value>28</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_29</name>
+                                <description>Reference resistor tap for setting 29.</description>
+                                <value>29</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_30</name>
+                                <description>Reference resistor tap for setting 30.</description>
+                                <value>30</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_31</name>
+                                <description>Reference resistor tap for setting 31.</description>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CERSEL</name>
+                        <description>Reference select</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CERSEL_0</name>
+                                <description>When CEEX = 0, VREF is applied to the V+ terminal; When CEEX = 1, VREF is applied to the V- terminal</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CERSEL_1</name>
+                                <description>When CEEX = 0, VREF is applied to the V- terminal; When CEEX = 1, VREF is applied to the V+ terminal</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CERS</name>
+                        <description>Reference source</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CERS_0</name>
+                                <description>No current is drawn by the reference circuitry</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CERS_1</name>
+                                <description>VCC applied to the resistor ladder</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CERS_2</name>
+                                <description>Shared reference voltage applied to the resistor ladder</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CERS_3</name>
+                                <description>Shared reference voltage supplied to V(CREF). Resistor ladder is off</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEREF1</name>
+                        <description>Reference resistor tap 1</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x5</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEREF1_0</name>
+                                <description>Reference resistor tap for setting 0.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_1</name>
+                                <description>Reference resistor tap for setting 1.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_2</name>
+                                <description>Reference resistor tap for setting 2.</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_3</name>
+                                <description>Reference resistor tap for setting 3.</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_4</name>
+                                <description>Reference resistor tap for setting 4.</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_5</name>
+                                <description>Reference resistor tap for setting 5.</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_6</name>
+                                <description>Reference resistor tap for setting 6.</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_7</name>
+                                <description>Reference resistor tap for setting 7.</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_8</name>
+                                <description>Reference resistor tap for setting 8.</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_9</name>
+                                <description>Reference resistor tap for setting 9.</description>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_10</name>
+                                <description>Reference resistor tap for setting 10.</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_11</name>
+                                <description>Reference resistor tap for setting 11.</description>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_12</name>
+                                <description>Reference resistor tap for setting 12.</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_13</name>
+                                <description>Reference resistor tap for setting 13.</description>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_14</name>
+                                <description>Reference resistor tap for setting 14.</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_15</name>
+                                <description>Reference resistor tap for setting 15.</description>
+                                <value>15</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_16</name>
+                                <description>Reference resistor tap for setting 16.</description>
+                                <value>16</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_17</name>
+                                <description>Reference resistor tap for setting 17.</description>
+                                <value>17</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_18</name>
+                                <description>Reference resistor tap for setting 18.</description>
+                                <value>18</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_19</name>
+                                <description>Reference resistor tap for setting 19.</description>
+                                <value>19</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_20</name>
+                                <description>Reference resistor tap for setting 20.</description>
+                                <value>20</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_21</name>
+                                <description>Reference resistor tap for setting 21.</description>
+                                <value>21</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_22</name>
+                                <description>Reference resistor tap for setting 22.</description>
+                                <value>22</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_23</name>
+                                <description>Reference resistor tap for setting 23.</description>
+                                <value>23</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_24</name>
+                                <description>Reference resistor tap for setting 24.</description>
+                                <value>24</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_25</name>
+                                <description>Reference resistor tap for setting 25.</description>
+                                <value>25</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_26</name>
+                                <description>Reference resistor tap for setting 26.</description>
+                                <value>26</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_27</name>
+                                <description>Reference resistor tap for setting 27.</description>
+                                <value>27</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_28</name>
+                                <description>Reference resistor tap for setting 28.</description>
+                                <value>28</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_29</name>
+                                <description>Reference resistor tap for setting 29.</description>
+                                <value>29</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_30</name>
+                                <description>Reference resistor tap for setting 30.</description>
+                                <value>30</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_31</name>
+                                <description>Reference resistor tap for setting 31.</description>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEREFL</name>
+                        <description>Reference voltage level</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEREFL_0</name>
+                                <description>Reference amplifier is disabled. No reference voltage is requested</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREFL_1</name>
+                                <description>1.2 V is selected as shared reference voltage input</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREFL_2</name>
+                                <description>2.0 V is selected as shared reference voltage input</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREFL_3</name>
+                                <description>2.5 V is selected as shared reference voltage input</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEREFACC</name>
+                        <description>Reference accuracy</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEREFACC_0</name>
+                                <description>Static mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREFACC_1</name>
+                                <description>Clocked (low power, low accuracy) mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CExCTL3</name>
+                  <displayName>CTL3</displayName>
+                  <description>Comparator Control Register 3</description>
+                  <addressOffset>0x6</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CEPD0</name>
+                        <description>Port disable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD0_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD0_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPD1</name>
+                        <description>Port disable</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD1_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD1_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPD2</name>
+                        <description>Port disable</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD2_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD2_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPD3</name>
+                        <description>Port disable</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD3_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD3_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPD4</name>
+                        <description>Port disable</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD4_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD4_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPD5</name>
+                        <description>Port disable</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD5_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD5_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPD6</name>
+                        <description>Port disable</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD6_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD6_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPD7</name>
+                        <description>Port disable</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD7_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD7_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPD8</name>
+                        <description>Port disable</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD8_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD8_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPD9</name>
+                        <description>Port disable</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD9_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD9_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPD10</name>
+                        <description>Port disable</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD10_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD10_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPD11</name>
+                        <description>Port disable</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD11_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD11_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPD12</name>
+                        <description>Port disable</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD12_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD12_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPD13</name>
+                        <description>Port disable</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD13_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD13_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPD14</name>
+                        <description>Port disable</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD14_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD14_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPD15</name>
+                        <description>Port disable</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD15_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD15_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CExINT</name>
+                  <displayName>INT</displayName>
+                  <description>Comparator Interrupt Control Register</description>
+                  <addressOffset>0xC</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CEIFG</name>
+                        <description>Comparator output interrupt flag</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEIIFG</name>
+                        <description>Comparator output inverted interrupt flag</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEIIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CERDYIFG</name>
+                        <description>Comparator ready interrupt flag</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CERDYIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CERDYIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEIE</name>
+                        <description>Comparator output interrupt enable</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEIIE</name>
+                        <description>Comparator output interrupt enable inverted polarity</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEIIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CERDYIE</name>
+                        <description>Comparator ready interrupt enable</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CERDYIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CERDYIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CExIV</name>
+                  <displayName>IV</displayName>
+                  <description>Comparator Interrupt Vector Word Register</description>
+                  <addressOffset>0xE</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CEIV</name>
+                        <description>Comparator interrupt vector word register</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>CEIV_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>CEIV_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIV_2</name>
+                                <description>Interrupt Source: CEOUT interrupt; Interrupt Flag: CEIFG; Interrupt Priority: Highest</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIV_4</name>
+                                <description>Interrupt Source: CEOUT interrupt inverted polarity; Interrupt Flag: CEIIFG</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIV_10</name>
+                                <description>Interrupt Source: Comparator ready interrupt; Interrupt Flag: CERDYIFG; Interrupt Priority: Lowest</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>COMP_E1</name>
+        <version>356.0</version>
+        <description>COMP_E1</description>
+        <baseAddress>0x40003800</baseAddress>
+        <interrupt>
+            <name>COMP_E1_IRQ</name>
+            <description>COMP_E1 Interrupt</description>
+            <value>7</value>
+        </interrupt>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x10</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>CExCTL0</name>
+                  <displayName>CTL0</displayName>
+                  <description>Comparator Control Register 0</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CEIPSEL</name>
+                        <description>Channel input selected for the V+ terminal</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEIPSEL_0</name>
+                                <description>Channel 0 selected</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPSEL_1</name>
+                                <description>Channel 1 selected</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPSEL_2</name>
+                                <description>Channel 2 selected</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPSEL_3</name>
+                                <description>Channel 3 selected</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPSEL_4</name>
+                                <description>Channel 4 selected</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPSEL_5</name>
+                                <description>Channel 5 selected</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPSEL_6</name>
+                                <description>Channel 6 selected</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPSEL_7</name>
+                                <description>Channel 7 selected</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPSEL_8</name>
+                                <description>Channel 8 selected</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPSEL_9</name>
+                                <description>Channel 9 selected</description>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPSEL_10</name>
+                                <description>Channel 10 selected</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPSEL_11</name>
+                                <description>Channel 11 selected</description>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPSEL_12</name>
+                                <description>Channel 12 selected</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPSEL_13</name>
+                                <description>Channel 13 selected</description>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPSEL_14</name>
+                                <description>Channel 14 selected</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPSEL_15</name>
+                                <description>Channel 15 selected</description>
+                                <value>15</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEIPEN</name>
+                        <description>Channel input enable for the V+ terminal</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEIPEN_0</name>
+                                <description>Selected analog input channel for V+ terminal is disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIPEN_1</name>
+                                <description>Selected analog input channel for V+ terminal is enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEIMSEL</name>
+                        <description>Channel input selected for the - terminal</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEIMSEL_0</name>
+                                <description>Channel 0 selected</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMSEL_1</name>
+                                <description>Channel 1 selected</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMSEL_2</name>
+                                <description>Channel 2 selected</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMSEL_3</name>
+                                <description>Channel 3 selected</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMSEL_4</name>
+                                <description>Channel 4 selected</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMSEL_5</name>
+                                <description>Channel 5 selected</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMSEL_6</name>
+                                <description>Channel 6 selected</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMSEL_7</name>
+                                <description>Channel 7 selected</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMSEL_8</name>
+                                <description>Channel 8 selected</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMSEL_9</name>
+                                <description>Channel 9 selected</description>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMSEL_10</name>
+                                <description>Channel 10 selected</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMSEL_11</name>
+                                <description>Channel 11 selected</description>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMSEL_12</name>
+                                <description>Channel 12 selected</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMSEL_13</name>
+                                <description>Channel 13 selected</description>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMSEL_14</name>
+                                <description>Channel 14 selected</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMSEL_15</name>
+                                <description>Channel 15 selected</description>
+                                <value>15</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEIMEN</name>
+                        <description>Channel input enable for the - terminal</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEIMEN_0</name>
+                                <description>Selected analog input channel for V- terminal is disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIMEN_1</name>
+                                <description>Selected analog input channel for V- terminal is enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CExCTL1</name>
+                  <displayName>CTL1</displayName>
+                  <description>Comparator Control Register 1</description>
+                  <addressOffset>0x2</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CEOUT</name>
+                        <description>Comparator output value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CEOUTPOL</name>
+                        <description>Comparator output polarity</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEOUTPOL_0</name>
+                                <description>Noninverted</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEOUTPOL_1</name>
+                                <description>Inverted</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEF</name>
+                        <description>Comparator output filter</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEF_0</name>
+                                <description>Comparator output is not filtered</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEF_1</name>
+                                <description>Comparator output is filtered</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEIES</name>
+                        <description>Interrupt edge select for CEIIFG and CEIFG</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEIES_0</name>
+                                <description>Rising edge for CEIFG, falling edge for CEIIFG</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIES_1</name>
+                                <description>Falling edge for CEIFG, rising edge for CEIIFG</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CESHORT</name>
+                        <description>Input short</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CESHORT_0</name>
+                                <description>Inputs not shorted</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CESHORT_1</name>
+                                <description>Inputs shorted</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEEX</name>
+                        <description>Exchange</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CEFDLY</name>
+                        <description>Filter delay</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEFDLY_0</name>
+                                <description>Typical filter delay of TBD (450) ns</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEFDLY_1</name>
+                                <description>Typical filter delay of TBD (900) ns</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEFDLY_2</name>
+                                <description>Typical filter delay of TBD (1800) ns</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEFDLY_3</name>
+                                <description>Typical filter delay of TBD (3600) ns</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPWRMD</name>
+                        <description>Power Mode</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPWRMD_0</name>
+                                <description>High-speed mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPWRMD_1</name>
+                                <description>Normal mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPWRMD_2</name>
+                                <description>Ultra-low power mode</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEON</name>
+                        <description>Comparator On</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEON_0</name>
+                                <description>Off</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEON_1</name>
+                                <description>On</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEMRVL</name>
+                        <description>This bit is valid of CEMRVS is set to 1</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEMRVL_0</name>
+                                <description>VREF0 is selected if CERS = 00, 01, or 10</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEMRVL_1</name>
+                                <description>VREF1 is selected if CERS = 00, 01, or 10</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEMRVS</name>
+                        <description>This bit defines if the comparator output selects between VREF0 or VREF1 if CERS = 00, 01, or 10.</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEMRVS_0</name>
+                                <description>Comparator output state selects between VREF0 or VREF1</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEMRVS_1</name>
+                                <description>CEMRVL selects between VREF0 or VREF1</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CExCTL2</name>
+                  <displayName>CTL2</displayName>
+                  <description>Comparator Control Register 2</description>
+                  <addressOffset>0x4</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CEREF0</name>
+                        <description>Reference resistor tap 0</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x5</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEREF0_0</name>
+                                <description>Reference resistor tap for setting 0.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_1</name>
+                                <description>Reference resistor tap for setting 1.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_2</name>
+                                <description>Reference resistor tap for setting 2.</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_3</name>
+                                <description>Reference resistor tap for setting 3.</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_4</name>
+                                <description>Reference resistor tap for setting 4.</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_5</name>
+                                <description>Reference resistor tap for setting 5.</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_6</name>
+                                <description>Reference resistor tap for setting 6.</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_7</name>
+                                <description>Reference resistor tap for setting 7.</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_8</name>
+                                <description>Reference resistor tap for setting 8.</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_9</name>
+                                <description>Reference resistor tap for setting 9.</description>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_10</name>
+                                <description>Reference resistor tap for setting 10.</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_11</name>
+                                <description>Reference resistor tap for setting 11.</description>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_12</name>
+                                <description>Reference resistor tap for setting 12.</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_13</name>
+                                <description>Reference resistor tap for setting 13.</description>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_14</name>
+                                <description>Reference resistor tap for setting 14.</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_15</name>
+                                <description>Reference resistor tap for setting 15.</description>
+                                <value>15</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_16</name>
+                                <description>Reference resistor tap for setting 16.</description>
+                                <value>16</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_17</name>
+                                <description>Reference resistor tap for setting 17.</description>
+                                <value>17</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_18</name>
+                                <description>Reference resistor tap for setting 18.</description>
+                                <value>18</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_19</name>
+                                <description>Reference resistor tap for setting 19.</description>
+                                <value>19</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_20</name>
+                                <description>Reference resistor tap for setting 20.</description>
+                                <value>20</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_21</name>
+                                <description>Reference resistor tap for setting 21.</description>
+                                <value>21</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_22</name>
+                                <description>Reference resistor tap for setting 22.</description>
+                                <value>22</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_23</name>
+                                <description>Reference resistor tap for setting 23.</description>
+                                <value>23</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_24</name>
+                                <description>Reference resistor tap for setting 24.</description>
+                                <value>24</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_25</name>
+                                <description>Reference resistor tap for setting 25.</description>
+                                <value>25</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_26</name>
+                                <description>Reference resistor tap for setting 26.</description>
+                                <value>26</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_27</name>
+                                <description>Reference resistor tap for setting 27.</description>
+                                <value>27</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_28</name>
+                                <description>Reference resistor tap for setting 28.</description>
+                                <value>28</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_29</name>
+                                <description>Reference resistor tap for setting 29.</description>
+                                <value>29</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_30</name>
+                                <description>Reference resistor tap for setting 30.</description>
+                                <value>30</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF0_31</name>
+                                <description>Reference resistor tap for setting 31.</description>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CERSEL</name>
+                        <description>Reference select</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CERSEL_0</name>
+                                <description>When CEEX = 0, VREF is applied to the V+ terminal; When CEEX = 1, VREF is applied to the V- terminal</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CERSEL_1</name>
+                                <description>When CEEX = 0, VREF is applied to the V- terminal; When CEEX = 1, VREF is applied to the V+ terminal</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CERS</name>
+                        <description>Reference source</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CERS_0</name>
+                                <description>No current is drawn by the reference circuitry</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CERS_1</name>
+                                <description>VCC applied to the resistor ladder</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CERS_2</name>
+                                <description>Shared reference voltage applied to the resistor ladder</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CERS_3</name>
+                                <description>Shared reference voltage supplied to V(CREF). Resistor ladder is off</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEREF1</name>
+                        <description>Reference resistor tap 1</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x5</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEREF1_0</name>
+                                <description>Reference resistor tap for setting 0.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_1</name>
+                                <description>Reference resistor tap for setting 1.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_2</name>
+                                <description>Reference resistor tap for setting 2.</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_3</name>
+                                <description>Reference resistor tap for setting 3.</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_4</name>
+                                <description>Reference resistor tap for setting 4.</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_5</name>
+                                <description>Reference resistor tap for setting 5.</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_6</name>
+                                <description>Reference resistor tap for setting 6.</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_7</name>
+                                <description>Reference resistor tap for setting 7.</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_8</name>
+                                <description>Reference resistor tap for setting 8.</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_9</name>
+                                <description>Reference resistor tap for setting 9.</description>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_10</name>
+                                <description>Reference resistor tap for setting 10.</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_11</name>
+                                <description>Reference resistor tap for setting 11.</description>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_12</name>
+                                <description>Reference resistor tap for setting 12.</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_13</name>
+                                <description>Reference resistor tap for setting 13.</description>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_14</name>
+                                <description>Reference resistor tap for setting 14.</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_15</name>
+                                <description>Reference resistor tap for setting 15.</description>
+                                <value>15</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_16</name>
+                                <description>Reference resistor tap for setting 16.</description>
+                                <value>16</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_17</name>
+                                <description>Reference resistor tap for setting 17.</description>
+                                <value>17</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_18</name>
+                                <description>Reference resistor tap for setting 18.</description>
+                                <value>18</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_19</name>
+                                <description>Reference resistor tap for setting 19.</description>
+                                <value>19</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_20</name>
+                                <description>Reference resistor tap for setting 20.</description>
+                                <value>20</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_21</name>
+                                <description>Reference resistor tap for setting 21.</description>
+                                <value>21</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_22</name>
+                                <description>Reference resistor tap for setting 22.</description>
+                                <value>22</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_23</name>
+                                <description>Reference resistor tap for setting 23.</description>
+                                <value>23</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_24</name>
+                                <description>Reference resistor tap for setting 24.</description>
+                                <value>24</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_25</name>
+                                <description>Reference resistor tap for setting 25.</description>
+                                <value>25</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_26</name>
+                                <description>Reference resistor tap for setting 26.</description>
+                                <value>26</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_27</name>
+                                <description>Reference resistor tap for setting 27.</description>
+                                <value>27</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_28</name>
+                                <description>Reference resistor tap for setting 28.</description>
+                                <value>28</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_29</name>
+                                <description>Reference resistor tap for setting 29.</description>
+                                <value>29</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_30</name>
+                                <description>Reference resistor tap for setting 30.</description>
+                                <value>30</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREF1_31</name>
+                                <description>Reference resistor tap for setting 31.</description>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEREFL</name>
+                        <description>Reference voltage level</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEREFL_0</name>
+                                <description>Reference amplifier is disabled. No reference voltage is requested</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREFL_1</name>
+                                <description>1.2 V is selected as shared reference voltage input</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREFL_2</name>
+                                <description>2.0 V is selected as shared reference voltage input</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREFL_3</name>
+                                <description>2.5 V is selected as shared reference voltage input</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEREFACC</name>
+                        <description>Reference accuracy</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEREFACC_0</name>
+                                <description>Static mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEREFACC_1</name>
+                                <description>Clocked (low power, low accuracy) mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CExCTL3</name>
+                  <displayName>CTL3</displayName>
+                  <description>Comparator Control Register 3</description>
+                  <addressOffset>0x6</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CEPD0</name>
+                        <description>Port disable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD0_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD0_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPD1</name>
+                        <description>Port disable</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD1_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD1_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPD2</name>
+                        <description>Port disable</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD2_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD2_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPD3</name>
+                        <description>Port disable</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD3_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD3_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPD4</name>
+                        <description>Port disable</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD4_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD4_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPD5</name>
+                        <description>Port disable</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD5_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD5_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPD6</name>
+                        <description>Port disable</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD6_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD6_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPD7</name>
+                        <description>Port disable</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD7_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD7_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPD8</name>
+                        <description>Port disable</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD8_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD8_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPD9</name>
+                        <description>Port disable</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD9_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD9_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPD10</name>
+                        <description>Port disable</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD10_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD10_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPD11</name>
+                        <description>Port disable</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD11_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD11_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPD12</name>
+                        <description>Port disable</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD12_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD12_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPD13</name>
+                        <description>Port disable</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD13_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD13_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPD14</name>
+                        <description>Port disable</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD14_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD14_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEPD15</name>
+                        <description>Port disable</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEPD15_0</name>
+                                <description>The input buffer is enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEPD15_1</name>
+                                <description>The input buffer is disabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CExINT</name>
+                  <displayName>INT</displayName>
+                  <description>Comparator Interrupt Control Register</description>
+                  <addressOffset>0xC</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CEIFG</name>
+                        <description>Comparator output interrupt flag</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEIIFG</name>
+                        <description>Comparator output inverted interrupt flag</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEIIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CERDYIFG</name>
+                        <description>Comparator ready interrupt flag</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CERDYIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CERDYIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEIE</name>
+                        <description>Comparator output interrupt enable</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CEIIE</name>
+                        <description>Comparator output interrupt enable inverted polarity</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CEIIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CERDYIE</name>
+                        <description>Comparator ready interrupt enable</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CERDYIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CERDYIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CExIV</name>
+                  <displayName>IV</displayName>
+                  <description>Comparator Interrupt Vector Word Register</description>
+                  <addressOffset>0xE</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CEIV</name>
+                        <description>Comparator interrupt vector word register</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>CEIV_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>CEIV_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIV_2</name>
+                                <description>Interrupt Source: CEOUT interrupt; Interrupt Flag: CEIFG; Interrupt Priority: Highest</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIV_4</name>
+                                <description>Interrupt Source: CEOUT interrupt inverted polarity; Interrupt Flag: CEIIFG</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CEIV_10</name>
+                                <description>Interrupt Source: Comparator ready interrupt; Interrupt Flag: CERDYIFG; Interrupt Priority: Lowest</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>AES256</name>
+        <version>356.0</version>
+        <description>AES256</description>
+        <baseAddress>0x40003C00</baseAddress>
+        <interrupt>
+            <name>AES256_IRQ</name>
+            <description>AES256 Interrupt</description>
+            <value>28</value>
+        </interrupt>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x10</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>AESACTL0</name>
+                  <displayName>CTL0</displayName>
+                  <description>AES Accelerator Control Register 0</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>AESOPx</name>
+                        <description>AES operation</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>AESOPx_0</name>
+                                <description>Encryption</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>AESOPx_1</name>
+                                <description>Decryption. The provided key is the same key used for encryption</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>AESOPx_2</name>
+                                <description>Generate first round key required for decryption</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>AESOPx_3</name>
+                                <description>Decryption. The provided key is the first round key required for decryption</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AESKLx</name>
+                        <description>AES key length</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>AESKLx_0</name>
+                                <description>AES128. The key size is 128 bit</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>AESKLx_1</name>
+                                <description>AES192. The key size is 192 bit.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>AESKLx_2</name>
+                                <description>AES256. The key size is 256 bit</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AESCMx</name>
+                        <description>AES cipher mode select</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>AESCMx_0</name>
+                                <description>ECB</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>AESCMx_1</name>
+                                <description>CBC</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>AESCMx_2</name>
+                                <description>OFB</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>AESCMx_3</name>
+                                <description>CFB</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AESSWRST</name>
+                        <description>AES software reset</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>AESSWRST_0</name>
+                                <description>No reset</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>AESSWRST_1</name>
+                                <description>Reset AES accelerator module</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AESRDYIFG</name>
+                        <description>AES ready interrupt flag</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>AESRDYIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>AESRDYIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AESERRFG</name>
+                        <description>AES error flag</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>AESERRFG_0</name>
+                                <description>No error</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>AESERRFG_1</name>
+                                <description>Error occurred</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AESRDYIE</name>
+                        <description>AES ready interrupt enable</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>AESRDYIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>AESRDYIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AESCMEN</name>
+                        <description>AES cipher mode enable</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>AESCMEN_0</name>
+                                <description>No DMA triggers are generated</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>AESCMEN_1</name>
+                                <description>DMA ciphermode support operation is enabled and the corresponding DMA triggers are generated</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>AESACTL1</name>
+                  <displayName>CTL1</displayName>
+                  <description>AES Accelerator Control Register 1</description>
+                  <addressOffset>0x2</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>AESBLKCNTx</name>
+                        <description>Cipher Block Counter</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>AESASTAT</name>
+                  <displayName>STAT</displayName>
+                  <description>AES Accelerator Status Register</description>
+                  <addressOffset>0x4</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>AESBUSY</name>
+                        <description>AES accelerator module busy</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>AESBUSY_0</name>
+                                <description>Not busy</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>AESBUSY_1</name>
+                                <description>Busy</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AESKEYWR</name>
+                        <description>All 16 bytes written to AESAKEY</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>AESKEYWR_0</name>
+                                <description>Not all bytes written</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>AESKEYWR_1</name>
+                                <description>All bytes written</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AESDINWR</name>
+                        <description>All 16 bytes written to AESADIN, AESAXDIN or AESAXIN</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>AESDINWR_0</name>
+                                <description>Not all bytes written</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>AESDINWR_1</name>
+                                <description>All bytes written</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AESDOUTRD</name>
+                        <description>All 16 bytes read from AESADOUT</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>AESDOUTRD_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>AESDOUTRD_0</name>
+                                <description>Not all bytes read</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>AESDOUTRD_1</name>
+                                <description>All bytes read</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AESKEYCNTx</name>
+                        <description>Bytes written via AESAKEY for AESKLx=00, half-words written via AESAKEY</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>AESDINCNTx</name>
+                        <description>Bytes written via AESADIN, AESAXDIN or AESAXIN</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>AESDOUTCNTx</name>
+                        <description>Bytes read via AESADOUT</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>AESAKEY</name>
+                  <displayName>KEY</displayName>
+                  <description>AES Accelerator Key Register</description>
+                  <addressOffset>0x6</addressOffset>
+                  <size>16</size>
+                  <access>write-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>AESKEY0x</name>
+                        <description>AES key byte n when AESAKEY is written as half-word</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>AESKEY1x</name>
+                        <description>AES key byte n+1 when AESAKEY is written as half-word</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>AESADIN</name>
+                  <displayName>DIN</displayName>
+                  <description>AES Accelerator Data In Register</description>
+                  <addressOffset>0x8</addressOffset>
+                  <size>16</size>
+                  <access>write-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>AESDIN0x</name>
+                        <description>AES data in byte n when AESADIN is written as half-word</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>AESDIN1x</name>
+                        <description>AES data in byte n+1 when AESADIN is written as half-word</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>AESADOUT</name>
+                  <displayName>DOUT</displayName>
+                  <description>AES Accelerator Data Out Register</description>
+                  <addressOffset>0xA</addressOffset>
+                  <size>16</size>
+                  <access>write-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>AESDOUT0x</name>
+                        <description>AES data out byte n when AESADOUT is read as half-word</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>AESDOUT1x</name>
+                        <description>AES data out byte n+1 when AESADOUT is read as half-word</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>AESAXDIN</name>
+                  <displayName>XDIN</displayName>
+                  <description>AES Accelerator XORed Data In Register</description>
+                  <addressOffset>0xC</addressOffset>
+                  <size>16</size>
+                  <access>write-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>AESXDIN0x</name>
+                        <description>AES data in byte n when AESAXDIN is written as half-word</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>AESXDIN1x</name>
+                        <description>AES data in byte n+1 when AESAXDIN is written as half-word</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>AESAXIN</name>
+                  <displayName>XIN</displayName>
+                  <description>AES Accelerator XORed Data In Register</description>
+                  <addressOffset>0xE</addressOffset>
+                  <size>16</size>
+                  <access>write-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>AESXIN0x</name>
+                        <description>AES data in byte n when AESAXIN is written as half-word</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>AESXIN1x</name>
+                        <description>AES data in byte n+1 when AESAXIN is written as half-word</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>CRC32</name>
+        <version>356.0</version>
+        <description>CRC32</description>
+        <baseAddress>0x40004000</baseAddress>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x20</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>CRC32DI</name>
+                  <displayName>CRC32DI</displayName>
+                  <description>Data Input for CRC32 Signature Computation</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CRC32DI</name>
+                        <description>Data input register</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CRC32DIRB</name>
+                  <displayName>CRC32DIRB</displayName>
+                  <description>Data In Reverse for CRC32 Computation</description>
+                  <addressOffset>0x4</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CRC32DIRB</name>
+                        <description>Data input register reversed</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CRC32INIRES_LO</name>
+                  <displayName>CRC32INIRES_LO</displayName>
+                  <description>CRC32 Initialization and Result, lower 16 bits</description>
+                  <addressOffset>0x8</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CRC32INIRES_LO</name>
+                        <description>CRC32 initialization and result, lower 16 bits</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CRC32INIRES_HI</name>
+                  <displayName>CRC32INIRES_HI</displayName>
+                  <description>CRC32 Initialization and Result, upper 16 bits</description>
+                  <addressOffset>0xA</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CRC32INIRES_HI</name>
+                        <description>CRC32 initialization and result, upper 16 bits</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CRC32RESR_LO</name>
+                  <displayName>CRC32RESR_LO</displayName>
+                  <description>CRC32 Result Reverse, lower 16 bits</description>
+                  <addressOffset>0xC</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x0000ffff</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CRC32RESR_LO</name>
+                        <description>CRC32 reverse result, lower 16 bits</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CRC32RESR_HI</name>
+                  <displayName>CRC32RESR_HI</displayName>
+                  <description>CRC32 Result Reverse, Upper 16 bits</description>
+                  <addressOffset>0xE</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x0000ffff</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CRC32RESR_HI</name>
+                        <description>CRC32 reverse result, upper 16 bits</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CRC16DI</name>
+                  <displayName>CRC16DI</displayName>
+                  <description>Data Input for CRC16 computation</description>
+                  <addressOffset>0x10</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CRC16DI</name>
+                        <description>CRC16 data in</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CRC16DIRB</name>
+                  <displayName>CRC16DIRB</displayName>
+                  <description>CRC16 Data In Reverse</description>
+                  <addressOffset>0x14</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CRC16DIRB</name>
+                        <description>CRC16 data in reverse byte</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CRC16INIRES</name>
+                  <displayName>CRC16INIRES</displayName>
+                  <description>CRC16 Initialization and Result register</description>
+                  <addressOffset>0x18</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x0000ffff</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CRC16INIRES</name>
+                        <description>CRC16 initialization and result</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CRC16RESR</name>
+                  <displayName>CRC16RESR</displayName>
+                  <description>CRC16 Result Reverse</description>
+                  <addressOffset>0x1E</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x0000ffff</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CRC16RESR</name>
+                        <description>CRC16 reverse result</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>RTC_C</name>
+        <version>356.0</version>
+        <description>RTC_C</description>
+        <baseAddress>0x40004400</baseAddress>
+        <interrupt>
+            <name>RTC_C_IRQ</name>
+            <description>RTC_C Interrupt</description>
+            <value>29</value>
+        </interrupt>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x20</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>RTCCTL0</name>
+                  <displayName>CTL0</displayName>
+                  <description>RTCCTL0 Register</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00009608</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>RTCRDYIFG</name>
+                        <description>Real-time clock ready interrupt flag</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RTCRDYIFG_0</name>
+                                <description>RTC cannot be read safely</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RTCRDYIFG_1</name>
+                                <description>RTC can be read safely</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RTCAIFG</name>
+                        <description>Real-time clock alarm interrupt flag</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RTCAIFG_0</name>
+                                <description>No time event occurred</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RTCAIFG_1</name>
+                                <description>Time event occurred</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RTCTEVIFG</name>
+                        <description>Real-time clock time event interrupt flag</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RTCTEVIFG_0</name>
+                                <description>No time event occurred</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RTCTEVIFG_1</name>
+                                <description>Time event occurred</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RTCOFIFG</name>
+                        <description>32-kHz crystal oscillator fault interrupt flag</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RTCOFIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RTCOFIFG_1</name>
+                                <description>Interrupt pending. A 32-kHz crystal oscillator fault occurred after last reset.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RTCRDYIE</name>
+                        <description>Real-time clock ready interrupt enable</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RTCRDYIE_0</name>
+                                <description>Interrupt not enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RTCRDYIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RTCAIE</name>
+                        <description>Real-time clock alarm interrupt enable</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RTCAIE_0</name>
+                                <description>Interrupt not enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RTCAIE_1</name>
+                                <description>Interrupt enabled (LPM3/LPM3.5 wake-up enabled)</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RTCTEVIE</name>
+                        <description>Real-time clock time event interrupt enable</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RTCTEVIE_0</name>
+                                <description>Interrupt not enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RTCTEVIE_1</name>
+                                <description>Interrupt enabled (LPM3/LPM3.5 wake-up enabled)</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RTCOFIE</name>
+                        <description>32-kHz crystal oscillator fault interrupt enable</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RTCOFIE_0</name>
+                                <description>Interrupt not enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RTCOFIE_1</name>
+                                <description>Interrupt enabled (LPM3/LPM3.5 wake-up enabled)</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RTCKEY</name>
+                        <description>Real-time clock key</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>RTCCTL13</name>
+                  <displayName>CTL13</displayName>
+                  <description>RTCCTL13 Register</description>
+                  <addressOffset>0x2</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000070</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>RTCTEV</name>
+                        <description>Real-time clock time event</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RTCTEV_0</name>
+                                <description>Minute changed</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RTCTEV_1</name>
+                                <description>Hour changed</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RTCTEV_2</name>
+                                <description>Every day at midnight (00:00)</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RTCTEV_3</name>
+                                <description>Every day at noon (12:00)</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RTCSSEL</name>
+                        <description>Real-time clock source select</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RTCSSEL_0</name>
+                                <description>BCLK</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RTCRDY</name>
+                        <description>Real-time clock ready</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>RTCRDY_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>RTCRDY_0</name>
+                                <description>RTC time values in transition</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RTCRDY_1</name>
+                                <description>RTC time values safe for reading. This bit indicates when the real-time clock time values are safe for reading.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RTCMODE</name>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>RTCMODE_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>RTCMODE_1</name>
+                                <description>Calendar mode. Always reads a value of 1.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RTCHOLD</name>
+                        <description>Real-time clock hold</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RTCHOLD_0</name>
+                                <description>Real-time clock is operational</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RTCHOLD_1</name>
+                                <description>When set, the calendar is stopped as well as the prescale counters, RT0PS and RT1PS are don't care</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RTCBCD</name>
+                        <description>Real-time clock BCD select</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RTCBCD_0</name>
+                                <description>Binary (hexadecimal) code selected</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RTCBCD_1</name>
+                                <description>Binary coded decimal (BCD) code selected</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RTCCALF</name>
+                        <description>Real-time clock calibration frequency</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RTCCALF_0</name>
+                                <description>No frequency output to RTCCLK pin</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RTCCALF_1</name>
+                                <description>512 Hz</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RTCCALF_2</name>
+                                <description>256 Hz</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RTCCALF_3</name>
+                                <description>1 Hz</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>RTCOCAL</name>
+                  <displayName>OCAL</displayName>
+                  <description>RTCOCAL Register</description>
+                  <addressOffset>0x4</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>RTCOCAL</name>
+                        <description>Real-time clock offset error calibration</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RTCOCALS</name>
+                        <description>Real-time clock offset error calibration sign</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RTCOCALS_0</name>
+                                <description>Down calibration. Frequency adjusted down.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RTCOCALS_1</name>
+                                <description>Up calibration. Frequency adjusted up.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>RTCTCMP</name>
+                  <displayName>TCMP</displayName>
+                  <description>RTCTCMP Register</description>
+                  <addressOffset>0x6</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00004000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>RTCTCMP</name>
+                        <description>Real-time clock temperature compensation</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RTCTCOK</name>
+                        <description>Real-time clock temperature compensation write OK</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>RTCTCOK_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>RTCTCOK_0</name>
+                                <description>Write to RTCTCMPx is unsuccessful</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RTCTCOK_1</name>
+                                <description>Write to RTCTCMPx is successful</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RTCTCRDY</name>
+                        <description>Real-time clock temperature compensation ready</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RTCTCMPS</name>
+                        <description>Real-time clock temperature compensation sign</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RTCTCMPS_0</name>
+                                <description>Down calibration. Frequency adjusted down</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RTCTCMPS_1</name>
+                                <description>Up calibration. Frequency adjusted up</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>RTCPS0CTL</name>
+                  <displayName>PS0CTL</displayName>
+                  <description>Real-Time Clock Prescale Timer 0 Control Register</description>
+                  <addressOffset>0x8</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>RT0PSIFG</name>
+                        <description>Prescale timer 0 interrupt flag</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RT0PSIFG_0</name>
+                                <description>No time event occurred</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RT0PSIFG_1</name>
+                                <description>Time event occurred</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RT0PSIE</name>
+                        <description>Prescale timer 0 interrupt enable</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RT0PSIE_0</name>
+                                <description>Interrupt not enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RT0PSIE_1</name>
+                                <description>Interrupt enabled (LPM3/LPM3.5 wake-up enabled)</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RT0IP</name>
+                        <description>Prescale timer 0 interrupt interval</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RT0IP_0</name>
+                                <description>Divide by 2</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RT0IP_1</name>
+                                <description>Divide by 4</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RT0IP_2</name>
+                                <description>Divide by 8</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RT0IP_3</name>
+                                <description>Divide by 16</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RT0IP_4</name>
+                                <description>Divide by 32</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RT0IP_5</name>
+                                <description>Divide by 64</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RT0IP_6</name>
+                                <description>Divide by 128</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RT0IP_7</name>
+                                <description>Divide by 256</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>RTCPS1CTL</name>
+                  <displayName>PS1CTL</displayName>
+                  <description>Real-Time Clock Prescale Timer 1 Control Register</description>
+                  <addressOffset>0xA</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>RT1PSIFG</name>
+                        <description>Prescale timer 1 interrupt flag</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RT1PSIFG_0</name>
+                                <description>No time event occurred</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RT1PSIFG_1</name>
+                                <description>Time event occurred</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RT1PSIE</name>
+                        <description>Prescale timer 1 interrupt enable</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RT1PSIE_0</name>
+                                <description>Interrupt not enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RT1PSIE_1</name>
+                                <description>Interrupt enabled (LPM3/LPM3.5 wake-up enabled)</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RT1IP</name>
+                        <description>Prescale timer 1 interrupt interval</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RT1IP_0</name>
+                                <description>Divide by 2</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RT1IP_1</name>
+                                <description>Divide by 4</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RT1IP_2</name>
+                                <description>Divide by 8</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RT1IP_3</name>
+                                <description>Divide by 16</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RT1IP_4</name>
+                                <description>Divide by 32</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RT1IP_5</name>
+                                <description>Divide by 64</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RT1IP_6</name>
+                                <description>Divide by 128</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RT1IP_7</name>
+                                <description>Divide by 256</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>RTCPS</name>
+                  <displayName>PS</displayName>
+                  <description>Real-Time Clock Prescale Timer Counter Register</description>
+                  <addressOffset>0xC</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000000</resetMask>
+                  <fields>
+                    <field>
+                        <name>RT0PS</name>
+                        <description>Prescale timer 0 counter value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RT1PS</name>
+                        <description>Prescale timer 1 counter value</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>RTCIV</name>
+                  <displayName>IV</displayName>
+                  <description>Real-Time Clock Interrupt Vector Register</description>
+                  <addressOffset>0xE</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>RTCIV</name>
+                        <description>Real-time clock interrupt vector value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>RTCIV_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>RTCIV_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RTCIV_2</name>
+                                <description>Interrupt Source: RTC oscillator failure; Interrupt Flag: RTCOFIFG; Interrupt Priority: Highest</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RTCIV_4</name>
+                                <description>Interrupt Source: RTC ready; Interrupt Flag: RTCRDYIFG</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RTCIV_6</name>
+                                <description>Interrupt Source: RTC interval timer; Interrupt Flag: RTCTEVIFG</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RTCIV_8</name>
+                                <description>Interrupt Source: RTC user alarm; Interrupt Flag: RTCAIFG</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RTCIV_10</name>
+                                <description>Interrupt Source: RTC prescaler 0; Interrupt Flag: RT0PSIFG</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RTCIV_12</name>
+                                <description>Interrupt Source: RTC prescaler 1; Interrupt Flag: RT1PSIFG</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>RTCTIM0</name>
+                  <displayName>TIM0</displayName>
+                  <description>RTCTIM0 Register  Hexadecimal Format</description>
+                  <addressOffset>0x10</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000c0c0</resetMask>
+                  <fields>
+                    <field>
+                        <name>Seconds</name>
+                        <description>Seconds (0 to 59)</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x6</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>Minutes</name>
+                        <description>Minutes (0 to 59)</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x6</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>RTCTIM1</name>
+                  <displayName>TIM1</displayName>
+                  <description>Real-Time Clock Hour, Day of Week</description>
+                  <addressOffset>0x12</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000f8e0</resetMask>
+                  <fields>
+                    <field>
+                        <name>Hours</name>
+                        <description>Hours (0 to 23)</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x5</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DayofWeek</name>
+                        <description>Day of week (0 to 6)</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>RTCDATE</name>
+                  <displayName>DATE</displayName>
+                  <description>RTCDATE - Hexadecimal Format</description>
+                  <addressOffset>0x14</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000f0e0</resetMask>
+                  <fields>
+                    <field>
+                        <name>Day</name>
+                        <description>Day of month (1 to 28, 29, 30, 31)</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x5</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>Month</name>
+                        <description>Month (1 to 12)</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>RTCYEAR</name>
+                  <displayName>YEAR</displayName>
+                  <description>RTCYEAR Register  Hexadecimal Format</description>
+                  <addressOffset>0x16</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000f000</resetMask>
+                  <fields>
+                    <field>
+                        <name>YearLowByte</name>
+                        <description>Year  low byte. Valid values for Year are 0 to 4095.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>YearHighByte</name>
+                        <description>Year  high byte. Valid values for Year are 0 to 4095.</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>RTCAMINHR</name>
+                  <displayName>AMINHR</displayName>
+                  <description>RTCMINHR - Hexadecimal Format</description>
+                  <addressOffset>0x18</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00006040</resetMask>
+                  <fields>
+                    <field>
+                        <name>Minutes</name>
+                        <description>Minutes (0 to 59)</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x6</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MINAE</name>
+                        <description>Alarm enable</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>Hours</name>
+                        <description>Hours (0 to 23)</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x5</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HOURAE</name>
+                        <description>Alarm enable</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>RTCADOWDAY</name>
+                  <displayName>ADOWDAY</displayName>
+                  <description>RTCADOWDAY - Hexadecimal Format</description>
+                  <addressOffset>0x1A</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00006078</resetMask>
+                  <fields>
+                    <field>
+                        <name>DayofWeek</name>
+                        <description>Day of week (0 to 6)</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOWAE</name>
+                        <description>Alarm enable</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DayofMonth</name>
+                        <description>Day of month (1 to 28, 29, 30, 31)</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x5</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DAYAE</name>
+                        <description>Alarm enable</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>RTCBIN2BCD</name>
+                  <displayName>BIN2BCD</displayName>
+                  <description>Binary-to-BCD Conversion Register</description>
+                  <addressOffset>0x1C</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>BIN2BCD</name>
+                        <description>bin to bcd conversion</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>RTCBCD2BIN</name>
+                  <displayName>BCD2BIN</displayName>
+                  <description>BCD-to-Binary Conversion Register</description>
+                  <addressOffset>0x1E</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>BCD2BIN</name>
+                        <description>bcd to bin conversion</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>WDT_A</name>
+        <version>356.0</version>
+        <description>WDT_A</description>
+        <baseAddress>0x40004800</baseAddress>
+        <interrupt>
+            <name>WDT_A_IRQ</name>
+            <description>WDT_A Interrupt</description>
+            <value>3</value>
+        </interrupt>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0xE</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>WDTCTL</name>
+                  <displayName>CTL</displayName>
+                  <description>Watchdog Timer Control Register</description>
+                  <addressOffset>0xC</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00006904</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>WDTIS</name>
+                        <description>Watchdog timer interval select</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>WDTIS_0</name>
+                                <description>Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz)</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WDTIS_1</name>
+                                <description>Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz)</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WDTIS_2</name>
+                                <description>Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz)</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WDTIS_3</name>
+                                <description>Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz)</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WDTIS_4</name>
+                                <description>Watchdog clock source /(2^(15)) (1 s at 32.768 kHz)</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WDTIS_5</name>
+                                <description>Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz)</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WDTIS_6</name>
+                                <description>Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz)</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WDTIS_7</name>
+                                <description>Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz)</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>WDTCNTCL</name>
+                        <description>Watchdog timer counter clear</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>WDTCNTCL_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>WDTCNTCL_0</name>
+                                <description>No action</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WDTCNTCL_1</name>
+                                <description>WDTCNT = 0000h</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>WDTTMSEL</name>
+                        <description>Watchdog timer mode select</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>WDTTMSEL_0</name>
+                                <description>Watchdog mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WDTTMSEL_1</name>
+                                <description>Interval timer mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>WDTSSEL</name>
+                        <description>Watchdog timer clock source select</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>WDTSSEL_0</name>
+                                <description>SMCLK</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WDTSSEL_1</name>
+                                <description>ACLK</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WDTSSEL_2</name>
+                                <description>VLOCLK</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WDTSSEL_3</name>
+                                <description>BCLK</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>WDTHOLD</name>
+                        <description>Watchdog timer hold</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>WDTHOLD_0</name>
+                                <description>Watchdog timer is not stopped</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WDTHOLD_1</name>
+                                <description>Watchdog timer is stopped</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>WDTPW</name>
+                        <description>Watchdog timer password</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>DIO</name>
+        <version>356.0</version>
+        <description>DIO</description>
+        <baseAddress>0x40004C00</baseAddress>
+        <interrupt>
+            <name>PORT1_IRQ</name>
+            <description>Port1 Interrupt</description>
+            <value>35</value>
+        </interrupt>
+        <interrupt>
+            <name>PORT2_IRQ</name>
+            <description>Port2 Interrupt</description>
+            <value>36</value>
+        </interrupt>
+        <interrupt>
+            <name>PORT3_IRQ</name>
+            <description>Port3 Interrupt</description>
+            <value>37</value>
+        </interrupt>
+        <interrupt>
+            <name>PORT4_IRQ</name>
+            <description>Port4 Interrupt</description>
+            <value>38</value>
+        </interrupt>
+        <interrupt>
+            <name>PORT5_IRQ</name>
+            <description>Port5 Interrupt</description>
+            <value>39</value>
+        </interrupt>
+        <interrupt>
+            <name>PORT6_IRQ</name>
+            <description>Port6 Interrupt</description>
+            <value>40</value>
+        </interrupt>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x138</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>PAIN</name>
+                  <displayName>PAIN</displayName>
+                  <description>Port A Input</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000000</resetMask>
+                  <fields>
+                    <field>
+                        <name>P1IN</name>
+                        <description>Port 1 Input</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>P2IN</name>
+                        <description>Port 2 Input</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PAOUT</name>
+                  <displayName>PAOUT</displayName>
+                  <description>Port A Output</description>
+                  <addressOffset>0x2</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000000</resetMask>
+                  <fields>
+                    <field>
+                        <name>P2OUT</name>
+                        <description>Port 2 Output</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P1OUT</name>
+                        <description>Port 1 Output</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PADIR</name>
+                  <displayName>PADIR</displayName>
+                  <description>Port A Direction</description>
+                  <addressOffset>0x4</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P1DIR</name>
+                        <description>Port 1 Direction</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P2DIR</name>
+                        <description>Port 2 Direction</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PAREN</name>
+                  <displayName>PAREN</displayName>
+                  <description>Port A Resistor Enable</description>
+                  <addressOffset>0x6</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P1REN</name>
+                        <description>Port 1 Resistor Enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P2REN</name>
+                        <description>Port 2 Resistor Enable</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PADS</name>
+                  <displayName>PADS</displayName>
+                  <description>Port A Drive Strength</description>
+                  <addressOffset>0x8</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>P1DS</name>
+                        <description>Port 1 Drive Strength</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P2DS</name>
+                        <description>Port 2 Drive Strength</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PASEL0</name>
+                  <displayName>PASEL0</displayName>
+                  <description>Port A Select 0</description>
+                  <addressOffset>0xA</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P1SEL0</name>
+                        <description>Port 1 Select 0</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P2SEL0</name>
+                        <description>Port 2 Select 0</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PASEL1</name>
+                  <displayName>PASEL1</displayName>
+                  <description>Port A Select 1</description>
+                  <addressOffset>0xC</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P1SEL1</name>
+                        <description>Port 1 Select 1</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P2SEL1</name>
+                        <description>Port 2 Select 1</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P1IV</name>
+                  <displayName>P1IV</displayName>
+                  <description>Port 1 Interrupt Vector Register</description>
+                  <addressOffset>0xE</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P1IV</name>
+                        <description>Port 1 interrupt vector value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x5</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>P1IV_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>P1IV_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P1IV_2</name>
+                                <description>Interrupt Source: Port 1.0 interrupt; Interrupt Flag: P1IFG0; Interrupt Priority: Highest</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P1IV_4</name>
+                                <description>Interrupt Source: Port 1.1 interrupt; Interrupt Flag: P1IFG1</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P1IV_6</name>
+                                <description>Interrupt Source: Port 1.2 interrupt; Interrupt Flag: P1IFG2</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P1IV_8</name>
+                                <description>Interrupt Source: Port 1.3 interrupt; Interrupt Flag: P1IFG3</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P1IV_10</name>
+                                <description>Interrupt Source: Port 1.4 interrupt; Interrupt Flag: P1IFG4</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P1IV_12</name>
+                                <description>Interrupt Source: Port 1.5 interrupt; Interrupt Flag: P1IFG5</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P1IV_14</name>
+                                <description>Interrupt Source: Port 1.6 interrupt; Interrupt Flag: P1IFG6</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P1IV_16</name>
+                                <description>Interrupt Source: Port 1.7 interrupt; Interrupt Flag: P1IFG7; Interrupt Priority: Lowest</description>
+                                <value>16</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PASELC</name>
+                  <displayName>PASELC</displayName>
+                  <description>Port A Complement Select</description>
+                  <addressOffset>0x16</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P1SELC</name>
+                        <description>Port 1 Complement Select</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P2SELC</name>
+                        <description>Port 2 Complement Select</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PAIES</name>
+                  <displayName>PAIES</displayName>
+                  <description>Port A Interrupt Edge Select</description>
+                  <addressOffset>0x18</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000000</resetMask>
+                  <fields>
+                    <field>
+                        <name>P1IES</name>
+                        <description>Port 1 Interrupt Edge Select</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P2IES</name>
+                        <description>Port 2 Interrupt Edge Select</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PAIE</name>
+                  <displayName>PAIE</displayName>
+                  <description>Port A Interrupt Enable</description>
+                  <addressOffset>0x1A</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P1IE</name>
+                        <description>Port 1 Interrupt Enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P2IE</name>
+                        <description>Port 2 Interrupt Enable</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PAIFG</name>
+                  <displayName>PAIFG</displayName>
+                  <description>Port A Interrupt Flag</description>
+                  <addressOffset>0x1C</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P1IFG</name>
+                        <description>Port 1 Interrupt Flag</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P2IFG</name>
+                        <description>Port 2 Interrupt Flag</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P2IV</name>
+                  <displayName>P2IV</displayName>
+                  <description>Port 2 Interrupt Vector Register</description>
+                  <addressOffset>0x1E</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <fields>
+                    <field>
+                        <name>P2IV</name>
+                        <description>Port 2 interrupt vector value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x5</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>P2IV_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>P2IV_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P2IV_2</name>
+                                <description>Interrupt Source: Port 2.0 interrupt; Interrupt Flag: P2IFG0; Interrupt Priority: Highest</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P2IV_4</name>
+                                <description>Interrupt Source: Port 2.1 interrupt; Interrupt Flag: P2IFG1</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P2IV_6</name>
+                                <description>Interrupt Source: Port 2.2 interrupt; Interrupt Flag: P2IFG2</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P2IV_8</name>
+                                <description>Interrupt Source: Port 2.3 interrupt; Interrupt Flag: P2IFG3</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P2IV_10</name>
+                                <description>Interrupt Source: Port 2.4 interrupt; Interrupt Flag: P2IFG4</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P2IV_12</name>
+                                <description>Interrupt Source: Port 2.5 interrupt; Interrupt Flag: P2IFG5</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P2IV_14</name>
+                                <description>Interrupt Source: Port 2.6 interrupt; Interrupt Flag: P2IFG6</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P2IV_16</name>
+                                <description>Interrupt Source: Port 2.7 interrupt; Interrupt Flag: P2IFG7; Interrupt Priority: Lowest</description>
+                                <value>16</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PBIN</name>
+                  <displayName>PBIN</displayName>
+                  <description>Port B Input</description>
+                  <addressOffset>0x20</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000000</resetMask>
+                  <fields>
+                    <field>
+                        <name>P3IN</name>
+                        <description>Port 3 Input</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>P4IN</name>
+                        <description>Port 4 Input</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PBOUT</name>
+                  <displayName>PBOUT</displayName>
+                  <description>Port B Output</description>
+                  <addressOffset>0x22</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000000</resetMask>
+                  <fields>
+                    <field>
+                        <name>P3OUT</name>
+                        <description>Port 3 Output</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P4OUT</name>
+                        <description>Port 4 Output</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PBDIR</name>
+                  <displayName>PBDIR</displayName>
+                  <description>Port B Direction</description>
+                  <addressOffset>0x24</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P3DIR</name>
+                        <description>Port 3 Direction</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P4DIR</name>
+                        <description>Port 4 Direction</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PBREN</name>
+                  <displayName>PBREN</displayName>
+                  <description>Port B Resistor Enable</description>
+                  <addressOffset>0x26</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P3REN</name>
+                        <description>Port 3 Resistor Enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P4REN</name>
+                        <description>Port 4 Resistor Enable</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PBDS</name>
+                  <displayName>PBDS</displayName>
+                  <description>Port B Drive Strength</description>
+                  <addressOffset>0x28</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>P3DS</name>
+                        <description>Port 3 Drive Strength</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P4DS</name>
+                        <description>Port 4 Drive Strength</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PBSEL0</name>
+                  <displayName>PBSEL0</displayName>
+                  <description>Port B Select 0</description>
+                  <addressOffset>0x2A</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P4SEL0</name>
+                        <description>Port 4 Select 0</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P3SEL0</name>
+                        <description>Port 3 Select 0</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PBSEL1</name>
+                  <displayName>PBSEL1</displayName>
+                  <description>Port B Select 1</description>
+                  <addressOffset>0x2C</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P3SEL1</name>
+                        <description>Port 3 Select 1</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P4SEL1</name>
+                        <description>Port 4 Select 1</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P3IV</name>
+                  <displayName>P3IV</displayName>
+                  <description>Port 3 Interrupt Vector Register</description>
+                  <addressOffset>0x2E</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P3IV</name>
+                        <description>Port 3 interrupt vector value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x5</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>P3IV_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>P3IV_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P3IV_2</name>
+                                <description>Interrupt Source: Port 3.0 interrupt; Interrupt Flag: P3IFG0; Interrupt Priority: Highest</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P3IV_4</name>
+                                <description>Interrupt Source: Port 3.1 interrupt; Interrupt Flag: P3IFG1</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P3IV_6</name>
+                                <description>Interrupt Source: Port 3.2 interrupt; Interrupt Flag: P3IFG2</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P3IV_8</name>
+                                <description>Interrupt Source: Port 3.3 interrupt; Interrupt Flag: P3IFG3</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P3IV_10</name>
+                                <description>Interrupt Source: Port 3.4 interrupt; Interrupt Flag: P3IFG4</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P3IV_12</name>
+                                <description>Interrupt Source: Port 3.5 interrupt; Interrupt Flag: P3IFG5</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P3IV_14</name>
+                                <description>Interrupt Source: Port 3.6 interrupt; Interrupt Flag: P3IFG6</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P3IV_16</name>
+                                <description>Interrupt Source: Port 3.7 interrupt; Interrupt Flag: P3IFG7; Interrupt Priority: Lowest</description>
+                                <value>16</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PBSELC</name>
+                  <displayName>PBSELC</displayName>
+                  <description>Port B Complement Select</description>
+                  <addressOffset>0x36</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P3SELC</name>
+                        <description>Port 3 Complement Select</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P4SELC</name>
+                        <description>Port 4 Complement Select</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PBIES</name>
+                  <displayName>PBIES</displayName>
+                  <description>Port B Interrupt Edge Select</description>
+                  <addressOffset>0x38</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000000</resetMask>
+                  <fields>
+                    <field>
+                        <name>P3IES</name>
+                        <description>Port 3 Interrupt Edge Select</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P4IES</name>
+                        <description>Port 4 Interrupt Edge Select</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PBIE</name>
+                  <displayName>PBIE</displayName>
+                  <description>Port B Interrupt Enable</description>
+                  <addressOffset>0x3A</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P3IE</name>
+                        <description>Port 3 Interrupt Enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P4IE</name>
+                        <description>Port 4 Interrupt Enable</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PBIFG</name>
+                  <displayName>PBIFG</displayName>
+                  <description>Port B Interrupt Flag</description>
+                  <addressOffset>0x3C</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P3IFG</name>
+                        <description>Port 3 Interrupt Flag</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P4IFG</name>
+                        <description>Port 4 Interrupt Flag</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P4IV</name>
+                  <displayName>P4IV</displayName>
+                  <description>Port 4 Interrupt Vector Register</description>
+                  <addressOffset>0x3E</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <fields>
+                    <field>
+                        <name>P4IV</name>
+                        <description>Port 4 interrupt vector value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x5</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>P4IV_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>P4IV_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P4IV_2</name>
+                                <description>Interrupt Source: Port 4.0 interrupt; Interrupt Flag: P4IFG0; Interrupt Priority: Highest</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P4IV_4</name>
+                                <description>Interrupt Source: Port 4.1 interrupt; Interrupt Flag: P4IFG1</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P4IV_6</name>
+                                <description>Interrupt Source: Port 4.2 interrupt; Interrupt Flag: P4IFG2</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P4IV_8</name>
+                                <description>Interrupt Source: Port 4.3 interrupt; Interrupt Flag: P4IFG3</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P4IV_10</name>
+                                <description>Interrupt Source: Port 4.4 interrupt; Interrupt Flag: P4IFG4</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P4IV_12</name>
+                                <description>Interrupt Source: Port 4.5 interrupt; Interrupt Flag: P4IFG5</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P4IV_14</name>
+                                <description>Interrupt Source: Port 4.6 interrupt; Interrupt Flag: P4IFG6</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P4IV_16</name>
+                                <description>Interrupt Source: Port 4.7 interrupt; Interrupt Flag: P4IFG7; Interrupt Priority: Lowest</description>
+                                <value>16</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PCIN</name>
+                  <displayName>PCIN</displayName>
+                  <description>Port C Input</description>
+                  <addressOffset>0x40</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000000</resetMask>
+                  <fields>
+                    <field>
+                        <name>P5IN</name>
+                        <description>Port 5 Input</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>P6IN</name>
+                        <description>Port 6 Input</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PCOUT</name>
+                  <displayName>PCOUT</displayName>
+                  <description>Port C Output</description>
+                  <addressOffset>0x42</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000000</resetMask>
+                  <fields>
+                    <field>
+                        <name>P5OUT</name>
+                        <description>Port 5 Output</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P6OUT</name>
+                        <description>Port 6 Output</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PCDIR</name>
+                  <displayName>PCDIR</displayName>
+                  <description>Port C Direction</description>
+                  <addressOffset>0x44</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P5DIR</name>
+                        <description>Port 5 Direction</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P6DIR</name>
+                        <description>Port 6 Direction</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PCREN</name>
+                  <displayName>PCREN</displayName>
+                  <description>Port C Resistor Enable</description>
+                  <addressOffset>0x46</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P5REN</name>
+                        <description>Port 5 Resistor Enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P6REN</name>
+                        <description>Port 6 Resistor Enable</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PCDS</name>
+                  <displayName>PCDS</displayName>
+                  <description>Port C Drive Strength</description>
+                  <addressOffset>0x48</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>P5DS</name>
+                        <description>Port 5 Drive Strength</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P6DS</name>
+                        <description>Port 6 Drive Strength</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PCSEL0</name>
+                  <displayName>PCSEL0</displayName>
+                  <description>Port C Select 0</description>
+                  <addressOffset>0x4A</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P5SEL0</name>
+                        <description>Port 5 Select 0</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P6SEL0</name>
+                        <description>Port 6 Select 0</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PCSEL1</name>
+                  <displayName>PCSEL1</displayName>
+                  <description>Port C Select 1</description>
+                  <addressOffset>0x4C</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P5SEL1</name>
+                        <description>Port 5 Select 1</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P6SEL1</name>
+                        <description>Port 6 Select 1</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P5IV</name>
+                  <displayName>P5IV</displayName>
+                  <description>Port 5 Interrupt Vector Register</description>
+                  <addressOffset>0x4E</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P5IV</name>
+                        <description>Port 5 interrupt vector value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x5</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>P5IV_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>P5IV_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P5IV_2</name>
+                                <description>Interrupt Source: Port 5.0 interrupt; Interrupt Flag: P5IFG0; Interrupt Priority: Highest</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P5IV_4</name>
+                                <description>Interrupt Source: Port 5.1 interrupt; Interrupt Flag: P5IFG1</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P5IV_6</name>
+                                <description>Interrupt Source: Port 5.2 interrupt; Interrupt Flag: P5IFG2</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P5IV_8</name>
+                                <description>Interrupt Source: Port 5.3 interrupt; Interrupt Flag: P5IFG3</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P5IV_10</name>
+                                <description>Interrupt Source: Port 5.4 interrupt; Interrupt Flag: P5IFG4</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P5IV_12</name>
+                                <description>Interrupt Source: Port 5.5 interrupt; Interrupt Flag: P5IFG5</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P5IV_14</name>
+                                <description>Interrupt Source: Port 5.6 interrupt; Interrupt Flag: P5IFG6</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P5IV_16</name>
+                                <description>Interrupt Source: Port 5.7 interrupt; Interrupt Flag: P5IFG7; Interrupt Priority: Lowest</description>
+                                <value>16</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PCSELC</name>
+                  <displayName>PCSELC</displayName>
+                  <description>Port C Complement Select</description>
+                  <addressOffset>0x56</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P5SELC</name>
+                        <description>Port 5 Complement Select</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P6SELC</name>
+                        <description>Port 6 Complement Select</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PCIES</name>
+                  <displayName>PCIES</displayName>
+                  <description>Port C Interrupt Edge Select</description>
+                  <addressOffset>0x58</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000000</resetMask>
+                  <fields>
+                    <field>
+                        <name>P5IES</name>
+                        <description>Port 5 Interrupt Edge Select</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P6IES</name>
+                        <description>Port 6 Interrupt Edge Select</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PCIE</name>
+                  <displayName>PCIE</displayName>
+                  <description>Port C Interrupt Enable</description>
+                  <addressOffset>0x5A</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P5IE</name>
+                        <description>Port 5 Interrupt Enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P6IE</name>
+                        <description>Port 6 Interrupt Enable</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PCIFG</name>
+                  <displayName>PCIFG</displayName>
+                  <description>Port C Interrupt Flag</description>
+                  <addressOffset>0x5C</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P5IFG</name>
+                        <description>Port 5 Interrupt Flag</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P6IFG</name>
+                        <description>Port 6 Interrupt Flag</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P6IV</name>
+                  <displayName>P6IV</displayName>
+                  <description>Port 6 Interrupt Vector Register</description>
+                  <addressOffset>0x5E</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <fields>
+                    <field>
+                        <name>P6IV</name>
+                        <description>Port 6 interrupt vector value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x5</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>P6IV_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>P6IV_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P6IV_2</name>
+                                <description>Interrupt Source: Port 6.0 interrupt; Interrupt Flag: P6IFG0; Interrupt Priority: Highest</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P6IV_4</name>
+                                <description>Interrupt Source: Port 6.1 interrupt; Interrupt Flag: P6IFG1</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P6IV_6</name>
+                                <description>Interrupt Source: Port 6.2 interrupt; Interrupt Flag: P6IFG2</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P6IV_8</name>
+                                <description>Interrupt Source: Port 6.3 interrupt; Interrupt Flag: P6IFG3</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P6IV_10</name>
+                                <description>Interrupt Source: Port 6.4 interrupt; Interrupt Flag: P6IFG4</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P6IV_12</name>
+                                <description>Interrupt Source: Port 6.5 interrupt; Interrupt Flag: P6IFG5</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P6IV_14</name>
+                                <description>Interrupt Source: Port 6.6 interrupt; Interrupt Flag: P6IFG6</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P6IV_16</name>
+                                <description>Interrupt Source: Port 6.7 interrupt; Interrupt Flag: P6IFG7; Interrupt Priority: Lowest</description>
+                                <value>16</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PDIN</name>
+                  <displayName>PDIN</displayName>
+                  <description>Port D Input</description>
+                  <addressOffset>0x60</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000000</resetMask>
+                  <fields>
+                    <field>
+                        <name>P7IN</name>
+                        <description>Port 7 Input</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>P8IN</name>
+                        <description>Port 8 Input</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PDOUT</name>
+                  <displayName>PDOUT</displayName>
+                  <description>Port D Output</description>
+                  <addressOffset>0x62</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000000</resetMask>
+                  <fields>
+                    <field>
+                        <name>P7OUT</name>
+                        <description>Port 7 Output</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P8OUT</name>
+                        <description>Port 8 Output</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PDDIR</name>
+                  <displayName>PDDIR</displayName>
+                  <description>Port D Direction</description>
+                  <addressOffset>0x64</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P7DIR</name>
+                        <description>Port 7 Direction</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P8DIR</name>
+                        <description>Port 8 Direction</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PDREN</name>
+                  <displayName>PDREN</displayName>
+                  <description>Port D Resistor Enable</description>
+                  <addressOffset>0x66</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P7REN</name>
+                        <description>Port 7 Resistor Enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P8REN</name>
+                        <description>Port 8 Resistor Enable</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PDDS</name>
+                  <displayName>PDDS</displayName>
+                  <description>Port D Drive Strength</description>
+                  <addressOffset>0x68</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>P7DS</name>
+                        <description>Port 7 Drive Strength</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P8DS</name>
+                        <description>Port 8 Drive Strength</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PDSEL0</name>
+                  <displayName>PDSEL0</displayName>
+                  <description>Port D Select 0</description>
+                  <addressOffset>0x6A</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P7SEL0</name>
+                        <description>Port 7 Select 0</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P8SEL0</name>
+                        <description>Port 8 Select 0</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PDSEL1</name>
+                  <displayName>PDSEL1</displayName>
+                  <description>Port D Select 1</description>
+                  <addressOffset>0x6C</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P7SEL1</name>
+                        <description>Port 7 Select 1</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P8SEL1</name>
+                        <description>Port 8 Select 1</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P7IV</name>
+                  <displayName>P7IV</displayName>
+                  <description>Port 7 Interrupt Vector Register</description>
+                  <addressOffset>0x6E</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P7IV</name>
+                        <description>Port 7 interrupt vector value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x5</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>P7IV_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>P7IV_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P7IV_2</name>
+                                <description>Interrupt Source: Port 7.0 interrupt; Interrupt Flag: P7IFG0; Interrupt Priority: Highest</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P7IV_4</name>
+                                <description>Interrupt Source: Port 7.1 interrupt; Interrupt Flag: P7IFG1</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P7IV_6</name>
+                                <description>Interrupt Source: Port 7.2 interrupt; Interrupt Flag: P7IFG2</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P7IV_8</name>
+                                <description>Interrupt Source: Port 7.3 interrupt; Interrupt Flag: P7IFG3</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P7IV_10</name>
+                                <description>Interrupt Source: Port 7.4 interrupt; Interrupt Flag: P7IFG4</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P7IV_12</name>
+                                <description>Interrupt Source: Port 7.5 interrupt; Interrupt Flag: P7IFG5</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P7IV_14</name>
+                                <description>Interrupt Source: Port 7.6 interrupt; Interrupt Flag: P7IFG6</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P7IV_16</name>
+                                <description>Interrupt Source: Port 7.7 interrupt; Interrupt Flag: P7IFG7; Interrupt Priority: Lowest</description>
+                                <value>16</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PDSELC</name>
+                  <displayName>PDSELC</displayName>
+                  <description>Port D Complement Select</description>
+                  <addressOffset>0x76</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P7SELC</name>
+                        <description>Port 7 Complement Select</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P8SELC</name>
+                        <description>Port 8 Complement Select</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PDIES</name>
+                  <displayName>PDIES</displayName>
+                  <description>Port D Interrupt Edge Select</description>
+                  <addressOffset>0x78</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000000</resetMask>
+                  <fields>
+                    <field>
+                        <name>P7IES</name>
+                        <description>Port 7 Interrupt Edge Select</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P8IES</name>
+                        <description>Port 8 Interrupt Edge Select</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PDIE</name>
+                  <displayName>PDIE</displayName>
+                  <description>Port D Interrupt Enable</description>
+                  <addressOffset>0x7A</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P7IE</name>
+                        <description>Port 7 Interrupt Enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P8IE</name>
+                        <description>Port 8 Interrupt Enable</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PDIFG</name>
+                  <displayName>PDIFG</displayName>
+                  <description>Port D Interrupt Flag</description>
+                  <addressOffset>0x7C</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P7IFG</name>
+                        <description>Port 7 Interrupt Flag</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P8IFG</name>
+                        <description>Port 8 Interrupt Flag</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P8IV</name>
+                  <displayName>P8IV</displayName>
+                  <description>Port 8 Interrupt Vector Register</description>
+                  <addressOffset>0x7E</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <fields>
+                    <field>
+                        <name>P8IV</name>
+                        <description>Port 8 interrupt vector value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x5</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>P8IV_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>P8IV_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P8IV_2</name>
+                                <description>Interrupt Source: Port 8.0 interrupt; Interrupt Flag: P8IFG0; Interrupt Priority: Highest</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P8IV_4</name>
+                                <description>Interrupt Source: Port 8.1 interrupt; Interrupt Flag: P8IFG1</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P8IV_6</name>
+                                <description>Interrupt Source: Port 8.2 interrupt; Interrupt Flag: P8IFG2</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P8IV_8</name>
+                                <description>Interrupt Source: Port 8.3 interrupt; Interrupt Flag: P8IFG3</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P8IV_10</name>
+                                <description>Interrupt Source: Port 8.4 interrupt; Interrupt Flag: P8IFG4</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P8IV_12</name>
+                                <description>Interrupt Source: Port 8.5 interrupt; Interrupt Flag: P8IFG5</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P8IV_14</name>
+                                <description>Interrupt Source: Port 8.6 interrupt; Interrupt Flag: P8IFG6</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P8IV_16</name>
+                                <description>Interrupt Source: Port 8.7 interrupt; Interrupt Flag: P8IFG7; Interrupt Priority: Lowest</description>
+                                <value>16</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PEIN</name>
+                  <displayName>PEIN</displayName>
+                  <description>Port E Input</description>
+                  <addressOffset>0x80</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000000</resetMask>
+                  <fields>
+                    <field>
+                        <name>P9IN</name>
+                        <description>Port 9 Input</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>P10IN</name>
+                        <description>Port 10 Input</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PEOUT</name>
+                  <displayName>PEOUT</displayName>
+                  <description>Port E Output</description>
+                  <addressOffset>0x82</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000000</resetMask>
+                  <fields>
+                    <field>
+                        <name>P9OUT</name>
+                        <description>Port 9 Output</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P10OUT</name>
+                        <description>Port 10 Output</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PEDIR</name>
+                  <displayName>PEDIR</displayName>
+                  <description>Port E Direction</description>
+                  <addressOffset>0x84</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P9DIR</name>
+                        <description>Port 9 Direction</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P10DIR</name>
+                        <description>Port 10 Direction</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PEREN</name>
+                  <displayName>PEREN</displayName>
+                  <description>Port E Resistor Enable</description>
+                  <addressOffset>0x86</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P9REN</name>
+                        <description>Port 9 Resistor Enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P10REN</name>
+                        <description>Port 10 Resistor Enable</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PEDS</name>
+                  <displayName>PEDS</displayName>
+                  <description>Port E Drive Strength</description>
+                  <addressOffset>0x88</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>P9DS</name>
+                        <description>Port 9 Drive Strength</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P10DS</name>
+                        <description>Port 10 Drive Strength</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PESEL0</name>
+                  <displayName>PESEL0</displayName>
+                  <description>Port E Select 0</description>
+                  <addressOffset>0x8A</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P9SEL0</name>
+                        <description>Port 9 Select 0</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P10SEL0</name>
+                        <description>Port 10 Select 0</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PESEL1</name>
+                  <displayName>PESEL1</displayName>
+                  <description>Port E Select 1</description>
+                  <addressOffset>0x8C</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P9SEL1</name>
+                        <description>Port 9 Select 1</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P10SEL1</name>
+                        <description>Port 10 Select 1</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P9IV</name>
+                  <displayName>P9IV</displayName>
+                  <description>Port 9 Interrupt Vector Register</description>
+                  <addressOffset>0x8E</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P9IV</name>
+                        <description>Port 9 interrupt vector value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x5</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>P9IV_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>P9IV_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P9IV_2</name>
+                                <description>Interrupt Source: Port 9.0 interrupt; Interrupt Flag: P9IFG0; Interrupt Priority: Highest</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P9IV_4</name>
+                                <description>Interrupt Source: Port 9.1 interrupt; Interrupt Flag: P9IFG1</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P9IV_6</name>
+                                <description>Interrupt Source: Port 9.2 interrupt; Interrupt Flag: P9IFG2</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P9IV_8</name>
+                                <description>Interrupt Source: Port 9.3 interrupt; Interrupt Flag: P9IFG3</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P9IV_10</name>
+                                <description>Interrupt Source: Port 9.4 interrupt; Interrupt Flag: P9IFG4</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P9IV_12</name>
+                                <description>Interrupt Source: Port 9.5 interrupt; Interrupt Flag: P9IFG5</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P9IV_14</name>
+                                <description>Interrupt Source: Port 9.6 interrupt; Interrupt Flag: P9IFG6</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P9IV_16</name>
+                                <description>Interrupt Source: Port 9.7 interrupt; Interrupt Flag: P9IFG7; Interrupt Priority: Lowest</description>
+                                <value>16</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PESELC</name>
+                  <displayName>PESELC</displayName>
+                  <description>Port E Complement Select</description>
+                  <addressOffset>0x96</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P9SELC</name>
+                        <description>Port 9 Complement Select</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P10SELC</name>
+                        <description>Port 10 Complement Select</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PEIES</name>
+                  <displayName>PEIES</displayName>
+                  <description>Port E Interrupt Edge Select</description>
+                  <addressOffset>0x98</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000000</resetMask>
+                  <fields>
+                    <field>
+                        <name>P9IES</name>
+                        <description>Port 9 Interrupt Edge Select</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P10IES</name>
+                        <description>Port 10 Interrupt Edge Select</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PEIE</name>
+                  <displayName>PEIE</displayName>
+                  <description>Port E Interrupt Enable</description>
+                  <addressOffset>0x9A</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P9IE</name>
+                        <description>Port 9 Interrupt Enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P10IE</name>
+                        <description>Port 10 Interrupt Enable</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PEIFG</name>
+                  <displayName>PEIFG</displayName>
+                  <description>Port E Interrupt Flag</description>
+                  <addressOffset>0x9C</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>P9IFG</name>
+                        <description>Port 9 Interrupt Flag</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P10IFG</name>
+                        <description>Port 10 Interrupt Flag</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P10IV</name>
+                  <displayName>P10IV</displayName>
+                  <description>Port 10 Interrupt Vector Register</description>
+                  <addressOffset>0x9E</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <fields>
+                    <field>
+                        <name>P10IV</name>
+                        <description>Port 10 interrupt vector value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x5</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>P10IV_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>P10IV_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P10IV_2</name>
+                                <description>Interrupt Source: Port 10.0 interrupt; Interrupt Flag: P10IFG0; Interrupt Priority: Highest</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P10IV_4</name>
+                                <description>Interrupt Source: Port 10.1 interrupt; Interrupt Flag: P10IFG1</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P10IV_6</name>
+                                <description>Interrupt Source: Port 10.2 interrupt; Interrupt Flag: P10IFG2</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P10IV_8</name>
+                                <description>Interrupt Source: Port 10.3 interrupt; Interrupt Flag: P10IFG3</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P10IV_10</name>
+                                <description>Interrupt Source: Port 10.4 interrupt; Interrupt Flag: P10IFG4</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P10IV_12</name>
+                                <description>Interrupt Source: Port 10.5 interrupt; Interrupt Flag: P10IFG5</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P10IV_14</name>
+                                <description>Interrupt Source: Port 10.6 interrupt; Interrupt Flag: P10IFG6</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>P10IV_16</name>
+                                <description>Interrupt Source: Port 10.7 interrupt; Interrupt Flag: P10IFG7; Interrupt Priority: Lowest</description>
+                                <value>16</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PJIN</name>
+                  <displayName>PJIN</displayName>
+                  <description>Port J Input</description>
+                  <addressOffset>0x120</addressOffset>
+                  <size>16</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000000</resetMask>
+                  <fields>
+                    <field>
+                        <name>PJIN</name>
+                        <description>Port J Input</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PJOUT</name>
+                  <displayName>PJOUT</displayName>
+                  <description>Port J Output</description>
+                  <addressOffset>0x122</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000000</resetMask>
+                  <fields>
+                    <field>
+                        <name>PJOUT</name>
+                        <description>Port J Output</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PJDIR</name>
+                  <displayName>PJDIR</displayName>
+                  <description>Port J Direction</description>
+                  <addressOffset>0x124</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>PJDIR</name>
+                        <description>Port J Direction</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PJREN</name>
+                  <displayName>PJREN</displayName>
+                  <description>Port J Resistor Enable</description>
+                  <addressOffset>0x126</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>PJREN</name>
+                        <description>Port J Resistor Enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PJDS</name>
+                  <displayName>PJDS</displayName>
+                  <description>Port J Drive Strength</description>
+                  <addressOffset>0x128</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>PJDS</name>
+                        <description>Port J Drive Strength</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PJSEL0</name>
+                  <displayName>PJSEL0</displayName>
+                  <description>Port J Select 0</description>
+                  <addressOffset>0x12A</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>PJSEL0</name>
+                        <description>Port J Select 0</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PJSEL1</name>
+                  <displayName>PJSEL1</displayName>
+                  <description>Port J Select 1</description>
+                  <addressOffset>0x12C</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>PJSEL1</name>
+                        <description>Port J Select 1</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PJSELC</name>
+                  <displayName>PJSELC</displayName>
+                  <description>Port J Complement Select</description>
+                  <addressOffset>0x136</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>PJSELC</name>
+                        <description>Port J Complement Select</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>PMAP</name>
+        <version>356.0</version>
+        <description>PMAP</description>
+        <baseAddress>0x40005000</baseAddress>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x40</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>PMAPKEYID</name>
+                  <displayName>KEYID</displayName>
+                  <description>Port Mapping Key Register</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x000096a5</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>PMAPKEY</name>
+                        <description>Port mapping controller write access key</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PMAPCTL</name>
+                  <displayName>CTL</displayName>
+                  <description>Port Mapping Control Register</description>
+                  <addressOffset>0x2</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000001</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>PMAPLOCKED</name>
+                        <description>Port mapping lock bit</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>PMAPLOCKED_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>PMAPLOCKED_0</name>
+                                <description>Access to mapping registers is granted</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PMAPLOCKED_1</name>
+                                <description>Access to mapping registers is locked</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PMAPRECFG</name>
+                        <description>Port mapping reconfiguration control bit</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PMAPRECFG_0</name>
+                                <description>Configuration allowed only once</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PMAPRECFG_1</name>
+                                <description>Allow reconfiguration of port mapping</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P1MAP01</name>
+                  <displayName>P1MAP01</displayName>
+                  <description>Port mapping register, P1.0 and P1.1</description>
+                  <addressOffset>0x8</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>PMAPx</name>
+                        <description>Selects secondary port function</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P1MAP23</name>
+                  <displayName>P1MAP23</displayName>
+                  <description>Port mapping register, P1.2 and P1.3</description>
+                  <addressOffset>0xA</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>PMAPx</name>
+                        <description>Selects secondary port function</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P1MAP45</name>
+                  <displayName>P1MAP45</displayName>
+                  <description>Port mapping register, P1.4 and P1.5</description>
+                  <addressOffset>0xC</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>PMAPx</name>
+                        <description>Selects secondary port function</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P1MAP67</name>
+                  <displayName>P1MAP67</displayName>
+                  <description>Port mapping register, P1.6 and P1.7</description>
+                  <addressOffset>0xE</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>PMAPx</name>
+                        <description>Selects secondary port function</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P2MAP01</name>
+                  <displayName>P2MAP01</displayName>
+                  <description>Port mapping register, P2.0 and P2.1</description>
+                  <addressOffset>0x10</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>PMAPx</name>
+                        <description>Selects secondary port function</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P2MAP23</name>
+                  <displayName>P2MAP23</displayName>
+                  <description>Port mapping register, P2.2 and P2.3</description>
+                  <addressOffset>0x12</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>PMAPx</name>
+                        <description>Selects secondary port function</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P2MAP45</name>
+                  <displayName>P2MAP45</displayName>
+                  <description>Port mapping register, P2.4 and P2.5</description>
+                  <addressOffset>0x14</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>PMAPx</name>
+                        <description>Selects secondary port function</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P2MAP67</name>
+                  <displayName>P2MAP67</displayName>
+                  <description>Port mapping register, P2.6 and P2.7</description>
+                  <addressOffset>0x16</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>PMAPx</name>
+                        <description>Selects secondary port function</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P3MAP01</name>
+                  <displayName>P3MAP01</displayName>
+                  <description>Port mapping register, P3.0 and P3.1</description>
+                  <addressOffset>0x18</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>PMAPx</name>
+                        <description>Selects secondary port function</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P3MAP23</name>
+                  <displayName>P3MAP23</displayName>
+                  <description>Port mapping register, P3.2 and P3.3</description>
+                  <addressOffset>0x1A</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>PMAPx</name>
+                        <description>Selects secondary port function</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P3MAP45</name>
+                  <displayName>P3MAP45</displayName>
+                  <description>Port mapping register, P3.4 and P3.5</description>
+                  <addressOffset>0x1C</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>PMAPx</name>
+                        <description>Selects secondary port function</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P3MAP67</name>
+                  <displayName>P3MAP67</displayName>
+                  <description>Port mapping register, P3.6 and P3.7</description>
+                  <addressOffset>0x1E</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>PMAPx</name>
+                        <description>Selects secondary port function</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P4MAP01</name>
+                  <displayName>P4MAP01</displayName>
+                  <description>Port mapping register, P4.0 and P4.1</description>
+                  <addressOffset>0x20</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>PMAPx</name>
+                        <description>Selects secondary port function</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P4MAP23</name>
+                  <displayName>P4MAP23</displayName>
+                  <description>Port mapping register, P4.2 and P4.3</description>
+                  <addressOffset>0x22</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>PMAPx</name>
+                        <description>Selects secondary port function</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P4MAP45</name>
+                  <displayName>P4MAP45</displayName>
+                  <description>Port mapping register, P4.4 and P4.5</description>
+                  <addressOffset>0x24</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>PMAPx</name>
+                        <description>Selects secondary port function</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P4MAP67</name>
+                  <displayName>P4MAP67</displayName>
+                  <description>Port mapping register, P4.6 and P4.7</description>
+                  <addressOffset>0x26</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>PMAPx</name>
+                        <description>Selects secondary port function</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P5MAP01</name>
+                  <displayName>P5MAP01</displayName>
+                  <description>Port mapping register, P5.0 and P5.1</description>
+                  <addressOffset>0x28</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>PMAPx</name>
+                        <description>Selects secondary port function</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P5MAP23</name>
+                  <displayName>P5MAP23</displayName>
+                  <description>Port mapping register, P5.2 and P5.3</description>
+                  <addressOffset>0x2A</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>PMAPx</name>
+                        <description>Selects secondary port function</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P5MAP45</name>
+                  <displayName>P5MAP45</displayName>
+                  <description>Port mapping register, P5.4 and P5.5</description>
+                  <addressOffset>0x2C</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>PMAPx</name>
+                        <description>Selects secondary port function</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P5MAP67</name>
+                  <displayName>P5MAP67</displayName>
+                  <description>Port mapping register, P5.6 and P5.7</description>
+                  <addressOffset>0x2E</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>PMAPx</name>
+                        <description>Selects secondary port function</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P6MAP01</name>
+                  <displayName>P6MAP01</displayName>
+                  <description>Port mapping register, P6.0 and P6.1</description>
+                  <addressOffset>0x30</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>PMAPx</name>
+                        <description>Selects secondary port function</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P6MAP23</name>
+                  <displayName>P6MAP23</displayName>
+                  <description>Port mapping register, P6.2 and P6.3</description>
+                  <addressOffset>0x32</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>PMAPx</name>
+                        <description>Selects secondary port function</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P6MAP45</name>
+                  <displayName>P6MAP45</displayName>
+                  <description>Port mapping register, P6.4 and P6.5</description>
+                  <addressOffset>0x34</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>PMAPx</name>
+                        <description>Selects secondary port function</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P6MAP67</name>
+                  <displayName>P6MAP67</displayName>
+                  <description>Port mapping register, P6.6 and P6.7</description>
+                  <addressOffset>0x36</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>PMAPx</name>
+                        <description>Selects secondary port function</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P7MAP01</name>
+                  <displayName>P7MAP01</displayName>
+                  <description>Port mapping register, P7.0 and P7.1</description>
+                  <addressOffset>0x38</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>PMAPx</name>
+                        <description>Selects secondary port function</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P7MAP23</name>
+                  <displayName>P7MAP23</displayName>
+                  <description>Port mapping register, P7.2 and P7.3</description>
+                  <addressOffset>0x3A</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>PMAPx</name>
+                        <description>Selects secondary port function</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P7MAP45</name>
+                  <displayName>P7MAP45</displayName>
+                  <description>Port mapping register, P7.4 and P7.5</description>
+                  <addressOffset>0x3C</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>PMAPx</name>
+                        <description>Selects secondary port function</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>P7MAP67</name>
+                  <displayName>P7MAP67</displayName>
+                  <description>Port mapping register, P7.6 and P7.7</description>
+                  <addressOffset>0x3E</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>PMAPx</name>
+                        <description>Selects secondary port function</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>CAPTIO0</name>
+        <version>356.0</version>
+        <description>CAPTIO0</description>
+        <baseAddress>0x40005400</baseAddress>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x10</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>CAPTIOxCTL</name>
+                  <displayName>CTL</displayName>
+                  <description>Capacitive Touch IO x Control Register</description>
+                  <addressOffset>0xE</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CAPTIOPISELx</name>
+                        <description>Capacitive Touch IO pin select</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CAPTIOPISELx_0</name>
+                                <description>Px.0</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPISELx_1</name>
+                                <description>Px.1</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPISELx_2</name>
+                                <description>Px.2</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPISELx_3</name>
+                                <description>Px.3</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPISELx_4</name>
+                                <description>Px.4</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPISELx_5</name>
+                                <description>Px.5</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPISELx_6</name>
+                                <description>Px.6</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPISELx_7</name>
+                                <description>Px.7</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CAPTIOPOSELx</name>
+                        <description>Capacitive Touch IO port select</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_0</name>
+                                <description>Px = PJ</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_1</name>
+                                <description>Px = P1</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_2</name>
+                                <description>Px = P2</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_3</name>
+                                <description>Px = P3</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_4</name>
+                                <description>Px = P4</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_5</name>
+                                <description>Px = P5</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_6</name>
+                                <description>Px = P6</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_7</name>
+                                <description>Px = P7</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_8</name>
+                                <description>Px = P8</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_9</name>
+                                <description>Px = P9</description>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_10</name>
+                                <description>Px = P10</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_11</name>
+                                <description>Px = P11</description>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_12</name>
+                                <description>Px = P12</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_13</name>
+                                <description>Px = P13</description>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_14</name>
+                                <description>Px = P14</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_15</name>
+                                <description>Px = P15</description>
+                                <value>15</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CAPTIOEN</name>
+                        <description>Capacitive Touch IO enable</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CAPTIOEN_0</name>
+                                <description>All Capacitive Touch IOs are disabled. Signal towards timers is 0.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOEN_1</name>
+                                <description>Selected Capacitive Touch IO is enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CAPTIOSTATE</name>
+                        <description>Capacitive Touch IO state</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>CAPTIOSTATE_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>CAPTIOSTATE_0</name>
+                                <description>Curent state 0 or Capacitive Touch IO is disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOSTATE_1</name>
+                                <description>Current state 1</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>CAPTIO1</name>
+        <version>356.0</version>
+        <description>CAPTIO1</description>
+        <baseAddress>0x40005800</baseAddress>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x10</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>CAPTIOxCTL</name>
+                  <displayName>CTL</displayName>
+                  <description>Capacitive Touch IO x Control Register</description>
+                  <addressOffset>0xE</addressOffset>
+                  <size>16</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0000ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CAPTIOPISELx</name>
+                        <description>Capacitive Touch IO pin select</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CAPTIOPISELx_0</name>
+                                <description>Px.0</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPISELx_1</name>
+                                <description>Px.1</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPISELx_2</name>
+                                <description>Px.2</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPISELx_3</name>
+                                <description>Px.3</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPISELx_4</name>
+                                <description>Px.4</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPISELx_5</name>
+                                <description>Px.5</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPISELx_6</name>
+                                <description>Px.6</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPISELx_7</name>
+                                <description>Px.7</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CAPTIOPOSELx</name>
+                        <description>Capacitive Touch IO port select</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_0</name>
+                                <description>Px = PJ</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_1</name>
+                                <description>Px = P1</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_2</name>
+                                <description>Px = P2</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_3</name>
+                                <description>Px = P3</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_4</name>
+                                <description>Px = P4</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_5</name>
+                                <description>Px = P5</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_6</name>
+                                <description>Px = P6</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_7</name>
+                                <description>Px = P7</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_8</name>
+                                <description>Px = P8</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_9</name>
+                                <description>Px = P9</description>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_10</name>
+                                <description>Px = P10</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_11</name>
+                                <description>Px = P11</description>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_12</name>
+                                <description>Px = P12</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_13</name>
+                                <description>Px = P13</description>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_14</name>
+                                <description>Px = P14</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOPOSELx_15</name>
+                                <description>Px = P15</description>
+                                <value>15</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CAPTIOEN</name>
+                        <description>Capacitive Touch IO enable</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CAPTIOEN_0</name>
+                                <description>All Capacitive Touch IOs are disabled. Signal towards timers is 0.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOEN_1</name>
+                                <description>Selected Capacitive Touch IO is enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CAPTIOSTATE</name>
+                        <description>Capacitive Touch IO state</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>CAPTIOSTATE_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>CAPTIOSTATE_0</name>
+                                <description>Curent state 0 or Capacitive Touch IO is disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CAPTIOSTATE_1</name>
+                                <description>Current state 1</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>TIMER32</name>
+        <version>356.0</version>
+        <description>TIMER32</description>
+        <baseAddress>0x4000C000</baseAddress>
+        <interrupt>
+            <name>T32_INT1_IRQ</name>
+            <description>T32_INT1 Interrupt</description>
+            <value>25</value>
+        </interrupt>
+        <interrupt>
+            <name>T32_INT2_IRQ</name>
+            <description>T32_INT2 Interrupt</description>
+            <value>26</value>
+        </interrupt>
+        <interrupt>
+            <name>T32_INTC_IRQ</name>
+            <description>T32_INTC Interrupt</description>
+            <value>27</value>
+        </interrupt>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0xF0C</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>T32LOAD1</name>
+                  <displayName>LOAD1</displayName>
+                  <description>Timer 1 Load Register</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>LOAD</name>
+                        <description>The value from which the Timer 1 counter decrements</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>T32VALUE1</name>
+                  <displayName>VALUE1</displayName>
+                  <description>Timer 1 Current Value Register</description>
+                  <addressOffset>0x4</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0xffffffff</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>VALUE</name>
+                        <description>Current value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>T32CONTROL1</name>
+                  <displayName>CONTROL1</displayName>
+                  <description>Timer 1 Timer Control Register</description>
+                  <addressOffset>0x8</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000020</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>ONESHOT</name>
+                        <description>Selects one-shot or wrapping counter mode</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ONESHOT_0</name>
+                                <description>wrapping mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ONESHOT_1</name>
+                                <description>one-shot mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SIZE</name>
+                        <description>Selects 16 or 32 bit counter operation</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SIZE_0</name>
+                                <description>16-bit counter</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_1</name>
+                                <description>32-bit counter</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PRESCALE</name>
+                        <description>Prescale bits</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PRESCALE_0</name>
+                                <description>0 stages of prescale, clock is divided by 1</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PRESCALE_1</name>
+                                <description>4 stages of prescale, clock is divided by 16</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PRESCALE_2</name>
+                                <description>8 stages of prescale, clock is divided by 256</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Interrupt enable bit</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>IE_0</name>
+                                <description>Timer interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>IE_1</name>
+                                <description>Timer interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>MODE</name>
+                        <description>Mode bit</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>MODE_0</name>
+                                <description>Timer is in free-running mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>MODE_1</name>
+                                <description>Timer is in periodic mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable bit</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ENABLE_0</name>
+                                <description>Timer disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE_1</name>
+                                <description>Timer enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>T32INTCLR1</name>
+                  <displayName>INTCLR1</displayName>
+                  <description>Timer 1 Interrupt Clear Register</description>
+                  <addressOffset>0xC</addressOffset>
+                  <size>32</size>
+                  <access>write-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000000</resetMask>
+                  <fields>
+                    <field>
+                        <name>INTCLR</name>
+                        <description>Write clears interrupt output</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>T32RIS1</name>
+                  <displayName>RIS1</displayName>
+                  <description>Timer 1 Raw Interrupt Status Register</description>
+                  <addressOffset>0x10</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>RAW_IFG</name>
+                        <description>Raw interrupt status</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>T32MIS1</name>
+                  <displayName>MIS1</displayName>
+                  <description>Timer 1 Interrupt Status Register</description>
+                  <addressOffset>0x14</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>IFG</name>
+                        <description>Enabled interrupt status</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>T32BGLOAD1</name>
+                  <displayName>BGLOAD1</displayName>
+                  <description>Timer 1 Background Load Register</description>
+                  <addressOffset>0x18</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>BGLOAD</name>
+                        <description>Value from which the counter decrements</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>T32LOAD2</name>
+                  <displayName>LOAD2</displayName>
+                  <description>Timer 2 Load Register</description>
+                  <addressOffset>0x20</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>LOAD</name>
+                        <description>The value from which the Timer 2 counter decrements</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>T32VALUE2</name>
+                  <displayName>VALUE2</displayName>
+                  <description>Timer 2 Current Value Register</description>
+                  <addressOffset>0x24</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0xffffffff</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>VALUE</name>
+                        <description>Current value of the decrementing counter</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>T32CONTROL2</name>
+                  <displayName>CONTROL2</displayName>
+                  <description>Timer 2 Timer Control Register</description>
+                  <addressOffset>0x28</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000020</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>ONESHOT</name>
+                        <description>Selects one-shot or wrapping counter mode</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ONESHOT_0</name>
+                                <description>wrapping mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ONESHOT_1</name>
+                                <description>one-shot mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SIZE</name>
+                        <description>Selects 16 or 32 bit counter operation</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SIZE_0</name>
+                                <description>16-bit counter</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_1</name>
+                                <description>32-bit counter</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PRESCALE</name>
+                        <description>Prescale bits</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PRESCALE_0</name>
+                                <description>0 stages of prescale, clock is divided by 1</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PRESCALE_1</name>
+                                <description>4 stages of prescale, clock is divided by 16</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PRESCALE_2</name>
+                                <description>8 stages of prescale, clock is divided by 256</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Interrupt enable bit</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>IE_0</name>
+                                <description>Timer interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>IE_1</name>
+                                <description>Timer interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>MODE</name>
+                        <description>Mode bit</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>MODE_0</name>
+                                <description>Timer is in free-running mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>MODE_1</name>
+                                <description>Timer is in periodic mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable bit</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ENABLE_0</name>
+                                <description>Timer disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE_1</name>
+                                <description>Timer enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>T32INTCLR2</name>
+                  <displayName>INTCLR2</displayName>
+                  <description>Timer 2 Interrupt Clear Register</description>
+                  <addressOffset>0x2C</addressOffset>
+                  <size>32</size>
+                  <access>write-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000000</resetMask>
+                  <fields>
+                    <field>
+                        <name>INTCLR</name>
+                        <description>Write clears the interrupt output</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>T32RIS2</name>
+                  <displayName>RIS2</displayName>
+                  <description>Timer 2 Raw Interrupt Status Register</description>
+                  <addressOffset>0x30</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>RAW_IFG</name>
+                        <description>Raw interrupt status</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>T32MIS2</name>
+                  <displayName>MIS2</displayName>
+                  <description>Timer 2 Interrupt Status Register</description>
+                  <addressOffset>0x34</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>IFG</name>
+                        <description>Enabled interrupt status</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>T32BGLOAD2</name>
+                  <displayName>BGLOAD2</displayName>
+                  <description>Timer 2 Background Load Register</description>
+                  <addressOffset>0x38</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>BGLOAD</name>
+                        <description>Value from which the counter decrements</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>DMA</name>
+        <version>356.0</version>
+        <description>DMA</description>
+        <baseAddress>0x4000E000</baseAddress>
+        <interrupt>
+            <name>DMA_ERR_IRQ</name>
+            <description>DMA_ERR Interrupt</description>
+            <value>30</value>
+        </interrupt>
+        <interrupt>
+            <name>DMA_INT3_IRQ</name>
+            <description>DMA_INT3 Interrupt</description>
+            <value>31</value>
+        </interrupt>
+        <interrupt>
+            <name>DMA_INT2_IRQ</name>
+            <description>DMA_INT2 Interrupt</description>
+            <value>32</value>
+        </interrupt>
+        <interrupt>
+            <name>DMA_INT1_IRQ</name>
+            <description>DMA_INT1 Interrupt</description>
+            <value>33</value>
+        </interrupt>
+        <interrupt>
+            <name>DMA_INT0_IRQ</name>
+            <description>DMA_INT0 Interrupt</description>
+            <value>34</value>
+        </interrupt>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x1050</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>DMA_DEVICE_CFG</name>
+                  <displayName>DEVICE_CFG</displayName>
+                  <description>Device Configuration Status</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffff0000</resetMask>
+                  <fields>
+                    <field>
+                        <name>NUM_DMA_CHANNELS</name>
+                        <description>Number of DMA channels available</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NUM_SRC_PER_CHANNEL</name>
+                        <description>Number of DMA sources per channel</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DMA_SW_CHTRIG</name>
+                  <displayName>SW_CHTRIG</displayName>
+                  <description>Software Channel Trigger Register</description>
+                  <addressOffset>0x4</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CH0</name>
+                        <description>Write 1, triggers DMA_CHANNEL0</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH1</name>
+                        <description>Write 1, triggers DMA_CHANNEL1</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH2</name>
+                        <description>Write 1, triggers DMA_CHANNEL2</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH3</name>
+                        <description>Write 1, triggers DMA_CHANNEL3</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH4</name>
+                        <description>Write 1, triggers DMA_CHANNEL4</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH5</name>
+                        <description>Write 1, triggers DMA_CHANNEL5</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH6</name>
+                        <description>Write 1, triggers DMA_CHANNEL6</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH7</name>
+                        <description>Write 1, triggers DMA_CHANNEL7</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH8</name>
+                        <description>Write 1, triggers DMA_CHANNEL8</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH9</name>
+                        <description>Write 1, triggers DMA_CHANNEL9</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH10</name>
+                        <description>Write 1, triggers DMA_CHANNEL10</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH11</name>
+                        <description>Write 1, triggers DMA_CHANNEL11</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH12</name>
+                        <description>Write 1, triggers DMA_CHANNEL12</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH13</name>
+                        <description>Write 1, triggers DMA_CHANNEL13</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH14</name>
+                        <description>Write 1, triggers DMA_CHANNEL14</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH15</name>
+                        <description>Write 1, triggers DMA_CHANNEL15</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH16</name>
+                        <description>Write 1, triggers DMA_CHANNEL16</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH17</name>
+                        <description>Write 1, triggers DMA_CHANNEL17</description>
+                        <bitOffset>0x11</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH18</name>
+                        <description>Write 1, triggers DMA_CHANNEL18</description>
+                        <bitOffset>0x12</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH19</name>
+                        <description>Write 1, triggers DMA_CHANNEL19</description>
+                        <bitOffset>0x13</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH20</name>
+                        <description>Write 1, triggers DMA_CHANNEL20</description>
+                        <bitOffset>0x14</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH21</name>
+                        <description>Write 1, triggers DMA_CHANNEL21</description>
+                        <bitOffset>0x15</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH22</name>
+                        <description>Write 1, triggers DMA_CHANNEL22</description>
+                        <bitOffset>0x16</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH23</name>
+                        <description>Write 1, triggers DMA_CHANNEL23</description>
+                        <bitOffset>0x17</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH24</name>
+                        <description>Write 1, triggers DMA_CHANNEL24</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH25</name>
+                        <description>Write 1, triggers DMA_CHANNEL25</description>
+                        <bitOffset>0x19</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH26</name>
+                        <description>Write 1, triggers DMA_CHANNEL26</description>
+                        <bitOffset>0x1A</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH27</name>
+                        <description>Write 1, triggers DMA_CHANNEL27</description>
+                        <bitOffset>0x1B</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH28</name>
+                        <description>Write 1, triggers DMA_CHANNEL28</description>
+                        <bitOffset>0x1C</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH29</name>
+                        <description>Write 1, triggers DMA_CHANNEL29</description>
+                        <bitOffset>0x1D</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH30</name>
+                        <description>Write 1, triggers DMA_CHANNEL30</description>
+                        <bitOffset>0x1E</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH31</name>
+                        <description>Write 1, triggers DMA_CHANNEL31</description>
+                        <bitOffset>0x1F</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <dim>32</dim>
+                  <dimIncrement>4</dimIncrement>
+                  <dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31</dimIndex>
+                  <name>DMA_CH_SRCCFG[%s]</name>
+                  <displayName>CH_SRCCFG[%s]</displayName>
+                  <description>Channel n Source Configuration Register</description>
+                  <addressOffset>0x10</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>DMA_SRC</name>
+                        <description>Device level DMA source mapping to channel input</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DMA_INT1_SRCCFG</name>
+                  <displayName>INT1_SRCCFG</displayName>
+                  <description>Interrupt 1 Source Channel Configuration</description>
+                  <addressOffset>0x100</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>INT_SRC</name>
+                        <description>Controls which channel's completion event is mapped as a source of this Interrupt</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x5</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Enables DMA_INT1 mapping</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DMA_INT2_SRCCFG</name>
+                  <displayName>INT2_SRCCFG</displayName>
+                  <description>Interrupt 2 Source Channel Configuration Register</description>
+                  <addressOffset>0x104</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>INT_SRC</name>
+                        <description>Controls which channel's completion event is mapped as a source of this Interrupt</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x5</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Enables DMA_INT2 mapping</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DMA_INT3_SRCCFG</name>
+                  <displayName>INT3_SRCCFG</displayName>
+                  <description>Interrupt 3 Source Channel Configuration Register</description>
+                  <addressOffset>0x108</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>INT_SRC</name>
+                        <description>Controls which channel's completion event is mapped as a source of this Interrupt</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x5</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Enables DMA_INT3 mapping</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DMA_INT0_SRCFLG</name>
+                  <displayName>INT0_SRCFLG</displayName>
+                  <description>Interrupt 0 Source Channel Flag Register</description>
+                  <addressOffset>0x110</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CH0</name>
+                        <description>Channel 0 was the source of DMA_INT0</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH1</name>
+                        <description>Channel 1 was the source of DMA_INT0</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH2</name>
+                        <description>Channel 2 was the source of DMA_INT0</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH3</name>
+                        <description>Channel 3 was the source of DMA_INT0</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH4</name>
+                        <description>Channel 4 was the source of DMA_INT0</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH5</name>
+                        <description>Channel 5 was the source of DMA_INT0</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH6</name>
+                        <description>Channel 6 was the source of DMA_INT0</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH7</name>
+                        <description>Channel 7 was the source of DMA_INT0</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH8</name>
+                        <description>Channel 8 was the source of DMA_INT0</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH9</name>
+                        <description>Channel 9 was the source of DMA_INT0</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH10</name>
+                        <description>Channel 10 was the source of DMA_INT0</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH11</name>
+                        <description>Channel 11 was the source of DMA_INT0</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH12</name>
+                        <description>Channel 12 was the source of DMA_INT0</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH13</name>
+                        <description>Channel 13 was the source of DMA_INT0</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH14</name>
+                        <description>Channel 14 was the source of DMA_INT0</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH15</name>
+                        <description>Channel 15 was the source of DMA_INT0</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH16</name>
+                        <description>Channel 16 was the source of DMA_INT0</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH17</name>
+                        <description>Channel 17 was the source of DMA_INT0</description>
+                        <bitOffset>0x11</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH18</name>
+                        <description>Channel 18 was the source of DMA_INT0</description>
+                        <bitOffset>0x12</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH19</name>
+                        <description>Channel 19 was the source of DMA_INT0</description>
+                        <bitOffset>0x13</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH20</name>
+                        <description>Channel 20 was the source of DMA_INT0</description>
+                        <bitOffset>0x14</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH21</name>
+                        <description>Channel 21 was the source of DMA_INT0</description>
+                        <bitOffset>0x15</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH22</name>
+                        <description>Channel 22 was the source of DMA_INT0</description>
+                        <bitOffset>0x16</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH23</name>
+                        <description>Channel 23 was the source of DMA_INT0</description>
+                        <bitOffset>0x17</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH24</name>
+                        <description>Channel 24 was the source of DMA_INT0</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH25</name>
+                        <description>Channel 25 was the source of DMA_INT0</description>
+                        <bitOffset>0x19</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH26</name>
+                        <description>Channel 26 was the source of DMA_INT0</description>
+                        <bitOffset>0x1A</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH27</name>
+                        <description>Channel 27 was the source of DMA_INT0</description>
+                        <bitOffset>0x1B</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH28</name>
+                        <description>Channel 28 was the source of DMA_INT0</description>
+                        <bitOffset>0x1C</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH29</name>
+                        <description>Channel 29 was the source of DMA_INT0</description>
+                        <bitOffset>0x1D</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH30</name>
+                        <description>Channel 30 was the source of DMA_INT0</description>
+                        <bitOffset>0x1E</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH31</name>
+                        <description>Channel 31 was the source of DMA_INT0</description>
+                        <bitOffset>0x1F</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DMA_INT0_CLRFLG</name>
+                  <displayName>INT0_CLRFLG</displayName>
+                  <description>Interrupt 0 Source Channel Clear Flag Register</description>
+                  <addressOffset>0x114</addressOffset>
+                  <size>32</size>
+                  <access>write-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000000</resetMask>
+                  <fields>
+                    <field>
+                        <name>CH0</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CH1</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CH2</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CH3</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CH4</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CH5</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CH6</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CH7</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CH8</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CH9</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CH10</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CH11</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CH12</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CH13</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CH14</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CH15</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CH16</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CH17</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0x11</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CH18</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0x12</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CH19</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0x13</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CH20</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0x14</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CH21</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0x15</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CH22</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0x16</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CH23</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0x17</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CH24</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CH25</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0x19</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CH26</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0x1A</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CH27</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0x1B</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CH28</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0x1C</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CH29</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0x1D</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CH30</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0x1E</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CH31</name>
+                        <description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
+                        <bitOffset>0x1F</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DMA_STAT</name>
+                  <displayName>STAT</displayName>
+                  <description>Status Register</description>
+                  <addressOffset>0x1000</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x0f00ffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>MASTEN</name>
+                        <description>Enable status of the controller</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>MASTEN_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>MASTEN_0</name>
+                                <description>Controller disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>MASTEN_1</name>
+                                <description>Controller enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>STATE</name>
+                        <description>Current state of the control state machine.

+State can be one of the following:</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>STATE_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>STATE_0</name>
+                                <description>idle</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>STATE_1</name>
+                                <description>reading channel controller data</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>STATE_2</name>
+                                <description>reading source data end pointer</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>STATE_3</name>
+                                <description>reading destination data end pointer</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>STATE_4</name>
+                                <description>reading source data</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>STATE_5</name>
+                                <description>writing destination data</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>STATE_6</name>
+                                <description>waiting for DMA request to clear</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>STATE_7</name>
+                                <description>writing channel controller data</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>STATE_8</name>
+                                <description>stalled</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>STATE_9</name>
+                                <description>done</description>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>STATE_10</name>
+                                <description>peripheral scatter-gather transition</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DMACHANS</name>
+                        <description>Number of available DMA channels minus one.</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x5</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>DMACHANS_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>DMACHANS_0</name>
+                                <description>Controller configured to use 1 DMA channel</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DMACHANS_1</name>
+                                <description>Controller configured to use 2 DMA channels</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DMACHANS_30</name>
+                                <description>Controller configured to use 31 DMA channels</description>
+                                <value>30</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DMACHANS_31</name>
+                                <description>Controller configured to use 32 DMA channels</description>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TESTSTAT</name>
+                        <description>To reduce the gate count the controller can be configured to exclude the integration test logic.

+The values 2h to Fh are Reserved.</description>
+                        <bitOffset>0x1C</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>TESTSTAT_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>TESTSTAT_0</name>
+                                <description>Controller does not include the integration test logic</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TESTSTAT_1</name>
+                                <description>Controller includes the integration test logic</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DMA_CFG</name>
+                  <displayName>CFG</displayName>
+                  <description>Configuration Register</description>
+                  <addressOffset>0x1004</addressOffset>
+                  <size>32</size>
+                  <access>write-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000000</resetMask>
+                  <fields>
+                    <field>
+                        <name>MASTEN</name>
+                        <description>Enable status of the controller</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>MASTEN_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>MASTEN_0</name>
+                                <description>Controller disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>MASTEN_1</name>
+                                <description>Controller enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CHPROTCTRL</name>
+                        <description>Sets the AHB-Lite protection by controlling the HPROT[3:1] signal

+levels as follows:

+Bit [7] Controls HPROT[3] to indicate if a cacheable access is occurring.

+Bit [6] Controls HPROT[2] to indicate if a bufferable access is occurring.

+Bit [5] Controls HPROT[1] to indicate if a privileged access is occurring.

+Note: When bit [n] = 1 then the corresponding HPROT is HIGH.

+When bit [n] = 0 then the corresponding HPROT is LOW.</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DMA_CTLBASE</name>
+                  <displayName>CTLBASE</displayName>
+                  <description>Channel Control Data Base Pointer Register</description>
+                  <addressOffset>0x1008</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>ADDR</name>
+                        <description>Pointer to the base address of the primary data structure.</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1B</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DMA_ALTBASE</name>
+                  <displayName>ALTBASE</displayName>
+                  <description>Channel Alternate Control Data Base Pointer Register</description>
+                  <addressOffset>0x100C</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffff00</resetMask>
+                  <fields>
+                    <field>
+                        <name>ADDR</name>
+                        <description>Base address of the alternate data structure</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DMA_WAITSTAT</name>
+                  <displayName>WAITSTAT</displayName>
+                  <description>Channel Wait on Request Status Register</description>
+                  <addressOffset>0x1010</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>WAITREQ</name>
+                        <description>Channel wait on request status.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>WAITREQ_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>WAITREQ_0</name>
+                                <description>dma_waitonreq[C] is LOW.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAITREQ_1</name>
+                                <description>dma_waitonreq[C] is HIGH.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DMA_SWREQ</name>
+                  <displayName>SWREQ</displayName>
+                  <description>Channel Software Request Register</description>
+                  <addressOffset>0x1014</addressOffset>
+                  <size>32</size>
+                  <access>write-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000000</resetMask>
+                  <fields>
+                    <field>
+                        <name>CHNL_SW_REQ</name>
+                        <description>Set the appropriate bit to generate a software DMA request on the

+corresponding DMA channel.

+Writing to a bit where a DMA channel is not implemented does not

+create a DMA request for that channel.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CHNL_SW_REQ_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CHNL_SW_REQ_0</name>
+                                <description>Does not create a DMA request for the channel</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CHNL_SW_REQ_1</name>
+                                <description>Creates a DMA request for the channel</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DMA_USEBURSTSET</name>
+                  <displayName>USEBURSTSET</displayName>
+                  <description>Channel Useburst Set Register</description>
+                  <addressOffset>0x1018</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>SET</name>
+                        <description>Returns the useburst status, or disables dma_sreq from generating DMA requests.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <name>SET_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>SET_0_READ</name>
+                                <description>DMA channel C responds to requests that it receives on dma_req[C] or dma_sreq[C].

+The controller performs 2R, or single, bus transfers.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SET_1_READ</name>
+                                <description>DMA channel C does not respond to requests that it receives on dma_sreq[C].

+The controller only responds to dma_req[C] requests and performs 2R transfers.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                        <enumeratedValues>
+                            <name>SET_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>SET_0_WRITE</name>
+                                <description>No effect. Use the DMA_USEBURST_CLR Register to set bit [C] to 0.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SET_1_WRITE</name>
+                                <description>Disables dma_sreq[C] from generating DMA requests.

+The controller performs 2R transfers.

+Writing to a bit where a DMA channel is not implemented has no effect.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DMA_USEBURSTCLR</name>
+                  <displayName>USEBURSTCLR</displayName>
+                  <description>Channel Useburst Clear Register</description>
+                  <addressOffset>0x101C</addressOffset>
+                  <size>32</size>
+                  <access>write-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000000</resetMask>
+                  <fields>
+                    <field>
+                        <name>CLR</name>
+                        <description>Set the appropriate bit to enable dma_sreq to generate requests.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLR_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLR_0</name>
+                                <description>No effect.

+Use the DMA_USEBURST_SET Register to disable dma_sreq from generating requests.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLR_1</name>
+                                <description>Enables dma_sreq[C] to generate DMA requests.

+Writing to a bit where a DMA channel is not implemented has no effect.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DMA_REQMASKSET</name>
+                  <displayName>REQMASKSET</displayName>
+                  <description>Channel Request Mask Set Register</description>
+                  <addressOffset>0x1020</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>SET</name>
+                        <description>Returns the request mask status of dma_req and dma_sreq, or

+disables the corresponding channel from generating DMA requests.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <name>SET_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>SET_0_READ</name>
+                                <description>External requests are enabled for channel C.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SET_1_READ</name>
+                                <description>External requests are disabled for channel C.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                        <enumeratedValues>
+                            <name>SET_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>SET_0_WRITE</name>
+                                <description>No effect.

+Use the DMA_REQMASKCLR Register to enable DMA requests.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SET_1_WRITE</name>
+                                <description>Disables dma_req[C] and dma_sreq[C] from generating DMA requests.

+Writing to a bit where a DMA channel is not implemented has no effect.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DMA_REQMASKCLR</name>
+                  <displayName>REQMASKCLR</displayName>
+                  <description>Channel Request Mask Clear Register</description>
+                  <addressOffset>0x1024</addressOffset>
+                  <size>32</size>
+                  <access>write-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000000</resetMask>
+                  <fields>
+                    <field>
+                        <name>CLR</name>
+                        <description>Set the appropriate bit to enable DMA requests for the channel

+corresponding to dma_req and dma_sreq.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLR_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLR_0</name>
+                                <description>No effect.

+Use the DMA_REQMASKSET Register to disable dma_req and

+dma_sreq from generating requests.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLR_1</name>
+                                <description>Enables dma_req[C] or dma_sreq[C] to generate DMA requests.

+Writing to a bit where a DMA channel is not implemented has no effect.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DMA_ENASET</name>
+                  <displayName>ENASET</displayName>
+                  <description>Channel Enable Set Register</description>
+                  <addressOffset>0x1028</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>SET</name>
+                        <description>Returns the enable status of the channels, or enables the

+corresponding channels.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <name>SET_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>SET_0_READ</name>
+                                <description>Channel C is disabled.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SET_1_READ</name>
+                                <description>Channel C is enabled.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                        <enumeratedValues>
+                            <name>SET_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>SET_0_WRITE</name>
+                                <description>No effect.

+Use the DMA_ENACLR Register to disable a channel.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SET_1_WRITE</name>
+                                <description>Enables channel C.

+Writing to a bit where a DMA channel is not implemented has no effect.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DMA_ENACLR</name>
+                  <displayName>ENACLR</displayName>
+                  <description>Channel Enable Clear Register</description>
+                  <addressOffset>0x102C</addressOffset>
+                  <size>32</size>
+                  <access>write-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000000</resetMask>
+                  <fields>
+                    <field>
+                        <name>CLR</name>
+                        <description>Set the appropriate bit to disable the corresponding DMA channel.

+Note: The controller disables a channel, by setting the appropriate

+bit, when:

+a) it completes the DMA cycle

+b) it reads a channel_cfg memory location which has cycle_ctrl =

+b000

+c) an ERROR occurs on the AHB-Lite bus.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLR_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLR_0</name>
+                                <description>No effect.

+Use the DMA_ENASET Register to enable DMA channels.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLR_1</name>
+                                <description>Disables channel C.

+Writing to a bit where a DMA channel is not implemented has no effect.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DMA_ALTSET</name>
+                  <displayName>ALTSET</displayName>
+                  <description>Channel Primary-Alternate Set Register</description>
+                  <addressOffset>0x1030</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>SET</name>
+                        <description>Channel Primary-Alternate Set Register</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <name>SET_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>SET_0_READ</name>
+                                <description>DMA channel C is using the primary data structure.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SET_1_READ</name>
+                                <description>DMA channel C is using the alternate data structure.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                        <enumeratedValues>
+                            <name>SET_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>SEL_0_WRITE</name>
+                                <description>No effect.

+Use the DMA_ALTCLR Register to set bit [C] to 0.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SEL_1_WRITE</name>
+                                <description>Selects the alternate data structure for channel C.

+Writing to a bit where a DMA channel is not implemented has no effect.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DMA_ALTCLR</name>
+                  <displayName>ALTCLR</displayName>
+                  <description>Channel Primary-Alternate Clear Register</description>
+                  <addressOffset>0x1034</addressOffset>
+                  <size>32</size>
+                  <access>write-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000000</resetMask>
+                  <fields>
+                    <field>
+                        <name>CLR</name>
+                        <description>Channel Primary-Alternate Clear Register</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLR_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLR_0</name>
+                                <description>No effect.

+Use the DMA_ALTSET Register to select the alternate data structure.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLR_1</name>
+                                <description>Selects the primary data structure for channel C.

+Writing to a bit where a DMA channel is not implemented has no effect.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DMA_PRIOSET</name>
+                  <displayName>PRIOSET</displayName>
+                  <description>Channel Priority Set Register</description>
+                  <addressOffset>0x1038</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>SET</name>
+                        <description>Returns the channel priority mask status, or sets the channel priority

+to high.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <name>SET_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>SET_0_READ</name>
+                                <description>DMA channel C is using the default priority level.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SET_1_READ</name>
+                                <description>DMA channel C is using a high priority level.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                        <enumeratedValues>
+                            <name>SET_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>SET_0_WRITE</name>
+                                <description>No effect.

+Use the DMA_PRIOCLR Register to set channel C to the default priority level.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SET_1_WRITE</name>
+                                <description>Channel C uses the high priority level.

+Writing to a bit where a DMA channel is not implemented has no effect.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DMA_PRIOCLR</name>
+                  <displayName>PRIOCLR</displayName>
+                  <description>Channel Priority Clear Register</description>
+                  <addressOffset>0x103C</addressOffset>
+                  <size>32</size>
+                  <access>write-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000000</resetMask>
+                  <fields>
+                    <field>
+                        <name>CLR</name>
+                        <description>Set the appropriate bit to select the default priority level for the

+specified DMA channel.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLR_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLR_0</name>
+                                <description>No effect.

+Use the DMA_PRIOSET Register to set channel C to the high priority level.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLR_1</name>
+                                <description>Channel C uses the default priority level.

+Writing to a bit where a DMA channel is not implemented has no effect.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DMA_ERRCLR</name>
+                  <displayName>ERRCLR</displayName>
+                  <description>Bus Error Clear Register</description>
+                  <addressOffset>0x104C</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>ERRCLR</name>
+                        <description>Returns the status of dma_err, or sets the signal LOW.

+

+For test purposes, use the ERRSET register to set dma_err HIGH.

+Note: If you deassert dma_err at the same time as an ERROR

+occurs on the AHB-Lite bus, then the ERROR condition takes

+precedence and dma_err remains asserted.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <name>ERRCLR_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ERRCLR_0_READ</name>
+                                <description>dma_err is LOW</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ERRCLR_1_READ</name>
+                                <description>dma_err is HIGH.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                        <enumeratedValues>
+                            <name>ERRCLR_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>ERRCLR_0_WRITE</name>
+                                <description>No effect, status of dma_err is unchanged.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ERRCLR_1_WRITE</name>
+                                <description>Sets dma_err LOW.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>PCM</name>
+        <version>356.0</version>
+        <description>PCM</description>
+        <baseAddress>0x40010000</baseAddress>
+        <interrupt>
+            <name>PCM_IRQ</name>
+            <description>PCM Interrupt</description>
+            <value>2</value>
+        </interrupt>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x14</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>PCMCTL0</name>
+                  <displayName>CTL0</displayName>
+                  <description>Control 0 Register</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0xa5960000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>AMR</name>
+                        <description>Active Mode Request</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>AMR_0</name>
+                                <description>LDO based Active Mode at Core voltage setting 0.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>AMR_1</name>
+                                <description>LDO based Active Mode at Core voltage setting 1.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>AMR_4</name>
+                                <description>DC-DC based Active Mode at Core voltage setting 0.</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>AMR_5</name>
+                                <description>DC-DC based Active Mode at Core voltage setting 1.</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>AMR_8</name>
+                                <description>Low-Frequency Active Mode at Core voltage setting 0.</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>AMR_9</name>
+                                <description>Low-Frequency Active Mode at Core voltage setting 1.</description>
+                                <value>9</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LPMR</name>
+                        <description>Low Power Mode Request</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>LPMR_0</name>
+                                <description>LPM3. Core voltage setting is similar to the mode from which LPM3 is entered.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LPMR_10</name>
+                                <description>LPM3.5. Core voltage setting 0.</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LPMR_12</name>
+                                <description>LPM4.5</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CPM</name>
+                        <description>Current Power Mode</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x6</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>CPM_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>CPM_0</name>
+                                <description>LDO based Active Mode at Core voltage setting 0.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CPM_1</name>
+                                <description>LDO based Active Mode at Core voltage setting 1.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CPM_4</name>
+                                <description>DC-DC based Active Mode at Core voltage setting 0.</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CPM_5</name>
+                                <description>DC-DC based Active Mode at Core voltage setting 1.</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CPM_8</name>
+                                <description>Low-Frequency Active Mode at Core voltage setting 0.</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CPM_9</name>
+                                <description>Low-Frequency Active Mode at Core voltage setting 1.</description>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CPM_16</name>
+                                <description>LDO based LPM0 at Core voltage setting 0.</description>
+                                <value>16</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CPM_17</name>
+                                <description>LDO based LPM0 at Core voltage setting 1.</description>
+                                <value>17</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CPM_20</name>
+                                <description>DC-DC based LPM0 at Core voltage setting 0.</description>
+                                <value>20</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CPM_21</name>
+                                <description>DC-DC based LPM0 at Core voltage setting 1.</description>
+                                <value>21</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CPM_24</name>
+                                <description>Low-Frequency LPM0 at Core voltage setting 0.</description>
+                                <value>24</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CPM_25</name>
+                                <description>Low-Frequency LPM0 at Core voltage setting 1.</description>
+                                <value>25</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CPM_32</name>
+                                <description>LPM3</description>
+                                <value>32</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PCMKEY</name>
+                        <description>PCM key</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PCMCTL1</name>
+                  <displayName>CTL1</displayName>
+                  <description>Control 1 Register</description>
+                  <addressOffset>0x4</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0xa5960000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>LOCKLPM5</name>
+                        <description>Lock LPM5</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>LOCKLPM5_0</name>
+                                <description>LPMx.5 configuration defaults to reset condition</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOCKLPM5_1</name>
+                                <description>LPMx.5 configuration remains locked during LPMx.5 entry and exit</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCKBKUP</name>
+                        <description>Lock Backup</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>LOCKBKUP_0</name>
+                                <description>Backup domain configuration defaults to reset condition</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOCKBKUP_1</name>
+                                <description>Backup domain configuration remains locked during LPM3.5 entry and exit</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FORCE_LPM_ENTRY</name>
+                        <description>Force LPM entry</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>FORCE_LPM_ENTRY_0</name>
+                                <description>PCM aborts LPM3/LPMx.5 transition if the active clock configuration does not meet the LPM3/LPMx.5 entry criteria. PCM generates the LPM_INVALID_CLK flag on abort to LPM3/LPMx.5 entry.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>FORCE_LPM_ENTRY_1</name>
+                                <description>PCM enters LPM3/LPMx.5 after shuting off the clocks forcefully. Application needs to ensure RTC and WDT are clocked using BCLK tree to keep these modules alive in LPM3/LPM3.5. In LPM4.5 all clocks are forcefully shutoff and the core voltage is turned off.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PMR_BUSY</name>
+                        <description>Power mode request busy flag</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PCMKEY</name>
+                        <description>PCM key</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PCMIE</name>
+                  <displayName>IE</displayName>
+                  <description>Interrupt Enable Register</description>
+                  <addressOffset>0x8</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>LPM_INVALID_TR_IE</name>
+                        <description>LPM invalid transition interrupt enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>LPM_INVALID_TR_IE_0</name>
+                                <description>Disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LPM_INVALID_TR_IE_1</name>
+                                <description>Enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LPM_INVALID_CLK_IE</name>
+                        <description>LPM invalid clock interrupt enable</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>LPM_INVALID_CLK_IE_0</name>
+                                <description>Disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LPM_INVALID_CLK_IE_1</name>
+                                <description>Enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AM_INVALID_TR_IE</name>
+                        <description>Active mode invalid transition interrupt enable</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>AM_INVALID_TR_IE_0</name>
+                                <description>Disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>AM_INVALID_TR_IE_1</name>
+                                <description>Enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DCDC_ERROR_IE</name>
+                        <description>DC-DC error interrupt enable</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DCDC_ERROR_IE_0</name>
+                                <description>Disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DCDC_ERROR_IE_1</name>
+                                <description>Enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PCMIFG</name>
+                  <displayName>IFG</displayName>
+                  <description>Interrupt Flag Register</description>
+                  <addressOffset>0xC</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>LPM_INVALID_TR_IFG</name>
+                        <description>LPM invalid transition flag</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LPM_INVALID_CLK_IFG</name>
+                        <description>LPM invalid clock flag</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>AM_INVALID_TR_IFG</name>
+                        <description>Active mode invalid transition flag</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DCDC_ERROR_IFG</name>
+                        <description>DC-DC error flag</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PCMCLRIFG</name>
+                  <displayName>CLRIFG</displayName>
+                  <description>Clear Interrupt Flag Register</description>
+                  <addressOffset>0x10</addressOffset>
+                  <size>32</size>
+                  <access>write-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CLR_LPM_INVALID_TR_IFG</name>
+                        <description>Clear LPM invalid transition flag</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CLR_LPM_INVALID_CLK_IFG</name>
+                        <description>Clear LPM invalid clock flag</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CLR_AM_INVALID_TR_IFG</name>
+                        <description>Clear active mode invalid transition flag</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CLR_DCDC_ERROR_IFG</name>
+                        <description>Clear DC-DC error flag</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>CS</name>
+        <version>356.0</version>
+        <description>CS</description>
+        <baseAddress>0x40010400</baseAddress>
+        <interrupt>
+            <name>CS_IRQ</name>
+            <description>CS Interrupt</description>
+            <value>1</value>
+        </interrupt>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x68</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>CSKEY</name>
+                  <displayName>KEY</displayName>
+                  <description>Key Register</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x0000a596</resetValue>
+                  <fields>
+                    <field>
+                        <name>CSKEY</name>
+                        <description>Write xxxx_695Ah to unlock</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CSCTL0</name>
+                  <displayName>CTL0</displayName>
+                  <description>Control 0 Register</description>
+                  <addressOffset>0x4</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00010000</resetValue>
+                  <fields>
+                    <field>
+                        <name>DCOTUNE</name>
+                        <description>DCO frequency tuning select</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0xA</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DCORSEL</name>
+                        <description>DCO frequency range select</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DCORSEL_0</name>
+                                <description>Nominal DCO Frequency Range (MHz): 1 to 2</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DCORSEL_1</name>
+                                <description>Nominal DCO Frequency Range (MHz): 2 to 4</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DCORSEL_2</name>
+                                <description>Nominal DCO Frequency Range (MHz): 4 to 8</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DCORSEL_3</name>
+                                <description>Nominal DCO Frequency Range (MHz): 8 to 16</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DCORSEL_4</name>
+                                <description>Nominal DCO Frequency Range (MHz): 16 to 32</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DCORSEL_5</name>
+                                <description>Nominal DCO Frequency Range (MHz): 32 to 64</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DCORES</name>
+                        <description>Enables the DCO external resistor mode</description>
+                        <bitOffset>0x16</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DCORES_0</name>
+                                <description>Internal resistor mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DCORES_1</name>
+                                <description>External resistor mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DCOEN</name>
+                        <description>Enables the DCO oscillator</description>
+                        <bitOffset>0x17</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DCOEN_0</name>
+                                <description>DCO is on if it is used as a source for MCLK, HSMCLK , or SMCLK and clock is requested, otherwise it is disabled.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DCOEN_1</name>
+                                <description>DCO is on</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CSCTL1</name>
+                  <displayName>CTL1</displayName>
+                  <description>Control 1 Register</description>
+                  <addressOffset>0x8</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000033</resetValue>
+                  <fields>
+                    <field>
+                        <name>SELM</name>
+                        <description>Selects the MCLK source</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SELM_0</name>
+                                <description>when LFXT available, otherwise REFOCLK</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SELM_1</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SELM_2</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SELM_3</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SELM_4</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SELM_5</name>
+                                <description>when HFXT available, otherwise DCOCLK</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SELM_6</name>
+                                <description>when HFXT2 available, otherwise DCOCLK</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SELM_7</name>
+                                <description>for future use. Defaults to DCOCLK. Not recommended for use

+to ensure future compatibilities.</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SELS</name>
+                        <description>Selects the SMCLK and HSMCLK source</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SELS_0</name>
+                                <description>when LFXT available, otherwise REFOCLK</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SELS_1</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SELS_2</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SELS_3</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SELS_4</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SELS_5</name>
+                                <description>when HFXT available, otherwise DCOCLK</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SELS_6</name>
+                                <description>when HFXT2 available, otherwise DCOCLK</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SELS_7</name>
+                                <description>for furture use. Defaults to DCOCLK. Do not use to ensure future compatibilities.</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SELA</name>
+                        <description>Selects the ACLK source</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SELA_0</name>
+                                <description>when LFXT available, otherwise REFOCLK</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SELA_1</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SELA_2</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SELA_3</name>
+                                <description>for future use. Defaults to REFOCLK. Not recommended

+for use to ensure future compatibilities.</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SELA_4</name>
+                                <description>for future use. Defaults to REFOCLK. Not recommended

+for use to ensure future compatibilities.</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SELA_5</name>
+                                <description>for future use. Defaults to REFOCLK. Not recommended

+for use to ensure future compatibilities.</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SELA_6</name>
+                                <description>for future use. Defaults to REFOCLK. Not recommended

+for use to ensure future compatibilities.</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SELA_7</name>
+                                <description>for future use. Defaults to REFOCLK. Not recommended

+for use to ensure future compatibilities.</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SELB</name>
+                        <description>Selects the BCLK source</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SELB_0</name>
+                                <description>LFXTCLK</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SELB_1</name>
+                                <description>REFOCLK</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DIVM</name>
+                        <description>MCLK source divider</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DIVM_0</name>
+                                <description>f(MCLK)/1</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DIVM_1</name>
+                                <description>f(MCLK)/2</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DIVM_2</name>
+                                <description>f(MCLK)/4</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DIVM_3</name>
+                                <description>f(MCLK)/8</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DIVM_4</name>
+                                <description>f(MCLK)/16</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DIVM_5</name>
+                                <description>f(MCLK)/32</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DIVM_6</name>
+                                <description>f(MCLK)/64</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DIVM_7</name>
+                                <description>f(MCLK)/128</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DIVHS</name>
+                        <description>HSMCLK source divider</description>
+                        <bitOffset>0x14</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DIVHS_0</name>
+                                <description>f(HSMCLK)/1</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DIVHS_1</name>
+                                <description>f(HSMCLK)/2</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DIVHS_2</name>
+                                <description>f(HSMCLK)/4</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DIVHS_3</name>
+                                <description>f(HSMCLK)/8</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DIVHS_4</name>
+                                <description>f(HSMCLK)/16</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DIVHS_5</name>
+                                <description>f(HSMCLK)/32</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DIVHS_6</name>
+                                <description>f(HSMCLK)/64</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DIVHS_7</name>
+                                <description>f(HSMCLK)/128</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DIVA</name>
+                        <description>ACLK source divider</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DIVA_0</name>
+                                <description>f(ACLK)/1</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DIVA_1</name>
+                                <description>f(ACLK)/2</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DIVA_2</name>
+                                <description>f(ACLK)/4</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DIVA_3</name>
+                                <description>f(ACLK)/8</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DIVA_4</name>
+                                <description>f(ACLK)/16</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DIVA_5</name>
+                                <description>f(ACLK)/32</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DIVA_6</name>
+                                <description>f(ACLK)/64</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DIVA_7</name>
+                                <description>f(ACLK)/128</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DIVS</name>
+                        <description>SMCLK source divider</description>
+                        <bitOffset>0x1C</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DIVS_0</name>
+                                <description>f(SMCLK)/1</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DIVS_1</name>
+                                <description>f(SMCLK)/2</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DIVS_2</name>
+                                <description>f(SMCLK)/4</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DIVS_3</name>
+                                <description>f(SMCLK)/8</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DIVS_4</name>
+                                <description>f(SMCLK)/16</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DIVS_5</name>
+                                <description>f(SMCLK)/32</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DIVS_6</name>
+                                <description>f(SMCLK)/64</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DIVS_7</name>
+                                <description>f(SMCLK)/128</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CSCTL2</name>
+                  <displayName>CTL2</displayName>
+                  <description>Control 2 Register</description>
+                  <addressOffset>0xC</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00010003</resetValue>
+                  <fields>
+                    <field>
+                        <name>LFXTDRIVE</name>
+                        <description>LFXT oscillator current can be adjusted to its drive needs</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>LFXTDRIVE_0</name>
+                                <description>Lowest drive strength and current consumption LFXT oscillator.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LFXTDRIVE_1</name>
+                                <description>Increased drive strength LFXT oscillator.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LFXTDRIVE_2</name>
+                                <description>Increased drive strength LFXT oscillator.</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LFXTDRIVE_3</name>
+                                <description>Maximum drive strength and maximum current consumption LFXT oscillator.</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LFXTAGCOFF</name>
+                        <description>Disables the automatic gain control of the LFXT crystal</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>LFXTAGCOFF_0</name>
+                                <description>AGC enabled.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LFXTAGCOFF_1</name>
+                                <description>AGC disabled.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LFXT_EN</name>
+                        <description>Turns on the LFXT oscillator regardless if used as a clock resource</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>LFXT_EN_0</name>
+                                <description>LFXT is on if it is used as a source for ACLK, MCLK, HSMCLK , or SMCLK

+and is selected via the port selection and not in bypass mode of operation.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LFXT_EN_1</name>
+                                <description>LFXT is on if LFXT is selected via the port selection and LFXT is not in

+bypass mode of operation.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LFXTBYPASS</name>
+                        <description>LFXT bypass select</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>LFXTBYPASS_0</name>
+                                <description>LFXT sourced by external crystal.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LFXTBYPASS_1</name>
+                                <description>LFXT sourced by external square wave.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HFXTDRIVE</name>
+                        <description>HFXT oscillator drive selection</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>HFXTDRIVE_0</name>
+                                <description>To be used for HFXTFREQ setting 000b</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HFXTDRIVE_1</name>
+                                <description>To be used for HFXTFREQ settings 001b to 110b</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HFXTFREQ</name>
+                        <description>HFXT frequency selection</description>
+                        <bitOffset>0x14</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>HFXTFREQ_0</name>
+                                <description>1 MHz to 4 MHz</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HFXTFREQ_1</name>
+                                <description>>4 MHz to 8 MHz</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HFXTFREQ_2</name>
+                                <description>>8 MHz to 16 MHz</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HFXTFREQ_3</name>
+                                <description>>16 MHz to 24 MHz</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HFXTFREQ_4</name>
+                                <description>>24 MHz to 32 MHz</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HFXTFREQ_5</name>
+                                <description>>32 MHz to 40 MHz</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HFXTFREQ_6</name>
+                                <description>>40 MHz to 48 MHz</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HFXT_EN</name>
+                        <description>Turns on the HFXT oscillator regardless if used as a clock resource</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>HFXT_EN_0</name>
+                                <description>HFXT is on if it is used as a source for MCLK, HSMCLK , or SMCLK and is selected via the port selection and not in bypass mode of operation.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HFXT_EN_1</name>
+                                <description>HFXT is on if HFXT is selected via the port selection and HFXT is not in bypass mode of operation.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HFXTBYPASS</name>
+                        <description>HFXT bypass select</description>
+                        <bitOffset>0x19</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>HFXTBYPASS_0</name>
+                                <description>HFXT sourced by external crystal.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HFXTBYPASS_1</name>
+                                <description>HFXT sourced by external square wave.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CSCTL3</name>
+                  <displayName>CTL3</displayName>
+                  <description>Control 3 Register</description>
+                  <addressOffset>0x10</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000bbb</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>FCNTLF</name>
+                        <description>Start flag counter for LFXT</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>FCNTLF_0</name>
+                                <description>4096 cycles</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>FCNTLF_1</name>
+                                <description>8192 cycles</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>FCNTLF_2</name>
+                                <description>16384 cycles</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>FCNTLF_3</name>
+                                <description>32768 cycles</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RFCNTLF</name>
+                        <description>Reset start fault counter for LFXT</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>RFCNTLF_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>RFCNTLF_0</name>
+                                <description>Not applicable. Always reads as zero due to self clearing.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RFCNTLF_1</name>
+                                <description>Restarts the counter immediately.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FCNTLF_EN</name>
+                        <description>Enable start fault counter for LFXT</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>FCNTLF_EN_0</name>
+                                <description>Startup fault counter disabled. Counter is cleared.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>FCNTLF_EN_1</name>
+                                <description>Startup fault counter enabled.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FCNTHF</name>
+                        <description>Start flag counter for HFXT</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>FCNTHF_0</name>
+                                <description>2048 cycles</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>FCNTHF_1</name>
+                                <description>4096 cycles</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>FCNTHF_2</name>
+                                <description>8192 cycles</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>FCNTHF_3</name>
+                                <description>16384 cycles</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RFCNTHF</name>
+                        <description>Reset start fault counter for HFXT</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>RFCNTHF_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>RFCNTHF_0</name>
+                                <description>Not applicable. Always reads as zero due to self clearing.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RFCNTHF_1</name>
+                                <description>Restarts the counter immediately.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FCNTHF_EN</name>
+                        <description>Enable start fault counter for HFXT</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>FCNTHF_EN_0</name>
+                                <description>Startup fault counter disabled. Counter is cleared.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>FCNTHF_EN_1</name>
+                                <description>Startup fault counter enabled.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FCNTHF2</name>
+                        <description>Start flag counter for HFXT2</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>FCNTHF2_0</name>
+                                <description>2048 cycles</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>FCNTHF2_1</name>
+                                <description>4096 cycles</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>FCNTHF2_2</name>
+                                <description>8192 cycles</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>FCNTHF2_3</name>
+                                <description>16384 cycles</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RFCNTHF2</name>
+                        <description>Reset start fault counter for HFXT2</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>RFCNTHF2_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>RFCNTHF2_0</name>
+                                <description>Not applicable. Always reads as zero due to self clearing.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RFCNTHF2_1</name>
+                                <description>Restarts the counter immediately.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FCNTHF2_EN</name>
+                        <description>Enable start fault counter for HFXT2</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>FCNTHF2_EN_0</name>
+                                <description>Startup fault counter disabled. Counter is cleared.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>FCNTHF2_EN_1</name>
+                                <description>Startup fault counter enabled.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CSCLKEN</name>
+                  <displayName>CLKEN</displayName>
+                  <description>Clock Enable Register</description>
+                  <addressOffset>0x30</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x0000000f</resetValue>
+                  <resetMask>0xffff847f</resetMask>
+                  <fields>
+                    <field>
+                        <name>ACLK_EN</name>
+                        <description>ACLK system clock conditional request enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ACLK_EN_0</name>
+                                <description>ACLK disabled regardless of conditional clock requests</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACLK_EN_1</name>
+                                <description>ACLK enabled based on any conditional clock requests</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>MCLK_EN</name>
+                        <description>MCLK system clock conditional request enable</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>MCLK_EN_0</name>
+                                <description>MCLK disabled regardless of conditional clock requests</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>MCLK_EN_1</name>
+                                <description>MCLK enabled based on any conditional clock requests</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HSMCLK_EN</name>
+                        <description>HSMCLK system clock conditional request enable</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>HSMCLK_EN_0</name>
+                                <description>HSMCLK disabled regardless of conditional clock requests</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HSMCLK_EN_1</name>
+                                <description>HSMCLK enabled based on any conditional clock requests</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SMCLK_EN</name>
+                        <description>SMCLK system clock conditional request enable</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SMCLK_EN_0</name>
+                                <description>SMCLK disabled regardless of conditional clock requests.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SMCLK_EN_1</name>
+                                <description>SMCLK enabled based on any conditional clock requests</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>VLO_EN</name>
+                        <description>Turns on the VLO oscillator</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>VLO_EN_0</name>
+                                <description>VLO is on only if it is used as a source for ACLK, MCLK, HSMCLK or SMCLK.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>VLO_EN_1</name>
+                                <description>VLO is on</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>REFO_EN</name>
+                        <description>Turns on the REFO oscillator</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>REFO_EN_0</name>
+                                <description>REFO is on only if it is used as a source for ACLK, MCLK, HSMCLK or SMCLK</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>REFO_EN_1</name>
+                                <description>REFO is on</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>MODOSC_EN</name>
+                        <description>Turns on the MODOSC oscillator</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>MODOSC_EN_0</name>
+                                <description>MODOSC is on only if it is used as a source for ACLK, MCLK, HSMCLK or SMCLK</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>MODOSC_EN_1</name>
+                                <description>MODOSC is on</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>REFOFSEL</name>
+                        <description>Selects REFO nominal frequency</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>REFOFSEL_0</name>
+                                <description>32 kHz</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>REFOFSEL_1</name>
+                                <description>128 kHz</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CSSTAT</name>
+                  <displayName>STAT</displayName>
+                  <description>Status Register</description>
+                  <addressOffset>0x34</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000003</resetValue>
+                  <resetMask>0xffff01ff</resetMask>
+                  <fields>
+                    <field>
+                        <name>DCO_ON</name>
+                        <description>DCO status</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>DCO_ON_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>DCO_ON_0</name>
+                                <description>Inactive</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DCO_ON_1</name>
+                                <description>Active</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DCOBIAS_ON</name>
+                        <description>DCO bias status</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>DCOBIAS_ON_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>DCOBIAS_ON_0</name>
+                                <description>Inactive</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DCOBIAS_ON_1</name>
+                                <description>Active</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HFXT_ON</name>
+                        <description>HFXT status</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>HFXT_ON_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>HFXT_ON_0</name>
+                                <description>Inactive</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HFXT_ON_1</name>
+                                <description>Active</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HFXT2_ON</name>
+                        <description>HFXT2 status</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>HFXT2_ON_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>HFXT2_ON_0</name>
+                                <description>Inactive</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HFXT2_ON_1</name>
+                                <description>Active</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>MODOSC_ON</name>
+                        <description>MODOSC status</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>MODOSC_ON_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>MODOSC_ON_0</name>
+                                <description>Inactive</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>MODOSC_ON_1</name>
+                                <description>Active</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>VLO_ON</name>
+                        <description>VLO status</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>VLO_ON_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>VLO_ON_0</name>
+                                <description>Inactive</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>VLO_ON_1</name>
+                                <description>Active</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LFXT_ON</name>
+                        <description>LFXT status</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>LFXT_ON_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>LFXT_ON_0</name>
+                                <description>Inactive</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LFXT_ON_1</name>
+                                <description>Active</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>REFO_ON</name>
+                        <description>REFO status</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>REFO_ON_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>REFO_ON_0</name>
+                                <description>Inactive</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>REFO_ON_1</name>
+                                <description>Active</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ACLK_ON</name>
+                        <description>ACLK system clock status</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ACLK_ON_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ACLK_ON_0</name>
+                                <description>Inactive</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACLK_ON_1</name>
+                                <description>Active</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>MCLK_ON</name>
+                        <description>MCLK system clock status</description>
+                        <bitOffset>0x11</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>MCLK_ON_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>MCLK_ON_0</name>
+                                <description>Inactive</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>MCLK_ON_1</name>
+                                <description>Active</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HSMCLK_ON</name>
+                        <description>HSMCLK system clock status</description>
+                        <bitOffset>0x12</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>HSMCLK_ON_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>HSMCLK_ON_0</name>
+                                <description>Inactive</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HSMCLK_ON_1</name>
+                                <description>Active</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SMCLK_ON</name>
+                        <description>SMCLK system clock status</description>
+                        <bitOffset>0x13</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>SMCLK_ON_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>SMCLK_ON_0</name>
+                                <description>Inactive</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SMCLK_ON_1</name>
+                                <description>Active</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>MODCLK_ON</name>
+                        <description>MODCLK system clock status</description>
+                        <bitOffset>0x14</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>MODCLK_ON_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>MODCLK_ON_0</name>
+                                <description>Inactive</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>MODCLK_ON_1</name>
+                                <description>Active</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>VLOCLK_ON</name>
+                        <description>VLOCLK system clock status</description>
+                        <bitOffset>0x15</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>VLOCLK_ON_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>VLOCLK_ON_0</name>
+                                <description>Inactive</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>VLOCLK_ON_1</name>
+                                <description>Active</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LFXTCLK_ON</name>
+                        <description>LFXTCLK system clock status</description>
+                        <bitOffset>0x16</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>LFXTCLK_ON_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>LFXTCLK_ON_0</name>
+                                <description>Inactive</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LFXTCLK_ON_1</name>
+                                <description>Active</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>REFOCLK_ON</name>
+                        <description>REFOCLK system clock status</description>
+                        <bitOffset>0x17</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>REFOCLK_ON_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>REFOCLK_ON_0</name>
+                                <description>Inactive</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>REFOCLK_ON_1</name>
+                                <description>Active</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ACLK_READY</name>
+                        <description>ACLK Ready status</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ACLK_READY_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ACLK_READY_0</name>
+                                <description>Not ready</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACLK_READY_1</name>
+                                <description>Ready</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>MCLK_READY</name>
+                        <description>MCLK Ready status</description>
+                        <bitOffset>0x19</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>MCLK_READY_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>MCLK_READY_0</name>
+                                <description>Not ready</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>MCLK_READY_1</name>
+                                <description>Ready</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HSMCLK_READY</name>
+                        <description>HSMCLK Ready status</description>
+                        <bitOffset>0x1A</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>HSMCLK_READY_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>HSMCLK_READY_0</name>
+                                <description>Not ready</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HSMCLK_READY_1</name>
+                                <description>Ready</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SMCLK_READY</name>
+                        <description>SMCLK Ready status</description>
+                        <bitOffset>0x1B</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>SMCLK_READY_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>SMCLK_READY_0</name>
+                                <description>Not ready</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SMCLK_READY_1</name>
+                                <description>Ready</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>BCLK_READY</name>
+                        <description>BCLK Ready status</description>
+                        <bitOffset>0x1C</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>BCLK_READY_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>BCLK_READY_0</name>
+                                <description>Not ready</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>BCLK_READY_1</name>
+                                <description>Ready</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CSIE</name>
+                  <displayName>IE</displayName>
+                  <description>Interrupt Enable Register</description>
+                  <addressOffset>0x40</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>LFXTIE</name>
+                        <description>LFXT oscillator fault flag interrupt enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>LFXTIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LFXTIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HFXTIE</name>
+                        <description>HFXT oscillator fault flag interrupt enable</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>HFXTIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HFXTIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HFXT2IE</name>
+                        <description>HFXT2 oscillator fault flag interrupt enable</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>HFXT2IE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HFXT2IE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DCOR_OPNIE</name>
+                        <description>DCO external resistor open circuit fault flag interrupt enable.</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DCOR_OPNIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DCOR_OPNIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FCNTLFIE</name>
+                        <description>Start fault counter interrupt enable LFXT</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>FCNTLFIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>FCNTLFIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FCNTHFIE</name>
+                        <description>Start fault counter interrupt enable HFXT</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>FCNTHFIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>FCNTHFIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FCNTHF2IE</name>
+                        <description>Start fault counter interrupt enable HFXT2</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>FCNTHF2IE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>FCNTHF2IE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PLLOOLIE</name>
+                        <description>PLL out-of-lock interrupt enable</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PLLOOLIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PLLOOLIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PLLLOSIE</name>
+                        <description>PLL loss-of-signal interrupt enable</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PLLLOSIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PLLLOSIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PLLOORIE</name>
+                        <description>PLL out-of-range interrupt enable</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PLLOORIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PLLOORIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CALIE</name>
+                        <description>REFCNT period counter interrupt enable</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CALIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CALIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CSIFG</name>
+                  <displayName>IFG</displayName>
+                  <description>Interrupt Flag Register</description>
+                  <addressOffset>0x48</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000001</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>LFXTIFG</name>
+                        <description>LFXT oscillator fault flag</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>LFXTIFG_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>LFXTIFG_0</name>
+                                <description>No fault condition occurred after the last reset</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LFXTIFG_1</name>
+                                <description>LFXT fault. A LFXT fault occurred after the last reset</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HFXTIFG</name>
+                        <description>HFXT oscillator fault flag</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>HFXTIFG_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>HFXTIFG_0</name>
+                                <description>No fault condition occurred after the last reset</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HFXTIFG_1</name>
+                                <description>HFXT fault. A HFXT fault occurred after the last reset</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HFXT2IFG</name>
+                        <description>HFXT2 oscillator fault flag</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>HFXT2IFG_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>HFXT2IFG_0</name>
+                                <description>No fault condition occurred after the last reset</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HFXT2IFG_1</name>
+                                <description>HFXT2 fault. A HFXT2 fault occurred after the last reset</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DCOR_SHTIFG</name>
+                        <description>DCO external resistor short circuit fault flag.</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>DCOR_SHTIFG_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>DCOR_SHTIFG_0</name>
+                                <description>DCO external resistor present</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DCOR_SHTIFG_1</name>
+                                <description>DCO external resistor short circuit fault</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DCOR_OPNIFG</name>
+                        <description>DCO external resistor open circuit fault flag.</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>DCOR_OPNIFG_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>DCOR_OPNIFG_0</name>
+                                <description>DCO external resistor present</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DCOR_OPNIFG_1</name>
+                                <description>DCO external resistor open circuit fault</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FCNTLFIFG</name>
+                        <description>Start fault counter interrupt flag LFXT</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>FCNTLFIFG_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>FCNTLFIFG_0</name>
+                                <description>Start counter not expired</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>FCNTLFIFG_1</name>
+                                <description>Start counter expired</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FCNTHFIFG</name>
+                        <description>Start fault counter interrupt flag HFXT</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>FCNTHFIFG_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>FCNTHFIFG_0</name>
+                                <description>Start counter not expired</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>FCNTHFIFG_1</name>
+                                <description>Start counter expired</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FCNTHF2IFG</name>
+                        <description>Start fault counter interrupt flag HFXT2</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>FCNTHF2IFG_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>FCNTHF2IFG_0</name>
+                                <description>Start counter not expired</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>FCNTHF2IFG_1</name>
+                                <description>Start counter expired</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PLLOOLIFG</name>
+                        <description>PLL out-of-lock interrupt flag</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>PLLOOLIFG_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>PLLOOLIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PLLOOLIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PLLLOSIFG</name>
+                        <description>PLL loss-of-signal interrupt flag</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>PLLLOSIFG_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>PLLLOSIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PLLLOSIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PLLOORIFG</name>
+                        <description>PLL out-of-range interrupt flag</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>PLLOORIFG_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>PLLOORIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PLLOORIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CALIFG</name>
+                        <description>REFCNT period counter expired</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>CALIFG_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>CALIFG_0</name>
+                                <description>REFCNT period counter not expired</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CALIFG_1</name>
+                                <description>REFCNT period counter expired</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CSCLRIFG</name>
+                  <displayName>CLRIFG</displayName>
+                  <description>Clear Interrupt Flag Register</description>
+                  <addressOffset>0x50</addressOffset>
+                  <size>32</size>
+                  <access>write-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CLR_LFXTIFG</name>
+                        <description>Clear LFXT oscillator fault interrupt flag</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLR_LFXTIFG_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLR_LFXTIFG_0</name>
+                                <description>No effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLR_LFXTIFG_1</name>
+                                <description>Clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLR_HFXTIFG</name>
+                        <description>Clear HFXT oscillator fault interrupt flag</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLR_HFXTIFG_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLR_HFXTIFG_0</name>
+                                <description>No effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLR_HFXTIFG_1</name>
+                                <description>Clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLR_HFXT2IFG</name>
+                        <description>Clear HFXT2 oscillator fault interrupt flag</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLR_HFXT2IFG_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLR_HFXT2IFG_0</name>
+                                <description>No effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLR_HFXT2IFG_1</name>
+                                <description>Clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLR_DCOR_OPNIFG</name>
+                        <description>Clear DCO external resistor open circuit fault interrupt flag.</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLR_DCOR_OPNIFG_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLR_DCOR_OPNIFG_0</name>
+                                <description>No effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLR_DCOR_OPNIFG_1</name>
+                                <description>Clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLR_CALIFG</name>
+                        <description>REFCNT period counter clear interrupt flag</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLR_CALIFG_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLR_CALIFG_0</name>
+                                <description>No effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLR_CALIFG_1</name>
+                                <description>Clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLR_FCNTLFIFG</name>
+                        <description>Start fault counter clear interrupt flag LFXT</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLR_FCNTLFIFG_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLR_FCNTLFIFG_0</name>
+                                <description>No effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLR_FCNTLFIFG_1</name>
+                                <description>Clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLR_FCNTHFIFG</name>
+                        <description>Start fault counter clear interrupt flag HFXT</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLR_FCNTHFIFG_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLR_FCNTHFIFG_0</name>
+                                <description>No effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLR_FCNTHFIFG_1</name>
+                                <description>Clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLR_FCNTHF2IFG</name>
+                        <description>Start fault counter clear interrupt flag HFXT2</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLR_FCNTHF2IFG_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLR_FCNTHF2IFG_0</name>
+                                <description>No effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLR_FCNTHF2IFG_1</name>
+                                <description>Clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLR_PLLOOLIFG</name>
+                        <description>PLL out-of-lock clear interrupt flag</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLR_PLLOOLIFG_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLR_PLLOOLIFG_0</name>
+                                <description>No effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLR_PLLOOLIFG_1</name>
+                                <description>Clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLR_PLLLOSIFG</name>
+                        <description>PLL loss-of-signal clear interrupt flag</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLR_PLLLOSIFG_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLR_PLLLOSIFG_0</name>
+                                <description>No effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLR_PLLLOSIFG_1</name>
+                                <description>Clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLR_PLLOORIFG</name>
+                        <description>PLL out-of-range clear interrupt flag</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLR_PLLOORIFG_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLR_PLLOORIFG_0</name>
+                                <description>No effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLR_PLLOORIFG_1</name>
+                                <description>Clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CSSETIFG</name>
+                  <displayName>SETIFG</displayName>
+                  <description>Set Interrupt Flag Register</description>
+                  <addressOffset>0x58</addressOffset>
+                  <size>32</size>
+                  <access>write-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>SET_LFXTIFG</name>
+                        <description>Set LFXT oscillator fault interrupt flag</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>SET_LFXTIFG_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>SET_LFXTIFG_0</name>
+                                <description>No effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SET_LFXTIFG_1</name>
+                                <description>Set pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SET_HFXTIFG</name>
+                        <description>Set HFXT oscillator fault interrupt flag</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>SET_HFXTIFG_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>SET_HFXTIFG_0</name>
+                                <description>No effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SET_HFXTIFG_1</name>
+                                <description>Set pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SET_HFXT2IFG</name>
+                        <description>Set HFXT2 oscillator fault interrupt flag</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>SET_HFXT2IFG_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>SET_HFXT2IFG_0</name>
+                                <description>No effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SET_HFXT2IFG_1</name>
+                                <description>Set pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SET_DCOR_OPNIFG</name>
+                        <description>Set DCO external resistor open circuit fault interrupt flag.</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>SET_DCOR_OPNIFG_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>SET_DCOR_OPNIFG_0</name>
+                                <description>No effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SET_DCOR_OPNIFG_1</name>
+                                <description>Set pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SET_CALIFG</name>
+                        <description>REFCNT period counter set interrupt flag</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>SET_CALIFG_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>SET_CALIFG_0</name>
+                                <description>No effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SET_CALIFG_1</name>
+                                <description>Set pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SET_FCNTHFIFG</name>
+                        <description>Start fault counter set interrupt flag HFXT</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>SET_FCNTHFIFG_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>SET_FCNTHFIFG_0</name>
+                                <description>No effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SET_FCNTHFIFG_1</name>
+                                <description>Set pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SET_FCNTHF2IFG</name>
+                        <description>Start fault counter set interrupt flag HFXT2</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>SET_FCNTHF2IFG_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>SET_FCNTHF2IFG_0</name>
+                                <description>No effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SET_FCNTHF2IFG_1</name>
+                                <description>Set pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SET_FCNTLFIFG</name>
+                        <description>Start fault counter set interrupt flag LFXT</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>SET_FCNTLFIFG_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>SET_FCNTLFIFG_0</name>
+                                <description>No effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SET_FCNTLFIFG_1</name>
+                                <description>Set pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SET_PLLOOLIFG</name>
+                        <description>PLL out-of-lock set interrupt flag</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>SET_PLLOOLIFG_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>SET_PLLOOLIFG_0</name>
+                                <description>No effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SET_PLLOOLIFG_1</name>
+                                <description>Set pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SET_PLLLOSIFG</name>
+                        <description>PLL loss-of-signal set interrupt flag</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>SET_PLLLOSIFG_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>SET_PLLLOSIFG_0</name>
+                                <description>No effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SET_PLLLOSIFG_1</name>
+                                <description>Set pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SET_PLLOORIFG</name>
+                        <description>PLL out-of-range set interrupt flag</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>SET_PLLOORIFG_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>SET_PLLOORIFG_0</name>
+                                <description>No effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SET_PLLOORIFG_1</name>
+                                <description>Set pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CSDCOERCAL0</name>
+                  <displayName>DCOERCAL0</displayName>
+                  <description>DCO External Resistor Cailbration 0 Register</description>
+                  <addressOffset>0x60</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x01000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>DCO_TCCAL</name>
+                        <description>DCO Temperature compensation calibration</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DCO_FCAL_RSEL04</name>
+                        <description>DCO frequency calibration for DCO frequency range (DCORSEL) 0 to 4.</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0xA</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CSDCOERCAL1</name>
+                  <displayName>DCOERCAL1</displayName>
+                  <description>DCO External Resistor Calibration 1 Register</description>
+                  <addressOffset>0x64</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000100</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>DCO_FCAL_RSEL5</name>
+                        <description>DCO frequency calibration for DCO frequency range (DCORSEL) 5.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0xA</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>PSS</name>
+        <version>356.0</version>
+        <description>PSS</description>
+        <baseAddress>0x40010800</baseAddress>
+        <interrupt>
+            <name>PSS_IRQ</name>
+            <description>PSS Interrupt</description>
+            <value>0</value>
+        </interrupt>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x40</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>PSSKEY</name>
+                  <displayName>KEY</displayName>
+                  <description>Key Register</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x0000a596</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>PSSKEY</name>
+                        <description>PSS control key</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PSSCTL0</name>
+                  <displayName>CTL0</displayName>
+                  <description>Control 0 Register</description>
+                  <addressOffset>0x4</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00002000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>SVSMHOFF</name>
+                        <description>SVSM high-side off</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SVSMHOFF_0</name>
+                                <description>The SVSMH is on</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SVSMHOFF_1</name>
+                                <description>The SVSMH is off</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SVSMHLP</name>
+                        <description>SVSM high-side low power normal performance mode</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SVSMHLP_0</name>
+                                <description>Full performance mode. See the device-specific data sheet for response times.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SVSMHLP_1</name>
+                                <description>Low power normal performance mode in LPM3, LPM4, and LPMx.5, full performance in all other modes. See the device-specific data sheet for response times.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SVSMHS</name>
+                        <description>Supply supervisor or monitor selection for the high-side</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SVSMHS_0</name>
+                                <description>Configure as SVSH</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SVSMHS_1</name>
+                                <description>Configure as SVMH</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SVSMHTH</name>
+                        <description>SVSM high-side reset voltage level</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SVMHOE</name>
+                        <description>SVSM high-side output enable</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SVMHOE_0</name>
+                                <description>SVSMHIFG bit is not output</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SVMHOE_1</name>
+                                <description>SVSMHIFG bit is output to the device SVMHOUT pin. The device-specific port logic must be configured accordingly</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SVMHOUTPOLAL</name>
+                        <description>SVMHOUT pin polarity active low</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SVMHOUTPOLAL_0</name>
+                                <description>SVMHOUT is active high. An error condition is signaled by a 1 at the SVMHOUT pin</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SVMHOUTPOLAL_1</name>
+                                <description>SVMHOUT is active low. An error condition is signaled by a 0 at the SVMHOUT pin</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DCDC_FORCE</name>
+                        <description>Force DC-DC regulator operation</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DCDC_FORCE_0</name>
+                                <description>DC-DC regulator operation not forced. Automatic fail-safe mechanism switches the core voltage regulator from DC-DC to LDO when the supply voltage falls below the minimum supply voltage necessary for DC-DC operation.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DCDC_FORCE_1</name>
+                                <description>DC-DC regulator operation forced. Automatic fail-safe mechanism is disabled and device continues to operate out of DC-DC regulator.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>VCORETRAN</name>
+                        <description>Controls core voltage level transition time</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>VCORETRAN_0</name>
+                                <description>32 s / 100 mV</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>VCORETRAN_1</name>
+                                <description>64 s / 100 mV</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>VCORETRAN_2</name>
+                                <description>128 s / 100 mV (default)</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>VCORETRAN_3</name>
+                                <description>256 s / 100 mV</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PSSIE</name>
+                  <displayName>IE</displayName>
+                  <description>Interrupt Enable Register</description>
+                  <addressOffset>0x34</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>SVSMHIE</name>
+                        <description>High-side SVSM interrupt enable</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SVSMHIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SVSMHIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PSSIFG</name>
+                  <displayName>IFG</displayName>
+                  <description>Interrupt Flag Register</description>
+                  <addressOffset>0x38</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>SVSMHIFG</name>
+                        <description>High-side SVSM interrupt flag</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>SVSMHIFG_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>SVSMHIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SVSMHIFG_1</name>
+                                <description>Interrupt due to SVSMH</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PSSCLRIFG</name>
+                  <displayName>CLRIFG</displayName>
+                  <description>Clear Interrupt Flag Register</description>
+                  <addressOffset>0x3C</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CLRSVSMHIFG</name>
+                        <description>SVSMH clear interrupt flag</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRSVSMHIFG_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRSVSMHIFG_0</name>
+                                <description>No effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRSVSMHIFG_1</name>
+                                <description>Clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>FLCTL</name>
+        <version>356.0</version>
+        <description>FLCTL</description>
+        <baseAddress>0x40011000</baseAddress>
+        <interrupt>
+            <name>FLCTL_IRQ</name>
+            <description>Flash Controller Interrupt</description>
+            <value>5</value>
+        </interrupt>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x124</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>FLCTL_POWER_STAT</name>
+                  <displayName>POWER_STAT</displayName>
+                  <description>Power Status Register</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000080</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>PSTAT</name>
+                        <description>Flash power status</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PSTAT_0</name>
+                                <description>Flash IP in power-down mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PSTAT_1</name>
+                                <description>Flash IP Vdd domain power-up in progress</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PSTAT_2</name>
+                                <description>PSS LDO_GOOD, IREF_OK and VREF_OK check in progress</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PSTAT_3</name>
+                                <description>Flash IP SAFE_LV check in progress</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PSTAT_4</name>
+                                <description>Flash IP Active</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PSTAT_5</name>
+                                <description>Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes.</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PSTAT_6</name>
+                                <description>Flash IP in Standby mode</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PSTAT_7</name>
+                                <description>Flash IP in Current mirror boost state</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LDOSTAT</name>
+                        <description>PSS FLDO GOOD status</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>LDOSTAT_0</name>
+                                <description>FLDO not GOOD</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LDOSTAT_1</name>
+                                <description>FLDO GOOD</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>VREFSTAT</name>
+                        <description>PSS VREF stable status</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>VREFSTAT_0</name>
+                                <description>Flash LDO not stable</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>VREFSTAT_1</name>
+                                <description>Flash LDO stable</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>IREFSTAT</name>
+                        <description>PSS IREF stable status</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>IREFSTAT_0</name>
+                                <description>IREF not stable</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>IREFSTAT_1</name>
+                                <description>IREF stable</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TRIMSTAT</name>
+                        <description>PSS trim done status</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>TRIMSTAT_0</name>
+                                <description>PSS trim not complete</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TRIMSTAT_1</name>
+                                <description>PSS trim complete</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RD_2T</name>
+                        <description>Indicates if Flash is being accessed in 2T mode</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RD_2T_0</name>
+                                <description>Flash reads are in 1T mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RD_2T_1</name>
+                                <description>Flash reads are in 2T mode</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_BANK0_RDCTL</name>
+                  <displayName>BANK0_RDCTL</displayName>
+                  <description>Bank0 Read Control Register</description>
+                  <addressOffset>0x10</addressOffset>
+                  <size>32</size>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>RD_MODE</name>
+                        <description>Flash read mode control setting for Bank 0</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RD_MODE_0</name>
+                                <description>Normal read mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RD_MODE_1</name>
+                                <description>Read Margin 0</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RD_MODE_2</name>
+                                <description>Read Margin 1</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RD_MODE_3</name>
+                                <description>Program Verify</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RD_MODE_4</name>
+                                <description>Erase Verify</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RD_MODE_5</name>
+                                <description>Leakage Verify</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RD_MODE_9</name>
+                                <description>Read Margin 0B</description>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RD_MODE_10</name>
+                                <description>Read Margin 1B</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>BUFI</name>
+                        <description>Enables read buffering feature for instruction fetches to this Bank</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFD</name>
+                        <description>Enables read buffering feature for data reads to this Bank</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>WAIT</name>
+                        <description>Number of wait states for read</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>WAIT_0</name>
+                                <description>0 wait states</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAIT_1</name>
+                                <description>1 wait states</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAIT_2</name>
+                                <description>2 wait states</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAIT_3</name>
+                                <description>3 wait states</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAIT_4</name>
+                                <description>4 wait states</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAIT_5</name>
+                                <description>5 wait states</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAIT_6</name>
+                                <description>6 wait states</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAIT_7</name>
+                                <description>7 wait states</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAIT_8</name>
+                                <description>8 wait states</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAIT_9</name>
+                                <description>9 wait states</description>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAIT_10</name>
+                                <description>10 wait states</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAIT_11</name>
+                                <description>11 wait states</description>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAIT_12</name>
+                                <description>12 wait states</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAIT_13</name>
+                                <description>13 wait states</description>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAIT_14</name>
+                                <description>14 wait states</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAIT_15</name>
+                                <description>15 wait states</description>
+                                <value>15</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RD_MODE_STATUS</name>
+                        <description>Read mode</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RD_MODE_STATUS_0</name>
+                                <description>Normal read mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RD_MODE_STATUS_1</name>
+                                <description>Read Margin 0</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RD_MODE_STATUS_2</name>
+                                <description>Read Margin 1</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RD_MODE_STATUS_3</name>
+                                <description>Program Verify</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RD_MODE_STATUS_4</name>
+                                <description>Erase Verify</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RD_MODE_STATUS_5</name>
+                                <description>Leakage Verify</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RD_MODE_STATUS_9</name>
+                                <description>Read Margin 0B</description>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RD_MODE_STATUS_10</name>
+                                <description>Read Margin 1B</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_BANK1_RDCTL</name>
+                  <displayName>BANK1_RDCTL</displayName>
+                  <description>Bank1 Read Control Register</description>
+                  <addressOffset>0x14</addressOffset>
+                  <size>32</size>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>RD_MODE</name>
+                        <description>Flash read mode control setting for Bank 0</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RD_MODE_0</name>
+                                <description>Normal read mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RD_MODE_1</name>
+                                <description>Read Margin 0</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RD_MODE_2</name>
+                                <description>Read Margin 1</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RD_MODE_3</name>
+                                <description>Program Verify</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RD_MODE_4</name>
+                                <description>Erase Verify</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RD_MODE_5</name>
+                                <description>Leakage Verify</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RD_MODE_9</name>
+                                <description>Read Margin 0B</description>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RD_MODE_10</name>
+                                <description>Read Margin 1B</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>BUFI</name>
+                        <description>Enables read buffering feature for instruction fetches to this Bank</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFD</name>
+                        <description>Enables read buffering feature for data reads to this Bank</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RD_MODE_STATUS</name>
+                        <description>Read mode</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RD_MODE_STATUS_0</name>
+                                <description>Normal read mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RD_MODE_STATUS_1</name>
+                                <description>Read Margin 0</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RD_MODE_STATUS_2</name>
+                                <description>Read Margin 1</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RD_MODE_STATUS_3</name>
+                                <description>Program Verify</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RD_MODE_STATUS_4</name>
+                                <description>Erase Verify</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RD_MODE_STATUS_5</name>
+                                <description>Leakage Verify</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RD_MODE_STATUS_9</name>
+                                <description>Read Margin 0B</description>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RD_MODE_STATUS_10</name>
+                                <description>Read Margin 1B</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>WAIT</name>
+                        <description>Number of wait states for read</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>WAIT_0</name>
+                                <description>0 wait states</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAIT_1</name>
+                                <description>1 wait states</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAIT_2</name>
+                                <description>2 wait states</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAIT_3</name>
+                                <description>3 wait states</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAIT_4</name>
+                                <description>4 wait states</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAIT_5</name>
+                                <description>5 wait states</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAIT_6</name>
+                                <description>6 wait states</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAIT_7</name>
+                                <description>7 wait states</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAIT_8</name>
+                                <description>8 wait states</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAIT_9</name>
+                                <description>9 wait states</description>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAIT_10</name>
+                                <description>10 wait states</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAIT_11</name>
+                                <description>11 wait states</description>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAIT_12</name>
+                                <description>12 wait states</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAIT_13</name>
+                                <description>13 wait states</description>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAIT_14</name>
+                                <description>14 wait states</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAIT_15</name>
+                                <description>15 wait states</description>
+                                <value>15</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_RDBRST_CTLSTAT</name>
+                  <displayName>RDBRST_CTLSTAT</displayName>
+                  <description>Read Burst/Compare Control and Status Register</description>
+                  <addressOffset>0x20</addressOffset>
+                  <size>32</size>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>START</name>
+                        <description>Start of burst/compare operation</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>MEM_TYPE</name>
+                        <description>Type of memory that burst is carried out on</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>MEM_TYPE_0</name>
+                                <description>Main Memory</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>MEM_TYPE_1</name>
+                                <description>Information Memory</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>MEM_TYPE_3</name>
+                                <description>Engineering Memory</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>STOP_FAIL</name>
+                        <description>Terminate burst/compare operation</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATA_CMP</name>
+                        <description>Data pattern used for comparison against memory read data</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DATA_CMP_0</name>
+                                <description>0000_0000_0000_0000_0000_0000_0000_0000</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DATA_CMP_1</name>
+                                <description>FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TEST_EN</name>
+                        <description>Enable comparison against test data compare registers</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BRST_STAT</name>
+                        <description>Status of Burst/Compare operation</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>BRST_STAT_0</name>
+                                <description>Idle</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>BRST_STAT_1</name>
+                                <description>Burst/Compare START bit written, but operation pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>BRST_STAT_2</name>
+                                <description>Burst/Compare in progress</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>BRST_STAT_3</name>
+                                <description>Burst complete (status of completed burst remains in this state unless explicitly cleared by SW)</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CMP_ERR</name>
+                        <description>Burst/Compare Operation encountered atleast one data</description>
+                        <bitOffset>0x12</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ADDR_ERR</name>
+                        <description>Burst/Compare Operation was terminated due to access to</description>
+                        <bitOffset>0x13</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLR_STAT</name>
+                        <description>Clear status bits 19-16 of this register</description>
+                        <bitOffset>0x17</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_RDBRST_STARTADDR</name>
+                  <displayName>RDBRST_STARTADDR</displayName>
+                  <description>Read Burst/Compare Start Address Register</description>
+                  <addressOffset>0x24</addressOffset>
+                  <size>32</size>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>START_ADDRESS</name>
+                        <description>Start Address of Burst Operation</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x15</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_RDBRST_LEN</name>
+                  <displayName>RDBRST_LEN</displayName>
+                  <description>Read Burst/Compare Length Register</description>
+                  <addressOffset>0x28</addressOffset>
+                  <size>32</size>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>BURST_LENGTH</name>
+                        <description>Length of Burst Operation</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x15</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_RDBRST_FAILADDR</name>
+                  <displayName>RDBRST_FAILADDR</displayName>
+                  <description>Read Burst/Compare Fail Address Register</description>
+                  <addressOffset>0x3C</addressOffset>
+                  <size>32</size>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>FAIL_ADDRESS</name>
+                        <description>Reflects address of last failed compare</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x15</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_RDBRST_FAILCNT</name>
+                  <displayName>RDBRST_FAILCNT</displayName>
+                  <description>Read Burst/Compare Fail Count Register</description>
+                  <addressOffset>0x40</addressOffset>
+                  <size>32</size>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>FAIL_COUNT</name>
+                        <description>Number of failures encountered in burst operation</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x11</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_PRG_CTLSTAT</name>
+                  <displayName>PRG_CTLSTAT</displayName>
+                  <description>Program Control and Status Register</description>
+                  <addressOffset>0x50</addressOffset>
+                  <size>32</size>
+                  <resetValue>0x0000000c</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Master control for all word program operations</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ENABLE_0</name>
+                                <description>Word program operation disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE_1</name>
+                                <description>Word program operation enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>MODE</name>
+                        <description>Write mode</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>MODE_0</name>
+                                <description>Write immediate mode. Starts program operation immediately on each write to the Flash</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>MODE_1</name>
+                                <description>Full word write mode. Flash controller collates data over multiple writes to compose the full 128bit word before initiating the program operation</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>VER_PRE</name>
+                        <description>Controls automatic pre program verify operations</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>VER_PRE_0</name>
+                                <description>No pre program verification</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>VER_PRE_1</name>
+                                <description>Pre verify feature automatically invoked for each write operation (irrespective of the mode)</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>VER_PST</name>
+                        <description>Controls automatic post program verify operations</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>VER_PST_0</name>
+                                <description>No post program verification</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>VER_PST_1</name>
+                                <description>Post verify feature automatically invoked for each write operation (irrespective of the mode)</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>STATUS</name>
+                        <description>Status of program operations in the Flash memory</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>STATUS_0</name>
+                                <description>Idle (no program operation currently active)</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>STATUS_1</name>
+                                <description>Single word program operation triggered, but pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>STATUS_2</name>
+                                <description>Single word program in progress</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>BNK_ACT</name>
+                        <description>Bank active</description>
+                        <bitOffset>0x12</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>BNK_ACT_0</name>
+                                <description>Word in Bank0 being programmed</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>BNK_ACT_1</name>
+                                <description>Word in Bank1 being programmed</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_PRGBRST_CTLSTAT</name>
+                  <displayName>PRGBRST_CTLSTAT</displayName>
+                  <description>Program Burst Control and Status Register</description>
+                  <addressOffset>0x54</addressOffset>
+                  <size>32</size>
+                  <resetValue>0x000000c0</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>START</name>
+                        <description>Trigger start of burst program operation</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>TYPE</name>
+                        <description>Type of memory that burst program is carried out on</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>TYPE_0</name>
+                                <description>Main Memory</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TYPE_1</name>
+                                <description>Information Memory</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TYPE_3</name>
+                                <description>Engineering Memory</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LEN</name>
+                        <description>Length of burst</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>LEN_0</name>
+                                <description>No burst operation</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LEN_1</name>
+                                <description>1 word burst of 128 bits, starting with address in the FLCTL_PRGBRST_STARTADDR Register</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LEN_2</name>
+                                <description>2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LEN_3</name>
+                                <description>3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LEN_4</name>
+                                <description>4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AUTO_PRE</name>
+                        <description>Auto-Verify operation before the Burst Program</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>AUTO_PRE_0</name>
+                                <description>No program verify operations carried out</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>AUTO_PRE_1</name>
+                                <description>Causes an automatic Burst Program Verify after the Burst Program Operation</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AUTO_PST</name>
+                        <description>Auto-Verify operation after the Burst Program</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>AUTO_PST_0</name>
+                                <description>No program verify operations carried out</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>AUTO_PST_1</name>
+                                <description>Causes an automatic Burst Program Verify before the Burst Program Operation</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>BURST_STATUS</name>
+                        <description>Status of a Burst Operation</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>BURST_STATUS_0</name>
+                                <description>Idle (Burst not active)</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>BURST_STATUS_1</name>
+                                <description>Burst program started but pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>BURST_STATUS_2</name>
+                                <description>Burst active, with 1st 128 bit word being written into Flash</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>BURST_STATUS_3</name>
+                                <description>Burst active, with 2nd 128 bit word being written into Flash</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>BURST_STATUS_4</name>
+                                <description>Burst active, with 3rd 128 bit word being written into Flash</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>BURST_STATUS_5</name>
+                                <description>Burst active, with 4th 128 bit word being written into Flash</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>BURST_STATUS_7</name>
+                                <description>Burst Complete (status of completed burst remains in this state unless explicitly cleared by SW)</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PRE_ERR</name>
+                        <description>Burst Operation encountered preprogram auto-verify errors</description>
+                        <bitOffset>0x13</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PST_ERR</name>
+                        <description>Burst Operation encountered postprogram auto-verify errors</description>
+                        <bitOffset>0x14</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ADDR_ERR</name>
+                        <description>Burst Operation was terminated due to attempted program of reserved memory</description>
+                        <bitOffset>0x15</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLR_STAT</name>
+                        <description>Clear status bits 21-16 of this register</description>
+                        <bitOffset>0x17</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_PRGBRST_STARTADDR</name>
+                  <displayName>PRGBRST_STARTADDR</displayName>
+                  <description>Program Burst Start Address Register</description>
+                  <addressOffset>0x58</addressOffset>
+                  <size>32</size>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>START_ADDRESS</name>
+                        <description>Start Address of Program Burst Operation</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x16</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_PRGBRST_DATA0_0</name>
+                  <displayName>PRGBRST_DATA0_0</displayName>
+                  <description>Program Burst Data0 Register0</description>
+                  <addressOffset>0x60</addressOffset>
+                  <size>32</size>
+                  <resetValue>0xffffffff</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>DATAIN</name>
+                        <description>Program Burst 128 bit Data Word 0</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_PRGBRST_DATA0_1</name>
+                  <displayName>PRGBRST_DATA0_1</displayName>
+                  <description>Program Burst Data0 Register1</description>
+                  <addressOffset>0x64</addressOffset>
+                  <size>32</size>
+                  <resetValue>0xffffffff</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>DATAIN</name>
+                        <description>Program Burst 128 bit Data Word 0</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_PRGBRST_DATA0_2</name>
+                  <displayName>PRGBRST_DATA0_2</displayName>
+                  <description>Program Burst Data0 Register2</description>
+                  <addressOffset>0x68</addressOffset>
+                  <size>32</size>
+                  <resetValue>0xffffffff</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>DATAIN</name>
+                        <description>Program Burst 128 bit Data Word 0</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_PRGBRST_DATA0_3</name>
+                  <displayName>PRGBRST_DATA0_3</displayName>
+                  <description>Program Burst Data0 Register3</description>
+                  <addressOffset>0x6C</addressOffset>
+                  <size>32</size>
+                  <resetValue>0xffffffff</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>DATAIN</name>
+                        <description>Program Burst 128 bit Data Word 0</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_PRGBRST_DATA1_0</name>
+                  <displayName>PRGBRST_DATA1_0</displayName>
+                  <description>Program Burst Data1 Register0</description>
+                  <addressOffset>0x70</addressOffset>
+                  <size>32</size>
+                  <resetValue>0xffffffff</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>DATAIN</name>
+                        <description>Program Burst 128 bit Data Word 1</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_PRGBRST_DATA1_1</name>
+                  <displayName>PRGBRST_DATA1_1</displayName>
+                  <description>Program Burst Data1 Register1</description>
+                  <addressOffset>0x74</addressOffset>
+                  <size>32</size>
+                  <resetValue>0xffffffff</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>DATAIN</name>
+                        <description>Program Burst 128 bit Data Word 1</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_PRGBRST_DATA1_2</name>
+                  <displayName>PRGBRST_DATA1_2</displayName>
+                  <description>Program Burst Data1 Register2</description>
+                  <addressOffset>0x78</addressOffset>
+                  <size>32</size>
+                  <resetValue>0xffffffff</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>DATAIN</name>
+                        <description>Program Burst 128 bit Data Word 1</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_PRGBRST_DATA1_3</name>
+                  <displayName>PRGBRST_DATA1_3</displayName>
+                  <description>Program Burst Data1 Register3</description>
+                  <addressOffset>0x7C</addressOffset>
+                  <size>32</size>
+                  <resetValue>0xffffffff</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>DATAIN</name>
+                        <description>Program Burst 128 bit Data Word 1</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_PRGBRST_DATA2_0</name>
+                  <displayName>PRGBRST_DATA2_0</displayName>
+                  <description>Program Burst Data2 Register0</description>
+                  <addressOffset>0x80</addressOffset>
+                  <size>32</size>
+                  <resetValue>0xffffffff</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>DATAIN</name>
+                        <description>Program Burst 128 bit Data Word 2</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_PRGBRST_DATA2_1</name>
+                  <displayName>PRGBRST_DATA2_1</displayName>
+                  <description>Program Burst Data2 Register1</description>
+                  <addressOffset>0x84</addressOffset>
+                  <size>32</size>
+                  <resetValue>0xffffffff</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>DATAIN</name>
+                        <description>Program Burst 128 bit Data Word 2</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_PRGBRST_DATA2_2</name>
+                  <displayName>PRGBRST_DATA2_2</displayName>
+                  <description>Program Burst Data2 Register2</description>
+                  <addressOffset>0x88</addressOffset>
+                  <size>32</size>
+                  <resetValue>0xffffffff</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>DATAIN</name>
+                        <description>Program Burst 128 bit Data Word 2</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_PRGBRST_DATA2_3</name>
+                  <displayName>PRGBRST_DATA2_3</displayName>
+                  <description>Program Burst Data2 Register3</description>
+                  <addressOffset>0x8C</addressOffset>
+                  <size>32</size>
+                  <resetValue>0xffffffff</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>DATAIN</name>
+                        <description>Program Burst 128 bit Data Word 2</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_PRGBRST_DATA3_0</name>
+                  <displayName>PRGBRST_DATA3_0</displayName>
+                  <description>Program Burst Data3 Register0</description>
+                  <addressOffset>0x90</addressOffset>
+                  <size>32</size>
+                  <resetValue>0xffffffff</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>DATAIN</name>
+                        <description>Program Burst 128 bit Data Word 3</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_PRGBRST_DATA3_1</name>
+                  <displayName>PRGBRST_DATA3_1</displayName>
+                  <description>Program Burst Data3 Register1</description>
+                  <addressOffset>0x94</addressOffset>
+                  <size>32</size>
+                  <resetValue>0xffffffff</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>DATAIN</name>
+                        <description>Program Burst 128 bit Data Word 3</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_PRGBRST_DATA3_2</name>
+                  <displayName>PRGBRST_DATA3_2</displayName>
+                  <description>Program Burst Data3 Register2</description>
+                  <addressOffset>0x98</addressOffset>
+                  <size>32</size>
+                  <resetValue>0xffffffff</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>DATAIN</name>
+                        <description>Program Burst 128 bit Data Word 3</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_PRGBRST_DATA3_3</name>
+                  <displayName>PRGBRST_DATA3_3</displayName>
+                  <description>Program Burst Data3 Register3</description>
+                  <addressOffset>0x9C</addressOffset>
+                  <size>32</size>
+                  <resetValue>0xffffffff</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>DATAIN</name>
+                        <description>Program Burst 128 bit Data Word 3</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_ERASE_CTLSTAT</name>
+                  <displayName>ERASE_CTLSTAT</displayName>
+                  <description>Erase Control and Status Register</description>
+                  <addressOffset>0xA0</addressOffset>
+                  <size>32</size>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>START</name>
+                        <description>Start of Erase operation</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>MODE</name>
+                        <description>Erase mode selected by application</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>MODE_0</name>
+                                <description>Sector Erase (controlled by FLTCTL_ERASE_SECTADDR)</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>MODE_1</name>
+                                <description>Mass Erase (includes all Main and Information memory sectors that don't have corresponding WE bits set)</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TYPE</name>
+                        <description>Type of memory that erase operation is carried out on</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>TYPE_0</name>
+                                <description>Main Memory</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TYPE_1</name>
+                                <description>Information Memory</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TYPE_3</name>
+                                <description>Engineering Memory</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>STATUS</name>
+                        <description>Status of erase operations in the Flash memory</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>STATUS_0</name>
+                                <description>Idle (no program operation currently active)</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>STATUS_1</name>
+                                <description>Erase operation triggered to START but pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>STATUS_2</name>
+                                <description>Erase operation in progress</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>STATUS_3</name>
+                                <description>Erase operation completed (status of completed erase remains in this state unless explicitly cleared by SW)</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADDR_ERR</name>
+                        <description>Erase Operation was terminated due to attempted erase of reserved memory address</description>
+                        <bitOffset>0x12</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLR_STAT</name>
+                        <description>Clear status bits 18-16 of this register</description>
+                        <bitOffset>0x13</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_ERASE_SECTADDR</name>
+                  <displayName>ERASE_SECTADDR</displayName>
+                  <description>Erase Sector Address Register</description>
+                  <addressOffset>0xA4</addressOffset>
+                  <size>32</size>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>SECT_ADDRESS</name>
+                        <description>Address of Sector being Erased</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x16</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_BANK0_INFO_WEPROT</name>
+                  <displayName>BANK0_INFO_WEPROT</displayName>
+                  <description>Information Memory Bank0 Write/Erase Protection Register</description>
+                  <addressOffset>0xB0</addressOffset>
+                  <size>32</size>
+                  <resetValue>0x00000003</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>PROT0</name>
+                        <description>Protects Sector 0 from program or erase</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT1</name>
+                        <description>Protects Sector 1 from program or erase</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_BANK0_MAIN_WEPROT</name>
+                  <displayName>BANK0_MAIN_WEPROT</displayName>
+                  <description>Main Memory Bank0 Write/Erase Protection Register</description>
+                  <addressOffset>0xB4</addressOffset>
+                  <size>32</size>
+                  <resetValue>0xffffffff</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>PROT0</name>
+                        <description>Protects Sector 0 from program or erase</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT1</name>
+                        <description>Protects Sector 1 from program or erase</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT2</name>
+                        <description>Protects Sector 2 from program or erase</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT3</name>
+                        <description>Protects Sector 3 from program or erase</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT4</name>
+                        <description>Protects Sector 4 from program or erase</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT5</name>
+                        <description>Protects Sector 5 from program or erase</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT6</name>
+                        <description>Protects Sector 6 from program or erase</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT7</name>
+                        <description>Protects Sector 7 from program or erase</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT8</name>
+                        <description>Protects Sector 8 from program or erase</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT9</name>
+                        <description>Protects Sector 9 from program or erase</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT10</name>
+                        <description>Protects Sector 10 from program or erase</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT11</name>
+                        <description>Protects Sector 11 from program or erase</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT12</name>
+                        <description>Protects Sector 12 from program or erase</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT13</name>
+                        <description>Protects Sector 13 from program or erase</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT14</name>
+                        <description>Protects Sector 14 from program or erase</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT15</name>
+                        <description>Protects Sector 15 from program or erase</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT16</name>
+                        <description>Protects Sector 16 from program or erase</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT17</name>
+                        <description>Protects Sector 17 from program or erase</description>
+                        <bitOffset>0x11</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT18</name>
+                        <description>Protects Sector 18 from program or erase</description>
+                        <bitOffset>0x12</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT19</name>
+                        <description>Protects Sector 19 from program or erase</description>
+                        <bitOffset>0x13</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT20</name>
+                        <description>Protects Sector 20 from program or erase</description>
+                        <bitOffset>0x14</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT21</name>
+                        <description>Protects Sector 21 from program or erase</description>
+                        <bitOffset>0x15</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT22</name>
+                        <description>Protects Sector 22 from program or erase</description>
+                        <bitOffset>0x16</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT23</name>
+                        <description>Protects Sector 23 from program or erase</description>
+                        <bitOffset>0x17</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT24</name>
+                        <description>Protects Sector 24 from program or erase</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT25</name>
+                        <description>Protects Sector 25 from program or erase</description>
+                        <bitOffset>0x19</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT26</name>
+                        <description>Protects Sector 26 from program or erase</description>
+                        <bitOffset>0x1A</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT27</name>
+                        <description>Protects Sector 27 from program or erase</description>
+                        <bitOffset>0x1B</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT28</name>
+                        <description>Protects Sector 28 from program or erase</description>
+                        <bitOffset>0x1C</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT29</name>
+                        <description>Protects Sector 29 from program or erase</description>
+                        <bitOffset>0x1D</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT30</name>
+                        <description>Protects Sector 30 from program or erase</description>
+                        <bitOffset>0x1E</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT31</name>
+                        <description>Protects Sector 31 from program or erase</description>
+                        <bitOffset>0x1F</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_BANK1_INFO_WEPROT</name>
+                  <displayName>BANK1_INFO_WEPROT</displayName>
+                  <description>Information Memory Bank1 Write/Erase Protection Register</description>
+                  <addressOffset>0xC0</addressOffset>
+                  <size>32</size>
+                  <resetValue>0x00000003</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>PROT0</name>
+                        <description>Protects Sector 0 from program or erase operations</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT1</name>
+                        <description>Protects Sector 1 from program or erase operations</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_BANK1_MAIN_WEPROT</name>
+                  <displayName>BANK1_MAIN_WEPROT</displayName>
+                  <description>Main Memory Bank1 Write/Erase Protection Register</description>
+                  <addressOffset>0xC4</addressOffset>
+                  <size>32</size>
+                  <resetValue>0xffffffff</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>PROT0</name>
+                        <description>Protects Sector 0 from program or erase operations</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT1</name>
+                        <description>Protects Sector 1 from program or erase operations</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT2</name>
+                        <description>Protects Sector 2 from program or erase operations</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT3</name>
+                        <description>Protects Sector 3 from program or erase operations</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT4</name>
+                        <description>Protects Sector 4 from program or erase operations</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT5</name>
+                        <description>Protects Sector 5 from program or erase operations</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT6</name>
+                        <description>Protects Sector 6 from program or erase operations</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT7</name>
+                        <description>Protects Sector 7 from program or erase operations</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT8</name>
+                        <description>Protects Sector 8 from program or erase operations</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT9</name>
+                        <description>Protects Sector 9 from program or erase operations</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT10</name>
+                        <description>Protects Sector 10 from program or erase operations</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT11</name>
+                        <description>Protects Sector 11 from program or erase operations</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT12</name>
+                        <description>Protects Sector 12 from program or erase operations</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT13</name>
+                        <description>Protects Sector 13 from program or erase operations</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT14</name>
+                        <description>Protects Sector 14 from program or erase operations</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT15</name>
+                        <description>Protects Sector 15 from program or erase operations</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT16</name>
+                        <description>Protects Sector 16 from program or erase operations</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT17</name>
+                        <description>Protects Sector 17 from program or erase operations</description>
+                        <bitOffset>0x11</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT18</name>
+                        <description>Protects Sector 18 from program or erase operations</description>
+                        <bitOffset>0x12</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT19</name>
+                        <description>Protects Sector 19 from program or erase operations</description>
+                        <bitOffset>0x13</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT20</name>
+                        <description>Protects Sector 20 from program or erase operations</description>
+                        <bitOffset>0x14</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT21</name>
+                        <description>Protects Sector 21 from program or erase operations</description>
+                        <bitOffset>0x15</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT22</name>
+                        <description>Protects Sector 22 from program or erase operations</description>
+                        <bitOffset>0x16</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT23</name>
+                        <description>Protects Sector 23 from program or erase operations</description>
+                        <bitOffset>0x17</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT24</name>
+                        <description>Protects Sector 24 from program or erase operations</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT25</name>
+                        <description>Protects Sector 25 from program or erase operations</description>
+                        <bitOffset>0x19</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT26</name>
+                        <description>Protects Sector 26 from program or erase operations</description>
+                        <bitOffset>0x1A</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT27</name>
+                        <description>Protects Sector 27 from program or erase operations</description>
+                        <bitOffset>0x1B</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT28</name>
+                        <description>Protects Sector 28 from program or erase operations</description>
+                        <bitOffset>0x1C</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT29</name>
+                        <description>Protects Sector 29 from program or erase operations</description>
+                        <bitOffset>0x1D</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT30</name>
+                        <description>Protects Sector 30 from program or erase operations</description>
+                        <bitOffset>0x1E</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROT31</name>
+                        <description>Protects Sector 31 from program or erase operations</description>
+                        <bitOffset>0x1F</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_BMRK_CTLSTAT</name>
+                  <displayName>BMRK_CTLSTAT</displayName>
+                  <description>Benchmark Control and Status Register</description>
+                  <addressOffset>0xD0</addressOffset>
+                  <size>32</size>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>I_BMRK</name>
+                        <description>When 1, increments the Instruction Benchmark count register on each instruction fetch to the Flash</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>D_BMRK</name>
+                        <description>When 1, increments the Data Benchmark count register on each data read access to the Flash</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CMP_EN</name>
+                        <description>When 1, enables comparison of the Instruction or Data Benchmark Registers against the threshold value</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CMP_SEL</name>
+                        <description>Selects which benchmark register should be compared against the threshold</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_1_0x0</name>
+                                <description>Compares the Instruction Benchmark Register against the threshold value</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_2_0x1</name>
+                                <description>Compares the Data Benchmark Register against the threshold value</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_BMRK_IFETCH</name>
+                  <displayName>BMRK_IFETCH</displayName>
+                  <description>Benchmark Instruction Fetch Count Register</description>
+                  <addressOffset>0xD4</addressOffset>
+                  <size>32</size>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>COUNT</name>
+                        <description>Reflects the number of Instruction Fetches to the Flash (increments by one on each fetch)</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_BMRK_DREAD</name>
+                  <displayName>BMRK_DREAD</displayName>
+                  <description>Benchmark Data Read Count Register</description>
+                  <addressOffset>0xD8</addressOffset>
+                  <size>32</size>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>COUNT</name>
+                        <description>Reflects the number of Data Read operations to the Flash (increments by one on each read)</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_BMRK_CMP</name>
+                  <displayName>BMRK_CMP</displayName>
+                  <description>Benchmark Count Compare Register</description>
+                  <addressOffset>0xDC</addressOffset>
+                  <size>32</size>
+                  <resetValue>0x00010000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>COUNT</name>
+                        <description>Reflects the threshold value that is compared against either the IFETCH or DREAD Benchmark Counters</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_IFG</name>
+                  <displayName>IFG</displayName>
+                  <description>Interrupt Flag Register</description>
+                  <addressOffset>0xF0</addressOffset>
+                  <size>32</size>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>RDBRST</name>
+                        <description>If set to 1, indicates that the Read Burst/Compare operation is complete</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>AVPRE</name>
+                        <description>If set to 1, indicates that the pre-program verify operation has detected an error</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>AVPST</name>
+                        <description>If set to 1, indicates that the post-program verify operation has failed comparison</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PRG</name>
+                        <description>If set to 1, indicates that a word Program operation is complete</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PRGB</name>
+                        <description>If set to 1, indicates that the configured Burst Program operation is complete</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ERASE</name>
+                        <description>If set to 1, indicates that the Erase operation is complete</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BMRK</name>
+                        <description>If set to 1, indicates that a Benchmark Compare match occurred</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PRG_ERR</name>
+                        <description>If set to 1, indicates a word composition error in full word write mode (possible data loss due to writes crossing over to a new 128bit boundary before full word has been composed)</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_IE</name>
+                  <displayName>IE</displayName>
+                  <description>Interrupt Enable Register</description>
+                  <addressOffset>0xF4</addressOffset>
+                  <size>32</size>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>RDBRST</name>
+                        <description>If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVPRE</name>
+                        <description>If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVPST</name>
+                        <description>If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRG</name>
+                        <description>If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRGB</name>
+                        <description>If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ERASE</name>
+                        <description>If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BMRK</name>
+                        <description>If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRG_ERR</name>
+                        <description>If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_CLRIFG</name>
+                  <displayName>CLRIFG</displayName>
+                  <description>Clear Interrupt Flag Register</description>
+                  <addressOffset>0xF8</addressOffset>
+                  <size>32</size>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>RDBRST</name>
+                        <description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>AVPRE</name>
+                        <description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>AVPST</name>
+                        <description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>PRG</name>
+                        <description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>PRGB</name>
+                        <description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>ERASE</name>
+                        <description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>BMRK</name>
+                        <description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>PRG_ERR</name>
+                        <description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_SETIFG</name>
+                  <displayName>SETIFG</displayName>
+                  <description>Set Interrupt Flag Register</description>
+                  <addressOffset>0xFC</addressOffset>
+                  <size>32</size>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>RDBRST</name>
+                        <description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>AVPRE</name>
+                        <description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>AVPST</name>
+                        <description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>PRG</name>
+                        <description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>PRGB</name>
+                        <description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>ERASE</name>
+                        <description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>BMRK</name>
+                        <description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>PRG_ERR</name>
+                        <description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_READ_TIMCTL</name>
+                  <displayName>READ_TIMCTL</displayName>
+                  <description>Read Timing Control Register</description>
+                  <addressOffset>0x100</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <fields>
+                    <field>
+                        <name>SETUP</name>
+                        <description>Configures the length of the Setup phase for this operation</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IREF_BOOST1</name>
+                        <description>Length of the IREF_BOOST1 signal of the IP</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SETUP_LONG</name>
+                        <description>Length of the Setup time into read mode when the device is recovering from one of the following conditions: Moving from Power-down or Standby back to Active and device is not trimmed. Moving from standby to active state in low-frequency active mode. Recovering from the LDO Boost operation after a Mass Erase.</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_READMARGIN_TIMCTL</name>
+                  <displayName>READMARGIN_TIMCTL</displayName>
+                  <description>Read Margin Timing Control Register</description>
+                  <addressOffset>0x104</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <fields>
+                    <field>
+                        <name>SETUP</name>
+                        <description>Length of the Setup phase for this operation</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_PRGVER_TIMCTL</name>
+                  <displayName>PRGVER_TIMCTL</displayName>
+                  <description>Program Verify Timing Control Register</description>
+                  <addressOffset>0x108</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <fields>
+                    <field>
+                        <name>SETUP</name>
+                        <description>Length of the Setup phase for this operation</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ACTIVE</name>
+                        <description>Length of the Active phase for this operation</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HOLD</name>
+                        <description>Length of the Hold phase for this operation</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_ERSVER_TIMCTL</name>
+                  <displayName>ERSVER_TIMCTL</displayName>
+                  <description>Erase Verify Timing Control Register</description>
+                  <addressOffset>0x10C</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <fields>
+                    <field>
+                        <name>SETUP</name>
+                        <description>Length of the Setup phase for this operation</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_LKGVER_TIMCTL</name>
+                  <displayName>LKGVER_TIMCTL</displayName>
+                  <description>Leakage Verify Timing Control Register</description>
+                  <addressOffset>0x110</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <fields>
+                    <field>
+                        <name>SETUP</name>
+                        <description>Length of the Setup phase for this operation</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_PROGRAM_TIMCTL</name>
+                  <displayName>PROGRAM_TIMCTL</displayName>
+                  <description>Program Timing Control Register</description>
+                  <addressOffset>0x114</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <fields>
+                    <field>
+                        <name>SETUP</name>
+                        <description>Length of the Setup phase for this operation</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ACTIVE</name>
+                        <description>Length of the Active phase for this operation</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x14</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HOLD</name>
+                        <description>Length of the Hold phase for this operation</description>
+                        <bitOffset>0x1C</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_ERASE_TIMCTL</name>
+                  <displayName>ERASE_TIMCTL</displayName>
+                  <description>Erase Timing Control Register</description>
+                  <addressOffset>0x118</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <fields>
+                    <field>
+                        <name>SETUP</name>
+                        <description>Length of the Setup phase for this operation</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ACTIVE</name>
+                        <description>Length of the Active phase for this operation</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x14</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HOLD</name>
+                        <description>Length of the Hold phase for this operation</description>
+                        <bitOffset>0x1C</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_MASSERASE_TIMCTL</name>
+                  <displayName>MASSERASE_TIMCTL</displayName>
+                  <description>Mass Erase Timing Control Register</description>
+                  <addressOffset>0x11C</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <fields>
+                    <field>
+                        <name>BOOST_ACTIVE</name>
+                        <description>Length of the time for which LDO Boost Signal is kept active</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BOOST_HOLD</name>
+                        <description>Length for which Flash deactivates the LDO Boost signal before processing any new commands</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FLCTL_BURSTPRG_TIMCTL</name>
+                  <displayName>BURSTPRG_TIMCTL</displayName>
+                  <description>Burst Program Timing Control Register</description>
+                  <addressOffset>0x120</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <fields>
+                    <field>
+                        <name>ACTIVE</name>
+                        <description>Length of the Active phase for this operation</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x14</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>ADC14</name>
+        <version>356.0</version>
+        <description>ADC14</description>
+        <baseAddress>0x40012000</baseAddress>
+        <interrupt>
+            <name>ADC14_IRQ</name>
+            <description>ADC14 Interrupt</description>
+            <value>24</value>
+        </interrupt>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x158</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>ADC14CTL0</name>
+                  <displayName>CTL0</displayName>
+                  <description>Control 0 Register</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>ADC14SC</name>
+                        <description>ADC14 start conversion</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14SC_0</name>
+                                <description>No sample-and-conversion-start</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14SC_1</name>
+                                <description>Start sample-and-conversion</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14ENC</name>
+                        <description>ADC14 enable conversion</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14ENC_0</name>
+                                <description>ADC14 disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14ENC_1</name>
+                                <description>ADC14 enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14ON</name>
+                        <description>ADC14 on</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14ON_0</name>
+                                <description>ADC14 off</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14ON_1</name>
+                                <description>ADC14 on. ADC core is ready to power up when a valid conversion is triggered.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14MSC</name>
+                        <description>ADC14 multiple sample and conversion</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14MSC_0</name>
+                                <description>The sampling timer requires a rising edge of the SHI signal to trigger each sample-and-convert</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14MSC_1</name>
+                                <description>The first rising edge of the SHI signal triggers the sampling timer, but further sample-and-conversions are performed automatically as soon as the prior conversion is completed</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14SHT0</name>
+                        <description>ADC14 sample-and-hold time</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14SHT0_0</name>
+                                <description>4</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14SHT0_1</name>
+                                <description>8</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14SHT0_2</name>
+                                <description>16</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14SHT0_3</name>
+                                <description>32</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14SHT0_4</name>
+                                <description>64</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14SHT0_5</name>
+                                <description>96</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14SHT0_6</name>
+                                <description>128</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14SHT0_7</name>
+                                <description>192</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14SHT1</name>
+                        <description>ADC14 sample-and-hold time</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14SHT1_0</name>
+                                <description>4</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14SHT1_1</name>
+                                <description>8</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14SHT1_2</name>
+                                <description>16</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14SHT1_3</name>
+                                <description>32</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14SHT1_4</name>
+                                <description>64</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14SHT1_5</name>
+                                <description>96</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14SHT1_6</name>
+                                <description>128</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14SHT1_7</name>
+                                <description>192</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14BUSY</name>
+                        <description>ADC14 busy</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14BUSY_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14BUSY_0</name>
+                                <description>No operation is active</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14BUSY_1</name>
+                                <description>A sequence, sample, or conversion is active</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14CONSEQ</name>
+                        <description>ADC14 conversion sequence mode select</description>
+                        <bitOffset>0x11</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14CONSEQ_0</name>
+                                <description>Single-channel, single-conversion</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14CONSEQ_1</name>
+                                <description>Sequence-of-channels</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14CONSEQ_2</name>
+                                <description>Repeat-single-channel</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14CONSEQ_3</name>
+                                <description>Repeat-sequence-of-channels</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14SSEL</name>
+                        <description>ADC14 clock source select</description>
+                        <bitOffset>0x13</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14SSEL_0</name>
+                                <description>MODCLK</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14SSEL_1</name>
+                                <description>SYSCLK</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14SSEL_2</name>
+                                <description>ACLK</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14SSEL_3</name>
+                                <description>MCLK</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14SSEL_4</name>
+                                <description>SMCLK</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14SSEL_5</name>
+                                <description>HSMCLK</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14DIV</name>
+                        <description>ADC14 clock divider</description>
+                        <bitOffset>0x16</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14DIV_0</name>
+                                <description>/1</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14DIV_1</name>
+                                <description>/2</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14DIV_2</name>
+                                <description>/3</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14DIV_3</name>
+                                <description>/4</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14DIV_4</name>
+                                <description>/5</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14DIV_5</name>
+                                <description>/6</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14DIV_6</name>
+                                <description>/7</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14DIV_7</name>
+                                <description>/8</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14ISSH</name>
+                        <description>ADC14 invert signal sample-and-hold</description>
+                        <bitOffset>0x19</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14ISSH_0</name>
+                                <description>The sample-input signal is not inverted</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14ISSH_1</name>
+                                <description>The sample-input signal is inverted</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14SHP</name>
+                        <description>ADC14 sample-and-hold pulse-mode select</description>
+                        <bitOffset>0x1A</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14SHP_0</name>
+                                <description>SAMPCON signal is sourced from the sample-input signal</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14SHP_1</name>
+                                <description>SAMPCON signal is sourced from the sampling timer</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14SHS</name>
+                        <description>ADC14 sample-and-hold source select</description>
+                        <bitOffset>0x1B</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14SHS_0</name>
+                                <description>ADC14SC bit</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14SHS_1</name>
+                                <description>See device-specific data sheet for source</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14SHS_2</name>
+                                <description>See device-specific data sheet for source</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14SHS_3</name>
+                                <description>See device-specific data sheet for source</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14SHS_4</name>
+                                <description>See device-specific data sheet for source</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14SHS_5</name>
+                                <description>See device-specific data sheet for source</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14SHS_6</name>
+                                <description>See device-specific data sheet for source</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14SHS_7</name>
+                                <description>See device-specific data sheet for source</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14PDIV</name>
+                        <description>ADC14 predivider</description>
+                        <bitOffset>0x1E</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14PDIV_0</name>
+                                <description>Predivide by 1</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14PDIV_1</name>
+                                <description>Predivide by 4</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14PDIV_2</name>
+                                <description>Predivide by 32</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14PDIV_3</name>
+                                <description>Predivide by 64</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>ADC14CTL1</name>
+                  <displayName>CTL1</displayName>
+                  <description>Control 1 Register</description>
+                  <addressOffset>0x4</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000030</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>ADC14PWRMD</name>
+                        <description>ADC14 power modes</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14PWRMD_0</name>
+                                <description>Regular power mode for use with any resolution setting. Sample rate can be up to 1 Msps.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14PWRMD_2</name>
+                                <description>Low-power mode for 12-bit, 10-bit, and 8-bit resolution settings. Sample rate must not exceed 200 ksps.</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14REFBURST</name>
+                        <description>ADC14 reference buffer burst</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14REFBURST_0</name>
+                                <description>ADC reference buffer on continuously</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14REFBURST_1</name>
+                                <description>ADC reference buffer on only during sample-and-conversion</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14DF</name>
+                        <description>ADC14 data read-back format</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14DF_0</name>
+                                <description>Binary unsigned. Theoretically, for ADC14DIF = 0 and 14-bit mode, the analog input voltage - V(REF) results in 0000h, and the analog input voltage + V(REF) results in 3FFFh</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14DF_1</name>
+                                <description>Signed binary (2s complement), left aligned. Theoretically, for ADC14DIF = 0 and 14-bit mode, the analog input voltage - V(REF) results in 8000h, and the analog input voltage + V(REF) results in 7FFCh</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14RES</name>
+                        <description>ADC14 resolution</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14RES_0</name>
+                                <description>8 bit (9 clock cycle conversion time)</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14RES_1</name>
+                                <description>10 bit (11 clock cycle conversion time)</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14RES_2</name>
+                                <description>12 bit (14 clock cycle conversion time)</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14RES_3</name>
+                                <description>14 bit (16 clock cycle conversion time)</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14CSTARTADD</name>
+                        <description>ADC14 conversion start address</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x5</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADC14BATMAP</name>
+                        <description>Controls 1/2 AVCC ADC input channel selection</description>
+                        <bitOffset>0x16</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14BATMAP_0</name>
+                                <description>ADC internal 1/2 x AVCC channel is not selected for ADC</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14BATMAP_1</name>
+                                <description>ADC internal 1/2 x AVCC channel is selected for ADC input channel MAX</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14TCMAP</name>
+                        <description>Controls temperature sensor ADC input channel selection</description>
+                        <bitOffset>0x17</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14TCMAP_0</name>
+                                <description>ADC internal temperature sensor channel is not selected for ADC</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14TCMAP_1</name>
+                                <description>ADC internal temperature sensor channel is selected for ADC input channel MAX-1</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14CH0MAP</name>
+                        <description>Controls internal channel 0 selection to ADC input channel MAX-2</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14CH0MAP_0</name>
+                                <description>ADC input channel internal 0 is not selected</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14CH0MAP_1</name>
+                                <description>ADC input channel internal 0 is selected for ADC input channel MAX-2</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14CH1MAP</name>
+                        <description>Controls internal channel 1 selection to ADC input channel MAX-3</description>
+                        <bitOffset>0x19</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14CH1MAP_0</name>
+                                <description>ADC input channel internal 1 is not selected</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14CH1MAP_1</name>
+                                <description>ADC input channel internal 1 is selected for ADC input channel MAX-3</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14CH2MAP</name>
+                        <description>Controls internal channel 2 selection to ADC input channel MAX-4</description>
+                        <bitOffset>0x1A</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14CH2MAP_0</name>
+                                <description>ADC input channel internal 2 is not selected</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14CH2MAP_1</name>
+                                <description>ADC input channel internal 2 is selected for ADC input channel MAX-4</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14CH3MAP</name>
+                        <description>Controls internal channel 3 selection to ADC input channel MAX-5</description>
+                        <bitOffset>0x1B</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14CH3MAP_0</name>
+                                <description>ADC input channel internal 3 is not selected</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14CH3MAP_1</name>
+                                <description>ADC input channel internal 3 is selected for ADC input channel MAX-5</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>ADC14LO0</name>
+                  <displayName>LO0</displayName>
+                  <description>Window Comparator Low Threshold 0 Register</description>
+                  <addressOffset>0x8</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>ADC14LO0</name>
+                        <description>Low threshold 0</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>ADC14HI0</name>
+                  <displayName>HI0</displayName>
+                  <description>Window Comparator High Threshold 0 Register</description>
+                  <addressOffset>0xC</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00003fff</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>ADC14HI0</name>
+                        <description>High threshold 0</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>ADC14LO1</name>
+                  <displayName>LO1</displayName>
+                  <description>Window Comparator Low Threshold 1 Register</description>
+                  <addressOffset>0x10</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>ADC14LO1</name>
+                        <description>Low threshold 1</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>ADC14HI1</name>
+                  <displayName>HI1</displayName>
+                  <description>Window Comparator High Threshold 1 Register</description>
+                  <addressOffset>0x14</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00003fff</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>ADC14HI1</name>
+                        <description>High threshold 1</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <dim>32</dim>
+                  <dimIncrement>4</dimIncrement>
+                  <dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31</dimIndex>
+                  <name>ADC14MCTL[%s]</name>
+                  <displayName>MCTL[%s]</displayName>
+                  <description>Conversion Memory Control Register</description>
+                  <addressOffset>0x18</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>ADC14INCH</name>
+                        <description>Input channel select</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x5</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14INCH_0</name>
+                                <description>If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INCH_1</name>
+                                <description>If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INCH_2</name>
+                                <description>If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INCH_3</name>
+                                <description>If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INCH_4</name>
+                                <description>If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INCH_5</name>
+                                <description>If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INCH_6</name>
+                                <description>If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INCH_7</name>
+                                <description>If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INCH_8</name>
+                                <description>If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INCH_9</name>
+                                <description>If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9</description>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INCH_10</name>
+                                <description>If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INCH_11</name>
+                                <description>If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11</description>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INCH_12</name>
+                                <description>If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INCH_13</name>
+                                <description>If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13</description>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INCH_14</name>
+                                <description>If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INCH_15</name>
+                                <description>If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15</description>
+                                <value>15</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INCH_16</name>
+                                <description>If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17</description>
+                                <value>16</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INCH_17</name>
+                                <description>If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17</description>
+                                <value>17</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INCH_18</name>
+                                <description>If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19</description>
+                                <value>18</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INCH_19</name>
+                                <description>If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19</description>
+                                <value>19</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INCH_20</name>
+                                <description>If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21</description>
+                                <value>20</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INCH_21</name>
+                                <description>If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21</description>
+                                <value>21</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INCH_22</name>
+                                <description>If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23</description>
+                                <value>22</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INCH_23</name>
+                                <description>If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23</description>
+                                <value>23</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INCH_24</name>
+                                <description>If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25</description>
+                                <value>24</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INCH_25</name>
+                                <description>If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25</description>
+                                <value>25</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INCH_26</name>
+                                <description>If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27</description>
+                                <value>26</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INCH_27</name>
+                                <description>If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27</description>
+                                <value>27</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INCH_28</name>
+                                <description>If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29</description>
+                                <value>28</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INCH_29</name>
+                                <description>If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29</description>
+                                <value>29</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INCH_30</name>
+                                <description>If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31</description>
+                                <value>30</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INCH_31</name>
+                                <description>If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31</description>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14EOS</name>
+                        <description>End of sequence</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14EOS_0</name>
+                                <description>Not end of sequence</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14EOS_1</name>
+                                <description>End of sequence</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14VRSEL</name>
+                        <description>Selects combinations of V(R+) and V(R-) sources</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14VRSEL_0</name>
+                                <description>V(R+) = AVCC, V(R-) = AVSS</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14VRSEL_1</name>
+                                <description>V(R+) = VREF buffered, V(R-) = AVSS</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14VRSEL_14</name>
+                                <description>V(R+) = VeREF+, V(R-) = VeREF-</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14VRSEL_15</name>
+                                <description>V(R+) = VeREF+ buffered, V(R-) = VeREF</description>
+                                <value>15</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14DIF</name>
+                        <description>Differential mode</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14DIF_0</name>
+                                <description>Single-ended mode enabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14DIF_1</name>
+                                <description>Differential mode enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14WINC</name>
+                        <description>Comparator window enable</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14WINC_0</name>
+                                <description>Comparator window disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14WINC_1</name>
+                                <description>Comparator window enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14WINCTH</name>
+                        <description>Window comparator threshold register selection</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14WINCTH_0</name>
+                                <description>Use window comparator thresholds 0, ADC14LO0 and ADC14HI0</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14WINCTH_1</name>
+                                <description>Use window comparator thresholds 1, ADC14LO1 and ADC14HI1</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <dim>32</dim>
+                  <dimIncrement>4</dimIncrement>
+                  <dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31</dimIndex>
+                  <name>ADC14MEM[%s]</name>
+                  <displayName>MEM[%s]</displayName>
+                  <description>Conversion Memory Register</description>
+                  <addressOffset>0x98</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000000</resetMask>
+                  <fields>
+                    <field>
+                        <name>Conversion_Results</name>
+                        <description>Conversion Result</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>ADC14IER0</name>
+                  <displayName>IER0</displayName>
+                  <description>Interrupt Enable 0 Register</description>
+                  <addressOffset>0x13C</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>ADC14IE0</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE0_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE0_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IE1</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE1_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE1_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IE2</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE2_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE2_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IE3</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE3_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE3_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IE4</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE4_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE4_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IE5</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE5_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE5_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IE6</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE6_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE6_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IE7</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE7_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE7_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IE8</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE8_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE8_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IE9</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE9_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE9_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IE10</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE10_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE10_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IE11</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE11_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE11_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IE12</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE12_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE12_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IE13</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE13_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE13_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IE14</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE14_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE14_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IE15</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE15_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE15_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IE16</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE16_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE16_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IE17</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0x11</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE17_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE17_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IE19</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0x13</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE19_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE19_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IE18</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0x12</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE18_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE18_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IE20</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0x14</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE20_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE20_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IE21</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0x15</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE21_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE21_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IE22</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0x16</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE22_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE22_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IE23</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0x17</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE23_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE23_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IE24</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE24_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE24_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IE25</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0x19</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE25_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE25_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IE26</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0x1A</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE26_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE26_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IE27</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0x1B</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE27_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE27_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IE28</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0x1C</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE28_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE28_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IE29</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0x1D</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE29_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE29_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IE30</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0x1E</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE30_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE30_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IE31</name>
+                        <description>Interrupt enable</description>
+                        <bitOffset>0x1F</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IE31_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IE31_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>ADC14IER1</name>
+                  <displayName>IER1</displayName>
+                  <description>Interrupt Enable 1 Register</description>
+                  <addressOffset>0x140</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>ADC14INIE</name>
+                        <description>Interrupt enable for ADC14MEMx within comparator window</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14INIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14LOIE</name>
+                        <description>Interrupt enable for ADC14MEMx below comparator window</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14LOIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14LOIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14HIIE</name>
+                        <description>Interrupt enable for ADC14MEMx above comparator window</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14HIIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14HIIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14OVIE</name>
+                        <description>ADC14MEMx overflow-interrupt enable</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14OVIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14OVIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14TOVIE</name>
+                        <description>ADC14 conversion-time-overflow interrupt enable</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14TOVIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14TOVIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14RDYIE</name>
+                        <description>ADC14 local buffered reference ready interrupt enable</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14RDYIE_0</name>
+                                <description>Interrupt disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14RDYIE_1</name>
+                                <description>Interrupt enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>ADC14IFGR0</name>
+                  <displayName>IFGR0</displayName>
+                  <description>Interrupt Flag 0 Register</description>
+                  <addressOffset>0x144</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>ADC14IFG0</name>
+                        <description>ADC14MEM0 interrupt flag</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG0_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG0_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG0_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IFG1</name>
+                        <description>ADC14MEM1 interrupt flag</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG1_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG1_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG1_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IFG2</name>
+                        <description>ADC14MEM2 interrupt flag</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG2_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG2_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG2_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IFG3</name>
+                        <description>ADC14MEM3 interrupt flag</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG3_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG3_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG3_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IFG4</name>
+                        <description>ADC14MEM4 interrupt flag</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG4_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG4_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG4_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IFG5</name>
+                        <description>ADC14MEM5 interrupt flag</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG5_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG5_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG5_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IFG6</name>
+                        <description>ADC14MEM6 interrupt flag</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG6_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG6_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG6_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IFG7</name>
+                        <description>ADC14MEM7 interrupt flag</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG7_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG7_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG7_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IFG8</name>
+                        <description>ADC14MEM8 interrupt flag</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG8_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG8_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG8_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IFG9</name>
+                        <description>ADC14MEM9 interrupt flag</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG9_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG9_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG9_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IFG10</name>
+                        <description>ADC14MEM10 interrupt flag</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG10_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG10_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG10_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IFG11</name>
+                        <description>ADC14MEM11 interrupt flag</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG11_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG11_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG11_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IFG12</name>
+                        <description>ADC14MEM12 interrupt flag</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG12_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG12_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG12_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IFG13</name>
+                        <description>ADC14MEM13 interrupt flag</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG13_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG13_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG13_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IFG14</name>
+                        <description>ADC14MEM14 interrupt flag</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG14_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG14_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG14_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IFG15</name>
+                        <description>ADC14MEM15 interrupt flag</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG15_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG15_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG15_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IFG16</name>
+                        <description>ADC14MEM16 interrupt flag</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG16_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG16_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG16_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IFG17</name>
+                        <description>ADC14MEM17 interrupt flag</description>
+                        <bitOffset>0x11</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG17_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG17_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG17_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IFG18</name>
+                        <description>ADC14MEM18 interrupt flag</description>
+                        <bitOffset>0x12</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG18_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG18_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG18_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IFG19</name>
+                        <description>ADC14MEM19 interrupt flag</description>
+                        <bitOffset>0x13</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG19_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG19_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG19_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IFG20</name>
+                        <description>ADC14MEM20 interrupt flag</description>
+                        <bitOffset>0x14</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG20_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG20_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG20_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IFG21</name>
+                        <description>ADC14MEM21 interrupt flag</description>
+                        <bitOffset>0x15</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG21_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG21_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG21_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IFG22</name>
+                        <description>ADC14MEM22 interrupt flag</description>
+                        <bitOffset>0x16</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG22_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG22_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG22_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IFG23</name>
+                        <description>ADC14MEM23 interrupt flag</description>
+                        <bitOffset>0x17</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG23_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG23_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG23_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IFG24</name>
+                        <description>ADC14MEM24 interrupt flag</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG24_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG24_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG24_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IFG25</name>
+                        <description>ADC14MEM25 interrupt flag</description>
+                        <bitOffset>0x19</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG25_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG25_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG25_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IFG26</name>
+                        <description>ADC14MEM26 interrupt flag</description>
+                        <bitOffset>0x1A</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG26_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG26_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG26_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IFG27</name>
+                        <description>ADC14MEM27 interrupt flag</description>
+                        <bitOffset>0x1B</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG27_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG27_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG27_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IFG28</name>
+                        <description>ADC14MEM28 interrupt flag</description>
+                        <bitOffset>0x1C</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG28_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG28_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG28_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IFG29</name>
+                        <description>ADC14MEM29 interrupt flag</description>
+                        <bitOffset>0x1D</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG29_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG29_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG29_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IFG30</name>
+                        <description>ADC14MEM30 interrupt flag</description>
+                        <bitOffset>0x1E</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG30_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG30_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG30_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14IFG31</name>
+                        <description>ADC14MEM31 interrupt flag</description>
+                        <bitOffset>0x1F</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14IFG31_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14IFG31_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IFG31_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>ADC14IFGR1</name>
+                  <displayName>IFGR1</displayName>
+                  <description>Interrupt Flag 1 Register</description>
+                  <addressOffset>0x148</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>ADC14INIFG</name>
+                        <description>Interrupt flag for ADC14MEMx within comparator window</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14INIFG_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14INIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14INIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14LOIFG</name>
+                        <description>Interrupt flag for ADC14MEMx below comparator window</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14LOIFG_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14LOIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14LOIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14HIIFG</name>
+                        <description>Interrupt flag for ADC14MEMx above comparator window</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14HIIFG_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14HIIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14HIIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14OVIFG</name>
+                        <description>ADC14MEMx overflow interrupt flag</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14OVIFG_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14OVIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14OVIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14TOVIFG</name>
+                        <description>ADC14 conversion time overflow interrupt flag</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14TOVIFG_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14TOVIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14TOVIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADC14RDYIFG</name>
+                        <description>ADC14 local buffered reference ready interrupt flag</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>ADC14RDYIFG_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>ADC14RDYIFG_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14RDYIFG_1</name>
+                                <description>Interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>ADC14CLRIFGR0</name>
+                  <displayName>CLRIFGR0</displayName>
+                  <description>Clear Interrupt Flag 0 Register</description>
+                  <addressOffset>0x14C</addressOffset>
+                  <size>32</size>
+                  <access>write-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CLRADC14IFG0</name>
+                        <description>clear ADC14IFG0</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG0_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG0_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG0_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14IFG1</name>
+                        <description>clear ADC14IFG1</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG1_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG1_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG1_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14IFG2</name>
+                        <description>clear ADC14IFG2</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG2_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG2_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG2_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14IFG3</name>
+                        <description>clear ADC14IFG3</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG3_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG3_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG3_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14IFG4</name>
+                        <description>clear ADC14IFG4</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG4_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG4_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG4_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14IFG5</name>
+                        <description>clear ADC14IFG5</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG5_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG5_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG5_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14IFG6</name>
+                        <description>clear ADC14IFG6</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG6_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG6_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG6_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14IFG7</name>
+                        <description>clear ADC14IFG7</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG7_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG7_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG7_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14IFG8</name>
+                        <description>clear ADC14IFG8</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG8_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG8_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG8_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14IFG9</name>
+                        <description>clear ADC14IFG9</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG9_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG9_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG9_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14IFG10</name>
+                        <description>clear ADC14IFG10</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG10_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG10_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG10_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14IFG11</name>
+                        <description>clear ADC14IFG11</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG11_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG11_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG11_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14IFG12</name>
+                        <description>clear ADC14IFG12</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG12_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG12_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG12_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14IFG13</name>
+                        <description>clear ADC14IFG13</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG13_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG13_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG13_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14IFG14</name>
+                        <description>clear ADC14IFG14</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG14_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG14_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG14_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14IFG15</name>
+                        <description>clear ADC14IFG15</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG15_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG15_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG15_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14IFG16</name>
+                        <description>clear ADC14IFG16</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG16_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG16_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG16_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14IFG17</name>
+                        <description>clear ADC14IFG17</description>
+                        <bitOffset>0x11</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG17_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG17_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG17_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14IFG18</name>
+                        <description>clear ADC14IFG18</description>
+                        <bitOffset>0x12</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG18_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG18_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG18_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14IFG19</name>
+                        <description>clear ADC14IFG19</description>
+                        <bitOffset>0x13</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG19_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG19_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG19_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14IFG20</name>
+                        <description>clear ADC14IFG20</description>
+                        <bitOffset>0x14</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG20_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG20_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG20_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14IFG21</name>
+                        <description>clear ADC14IFG21</description>
+                        <bitOffset>0x15</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG21_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG21_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG21_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14IFG22</name>
+                        <description>clear ADC14IFG22</description>
+                        <bitOffset>0x16</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG22_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG22_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG22_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14IFG23</name>
+                        <description>clear ADC14IFG23</description>
+                        <bitOffset>0x17</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG23_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG23_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG23_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14IFG24</name>
+                        <description>clear ADC14IFG24</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG24_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG24_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG24_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14IFG25</name>
+                        <description>clear ADC14IFG25</description>
+                        <bitOffset>0x19</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG25_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG25_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG25_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14IFG26</name>
+                        <description>clear ADC14IFG26</description>
+                        <bitOffset>0x1A</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG26_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG26_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG26_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14IFG27</name>
+                        <description>clear ADC14IFG27</description>
+                        <bitOffset>0x1B</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG27_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG27_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG27_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14IFG28</name>
+                        <description>clear ADC14IFG28</description>
+                        <bitOffset>0x1C</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG28_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG28_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG28_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14IFG29</name>
+                        <description>clear ADC14IFG29</description>
+                        <bitOffset>0x1D</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG29_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG29_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG29_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14IFG30</name>
+                        <description>clear ADC14IFG30</description>
+                        <bitOffset>0x1E</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG30_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG30_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG30_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14IFG31</name>
+                        <description>clear ADC14IFG31</description>
+                        <bitOffset>0x1F</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14IFG31_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG31_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14IFG31_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>ADC14CLRIFGR1</name>
+                  <displayName>CLRIFGR1</displayName>
+                  <description>Clear Interrupt Flag 1 Register</description>
+                  <addressOffset>0x150</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CLRADC14INIFG</name>
+                        <description>clear ADC14INIFG</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14INIFG_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14INIFG_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14INIFG_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14LOIFG</name>
+                        <description>clear ADC14LOIFG</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14LOIFG_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14LOIFG_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14LOIFG_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14HIIFG</name>
+                        <description>clear ADC14HIIFG</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14HIIFG_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14HIIFG_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14HIIFG_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14OVIFG</name>
+                        <description>clear ADC14OVIFG</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14OVIFG_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14OVIFG_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14OVIFG_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14TOVIFG</name>
+                        <description>clear ADC14TOVIFG</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14TOVIFG_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14TOVIFG_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14TOVIFG_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLRADC14RDYIFG</name>
+                        <description>clear ADC14RDYIFG</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <name>CLRADC14RDYIFG_enum_write</name>
+                            <usage>write</usage>
+                            <enumeratedValue>
+                                <name>CLRADC14RDYIFG_0</name>
+                                <description>no effect</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLRADC14RDYIFG_1</name>
+                                <description>clear pending interrupt flag</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>ADC14IV</name>
+                  <displayName>IV</displayName>
+                  <description>Interrupt Vector Register</description>
+                  <addressOffset>0x154</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>ADC14IV</name>
+                        <description>ADC14 interrupt vector value</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADC14IV_0</name>
+                                <description>No interrupt pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_2</name>
+                                <description>Interrupt Source: ADC14MEMx overflow; Interrupt Flag: ADC14OVIFG; Interrupt Priority: Highest</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_4</name>
+                                <description>Interrupt Source: Conversion time overflow; Interrupt Flag: ADC14TOVIFG</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_6</name>
+                                <description>Interrupt Source: ADC14 window high interrupt flag; Interrupt Flag: ADC14HIIFG</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_8</name>
+                                <description>Interrupt Source: ADC14 window low interrupt flag; Interrupt Flag: ADC14LOIFG</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_10</name>
+                                <description>Interrupt Source: ADC14 in-window interrupt flag; Interrupt Flag: ADC14INIFG</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_12</name>
+                                <description>Interrupt Source: ADC14MEM0 interrupt flag; Interrupt Flag: ADC14IFG0</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_14</name>
+                                <description>Interrupt Source: ADC14MEM1 interrupt flag; Interrupt Flag: ADC14IFG1</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_16</name>
+                                <description>Interrupt Source: ADC14MEM2 interrupt flag; Interrupt Flag: ADC14IFG2</description>
+                                <value>16</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_18</name>
+                                <description>Interrupt Source: ADC14MEM3 interrupt flag; Interrupt Flag: ADC14IFG3</description>
+                                <value>18</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_20</name>
+                                <description>Interrupt Source: ADC14MEM4 interrupt flag; Interrupt Flag: ADC14IFG4</description>
+                                <value>20</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_22</name>
+                                <description>Interrupt Source: ADC14MEM5 interrupt flag; Interrupt Flag: ADC14IFG5</description>
+                                <value>22</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_24</name>
+                                <description>Interrupt Source: ADC14MEM6 interrupt flag; Interrupt Flag: ADC14IFG6</description>
+                                <value>24</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_26</name>
+                                <description>Interrupt Source: ADC14MEM7 interrupt flag; Interrupt Flag: ADC14IFG7</description>
+                                <value>26</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_28</name>
+                                <description>Interrupt Source: ADC14MEM8 interrupt flag; Interrupt Flag: ADC14IFG8</description>
+                                <value>28</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_30</name>
+                                <description>Interrupt Source: ADC14MEM9 interrupt flag; Interrupt Flag: ADC14IFG9</description>
+                                <value>30</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_32</name>
+                                <description>Interrupt Source: ADC14MEM10 interrupt flag; Interrupt Flag: ADC14IFG10</description>
+                                <value>32</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_34</name>
+                                <description>Interrupt Source: ADC14MEM11 interrupt flag; Interrupt Flag: ADC14IFG11</description>
+                                <value>34</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_36</name>
+                                <description>Interrupt Source: ADC14MEM12 interrupt flag; Interrupt Flag: ADC14IFG12</description>
+                                <value>36</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_38</name>
+                                <description>Interrupt Source: ADC14MEM13 interrupt flag; Interrupt Flag: ADC14IFG13</description>
+                                <value>38</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_40</name>
+                                <description>Interrupt Source: ADC14MEM14 interrupt flag; Interrupt Flag: ADC14IFG14</description>
+                                <value>40</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_42</name>
+                                <description>Interrupt Source: ADC14MEM15 interrupt flag; Interrupt Flag: ADC14IFG15</description>
+                                <value>42</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_44</name>
+                                <description>Interrupt Source: ADC14MEM16 interrupt flag; Interrupt Flag: ADC14IFG16</description>
+                                <value>44</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_46</name>
+                                <description>Interrupt Source: ADC14MEM17 interrupt flag; Interrupt Flag: ADC14IFG17</description>
+                                <value>46</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_48</name>
+                                <description>Interrupt Source: ADC14MEM18 interrupt flag; Interrupt Flag: ADC14IFG18</description>
+                                <value>48</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_50</name>
+                                <description>Interrupt Source: ADC14MEM19 interrupt flag; Interrupt Flag: ADC14IFG19</description>
+                                <value>50</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_52</name>
+                                <description>Interrupt Source: ADC14MEM20 interrupt flag; Interrupt Flag: ADC14IFG20</description>
+                                <value>52</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_54</name>
+                                <description>Interrupt Source: ADC14MEM22 interrupt flag; Interrupt Flag: ADC14IFG22</description>
+                                <value>54</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_56</name>
+                                <description>Interrupt Source: ADC14MEM22 interrupt flag; Interrupt Flag: ADC14IFG22</description>
+                                <value>56</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_58</name>
+                                <description>Interrupt Source: ADC14MEM23 interrupt flag; Interrupt Flag: ADC14IFG23</description>
+                                <value>58</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_60</name>
+                                <description>Interrupt Source: ADC14MEM24 interrupt flag; Interrupt Flag: ADC14IFG24</description>
+                                <value>60</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_62</name>
+                                <description>Interrupt Source: ADC14MEM25 interrupt flag; Interrupt Flag: ADC14IFG25</description>
+                                <value>62</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_64</name>
+                                <description>Interrupt Source: ADC14MEM26 interrupt flag; Interrupt Flag: ADC14IFG26</description>
+                                <value>64</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_66</name>
+                                <description>Interrupt Source: ADC14MEM27 interrupt flag; Interrupt Flag: ADC14IFG27</description>
+                                <value>66</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_68</name>
+                                <description>Interrupt Source: ADC14MEM28 interrupt flag; Interrupt Flag: ADC14IFG28</description>
+                                <value>68</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_70</name>
+                                <description>Interrupt Source: ADC14MEM29 interrupt flag; Interrupt Flag: ADC14IFG29</description>
+                                <value>70</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_72</name>
+                                <description>Interrupt Source: ADC14MEM30 interrupt flag; Interrupt Flag: ADC14IFG30</description>
+                                <value>72</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_74</name>
+                                <description>Interrupt Source: ADC14MEM31 interrupt flag; Interrupt Flag: ADC14IFG31</description>
+                                <value>74</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC14IV_76</name>
+                                <description>Interrupt Source: ADC14RDYIFG interrupt flag; Interrupt Flag: ADC14RDYIFG; Interrupt Priority: Lowest</description>
+                                <value>76</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>ITM</name>
+        <version>356.0</version>
+        <description>ITM</description>
+        <baseAddress>0xE0000000</baseAddress>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x1000</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>ITM_STIM0</name>
+                  <displayName>STIM0</displayName>
+                  <description>ITM Stimulus Port 0</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_STIM1</name>
+                  <displayName>STIM1</displayName>
+                  <description>ITM Stimulus Port 1</description>
+                  <addressOffset>0x4</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_STIM2</name>
+                  <displayName>STIM2</displayName>
+                  <description>ITM Stimulus Port 2</description>
+                  <addressOffset>0x8</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_STIM3</name>
+                  <displayName>STIM3</displayName>
+                  <description>ITM Stimulus Port 3</description>
+                  <addressOffset>0xC</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_STIM4</name>
+                  <displayName>STIM4</displayName>
+                  <description>ITM Stimulus Port 4</description>
+                  <addressOffset>0x10</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_STIM5</name>
+                  <displayName>STIM5</displayName>
+                  <description>ITM Stimulus Port 5</description>
+                  <addressOffset>0x14</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_STIM6</name>
+                  <displayName>STIM6</displayName>
+                  <description>ITM Stimulus Port 6</description>
+                  <addressOffset>0x18</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_STIM7</name>
+                  <displayName>STIM7</displayName>
+                  <description>ITM Stimulus Port 7</description>
+                  <addressOffset>0x1C</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_STIM8</name>
+                  <displayName>STIM8</displayName>
+                  <description>ITM Stimulus Port 8</description>
+                  <addressOffset>0x20</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_STIM9</name>
+                  <displayName>STIM9</displayName>
+                  <description>ITM Stimulus Port 9</description>
+                  <addressOffset>0x24</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_STIM10</name>
+                  <displayName>STIM10</displayName>
+                  <description>ITM Stimulus Port 10</description>
+                  <addressOffset>0x28</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_STIM11</name>
+                  <displayName>STIM11</displayName>
+                  <description>ITM Stimulus Port 11</description>
+                  <addressOffset>0x2C</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_STIM12</name>
+                  <displayName>STIM12</displayName>
+                  <description>ITM Stimulus Port 12</description>
+                  <addressOffset>0x30</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_STIM13</name>
+                  <displayName>STIM13</displayName>
+                  <description>ITM Stimulus Port 13</description>
+                  <addressOffset>0x34</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_STIM14</name>
+                  <displayName>STIM14</displayName>
+                  <description>ITM Stimulus Port 14</description>
+                  <addressOffset>0x38</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_STIM15</name>
+                  <displayName>STIM15</displayName>
+                  <description>ITM Stimulus Port 15</description>
+                  <addressOffset>0x3C</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_STIM16</name>
+                  <displayName>STIM16</displayName>
+                  <description>ITM Stimulus Port 16</description>
+                  <addressOffset>0x40</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_STIM17</name>
+                  <displayName>STIM17</displayName>
+                  <description>ITM Stimulus Port 17</description>
+                  <addressOffset>0x44</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_STIM18</name>
+                  <displayName>STIM18</displayName>
+                  <description>ITM Stimulus Port 18</description>
+                  <addressOffset>0x48</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_STIM19</name>
+                  <displayName>STIM19</displayName>
+                  <description>ITM Stimulus Port 19</description>
+                  <addressOffset>0x4C</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_STIM20</name>
+                  <displayName>STIM20</displayName>
+                  <description>ITM Stimulus Port 20</description>
+                  <addressOffset>0x50</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_STIM21</name>
+                  <displayName>STIM21</displayName>
+                  <description>ITM Stimulus Port 21</description>
+                  <addressOffset>0x54</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_STIM22</name>
+                  <displayName>STIM22</displayName>
+                  <description>ITM Stimulus Port 22</description>
+                  <addressOffset>0x58</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_STIM23</name>
+                  <displayName>STIM23</displayName>
+                  <description>ITM Stimulus Port 23</description>
+                  <addressOffset>0x5C</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_STIM24</name>
+                  <displayName>STIM24</displayName>
+                  <description>ITM Stimulus Port 24</description>
+                  <addressOffset>0x60</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_STIM25</name>
+                  <displayName>STIM25</displayName>
+                  <description>ITM Stimulus Port 25</description>
+                  <addressOffset>0x64</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_STIM26</name>
+                  <displayName>STIM26</displayName>
+                  <description>ITM Stimulus Port 26</description>
+                  <addressOffset>0x68</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_STIM27</name>
+                  <displayName>STIM27</displayName>
+                  <description>ITM Stimulus Port 27</description>
+                  <addressOffset>0x6C</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_STIM28</name>
+                  <displayName>STIM28</displayName>
+                  <description>ITM Stimulus Port 28</description>
+                  <addressOffset>0x70</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_STIM29</name>
+                  <displayName>STIM29</displayName>
+                  <description>ITM Stimulus Port 29</description>
+                  <addressOffset>0x74</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_STIM30</name>
+                  <displayName>STIM30</displayName>
+                  <description>ITM Stimulus Port 30</description>
+                  <addressOffset>0x78</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_STIM31</name>
+                  <displayName>STIM31</displayName>
+                  <description>ITM Stimulus Port 31</description>
+                  <addressOffset>0x7C</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>ITM_TER</name>
+                  <displayName>TER</displayName>
+                  <description>ITM Trace Enable Register</description>
+                  <addressOffset>0xE00</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>STIMENA</name>
+                        <description>Bit mask to enable tracing on ITM stimulus ports. One bit per stimulus port.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>ITM_TPR</name>
+                  <displayName>TPR</displayName>
+                  <description>ITM Trace Privilege Register</description>
+                  <addressOffset>0xE40</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>PRIVMASK</name>
+                        <description>Bit mask to enable tracing on ITM stimulus ports: bit [0] = stimulus ports [7:0], bit [1] = stimulus ports [15:8], bit [2] = stimulus ports [23:16], bit [3] = stimulus ports [31:24].</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>ITM_TCR</name>
+                  <displayName>TCR</displayName>
+                  <description>ITM Trace Control Register</description>
+                  <addressOffset>0xE80</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>ITMENA</name>
+                        <description>Enable ITM. This is the master enable, and must be set before ITM Stimulus and Trace Enable registers can be written.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TSENA</name>
+                        <description>Enables differential timestamps. Differential timestamps are emitted when a packet is written to the FIFO with a non-zero timestamp counter, and when the timestamp counter overflows. Timestamps are emitted during idle times after a fixed number of two million cycles. This provides a time reference for packets and inter-packet gaps. If SWOENA (bit [4]) is set, timestamps are triggered by activity on the internal trace bus only. In this case there is no regular timestamp output when the ITM is idle.</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SYNCENA</name>
+                        <description>Enables sync packets for TPIU.</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DWTENA</name>
+                        <description>Enables the DWT stimulus.</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SWOENA</name>
+                        <description>Enables asynchronous clocking of the timestamp counter.</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TSPRESCALE</name>
+                        <description>TSPrescale Timestamp prescaler.</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b00</name>
+                                <description>no prescaling</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b01</name>
+                                <description>divide by 4</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b10</name>
+                                <description>divide by 16</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b11</name>
+                                <description>divide by 64</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ATBID</name>
+                        <description>ATB ID for CoreSight system.</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x7</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>Set when ITM events present and being drained.</description>
+                        <bitOffset>0x17</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>ITM_IWR</name>
+                  <displayName>IWR</displayName>
+                  <description>ITM Integration Write Register</description>
+                  <addressOffset>0xEF8</addressOffset>
+                  <size>32</size>
+                  <access>write-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>ATVALIDM</name>
+                        <description>When the integration mode is set: 0 = ATVALIDM clear. 1 = ATVALIDM set.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>ATVALIDM clear</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>ATVALIDM set</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>ITM_IMCR</name>
+                  <displayName>IMCR</displayName>
+                  <description>ITM Integration Mode Control Register</description>
+                  <addressOffset>0xF00</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>INTEGRATION</name>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>ATVALIDM normal</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>ATVALIDM driven from Integration Write Register</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>ITM_LAR</name>
+                  <displayName>LAR</displayName>
+                  <description>ITM Lock Access Register</description>
+                  <addressOffset>0xFB0</addressOffset>
+                  <size>32</size>
+                  <access>write-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>LOCK_ACCESS</name>
+                        <description>A privileged write of 0xC5ACCE55 enables more write access to Control Register 0xE00::0xFFC. An invalid write removes write access.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>ITM_LSR</name>
+                  <displayName>LSR</displayName>
+                  <description>ITM Lock Status Register</description>
+                  <addressOffset>0xFB4</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000003</resetValue>
+                  <fields>
+                    <field>
+                        <name>PRESENT</name>
+                        <description>Indicates that a lock mechanism exists for this component.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ACCESS</name>
+                        <description>Write access to component is blocked. All writes are ignored, reads are permitted.</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BYTEACC</name>
+                        <description>You cannot implement 8-bit lock accesses.</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>DWT</name>
+        <version>356.0</version>
+        <description>DWT</description>
+        <baseAddress>0xE0001000</baseAddress>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x1000</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>DWT_CTRL</name>
+                  <displayName>CTRL</displayName>
+                  <description>DWT Control Register</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x40000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>CYCCNTENA</name>
+                        <description>Enable the CYCCNT counter. If not enabled, the counter does not count and no event is generated for PS sampling or CYCCNTENA. In normal use, the debugger must initialize the CYCCNT counter to 0.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>POSTPRESET</name>
+                        <description>Reload value for POSTCNT, bits [8:5], post-scalar counter. If this value is 0, events are triggered on each tap change (a power of 2). If this field has a non-0 value, this forms a count-down value, to be reloaded into POSTCNT each time it reaches 0. For example, a value 1 in this register means an event is formed every other tap change.</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>POSTCNT</name>
+                        <description>Post-scalar counter for CYCTAP. When the selected tapped bit changes from 0 to 1 or 1 to 0, the post scalar counter is down-counted when not 0. If 0, it triggers an event for PCSAMPLENA or CYCEVTENA use. It also reloads with the value from POSTPRESET (bits [4:1]).</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CYCTAP</name>
+                        <description>Selects a tap on the DWT_CYCCNT register. These are spaced at bits [6] and [10]. When the selected bit in the CYCCNT register changes from 0 to 1 or 1 to 0, it emits into the POSTCNT, bits [8:5], post-scalar counter. That counter then counts down. On a bit change when post-scalar is 0, it triggers an event for PC sampling or CYCEVTCNT.</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>selects bit [6] to tap</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>selects bit [10] to tap.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SYNCTAP</name>
+                        <description>Feeds a synchronization pulse to the ITM SYNCENA control. The value selected here picks the rate (approximately 1/second or less) by selecting a tap on the DWT_CYCCNT register. To use synchronization (heartbeat and hot-connect synchronization), CYCCNTENA must be set to 1, SYNCTAP must be set to one of its values, and SYNCENA must be set to 1.</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b00</name>
+                                <description>Disabled. No synch counting.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b01</name>
+                                <description>Tap at CYCCNT bit 24.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b10</name>
+                                <description>Tap at CYCCNT bit 26.</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b11</name>
+                                <description>Tap at CYCCNT bit 28.</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PCSAMPLEENA</name>
+                        <description>Enables PC Sampling event. A PC sample event is emitted when the POSTCNT counter triggers it. See CYCTAP, bit [9], and POSTPRESET, bits [4:1], for details. Enabling this bit overrides CYCEVTENA (bit [20]). Reset clears the PCSAMPLENA bit.</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>PC Sampling event disabled.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>Sampling event enabled.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>EXCTRCENA</name>
+                        <description>Enables Interrupt event tracing. Reset clears the EXCEVTENA bit.</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>interrupt event trace disabled.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>interrupt event trace enabled.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CPIEVTENA</name>
+                        <description>Enables CPI count event. Emits an event when DWT_CPICNT overflows (every 256 cycles of multi-cycle instructions). Reset clears the CPIEVTENA bit.</description>
+                        <bitOffset>0x11</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>CPI counter events disabled.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>CPI counter events enabled.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>EXCEVTENA</name>
+                        <description>Enables Interrupt overhead event. Emits an event when DWT_EXCCNT overflows (every 256 cycles of interrupt overhead). Reset clears the EXCEVTENA bit.</description>
+                        <bitOffset>0x12</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>Interrupt overhead event disabled.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>Interrupt overhead event enabled.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SLEEPEVTENA</name>
+                        <description>Enables Sleep count event. Emits an event when DWT_SLEEPCNT overflows (every 256 cycles that the processor is sleeping). Reset clears the SLEEPEVTENA bit.</description>
+                        <bitOffset>0x13</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>Sleep count events disabled.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>Sleep count events enabled.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LSUEVTENA</name>
+                        <description>Enables LSU count event. Emits an event when DWT_LSUCNT overflows (every 256 cycles of LSU operation). LSU counts include all LSU costs after the initial cycle for the instruction. Reset clears the LSUEVTENA bit.</description>
+                        <bitOffset>0x14</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>LSU count events disabled.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>LSU count events enabled.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FOLDEVTENA</name>
+                        <description>Enables Folded instruction count event. Emits an event when DWT_FOLDCNT overflows (every 256 cycles of folded instructions). A folded instruction is one that does not incur even one cycle to execute. For example, an IT instruction is folded away and so does not use up one cycle. Reset clears the FOLDEVTENA bit.</description>
+                        <bitOffset>0x15</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>Folded instruction count events disabled.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>Folded instruction count events enabled.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CYCEVTENA</name>
+                        <description>Enables Cycle count event. Emits an event when the POSTCNT counter triggers it. See CYCTAP (bit [9]) and POSTPRESET, bits [4:1], for details. This event is only emitted if PCSAMPLENA, bit [12], is disabled. PCSAMPLENA overrides the setting of this bit. Reset clears the CYCEVTENA bit.</description>
+                        <bitOffset>0x16</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>Cycle count events disabled.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>Cycle count events enabled.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>NOPRFCNT</name>
+                        <description>When set, DWT_FOLDCNT, DWT_LSUCNT, DWT_SLEEPCNT, DWT_EXCCNT, and DWT_CPICNT are not supported.</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NOCYCCNT</name>
+                        <description>When set, DWT_CYCCNT is not supported.</description>
+                        <bitOffset>0x19</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DWT_CYCCNT</name>
+                  <displayName>CYCCNT</displayName>
+                  <description>DWT Current PC Sampler Cycle Count Register</description>
+                  <addressOffset>0x4</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>CYCCNT</name>
+                        <description>Current PC Sampler Cycle Counter count value. When enabled, this counter counts the number of core cycles, except when the core is halted. CYCCNT is a free running counter, counting upwards. It wraps around to 0 on overflow. The debugger must initialize this to 0 when first enabling.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DWT_CPICNT</name>
+                  <displayName>CPICNT</displayName>
+                  <description>DWT CPI Count Register</description>
+                  <addressOffset>0x8</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>CPICNT</name>
+                        <description>Current CPI counter value. Increments on the additional cycles (the first cycle is not counted) required to execute all instructions except those recorded by DWT_LSUCNT. This counter also increments on all instruction fetch stalls. If CPIEVTENA is set, an event is emitted when the counter overflows. Clears to 0 on enabling.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DWT_EXCCNT</name>
+                  <displayName>EXCCNT</displayName>
+                  <description>DWT Exception Overhead Count Register</description>
+                  <addressOffset>0xC</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>EXCCNT</name>
+                        <description>Current interrupt overhead counter value. Counts the total cycles spent in interrupt processing (for example entry stacking, return unstacking, pre-emption). An event is emitted on counter overflow (every 256 cycles). This counter initializes to 0 when enabled. Clears to 0 on enabling.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DWT_SLEEPCNT</name>
+                  <displayName>SLEEPCNT</displayName>
+                  <description>DWT Sleep Count Register</description>
+                  <addressOffset>0x10</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>SLEEPCNT</name>
+                        <description>Sleep counter. Counts the number of cycles during which the processor is sleeping. An event is emitted on counter overflow (every 256 cycles). This counter initializes to 0 when enabled. Note that SLEEPCNT is clocked using FCLK. It is possible that the frequency of FCLK might be reduced while the processor is sleeping to minimize power consumption. This means that sleep duration must be calculated with the frequency of FCLK during sleep.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DWT_LSUCNT</name>
+                  <displayName>LSUCNT</displayName>
+                  <description>DWT LSU Count Register</description>
+                  <addressOffset>0x14</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>LSUCNT</name>
+                        <description>LSU counter. This counts the total number of cycles that the processor is processing an LSU operation. The initial execution cost of the instruction is not counted. For example, an LDR that takes two cycles to complete increments this counter one cycle. Equivalently, an LDR that stalls for two cycles (and so takes four cycles), increments this counter three times. An event is emitted on counter overflow (every 256 cycles). Clears to 0 on enabling.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DWT_FOLDCNT</name>
+                  <displayName>FOLDCNT</displayName>
+                  <description>DWT Fold Count Register</description>
+                  <addressOffset>0x18</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>FOLDCNT</name>
+                        <description>This counts the total number folded instructions. This counter initializes to 0 when enabled.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DWT_PCSR</name>
+                  <displayName>PCSR</displayName>
+                  <description>DWT Program Counter Sample Register</description>
+                  <addressOffset>0x1C</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <fields>
+                    <field>
+                        <name>EIASAMPLE</name>
+                        <description>Execution instruction address sample, or 0xFFFFFFFF if the core is halted.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DWT_COMP0</name>
+                  <displayName>COMP0</displayName>
+                  <description>DWT Comparator Register 0</description>
+                  <addressOffset>0x20</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>COMP</name>
+                        <description>Data value to compare against PC and the data address as given by DWT_FUNCTION0. DWT_COMP0 can also compare against the value of the PC Sampler Counter (DWT_CYCCNT).</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DWT_MASK0</name>
+                  <displayName>MASK0</displayName>
+                  <description>DWT Mask Register 0</description>
+                  <addressOffset>0x24</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>MASK</name>
+                        <description>Mask on data address when matching against COMP. This is the size of the ignore mask. hat is, DWT matching is performed as:(ADDR ANDed with (~0 left bit-shifted by MASK)) == COMP. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP is 3, this matches a word access of 0, because 3 would be within the word.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DWT_FUNCTION0</name>
+                  <displayName>FUNCTION0</displayName>
+                  <description>DWT Function Register 0</description>
+                  <addressOffset>0x28</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>FUNCTION</name>
+                        <description>Function settings. Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>Disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0010</name>
+                                <description>EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write.</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0011</name>
+                                <description>EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write.</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0100</name>
+                                <description>Watchpoint on PC match.</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0101</name>
+                                <description>Watchpoint on read.</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0110</name>
+                                <description>Watchpoint on write.</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0111</name>
+                                <description>Watchpoint on read or write.</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1000</name>
+                                <description>ETM trigger on PC match</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1001</name>
+                                <description>ETM trigger on read</description>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1010</name>
+                                <description>ETM trigger on write</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1011</name>
+                                <description>ETM trigger on read or write</description>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1100</name>
+                                <description>EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1101</name>
+                                <description>EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers</description>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1110</name>
+                                <description>EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1111</name>
+                                <description>EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers</description>
+                                <value>15</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>EMITRANGE</name>
+                        <description>Emit range field. Reserved to permit emitting offset when range match occurs. Reset clears the EMITRANGE bit. PC sampling is not supported when EMITRANGE is enabled. EMITRANGE only applies for: FUNCTION = b0001, b0010, b0011, b1100, b1101, b1110, and b1111.</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATAVMATCH</name>
+                        <description>This bit is only available in comparator 1. When DATAVMATCH is set, this comparator performs data value compares. The comparators given by DATAVADDR0 and DATAVADDR1provide the address for the data comparison. If DATAVMATCH is set in DWT_FUNCTION1, the FUNCTION setting for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and those comparators only provide the address match for the data comparison.</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LNK1ENA</name>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>DATAVADDR1 not supported</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>DATAVADDR1 supported (enabled).</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DATAVSIZE</name>
+                        <description>Defines the size of the data in the COMP register that is to be matched:</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b00</name>
+                                <description>byte</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b01</name>
+                                <description>halfword</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b10</name>
+                                <description>word</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b11</name>
+                                <description>Unpredictable.</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DATAVADDR0</name>
+                        <description>Identity of a linked address comparator for data value matching when DATAVMATCH == 1.</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATAVADDR1</name>
+                        <description>Identity of a second linked address comparator for data value matching when DATAVMATCH == 1 and LNK1ENA == 1.</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MATCHED</name>
+                        <description>This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read.</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DWT_COMP1</name>
+                  <displayName>COMP1</displayName>
+                  <description>DWT Comparator Register 1</description>
+                  <addressOffset>0x30</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>COMP</name>
+                        <description>Data value to compare against PC and the data address as given by DWT_FUNCTION1.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DWT_MASK1</name>
+                  <displayName>MASK1</displayName>
+                  <description>DWT Mask Register 1</description>
+                  <addressOffset>0x34</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>MASK</name>
+                        <description>Mask on data address when matching against COMP. This is the size of the ignore mask. hat is, DWT matching is performed as:(ADDR ANDed with (~0 left bit-shifted by MASK)) == COMP. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP is 3, this matches a word access of 0, because 3 would be within the word.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DWT_FUNCTION1</name>
+                  <displayName>FUNCTION1</displayName>
+                  <description>DWT Function Register 1</description>
+                  <addressOffset>0x38</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>FUNCTION</name>
+                        <description>Function settings. Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: FUNCTION is overridden for comparators given by DATAVADDR0 and DATAVADDR1 in DWT_FUNCTION1if DATAVMATCH is also set in DWT_FUNCTION1. The comparators given by DATAVADDR0 and DATAVADDR1 can then only perform address comparator matches for comparator 1 data matches. Note 4: If the data matching functionality is not included during implementation it is not possible to set DATAVADDR0, DATAVADDR1, or DATAVMATCH in DWT_FUNCTION1. This means that the data matching functionality is not available in the implementation. Test the availability of data matching by writing and reading the DATAVMATCH bit in DWT_FUNCTION1. If it is not settable then data matching is unavailable. Note 5: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>Disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0010</name>
+                                <description>EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write.</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0011</name>
+                                <description>EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write.</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0100</name>
+                                <description>Watchpoint on PC match.</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0101</name>
+                                <description>Watchpoint on read.</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0110</name>
+                                <description>Watchpoint on write.</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0111</name>
+                                <description>Watchpoint on read or write.</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1000</name>
+                                <description>ETM trigger on PC match</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1001</name>
+                                <description>ETM trigger on read</description>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1010</name>
+                                <description>ETM trigger on write</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1011</name>
+                                <description>ETM trigger on read or write</description>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1100</name>
+                                <description>EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1101</name>
+                                <description>EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers</description>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1110</name>
+                                <description>EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1111</name>
+                                <description>EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers</description>
+                                <value>15</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>EMITRANGE</name>
+                        <description>Emit range field. Reserved to permit emitting offset when range match occurs. Reset clears the EMITRANGE bit. PC sampling is not supported when EMITRANGE is enabled. EMITRANGE only applies for: FUNCTION = b0001, b0010, b0011, b1100, b1101, b1110, and b1111.</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CYCMATCH</name>
+                        <description>Only available in comparator 0. When set, this comparator compares against the clock cycle counter.</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATAVMATCH</name>
+                        <description>This bit is only available in comparator 1. When DATAVMATCH is set, this comparator performs data value compares. The comparators given by DATAVADDR0 and DATAVADDR1provide the address for the data comparison. If DATAVMATCH is set in DWT_FUNCTION1, the FUNCTION setting for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and those comparators only provide the address match for the data comparison.</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LNK1ENA</name>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>DATAVADDR1 not supported</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>DATAVADDR1 supported (enabled).</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DATAVSIZE</name>
+                        <description>Defines the size of the data in the COMP register that is to be matched:</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b00</name>
+                                <description>byte</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b01</name>
+                                <description>halfword</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b10</name>
+                                <description>word</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b11</name>
+                                <description>Unpredictable.</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DATAVADDR0</name>
+                        <description>Identity of a linked address comparator for data value matching when DATAVMATCH == 1.</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATAVADDR1</name>
+                        <description>Identity of a second linked address comparator for data value matching when DATAVMATCH == 1 and LNK1ENA == 1.</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MATCHED</name>
+                        <description>This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read.</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DWT_COMP2</name>
+                  <displayName>COMP2</displayName>
+                  <description>DWT Comparator Register 2</description>
+                  <addressOffset>0x40</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>COMP</name>
+                        <description>Data value to compare against PC and the data address as given by DWT_FUNCTION2.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DWT_MASK2</name>
+                  <displayName>MASK2</displayName>
+                  <description>DWT Mask Register 2</description>
+                  <addressOffset>0x44</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>MASK</name>
+                        <description>Mask on data address when matching against COMP. This is the size of the ignore mask. hat is, DWT matching is performed as:(ADDR ANDed with (~0 left bit-shifted by MASK)) == COMP. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP is 3, this matches a word access of 0, because 3 would be within the word.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DWT_FUNCTION2</name>
+                  <displayName>FUNCTION2</displayName>
+                  <description>DWT Function Register 2</description>
+                  <addressOffset>0x48</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>FUNCTION</name>
+                        <description>Function settings. Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>Disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0010</name>
+                                <description>EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write.</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0011</name>
+                                <description>EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write.</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0100</name>
+                                <description>Watchpoint on PC match.</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0101</name>
+                                <description>Watchpoint on read.</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0110</name>
+                                <description>Watchpoint on write.</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0111</name>
+                                <description>Watchpoint on read or write.</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1000</name>
+                                <description>ETM trigger on PC match</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1001</name>
+                                <description>ETM trigger on read</description>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1010</name>
+                                <description>ETM trigger on write</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1011</name>
+                                <description>ETM trigger on read or write</description>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1100</name>
+                                <description>EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1101</name>
+                                <description>EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers</description>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1110</name>
+                                <description>EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1111</name>
+                                <description>EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers</description>
+                                <value>15</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>EMITRANGE</name>
+                        <description>Emit range field. Reserved to permit emitting offset when range match occurs. Reset clears the EMITRANGE bit. PC sampling is not supported when EMITRANGE is enabled. EMITRANGE only applies for: FUNCTION = b0001, b0010, b0011, b1100, b1101, b1110, and b1111.</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATAVMATCH</name>
+                        <description>This bit is only available in comparator 1. When DATAVMATCH is set, this comparator performs data value compares. The comparators given by DATAVADDR0 and DATAVADDR1provide the address for the data comparison. If DATAVMATCH is set in DWT_FUNCTION1, the FUNCTION setting for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and those comparators only provide the address match for the data comparison.</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LNK1ENA</name>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>DATAVADDR1 not supported</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>DATAVADDR1 supported (enabled).</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DATAVSIZE</name>
+                        <description>Defines the size of the data in the COMP register that is to be matched:</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b00</name>
+                                <description>byte</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b01</name>
+                                <description>halfword</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b10</name>
+                                <description>word</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b11</name>
+                                <description>Unpredictable.</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DATAVADDR0</name>
+                        <description>Identity of a linked address comparator for data value matching when DATAVMATCH == 1.</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATAVADDR1</name>
+                        <description>Identity of a second linked address comparator for data value matching when DATAVMATCH == 1 and LNK1ENA == 1.</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MATCHED</name>
+                        <description>This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read.</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DWT_COMP3</name>
+                  <displayName>COMP3</displayName>
+                  <description>DWT Comparator Register 3</description>
+                  <addressOffset>0x50</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>COMP</name>
+                        <description>Data value to compare against PC and the data address as given by DWT_FUNCTION3.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DWT_MASK3</name>
+                  <displayName>MASK3</displayName>
+                  <description>DWT Mask Register 3</description>
+                  <addressOffset>0x54</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>MASK</name>
+                        <description>Mask on data address when matching against COMP. This is the size of the ignore mask. hat is, DWT matching is performed as:(ADDR ANDed with (~0 left bit-shifted by MASK)) == COMP. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP is 3, this matches a word access of 0, because 3 would be within the word.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DWT_FUNCTION3</name>
+                  <displayName>FUNCTION3</displayName>
+                  <description>DWT Function Register 3</description>
+                  <addressOffset>0x58</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>FUNCTION</name>
+                        <description>Function settings. Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>Disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0010</name>
+                                <description>EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write.</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0011</name>
+                                <description>EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write.</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0100</name>
+                                <description>Watchpoint on PC match.</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0101</name>
+                                <description>Watchpoint on read.</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0110</name>
+                                <description>Watchpoint on write.</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0111</name>
+                                <description>Watchpoint on read or write.</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1000</name>
+                                <description>ETM trigger on PC match</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1001</name>
+                                <description>ETM trigger on read</description>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1010</name>
+                                <description>ETM trigger on write</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1011</name>
+                                <description>ETM trigger on read or write</description>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1100</name>
+                                <description>EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1101</name>
+                                <description>EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers</description>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1110</name>
+                                <description>EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1111</name>
+                                <description>EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers</description>
+                                <value>15</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>EMITRANGE</name>
+                        <description>Emit range field. Reserved to permit emitting offset when range match occurs. Reset clears the EMITRANGE bit. PC sampling is not supported when EMITRANGE is enabled. EMITRANGE only applies for: FUNCTION = b0001, b0010, b0011, b1100, b1101, b1110, and b1111.</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATAVMATCH</name>
+                        <description>This bit is only available in comparator 1. When DATAVMATCH is set, this comparator performs data value compares. The comparators given by DATAVADDR0 and DATAVADDR1provide the address for the data comparison. If DATAVMATCH is set in DWT_FUNCTION1, the FUNCTION setting for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and those comparators only provide the address match for the data comparison.</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LNK1ENA</name>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>DATAVADDR1 not supported</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>DATAVADDR1 supported (enabled).</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DATAVSIZE</name>
+                        <description>Defines the size of the data in the COMP register that is to be matched:</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b00</name>
+                                <description>byte</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b01</name>
+                                <description>halfword</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b10</name>
+                                <description>word</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b11</name>
+                                <description>Unpredictable.</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DATAVADDR0</name>
+                        <description>Identity of a linked address comparator for data value matching when DATAVMATCH == 1.</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATAVADDR1</name>
+                        <description>Identity of a second linked address comparator for data value matching when DATAVMATCH == 1 and LNK1ENA == 1.</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MATCHED</name>
+                        <description>This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read.</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>FPB</name>
+        <version>356.0</version>
+        <description>FPB</description>
+        <baseAddress>0xE0002000</baseAddress>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x1000</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>FP_CTRL</name>
+                  <displayName>FP_CTRL</displayName>
+                  <description>Flash Patch Control Register</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000130</resetValue>
+                  <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Flash patch unit enable bit</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>flash patch unit disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>flash patch unit enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY</name>
+                        <description>Key field. To write to the Flash Patch Control Register, you must write a 1 to this write-only bit.</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>NUM_CODE1</name>
+                        <description>Number of code slots field.</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>no code slots</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0010</name>
+                                <description>two code slots</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0110</name>
+                                <description>six code slots</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>NUM_LIT</name>
+                        <description>Number of literal slots field.</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>no literal slots</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0010</name>
+                                <description>two literal slots</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>NUM_CODE2</name>
+                        <description>Number of full banks of code comparators, sixteen comparators per bank. Where less than sixteen code comparators are provided, the bank count is zero, and the number present indicated by NUM_CODE. This read only field contains 3'b000 to indicate 0 banks for Cortex-M4 processor.</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FP_REMAP</name>
+                  <displayName>FP_REMAP</displayName>
+                  <description>Flash Patch Remap Register</description>
+                  <addressOffset>0x4</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>REMAP</name>
+                        <description>Remap base address field.</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x18</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FP_COMP0</name>
+                  <displayName>FP_COMP0</displayName>
+                  <description>Flash Patch Comparator Registers</description>
+                  <addressOffset>0x8</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000001</resetMask>
+                  <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Compare and remap enable for Flash Patch Comparator Register 0. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>Flash Patch Comparator Register 0 compare and remap disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>Flash Patch Comparator Register 0 compare and remap enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>COMP</name>
+                        <description>Comparison address.</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1B</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>REPLACE</name>
+                        <description>This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting.</description>
+                        <bitOffset>0x1E</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b00</name>
+                                <description>remap to remap address. See FP_REMAP</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b01</name>
+                                <description>set BKPT on lower halfword, upper is unaffected</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b10</name>
+                                <description>set BKPT on upper halfword, lower is unaffected</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b11</name>
+                                <description>set BKPT on both lower and upper halfwords.</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FP_COMP1</name>
+                  <displayName>FP_COMP1</displayName>
+                  <description>Flash Patch Comparator Registers</description>
+                  <addressOffset>0xC</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000001</resetMask>
+                  <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Compare and remap enable for Flash Patch Comparator Register 1. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>Flash Patch Comparator Register 1 compare and remap disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>Flash Patch Comparator Register 1 compare and remap enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>COMP</name>
+                        <description>Comparison address.</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1B</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>REPLACE</name>
+                        <description>This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting.</description>
+                        <bitOffset>0x1E</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b00</name>
+                                <description>remap to remap address. See FP_REMAP</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b01</name>
+                                <description>set BKPT on lower halfword, upper is unaffected</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b10</name>
+                                <description>set BKPT on upper halfword, lower is unaffected</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b11</name>
+                                <description>set BKPT on both lower and upper halfwords.</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FP_COMP2</name>
+                  <displayName>FP_COMP2</displayName>
+                  <description>Flash Patch Comparator Registers</description>
+                  <addressOffset>0x10</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000001</resetMask>
+                  <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Compare and remap enable for Flash Patch Comparator Register 2. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>Flash Patch Comparator Register 2 compare and remap disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>Flash Patch Comparator Register 2 compare and remap enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>COMP</name>
+                        <description>Comparison address.</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1B</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>REPLACE</name>
+                        <description>This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting.</description>
+                        <bitOffset>0x1E</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b00</name>
+                                <description>remap to remap address. See FP_REMAP</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b01</name>
+                                <description>set BKPT on lower halfword, upper is unaffected</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b10</name>
+                                <description>set BKPT on upper halfword, lower is unaffected</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b11</name>
+                                <description>set BKPT on both lower and upper halfwords.</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FP_COMP3</name>
+                  <displayName>FP_COMP3</displayName>
+                  <description>Flash Patch Comparator Registers</description>
+                  <addressOffset>0x14</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000001</resetMask>
+                  <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Compare and remap enable for Flash Patch Comparator Register 3. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>Flash Patch Comparator Register 3 compare and remap disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>Flash Patch Comparator Register 3 compare and remap enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>COMP</name>
+                        <description>Comparison address.</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1B</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>REPLACE</name>
+                        <description>This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting.</description>
+                        <bitOffset>0x1E</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b00</name>
+                                <description>remap to remap address. See FP_REMAP</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b01</name>
+                                <description>set BKPT on lower halfword, upper is unaffected</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b10</name>
+                                <description>set BKPT on upper halfword, lower is unaffected</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b11</name>
+                                <description>set BKPT on both lower and upper halfwords.</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FP_COMP4</name>
+                  <displayName>FP_COMP4</displayName>
+                  <description>Flash Patch Comparator Registers</description>
+                  <addressOffset>0x18</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000001</resetMask>
+                  <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Compare and remap enable for Flash Patch Comparator Register 4. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>Flash Patch Comparator Register 4 compare and remap disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>Flash Patch Comparator Register 4 compare and remap enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>COMP</name>
+                        <description>Comparison address.</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1B</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>REPLACE</name>
+                        <description>This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting.</description>
+                        <bitOffset>0x1E</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b00</name>
+                                <description>remap to remap address. See FP_REMAP</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b01</name>
+                                <description>set BKPT on lower halfword, upper is unaffected</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b10</name>
+                                <description>set BKPT on upper halfword, lower is unaffected</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b11</name>
+                                <description>set BKPT on both lower and upper halfwords.</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FP_COMP5</name>
+                  <displayName>FP_COMP5</displayName>
+                  <description>Flash Patch Comparator Registers</description>
+                  <addressOffset>0x1C</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000001</resetMask>
+                  <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Compare and remap enable for Flash Patch Comparator Register 5. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>Flash Patch Comparator Register 5 compare and remap disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>Flash Patch Comparator Register 5 compare and remap enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>COMP</name>
+                        <description>Comparison address.</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1B</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>REPLACE</name>
+                        <description>This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting.</description>
+                        <bitOffset>0x1E</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b00</name>
+                                <description>remap to remap address. See FP_REMAP</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b01</name>
+                                <description>set BKPT on lower halfword, upper is unaffected</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b10</name>
+                                <description>set BKPT on upper halfword, lower is unaffected</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b11</name>
+                                <description>set BKPT on both lower and upper halfwords.</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FP_COMP6</name>
+                  <displayName>FP_COMP6</displayName>
+                  <description>Flash Patch Comparator Registers</description>
+                  <addressOffset>0x20</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000001</resetMask>
+                  <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Compare and remap enable for Flash Patch Comparator Register 6. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>Flash Patch Comparator Register 6 compare and remap disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>Flash Patch Comparator Register 6 compare and remap enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>COMP</name>
+                        <description>Comparison address.</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1B</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>REPLACE</name>
+                        <description>This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting.</description>
+                        <bitOffset>0x1E</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b00</name>
+                                <description>remap to remap address. See FP_REMAP</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b01</name>
+                                <description>set BKPT on lower halfword, upper is unaffected</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b10</name>
+                                <description>set BKPT on upper halfword, lower is unaffected</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b11</name>
+                                <description>set BKPT on both lower and upper halfwords.</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FP_COMP7</name>
+                  <displayName>FP_COMP7</displayName>
+                  <description>Flash Patch Comparator Registers</description>
+                  <addressOffset>0x24</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000001</resetMask>
+                  <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Compare and remap enable for Flash Patch Comparator Register 7. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>Flash Patch Comparator Register 7 compare and remap disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>Flash Patch Comparator Register 7 compare and remap enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>COMP</name>
+                        <description>Comparison address.</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1B</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>REPLACE</name>
+                        <description>This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting.</description>
+                        <bitOffset>0x1E</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b00</name>
+                                <description>remap to remap address. See FP_REMAP</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b01</name>
+                                <description>set BKPT on lower halfword, upper is unaffected</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b10</name>
+                                <description>set BKPT on upper halfword, lower is unaffected</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b11</name>
+                                <description>set BKPT on both lower and upper halfwords.</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>SystemControlSpace</name>
+        <version>356.0</version>
+        <description>System Control Space for ARM core: SCnSCB, SCB, SysTick, NVIC, CoreDebug, MPU, FPU</description>
+        <baseAddress>0xE000E000</baseAddress>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x1000</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>ICTR</name>
+                  <displayName>ICTR</displayName>
+                  <description>Interrupt Control Type Register</description>
+                  <addressOffset>0x4</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>INTLINESNUM</name>
+                        <description>Total number of interrupt lines in groups of 32.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x5</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>ACTLR</name>
+                  <displayName>ACTLR</displayName>
+                  <description>Auxiliary Control Register</description>
+                  <addressOffset>0x8</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>DISMCYCINT</name>
+                        <description>Disables interruption of multi-cycle instructions. This increases the interrupt latency of the processor becuase LDM/STM completes before interrupt stacking occurs.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DISDEFWBUF</name>
+                        <description>Disables write buffer us during default memorty map accesses. This causes all bus faults to be precise bus faults but decreases the performance of the processor because the stores to memory have to complete before the next instruction can be executed.</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DISFOLD</name>
+                        <description>Disables IT folding.</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DISFPCA</name>
+                        <description>Disable automatic update of CONTROL.FPCA</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DISOOFP</name>
+                        <description>Disables floating point instructions completing out of order with respect to integer

+instructions.</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x1000</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>ISER0</name>
+                  <displayName>ISER0</displayName>
+                  <description>Irq 0 to 31 Set Enable Register</description>
+                  <addressOffset>0x100</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>SETENA</name>
+                        <description>Writing 0 to a SETENA bit has no effect, writing 1 to a bit enables the corresponding interrupt. Reading the bit returns its current enable state. Reset clears the SETENA fields.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>ISER1</name>
+                  <displayName>ISER1</displayName>
+                  <description>Irq 32 to 63 Set Enable Register</description>
+                  <addressOffset>0x104</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>SETENA</name>
+                        <description>Writing 0 to a SETENA bit has no effect, writing 1 to a bit enables the corresponding interrupt. Reading the bit returns its current enable state. Reset clears the SETENA fields.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>ICER0</name>
+                  <displayName>ICER0</displayName>
+                  <description>Irq 0 to 31 Clear Enable Register</description>
+                  <addressOffset>0x180</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>CLRENA</name>
+                        <description>Writing 0 to a CLRENA bit has no effect, writing 1 to a bit disables the corresponding interrupt. Reading the bit returns its current enable state. Reset clears the CLRENA field.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>ICER1</name>
+                  <displayName>ICER1</displayName>
+                  <description>Irq 32 to 63 Clear Enable Register</description>
+                  <addressOffset>0x184</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>CLRENA</name>
+                        <description>Writing 0 to a CLRENA bit has no effect, writing 1 to a bit disables the corresponding interrupt. Reading the bit returns its current enable state. Reset clears the CLRENA field.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>ISPR0</name>
+                  <displayName>ISPR0</displayName>
+                  <description>Irq 0 to 31 Set Pending Register</description>
+                  <addressOffset>0x200</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>SETPEND</name>
+                        <description>Writing 0 to a SETPEND bit has no effect, writing 1 to a bit pends the corresponding interrupt. Reading the bit returns its current state.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>ISPR1</name>
+                  <displayName>ISPR1</displayName>
+                  <description>Irq 32 to 63 Set Pending Register</description>
+                  <addressOffset>0x204</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>SETPEND</name>
+                        <description>Writing 0 to a SETPEND bit has no effect, writing 1 to a bit pends the corresponding interrupt. Reading the bit returns its current state.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>ICPR0</name>
+                  <displayName>ICPR0</displayName>
+                  <description>Irq 0 to 31 Clear Pending Register</description>
+                  <addressOffset>0x280</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>CLRPEND</name>
+                        <description>Writing 0 to a CLRPEND bit has no effect, writing 1 to a bit clears the corresponding pending interrupt. Reading the bit returns its current state.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>ICPR1</name>
+                  <displayName>ICPR1</displayName>
+                  <description>Irq 32 to 63 Clear Pending Register</description>
+                  <addressOffset>0x284</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>CLRPEND</name>
+                        <description>Writing 0 to a CLRPEND bit has no effect, writing 1 to a bit clears the corresponding pending interrupt. Reading the bit returns its current state.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>IABR0</name>
+                  <displayName>IABR0</displayName>
+                  <description>Irq 0 to 31 Active Bit Register</description>
+                  <addressOffset>0x300</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>ACTIVE</name>
+                        <description>Interrupt active flags. Reading 0 implies the interrupt is not active or stacked.  Reading 1 implies the interrupt is active or pre-empted and stacked.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>IABR1</name>
+                  <displayName>IABR1</displayName>
+                  <description>Irq 32 to 63 Active Bit Register</description>
+                  <addressOffset>0x304</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>ACTIVE</name>
+                        <description>Interrupt active flags. Reading 0 implies the interrupt is not active or stacked.  Reading 1 implies the interrupt is active or pre-empted and stacked.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>IPR0</name>
+                  <displayName>IPR0</displayName>
+                  <description>Irq 0 to 3 Priority Register</description>
+                  <addressOffset>0x400</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>PRI_0</name>
+                        <description>Priority of interrupt 0</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_1</name>
+                        <description>Priority of interrupt 1</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_2</name>
+                        <description>Priority of interrupt 2</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_3</name>
+                        <description>Priority of interrupt 3</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>IPR1</name>
+                  <displayName>IPR1</displayName>
+                  <description>Irq 4 to 7 Priority Register</description>
+                  <addressOffset>0x404</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>PRI_4</name>
+                        <description>Priority of interrupt 4</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_5</name>
+                        <description>Priority of interrupt 5</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_6</name>
+                        <description>Priority of interrupt 6</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_7</name>
+                        <description>Priority of interrupt 7</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>IPR2</name>
+                  <displayName>IPR2</displayName>
+                  <description>Irq 8 to 11 Priority Register</description>
+                  <addressOffset>0x408</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>PRI_8</name>
+                        <description>Priority of interrupt 8</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_9</name>
+                        <description>Priority of interrupt 9</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_10</name>
+                        <description>Priority of interrupt 10</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_11</name>
+                        <description>Priority of interrupt 11</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>IPR3</name>
+                  <displayName>IPR3</displayName>
+                  <description>Irq 12 to 15 Priority Register</description>
+                  <addressOffset>0x40C</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>PRI_12</name>
+                        <description>Priority of interrupt 12</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_13</name>
+                        <description>Priority of interrupt 13</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_14</name>
+                        <description>Priority of interrupt 14</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_15</name>
+                        <description>Priority of interrupt 15</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>IPR4</name>
+                  <displayName>IPR4</displayName>
+                  <description>Irq 16 to 19 Priority Register</description>
+                  <addressOffset>0x410</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>PRI_16</name>
+                        <description>Priority of interrupt 16</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_17</name>
+                        <description>Priority of interrupt 17</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_18</name>
+                        <description>Priority of interrupt 18</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_19</name>
+                        <description>Priority of interrupt 19</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>IPR5</name>
+                  <displayName>IPR5</displayName>
+                  <description>Irq 20 to 23 Priority Register</description>
+                  <addressOffset>0x414</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>PRI_20</name>
+                        <description>Priority of interrupt 20</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_21</name>
+                        <description>Priority of interrupt 21</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_22</name>
+                        <description>Priority of interrupt 22</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_23</name>
+                        <description>Priority of interrupt 23</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>IPR6</name>
+                  <displayName>IPR6</displayName>
+                  <description>Irq 24 to 27 Priority Register</description>
+                  <addressOffset>0x418</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>PRI_24</name>
+                        <description>Priority of interrupt 24</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_25</name>
+                        <description>Priority of interrupt 25</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_26</name>
+                        <description>Priority of interrupt 26</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_27</name>
+                        <description>Priority of interrupt 27</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>IPR7</name>
+                  <displayName>IPR7</displayName>
+                  <description>Irq 28 to 31 Priority Register</description>
+                  <addressOffset>0x41C</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>PRI_28</name>
+                        <description>Priority of interrupt 28</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_29</name>
+                        <description>Priority of interrupt 29</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_30</name>
+                        <description>Priority of interrupt 30</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_31</name>
+                        <description>Priority of interrupt 31</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>IPR8</name>
+                  <displayName>IPR8</displayName>
+                  <description>Irq 32 to 35 Priority Register</description>
+                  <addressOffset>0x420</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>PRI_32</name>
+                        <description>Priority of interrupt 32</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_33</name>
+                        <description>Priority of interrupt 33</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_34</name>
+                        <description>Priority of interrupt 34</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_35</name>
+                        <description>Priority of interrupt 35</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>IPR9</name>
+                  <displayName>IPR9</displayName>
+                  <description>Irq 36 to 39 Priority Register</description>
+                  <addressOffset>0x424</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>PRI_36</name>
+                        <description>Priority of interrupt 36</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_37</name>
+                        <description>Priority of interrupt 37</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_38</name>
+                        <description>Priority of interrupt 38</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_39</name>
+                        <description>Priority of interrupt 39</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>IPR10</name>
+                  <displayName>IPR10</displayName>
+                  <description>Irq 40 to 43 Priority Register</description>
+                  <addressOffset>0x428</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>PRI_40</name>
+                        <description>Priority of interrupt 40</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_41</name>
+                        <description>Priority of interrupt 41</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_42</name>
+                        <description>Priority of interrupt 42</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_43</name>
+                        <description>Priority of interrupt 43</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>IPR11</name>
+                  <displayName>IPR11</displayName>
+                  <description>Irq 44 to 47 Priority Register</description>
+                  <addressOffset>0x42C</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>PRI_44</name>
+                        <description>Priority of interrupt 44</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_45</name>
+                        <description>Priority of interrupt 45</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_46</name>
+                        <description>Priority of interrupt 46</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_47</name>
+                        <description>Priority of interrupt 47</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>IPR12</name>
+                  <displayName>IPR12</displayName>
+                  <description>Irq 48 to 51 Priority Register</description>
+                  <addressOffset>0x430</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>PRI_48</name>
+                        <description>Priority of interrupt 48</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_49</name>
+                        <description>Priority of interrupt 49</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_50</name>
+                        <description>Priority of interrupt 50</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_51</name>
+                        <description>Priority of interrupt 51</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>IPR13</name>
+                  <displayName>IPR13</displayName>
+                  <description>Irq 52 to 55 Priority Register</description>
+                  <addressOffset>0x434</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>PRI_52</name>
+                        <description>Priority of interrupt 52</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_53</name>
+                        <description>Priority of interrupt 53</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_54</name>
+                        <description>Priority of interrupt 54</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_55</name>
+                        <description>Priority of interrupt 55</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>IPR14</name>
+                  <displayName>IPR14</displayName>
+                  <description>Irq 56 to 59 Priority Register</description>
+                  <addressOffset>0x438</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>PRI_56</name>
+                        <description>Priority of interrupt 56</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_57</name>
+                        <description>Priority of interrupt 57</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_58</name>
+                        <description>Priority of interrupt 58</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_59</name>
+                        <description>Priority of interrupt 59</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>IPR15</name>
+                  <displayName>IPR15</displayName>
+                  <description>Irq 60 to 63 Priority Register</description>
+                  <addressOffset>0x43C</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>PRI_60</name>
+                        <description>Priority of interrupt 60</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_61</name>
+                        <description>Priority of interrupt 61</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_62</name>
+                        <description>Priority of interrupt 62</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_63</name>
+                        <description>Priority of interrupt 63</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>STIR</name>
+                  <displayName>STIR</displayName>
+                  <description>Software Trigger Interrupt Register</description>
+                  <addressOffset>0xF00</addressOffset>
+                  <size>32</size>
+                  <access>write-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>INTID</name>
+                        <description>Interrupt ID field. Writing a value to the INTID field is the same as manually pending an interrupt by setting the corresponding interrupt bit in an Interrupt Set Pending Register.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x9</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x1000</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>STCSR</name>
+                  <displayName>STCSR</displayName>
+                  <description>SysTick Control and Status Register</description>
+                  <addressOffset>0x10</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000004</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable SysTick counter</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>First</name>
+                                <description>Counter disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TICKINT</name>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>VAL_0</name>
+                                <description>Counting down to zero does not pend the SysTick handler. Software can use COUNTFLAG to determine if the SysTick handler has ever counted to zero.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>VAL_1</name>
+                                <description>Counting down to zero pends the SysTick handler.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CLKSOURCE</name>
+                        <description>Clock source.</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>CLKSOURCE_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>VAL_0</name>
+                                <description>Not applicable</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>VAL_1</name>
+                                <description>Core clock</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>COUNTFLAG</name>
+                        <description>Returns 1 if timer counted to 0 since last time this was read. Clears on read by application of any part of the SysTick Control and Status Register. If read by the debugger using the DAP, this bit is cleared on read-only if the MasterType bit in the AHB-AP Control Register is set to 0. Otherwise, the COUNTFLAG bit is not changed by the debugger read.</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>STRVR</name>
+                  <displayName>STRVR</displayName>
+                  <description>SysTick Reload Value Register</description>
+                  <addressOffset>0x14</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>RELOAD</name>
+                        <description>Value to load into the SysTick Current Value Register when the counter reaches 0.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x18</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>STCVR</name>
+                  <displayName>STCVR</displayName>
+                  <description>SysTick Current Value Register</description>
+                  <addressOffset>0x18</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>CURRENT</name>
+                        <description>Current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x18</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>STCR</name>
+                  <displayName>STCR</displayName>
+                  <description>SysTick Calibration Value Register</description>
+                  <addressOffset>0x1C</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <fields>
+                    <field>
+                        <name>TENMS</name>
+                        <description>Reads as zero. Indicates calibration value is not known.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x18</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SKEW</name>
+                        <description>Reads as one. The calibration value is not exactly 10ms because of clock frequency. This could affect its suitability as a software real time clock.</description>
+                        <bitOffset>0x1E</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NOREF</name>
+                        <description>Reads as one. Indicates that no separate reference clock is provided.</description>
+                        <bitOffset>0x1F</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x1000</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>CPUID</name>
+                  <displayName>CPUID</displayName>
+                  <description>CPUID Base Register</description>
+                  <addressOffset>0xD00</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x410fc241</resetValue>
+                  <fields>
+                    <field>
+                        <name>REVISION</name>
+                        <description>Implementation defined revision number.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PARTNO</name>
+                        <description>Number of processor within family.</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0xC</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CONSTANT</name>
+                        <description>Reads as 0xC</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VARIANT</name>
+                        <description>Implementation defined variant number.</description>
+                        <bitOffset>0x14</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IMPLEMENTER</name>
+                        <description>Implementor code.</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>ICSR</name>
+                  <displayName>ICSR</displayName>
+                  <description>Interrupt Control State Register</description>
+                  <addressOffset>0xD04</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>VECTACTIVE</name>
+                        <description>Active ISR number field. Reset clears the VECTACTIVE field.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x9</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RETTOBASE</name>
+                        <description>This bit is 1 when the set of all active exceptions minus the IPSR_current_exception yields the empty set.</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VECTPENDING</name>
+                        <description>Pending ISR number field. VECTPENDING contains the interrupt number of the highest priority pending ISR.</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x6</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ISRPENDING</name>
+                        <description>Interrupt pending flag. Excludes NMI and faults.</description>
+                        <bitOffset>0x16</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>interrupt not pending</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>interrupt pending</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ISRPREEMPT</name>
+                        <description>You must only use this at debug time. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced.</description>
+                        <bitOffset>0x17</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>a pending exception is not serviced.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>a pending exception is serviced on exit from the debug halt state</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PENDSTCLR</name>
+                        <description>Clear pending SysTick bit</description>
+                        <bitOffset>0x19</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>do not clear pending SysTick</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>clear pending SysTick</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PENDSTSET</name>
+                        <description>Set a pending SysTick bit.</description>
+                        <bitOffset>0x1A</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>do not set pending SysTick</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>set pending SysTick</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PENDSVCLR</name>
+                        <description>Clear pending pendSV bit</description>
+                        <bitOffset>0x1B</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>do not clear pending pendSV</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>clear pending pendSV</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PENDSVSET</name>
+                        <description>Set pending pendSV bit.</description>
+                        <bitOffset>0x1C</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>do not set pending pendSV</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>set pending PendSV</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>NMIPENDSET</name>
+                        <description>Set pending NMI bit. NMIPENDSET pends and activates an NMI. Because NMI is the highest-priority interrupt, it takes effect as soon as it registers.</description>
+                        <bitOffset>0x1F</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>do not set pending NMI</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>set pending NMI</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>VTOR</name>
+                  <displayName>VTOR</displayName>
+                  <description>Vector Table Offset Register</description>
+                  <addressOffset>0xD08</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>TBLOFF</name>
+                        <description>Vector table base offset field. Contains the offset of the table base from the bottom of the SRAM or CODE space.</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x16</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TBLBASE</name>
+                        <description>Table base is in Code (0) or RAM (1).</description>
+                        <bitOffset>0x1D</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>AIRCR</name>
+                  <displayName>AIRCR</displayName>
+                  <description>Application Interrupt/Reset Control Register</description>
+                  <addressOffset>0xD0C</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0xfa050000</resetValue>
+                  <resetMask>0xffff7fff</resetMask>
+                  <fields>
+                    <field>
+                        <name>VECTRESET</name>
+                        <description>System Reset bit. Resets the system, with the exception of debug components. The VECTRESET bit self-clears. Reset clears the VECTRESET bit. For debugging, only write this bit when the core is halted.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>VECTCLRACTIVE</name>
+                        <description>Clears all active state information for active NMI, fault, and interrupts.  It is the responsibility of the application to reinitialize the stack. The VECTCLRACTIVE bit is for returning to a known state during debug. The VECTCLRACTIVE bit self-clears. IPSR is not cleared by this operation. So, if used by an application, it must only be used at the base level of activation, or within a system handler whose active bit can be set.</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SYSRESETREQ</name>
+                        <description>Causes a signal to be asserted to the outer system that indicates a reset is requested. Intended to force a large system reset of all major components except for debug. Setting this bit does not prevent Halting Debug from running.</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>PRIGROUP</name>
+                        <description>Interrupt priority grouping field. The PRIGROUP field is a binary point position indicator for creating subpriorities for exceptions that share the same pre-emption level. It divides the PRI_n field in the Interrupt Priority Register into a pre-emption level and a subpriority level. The binary point is a left-of value. This means that the PRIGROUP value represents a point starting at the left of the Least Significant Bit (LSB). This is bit [0] of 7:0. The lowest value might not be 0 depending on the number of bits allocated for priorities, and implementation choices</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDIANESS</name>
+                        <description>Data endianness bit. ENDIANNESS is sampled from the BIGEND input port during reset. You cannot change ENDIANNESS outside of reset.</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>little endian</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>big endian</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>VECTKEY</name>
+                        <description>Register key. Writing to this register requires 0x5FA in the VECTKEY field. Otherwise the write value is ignored.</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>SCR</name>
+                  <displayName>SCR</displayName>
+                  <description>System Control Register</description>
+                  <addressOffset>0xD10</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>SLEEPONEXIT</name>
+                        <description>Sleep on exit when returning from Handler mode to Thread mode. Enables interrupt driven applications to avoid returning to empty main application.</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>do not sleep when returning to thread mode</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>sleep on ISR exit</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SLEEPDEEP</name>
+                        <description>Sleep deep bit.</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>not OK to turn off system clock</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>indicates to the system that Cortex-M4 clock can be stopped. Setting this bit causes the SLEEPDEEP port to be asserted when the processor can be stopped.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEVONPEND</name>
+                        <description>When enabled, this causes WFE to wake up when an interrupt moves from inactive to pended. Otherwise, WFE only wakes up from an event signal, external and SEV instruction generated. The event input, RXEV, is registered even when not waiting for an event, and so effects the next WFE.</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CCR</name>
+                  <displayName>CCR</displayName>
+                  <description>Configuration Control Register</description>
+                  <addressOffset>0xD14</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000200</resetValue>
+                  <fields>
+                    <field>
+                        <name>NONBASETHREDENA</name>
+                        <description>When 0, default, It is only possible to enter Thread mode when returning from the last exception. When set to 1, Thread mode can be entered from any level in Handler mode by controlled return value.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USERSETMPEND</name>
+                        <description>If written as 1, enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception, which is one associated with the Main stack pointer.</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UNALIGN_TRP</name>
+                        <description>Trap for unaligned access. This enables faulting/halting on any unaligned half or full word access. Unaligned load-store multiples always fault. The relevant Usage Fault Status Register bit is UNALIGNED.</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DIV_0_TRP</name>
+                        <description>Trap on Divide by 0. This enables faulting/halting when an attempt is made to divide by 0. The relevant Usage Fault Status Register bit is DIVBYZERO.</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BFHFNMIGN</name>
+                        <description>When enabled, this causes handlers running at priority -1 and -2 (Hard Fault, NMI, and FAULTMASK escalated handlers) to ignore Data Bus faults caused by load and store instructions. When disabled, these bus faults cause a lock-up. You must only use this enable with extreme caution. All data bus faults are ignored therefore you must only use it when the handler and its data are in absolutely safe memory. Its normal use is to probe system devices and bridges to detect control path problems and fix them.</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STKALIGN</name>
+                        <description>Stack alignment bit.</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>Only 4-byte alignment is guaranteed for the SP used prior to the exception on exception entry.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned and the context to restore it is saved. The SP is restored on the associated exception return.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>SHPR1</name>
+                  <displayName>SHPR1</displayName>
+                  <description>System Handlers 4-7 Priority Register</description>
+                  <addressOffset>0xD18</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>PRI_4</name>
+                        <description>Priority of system handler 4.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_5</name>
+                        <description>Priority of system handler 5.</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_6</name>
+                        <description>Priority of system handler 6.</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_7</name>
+                        <description>Priority of system handler 7.</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>SHPR2</name>
+                  <displayName>SHPR2</displayName>
+                  <description>System Handlers 8-11 Priority Register</description>
+                  <addressOffset>0xD1C</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>PRI_8</name>
+                        <description>Priority of system handler 8.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_9</name>
+                        <description>Priority of system handler 9.</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_10</name>
+                        <description>Priority of system handler 10.</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_11</name>
+                        <description>Priority of system handler 11.</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>SHPR3</name>
+                  <displayName>SHPR3</displayName>
+                  <description>System Handlers 12-15 Priority Register</description>
+                  <addressOffset>0xD20</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>PRI_12</name>
+                        <description>Priority of system handler 12.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_13</name>
+                        <description>Priority of system handler 13.</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_14</name>
+                        <description>Priority of system handler 14.</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_15</name>
+                        <description>Priority of system handler 15.</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>SHCSR</name>
+                  <displayName>SHCSR</displayName>
+                  <description>System Handler Control and State Register</description>
+                  <addressOffset>0xD24</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>MEMFAULTACT</name>
+                        <description>MemManage active flag.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>not active</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>active</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>BUSFAULTACT</name>
+                        <description>BusFault active flag.</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>not active</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>active</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>USGFAULTACT</name>
+                        <description>UsageFault active flag.</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>not active</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>active</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SVCALLACT</name>
+                        <description>SVCall active flag.</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>not active</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>active</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>MONITORACT</name>
+                        <description>the Monitor active flag.</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>not active</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>active</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PENDSVACT</name>
+                        <description>PendSV active flag.</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>not active</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>active</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SYSTICKACT</name>
+                        <description>SysTick active flag.</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>not active</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>active</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>USGFAULTPENDED</name>
+                        <description>usage fault pended flag.</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>not pended</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>pended</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>MEMFAULTPENDED</name>
+                        <description>MemManage pended flag.</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>not pended</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>pended</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>BUSFAULTPENDED</name>
+                        <description>BusFault pended flag.</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>not pended</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>pended</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SVCALLPENDED</name>
+                        <description>SVCall pended flag.</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>not pended</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>pended</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>MEMFAULTENA</name>
+                        <description>MemManage fault system handler enable</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>BUSFAULTENA</name>
+                        <description>Bus fault system handler enable</description>
+                        <bitOffset>0x11</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>USGFAULTENA</name>
+                        <description>Usage fault system handler enable</description>
+                        <bitOffset>0x12</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>disabled</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>enabled</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CFSR</name>
+                  <displayName>CFSR</displayName>
+                  <description>Configurable Fault Status Registers</description>
+                  <addressOffset>0xD28</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>IACCVIOL</name>
+                        <description>Instruction access violation flag. Attempting to fetch an instruction from a location that does not permit execution sets the IACCVIOL flag. This occurs on any access to an XN region, even when the MPU is disabled or not present. The return PC points to the faulting instruction. The MMAR is not written.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DACCVIOL</name>
+                        <description>Data access violation flag. Attempting to load or store at a location that does not permit the operation sets the DACCVIOL flag. The return PC points to the faulting instruction. This error loads MMAR with the address of the attempted access.</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MUNSTKERR</name>
+                        <description>Unstack from exception return has caused one or more access violations. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. The MMAR is not written.</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MSTKERR</name>
+                        <description>Stacking from exception has caused one or more access violations. The SP is still adjusted and the values in the context area on the stack might be incorrect. The MMAR is not written.</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MMARVALID</name>
+                        <description>Memory Manage Address Register (MMAR) address valid flag. A later-arriving fault, such as a bus fault, can clear a memory manage fault.. If a MemManage fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems on return to a stacked active MemManage handler whose MMAR value has been overwritten.</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IBUSERR</name>
+                        <description>Instruction bus error flag. The IBUSERR flag is set by a prefetch error. The fault stops on the instruction, so if the error occurs under a branch shadow, no fault occurs. The BFAR is not written.</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRECISERR</name>
+                        <description>Precise data bus error return.</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IMPRECISERR</name>
+                        <description>Imprecise data bus error. It is a BusFault, but the Return PC is not related to the causing instruction. This is not a synchronous fault. So, if detected when the priority of the current activation is higher than the Bus Fault, it only pends. Bus fault activates when returning to a lower priority activation. If a precise fault occurs before returning to a lower priority exception, the handler detects both IMPRECISERR set and one of the precise fault status bits set at the same time. The BFAR is not written.</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UNSTKERR</name>
+                        <description>Unstack from exception return has caused one or more bus faults. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. The BFAR is not written.</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STKERR</name>
+                        <description>Stacking from exception has caused one or more bus faults. The SP is still adjusted and the values in the context area on the stack might be incorrect. The BFAR is not written.</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BFARVALID</name>
+                        <description>This bit is set if the Bus Fault Address Register (BFAR) contains a valid address. This is true after a bus fault where the address is known. Other faults can clear this bit, such as a Mem Manage fault occurring later. If a Bus fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems if returning to a stacked active Bus fault handler whose BFAR value has been overwritten.</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UNDEFINSTR</name>
+                        <description>The UNDEFINSTR flag is set when the processor attempts to execute an undefined instruction. This is an instruction that the processor cannot decode. The return PC points to the undefined instruction.</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INVSTATE</name>
+                        <description>Invalid combination of EPSR and instruction, for reasons other than UNDEFINED instruction. Return PC points to faulting instruction, with the invalid state.</description>
+                        <bitOffset>0x11</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INVPC</name>
+                        <description>Attempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid context, invalid value. The return PC points to the instruction that tried to set the PC.</description>
+                        <bitOffset>0x12</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NOCP</name>
+                        <description>Attempt to use a coprocessor instruction. The processor does not support coprocessor instructions.</description>
+                        <bitOffset>0x13</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UNALIGNED</name>
+                        <description>When UNALIGN_TRP is enabled (see Configuration Control Register on page 8-26), and there is an attempt to make an unaligned memory access, then this fault occurs. Unaligned LDM/STM/LDRD/STRD instructions always fault irrespective of the setting of UNALIGN_TRP.</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DIVBYZERO</name>
+                        <description>When DIV_0_TRP (see Configuration Control Register on page 8-26) is enabled and an SDIV or UDIV instruction is used with a divisor of 0, this fault occurs The instruction is executed and the return PC points to it. If DIV_0_TRP is not set, then the divide returns a quotient of 0.</description>
+                        <bitOffset>0x19</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MLSPERR</name>
+                        <description>Indicates if MemManage fault occurred during FP lazy state preservation.</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LSPERR</name>
+                        <description>Indicates if bus fault occurred during FP lazy state preservation.</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>HFSR</name>
+                  <displayName>HFSR</displayName>
+                  <description>Hard Fault Status Register</description>
+                  <addressOffset>0xD2C</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>VECTTBL</name>
+                        <description>This bit is set if there is a fault because of vector table read on exception processing (Bus Fault). This case is always a Hard Fault. The return PC points to the pre-empted instruction.</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FORCED</name>
+                        <description>Hard Fault activated because a Configurable Fault was received and cannot activate because of priority or because the Configurable Fault is disabled. The Hard Fault handler then has to read the other fault status registers to determine cause.</description>
+                        <bitOffset>0x1E</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DEBUGEVT</name>
+                        <description>This bit is set if there is a fault related to debug. This is only possible when halting debug is not enabled. For monitor enabled debug, it only happens for BKPT when the current priority is higher than the monitor. When both halting and monitor debug are disabled, it only happens for debug events that are not ignored (minimally, BKPT). The Debug Fault Status Register is updated.</description>
+                        <bitOffset>0x1F</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DFSR</name>
+                  <displayName>DFSR</displayName>
+                  <description>Debug Fault Status Register</description>
+                  <addressOffset>0xD30</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>HALTED</name>
+                        <description>Halt request flag. The processor is halted on the next instruction.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>no halt request</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>halt requested by NVIC, including step</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>BKPT</name>
+                        <description>BKPT flag. The BKPT flag is set by a BKPT instruction in flash patch code, and also by normal code. Return PC points to breakpoint containing instruction.</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>no BKPT instruction execution</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>BKPT instruction execution</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DWTTRAP</name>
+                        <description>Data Watchpoint and Trace (DWT) flag. The processor stops at the current instruction or at the next instruction.</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>no DWT match</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>DWT match</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>VCATCH</name>
+                        <description>Vector catch flag. When the VCATCH flag is set, a flag in one of the local fault status registers is also set to indicate the type of fault.</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>no vector catch occurred</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>vector catch occurred</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>EXTERNAL</name>
+                        <description>External debug request flag. The processor stops on next instruction boundary.</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>EDBGRQ signal not asserted</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>EDBGRQ signal asserted</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>MMFAR</name>
+                  <displayName>MMFAR</displayName>
+                  <description>Mem Manage Fault Address Register</description>
+                  <addressOffset>0xD34</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Mem Manage fault address field. ADDRESS is the data address of a faulted load or store attempt. When an unaligned access faults, the address is the actual address that faulted. Because an access can be split into multiple parts, each aligned, this address can be any offset in the range of the requested size. Flags in the Memory Manage Fault Status Register indicate the cause of the fault</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>BFAR</name>
+                  <displayName>BFAR</displayName>
+                  <description>Bus Fault Address Register</description>
+                  <addressOffset>0xD38</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Bus fault address field. ADDRESS is the data address of a faulted load or store attempt. When an unaligned access faults, the address is the address requested by the instruction, even if that is not the address that faulted. Flags in the Bus Fault Status Register indicate the cause of the fault</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>AFSR</name>
+                  <displayName>AFSR</displayName>
+                  <description>Auxiliary Fault Status Register</description>
+                  <addressOffset>0xD3C</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>IMPDEF</name>
+                        <description>Implementation defined. The bits map directly onto the signal assignment to the AUXFAULT inputs.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PFR0</name>
+                  <displayName>PFR0</displayName>
+                  <description>Processor Feature register0</description>
+                  <addressOffset>0xD40</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000030</resetValue>
+                  <fields>
+                    <field>
+                        <name>STATE0</name>
+                        <description>State0 (T-bit == 0)</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>no ARM encoding</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>N/A</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>STATE1</name>
+                        <description>State1 (T-bit == 1)</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>N/A</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>N/A</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0010</name>
+                                <description>Thumb-2 encoding with the 16-bit basic instructions plus 32-bit Buncond/BL but no other 32-bit basic instructions (Note non-basic 32-bit instructions can be added using the appropriate instruction attribute, but other 32-bit basic instructions cannot.)</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0011</name>
+                                <description>Thumb-2 encoding with all Thumb-2 basic instructions</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>PFR1</name>
+                  <displayName>PFR1</displayName>
+                  <description>Processor Feature register1</description>
+                  <addressOffset>0xD44</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000200</resetValue>
+                  <fields>
+                    <field>
+                        <name>MICROCONTROLLER_PROGRAMMERS_MODEL</name>
+                        <description>Microcontroller programmer's model</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>not supported</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0010</name>
+                                <description>two-stack support</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DFR0</name>
+                  <displayName>DFR0</displayName>
+                  <description>Debug Feature register0</description>
+                  <addressOffset>0xD48</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00100000</resetValue>
+                  <fields>
+                    <field>
+                        <name>MICROCONTROLLER_DEBUG_MODEL</name>
+                        <description>Microcontroller Debug Model - memory mapped</description>
+                        <bitOffset>0x14</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>not supported</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>Microcontroller debug v1 (ITMv1, DWTv1, optional ETM)</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>AFR0</name>
+                  <displayName>AFR0</displayName>
+                  <description>Auxiliary Feature register0</description>
+                  <addressOffset>0xD4C</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+            </register>
+            <register>
+                  <name>MMFR0</name>
+                  <displayName>MMFR0</displayName>
+                  <description>Memory Model Feature register0</description>
+                  <addressOffset>0xD50</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00100030</resetValue>
+                  <fields>
+                    <field>
+                        <name>PMSA_SUPPORT</name>
+                        <description>PMSA support</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>not supported</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>IMPLEMENTATION DEFINED (N/A)</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0010</name>
+                                <description>PMSA base (features as defined for ARMv6) (N/A)</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0011</name>
+                                <description>PMSAv7 (base plus subregion support)</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CACHE_COHERENCE_SUPPORT</name>
+                        <description>Cache coherence support</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>no shared support</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>partial-inner-shared coherency (coherency amongst some - but not all - of the entities within an inner-coherent domain)</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0010</name>
+                                <description>full-inner-shared coherency (coherency amongst all of the entities within an inner-coherent domain)</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0011</name>
+                                <description>full coherency (coherency amongst all of the entities)</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTER_NON_SHARABLE_SUPPORT</name>
+                        <description>Outer non-sharable support</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>Outer non-sharable not supported</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>Outer sharable supported</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AUXILIARY_REGISTER_SUPPORT</name>
+                        <description>Auxiliary register support</description>
+                        <bitOffset>0x14</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>not supported</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>Auxiliary control register</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>MMFR1</name>
+                  <displayName>MMFR1</displayName>
+                  <description>Memory Model Feature register1</description>
+                  <addressOffset>0xD54</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+            </register>
+            <register>
+                  <name>MMFR2</name>
+                  <displayName>MMFR2</displayName>
+                  <description>Memory Model Feature register2</description>
+                  <addressOffset>0xD58</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>WAIT_FOR_INTERRUPT_STALLING</name>
+                        <description>wait for interrupt stalling</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>not supported</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>wait for interrupt supported</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>MMFR3</name>
+                  <displayName>MMFR3</displayName>
+                  <description>Memory Model Feature register3</description>
+                  <addressOffset>0xD5C</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+            </register>
+            <register>
+                  <name>ISAR0</name>
+                  <displayName>ISAR0</displayName>
+                  <description>ISA Feature register0</description>
+                  <addressOffset>0xD60</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x01141110</resetValue>
+                  <fields>
+                    <field>
+                        <name>BITCOUNT_INSTRS</name>
+                        <description>BitCount instructions</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>no bit-counting instructions present</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>adds CLZ</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>BITFIELD_INSTRS</name>
+                        <description>BitField instructions</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>no bitfield instructions present</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>adds BFC, BFI, SBFX, UBFX</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CMPBRANCH_INSTRS</name>
+                        <description>CmpBranch instructions</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>no combined compare-and-branch instructions present</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>adds CB{N}Z</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>COPROC_INSTRS</name>
+                        <description>Coprocessor instructions</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>no coprocessor support, other than for separately attributed architectures such as CP15 or VFP</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>adds generic CDP, LDC, MCR, MRC, STC</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0010</name>
+                                <description>adds generic CDP2, LDC2, MCR2, MRC2, STC2</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0011</name>
+                                <description>adds generic MCRR, MRRC</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0100</name>
+                                <description>adds generic MCRR2, MRRC2</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DEBUG_INSTRS</name>
+                        <description>Debug instructions</description>
+                        <bitOffset>0x14</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>no debug instructions present</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>adds BKPT</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DIVIDE_INSTRS</name>
+                        <description>Divide instructions</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>no divide instructions present</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>adds SDIV, UDIV (v1 quotient only result)</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>ISAR1</name>
+                  <displayName>ISAR1</displayName>
+                  <description>ISA Feature register1</description>
+                  <addressOffset>0xD64</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x02112000</resetValue>
+                  <fields>
+                    <field>
+                        <name>EXTEND_INSRS</name>
+                        <description>Extend instructions. Note that the shift options on these instructions are also controlled by the WithShifts_instrs attribute.</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>no scalar (i.e. non-SIMD) sign/zero-extend instructions present</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>adds SXTB, SXTH, UXTB, UXTH</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0010</name>
+                                <description>N/A</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>IFTHEN_INSTRS</name>
+                        <description>IfThen instructions</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>IT instructions not present</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>adds IT instructions (and IT bits in PSRs)</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>IMMEDIATE_INSTRS</name>
+                        <description>Immediate instructions</description>
+                        <bitOffset>0x14</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>no special immediate-generating instructions present</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>adds ADDW, MOVW, MOVT, SUBW</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERWORK_INSTRS</name>
+                        <description>Interwork instructions</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>no interworking instructions supported</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>adds BX (and T bit in PSRs)</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0010</name>
+                                <description>adds BLX, and PC loads have BX-like behavior</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0011</name>
+                                <description>N/A</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>ISAR2</name>
+                  <displayName>ISAR2</displayName>
+                  <description>ISA Feature register2</description>
+                  <addressOffset>0xD68</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x21232231</resetValue>
+                  <fields>
+                    <field>
+                        <name>LOADSTORE_INSTRS</name>
+                        <description>LoadStore instructions</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>no additional normal load/store instructions present</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>adds LDRD/STRD</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>MEMHINT_INSTRS</name>
+                        <description>MemoryHint instructions</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>no memory hint instructions presen</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>adds PLD</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0010</name>
+                                <description>adds PLD (ie a repeat on value 1)</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0011</name>
+                                <description>adds PLI</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>MULTIACCESSINT_INSTRS</name>
+                        <description>Multi-Access interruptible instructions</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>the (LDM/STM) instructions are non-interruptible</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>the (LDM/STM) instructions are restartable</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0010</name>
+                                <description>the (LDM/STM) instructions are continuable</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>MULT_INSTRS</name>
+                        <description>Multiply instructions</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>only MUL present</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>adds MLA</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0010</name>
+                                <description>adds MLS</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>MULTS_INSTRS</name>
+                        <description>Multiply instructions (advanced, signed)</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>no signed multiply instructions present</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>adds SMULL, SMLAL</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0010</name>
+                                <description>N/A</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0011</name>
+                                <description>N/A</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>MULTU_INSTRS</name>
+                        <description>Multiply instructions (advanced, unsigned)</description>
+                        <bitOffset>0x14</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>no unsigned multiply instructions present</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>adds UMULL, UMLAL</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0010</name>
+                                <description>N/A</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>REVERSAL_INSTRS</name>
+                        <description>Reversal instructions</description>
+                        <bitOffset>0x1C</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>no reversal instructions present</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>adds REV, REV16, REVSH</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0010</name>
+                                <description>adds RBIT</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>ISAR3</name>
+                  <displayName>ISAR3</displayName>
+                  <description>ISA Feature register3</description>
+                  <addressOffset>0xD6C</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x01111131</resetValue>
+                  <fields>
+                    <field>
+                        <name>SATRUATE_INSTRS</name>
+                        <description>Saturate instructions</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>no non-SIMD saturate instructions present</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>N/A</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SIMD_INSTRS</name>
+                        <description>SIMD instructions</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>no SIMD instructions present</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>adds SSAT, USAT (and the Q flag in the PSRs)</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0011</name>
+                                <description>N/A</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SVC_INSTRS</name>
+                        <description>SVC instructions</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>no SVC (SWI) instructions present</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>adds SVC (SWI)</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SYNCPRIM_INSTRS</name>
+                        <description>SyncPrim instructions. Note there are no LDREXD or STREXD in ARMv7-M. This attribute is used in conjunction with the SyncPrim_instrs_frac attribute in ID_ISAR4[23:20].</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>no synchronization primitives present</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>adds LDREX, STREX</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0010</name>
+                                <description>adds LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, CLREX(N/A)</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TABBRANCH_INSTRS</name>
+                        <description>TableBranch instructions</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>no table-branch instructions present</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>adds TBB, TBH</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>THUMBCOPY_INSTRS</name>
+                        <description>ThumbCopy instructions</description>
+                        <bitOffset>0x14</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>Thumb MOV(register) instruction does not allow low reg -> low reg</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>adds Thumb MOV(register) low reg -> low reg and the CPY alias</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TRUENOP_INSTRS</name>
+                        <description>TrueNOP instructions</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>true NOP instructions not present - that is, NOP instructions with no register dependencies</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>adds "true NOP", and the capability of additional "NOP compatible hints"</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>ISAR4</name>
+                  <displayName>ISAR4</displayName>
+                  <description>ISA Feature register4</description>
+                  <addressOffset>0xD70</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x01310102</resetValue>
+                  <fields>
+                    <field>
+                        <name>UNPRIV_INSTRS</name>
+                        <description>Unprivileged instructions</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>no "T variant" instructions exist</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>adds LDRBT, LDRT, STRBT, STRT</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0010</name>
+                                <description>adds LDRHT, LDRSBT, LDRSHT, STRHT</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>WITHSHIFTS_INSTRS</name>
+                        <description>WithShift instructions. Note that all additions only apply in cases where the encoding supports them - e.g. there is no difference between levels 3 and 4 in the Thumb-2 instruction set. Also note that MOV instructions with shift options should instead be treated as ASR, LSL, LSR, ROR or RRX instructions.</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>non-zero shifts only support MOV and shift instructions (see notes)</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>shifts of loads/stores over the range LSL 0-3</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0010</name>
+                                <description>adds other constant shift options.</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0100</name>
+                                <description>adds register-controlled shift options.</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>WRITEBACK_INSTRS</name>
+                        <description>Writeback instructions</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>only non-writeback addressing modes present, except that LDMIA/STMDB/PUSH/POP instructions support writeback addressing.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>adds all currently-defined writeback addressing modes (ARMv7, Thumb-2)</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>BARRIER_INSTRS</name>
+                        <description>Barrier instructions</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>no barrier instructions supported</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>adds DMB, DSB, ISB barrier instructions</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SYNCPRIM_INSTRS_FRAC</name>
+                        <description>SyncPrim_instrs_frac</description>
+                        <bitOffset>0x14</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>no additional support</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0011</name>
+                                <description>adds CLREX, LDREXB, STREXB, LDREXH, STREXH</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PSR_M_INSTRS</name>
+                        <description>PSR_M_instrs</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0000</name>
+                                <description>instructions not present</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b0001</name>
+                                <description>adds CPS, MRS, and MSR instructions (M-profile forms)</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>CPACR</name>
+                  <displayName>CPACR</displayName>
+                  <description>Coprocessor Access Control Register</description>
+                  <addressOffset>0xD88</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>CP11</name>
+                        <description>Access privileges for coprocessor 11. The possible values of each field are: 0b00 = Access denied. Any attempted access generates a NOCP UsageFault. 0b01 = Privileged access only. An unprivileged access generates a NOCP UsageFault. 0b10 = Reserved. 0b11 = Full access. Used in conjunction with the control for CP10, this controls access to the Floating Point Coprocessor.</description>
+                        <bitOffset>0x16</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CP10</name>
+                        <description>Access privileges for coprocessor 10. The possible values of each field are: 0b00 = Access denied. Any attempted access generates a NOCP UsageFault. 0b01 = Privileged access only. An unprivileged access generates a NOCP UsageFault. 0b10 = Reserved. 0b11 = Full access. Used in conjunction with the control for CP11, this controls access to the Floating Point Coprocessor.</description>
+                        <bitOffset>0x14</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x1000</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>FPCCR</name>
+                  <displayName>FPCCR</displayName>
+                  <description>Floating Point Context Control Register</description>
+                  <addressOffset>0xF34</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0xc0000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>ASPEN</name>
+                        <description>Automatic State Preservation ENable. When this bit is set is will cause bit [2] of the Special CONTROL register to be set (FPCA) on execution of a floating point instruction which results in the floating point state automatically being preserved on exception entry.</description>
+                        <bitOffset>0x1F</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LSPEN</name>
+                        <description>Lazy State Preservation ENable. When the processor performs a context save, space on the stack is reserved for the floating point state but it is not stacked until the new context performs a floating point operation.</description>
+                        <bitOffset>0x1E</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MONRDY</name>
+                        <description>Indicates whether the the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending.</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BFRDY</name>
+                        <description>Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending.</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MMRDY</name>
+                        <description>Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending.</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HFRDY</name>
+                        <description>Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending.</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>THREAD</name>
+                        <description>Indicates the processor mode was Thread when it allocated the FP stack frame.</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USER</name>
+                        <description>Indicates the privilege level of the software executing was User (Unpriviledged) when the processor allocated the FP stack frame.</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LSPACT</name>
+                        <description>Indicates whether Lazy preservation of the FP state is active.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FPCAR</name>
+                  <displayName>FPCAR</displayName>
+                  <description>Floating-Point Context Address Register</description>
+                  <addressOffset>0xF38</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Holds the (double-word-aligned) location of the unpopulated floating-point register space allocated on an exception stack frame.</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1D</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>FPDSCR</name>
+                  <displayName>FPDSCR</displayName>
+                  <description>Floating Point Default Status Control Register</description>
+                  <addressOffset>0xF3C</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>AHP</name>
+                        <description>Default value for Alternative Half Precision bit. (If this bit is set to 1 then Alternative half-precision format is selected).</description>
+                        <bitOffset>0x1A</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DN</name>
+                        <description>Default value for Default NaN mode bit. (If this bit is set to 1 then any operation involving one or more NaNs returns the Default NaN).</description>
+                        <bitOffset>0x19</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FZ</name>
+                        <description>Default value for Flush-to-Zero mode bit. (If this bit is set to 1 then Flush-to-zero mode is enabled).</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RMODE</name>
+                        <description>Default value for Rounding Mode control field. (The encoding for this field is: 0b00 Round to Nearest (RN) mode, 0b01 Round towards Plus Infinity (RP) mode, 0b10 Round towards Minus Infinity (RM) mode, 0b11 Round towards Zero (RZ) mode. The specified rounding mode is used by almost all floating-point instructions).</description>
+                        <bitOffset>0x16</bitOffset>
+                        <bitWidth>0x2</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>MVFR0</name>
+                  <displayName>MVFR0</displayName>
+                  <description>Media and FP Feature Register 0 (MVFR0)</description>
+                  <addressOffset>0xF40</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x10110021</resetValue>
+                  <fields>
+                    <field>
+                        <name>FP_ROUNDING_MODES</name>
+                        <description>Indicates the rounding modes supported by the FP floating-point hardware. The value of this field is: 0b0001 - all rounding modes supported.</description>
+                        <bitOffset>0x1C</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SHORT_VECTORS</name>
+                        <description>Indicates the hardware support for FP short vectors. The value of this field is: 0b0000 - not supported in ARMv7-M.</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SQUARE_ROOT</name>
+                        <description>Indicates the hardware support for FP square root operations. The value of this field is: 0b0001 - supported.</description>
+                        <bitOffset>0x14</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DIVIDE</name>
+                        <description>Indicates the hardware support for FP divide operations. The value of this field is: 0b0001 - supported.</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FP_EXCEPTION_TRAPPING</name>
+                        <description>Indicates whether the FP hardware implementation supports exception trapping. The value of this field is: 0b0000 - not supported in ARMv7-M.</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_PRECISION</name>
+                        <description>Indicates the hardware support for FP double-precision operations. The value of this field is: 0b0000 - not supported in ARMv7-M.</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SINGLE_PRECISION</name>
+                        <description>Indicates the hardware support for FP single-precision operations. The value of this field is: 0b0010 - supported.</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>A_SIMD_REGISTERS</name>
+                        <description>Indicates the size of the FP register bank. The value of this field is: 0b0001 - supported, 16 x 64-bit registers.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>MVFR1</name>
+                  <displayName>MVFR1</displayName>
+                  <description>Media and FP Feature Register 1 (MVFR1)</description>
+                  <addressOffset>0xF44</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x11000011</resetValue>
+                  <fields>
+                    <field>
+                        <name>FP_FUSED_MAC</name>
+                        <description>Indicates whether the FP supports fused multiply accumulate operations. The value of this field is: 0b0001 - supported.</description>
+                        <bitOffset>0x1C</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FP_HPFP</name>
+                        <description>Indicates whether the FP supports half-precision floating-point conversion operations. The value of this field is: 0b0001 - supported.</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>D_NAN_MODE</name>
+                        <description>Indicates whether the FP hardware implementation supports only the Default NaN mode. The value of this field is: 0b0001 - hardware supports propagation of NaN values.</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FTZ_MODE</name>
+                        <description>Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation. The value of this field is: 0b0001 - hardware supports full denormalized number arithmetic.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x1000</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>MPU_TYPE</name>
+                  <displayName>TYPE</displayName>
+                  <description>MPU Type Register</description>
+                  <addressOffset>0xD90</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000800</resetValue>
+                  <fields>
+                    <field>
+                        <name>SEPARATE</name>
+                        <description>Because the processor core uses only a unified MPU, SEPARATE is always 0.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DREGION</name>
+                        <description>Number of supported MPU regions field. DREGION contains 0x08 if the implementation contains an MPU indicating eight MPU regions, otherwise it contains 0x00.</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IREGION</name>
+                        <description>Because the processor core uses only a unified MPU, IREGION always contains 0x00.</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>MPU_CTRL</name>
+                  <displayName>CTRL</displayName>
+                  <description>MPU Control Register</description>
+                  <addressOffset>0xD94</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>MPU enable bit. Reset clears the ENABLE bit.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>disable MPU</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>enable MPU</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HFNMIENA</name>
+                        <description>This bit enables the MPU when in Hard Fault, NMI, and FAULTMASK escalated handlers. If this bit = 1 and the ENABLE bit = 1, the MPU is enabled when in these handlers. If this bit = 0, the MPU is disabled when in these handlers, regardless of the value of ENABLE. If this bit =1 and ENABLE = 0, behavior is Unpredictable. Reset clears the HFNMIENA bit.</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRIVDEFENA</name>
+                        <description>This bit enables the default memory map for privileged access, as a background region, when the MPU is enabled. The background region acts as if it was region number 1 before any settable regions. Any region that is set up overlays this default map, and overrides it. If this bit = 0, the default memory map is disabled, and memory not covered by a region faults. This applies to memory type, Execute Never (XN), cache and shareable rules. However, this only applies to privileged mode (fetch and data access). User mode code faults unless a region has been set up for its code and data. When the MPU is disabled, the default map acts on both privileged and user mode code. XN and SO rules always apply to the System partition whether this enable is set or not. If the MPU is disabled, this bit is ignored. Reset clears the PRIVDEFENA bit.</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>MPU_RNR</name>
+                  <displayName>RNR</displayName>
+                  <description>MPU Region Number Register</description>
+                  <addressOffset>0xD98</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>REGION</name>
+                        <description>Region select field. Selects the region to operate on when using the Region Attribute and Size Register and the Region Base Address Register. It must be written first except when the address VALID + REGION fields are written, which overwrites this.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>MPU_RBAR</name>
+                  <displayName>RBAR</displayName>
+                  <description>MPU Region Base Address Register</description>
+                  <addressOffset>0xD9C</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>REGION</name>
+                        <description>MPU region override field.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x4</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VALID</name>
+                        <description>MPU Region Number valid bit.</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>MPU Region Number Register remains unchanged and is interpreted.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>MPU Region Number Register is overwritten by bits 3:0 (the REGION value).</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADDR</name>
+                        <description>Region base address field. The position of the LSB depends on the region size, so that the base address is aligned according to an even multiple of size. The power of 2 size specified by the SZENABLE field of the MPU Region Attribute and Size Register defines how many bits of base address are used.</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1B</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>MPU_RASR</name>
+                  <displayName>RASR</displayName>
+                  <description>MPU Region Attribute and Size Register</description>
+                  <addressOffset>0xDA0</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Region enable bit.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIZE</name>
+                        <description>MPU Protection Region Size Field.</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x5</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b00100</name>
+                                <description>32B</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b00101</name>
+                                <description>64B</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b00110</name>
+                                <description>128B</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b00111</name>
+                                <description>256B</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b01000</name>
+                                <description>512B</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b01001</name>
+                                <description>1KB</description>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b01010</name>
+                                <description>2KB</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b01011</name>
+                                <description>4KB</description>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b01100</name>
+                                <description>8KB</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b01101</name>
+                                <description>16KB</description>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b01110</name>
+                                <description>32KB</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b01111</name>
+                                <description>64KB</description>
+                                <value>15</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b10000</name>
+                                <description>128KB</description>
+                                <value>16</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b10001</name>
+                                <description>256KB</description>
+                                <value>17</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b10010</name>
+                                <description>512KB</description>
+                                <value>18</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b10011</name>
+                                <description>1MB</description>
+                                <value>19</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b10100</name>
+                                <description>2MB</description>
+                                <value>20</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b10101</name>
+                                <description>4MB</description>
+                                <value>21</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b10110</name>
+                                <description>8MB</description>
+                                <value>22</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b10111</name>
+                                <description>16MB</description>
+                                <value>23</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b11000</name>
+                                <description>32MB</description>
+                                <value>24</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b11001</name>
+                                <description>64MB</description>
+                                <value>25</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b11010</name>
+                                <description>128MB</description>
+                                <value>26</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b11011</name>
+                                <description>256MB</description>
+                                <value>27</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b11100</name>
+                                <description>512MB</description>
+                                <value>28</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b11101</name>
+                                <description>1GB</description>
+                                <value>29</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b11110</name>
+                                <description>2GB</description>
+                                <value>30</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b11111</name>
+                                <description>4GB</description>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SRD</name>
+                        <description>Sub-Region Disable (SRD) field. Setting an SRD bit disables the corresponding sub-region. Regions are split into eight equal-sized sub-regions. Sub-regions are not supported for region sizes of 128 bytes and less.</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>B</name>
+                        <description>Bufferable bit</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>not bufferable</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>bufferable</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>C</name>
+                        <description>Cacheable bit</description>
+                        <bitOffset>0x11</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>not cacheable</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>cacheable</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>S</name>
+                        <description>Shareable bit</description>
+                        <bitOffset>0x12</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>not shareable</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>shareable</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TEX</name>
+                        <description>Type extension field</description>
+                        <bitOffset>0x13</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AP</name>
+                        <description>Data access permission field</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x3</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b000</name>
+                                <description>Priviliged permissions: No access. User permissions: No access.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b001</name>
+                                <description>Priviliged permissions: Read-write. User permissions: No access.</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b010</name>
+                                <description>Priviliged permissions: Read-write. User permissions: Read-only.</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b011</name>
+                                <description>Priviliged permissions: Read-write. User permissions: Read-write.</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b101</name>
+                                <description>Priviliged permissions: Read-only. User permissions: No access.</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b110</name>
+                                <description>Priviliged permissions: Read-only. User permissions: Read-only.</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b111</name>
+                                <description>Priviliged permissions: Read-only. User permissions: Read-only.</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>XN</name>
+                        <description>Instruction access disable bit</description>
+                        <bitOffset>0x1C</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>enable instruction fetches</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>disable instruction fetches</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>MPU_RBAR_A1</name>
+                  <displayName>RBAR_A1</displayName>
+                  <description>MPU Alias 1 Region Base Address register</description>
+                  <addressOffset>0xDA4</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+            </register>
+            <register>
+                  <name>MPU_RASR_A1</name>
+                  <displayName>RASR_A1</displayName>
+                  <description>MPU Alias 1 Region Attribute and Size register</description>
+                  <addressOffset>0xDA8</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+            </register>
+            <register>
+                  <name>MPU_RBAR_A2</name>
+                  <displayName>RBAR_A2</displayName>
+                  <description>MPU Alias 2 Region Base Address register</description>
+                  <addressOffset>0xDAC</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+            </register>
+            <register>
+                  <name>MPU_RASR_A2</name>
+                  <displayName>RASR_A2</displayName>
+                  <description>MPU Alias 2 Region Attribute and Size register</description>
+                  <addressOffset>0xDB0</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+            </register>
+            <register>
+                  <name>MPU_RBAR_A3</name>
+                  <displayName>RBAR_A3</displayName>
+                  <description>MPU Alias 3 Region Base Address register</description>
+                  <addressOffset>0xDB4</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>MPU_RASR_A3</name>
+                  <displayName>RASR_A3</displayName>
+                  <description>MPU Alias 3 Region Attribute and Size register</description>
+                  <addressOffset>0xDB8</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+            </register>
+        </registers>
+        <interrupt>
+            <name>FPU_IRQ</name>
+            <description>FPU Interrupt</description>
+            <value>4</value>
+        </interrupt>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x1000</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>DHCSR</name>
+                  <displayName>DHCSR</displayName>
+                  <description>Debug Halting Control and Status Register</description>
+                  <addressOffset>0xDF0</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xfffeffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>C_DEBUGEN</name>
+                        <description>Enables debug. This can only be written by AHB-AP and not by the core. It is ignored when written by the core, which cannot set or clear it. The core must write a 1 to it when writing C_HALT to halt itself.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>C_HALT</name>
+                        <description>Halts the core. This bit is set automatically when the core Halts. For example Breakpoint. This bit clears on core reset. This bit can only be written if C_DEBUGEN is 1, otherwise it is ignored. When setting this bit to 1, C_DEBUGEN must also be written to 1 in the same value (value[1:0] is 2'b11). The core can halt itself, but only if C_DEBUGEN is already 1 and only if it writes with b11).</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>C_STEP</name>
+                        <description>Steps the core in halted debug. When C_DEBUGEN = 0, this bit has no effect. Must only be modified when the processor is halted (S_HALT == 1).</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>C_MASKINTS</name>
+                        <description>Mask interrupts when stepping or running in halted debug. Does not affect NMI, which is not maskable. Must only be modified when the processor is halted (S_HALT == 1). Also does not affect fault exceptions and SVC caused by execution of the instructions. CMASKINTS must be set or cleared before halt is released. This means that the writes to set or clear C_MASKINTS and to set or clear C_HALT must be separate.</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>C_SNAPSTALL</name>
+                        <description>If the core is stalled on a load/store operation the stall ceases and the instruction is forced to complete. This enables Halting debug to gain control of the core. It can only be set if: C_DEBUGEN = 1 and C_HALT = 1. The core reads S_RETIRE_ST as 0. This indicates that no instruction has advanced. This prevents misuse. The bus state is Unpredictable when this is used. S_RETIRE can detect core stalls on load/store operations.</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>S_REGRDY</name>
+                        <description>Register Read/Write on the Debug Core Register Selector register is available. Last transfer is complete.</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>S_HALT</name>
+                        <description>The core is in debug state when S_HALT is set.</description>
+                        <bitOffset>0x11</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>S_SLEEP</name>
+                        <description>Indicates that the core is sleeping (WFI, WFE, or SLEEP-ON-EXIT). Must use C_HALT to gain control or wait for interrupt to wake-up.</description>
+                        <bitOffset>0x12</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>S_LOCKUP</name>
+                        <description>Reads as one if the core is running (not halted) and a lockup condition is present.</description>
+                        <bitOffset>0x13</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>S_RETIRE_ST</name>
+                        <description>Indicates that an instruction has completed since last read. This is a sticky bit that clears on read. This determines if the core is stalled on a load/store or fetch.</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>S_RESET_ST</name>
+                        <description>Indicates that the core has been reset, or is now being reset, since the last time this bit was read. This a sticky bit that clears on read. So, reading twice and getting 1 then 0 means it was reset in the past. Reading twice and getting 1 both times means that it is being reset now (held in reset still).</description>
+                        <bitOffset>0x19</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DCRSR</name>
+                  <displayName>DCRSR</displayName>
+                  <description>Deubg Core Register Selector Register</description>
+                  <addressOffset>0xDF4</addressOffset>
+                  <size>32</size>
+                  <access>write-only</access>
+                  <fields>
+                    <field>
+                        <name>REGSEL</name>
+                        <description>Register select</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x5</bitWidth>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b00000</name>
+                                <description>R0</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b00001</name>
+                                <description>R1</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b00010</name>
+                                <description>R2</description>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b00011</name>
+                                <description>R3</description>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b00100</name>
+                                <description>R4</description>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b00101</name>
+                                <description>R5</description>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b00110</name>
+                                <description>R6</description>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b00111</name>
+                                <description>R7</description>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b01000</name>
+                                <description>R8</description>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b01001</name>
+                                <description>R9</description>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b01010</name>
+                                <description>R10</description>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b01011</name>
+                                <description>R11</description>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b01100</name>
+                                <description>R12</description>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b01101</name>
+                                <description>Current SP</description>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b01110</name>
+                                <description>LR</description>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b01111</name>
+                                <description>DebugReturnAddress</description>
+                                <value>15</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b10000</name>
+                                <description>xPSR/flags, execution state information, and exception number</description>
+                                <value>16</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b10001</name>
+                                <description>MSP (Main SP)</description>
+                                <value>17</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b10010</name>
+                                <description>PSP (Process SP)</description>
+                                <value>18</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b10100</name>
+                                <description>CONTROL bits [31:24], FAULTMASK bits [23:16], BASEPRI bits [15:8], PRIMASK bits [7:0]</description>
+                                <value>20</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>REGWNR</name>
+                        <description>Write = 1, Read = 0</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>DCRDR</name>
+                  <displayName>DCRDR</displayName>
+                  <description>Debug Core Register Data Register</description>
+                  <addressOffset>0xDF8</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+            </register>
+            <register>
+                  <name>DEMCR</name>
+                  <displayName>DEMCR</displayName>
+                  <description>Debug Exception and Monitor Control Register</description>
+                  <addressOffset>0xDFC</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <fields>
+                    <field>
+                        <name>VC_CORERESET</name>
+                        <description>Reset Vector Catch. Halt running system if Core reset occurs.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VC_MMERR</name>
+                        <description>Debug trap on Memory Management faults.</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VC_NOCPERR</name>
+                        <description>Debug trap on Usage Fault access to Coprocessor that is not present or marked as not present in CAR register.</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VC_CHKERR</name>
+                        <description>Debug trap on Usage Fault enabled checking errors.</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VC_STATERR</name>
+                        <description>Debug trap on Usage Fault state errors.</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VC_BUSERR</name>
+                        <description>Debug Trap on normal Bus error.</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VC_INTERR</name>
+                        <description>Debug Trap on interrupt/exception service errors. These are a subset of other faults and catches before BUSERR or HARDERR.</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VC_HARDERR</name>
+                        <description>Debug trap on Hard Fault.</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MON_EN</name>
+                        <description>Enable the debug monitor. When enabled, the System handler priority register controls its priority level. If disabled, then all debug events go to Hard fault. C_DEBUGEN in the Debug Halting Control and Statue register overrides this bit. Vector catching is semi-synchronous. When a matching event is seen, a Halt is requested. Because the processor can only halt on an instruction boundary, it must wait until the next instruction boundary. As a result, it stops on the first instruction of the exception handler. However, two special cases exist when a vector catch has triggered: 1. If a fault is taken during vectoring, vector read or stack push error, the halt occurs on the corresponding fault handler, for the vector error or stack push. 2. If a late arriving interrupt comes in during vectoring, it is not taken. That is, an implementation that supports the late arrival optimization must suppress it in this case.</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MON_PEND</name>
+                        <description>Pend the monitor to activate when priority permits. This can wake up the monitor through the AHB-AP port. It is the equivalent to C_HALT for Monitor debug. This register does not reset on a system reset. It is only reset by a POR reset. Software in the reset handler or later, or by the DAP must enable the debug monitor.</description>
+                        <bitOffset>0x11</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MON_STEP</name>
+                        <description>When MON_EN = 1, this steps the core. When MON_EN = 0, this bit is ignored. This is the equivalent to C_STEP. Interrupts are only stepped according to the priority of the monitor and settings of PRIMASK, FAULTMASK, or BASEPRI.</description>
+                        <bitOffset>0x12</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MON_REQ</name>
+                        <description>This enables the monitor to identify how it wakes up. This bit clears on a Core Reset.</description>
+                        <bitOffset>0x13</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>en_0b0</name>
+                                <description>woken up by debug exception.</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>en_0b1</name>
+                                <description>woken up by MON_PEND</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TRCENA</name>
+                        <description>This bit must be set to 1 to enable use of the trace and debug blocks: Data Watchpoint and Trace (DWT), Instrumentation Trace Macrocell (ITM), Embedded Trace Macrocell (ETM), Trace Port Interface Unit (TPIU). This enables control of power usage unless tracing is required. The application can enable this, for ITM use, or use by a debugger. Note that if no debug or trace components are present in the implementation then it is not possible to set TRCENA.</description>
+                        <bitOffset>0x18</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>RSTCTL</name>
+        <version>356.0</version>
+        <description>RSTCTL</description>
+        <baseAddress>0xE0042000</baseAddress>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x128</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>RSTCTL_RESET_REQ</name>
+                  <displayName>RESET_REQ</displayName>
+                  <description>Reset Request Register</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffff00fc</resetMask>
+                  <fields>
+                    <field>
+                        <name>SOFT_REQ</name>
+                        <description>Soft Reset request</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>HARD_REQ</name>
+                        <description>Hard Reset request</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>RSTKEY</name>
+                        <description>Write key to unlock reset request bits</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>RSTCTL_HARDRESET_STAT</name>
+                  <displayName>HARDRESET_STAT</displayName>
+                  <description>Hard Reset Status Register</description>
+                  <addressOffset>0x4</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>SRC0</name>
+                        <description>Indicates that SRC0 was the source of the Hard Reset</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRC1</name>
+                        <description>Indicates that SRC1 was the source of the Hard Reset</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRC2</name>
+                        <description>Indicates that SRC2 was the source of the Hard Reset</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRC3</name>
+                        <description>Indicates that SRC3 was the source of the Hard Reset</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRC4</name>
+                        <description>Indicates that SRC4 was the source of the Hard Reset</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRC5</name>
+                        <description>Indicates that SRC5 was the source of the Hard Reset</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRC6</name>
+                        <description>Indicates that SRC6 was the source of the Hard Reset</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRC7</name>
+                        <description>Indicates that SRC7 was the source of the Hard Reset</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRC8</name>
+                        <description>Indicates that SRC8 was the source of the Hard Reset</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRC9</name>
+                        <description>Indicates that SRC9 was the source of the Hard Reset</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRC10</name>
+                        <description>Indicates that SRC10 was the source of the Hard Reset</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRC11</name>
+                        <description>Indicates that SRC11 was the source of the Hard Reset</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRC12</name>
+                        <description>Indicates that SRC12 was the source of the Hard Reset</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRC13</name>
+                        <description>Indicates that SRC13 was the source of the Hard Reset</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRC14</name>
+                        <description>Indicates that SRC14 was the source of the Hard Reset</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRC15</name>
+                        <description>Indicates that SRC15 was the source of the Hard Reset</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>RSTCTL_HARDRESET_CLR</name>
+                  <displayName>HARDRESET_CLR</displayName>
+                  <description>Hard Reset Status Clear Register</description>
+                  <addressOffset>0x8</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffff0000</resetMask>
+                  <fields>
+                    <field>
+                        <name>SRC0</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC1</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC2</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC3</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC4</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC5</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC6</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC7</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC8</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC9</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC10</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC11</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC12</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC13</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC14</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC15</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_HRDRESETSTAT_REG</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>RSTCTL_HARDRESET_SET</name>
+                  <displayName>HARDRESET_SET</displayName>
+                  <description>Hard Reset Status Set Register</description>
+                  <addressOffset>0xC</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>SRC0</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC1</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC2</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC3</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC4</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC5</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC6</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC7</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC8</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC9</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC10</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC11</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC12</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC13</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC14</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC15</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>RSTCTL_SOFTRESET_STAT</name>
+                  <displayName>SOFTRESET_STAT</displayName>
+                  <description>Soft Reset Status Register</description>
+                  <addressOffset>0x10</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>SRC0</name>
+                        <description>If 1, indicates that SRC0 was the source of the Soft Reset</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRC1</name>
+                        <description>If 1, indicates that SRC1 was the source of the Soft Reset</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRC2</name>
+                        <description>If 1, indicates that SRC2 was the source of the Soft Reset</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRC3</name>
+                        <description>If 1, indicates that SRC3 was the source of the Soft Reset</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRC4</name>
+                        <description>If 1, indicates that SRC4 was the source of the Soft Reset</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRC5</name>
+                        <description>If 1, indicates that SRC5 was the source of the Soft Reset</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRC6</name>
+                        <description>If 1, indicates that SRC6 was the source of the Soft Reset</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRC7</name>
+                        <description>If 1, indicates that SRC7 was the source of the Soft Reset</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRC8</name>
+                        <description>If 1, indicates that SRC8 was the source of the Soft Reset</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRC9</name>
+                        <description>If 1, indicates that SRC9 was the source of the Soft Reset</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRC10</name>
+                        <description>If 1, indicates that SRC10 was the source of the Soft Reset</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRC11</name>
+                        <description>If 1, indicates that SRC11 was the source of the Soft Reset</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRC12</name>
+                        <description>If 1, indicates that SRC12 was the source of the Soft Reset</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRC13</name>
+                        <description>If 1, indicates that SRC13 was the source of the Soft Reset</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRC14</name>
+                        <description>If 1, indicates that SRC14 was the source of the Soft Reset</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRC15</name>
+                        <description>If 1, indicates that SRC15 was the source of the Soft Reset</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>RSTCTL_SOFTRESET_CLR</name>
+                  <displayName>SOFTRESET_CLR</displayName>
+                  <description>Soft Reset Status Clear Register</description>
+                  <addressOffset>0x14</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>SRC0</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC1</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC2</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC3</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC4</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC5</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC6</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC7</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC8</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC9</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC10</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC11</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC12</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC13</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC14</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC15</name>
+                        <description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>RSTCTL_SOFTRESET_SET</name>
+                  <displayName>SOFTRESET_SET</displayName>
+                  <description>Soft Reset Status Set Register</description>
+                  <addressOffset>0x18</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>SRC0</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC1</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC2</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC3</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC4</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC5</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC6</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC7</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC8</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC9</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC10</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC11</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC12</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC13</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC14</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SRC15</name>
+                        <description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>RSTCTL_PSSRESET_STAT</name>
+                  <displayName>PSSRESET_STAT</displayName>
+                  <description>PSS Reset Status Register</description>
+                  <addressOffset>0x100</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x0000000f</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>SVSMH</name>
+                        <description>Indicates if POR was caused by an SVSMH trip condition int the PSS</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BGREF</name>
+                        <description>Indicates if POR was caused by a BGREF not okay condition in the PSS</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VCCDET</name>
+                        <description>Indicates if POR was caused by a VCCDET trip condition in the PSS</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SVSL</name>
+                        <description>Indicates if POR was caused by an SVSL trip condition in the PSS</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>RSTCTL_PSSRESET_CLR</name>
+                  <displayName>PSSRESET_CLR</displayName>
+                  <description>PSS Reset Status Clear Register</description>
+                  <addressOffset>0x104</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CLR</name>
+                        <description>Write 1 clears all PSS Reset Flags in the RSTCTL_PSSRESET_STAT</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>RSTCTL_PCMRESET_STAT</name>
+                  <displayName>PCMRESET_STAT</displayName>
+                  <description>PCM Reset Status Register</description>
+                  <addressOffset>0x108</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>LPM35</name>
+                        <description>Indicates if POR was caused by PCM due to an exit from LPM3.5</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LPM45</name>
+                        <description>Indicates if POR was caused by PCM due to an exit from LPM4.5</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>RSTCTL_PCMRESET_CLR</name>
+                  <displayName>PCMRESET_CLR</displayName>
+                  <description>PCM Reset Status Clear Register</description>
+                  <addressOffset>0x10C</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CLR</name>
+                        <description>Write 1 clears all PCM Reset Flags in the RSTCTL_PCMRESET_STAT</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>RSTCTL_PINRESET_STAT</name>
+                  <displayName>PINRESET_STAT</displayName>
+                  <description>Pin Reset Status Register</description>
+                  <addressOffset>0x110</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>RSTNMI</name>
+                        <description>POR was caused by RSTn/NMI pin based reset event</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>RSTCTL_PINRESET_CLR</name>
+                  <displayName>PINRESET_CLR</displayName>
+                  <description>Pin Reset Status Clear Register</description>
+                  <addressOffset>0x114</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CLR</name>
+                        <description>Write 1 clears the RSTn/NMI Pin Reset Flag in RSTCTL_PINRESET_STAT</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>RSTCTL_REBOOTRESET_STAT</name>
+                  <displayName>REBOOTRESET_STAT</displayName>
+                  <description>Reboot Reset Status Register</description>
+                  <addressOffset>0x118</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>REBOOT</name>
+                        <description>Indicates if Reboot reset was caused by the SYSCTL module.</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>RSTCTL_REBOOTRESET_CLR</name>
+                  <displayName>REBOOTRESET_CLR</displayName>
+                  <description>Reboot Reset Status Clear Register</description>
+                  <addressOffset>0x11C</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CLR</name>
+                        <description>Write 1 clears the Reboot Reset Flag in RSTCTL_REBOOTRESET_STAT</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>RSTCTL_CSRESET_STAT</name>
+                  <displayName>CSRESET_STAT</displayName>
+                  <description>CS Reset Status Register</description>
+                  <addressOffset>0x120</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>DCOR_SHT</name>
+                        <description>Indicates if POR was caused by DCO short circuit fault in the external resistor mode</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>RSTCTL_CSRESET_CLR</name>
+                  <displayName>CSRESET_CLR</displayName>
+                  <description>CS Reset Status Clear Register</description>
+                  <addressOffset>0x124</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CLR</name>
+                        <description>Write 1 clears the DCOR_SHT Flag in RSTCTL_CSRESET_STAT as well as DCOR_SHTIFG flag in CSIFG register of clock system</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>SYSCTL</name>
+        <version>356.0</version>
+        <description>SYSCTL</description>
+        <baseAddress>0xE0043000</baseAddress>
+        <addressBlock>
+            <offset>0x0</offset>
+            <size>0x1028</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                  <name>SYS_REBOOT_CTL</name>
+                  <displayName>REBOOT_CTL</displayName>
+                  <description>Reboot Control Register</description>
+                  <addressOffset>0x0</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x000000fe</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>REBOOT</name>
+                        <description>Write 1 initiates a Reboot of the device</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>WKEY</name>
+                        <description>Key to enable writes to bit 0</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>SYS_NMI_CTLSTAT</name>
+                  <displayName>NMI_CTLSTAT</displayName>
+                  <description>NMI Control and Status Register</description>
+                  <addressOffset>0x4</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000007</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>CS_SRC</name>
+                        <description>CS interrupt as a source of NMI</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CS_SRC_0</name>
+                                <description>Disables CS interrupt as a source of NMI</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CS_SRC_1</name>
+                                <description>Enables CS interrupt as a source of NMI</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PSS_SRC</name>
+                        <description>PSS interrupt as a source of NMI</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PSS_SRC_0</name>
+                                <description>Disables the PSS interrupt as a source of NMI</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PSS_SRC_1</name>
+                                <description>Enables the PSS interrupt as a source of NMI</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PCM_SRC</name>
+                        <description>PCM interrupt as a source of NMI</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PCM_SRC_0</name>
+                                <description>Disbles the PCM interrupt as a source of NMI</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PCM_SRC_1</name>
+                                <description>Enables the PCM interrupt as a source of NMI</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PIN_SRC</name>
+                        <description>RSTn/NMI pin configuration

+Note: When the device enters LPM3/LPM4 modes of operation, the functionality selected by this bit is retained. If selected as an NMI, activity on this pin in 

+LPM3/LPM4 wakes the device and processes the interrupt, without causing a POR. If selected as a Reset, activity on this pin in LPM3/LPM4 causes a device-level POR

+When the device enters LPM3.5/LPM4.5 modes of operation, this bit is always cleared to 0. In other words, the RSTn/NMI pin always assumes a reset functionality in LPM3.5/LPM4.5 modes.</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PIN_SRC_0</name>
+                                <description>Configures the RSTn_NMI pin as a source of POR Class Reset</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIN_SRC_1</name>
+                                <description>Configures the RSTn_NMI pin as a source of NMI</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CS_FLG</name>
+                        <description>CS interrupt was the source of NMI</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>CS_FLG_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>CS_FLG_0</name>
+                                <description>indicates CS interrupt was not the source of NMI</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CS_FLG_1</name>
+                                <description>indicates CS interrupt was the source of NMI</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PSS_FLG</name>
+                        <description>PSS interrupt was the source of NMI</description>
+                        <bitOffset>0x11</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>PSS_FLG_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>PSS_FLG_0</name>
+                                <description>indicates the PSS interrupt was not the source of NMI</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PSS_FLG_1</name>
+                                <description>indicates the PSS interrupt was the source of NMI</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PCM_FLG</name>
+                        <description>PCM interrupt was the source of NMI</description>
+                        <bitOffset>0x12</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>PCM_FLG_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>PCM_FLG_0</name>
+                                <description>indicates the PCM interrupt was not the source of NMI</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PCM_FLG_1</name>
+                                <description>indicates the PCM interrupt was the source of NMI</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PIN_FLG</name>
+                        <description>RSTn/NMI pin was the source of NMI</description>
+                        <bitOffset>0x13</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PIN_FLG_0</name>
+                                <description>Indicates the RSTn_NMI pin was not the source of NMI</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIN_FLG_1</name>
+                                <description>Indicates the RSTn_NMI pin was the source of NMI</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>SYS_WDTRESET_CTL</name>
+                  <displayName>WDTRESET_CTL</displayName>
+                  <description>Watchdog Reset Control Register</description>
+                  <addressOffset>0x8</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000003</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>TIMEOUT</name>
+                        <description>WDT timeout reset type</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>TIMEOUT_0</name>
+                                <description>WDT timeout event generates Soft reset</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMEOUT_1</name>
+                                <description>WDT timeout event generates Hard reset</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>VIOLATION</name>
+                        <description>WDT password violation reset type</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>VIOLATION_0</name>
+                                <description>WDT password violation event generates Soft reset</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>VIOLATION_1</name>
+                                <description>WDT password violation event generates Hard reset</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>SYS_PERIHALT_CTL</name>
+                  <displayName>PERIHALT_CTL</displayName>
+                  <description>Peripheral Halt Control Register</description>
+                  <addressOffset>0xC</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00004000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>HALT_T16_0</name>
+                        <description>Freezes IP operation when CPU is halted</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>HALT_T16_0_0</name>
+                                <description>IP operation unaffected when CPU is halted</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HALT_T16_0_1</name>
+                                <description>freezes IP operation when CPU is halted</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HALT_T16_1</name>
+                        <description>Freezes IP operation when CPU is halted</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>HALT_T16_1_0</name>
+                                <description>IP operation unaffected when CPU is halted</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HALT_T16_1_1</name>
+                                <description>freezes IP operation when CPU is halted</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HALT_T16_2</name>
+                        <description>Freezes IP operation when CPU is halted</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>HALT_T16_2_0</name>
+                                <description>IP operation unaffected when CPU is halted</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HALT_T16_2_1</name>
+                                <description>freezes IP operation when CPU is halted</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HALT_T16_3</name>
+                        <description>Freezes IP operation when CPU is halted</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>HALT_T16_3_0</name>
+                                <description>IP operation unaffected when CPU is halted</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HALT_T16_3_1</name>
+                                <description>freezes IP operation when CPU is halted</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HALT_T32_0</name>
+                        <description>Freezes IP operation when CPU is halted</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>HALT_T32_0_0</name>
+                                <description>IP operation unaffected when CPU is halted</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HALT_T32_0_1</name>
+                                <description>freezes IP operation when CPU is halted</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HALT_eUA0</name>
+                        <description>Freezes IP operation when CPU is halted</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>HALT_eUA0_0</name>
+                                <description>IP operation unaffected when CPU is halted</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HALT_eUA0_1</name>
+                                <description>freezes IP operation when CPU is halted</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HALT_eUA1</name>
+                        <description>Freezes IP operation when CPU is halted</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>HALT_eUA1_0</name>
+                                <description>IP operation unaffected when CPU is halted</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HALT_eUA1_1</name>
+                                <description>freezes IP operation when CPU is halted</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HALT_eUA2</name>
+                        <description>Freezes IP operation when CPU is halted</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>HALT_eUA2_0</name>
+                                <description>IP operation unaffected when CPU is halted</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HALT_eUA2_1</name>
+                                <description>freezes IP operation when CPU is halted</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HALT_eUA3</name>
+                        <description>Freezes IP operation when CPU is halted</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>HALT_eUA3_0</name>
+                                <description>IP operation unaffected when CPU is halted</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HALT_eUA3_1</name>
+                                <description>freezes IP operation when CPU is halted</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HALT_eUB0</name>
+                        <description>Freezes IP operation when CPU is halted</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>HALT_eUB0_0</name>
+                                <description>IP operation unaffected when CPU is halted</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HALT_eUB0_1</name>
+                                <description>freezes IP operation when CPU is halted</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HALT_eUB1</name>
+                        <description>Freezes IP operation when CPU is halted</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>HALT_eUB1_0</name>
+                                <description>IP operation unaffected when CPU is halted</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HALT_eUB1_1</name>
+                                <description>freezes IP operation when CPU is halted</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HALT_eUB2</name>
+                        <description>Freezes IP operation when CPU is halted</description>
+                        <bitOffset>0xB</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>HALT_eUB2_0</name>
+                                <description>IP operation unaffected when CPU is halted</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HALT_eUB2_1</name>
+                                <description>freezes IP operation when CPU is halted</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HALT_eUB3</name>
+                        <description>Freezes IP operation when CPU is halted</description>
+                        <bitOffset>0xC</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>HALT_eUB3_0</name>
+                                <description>IP operation unaffected when CPU is halted</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HALT_eUB3_1</name>
+                                <description>freezes IP operation when CPU is halted</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HALT_ADC</name>
+                        <description>Freezes IP operation when CPU is halted</description>
+                        <bitOffset>0xD</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>HALT_ADC_0</name>
+                                <description>IP operation unaffected when CPU is halted</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HALT_ADC_1</name>
+                                <description>freezes IP operation when CPU is halted</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HALT_WDT</name>
+                        <description>Freezes IP operation when CPU is halted</description>
+                        <bitOffset>0xE</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>HALT_WDT_0</name>
+                                <description>IP operation unaffected when CPU is halted</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HALT_WDT_1</name>
+                                <description>freezes IP operation when CPU is halted</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HALT_DMA</name>
+                        <description>Freezes IP operation when CPU is halted</description>
+                        <bitOffset>0xF</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>HALT_DMA_0</name>
+                                <description>IP operation unaffected when CPU is halted</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HALT_DMA_1</name>
+                                <description>freezes IP operation when CPU is halted</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>SYS_SRAM_SIZE</name>
+                  <displayName>SRAM_SIZE</displayName>
+                  <description>SRAM Size Register</description>
+                  <addressOffset>0x10</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <fields>
+                    <field>
+                        <name>SIZE</name>
+                        <description>Indicates the size of SRAM on the device</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>SYS_SRAM_BANKEN</name>
+                  <displayName>SRAM_BANKEN</displayName>
+                  <description>SRAM Bank Enable Register</description>
+                  <addressOffset>0x14</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x000000ff</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>BNK0_EN</name>
+                        <description>SRAM Bank0 enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BNK1_EN</name>
+                        <description>SRAM Bank1 enable</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>BNK1_EN_0</name>
+                                <description>Disables Bank1 of the SRAM</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>BNK1_EN_1</name>
+                                <description>Enables Bank1 of the SRAM</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>BNK2_EN</name>
+                        <description>SRAM Bank1 enable</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>BNK2_EN_0</name>
+                                <description>Disables Bank2 of the SRAM</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>BNK2_EN_1</name>
+                                <description>Enables Bank2 of the SRAM</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>BNK3_EN</name>
+                        <description>SRAM Bank1 enable</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>BNK3_EN_0</name>
+                                <description>Disables Bank3 of the SRAM</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>BNK3_EN_1</name>
+                                <description>Enables Bank3 of the SRAM</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>BNK4_EN</name>
+                        <description>SRAM Bank1 enable</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>BNK4_EN_0</name>
+                                <description>Disables Bank4 of the SRAM</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>BNK4_EN_1</name>
+                                <description>Enables Bank4 of the SRAM</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>BNK5_EN</name>
+                        <description>SRAM Bank1 enable</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>BNK5_EN_0</name>
+                                <description>Disables Bank5 of the SRAM</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>BNK5_EN_1</name>
+                                <description>Enables Bank5 of the SRAM</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>BNK6_EN</name>
+                        <description>SRAM Bank1 enable</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>BNK6_EN_0</name>
+                                <description>Disables Bank6 of the SRAM</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>BNK6_EN_1</name>
+                                <description>Enables Bank6 of the SRAM</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>BNK7_EN</name>
+                        <description>SRAM Bank1 enable</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>BNK7_EN_0</name>
+                                <description>Disables Bank7 of the SRAM</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>BNK7_EN_1</name>
+                                <description>Enables Bank7 of the SRAM</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SRAM_RDY</name>
+                        <description>SRAM ready</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>SRAM_RDY_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>SRAM_RDY_0</name>
+                                <description>SRAM is not ready for accesses. Banks are undergoing an enable or disable sequence, and reads or writes to SRAM are stalled until the banks are ready</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SRAM_RDY_1</name>
+                                <description>SRAM is ready for accesses. All SRAM banks are enabled/disabled according to values of bits 7:0 of this register</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>SYS_SRAM_BANKRET</name>
+                  <displayName>SRAM_BANKRET</displayName>
+                  <description>SRAM Bank Retention Control Register</description>
+                  <addressOffset>0x18</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x000000ff</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>BNK0_RET</name>
+                        <description>Bank0 retention</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BNK1_RET</name>
+                        <description>Bank1 retention</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>BNK1_RET_0</name>
+                                <description>Bank1 of the SRAM is not retained in LPM3 or LPM4</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>BNK1_RET_1</name>
+                                <description>Bank1 of the SRAM is retained in LPM3 and LPM4</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>BNK2_RET</name>
+                        <description>Bank2 retention</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>BNK2_RET_0</name>
+                                <description>Bank2 of the SRAM is not retained in LPM3 or LPM4</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>BNK2_RET_1</name>
+                                <description>Bank2 of the SRAM is retained in LPM3 and LPM4</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>BNK3_RET</name>
+                        <description>Bank3 retention</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>BNK3_RET_0</name>
+                                <description>Bank3 of the SRAM is not retained in LPM3 or LPM4</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>BNK3_RET_1</name>
+                                <description>Bank3 of the SRAM is retained in LPM3 and LPM4</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>BNK4_RET</name>
+                        <description>Bank4 retention</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>BNK4_RET_0</name>
+                                <description>Bank4 of the SRAM is not retained in LPM3 or LPM4</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>BNK4_RET_1</name>
+                                <description>Bank4 of the SRAM is retained in LPM3 and LPM4</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>BNK5_RET</name>
+                        <description>Bank5 retention</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>BNK5_RET_0</name>
+                                <description>Bank5 of the SRAM is not retained in LPM3 or LPM4</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>BNK5_RET_1</name>
+                                <description>Bank5 of the SRAM is retained in LPM3 and LPM4</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>BNK6_RET</name>
+                        <description>Bank6 retention</description>
+                        <bitOffset>0x6</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>BNK6_RET_0</name>
+                                <description>Bank6 of the SRAM is not retained in LPM3 or LPM4</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>BNK6_RET_1</name>
+                                <description>Bank6 of the SRAM is retained in LPM3 and LPM4</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>BNK7_RET</name>
+                        <description>Bank7 retention</description>
+                        <bitOffset>0x7</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>BNK7_RET_0</name>
+                                <description>Bank7 of the SRAM is not retained in LPM3 or LPM4</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>BNK7_RET_1</name>
+                                <description>Bank7 of the SRAM is retained in LPM3 and LPM4</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SRAM_RDY</name>
+                        <description>SRAM ready</description>
+                        <bitOffset>0x10</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <name>SRAM_RDY_enum_read</name>
+                            <usage>read</usage>
+                            <enumeratedValue>
+                                <name>SRAM_RDY_0</name>
+                                <description>SRAM banks are being set up for retention. Entry into LPM3, LPM4 should not be attempted until this bit is set to 1</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SRAM_RDY_1</name>
+                                <description>SRAM is ready for accesses. All SRAM banks are enabled/disabled for retention according to values of bits 7:0 of this register</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>SYS_FLASH_SIZE</name>
+                  <displayName>FLASH_SIZE</displayName>
+                  <description>Flash Size Register</description>
+                  <addressOffset>0x20</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <fields>
+                    <field>
+                        <name>SIZE</name>
+                        <description>Flash User Region size</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>SYS_DIO_GLTFLT_CTL</name>
+                  <displayName>DIO_GLTFLT_CTL</displayName>
+                  <description>Digital I/O Glitch Filter Control Register</description>
+                  <addressOffset>0x30</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000001</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>GLTCH_EN</name>
+                        <description>Glitch filter enable</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>GLTCH_EN_0</name>
+                                <description>Disables glitch filter on the digital I/Os</description>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>GLTCH_EN_1</name>
+                                <description>Enables glitch filter on the digital I/Os</description>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>SYS_SECDATA_UNLOCK</name>
+                  <displayName>SECDATA_UNLOCK</displayName>
+                  <description>IP Protected Secure Zone Data Access Unlock Register</description>
+                  <addressOffset>0x40</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UNLKEY</name>
+                        <description>Unlock key</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>SYS_MASTER_UNLOCK</name>
+                  <displayName>MASTER_UNLOCK</displayName>
+                  <description>Master Unlock Register</description>
+                  <addressOffset>0x1000</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>UNLKEY</name>
+                        <description>Unlock Key</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x10</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <dim>2</dim>
+                  <dimIncrement>4</dimIncrement>
+                  <dimIndex>0,1</dimIndex>
+                  <name>SYS_BOOTOVER_REQ[%s]</name>
+                  <displayName>BOOTOVER_REQ[%s]</displayName>
+                  <description>Boot Override Request Register</description>
+                  <addressOffset>0x1004</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>REGVAL</name>
+                        <description>Value set by debugger, read and clear by the CPU</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>SYS_BOOTOVER_ACK</name>
+                  <displayName>BOOTOVER_ACK</displayName>
+                  <description>Boot Override Acknowledge Register</description>
+                  <addressOffset>0x100C</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0xffffffff</resetMask>
+                  <fields>
+                    <field>
+                        <name>REGVAL</name>
+                        <description>Value set by CPU, read/clear by the debugger</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x20</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>SYS_RESET_REQ</name>
+                  <displayName>RESET_REQ</displayName>
+                  <description>Reset Request Register</description>
+                  <addressOffset>0x1010</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <fields>
+                    <field>
+                        <name>POR</name>
+                        <description>Generate POR</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>REBOOT</name>
+                        <description>Generate Reboot_Reset</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>WKEY</name>
+                        <description>Write key</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x8</bitWidth>
+                        <access>write-only</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>SYS_RESET_STATOVER</name>
+                  <displayName>RESET_STATOVER</displayName>
+                  <description>Reset Status and Override Register</description>
+                  <addressOffset>0x1014</addressOffset>
+                  <size>32</size>
+                  <access>read-write</access>
+                  <resetValue>0x00000000</resetValue>
+                  <resetMask>0x00000700</resetMask>
+                  <fields>
+                    <field>
+                        <name>SOFT</name>
+                        <description>Indicates if SOFT Reset is active</description>
+                        <bitOffset>0x0</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HARD</name>
+                        <description>Indicates if HARD Reset is active</description>
+                        <bitOffset>0x1</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>REBOOT</name>
+                        <description>Indicates if Reboot Reset is active</description>
+                        <bitOffset>0x2</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SOFT_OVER</name>
+                        <description>SOFT_Reset overwrite request</description>
+                        <bitOffset>0x8</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HARD_OVER</name>
+                        <description>HARD_Reset overwrite request</description>
+                        <bitOffset>0x9</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RBT_OVER</name>
+                        <description>Reboot Reset overwrite request</description>
+                        <bitOffset>0xA</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-write</access>
+                    </field>
+                  </fields>
+            </register>
+            <register>
+                  <name>SYS_SYSTEM_STAT</name>
+                  <displayName>SYSTEM_STAT</displayName>
+                  <description>System Status Register</description>
+                  <addressOffset>0x1020</addressOffset>
+                  <size>32</size>
+                  <access>read-only</access>
+                  <fields>
+                    <field>
+                        <name>DBG_SEC_ACT</name>
+                        <description>Debug Security active</description>
+                        <bitOffset>0x3</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>JTAG_SWD_LOCK_ACT</name>
+                        <description>Indicates if JTAG and SWD Lock is active</description>
+                        <bitOffset>0x4</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IP_PROT_ACT</name>
+                        <description>Indicates if IP protection is active</description>
+                        <bitOffset>0x5</bitOffset>
+                        <bitWidth>0x1</bitWidth>
+                        <access>read-only</access>
+                    </field>
+                  </fields>
+            </register>
+        </registers>
+    </peripheral>
+   </peripherals>
+</device>
+
+
diff --git a/example-source/msp432p401r/build.rs b/example-source/msp432p401r/build.rs
new file mode 100644
index 0000000..597923f
--- /dev/null
+++ b/example-source/msp432p401r/build.rs
@@ -0,0 +1,16 @@
+use std::env;
+use std::fs::File;
+use std::io::Write;
+use std::path::PathBuf;
+fn main() {
+    if env::var_os("CARGO_FEATURE_RT").is_some() {
+        let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+        File::create(out.join("device.x"))
+            .unwrap()
+            .write_all(include_bytes!("device.x"))
+            .unwrap();
+        println!("cargo:rustc-link-search={}", out.display());
+        println!("cargo:rerun-if-changed=device.x");
+    }
+    println!("cargo:rerun-if-changed=build.rs");
+}
diff --git a/example-source/msp432p401r/device.x b/example-source/msp432p401r/device.x
new file mode 100644
index 0000000..377cc01
--- /dev/null
+++ b/example-source/msp432p401r/device.x
@@ -0,0 +1,42 @@
+PROVIDE(PSS_IRQ = DefaultHandler);
+PROVIDE(CS_IRQ = DefaultHandler);
+PROVIDE(PCM_IRQ = DefaultHandler);
+PROVIDE(WDT_A_IRQ = DefaultHandler);
+PROVIDE(FPU_IRQ = DefaultHandler);
+PROVIDE(FLCTL_IRQ = DefaultHandler);
+PROVIDE(COMP_E0_IRQ = DefaultHandler);
+PROVIDE(COMP_E1_IRQ = DefaultHandler);
+PROVIDE(TA0_0_IRQ = DefaultHandler);
+PROVIDE(TA0_N_IRQ = DefaultHandler);
+PROVIDE(TA1_0_IRQ = DefaultHandler);
+PROVIDE(TA1_N_IRQ = DefaultHandler);
+PROVIDE(TA2_0_IRQ = DefaultHandler);
+PROVIDE(TA2_N_IRQ = DefaultHandler);
+PROVIDE(TA3_0_IRQ = DefaultHandler);
+PROVIDE(TA3_N_IRQ = DefaultHandler);
+PROVIDE(EUSCIA0_IRQ = DefaultHandler);
+PROVIDE(EUSCIA1_IRQ = DefaultHandler);
+PROVIDE(EUSCIA2_IRQ = DefaultHandler);
+PROVIDE(EUSCIA3_IRQ = DefaultHandler);
+PROVIDE(EUSCIB0_IRQ = DefaultHandler);
+PROVIDE(EUSCIB1_IRQ = DefaultHandler);
+PROVIDE(EUSCIB2_IRQ = DefaultHandler);
+PROVIDE(EUSCIB3_IRQ = DefaultHandler);
+PROVIDE(ADC14_IRQ = DefaultHandler);
+PROVIDE(T32_INT1_IRQ = DefaultHandler);
+PROVIDE(T32_INT2_IRQ = DefaultHandler);
+PROVIDE(T32_INTC_IRQ = DefaultHandler);
+PROVIDE(AES256_IRQ = DefaultHandler);
+PROVIDE(RTC_C_IRQ = DefaultHandler);
+PROVIDE(DMA_ERR_IRQ = DefaultHandler);
+PROVIDE(DMA_INT3_IRQ = DefaultHandler);
+PROVIDE(DMA_INT2_IRQ = DefaultHandler);
+PROVIDE(DMA_INT1_IRQ = DefaultHandler);
+PROVIDE(DMA_INT0_IRQ = DefaultHandler);
+PROVIDE(PORT1_IRQ = DefaultHandler);
+PROVIDE(PORT2_IRQ = DefaultHandler);
+PROVIDE(PORT3_IRQ = DefaultHandler);
+PROVIDE(PORT4_IRQ = DefaultHandler);
+PROVIDE(PORT5_IRQ = DefaultHandler);
+PROVIDE(PORT6_IRQ = DefaultHandler);
+
diff --git a/example-source/msp432p401r/src/adc14.rs b/example-source/msp432p401r/src/adc14.rs
new file mode 100644
index 0000000..7db4c46
--- /dev/null
+++ b/example-source/msp432p401r/src/adc14.rs
@@ -0,0 +1,125 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - Control 0 Register"]
+    pub adc14ctl0: ADC14CTL0,
+    #[doc = "0x04 - Control 1 Register"]
+    pub adc14ctl1: ADC14CTL1,
+    #[doc = "0x08 - Window Comparator Low Threshold 0 Register"]
+    pub adc14lo0: ADC14LO0,
+    #[doc = "0x0c - Window Comparator High Threshold 0 Register"]
+    pub adc14hi0: ADC14HI0,
+    #[doc = "0x10 - Window Comparator Low Threshold 1 Register"]
+    pub adc14lo1: ADC14LO1,
+    #[doc = "0x14 - Window Comparator High Threshold 1 Register"]
+    pub adc14hi1: ADC14HI1,
+    #[doc = "0x18 - Conversion Memory Control Register"]
+    pub adc14mctl: [ADC14MCTL; 32],
+    #[doc = "0x98 - Conversion Memory Register"]
+    pub adc14mem: [ADC14MEM; 32],
+    _reserved0: [u8; 36usize],
+    #[doc = "0x13c - Interrupt Enable 0 Register"]
+    pub adc14ier0: ADC14IER0,
+    #[doc = "0x140 - Interrupt Enable 1 Register"]
+    pub adc14ier1: ADC14IER1,
+    #[doc = "0x144 - Interrupt Flag 0 Register"]
+    pub adc14ifgr0: ADC14IFGR0,
+    #[doc = "0x148 - Interrupt Flag 1 Register"]
+    pub adc14ifgr1: ADC14IFGR1,
+    #[doc = "0x14c - Clear Interrupt Flag 0 Register"]
+    pub adc14clrifgr0: ADC14CLRIFGR0,
+    #[doc = "0x150 - Clear Interrupt Flag 1 Register"]
+    pub adc14clrifgr1: ADC14CLRIFGR1,
+    #[doc = "0x154 - Interrupt Vector Register"]
+    pub adc14iv: ADC14IV,
+}
+#[doc = "Control 0 Register"]
+pub struct ADC14CTL0 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Control 0 Register"]
+pub mod adc14ctl0;
+#[doc = "Control 1 Register"]
+pub struct ADC14CTL1 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Control 1 Register"]
+pub mod adc14ctl1;
+#[doc = "Window Comparator Low Threshold 0 Register"]
+pub struct ADC14LO0 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Window Comparator Low Threshold 0 Register"]
+pub mod adc14lo0;
+#[doc = "Window Comparator High Threshold 0 Register"]
+pub struct ADC14HI0 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Window Comparator High Threshold 0 Register"]
+pub mod adc14hi0;
+#[doc = "Window Comparator Low Threshold 1 Register"]
+pub struct ADC14LO1 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Window Comparator Low Threshold 1 Register"]
+pub mod adc14lo1;
+#[doc = "Window Comparator High Threshold 1 Register"]
+pub struct ADC14HI1 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Window Comparator High Threshold 1 Register"]
+pub mod adc14hi1;
+#[doc = "Conversion Memory Control Register"]
+pub struct ADC14MCTL {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Conversion Memory Control Register"]
+pub mod adc14mctl;
+#[doc = "Conversion Memory Register"]
+pub struct ADC14MEM {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Conversion Memory Register"]
+pub mod adc14mem;
+#[doc = "Interrupt Enable 0 Register"]
+pub struct ADC14IER0 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Interrupt Enable 0 Register"]
+pub mod adc14ier0;
+#[doc = "Interrupt Enable 1 Register"]
+pub struct ADC14IER1 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Interrupt Enable 1 Register"]
+pub mod adc14ier1;
+#[doc = "Interrupt Flag 0 Register"]
+pub struct ADC14IFGR0 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Interrupt Flag 0 Register"]
+pub mod adc14ifgr0;
+#[doc = "Interrupt Flag 1 Register"]
+pub struct ADC14IFGR1 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Interrupt Flag 1 Register"]
+pub mod adc14ifgr1;
+#[doc = "Clear Interrupt Flag 0 Register"]
+pub struct ADC14CLRIFGR0 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Clear Interrupt Flag 0 Register"]
+pub mod adc14clrifgr0;
+#[doc = "Clear Interrupt Flag 1 Register"]
+pub struct ADC14CLRIFGR1 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Clear Interrupt Flag 1 Register"]
+pub mod adc14clrifgr1;
+#[doc = "Interrupt Vector Register"]
+pub struct ADC14IV {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Interrupt Vector Register"]
+pub mod adc14iv;
diff --git a/example-source/msp432p401r/src/adc14/adc14clrifgr0.rs b/example-source/msp432p401r/src/adc14/adc14clrifgr0.rs
new file mode 100644
index 0000000..c0eca99
--- /dev/null
+++ b/example-source/msp432p401r/src/adc14/adc14clrifgr0.rs
@@ -0,0 +1,2045 @@
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::ADC14CLRIFGR0 {
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG0`"]
+pub enum CLRADC14IFG0W {
+    #[doc = "no effect"]
+    CLRADC14IFG0_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG0_1,
+}
+impl CLRADC14IFG0W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG0W::CLRADC14IFG0_0 => false,
+            CLRADC14IFG0W::CLRADC14IFG0_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG0W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG0W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg0_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG0W::CLRADC14IFG0_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg0_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG0W::CLRADC14IFG0_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG1`"]
+pub enum CLRADC14IFG1W {
+    #[doc = "no effect"]
+    CLRADC14IFG1_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG1_1,
+}
+impl CLRADC14IFG1W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG1W::CLRADC14IFG1_0 => false,
+            CLRADC14IFG1W::CLRADC14IFG1_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG1W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG1W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg1_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG1W::CLRADC14IFG1_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg1_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG1W::CLRADC14IFG1_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG2`"]
+pub enum CLRADC14IFG2W {
+    #[doc = "no effect"]
+    CLRADC14IFG2_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG2_1,
+}
+impl CLRADC14IFG2W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG2W::CLRADC14IFG2_0 => false,
+            CLRADC14IFG2W::CLRADC14IFG2_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG2W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG2W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg2_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG2W::CLRADC14IFG2_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg2_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG2W::CLRADC14IFG2_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG3`"]
+pub enum CLRADC14IFG3W {
+    #[doc = "no effect"]
+    CLRADC14IFG3_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG3_1,
+}
+impl CLRADC14IFG3W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG3W::CLRADC14IFG3_0 => false,
+            CLRADC14IFG3W::CLRADC14IFG3_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG3W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG3W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg3_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG3W::CLRADC14IFG3_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg3_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG3W::CLRADC14IFG3_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG4`"]
+pub enum CLRADC14IFG4W {
+    #[doc = "no effect"]
+    CLRADC14IFG4_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG4_1,
+}
+impl CLRADC14IFG4W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG4W::CLRADC14IFG4_0 => false,
+            CLRADC14IFG4W::CLRADC14IFG4_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG4W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG4W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG4W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg4_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG4W::CLRADC14IFG4_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg4_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG4W::CLRADC14IFG4_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG5`"]
+pub enum CLRADC14IFG5W {
+    #[doc = "no effect"]
+    CLRADC14IFG5_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG5_1,
+}
+impl CLRADC14IFG5W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG5W::CLRADC14IFG5_0 => false,
+            CLRADC14IFG5W::CLRADC14IFG5_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG5W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG5W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG5W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg5_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG5W::CLRADC14IFG5_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg5_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG5W::CLRADC14IFG5_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG6`"]
+pub enum CLRADC14IFG6W {
+    #[doc = "no effect"]
+    CLRADC14IFG6_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG6_1,
+}
+impl CLRADC14IFG6W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG6W::CLRADC14IFG6_0 => false,
+            CLRADC14IFG6W::CLRADC14IFG6_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG6W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG6W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG6W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg6_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG6W::CLRADC14IFG6_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg6_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG6W::CLRADC14IFG6_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG7`"]
+pub enum CLRADC14IFG7W {
+    #[doc = "no effect"]
+    CLRADC14IFG7_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG7_1,
+}
+impl CLRADC14IFG7W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG7W::CLRADC14IFG7_0 => false,
+            CLRADC14IFG7W::CLRADC14IFG7_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG7W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG7W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG7W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg7_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG7W::CLRADC14IFG7_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg7_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG7W::CLRADC14IFG7_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG8`"]
+pub enum CLRADC14IFG8W {
+    #[doc = "no effect"]
+    CLRADC14IFG8_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG8_1,
+}
+impl CLRADC14IFG8W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG8W::CLRADC14IFG8_0 => false,
+            CLRADC14IFG8W::CLRADC14IFG8_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG8W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG8W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG8W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg8_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG8W::CLRADC14IFG8_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg8_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG8W::CLRADC14IFG8_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG9`"]
+pub enum CLRADC14IFG9W {
+    #[doc = "no effect"]
+    CLRADC14IFG9_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG9_1,
+}
+impl CLRADC14IFG9W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG9W::CLRADC14IFG9_0 => false,
+            CLRADC14IFG9W::CLRADC14IFG9_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG9W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG9W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG9W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg9_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG9W::CLRADC14IFG9_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg9_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG9W::CLRADC14IFG9_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG10`"]
+pub enum CLRADC14IFG10W {
+    #[doc = "no effect"]
+    CLRADC14IFG10_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG10_1,
+}
+impl CLRADC14IFG10W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG10W::CLRADC14IFG10_0 => false,
+            CLRADC14IFG10W::CLRADC14IFG10_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG10W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG10W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG10W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg10_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG10W::CLRADC14IFG10_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg10_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG10W::CLRADC14IFG10_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG11`"]
+pub enum CLRADC14IFG11W {
+    #[doc = "no effect"]
+    CLRADC14IFG11_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG11_1,
+}
+impl CLRADC14IFG11W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG11W::CLRADC14IFG11_0 => false,
+            CLRADC14IFG11W::CLRADC14IFG11_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG11W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG11W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG11W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg11_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG11W::CLRADC14IFG11_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg11_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG11W::CLRADC14IFG11_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG12`"]
+pub enum CLRADC14IFG12W {
+    #[doc = "no effect"]
+    CLRADC14IFG12_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG12_1,
+}
+impl CLRADC14IFG12W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG12W::CLRADC14IFG12_0 => false,
+            CLRADC14IFG12W::CLRADC14IFG12_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG12W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG12W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG12W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg12_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG12W::CLRADC14IFG12_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg12_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG12W::CLRADC14IFG12_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG13`"]
+pub enum CLRADC14IFG13W {
+    #[doc = "no effect"]
+    CLRADC14IFG13_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG13_1,
+}
+impl CLRADC14IFG13W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG13W::CLRADC14IFG13_0 => false,
+            CLRADC14IFG13W::CLRADC14IFG13_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG13W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG13W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG13W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg13_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG13W::CLRADC14IFG13_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg13_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG13W::CLRADC14IFG13_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG14`"]
+pub enum CLRADC14IFG14W {
+    #[doc = "no effect"]
+    CLRADC14IFG14_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG14_1,
+}
+impl CLRADC14IFG14W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG14W::CLRADC14IFG14_0 => false,
+            CLRADC14IFG14W::CLRADC14IFG14_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG14W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG14W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG14W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg14_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG14W::CLRADC14IFG14_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg14_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG14W::CLRADC14IFG14_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG15`"]
+pub enum CLRADC14IFG15W {
+    #[doc = "no effect"]
+    CLRADC14IFG15_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG15_1,
+}
+impl CLRADC14IFG15W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG15W::CLRADC14IFG15_0 => false,
+            CLRADC14IFG15W::CLRADC14IFG15_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG15W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG15W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG15W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg15_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG15W::CLRADC14IFG15_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg15_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG15W::CLRADC14IFG15_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG16`"]
+pub enum CLRADC14IFG16W {
+    #[doc = "no effect"]
+    CLRADC14IFG16_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG16_1,
+}
+impl CLRADC14IFG16W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG16W::CLRADC14IFG16_0 => false,
+            CLRADC14IFG16W::CLRADC14IFG16_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG16W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG16W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG16W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg16_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG16W::CLRADC14IFG16_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg16_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG16W::CLRADC14IFG16_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 16;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG17`"]
+pub enum CLRADC14IFG17W {
+    #[doc = "no effect"]
+    CLRADC14IFG17_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG17_1,
+}
+impl CLRADC14IFG17W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG17W::CLRADC14IFG17_0 => false,
+            CLRADC14IFG17W::CLRADC14IFG17_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG17W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG17W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG17W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg17_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG17W::CLRADC14IFG17_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg17_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG17W::CLRADC14IFG17_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 17;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG18`"]
+pub enum CLRADC14IFG18W {
+    #[doc = "no effect"]
+    CLRADC14IFG18_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG18_1,
+}
+impl CLRADC14IFG18W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG18W::CLRADC14IFG18_0 => false,
+            CLRADC14IFG18W::CLRADC14IFG18_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG18W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG18W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG18W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg18_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG18W::CLRADC14IFG18_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg18_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG18W::CLRADC14IFG18_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 18;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG19`"]
+pub enum CLRADC14IFG19W {
+    #[doc = "no effect"]
+    CLRADC14IFG19_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG19_1,
+}
+impl CLRADC14IFG19W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG19W::CLRADC14IFG19_0 => false,
+            CLRADC14IFG19W::CLRADC14IFG19_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG19W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG19W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG19W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg19_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG19W::CLRADC14IFG19_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg19_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG19W::CLRADC14IFG19_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 19;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG20`"]
+pub enum CLRADC14IFG20W {
+    #[doc = "no effect"]
+    CLRADC14IFG20_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG20_1,
+}
+impl CLRADC14IFG20W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG20W::CLRADC14IFG20_0 => false,
+            CLRADC14IFG20W::CLRADC14IFG20_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG20W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG20W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG20W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg20_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG20W::CLRADC14IFG20_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg20_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG20W::CLRADC14IFG20_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 20;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG21`"]
+pub enum CLRADC14IFG21W {
+    #[doc = "no effect"]
+    CLRADC14IFG21_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG21_1,
+}
+impl CLRADC14IFG21W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG21W::CLRADC14IFG21_0 => false,
+            CLRADC14IFG21W::CLRADC14IFG21_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG21W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG21W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG21W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg21_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG21W::CLRADC14IFG21_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg21_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG21W::CLRADC14IFG21_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 21;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG22`"]
+pub enum CLRADC14IFG22W {
+    #[doc = "no effect"]
+    CLRADC14IFG22_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG22_1,
+}
+impl CLRADC14IFG22W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG22W::CLRADC14IFG22_0 => false,
+            CLRADC14IFG22W::CLRADC14IFG22_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG22W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG22W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG22W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg22_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG22W::CLRADC14IFG22_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg22_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG22W::CLRADC14IFG22_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 22;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG23`"]
+pub enum CLRADC14IFG23W {
+    #[doc = "no effect"]
+    CLRADC14IFG23_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG23_1,
+}
+impl CLRADC14IFG23W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG23W::CLRADC14IFG23_0 => false,
+            CLRADC14IFG23W::CLRADC14IFG23_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG23W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG23W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG23W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg23_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG23W::CLRADC14IFG23_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg23_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG23W::CLRADC14IFG23_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 23;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG24`"]
+pub enum CLRADC14IFG24W {
+    #[doc = "no effect"]
+    CLRADC14IFG24_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG24_1,
+}
+impl CLRADC14IFG24W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG24W::CLRADC14IFG24_0 => false,
+            CLRADC14IFG24W::CLRADC14IFG24_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG24W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG24W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG24W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg24_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG24W::CLRADC14IFG24_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg24_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG24W::CLRADC14IFG24_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 24;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG25`"]
+pub enum CLRADC14IFG25W {
+    #[doc = "no effect"]
+    CLRADC14IFG25_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG25_1,
+}
+impl CLRADC14IFG25W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG25W::CLRADC14IFG25_0 => false,
+            CLRADC14IFG25W::CLRADC14IFG25_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG25W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG25W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG25W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg25_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG25W::CLRADC14IFG25_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg25_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG25W::CLRADC14IFG25_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 25;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG26`"]
+pub enum CLRADC14IFG26W {
+    #[doc = "no effect"]
+    CLRADC14IFG26_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG26_1,
+}
+impl CLRADC14IFG26W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG26W::CLRADC14IFG26_0 => false,
+            CLRADC14IFG26W::CLRADC14IFG26_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG26W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG26W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG26W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg26_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG26W::CLRADC14IFG26_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg26_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG26W::CLRADC14IFG26_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 26;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG27`"]
+pub enum CLRADC14IFG27W {
+    #[doc = "no effect"]
+    CLRADC14IFG27_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG27_1,
+}
+impl CLRADC14IFG27W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG27W::CLRADC14IFG27_0 => false,
+            CLRADC14IFG27W::CLRADC14IFG27_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG27W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG27W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG27W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg27_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG27W::CLRADC14IFG27_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg27_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG27W::CLRADC14IFG27_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 27;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG28`"]
+pub enum CLRADC14IFG28W {
+    #[doc = "no effect"]
+    CLRADC14IFG28_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG28_1,
+}
+impl CLRADC14IFG28W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG28W::CLRADC14IFG28_0 => false,
+            CLRADC14IFG28W::CLRADC14IFG28_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG28W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG28W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG28W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg28_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG28W::CLRADC14IFG28_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg28_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG28W::CLRADC14IFG28_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 28;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG29`"]
+pub enum CLRADC14IFG29W {
+    #[doc = "no effect"]
+    CLRADC14IFG29_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG29_1,
+}
+impl CLRADC14IFG29W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG29W::CLRADC14IFG29_0 => false,
+            CLRADC14IFG29W::CLRADC14IFG29_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG29W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG29W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG29W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg29_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG29W::CLRADC14IFG29_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg29_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG29W::CLRADC14IFG29_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 29;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG30`"]
+pub enum CLRADC14IFG30W {
+    #[doc = "no effect"]
+    CLRADC14IFG30_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG30_1,
+}
+impl CLRADC14IFG30W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG30W::CLRADC14IFG30_0 => false,
+            CLRADC14IFG30W::CLRADC14IFG30_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG30W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG30W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG30W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg30_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG30W::CLRADC14IFG30_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg30_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG30W::CLRADC14IFG30_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 30;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14IFG31`"]
+pub enum CLRADC14IFG31W {
+    #[doc = "no effect"]
+    CLRADC14IFG31_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14IFG31_1,
+}
+impl CLRADC14IFG31W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14IFG31W::CLRADC14IFG31_0 => false,
+            CLRADC14IFG31W::CLRADC14IFG31_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14IFG31W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14IFG31W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14IFG31W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ifg31_0(self) -> &'a mut W {
+        self.variant(CLRADC14IFG31W::CLRADC14IFG31_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ifg31_1(self) -> &'a mut W {
+        self.variant(CLRADC14IFG31W::CLRADC14IFG31_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 31;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - clear ADC14IFG0"]
+    #[inline]
+    pub fn clradc14ifg0(&mut self) -> _CLRADC14IFG0W {
+        _CLRADC14IFG0W { w: self }
+    }
+    #[doc = "Bit 1 - clear ADC14IFG1"]
+    #[inline]
+    pub fn clradc14ifg1(&mut self) -> _CLRADC14IFG1W {
+        _CLRADC14IFG1W { w: self }
+    }
+    #[doc = "Bit 2 - clear ADC14IFG2"]
+    #[inline]
+    pub fn clradc14ifg2(&mut self) -> _CLRADC14IFG2W {
+        _CLRADC14IFG2W { w: self }
+    }
+    #[doc = "Bit 3 - clear ADC14IFG3"]
+    #[inline]
+    pub fn clradc14ifg3(&mut self) -> _CLRADC14IFG3W {
+        _CLRADC14IFG3W { w: self }
+    }
+    #[doc = "Bit 4 - clear ADC14IFG4"]
+    #[inline]
+    pub fn clradc14ifg4(&mut self) -> _CLRADC14IFG4W {
+        _CLRADC14IFG4W { w: self }
+    }
+    #[doc = "Bit 5 - clear ADC14IFG5"]
+    #[inline]
+    pub fn clradc14ifg5(&mut self) -> _CLRADC14IFG5W {
+        _CLRADC14IFG5W { w: self }
+    }
+    #[doc = "Bit 6 - clear ADC14IFG6"]
+    #[inline]
+    pub fn clradc14ifg6(&mut self) -> _CLRADC14IFG6W {
+        _CLRADC14IFG6W { w: self }
+    }
+    #[doc = "Bit 7 - clear ADC14IFG7"]
+    #[inline]
+    pub fn clradc14ifg7(&mut self) -> _CLRADC14IFG7W {
+        _CLRADC14IFG7W { w: self }
+    }
+    #[doc = "Bit 8 - clear ADC14IFG8"]
+    #[inline]
+    pub fn clradc14ifg8(&mut self) -> _CLRADC14IFG8W {
+        _CLRADC14IFG8W { w: self }
+    }
+    #[doc = "Bit 9 - clear ADC14IFG9"]
+    #[inline]
+    pub fn clradc14ifg9(&mut self) -> _CLRADC14IFG9W {
+        _CLRADC14IFG9W { w: self }
+    }
+    #[doc = "Bit 10 - clear ADC14IFG10"]
+    #[inline]
+    pub fn clradc14ifg10(&mut self) -> _CLRADC14IFG10W {
+        _CLRADC14IFG10W { w: self }
+    }
+    #[doc = "Bit 11 - clear ADC14IFG11"]
+    #[inline]
+    pub fn clradc14ifg11(&mut self) -> _CLRADC14IFG11W {
+        _CLRADC14IFG11W { w: self }
+    }
+    #[doc = "Bit 12 - clear ADC14IFG12"]
+    #[inline]
+    pub fn clradc14ifg12(&mut self) -> _CLRADC14IFG12W {
+        _CLRADC14IFG12W { w: self }
+    }
+    #[doc = "Bit 13 - clear ADC14IFG13"]
+    #[inline]
+    pub fn clradc14ifg13(&mut self) -> _CLRADC14IFG13W {
+        _CLRADC14IFG13W { w: self }
+    }
+    #[doc = "Bit 14 - clear ADC14IFG14"]
+    #[inline]
+    pub fn clradc14ifg14(&mut self) -> _CLRADC14IFG14W {
+        _CLRADC14IFG14W { w: self }
+    }
+    #[doc = "Bit 15 - clear ADC14IFG15"]
+    #[inline]
+    pub fn clradc14ifg15(&mut self) -> _CLRADC14IFG15W {
+        _CLRADC14IFG15W { w: self }
+    }
+    #[doc = "Bit 16 - clear ADC14IFG16"]
+    #[inline]
+    pub fn clradc14ifg16(&mut self) -> _CLRADC14IFG16W {
+        _CLRADC14IFG16W { w: self }
+    }
+    #[doc = "Bit 17 - clear ADC14IFG17"]
+    #[inline]
+    pub fn clradc14ifg17(&mut self) -> _CLRADC14IFG17W {
+        _CLRADC14IFG17W { w: self }
+    }
+    #[doc = "Bit 18 - clear ADC14IFG18"]
+    #[inline]
+    pub fn clradc14ifg18(&mut self) -> _CLRADC14IFG18W {
+        _CLRADC14IFG18W { w: self }
+    }
+    #[doc = "Bit 19 - clear ADC14IFG19"]
+    #[inline]
+    pub fn clradc14ifg19(&mut self) -> _CLRADC14IFG19W {
+        _CLRADC14IFG19W { w: self }
+    }
+    #[doc = "Bit 20 - clear ADC14IFG20"]
+    #[inline]
+    pub fn clradc14ifg20(&mut self) -> _CLRADC14IFG20W {
+        _CLRADC14IFG20W { w: self }
+    }
+    #[doc = "Bit 21 - clear ADC14IFG21"]
+    #[inline]
+    pub fn clradc14ifg21(&mut self) -> _CLRADC14IFG21W {
+        _CLRADC14IFG21W { w: self }
+    }
+    #[doc = "Bit 22 - clear ADC14IFG22"]
+    #[inline]
+    pub fn clradc14ifg22(&mut self) -> _CLRADC14IFG22W {
+        _CLRADC14IFG22W { w: self }
+    }
+    #[doc = "Bit 23 - clear ADC14IFG23"]
+    #[inline]
+    pub fn clradc14ifg23(&mut self) -> _CLRADC14IFG23W {
+        _CLRADC14IFG23W { w: self }
+    }
+    #[doc = "Bit 24 - clear ADC14IFG24"]
+    #[inline]
+    pub fn clradc14ifg24(&mut self) -> _CLRADC14IFG24W {
+        _CLRADC14IFG24W { w: self }
+    }
+    #[doc = "Bit 25 - clear ADC14IFG25"]
+    #[inline]
+    pub fn clradc14ifg25(&mut self) -> _CLRADC14IFG25W {
+        _CLRADC14IFG25W { w: self }
+    }
+    #[doc = "Bit 26 - clear ADC14IFG26"]
+    #[inline]
+    pub fn clradc14ifg26(&mut self) -> _CLRADC14IFG26W {
+        _CLRADC14IFG26W { w: self }
+    }
+    #[doc = "Bit 27 - clear ADC14IFG27"]
+    #[inline]
+    pub fn clradc14ifg27(&mut self) -> _CLRADC14IFG27W {
+        _CLRADC14IFG27W { w: self }
+    }
+    #[doc = "Bit 28 - clear ADC14IFG28"]
+    #[inline]
+    pub fn clradc14ifg28(&mut self) -> _CLRADC14IFG28W {
+        _CLRADC14IFG28W { w: self }
+    }
+    #[doc = "Bit 29 - clear ADC14IFG29"]
+    #[inline]
+    pub fn clradc14ifg29(&mut self) -> _CLRADC14IFG29W {
+        _CLRADC14IFG29W { w: self }
+    }
+    #[doc = "Bit 30 - clear ADC14IFG30"]
+    #[inline]
+    pub fn clradc14ifg30(&mut self) -> _CLRADC14IFG30W {
+        _CLRADC14IFG30W { w: self }
+    }
+    #[doc = "Bit 31 - clear ADC14IFG31"]
+    #[inline]
+    pub fn clradc14ifg31(&mut self) -> _CLRADC14IFG31W {
+        _CLRADC14IFG31W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/adc14/adc14clrifgr1.rs b/example-source/msp432p401r/src/adc14/adc14clrifgr1.rs
new file mode 100644
index 0000000..a683e1d
--- /dev/null
+++ b/example-source/msp432p401r/src/adc14/adc14clrifgr1.rs
@@ -0,0 +1,442 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::ADC14CLRIFGR1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14INIFG`"]
+pub enum CLRADC14INIFGW {
+    #[doc = "no effect"]
+    CLRADC14INIFG_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14INIFG_1,
+}
+impl CLRADC14INIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14INIFGW::CLRADC14INIFG_0 => false,
+            CLRADC14INIFGW::CLRADC14INIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14INIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14INIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14INIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14inifg_0(self) -> &'a mut W {
+        self.variant(CLRADC14INIFGW::CLRADC14INIFG_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14inifg_1(self) -> &'a mut W {
+        self.variant(CLRADC14INIFGW::CLRADC14INIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14LOIFG`"]
+pub enum CLRADC14LOIFGW {
+    #[doc = "no effect"]
+    CLRADC14LOIFG_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14LOIFG_1,
+}
+impl CLRADC14LOIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14LOIFGW::CLRADC14LOIFG_0 => false,
+            CLRADC14LOIFGW::CLRADC14LOIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14LOIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14LOIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14LOIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14loifg_0(self) -> &'a mut W {
+        self.variant(CLRADC14LOIFGW::CLRADC14LOIFG_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14loifg_1(self) -> &'a mut W {
+        self.variant(CLRADC14LOIFGW::CLRADC14LOIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14HIIFG`"]
+pub enum CLRADC14HIIFGW {
+    #[doc = "no effect"]
+    CLRADC14HIIFG_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14HIIFG_1,
+}
+impl CLRADC14HIIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14HIIFGW::CLRADC14HIIFG_0 => false,
+            CLRADC14HIIFGW::CLRADC14HIIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14HIIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14HIIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14HIIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14hiifg_0(self) -> &'a mut W {
+        self.variant(CLRADC14HIIFGW::CLRADC14HIIFG_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14hiifg_1(self) -> &'a mut W {
+        self.variant(CLRADC14HIIFGW::CLRADC14HIIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14OVIFG`"]
+pub enum CLRADC14OVIFGW {
+    #[doc = "no effect"]
+    CLRADC14OVIFG_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14OVIFG_1,
+}
+impl CLRADC14OVIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14OVIFGW::CLRADC14OVIFG_0 => false,
+            CLRADC14OVIFGW::CLRADC14OVIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14OVIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14OVIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14OVIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14ovifg_0(self) -> &'a mut W {
+        self.variant(CLRADC14OVIFGW::CLRADC14OVIFG_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14ovifg_1(self) -> &'a mut W {
+        self.variant(CLRADC14OVIFGW::CLRADC14OVIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14TOVIFG`"]
+pub enum CLRADC14TOVIFGW {
+    #[doc = "no effect"]
+    CLRADC14TOVIFG_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14TOVIFG_1,
+}
+impl CLRADC14TOVIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14TOVIFGW::CLRADC14TOVIFG_0 => false,
+            CLRADC14TOVIFGW::CLRADC14TOVIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14TOVIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14TOVIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14TOVIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14tovifg_0(self) -> &'a mut W {
+        self.variant(CLRADC14TOVIFGW::CLRADC14TOVIFG_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14tovifg_1(self) -> &'a mut W {
+        self.variant(CLRADC14TOVIFGW::CLRADC14TOVIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLRADC14RDYIFG`"]
+pub enum CLRADC14RDYIFGW {
+    #[doc = "no effect"]
+    CLRADC14RDYIFG_0,
+    #[doc = "clear pending interrupt flag"]
+    CLRADC14RDYIFG_1,
+}
+impl CLRADC14RDYIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRADC14RDYIFGW::CLRADC14RDYIFG_0 => false,
+            CLRADC14RDYIFGW::CLRADC14RDYIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRADC14RDYIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRADC14RDYIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRADC14RDYIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "no effect"]
+    #[inline]
+    pub fn clradc14rdyifg_0(self) -> &'a mut W {
+        self.variant(CLRADC14RDYIFGW::CLRADC14RDYIFG_0)
+    }
+    #[doc = "clear pending interrupt flag"]
+    #[inline]
+    pub fn clradc14rdyifg_1(self) -> &'a mut W {
+        self.variant(CLRADC14RDYIFGW::CLRADC14RDYIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 1 - clear ADC14INIFG"]
+    #[inline]
+    pub fn clradc14inifg(&mut self) -> _CLRADC14INIFGW {
+        _CLRADC14INIFGW { w: self }
+    }
+    #[doc = "Bit 2 - clear ADC14LOIFG"]
+    #[inline]
+    pub fn clradc14loifg(&mut self) -> _CLRADC14LOIFGW {
+        _CLRADC14LOIFGW { w: self }
+    }
+    #[doc = "Bit 3 - clear ADC14HIIFG"]
+    #[inline]
+    pub fn clradc14hiifg(&mut self) -> _CLRADC14HIIFGW {
+        _CLRADC14HIIFGW { w: self }
+    }
+    #[doc = "Bit 4 - clear ADC14OVIFG"]
+    #[inline]
+    pub fn clradc14ovifg(&mut self) -> _CLRADC14OVIFGW {
+        _CLRADC14OVIFGW { w: self }
+    }
+    #[doc = "Bit 5 - clear ADC14TOVIFG"]
+    #[inline]
+    pub fn clradc14tovifg(&mut self) -> _CLRADC14TOVIFGW {
+        _CLRADC14TOVIFGW { w: self }
+    }
+    #[doc = "Bit 6 - clear ADC14RDYIFG"]
+    #[inline]
+    pub fn clradc14rdyifg(&mut self) -> _CLRADC14RDYIFGW {
+        _CLRADC14RDYIFGW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/adc14/adc14ctl0.rs b/example-source/msp432p401r/src/adc14/adc14ctl0.rs
new file mode 100644
index 0000000..f4cbf87
--- /dev/null
+++ b/example-source/msp432p401r/src/adc14/adc14ctl0.rs
@@ -0,0 +1,2095 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::ADC14CTL0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `ADC14SC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14SCR {
+    #[doc = "No sample-and-conversion-start"]
+    ADC14SC_0,
+    #[doc = "Start sample-and-conversion"]
+    ADC14SC_1,
+}
+impl ADC14SCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14SCR::ADC14SC_0 => false,
+            ADC14SCR::ADC14SC_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14SCR {
+        match value {
+            false => ADC14SCR::ADC14SC_0,
+            true => ADC14SCR::ADC14SC_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14SC_0`"]
+    #[inline]
+    pub fn is_adc14sc_0(&self) -> bool {
+        *self == ADC14SCR::ADC14SC_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14SC_1`"]
+    #[inline]
+    pub fn is_adc14sc_1(&self) -> bool {
+        *self == ADC14SCR::ADC14SC_1
+    }
+}
+#[doc = "Possible values of the field `ADC14ENC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14ENCR {
+    #[doc = "ADC14 disabled"]
+    ADC14ENC_0,
+    #[doc = "ADC14 enabled"]
+    ADC14ENC_1,
+}
+impl ADC14ENCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14ENCR::ADC14ENC_0 => false,
+            ADC14ENCR::ADC14ENC_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14ENCR {
+        match value {
+            false => ADC14ENCR::ADC14ENC_0,
+            true => ADC14ENCR::ADC14ENC_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14ENC_0`"]
+    #[inline]
+    pub fn is_adc14enc_0(&self) -> bool {
+        *self == ADC14ENCR::ADC14ENC_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14ENC_1`"]
+    #[inline]
+    pub fn is_adc14enc_1(&self) -> bool {
+        *self == ADC14ENCR::ADC14ENC_1
+    }
+}
+#[doc = "Possible values of the field `ADC14ON`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14ONR {
+    #[doc = "ADC14 off"]
+    ADC14ON_0,
+    #[doc = "ADC14 on. ADC core is ready to power up when a valid conversion is triggered."]
+    ADC14ON_1,
+}
+impl ADC14ONR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14ONR::ADC14ON_0 => false,
+            ADC14ONR::ADC14ON_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14ONR {
+        match value {
+            false => ADC14ONR::ADC14ON_0,
+            true => ADC14ONR::ADC14ON_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14ON_0`"]
+    #[inline]
+    pub fn is_adc14on_0(&self) -> bool {
+        *self == ADC14ONR::ADC14ON_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14ON_1`"]
+    #[inline]
+    pub fn is_adc14on_1(&self) -> bool {
+        *self == ADC14ONR::ADC14ON_1
+    }
+}
+#[doc = "Possible values of the field `ADC14MSC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14MSCR {
+    #[doc = "The sampling timer requires a rising edge of the SHI signal to trigger each sample-and-convert"]
+    ADC14MSC_0,
+    #[doc = "The first rising edge of the SHI signal triggers the sampling timer, but further sample-and-conversions are performed automatically as soon as the prior conversion is completed"]
+    ADC14MSC_1,
+}
+impl ADC14MSCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14MSCR::ADC14MSC_0 => false,
+            ADC14MSCR::ADC14MSC_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14MSCR {
+        match value {
+            false => ADC14MSCR::ADC14MSC_0,
+            true => ADC14MSCR::ADC14MSC_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14MSC_0`"]
+    #[inline]
+    pub fn is_adc14msc_0(&self) -> bool {
+        *self == ADC14MSCR::ADC14MSC_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14MSC_1`"]
+    #[inline]
+    pub fn is_adc14msc_1(&self) -> bool {
+        *self == ADC14MSCR::ADC14MSC_1
+    }
+}
+#[doc = "Possible values of the field `ADC14SHT0`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14SHT0R {
+    #[doc = "4"]
+    ADC14SHT0_0,
+    #[doc = "8"]
+    ADC14SHT0_1,
+    #[doc = "16"]
+    ADC14SHT0_2,
+    #[doc = "32"]
+    ADC14SHT0_3,
+    #[doc = "64"]
+    ADC14SHT0_4,
+    #[doc = "96"]
+    ADC14SHT0_5,
+    #[doc = "128"]
+    ADC14SHT0_6,
+    #[doc = "192"]
+    ADC14SHT0_7,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl ADC14SHT0R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            ADC14SHT0R::ADC14SHT0_0 => 0,
+            ADC14SHT0R::ADC14SHT0_1 => 1,
+            ADC14SHT0R::ADC14SHT0_2 => 2,
+            ADC14SHT0R::ADC14SHT0_3 => 3,
+            ADC14SHT0R::ADC14SHT0_4 => 4,
+            ADC14SHT0R::ADC14SHT0_5 => 5,
+            ADC14SHT0R::ADC14SHT0_6 => 6,
+            ADC14SHT0R::ADC14SHT0_7 => 7,
+            ADC14SHT0R::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> ADC14SHT0R {
+        match value {
+            0 => ADC14SHT0R::ADC14SHT0_0,
+            1 => ADC14SHT0R::ADC14SHT0_1,
+            2 => ADC14SHT0R::ADC14SHT0_2,
+            3 => ADC14SHT0R::ADC14SHT0_3,
+            4 => ADC14SHT0R::ADC14SHT0_4,
+            5 => ADC14SHT0R::ADC14SHT0_5,
+            6 => ADC14SHT0R::ADC14SHT0_6,
+            7 => ADC14SHT0R::ADC14SHT0_7,
+            i => ADC14SHT0R::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14SHT0_0`"]
+    #[inline]
+    pub fn is_adc14sht0_0(&self) -> bool {
+        *self == ADC14SHT0R::ADC14SHT0_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14SHT0_1`"]
+    #[inline]
+    pub fn is_adc14sht0_1(&self) -> bool {
+        *self == ADC14SHT0R::ADC14SHT0_1
+    }
+    #[doc = "Checks if the value of the field is `ADC14SHT0_2`"]
+    #[inline]
+    pub fn is_adc14sht0_2(&self) -> bool {
+        *self == ADC14SHT0R::ADC14SHT0_2
+    }
+    #[doc = "Checks if the value of the field is `ADC14SHT0_3`"]
+    #[inline]
+    pub fn is_adc14sht0_3(&self) -> bool {
+        *self == ADC14SHT0R::ADC14SHT0_3
+    }
+    #[doc = "Checks if the value of the field is `ADC14SHT0_4`"]
+    #[inline]
+    pub fn is_adc14sht0_4(&self) -> bool {
+        *self == ADC14SHT0R::ADC14SHT0_4
+    }
+    #[doc = "Checks if the value of the field is `ADC14SHT0_5`"]
+    #[inline]
+    pub fn is_adc14sht0_5(&self) -> bool {
+        *self == ADC14SHT0R::ADC14SHT0_5
+    }
+    #[doc = "Checks if the value of the field is `ADC14SHT0_6`"]
+    #[inline]
+    pub fn is_adc14sht0_6(&self) -> bool {
+        *self == ADC14SHT0R::ADC14SHT0_6
+    }
+    #[doc = "Checks if the value of the field is `ADC14SHT0_7`"]
+    #[inline]
+    pub fn is_adc14sht0_7(&self) -> bool {
+        *self == ADC14SHT0R::ADC14SHT0_7
+    }
+}
+#[doc = "Possible values of the field `ADC14SHT1`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14SHT1R {
+    #[doc = "4"]
+    ADC14SHT1_0,
+    #[doc = "8"]
+    ADC14SHT1_1,
+    #[doc = "16"]
+    ADC14SHT1_2,
+    #[doc = "32"]
+    ADC14SHT1_3,
+    #[doc = "64"]
+    ADC14SHT1_4,
+    #[doc = "96"]
+    ADC14SHT1_5,
+    #[doc = "128"]
+    ADC14SHT1_6,
+    #[doc = "192"]
+    ADC14SHT1_7,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl ADC14SHT1R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            ADC14SHT1R::ADC14SHT1_0 => 0,
+            ADC14SHT1R::ADC14SHT1_1 => 1,
+            ADC14SHT1R::ADC14SHT1_2 => 2,
+            ADC14SHT1R::ADC14SHT1_3 => 3,
+            ADC14SHT1R::ADC14SHT1_4 => 4,
+            ADC14SHT1R::ADC14SHT1_5 => 5,
+            ADC14SHT1R::ADC14SHT1_6 => 6,
+            ADC14SHT1R::ADC14SHT1_7 => 7,
+            ADC14SHT1R::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> ADC14SHT1R {
+        match value {
+            0 => ADC14SHT1R::ADC14SHT1_0,
+            1 => ADC14SHT1R::ADC14SHT1_1,
+            2 => ADC14SHT1R::ADC14SHT1_2,
+            3 => ADC14SHT1R::ADC14SHT1_3,
+            4 => ADC14SHT1R::ADC14SHT1_4,
+            5 => ADC14SHT1R::ADC14SHT1_5,
+            6 => ADC14SHT1R::ADC14SHT1_6,
+            7 => ADC14SHT1R::ADC14SHT1_7,
+            i => ADC14SHT1R::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14SHT1_0`"]
+    #[inline]
+    pub fn is_adc14sht1_0(&self) -> bool {
+        *self == ADC14SHT1R::ADC14SHT1_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14SHT1_1`"]
+    #[inline]
+    pub fn is_adc14sht1_1(&self) -> bool {
+        *self == ADC14SHT1R::ADC14SHT1_1
+    }
+    #[doc = "Checks if the value of the field is `ADC14SHT1_2`"]
+    #[inline]
+    pub fn is_adc14sht1_2(&self) -> bool {
+        *self == ADC14SHT1R::ADC14SHT1_2
+    }
+    #[doc = "Checks if the value of the field is `ADC14SHT1_3`"]
+    #[inline]
+    pub fn is_adc14sht1_3(&self) -> bool {
+        *self == ADC14SHT1R::ADC14SHT1_3
+    }
+    #[doc = "Checks if the value of the field is `ADC14SHT1_4`"]
+    #[inline]
+    pub fn is_adc14sht1_4(&self) -> bool {
+        *self == ADC14SHT1R::ADC14SHT1_4
+    }
+    #[doc = "Checks if the value of the field is `ADC14SHT1_5`"]
+    #[inline]
+    pub fn is_adc14sht1_5(&self) -> bool {
+        *self == ADC14SHT1R::ADC14SHT1_5
+    }
+    #[doc = "Checks if the value of the field is `ADC14SHT1_6`"]
+    #[inline]
+    pub fn is_adc14sht1_6(&self) -> bool {
+        *self == ADC14SHT1R::ADC14SHT1_6
+    }
+    #[doc = "Checks if the value of the field is `ADC14SHT1_7`"]
+    #[inline]
+    pub fn is_adc14sht1_7(&self) -> bool {
+        *self == ADC14SHT1R::ADC14SHT1_7
+    }
+}
+#[doc = "Possible values of the field `ADC14BUSY`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14BUSYR {
+    #[doc = "No operation is active"]
+    ADC14BUSY_0,
+    #[doc = "A sequence, sample, or conversion is active"]
+    ADC14BUSY_1,
+}
+impl ADC14BUSYR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14BUSYR::ADC14BUSY_0 => false,
+            ADC14BUSYR::ADC14BUSY_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14BUSYR {
+        match value {
+            false => ADC14BUSYR::ADC14BUSY_0,
+            true => ADC14BUSYR::ADC14BUSY_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14BUSY_0`"]
+    #[inline]
+    pub fn is_adc14busy_0(&self) -> bool {
+        *self == ADC14BUSYR::ADC14BUSY_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14BUSY_1`"]
+    #[inline]
+    pub fn is_adc14busy_1(&self) -> bool {
+        *self == ADC14BUSYR::ADC14BUSY_1
+    }
+}
+#[doc = "Possible values of the field `ADC14CONSEQ`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14CONSEQR {
+    #[doc = "Single-channel, single-conversion"]
+    ADC14CONSEQ_0,
+    #[doc = "Sequence-of-channels"]
+    ADC14CONSEQ_1,
+    #[doc = "Repeat-single-channel"]
+    ADC14CONSEQ_2,
+    #[doc = "Repeat-sequence-of-channels"]
+    ADC14CONSEQ_3,
+}
+impl ADC14CONSEQR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            ADC14CONSEQR::ADC14CONSEQ_0 => 0,
+            ADC14CONSEQR::ADC14CONSEQ_1 => 1,
+            ADC14CONSEQR::ADC14CONSEQ_2 => 2,
+            ADC14CONSEQR::ADC14CONSEQ_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> ADC14CONSEQR {
+        match value {
+            0 => ADC14CONSEQR::ADC14CONSEQ_0,
+            1 => ADC14CONSEQR::ADC14CONSEQ_1,
+            2 => ADC14CONSEQR::ADC14CONSEQ_2,
+            3 => ADC14CONSEQR::ADC14CONSEQ_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14CONSEQ_0`"]
+    #[inline]
+    pub fn is_adc14conseq_0(&self) -> bool {
+        *self == ADC14CONSEQR::ADC14CONSEQ_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14CONSEQ_1`"]
+    #[inline]
+    pub fn is_adc14conseq_1(&self) -> bool {
+        *self == ADC14CONSEQR::ADC14CONSEQ_1
+    }
+    #[doc = "Checks if the value of the field is `ADC14CONSEQ_2`"]
+    #[inline]
+    pub fn is_adc14conseq_2(&self) -> bool {
+        *self == ADC14CONSEQR::ADC14CONSEQ_2
+    }
+    #[doc = "Checks if the value of the field is `ADC14CONSEQ_3`"]
+    #[inline]
+    pub fn is_adc14conseq_3(&self) -> bool {
+        *self == ADC14CONSEQR::ADC14CONSEQ_3
+    }
+}
+#[doc = "Possible values of the field `ADC14SSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14SSELR {
+    #[doc = "MODCLK"]
+    ADC14SSEL_0,
+    #[doc = "SYSCLK"]
+    ADC14SSEL_1,
+    #[doc = "ACLK"]
+    ADC14SSEL_2,
+    #[doc = "MCLK"]
+    ADC14SSEL_3,
+    #[doc = "SMCLK"]
+    ADC14SSEL_4,
+    #[doc = "HSMCLK"]
+    ADC14SSEL_5,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl ADC14SSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            ADC14SSELR::ADC14SSEL_0 => 0,
+            ADC14SSELR::ADC14SSEL_1 => 1,
+            ADC14SSELR::ADC14SSEL_2 => 2,
+            ADC14SSELR::ADC14SSEL_3 => 3,
+            ADC14SSELR::ADC14SSEL_4 => 4,
+            ADC14SSELR::ADC14SSEL_5 => 5,
+            ADC14SSELR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> ADC14SSELR {
+        match value {
+            0 => ADC14SSELR::ADC14SSEL_0,
+            1 => ADC14SSELR::ADC14SSEL_1,
+            2 => ADC14SSELR::ADC14SSEL_2,
+            3 => ADC14SSELR::ADC14SSEL_3,
+            4 => ADC14SSELR::ADC14SSEL_4,
+            5 => ADC14SSELR::ADC14SSEL_5,
+            i => ADC14SSELR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14SSEL_0`"]
+    #[inline]
+    pub fn is_adc14ssel_0(&self) -> bool {
+        *self == ADC14SSELR::ADC14SSEL_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14SSEL_1`"]
+    #[inline]
+    pub fn is_adc14ssel_1(&self) -> bool {
+        *self == ADC14SSELR::ADC14SSEL_1
+    }
+    #[doc = "Checks if the value of the field is `ADC14SSEL_2`"]
+    #[inline]
+    pub fn is_adc14ssel_2(&self) -> bool {
+        *self == ADC14SSELR::ADC14SSEL_2
+    }
+    #[doc = "Checks if the value of the field is `ADC14SSEL_3`"]
+    #[inline]
+    pub fn is_adc14ssel_3(&self) -> bool {
+        *self == ADC14SSELR::ADC14SSEL_3
+    }
+    #[doc = "Checks if the value of the field is `ADC14SSEL_4`"]
+    #[inline]
+    pub fn is_adc14ssel_4(&self) -> bool {
+        *self == ADC14SSELR::ADC14SSEL_4
+    }
+    #[doc = "Checks if the value of the field is `ADC14SSEL_5`"]
+    #[inline]
+    pub fn is_adc14ssel_5(&self) -> bool {
+        *self == ADC14SSELR::ADC14SSEL_5
+    }
+}
+#[doc = "Possible values of the field `ADC14DIV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14DIVR {
+    #[doc = "/1"]
+    ADC14DIV_0,
+    #[doc = "/2"]
+    ADC14DIV_1,
+    #[doc = "/3"]
+    ADC14DIV_2,
+    #[doc = "/4"]
+    ADC14DIV_3,
+    #[doc = "/5"]
+    ADC14DIV_4,
+    #[doc = "/6"]
+    ADC14DIV_5,
+    #[doc = "/7"]
+    ADC14DIV_6,
+    #[doc = "/8"]
+    ADC14DIV_7,
+}
+impl ADC14DIVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            ADC14DIVR::ADC14DIV_0 => 0,
+            ADC14DIVR::ADC14DIV_1 => 1,
+            ADC14DIVR::ADC14DIV_2 => 2,
+            ADC14DIVR::ADC14DIV_3 => 3,
+            ADC14DIVR::ADC14DIV_4 => 4,
+            ADC14DIVR::ADC14DIV_5 => 5,
+            ADC14DIVR::ADC14DIV_6 => 6,
+            ADC14DIVR::ADC14DIV_7 => 7,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> ADC14DIVR {
+        match value {
+            0 => ADC14DIVR::ADC14DIV_0,
+            1 => ADC14DIVR::ADC14DIV_1,
+            2 => ADC14DIVR::ADC14DIV_2,
+            3 => ADC14DIVR::ADC14DIV_3,
+            4 => ADC14DIVR::ADC14DIV_4,
+            5 => ADC14DIVR::ADC14DIV_5,
+            6 => ADC14DIVR::ADC14DIV_6,
+            7 => ADC14DIVR::ADC14DIV_7,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14DIV_0`"]
+    #[inline]
+    pub fn is_adc14div_0(&self) -> bool {
+        *self == ADC14DIVR::ADC14DIV_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14DIV_1`"]
+    #[inline]
+    pub fn is_adc14div_1(&self) -> bool {
+        *self == ADC14DIVR::ADC14DIV_1
+    }
+    #[doc = "Checks if the value of the field is `ADC14DIV_2`"]
+    #[inline]
+    pub fn is_adc14div_2(&self) -> bool {
+        *self == ADC14DIVR::ADC14DIV_2
+    }
+    #[doc = "Checks if the value of the field is `ADC14DIV_3`"]
+    #[inline]
+    pub fn is_adc14div_3(&self) -> bool {
+        *self == ADC14DIVR::ADC14DIV_3
+    }
+    #[doc = "Checks if the value of the field is `ADC14DIV_4`"]
+    #[inline]
+    pub fn is_adc14div_4(&self) -> bool {
+        *self == ADC14DIVR::ADC14DIV_4
+    }
+    #[doc = "Checks if the value of the field is `ADC14DIV_5`"]
+    #[inline]
+    pub fn is_adc14div_5(&self) -> bool {
+        *self == ADC14DIVR::ADC14DIV_5
+    }
+    #[doc = "Checks if the value of the field is `ADC14DIV_6`"]
+    #[inline]
+    pub fn is_adc14div_6(&self) -> bool {
+        *self == ADC14DIVR::ADC14DIV_6
+    }
+    #[doc = "Checks if the value of the field is `ADC14DIV_7`"]
+    #[inline]
+    pub fn is_adc14div_7(&self) -> bool {
+        *self == ADC14DIVR::ADC14DIV_7
+    }
+}
+#[doc = "Possible values of the field `ADC14ISSH`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14ISSHR {
+    #[doc = "The sample-input signal is not inverted"]
+    ADC14ISSH_0,
+    #[doc = "The sample-input signal is inverted"]
+    ADC14ISSH_1,
+}
+impl ADC14ISSHR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14ISSHR::ADC14ISSH_0 => false,
+            ADC14ISSHR::ADC14ISSH_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14ISSHR {
+        match value {
+            false => ADC14ISSHR::ADC14ISSH_0,
+            true => ADC14ISSHR::ADC14ISSH_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14ISSH_0`"]
+    #[inline]
+    pub fn is_adc14issh_0(&self) -> bool {
+        *self == ADC14ISSHR::ADC14ISSH_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14ISSH_1`"]
+    #[inline]
+    pub fn is_adc14issh_1(&self) -> bool {
+        *self == ADC14ISSHR::ADC14ISSH_1
+    }
+}
+#[doc = "Possible values of the field `ADC14SHP`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14SHPR {
+    #[doc = "SAMPCON signal is sourced from the sample-input signal"]
+    ADC14SHP_0,
+    #[doc = "SAMPCON signal is sourced from the sampling timer"]
+    ADC14SHP_1,
+}
+impl ADC14SHPR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14SHPR::ADC14SHP_0 => false,
+            ADC14SHPR::ADC14SHP_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14SHPR {
+        match value {
+            false => ADC14SHPR::ADC14SHP_0,
+            true => ADC14SHPR::ADC14SHP_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14SHP_0`"]
+    #[inline]
+    pub fn is_adc14shp_0(&self) -> bool {
+        *self == ADC14SHPR::ADC14SHP_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14SHP_1`"]
+    #[inline]
+    pub fn is_adc14shp_1(&self) -> bool {
+        *self == ADC14SHPR::ADC14SHP_1
+    }
+}
+#[doc = "Possible values of the field `ADC14SHS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14SHSR {
+    #[doc = "ADC14SC bit"]
+    ADC14SHS_0,
+    #[doc = "See device-specific data sheet for source"]
+    ADC14SHS_1,
+    #[doc = "See device-specific data sheet for source"]
+    ADC14SHS_2,
+    #[doc = "See device-specific data sheet for source"]
+    ADC14SHS_3,
+    #[doc = "See device-specific data sheet for source"]
+    ADC14SHS_4,
+    #[doc = "See device-specific data sheet for source"]
+    ADC14SHS_5,
+    #[doc = "See device-specific data sheet for source"]
+    ADC14SHS_6,
+    #[doc = "See device-specific data sheet for source"]
+    ADC14SHS_7,
+}
+impl ADC14SHSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            ADC14SHSR::ADC14SHS_0 => 0,
+            ADC14SHSR::ADC14SHS_1 => 1,
+            ADC14SHSR::ADC14SHS_2 => 2,
+            ADC14SHSR::ADC14SHS_3 => 3,
+            ADC14SHSR::ADC14SHS_4 => 4,
+            ADC14SHSR::ADC14SHS_5 => 5,
+            ADC14SHSR::ADC14SHS_6 => 6,
+            ADC14SHSR::ADC14SHS_7 => 7,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> ADC14SHSR {
+        match value {
+            0 => ADC14SHSR::ADC14SHS_0,
+            1 => ADC14SHSR::ADC14SHS_1,
+            2 => ADC14SHSR::ADC14SHS_2,
+            3 => ADC14SHSR::ADC14SHS_3,
+            4 => ADC14SHSR::ADC14SHS_4,
+            5 => ADC14SHSR::ADC14SHS_5,
+            6 => ADC14SHSR::ADC14SHS_6,
+            7 => ADC14SHSR::ADC14SHS_7,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14SHS_0`"]
+    #[inline]
+    pub fn is_adc14shs_0(&self) -> bool {
+        *self == ADC14SHSR::ADC14SHS_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14SHS_1`"]
+    #[inline]
+    pub fn is_adc14shs_1(&self) -> bool {
+        *self == ADC14SHSR::ADC14SHS_1
+    }
+    #[doc = "Checks if the value of the field is `ADC14SHS_2`"]
+    #[inline]
+    pub fn is_adc14shs_2(&self) -> bool {
+        *self == ADC14SHSR::ADC14SHS_2
+    }
+    #[doc = "Checks if the value of the field is `ADC14SHS_3`"]
+    #[inline]
+    pub fn is_adc14shs_3(&self) -> bool {
+        *self == ADC14SHSR::ADC14SHS_3
+    }
+    #[doc = "Checks if the value of the field is `ADC14SHS_4`"]
+    #[inline]
+    pub fn is_adc14shs_4(&self) -> bool {
+        *self == ADC14SHSR::ADC14SHS_4
+    }
+    #[doc = "Checks if the value of the field is `ADC14SHS_5`"]
+    #[inline]
+    pub fn is_adc14shs_5(&self) -> bool {
+        *self == ADC14SHSR::ADC14SHS_5
+    }
+    #[doc = "Checks if the value of the field is `ADC14SHS_6`"]
+    #[inline]
+    pub fn is_adc14shs_6(&self) -> bool {
+        *self == ADC14SHSR::ADC14SHS_6
+    }
+    #[doc = "Checks if the value of the field is `ADC14SHS_7`"]
+    #[inline]
+    pub fn is_adc14shs_7(&self) -> bool {
+        *self == ADC14SHSR::ADC14SHS_7
+    }
+}
+#[doc = "Possible values of the field `ADC14PDIV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14PDIVR {
+    #[doc = "Predivide by 1"]
+    ADC14PDIV_0,
+    #[doc = "Predivide by 4"]
+    ADC14PDIV_1,
+    #[doc = "Predivide by 32"]
+    ADC14PDIV_2,
+    #[doc = "Predivide by 64"]
+    ADC14PDIV_3,
+}
+impl ADC14PDIVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            ADC14PDIVR::ADC14PDIV_0 => 0,
+            ADC14PDIVR::ADC14PDIV_1 => 1,
+            ADC14PDIVR::ADC14PDIV_2 => 2,
+            ADC14PDIVR::ADC14PDIV_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> ADC14PDIVR {
+        match value {
+            0 => ADC14PDIVR::ADC14PDIV_0,
+            1 => ADC14PDIVR::ADC14PDIV_1,
+            2 => ADC14PDIVR::ADC14PDIV_2,
+            3 => ADC14PDIVR::ADC14PDIV_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14PDIV_0`"]
+    #[inline]
+    pub fn is_adc14pdiv_0(&self) -> bool {
+        *self == ADC14PDIVR::ADC14PDIV_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14PDIV_1`"]
+    #[inline]
+    pub fn is_adc14pdiv_1(&self) -> bool {
+        *self == ADC14PDIVR::ADC14PDIV_1
+    }
+    #[doc = "Checks if the value of the field is `ADC14PDIV_2`"]
+    #[inline]
+    pub fn is_adc14pdiv_2(&self) -> bool {
+        *self == ADC14PDIVR::ADC14PDIV_2
+    }
+    #[doc = "Checks if the value of the field is `ADC14PDIV_3`"]
+    #[inline]
+    pub fn is_adc14pdiv_3(&self) -> bool {
+        *self == ADC14PDIVR::ADC14PDIV_3
+    }
+}
+#[doc = "Values that can be written to the field `ADC14SC`"]
+pub enum ADC14SCW {
+    #[doc = "No sample-and-conversion-start"]
+    ADC14SC_0,
+    #[doc = "Start sample-and-conversion"]
+    ADC14SC_1,
+}
+impl ADC14SCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14SCW::ADC14SC_0 => false,
+            ADC14SCW::ADC14SC_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14SCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14SCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14SCW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No sample-and-conversion-start"]
+    #[inline]
+    pub fn adc14sc_0(self) -> &'a mut W {
+        self.variant(ADC14SCW::ADC14SC_0)
+    }
+    #[doc = "Start sample-and-conversion"]
+    #[inline]
+    pub fn adc14sc_1(self) -> &'a mut W {
+        self.variant(ADC14SCW::ADC14SC_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14ENC`"]
+pub enum ADC14ENCW {
+    #[doc = "ADC14 disabled"]
+    ADC14ENC_0,
+    #[doc = "ADC14 enabled"]
+    ADC14ENC_1,
+}
+impl ADC14ENCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14ENCW::ADC14ENC_0 => false,
+            ADC14ENCW::ADC14ENC_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14ENCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14ENCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14ENCW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "ADC14 disabled"]
+    #[inline]
+    pub fn adc14enc_0(self) -> &'a mut W {
+        self.variant(ADC14ENCW::ADC14ENC_0)
+    }
+    #[doc = "ADC14 enabled"]
+    #[inline]
+    pub fn adc14enc_1(self) -> &'a mut W {
+        self.variant(ADC14ENCW::ADC14ENC_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14ON`"]
+pub enum ADC14ONW {
+    #[doc = "ADC14 off"]
+    ADC14ON_0,
+    #[doc = "ADC14 on. ADC core is ready to power up when a valid conversion is triggered."]
+    ADC14ON_1,
+}
+impl ADC14ONW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14ONW::ADC14ON_0 => false,
+            ADC14ONW::ADC14ON_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14ONW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14ONW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14ONW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "ADC14 off"]
+    #[inline]
+    pub fn adc14on_0(self) -> &'a mut W {
+        self.variant(ADC14ONW::ADC14ON_0)
+    }
+    #[doc = "ADC14 on. ADC core is ready to power up when a valid conversion is triggered."]
+    #[inline]
+    pub fn adc14on_1(self) -> &'a mut W {
+        self.variant(ADC14ONW::ADC14ON_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14MSC`"]
+pub enum ADC14MSCW {
+    #[doc = "The sampling timer requires a rising edge of the SHI signal to trigger each sample-and-convert"]
+    ADC14MSC_0,
+    #[doc = "The first rising edge of the SHI signal triggers the sampling timer, but further sample-and-conversions are performed automatically as soon as the prior conversion is completed"]
+    ADC14MSC_1,
+}
+impl ADC14MSCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14MSCW::ADC14MSC_0 => false,
+            ADC14MSCW::ADC14MSC_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14MSCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14MSCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14MSCW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The sampling timer requires a rising edge of the SHI signal to trigger each sample-and-convert"]
+    #[inline]
+    pub fn adc14msc_0(self) -> &'a mut W {
+        self.variant(ADC14MSCW::ADC14MSC_0)
+    }
+    #[doc = "The first rising edge of the SHI signal triggers the sampling timer, but further sample-and-conversions are performed automatically as soon as the prior conversion is completed"]
+    #[inline]
+    pub fn adc14msc_1(self) -> &'a mut W {
+        self.variant(ADC14MSCW::ADC14MSC_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14SHT0`"]
+pub enum ADC14SHT0W {
+    #[doc = "4"]
+    ADC14SHT0_0,
+    #[doc = "8"]
+    ADC14SHT0_1,
+    #[doc = "16"]
+    ADC14SHT0_2,
+    #[doc = "32"]
+    ADC14SHT0_3,
+    #[doc = "64"]
+    ADC14SHT0_4,
+    #[doc = "96"]
+    ADC14SHT0_5,
+    #[doc = "128"]
+    ADC14SHT0_6,
+    #[doc = "192"]
+    ADC14SHT0_7,
+}
+impl ADC14SHT0W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            ADC14SHT0W::ADC14SHT0_0 => 0,
+            ADC14SHT0W::ADC14SHT0_1 => 1,
+            ADC14SHT0W::ADC14SHT0_2 => 2,
+            ADC14SHT0W::ADC14SHT0_3 => 3,
+            ADC14SHT0W::ADC14SHT0_4 => 4,
+            ADC14SHT0W::ADC14SHT0_5 => 5,
+            ADC14SHT0W::ADC14SHT0_6 => 6,
+            ADC14SHT0W::ADC14SHT0_7 => 7,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14SHT0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14SHT0W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14SHT0W) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "4"]
+    #[inline]
+    pub fn adc14sht0_0(self) -> &'a mut W {
+        self.variant(ADC14SHT0W::ADC14SHT0_0)
+    }
+    #[doc = "8"]
+    #[inline]
+    pub fn adc14sht0_1(self) -> &'a mut W {
+        self.variant(ADC14SHT0W::ADC14SHT0_1)
+    }
+    #[doc = "16"]
+    #[inline]
+    pub fn adc14sht0_2(self) -> &'a mut W {
+        self.variant(ADC14SHT0W::ADC14SHT0_2)
+    }
+    #[doc = "32"]
+    #[inline]
+    pub fn adc14sht0_3(self) -> &'a mut W {
+        self.variant(ADC14SHT0W::ADC14SHT0_3)
+    }
+    #[doc = "64"]
+    #[inline]
+    pub fn adc14sht0_4(self) -> &'a mut W {
+        self.variant(ADC14SHT0W::ADC14SHT0_4)
+    }
+    #[doc = "96"]
+    #[inline]
+    pub fn adc14sht0_5(self) -> &'a mut W {
+        self.variant(ADC14SHT0W::ADC14SHT0_5)
+    }
+    #[doc = "128"]
+    #[inline]
+    pub fn adc14sht0_6(self) -> &'a mut W {
+        self.variant(ADC14SHT0W::ADC14SHT0_6)
+    }
+    #[doc = "192"]
+    #[inline]
+    pub fn adc14sht0_7(self) -> &'a mut W {
+        self.variant(ADC14SHT0W::ADC14SHT0_7)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14SHT1`"]
+pub enum ADC14SHT1W {
+    #[doc = "4"]
+    ADC14SHT1_0,
+    #[doc = "8"]
+    ADC14SHT1_1,
+    #[doc = "16"]
+    ADC14SHT1_2,
+    #[doc = "32"]
+    ADC14SHT1_3,
+    #[doc = "64"]
+    ADC14SHT1_4,
+    #[doc = "96"]
+    ADC14SHT1_5,
+    #[doc = "128"]
+    ADC14SHT1_6,
+    #[doc = "192"]
+    ADC14SHT1_7,
+}
+impl ADC14SHT1W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            ADC14SHT1W::ADC14SHT1_0 => 0,
+            ADC14SHT1W::ADC14SHT1_1 => 1,
+            ADC14SHT1W::ADC14SHT1_2 => 2,
+            ADC14SHT1W::ADC14SHT1_3 => 3,
+            ADC14SHT1W::ADC14SHT1_4 => 4,
+            ADC14SHT1W::ADC14SHT1_5 => 5,
+            ADC14SHT1W::ADC14SHT1_6 => 6,
+            ADC14SHT1W::ADC14SHT1_7 => 7,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14SHT1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14SHT1W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14SHT1W) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "4"]
+    #[inline]
+    pub fn adc14sht1_0(self) -> &'a mut W {
+        self.variant(ADC14SHT1W::ADC14SHT1_0)
+    }
+    #[doc = "8"]
+    #[inline]
+    pub fn adc14sht1_1(self) -> &'a mut W {
+        self.variant(ADC14SHT1W::ADC14SHT1_1)
+    }
+    #[doc = "16"]
+    #[inline]
+    pub fn adc14sht1_2(self) -> &'a mut W {
+        self.variant(ADC14SHT1W::ADC14SHT1_2)
+    }
+    #[doc = "32"]
+    #[inline]
+    pub fn adc14sht1_3(self) -> &'a mut W {
+        self.variant(ADC14SHT1W::ADC14SHT1_3)
+    }
+    #[doc = "64"]
+    #[inline]
+    pub fn adc14sht1_4(self) -> &'a mut W {
+        self.variant(ADC14SHT1W::ADC14SHT1_4)
+    }
+    #[doc = "96"]
+    #[inline]
+    pub fn adc14sht1_5(self) -> &'a mut W {
+        self.variant(ADC14SHT1W::ADC14SHT1_5)
+    }
+    #[doc = "128"]
+    #[inline]
+    pub fn adc14sht1_6(self) -> &'a mut W {
+        self.variant(ADC14SHT1W::ADC14SHT1_6)
+    }
+    #[doc = "192"]
+    #[inline]
+    pub fn adc14sht1_7(self) -> &'a mut W {
+        self.variant(ADC14SHT1W::ADC14SHT1_7)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14CONSEQ`"]
+pub enum ADC14CONSEQW {
+    #[doc = "Single-channel, single-conversion"]
+    ADC14CONSEQ_0,
+    #[doc = "Sequence-of-channels"]
+    ADC14CONSEQ_1,
+    #[doc = "Repeat-single-channel"]
+    ADC14CONSEQ_2,
+    #[doc = "Repeat-sequence-of-channels"]
+    ADC14CONSEQ_3,
+}
+impl ADC14CONSEQW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            ADC14CONSEQW::ADC14CONSEQ_0 => 0,
+            ADC14CONSEQW::ADC14CONSEQ_1 => 1,
+            ADC14CONSEQW::ADC14CONSEQ_2 => 2,
+            ADC14CONSEQW::ADC14CONSEQ_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14CONSEQW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14CONSEQW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14CONSEQW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Single-channel, single-conversion"]
+    #[inline]
+    pub fn adc14conseq_0(self) -> &'a mut W {
+        self.variant(ADC14CONSEQW::ADC14CONSEQ_0)
+    }
+    #[doc = "Sequence-of-channels"]
+    #[inline]
+    pub fn adc14conseq_1(self) -> &'a mut W {
+        self.variant(ADC14CONSEQW::ADC14CONSEQ_1)
+    }
+    #[doc = "Repeat-single-channel"]
+    #[inline]
+    pub fn adc14conseq_2(self) -> &'a mut W {
+        self.variant(ADC14CONSEQW::ADC14CONSEQ_2)
+    }
+    #[doc = "Repeat-sequence-of-channels"]
+    #[inline]
+    pub fn adc14conseq_3(self) -> &'a mut W {
+        self.variant(ADC14CONSEQW::ADC14CONSEQ_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 17;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14SSEL`"]
+pub enum ADC14SSELW {
+    #[doc = "MODCLK"]
+    ADC14SSEL_0,
+    #[doc = "SYSCLK"]
+    ADC14SSEL_1,
+    #[doc = "ACLK"]
+    ADC14SSEL_2,
+    #[doc = "MCLK"]
+    ADC14SSEL_3,
+    #[doc = "SMCLK"]
+    ADC14SSEL_4,
+    #[doc = "HSMCLK"]
+    ADC14SSEL_5,
+}
+impl ADC14SSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            ADC14SSELW::ADC14SSEL_0 => 0,
+            ADC14SSELW::ADC14SSEL_1 => 1,
+            ADC14SSELW::ADC14SSEL_2 => 2,
+            ADC14SSELW::ADC14SSEL_3 => 3,
+            ADC14SSELW::ADC14SSEL_4 => 4,
+            ADC14SSELW::ADC14SSEL_5 => 5,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14SSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14SSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14SSELW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "MODCLK"]
+    #[inline]
+    pub fn adc14ssel_0(self) -> &'a mut W {
+        self.variant(ADC14SSELW::ADC14SSEL_0)
+    }
+    #[doc = "SYSCLK"]
+    #[inline]
+    pub fn adc14ssel_1(self) -> &'a mut W {
+        self.variant(ADC14SSELW::ADC14SSEL_1)
+    }
+    #[doc = "ACLK"]
+    #[inline]
+    pub fn adc14ssel_2(self) -> &'a mut W {
+        self.variant(ADC14SSELW::ADC14SSEL_2)
+    }
+    #[doc = "MCLK"]
+    #[inline]
+    pub fn adc14ssel_3(self) -> &'a mut W {
+        self.variant(ADC14SSELW::ADC14SSEL_3)
+    }
+    #[doc = "SMCLK"]
+    #[inline]
+    pub fn adc14ssel_4(self) -> &'a mut W {
+        self.variant(ADC14SSELW::ADC14SSEL_4)
+    }
+    #[doc = "HSMCLK"]
+    #[inline]
+    pub fn adc14ssel_5(self) -> &'a mut W {
+        self.variant(ADC14SSELW::ADC14SSEL_5)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 19;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14DIV`"]
+pub enum ADC14DIVW {
+    #[doc = "/1"]
+    ADC14DIV_0,
+    #[doc = "/2"]
+    ADC14DIV_1,
+    #[doc = "/3"]
+    ADC14DIV_2,
+    #[doc = "/4"]
+    ADC14DIV_3,
+    #[doc = "/5"]
+    ADC14DIV_4,
+    #[doc = "/6"]
+    ADC14DIV_5,
+    #[doc = "/7"]
+    ADC14DIV_6,
+    #[doc = "/8"]
+    ADC14DIV_7,
+}
+impl ADC14DIVW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            ADC14DIVW::ADC14DIV_0 => 0,
+            ADC14DIVW::ADC14DIV_1 => 1,
+            ADC14DIVW::ADC14DIV_2 => 2,
+            ADC14DIVW::ADC14DIV_3 => 3,
+            ADC14DIVW::ADC14DIV_4 => 4,
+            ADC14DIVW::ADC14DIV_5 => 5,
+            ADC14DIVW::ADC14DIV_6 => 6,
+            ADC14DIVW::ADC14DIV_7 => 7,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14DIVW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14DIVW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14DIVW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "/1"]
+    #[inline]
+    pub fn adc14div_0(self) -> &'a mut W {
+        self.variant(ADC14DIVW::ADC14DIV_0)
+    }
+    #[doc = "/2"]
+    #[inline]
+    pub fn adc14div_1(self) -> &'a mut W {
+        self.variant(ADC14DIVW::ADC14DIV_1)
+    }
+    #[doc = "/3"]
+    #[inline]
+    pub fn adc14div_2(self) -> &'a mut W {
+        self.variant(ADC14DIVW::ADC14DIV_2)
+    }
+    #[doc = "/4"]
+    #[inline]
+    pub fn adc14div_3(self) -> &'a mut W {
+        self.variant(ADC14DIVW::ADC14DIV_3)
+    }
+    #[doc = "/5"]
+    #[inline]
+    pub fn adc14div_4(self) -> &'a mut W {
+        self.variant(ADC14DIVW::ADC14DIV_4)
+    }
+    #[doc = "/6"]
+    #[inline]
+    pub fn adc14div_5(self) -> &'a mut W {
+        self.variant(ADC14DIVW::ADC14DIV_5)
+    }
+    #[doc = "/7"]
+    #[inline]
+    pub fn adc14div_6(self) -> &'a mut W {
+        self.variant(ADC14DIVW::ADC14DIV_6)
+    }
+    #[doc = "/8"]
+    #[inline]
+    pub fn adc14div_7(self) -> &'a mut W {
+        self.variant(ADC14DIVW::ADC14DIV_7)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 22;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14ISSH`"]
+pub enum ADC14ISSHW {
+    #[doc = "The sample-input signal is not inverted"]
+    ADC14ISSH_0,
+    #[doc = "The sample-input signal is inverted"]
+    ADC14ISSH_1,
+}
+impl ADC14ISSHW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14ISSHW::ADC14ISSH_0 => false,
+            ADC14ISSHW::ADC14ISSH_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14ISSHW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14ISSHW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14ISSHW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The sample-input signal is not inverted"]
+    #[inline]
+    pub fn adc14issh_0(self) -> &'a mut W {
+        self.variant(ADC14ISSHW::ADC14ISSH_0)
+    }
+    #[doc = "The sample-input signal is inverted"]
+    #[inline]
+    pub fn adc14issh_1(self) -> &'a mut W {
+        self.variant(ADC14ISSHW::ADC14ISSH_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 25;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14SHP`"]
+pub enum ADC14SHPW {
+    #[doc = "SAMPCON signal is sourced from the sample-input signal"]
+    ADC14SHP_0,
+    #[doc = "SAMPCON signal is sourced from the sampling timer"]
+    ADC14SHP_1,
+}
+impl ADC14SHPW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14SHPW::ADC14SHP_0 => false,
+            ADC14SHPW::ADC14SHP_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14SHPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14SHPW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14SHPW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "SAMPCON signal is sourced from the sample-input signal"]
+    #[inline]
+    pub fn adc14shp_0(self) -> &'a mut W {
+        self.variant(ADC14SHPW::ADC14SHP_0)
+    }
+    #[doc = "SAMPCON signal is sourced from the sampling timer"]
+    #[inline]
+    pub fn adc14shp_1(self) -> &'a mut W {
+        self.variant(ADC14SHPW::ADC14SHP_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 26;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14SHS`"]
+pub enum ADC14SHSW {
+    #[doc = "ADC14SC bit"]
+    ADC14SHS_0,
+    #[doc = "See device-specific data sheet for source"]
+    ADC14SHS_1,
+    #[doc = "See device-specific data sheet for source"]
+    ADC14SHS_2,
+    #[doc = "See device-specific data sheet for source"]
+    ADC14SHS_3,
+    #[doc = "See device-specific data sheet for source"]
+    ADC14SHS_4,
+    #[doc = "See device-specific data sheet for source"]
+    ADC14SHS_5,
+    #[doc = "See device-specific data sheet for source"]
+    ADC14SHS_6,
+    #[doc = "See device-specific data sheet for source"]
+    ADC14SHS_7,
+}
+impl ADC14SHSW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            ADC14SHSW::ADC14SHS_0 => 0,
+            ADC14SHSW::ADC14SHS_1 => 1,
+            ADC14SHSW::ADC14SHS_2 => 2,
+            ADC14SHSW::ADC14SHS_3 => 3,
+            ADC14SHSW::ADC14SHS_4 => 4,
+            ADC14SHSW::ADC14SHS_5 => 5,
+            ADC14SHSW::ADC14SHS_6 => 6,
+            ADC14SHSW::ADC14SHS_7 => 7,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14SHSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14SHSW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14SHSW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "ADC14SC bit"]
+    #[inline]
+    pub fn adc14shs_0(self) -> &'a mut W {
+        self.variant(ADC14SHSW::ADC14SHS_0)
+    }
+    #[doc = "See device-specific data sheet for source"]
+    #[inline]
+    pub fn adc14shs_1(self) -> &'a mut W {
+        self.variant(ADC14SHSW::ADC14SHS_1)
+    }
+    #[doc = "See device-specific data sheet for source"]
+    #[inline]
+    pub fn adc14shs_2(self) -> &'a mut W {
+        self.variant(ADC14SHSW::ADC14SHS_2)
+    }
+    #[doc = "See device-specific data sheet for source"]
+    #[inline]
+    pub fn adc14shs_3(self) -> &'a mut W {
+        self.variant(ADC14SHSW::ADC14SHS_3)
+    }
+    #[doc = "See device-specific data sheet for source"]
+    #[inline]
+    pub fn adc14shs_4(self) -> &'a mut W {
+        self.variant(ADC14SHSW::ADC14SHS_4)
+    }
+    #[doc = "See device-specific data sheet for source"]
+    #[inline]
+    pub fn adc14shs_5(self) -> &'a mut W {
+        self.variant(ADC14SHSW::ADC14SHS_5)
+    }
+    #[doc = "See device-specific data sheet for source"]
+    #[inline]
+    pub fn adc14shs_6(self) -> &'a mut W {
+        self.variant(ADC14SHSW::ADC14SHS_6)
+    }
+    #[doc = "See device-specific data sheet for source"]
+    #[inline]
+    pub fn adc14shs_7(self) -> &'a mut W {
+        self.variant(ADC14SHSW::ADC14SHS_7)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 27;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14PDIV`"]
+pub enum ADC14PDIVW {
+    #[doc = "Predivide by 1"]
+    ADC14PDIV_0,
+    #[doc = "Predivide by 4"]
+    ADC14PDIV_1,
+    #[doc = "Predivide by 32"]
+    ADC14PDIV_2,
+    #[doc = "Predivide by 64"]
+    ADC14PDIV_3,
+}
+impl ADC14PDIVW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            ADC14PDIVW::ADC14PDIV_0 => 0,
+            ADC14PDIVW::ADC14PDIV_1 => 1,
+            ADC14PDIVW::ADC14PDIV_2 => 2,
+            ADC14PDIVW::ADC14PDIV_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14PDIVW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14PDIVW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14PDIVW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Predivide by 1"]
+    #[inline]
+    pub fn adc14pdiv_0(self) -> &'a mut W {
+        self.variant(ADC14PDIVW::ADC14PDIV_0)
+    }
+    #[doc = "Predivide by 4"]
+    #[inline]
+    pub fn adc14pdiv_1(self) -> &'a mut W {
+        self.variant(ADC14PDIVW::ADC14PDIV_1)
+    }
+    #[doc = "Predivide by 32"]
+    #[inline]
+    pub fn adc14pdiv_2(self) -> &'a mut W {
+        self.variant(ADC14PDIVW::ADC14PDIV_2)
+    }
+    #[doc = "Predivide by 64"]
+    #[inline]
+    pub fn adc14pdiv_3(self) -> &'a mut W {
+        self.variant(ADC14PDIVW::ADC14PDIV_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 30;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - ADC14 start conversion"]
+    #[inline]
+    pub fn adc14sc(&self) -> ADC14SCR {
+        ADC14SCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - ADC14 enable conversion"]
+    #[inline]
+    pub fn adc14enc(&self) -> ADC14ENCR {
+        ADC14ENCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 4 - ADC14 on"]
+    #[inline]
+    pub fn adc14on(&self) -> ADC14ONR {
+        ADC14ONR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 7 - ADC14 multiple sample and conversion"]
+    #[inline]
+    pub fn adc14msc(&self) -> ADC14MSCR {
+        ADC14MSCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 8:11 - ADC14 sample-and-hold time"]
+    #[inline]
+    pub fn adc14sht0(&self) -> ADC14SHT0R {
+        ADC14SHT0R::_from({
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 12:15 - ADC14 sample-and-hold time"]
+    #[inline]
+    pub fn adc14sht1(&self) -> ADC14SHT1R {
+        ADC14SHT1R::_from({
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 16 - ADC14 busy"]
+    #[inline]
+    pub fn adc14busy(&self) -> ADC14BUSYR {
+        ADC14BUSYR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 17:18 - ADC14 conversion sequence mode select"]
+    #[inline]
+    pub fn adc14conseq(&self) -> ADC14CONSEQR {
+        ADC14CONSEQR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 17;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 19:21 - ADC14 clock source select"]
+    #[inline]
+    pub fn adc14ssel(&self) -> ADC14SSELR {
+        ADC14SSELR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 19;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 22:24 - ADC14 clock divider"]
+    #[inline]
+    pub fn adc14div(&self) -> ADC14DIVR {
+        ADC14DIVR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 22;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 25 - ADC14 invert signal sample-and-hold"]
+    #[inline]
+    pub fn adc14issh(&self) -> ADC14ISSHR {
+        ADC14ISSHR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 25;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 26 - ADC14 sample-and-hold pulse-mode select"]
+    #[inline]
+    pub fn adc14shp(&self) -> ADC14SHPR {
+        ADC14SHPR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 26;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 27:29 - ADC14 sample-and-hold source select"]
+    #[inline]
+    pub fn adc14shs(&self) -> ADC14SHSR {
+        ADC14SHSR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 27;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 30:31 - ADC14 predivider"]
+    #[inline]
+    pub fn adc14pdiv(&self) -> ADC14PDIVR {
+        ADC14PDIVR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 30;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - ADC14 start conversion"]
+    #[inline]
+    pub fn adc14sc(&mut self) -> _ADC14SCW {
+        _ADC14SCW { w: self }
+    }
+    #[doc = "Bit 1 - ADC14 enable conversion"]
+    #[inline]
+    pub fn adc14enc(&mut self) -> _ADC14ENCW {
+        _ADC14ENCW { w: self }
+    }
+    #[doc = "Bit 4 - ADC14 on"]
+    #[inline]
+    pub fn adc14on(&mut self) -> _ADC14ONW {
+        _ADC14ONW { w: self }
+    }
+    #[doc = "Bit 7 - ADC14 multiple sample and conversion"]
+    #[inline]
+    pub fn adc14msc(&mut self) -> _ADC14MSCW {
+        _ADC14MSCW { w: self }
+    }
+    #[doc = "Bits 8:11 - ADC14 sample-and-hold time"]
+    #[inline]
+    pub fn adc14sht0(&mut self) -> _ADC14SHT0W {
+        _ADC14SHT0W { w: self }
+    }
+    #[doc = "Bits 12:15 - ADC14 sample-and-hold time"]
+    #[inline]
+    pub fn adc14sht1(&mut self) -> _ADC14SHT1W {
+        _ADC14SHT1W { w: self }
+    }
+    #[doc = "Bits 17:18 - ADC14 conversion sequence mode select"]
+    #[inline]
+    pub fn adc14conseq(&mut self) -> _ADC14CONSEQW {
+        _ADC14CONSEQW { w: self }
+    }
+    #[doc = "Bits 19:21 - ADC14 clock source select"]
+    #[inline]
+    pub fn adc14ssel(&mut self) -> _ADC14SSELW {
+        _ADC14SSELW { w: self }
+    }
+    #[doc = "Bits 22:24 - ADC14 clock divider"]
+    #[inline]
+    pub fn adc14div(&mut self) -> _ADC14DIVW {
+        _ADC14DIVW { w: self }
+    }
+    #[doc = "Bit 25 - ADC14 invert signal sample-and-hold"]
+    #[inline]
+    pub fn adc14issh(&mut self) -> _ADC14ISSHW {
+        _ADC14ISSHW { w: self }
+    }
+    #[doc = "Bit 26 - ADC14 sample-and-hold pulse-mode select"]
+    #[inline]
+    pub fn adc14shp(&mut self) -> _ADC14SHPW {
+        _ADC14SHPW { w: self }
+    }
+    #[doc = "Bits 27:29 - ADC14 sample-and-hold source select"]
+    #[inline]
+    pub fn adc14shs(&mut self) -> _ADC14SHSW {
+        _ADC14SHSW { w: self }
+    }
+    #[doc = "Bits 30:31 - ADC14 predivider"]
+    #[inline]
+    pub fn adc14pdiv(&mut self) -> _ADC14PDIVW {
+        _ADC14PDIVW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/adc14/adc14ctl1.rs b/example-source/msp432p401r/src/adc14/adc14ctl1.rs
new file mode 100644
index 0000000..56cef37
--- /dev/null
+++ b/example-source/msp432p401r/src/adc14/adc14ctl1.rs
@@ -0,0 +1,1296 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::ADC14CTL1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `ADC14PWRMD`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14PWRMDR {
+    #[doc = "Regular power mode for use with any resolution setting. Sample rate can be up to 1 Msps."]
+    ADC14PWRMD_0,
+    #[doc = "Low-power mode for 12-bit, 10-bit, and 8-bit resolution settings. Sample rate must not exceed 200 ksps."]
+    ADC14PWRMD_2,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl ADC14PWRMDR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            ADC14PWRMDR::ADC14PWRMD_0 => 0,
+            ADC14PWRMDR::ADC14PWRMD_2 => 2,
+            ADC14PWRMDR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> ADC14PWRMDR {
+        match value {
+            0 => ADC14PWRMDR::ADC14PWRMD_0,
+            2 => ADC14PWRMDR::ADC14PWRMD_2,
+            i => ADC14PWRMDR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14PWRMD_0`"]
+    #[inline]
+    pub fn is_adc14pwrmd_0(&self) -> bool {
+        *self == ADC14PWRMDR::ADC14PWRMD_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14PWRMD_2`"]
+    #[inline]
+    pub fn is_adc14pwrmd_2(&self) -> bool {
+        *self == ADC14PWRMDR::ADC14PWRMD_2
+    }
+}
+#[doc = "Possible values of the field `ADC14REFBURST`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14REFBURSTR {
+    #[doc = "ADC reference buffer on continuously"]
+    ADC14REFBURST_0,
+    #[doc = "ADC reference buffer on only during sample-and-conversion"]
+    ADC14REFBURST_1,
+}
+impl ADC14REFBURSTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14REFBURSTR::ADC14REFBURST_0 => false,
+            ADC14REFBURSTR::ADC14REFBURST_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14REFBURSTR {
+        match value {
+            false => ADC14REFBURSTR::ADC14REFBURST_0,
+            true => ADC14REFBURSTR::ADC14REFBURST_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14REFBURST_0`"]
+    #[inline]
+    pub fn is_adc14refburst_0(&self) -> bool {
+        *self == ADC14REFBURSTR::ADC14REFBURST_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14REFBURST_1`"]
+    #[inline]
+    pub fn is_adc14refburst_1(&self) -> bool {
+        *self == ADC14REFBURSTR::ADC14REFBURST_1
+    }
+}
+#[doc = "Possible values of the field `ADC14DF`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14DFR {
+    #[doc = "Binary unsigned. Theoretically, for ADC14DIF = 0 and 14-bit mode, the analog input voltage - V(REF) results in 0000h, and the analog input voltage + V(REF) results in 3FFFh"]
+    ADC14DF_0,
+    #[doc = "Signed binary (2s complement), left aligned. Theoretically, for ADC14DIF = 0 and 14-bit mode, the analog input voltage - V(REF) results in 8000h, and the analog input voltage + V(REF) results in 7FFCh"]
+    ADC14DF_1,
+}
+impl ADC14DFR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14DFR::ADC14DF_0 => false,
+            ADC14DFR::ADC14DF_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14DFR {
+        match value {
+            false => ADC14DFR::ADC14DF_0,
+            true => ADC14DFR::ADC14DF_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14DF_0`"]
+    #[inline]
+    pub fn is_adc14df_0(&self) -> bool {
+        *self == ADC14DFR::ADC14DF_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14DF_1`"]
+    #[inline]
+    pub fn is_adc14df_1(&self) -> bool {
+        *self == ADC14DFR::ADC14DF_1
+    }
+}
+#[doc = "Possible values of the field `ADC14RES`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14RESR {
+    #[doc = "8 bit (9 clock cycle conversion time)"]
+    ADC14RES_0,
+    #[doc = "10 bit (11 clock cycle conversion time)"]
+    ADC14RES_1,
+    #[doc = "12 bit (14 clock cycle conversion time)"]
+    ADC14RES_2,
+    #[doc = "14 bit (16 clock cycle conversion time)"]
+    ADC14RES_3,
+}
+impl ADC14RESR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            ADC14RESR::ADC14RES_0 => 0,
+            ADC14RESR::ADC14RES_1 => 1,
+            ADC14RESR::ADC14RES_2 => 2,
+            ADC14RESR::ADC14RES_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> ADC14RESR {
+        match value {
+            0 => ADC14RESR::ADC14RES_0,
+            1 => ADC14RESR::ADC14RES_1,
+            2 => ADC14RESR::ADC14RES_2,
+            3 => ADC14RESR::ADC14RES_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14RES_0`"]
+    #[inline]
+    pub fn is_adc14res_0(&self) -> bool {
+        *self == ADC14RESR::ADC14RES_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14RES_1`"]
+    #[inline]
+    pub fn is_adc14res_1(&self) -> bool {
+        *self == ADC14RESR::ADC14RES_1
+    }
+    #[doc = "Checks if the value of the field is `ADC14RES_2`"]
+    #[inline]
+    pub fn is_adc14res_2(&self) -> bool {
+        *self == ADC14RESR::ADC14RES_2
+    }
+    #[doc = "Checks if the value of the field is `ADC14RES_3`"]
+    #[inline]
+    pub fn is_adc14res_3(&self) -> bool {
+        *self == ADC14RESR::ADC14RES_3
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ADC14CSTARTADDR {
+    bits: u8,
+}
+impl ADC14CSTARTADDR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `ADC14BATMAP`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14BATMAPR {
+    #[doc = "ADC internal 1/2 x AVCC channel is not selected for ADC"]
+    ADC14BATMAP_0,
+    #[doc = "ADC internal 1/2 x AVCC channel is selected for ADC input channel MAX"]
+    ADC14BATMAP_1,
+}
+impl ADC14BATMAPR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14BATMAPR::ADC14BATMAP_0 => false,
+            ADC14BATMAPR::ADC14BATMAP_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14BATMAPR {
+        match value {
+            false => ADC14BATMAPR::ADC14BATMAP_0,
+            true => ADC14BATMAPR::ADC14BATMAP_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14BATMAP_0`"]
+    #[inline]
+    pub fn is_adc14batmap_0(&self) -> bool {
+        *self == ADC14BATMAPR::ADC14BATMAP_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14BATMAP_1`"]
+    #[inline]
+    pub fn is_adc14batmap_1(&self) -> bool {
+        *self == ADC14BATMAPR::ADC14BATMAP_1
+    }
+}
+#[doc = "Possible values of the field `ADC14TCMAP`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14TCMAPR {
+    #[doc = "ADC internal temperature sensor channel is not selected for ADC"]
+    ADC14TCMAP_0,
+    #[doc = "ADC internal temperature sensor channel is selected for ADC input channel MAX-1"]
+    ADC14TCMAP_1,
+}
+impl ADC14TCMAPR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14TCMAPR::ADC14TCMAP_0 => false,
+            ADC14TCMAPR::ADC14TCMAP_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14TCMAPR {
+        match value {
+            false => ADC14TCMAPR::ADC14TCMAP_0,
+            true => ADC14TCMAPR::ADC14TCMAP_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14TCMAP_0`"]
+    #[inline]
+    pub fn is_adc14tcmap_0(&self) -> bool {
+        *self == ADC14TCMAPR::ADC14TCMAP_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14TCMAP_1`"]
+    #[inline]
+    pub fn is_adc14tcmap_1(&self) -> bool {
+        *self == ADC14TCMAPR::ADC14TCMAP_1
+    }
+}
+#[doc = "Possible values of the field `ADC14CH0MAP`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14CH0MAPR {
+    #[doc = "ADC input channel internal 0 is not selected"]
+    ADC14CH0MAP_0,
+    #[doc = "ADC input channel internal 0 is selected for ADC input channel MAX-2"]
+    ADC14CH0MAP_1,
+}
+impl ADC14CH0MAPR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14CH0MAPR::ADC14CH0MAP_0 => false,
+            ADC14CH0MAPR::ADC14CH0MAP_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14CH0MAPR {
+        match value {
+            false => ADC14CH0MAPR::ADC14CH0MAP_0,
+            true => ADC14CH0MAPR::ADC14CH0MAP_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14CH0MAP_0`"]
+    #[inline]
+    pub fn is_adc14ch0map_0(&self) -> bool {
+        *self == ADC14CH0MAPR::ADC14CH0MAP_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14CH0MAP_1`"]
+    #[inline]
+    pub fn is_adc14ch0map_1(&self) -> bool {
+        *self == ADC14CH0MAPR::ADC14CH0MAP_1
+    }
+}
+#[doc = "Possible values of the field `ADC14CH1MAP`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14CH1MAPR {
+    #[doc = "ADC input channel internal 1 is not selected"]
+    ADC14CH1MAP_0,
+    #[doc = "ADC input channel internal 1 is selected for ADC input channel MAX-3"]
+    ADC14CH1MAP_1,
+}
+impl ADC14CH1MAPR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14CH1MAPR::ADC14CH1MAP_0 => false,
+            ADC14CH1MAPR::ADC14CH1MAP_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14CH1MAPR {
+        match value {
+            false => ADC14CH1MAPR::ADC14CH1MAP_0,
+            true => ADC14CH1MAPR::ADC14CH1MAP_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14CH1MAP_0`"]
+    #[inline]
+    pub fn is_adc14ch1map_0(&self) -> bool {
+        *self == ADC14CH1MAPR::ADC14CH1MAP_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14CH1MAP_1`"]
+    #[inline]
+    pub fn is_adc14ch1map_1(&self) -> bool {
+        *self == ADC14CH1MAPR::ADC14CH1MAP_1
+    }
+}
+#[doc = "Possible values of the field `ADC14CH2MAP`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14CH2MAPR {
+    #[doc = "ADC input channel internal 2 is not selected"]
+    ADC14CH2MAP_0,
+    #[doc = "ADC input channel internal 2 is selected for ADC input channel MAX-4"]
+    ADC14CH2MAP_1,
+}
+impl ADC14CH2MAPR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14CH2MAPR::ADC14CH2MAP_0 => false,
+            ADC14CH2MAPR::ADC14CH2MAP_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14CH2MAPR {
+        match value {
+            false => ADC14CH2MAPR::ADC14CH2MAP_0,
+            true => ADC14CH2MAPR::ADC14CH2MAP_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14CH2MAP_0`"]
+    #[inline]
+    pub fn is_adc14ch2map_0(&self) -> bool {
+        *self == ADC14CH2MAPR::ADC14CH2MAP_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14CH2MAP_1`"]
+    #[inline]
+    pub fn is_adc14ch2map_1(&self) -> bool {
+        *self == ADC14CH2MAPR::ADC14CH2MAP_1
+    }
+}
+#[doc = "Possible values of the field `ADC14CH3MAP`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14CH3MAPR {
+    #[doc = "ADC input channel internal 3 is not selected"]
+    ADC14CH3MAP_0,
+    #[doc = "ADC input channel internal 3 is selected for ADC input channel MAX-5"]
+    ADC14CH3MAP_1,
+}
+impl ADC14CH3MAPR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14CH3MAPR::ADC14CH3MAP_0 => false,
+            ADC14CH3MAPR::ADC14CH3MAP_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14CH3MAPR {
+        match value {
+            false => ADC14CH3MAPR::ADC14CH3MAP_0,
+            true => ADC14CH3MAPR::ADC14CH3MAP_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14CH3MAP_0`"]
+    #[inline]
+    pub fn is_adc14ch3map_0(&self) -> bool {
+        *self == ADC14CH3MAPR::ADC14CH3MAP_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14CH3MAP_1`"]
+    #[inline]
+    pub fn is_adc14ch3map_1(&self) -> bool {
+        *self == ADC14CH3MAPR::ADC14CH3MAP_1
+    }
+}
+#[doc = "Values that can be written to the field `ADC14PWRMD`"]
+pub enum ADC14PWRMDW {
+    #[doc = "Regular power mode for use with any resolution setting. Sample rate can be up to 1 Msps."]
+    ADC14PWRMD_0,
+    #[doc = "Low-power mode for 12-bit, 10-bit, and 8-bit resolution settings. Sample rate must not exceed 200 ksps."]
+    ADC14PWRMD_2,
+}
+impl ADC14PWRMDW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            ADC14PWRMDW::ADC14PWRMD_0 => 0,
+            ADC14PWRMDW::ADC14PWRMD_2 => 2,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14PWRMDW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14PWRMDW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14PWRMDW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "Regular power mode for use with any resolution setting. Sample rate can be up to 1 Msps."]
+    #[inline]
+    pub fn adc14pwrmd_0(self) -> &'a mut W {
+        self.variant(ADC14PWRMDW::ADC14PWRMD_0)
+    }
+    #[doc = "Low-power mode for 12-bit, 10-bit, and 8-bit resolution settings. Sample rate must not exceed 200 ksps."]
+    #[inline]
+    pub fn adc14pwrmd_2(self) -> &'a mut W {
+        self.variant(ADC14PWRMDW::ADC14PWRMD_2)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14REFBURST`"]
+pub enum ADC14REFBURSTW {
+    #[doc = "ADC reference buffer on continuously"]
+    ADC14REFBURST_0,
+    #[doc = "ADC reference buffer on only during sample-and-conversion"]
+    ADC14REFBURST_1,
+}
+impl ADC14REFBURSTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14REFBURSTW::ADC14REFBURST_0 => false,
+            ADC14REFBURSTW::ADC14REFBURST_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14REFBURSTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14REFBURSTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14REFBURSTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "ADC reference buffer on continuously"]
+    #[inline]
+    pub fn adc14refburst_0(self) -> &'a mut W {
+        self.variant(ADC14REFBURSTW::ADC14REFBURST_0)
+    }
+    #[doc = "ADC reference buffer on only during sample-and-conversion"]
+    #[inline]
+    pub fn adc14refburst_1(self) -> &'a mut W {
+        self.variant(ADC14REFBURSTW::ADC14REFBURST_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14DF`"]
+pub enum ADC14DFW {
+    #[doc = "Binary unsigned. Theoretically, for ADC14DIF = 0 and 14-bit mode, the analog input voltage - V(REF) results in 0000h, and the analog input voltage + V(REF) results in 3FFFh"]
+    ADC14DF_0,
+    #[doc = "Signed binary (2s complement), left aligned. Theoretically, for ADC14DIF = 0 and 14-bit mode, the analog input voltage - V(REF) results in 8000h, and the analog input voltage + V(REF) results in 7FFCh"]
+    ADC14DF_1,
+}
+impl ADC14DFW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14DFW::ADC14DF_0 => false,
+            ADC14DFW::ADC14DF_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14DFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14DFW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14DFW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Binary unsigned. Theoretically, for ADC14DIF = 0 and 14-bit mode, the analog input voltage - V(REF) results in 0000h, and the analog input voltage + V(REF) results in 3FFFh"]
+    #[inline]
+    pub fn adc14df_0(self) -> &'a mut W {
+        self.variant(ADC14DFW::ADC14DF_0)
+    }
+    #[doc = "Signed binary (2s complement), left aligned. Theoretically, for ADC14DIF = 0 and 14-bit mode, the analog input voltage - V(REF) results in 8000h, and the analog input voltage + V(REF) results in 7FFCh"]
+    #[inline]
+    pub fn adc14df_1(self) -> &'a mut W {
+        self.variant(ADC14DFW::ADC14DF_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14RES`"]
+pub enum ADC14RESW {
+    #[doc = "8 bit (9 clock cycle conversion time)"]
+    ADC14RES_0,
+    #[doc = "10 bit (11 clock cycle conversion time)"]
+    ADC14RES_1,
+    #[doc = "12 bit (14 clock cycle conversion time)"]
+    ADC14RES_2,
+    #[doc = "14 bit (16 clock cycle conversion time)"]
+    ADC14RES_3,
+}
+impl ADC14RESW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            ADC14RESW::ADC14RES_0 => 0,
+            ADC14RESW::ADC14RES_1 => 1,
+            ADC14RESW::ADC14RES_2 => 2,
+            ADC14RESW::ADC14RES_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14RESW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14RESW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14RESW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "8 bit (9 clock cycle conversion time)"]
+    #[inline]
+    pub fn adc14res_0(self) -> &'a mut W {
+        self.variant(ADC14RESW::ADC14RES_0)
+    }
+    #[doc = "10 bit (11 clock cycle conversion time)"]
+    #[inline]
+    pub fn adc14res_1(self) -> &'a mut W {
+        self.variant(ADC14RESW::ADC14RES_1)
+    }
+    #[doc = "12 bit (14 clock cycle conversion time)"]
+    #[inline]
+    pub fn adc14res_2(self) -> &'a mut W {
+        self.variant(ADC14RESW::ADC14RES_2)
+    }
+    #[doc = "14 bit (16 clock cycle conversion time)"]
+    #[inline]
+    pub fn adc14res_3(self) -> &'a mut W {
+        self.variant(ADC14RESW::ADC14RES_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14CSTARTADDW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14CSTARTADDW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 31;
+        const OFFSET: u8 = 16;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14BATMAP`"]
+pub enum ADC14BATMAPW {
+    #[doc = "ADC internal 1/2 x AVCC channel is not selected for ADC"]
+    ADC14BATMAP_0,
+    #[doc = "ADC internal 1/2 x AVCC channel is selected for ADC input channel MAX"]
+    ADC14BATMAP_1,
+}
+impl ADC14BATMAPW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14BATMAPW::ADC14BATMAP_0 => false,
+            ADC14BATMAPW::ADC14BATMAP_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14BATMAPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14BATMAPW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14BATMAPW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "ADC internal 1/2 x AVCC channel is not selected for ADC"]
+    #[inline]
+    pub fn adc14batmap_0(self) -> &'a mut W {
+        self.variant(ADC14BATMAPW::ADC14BATMAP_0)
+    }
+    #[doc = "ADC internal 1/2 x AVCC channel is selected for ADC input channel MAX"]
+    #[inline]
+    pub fn adc14batmap_1(self) -> &'a mut W {
+        self.variant(ADC14BATMAPW::ADC14BATMAP_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 22;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14TCMAP`"]
+pub enum ADC14TCMAPW {
+    #[doc = "ADC internal temperature sensor channel is not selected for ADC"]
+    ADC14TCMAP_0,
+    #[doc = "ADC internal temperature sensor channel is selected for ADC input channel MAX-1"]
+    ADC14TCMAP_1,
+}
+impl ADC14TCMAPW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14TCMAPW::ADC14TCMAP_0 => false,
+            ADC14TCMAPW::ADC14TCMAP_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14TCMAPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14TCMAPW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14TCMAPW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "ADC internal temperature sensor channel is not selected for ADC"]
+    #[inline]
+    pub fn adc14tcmap_0(self) -> &'a mut W {
+        self.variant(ADC14TCMAPW::ADC14TCMAP_0)
+    }
+    #[doc = "ADC internal temperature sensor channel is selected for ADC input channel MAX-1"]
+    #[inline]
+    pub fn adc14tcmap_1(self) -> &'a mut W {
+        self.variant(ADC14TCMAPW::ADC14TCMAP_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 23;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14CH0MAP`"]
+pub enum ADC14CH0MAPW {
+    #[doc = "ADC input channel internal 0 is not selected"]
+    ADC14CH0MAP_0,
+    #[doc = "ADC input channel internal 0 is selected for ADC input channel MAX-2"]
+    ADC14CH0MAP_1,
+}
+impl ADC14CH0MAPW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14CH0MAPW::ADC14CH0MAP_0 => false,
+            ADC14CH0MAPW::ADC14CH0MAP_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14CH0MAPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14CH0MAPW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14CH0MAPW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "ADC input channel internal 0 is not selected"]
+    #[inline]
+    pub fn adc14ch0map_0(self) -> &'a mut W {
+        self.variant(ADC14CH0MAPW::ADC14CH0MAP_0)
+    }
+    #[doc = "ADC input channel internal 0 is selected for ADC input channel MAX-2"]
+    #[inline]
+    pub fn adc14ch0map_1(self) -> &'a mut W {
+        self.variant(ADC14CH0MAPW::ADC14CH0MAP_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 24;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14CH1MAP`"]
+pub enum ADC14CH1MAPW {
+    #[doc = "ADC input channel internal 1 is not selected"]
+    ADC14CH1MAP_0,
+    #[doc = "ADC input channel internal 1 is selected for ADC input channel MAX-3"]
+    ADC14CH1MAP_1,
+}
+impl ADC14CH1MAPW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14CH1MAPW::ADC14CH1MAP_0 => false,
+            ADC14CH1MAPW::ADC14CH1MAP_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14CH1MAPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14CH1MAPW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14CH1MAPW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "ADC input channel internal 1 is not selected"]
+    #[inline]
+    pub fn adc14ch1map_0(self) -> &'a mut W {
+        self.variant(ADC14CH1MAPW::ADC14CH1MAP_0)
+    }
+    #[doc = "ADC input channel internal 1 is selected for ADC input channel MAX-3"]
+    #[inline]
+    pub fn adc14ch1map_1(self) -> &'a mut W {
+        self.variant(ADC14CH1MAPW::ADC14CH1MAP_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 25;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14CH2MAP`"]
+pub enum ADC14CH2MAPW {
+    #[doc = "ADC input channel internal 2 is not selected"]
+    ADC14CH2MAP_0,
+    #[doc = "ADC input channel internal 2 is selected for ADC input channel MAX-4"]
+    ADC14CH2MAP_1,
+}
+impl ADC14CH2MAPW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14CH2MAPW::ADC14CH2MAP_0 => false,
+            ADC14CH2MAPW::ADC14CH2MAP_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14CH2MAPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14CH2MAPW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14CH2MAPW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "ADC input channel internal 2 is not selected"]
+    #[inline]
+    pub fn adc14ch2map_0(self) -> &'a mut W {
+        self.variant(ADC14CH2MAPW::ADC14CH2MAP_0)
+    }
+    #[doc = "ADC input channel internal 2 is selected for ADC input channel MAX-4"]
+    #[inline]
+    pub fn adc14ch2map_1(self) -> &'a mut W {
+        self.variant(ADC14CH2MAPW::ADC14CH2MAP_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 26;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14CH3MAP`"]
+pub enum ADC14CH3MAPW {
+    #[doc = "ADC input channel internal 3 is not selected"]
+    ADC14CH3MAP_0,
+    #[doc = "ADC input channel internal 3 is selected for ADC input channel MAX-5"]
+    ADC14CH3MAP_1,
+}
+impl ADC14CH3MAPW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14CH3MAPW::ADC14CH3MAP_0 => false,
+            ADC14CH3MAPW::ADC14CH3MAP_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14CH3MAPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14CH3MAPW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14CH3MAPW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "ADC input channel internal 3 is not selected"]
+    #[inline]
+    pub fn adc14ch3map_0(self) -> &'a mut W {
+        self.variant(ADC14CH3MAPW::ADC14CH3MAP_0)
+    }
+    #[doc = "ADC input channel internal 3 is selected for ADC input channel MAX-5"]
+    #[inline]
+    pub fn adc14ch3map_1(self) -> &'a mut W {
+        self.variant(ADC14CH3MAPW::ADC14CH3MAP_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 27;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:1 - ADC14 power modes"]
+    #[inline]
+    pub fn adc14pwrmd(&self) -> ADC14PWRMDR {
+        ADC14PWRMDR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 2 - ADC14 reference buffer burst"]
+    #[inline]
+    pub fn adc14refburst(&self) -> ADC14REFBURSTR {
+        ADC14REFBURSTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 3 - ADC14 data read-back format"]
+    #[inline]
+    pub fn adc14df(&self) -> ADC14DFR {
+        ADC14DFR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 4:5 - ADC14 resolution"]
+    #[inline]
+    pub fn adc14res(&self) -> ADC14RESR {
+        ADC14RESR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 16:20 - ADC14 conversion start address"]
+    #[inline]
+    pub fn adc14cstartadd(&self) -> ADC14CSTARTADDR {
+        let bits = {
+            const MASK: u8 = 31;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        ADC14CSTARTADDR { bits }
+    }
+    #[doc = "Bit 22 - Controls 1/2 AVCC ADC input channel selection"]
+    #[inline]
+    pub fn adc14batmap(&self) -> ADC14BATMAPR {
+        ADC14BATMAPR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 22;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 23 - Controls temperature sensor ADC input channel selection"]
+    #[inline]
+    pub fn adc14tcmap(&self) -> ADC14TCMAPR {
+        ADC14TCMAPR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 23;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 24 - Controls internal channel 0 selection to ADC input channel MAX-2"]
+    #[inline]
+    pub fn adc14ch0map(&self) -> ADC14CH0MAPR {
+        ADC14CH0MAPR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 24;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 25 - Controls internal channel 1 selection to ADC input channel MAX-3"]
+    #[inline]
+    pub fn adc14ch1map(&self) -> ADC14CH1MAPR {
+        ADC14CH1MAPR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 25;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 26 - Controls internal channel 2 selection to ADC input channel MAX-4"]
+    #[inline]
+    pub fn adc14ch2map(&self) -> ADC14CH2MAPR {
+        ADC14CH2MAPR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 26;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 27 - Controls internal channel 3 selection to ADC input channel MAX-5"]
+    #[inline]
+    pub fn adc14ch3map(&self) -> ADC14CH3MAPR {
+        ADC14CH3MAPR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 27;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 48 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:1 - ADC14 power modes"]
+    #[inline]
+    pub fn adc14pwrmd(&mut self) -> _ADC14PWRMDW {
+        _ADC14PWRMDW { w: self }
+    }
+    #[doc = "Bit 2 - ADC14 reference buffer burst"]
+    #[inline]
+    pub fn adc14refburst(&mut self) -> _ADC14REFBURSTW {
+        _ADC14REFBURSTW { w: self }
+    }
+    #[doc = "Bit 3 - ADC14 data read-back format"]
+    #[inline]
+    pub fn adc14df(&mut self) -> _ADC14DFW {
+        _ADC14DFW { w: self }
+    }
+    #[doc = "Bits 4:5 - ADC14 resolution"]
+    #[inline]
+    pub fn adc14res(&mut self) -> _ADC14RESW {
+        _ADC14RESW { w: self }
+    }
+    #[doc = "Bits 16:20 - ADC14 conversion start address"]
+    #[inline]
+    pub fn adc14cstartadd(&mut self) -> _ADC14CSTARTADDW {
+        _ADC14CSTARTADDW { w: self }
+    }
+    #[doc = "Bit 22 - Controls 1/2 AVCC ADC input channel selection"]
+    #[inline]
+    pub fn adc14batmap(&mut self) -> _ADC14BATMAPW {
+        _ADC14BATMAPW { w: self }
+    }
+    #[doc = "Bit 23 - Controls temperature sensor ADC input channel selection"]
+    #[inline]
+    pub fn adc14tcmap(&mut self) -> _ADC14TCMAPW {
+        _ADC14TCMAPW { w: self }
+    }
+    #[doc = "Bit 24 - Controls internal channel 0 selection to ADC input channel MAX-2"]
+    #[inline]
+    pub fn adc14ch0map(&mut self) -> _ADC14CH0MAPW {
+        _ADC14CH0MAPW { w: self }
+    }
+    #[doc = "Bit 25 - Controls internal channel 1 selection to ADC input channel MAX-3"]
+    #[inline]
+    pub fn adc14ch1map(&mut self) -> _ADC14CH1MAPW {
+        _ADC14CH1MAPW { w: self }
+    }
+    #[doc = "Bit 26 - Controls internal channel 2 selection to ADC input channel MAX-4"]
+    #[inline]
+    pub fn adc14ch2map(&mut self) -> _ADC14CH2MAPW {
+        _ADC14CH2MAPW { w: self }
+    }
+    #[doc = "Bit 27 - Controls internal channel 3 selection to ADC input channel MAX-5"]
+    #[inline]
+    pub fn adc14ch3map(&mut self) -> _ADC14CH3MAPW {
+        _ADC14CH3MAPW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/adc14/adc14hi0.rs b/example-source/msp432p401r/src/adc14/adc14hi0.rs
new file mode 100644
index 0000000..e29f629
--- /dev/null
+++ b/example-source/msp432p401r/src/adc14/adc14hi0.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::ADC14HI0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ADC14HI0R {
+    bits: u16,
+}
+impl ADC14HI0R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14HI0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14HI0W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - High threshold 0"]
+    #[inline]
+    pub fn adc14hi0(&self) -> ADC14HI0R {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        ADC14HI0R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 16383 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - High threshold 0"]
+    #[inline]
+    pub fn adc14hi0(&mut self) -> _ADC14HI0W {
+        _ADC14HI0W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/adc14/adc14hi1.rs b/example-source/msp432p401r/src/adc14/adc14hi1.rs
new file mode 100644
index 0000000..50a2158
--- /dev/null
+++ b/example-source/msp432p401r/src/adc14/adc14hi1.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::ADC14HI1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ADC14HI1R {
+    bits: u16,
+}
+impl ADC14HI1R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14HI1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14HI1W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - High threshold 1"]
+    #[inline]
+    pub fn adc14hi1(&self) -> ADC14HI1R {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        ADC14HI1R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 16383 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - High threshold 1"]
+    #[inline]
+    pub fn adc14hi1(&mut self) -> _ADC14HI1W {
+        _ADC14HI1W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/adc14/adc14ier0.rs b/example-source/msp432p401r/src/adc14/adc14ier0.rs
new file mode 100644
index 0000000..ca514d4
--- /dev/null
+++ b/example-source/msp432p401r/src/adc14/adc14ier0.rs
@@ -0,0 +1,3872 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::ADC14IER0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `ADC14IE0`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE0R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE0_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE0_1,
+}
+impl ADC14IE0R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE0R::ADC14IE0_0 => false,
+            ADC14IE0R::ADC14IE0_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE0R {
+        match value {
+            false => ADC14IE0R::ADC14IE0_0,
+            true => ADC14IE0R::ADC14IE0_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE0_0`"]
+    #[inline]
+    pub fn is_adc14ie0_0(&self) -> bool {
+        *self == ADC14IE0R::ADC14IE0_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE0_1`"]
+    #[inline]
+    pub fn is_adc14ie0_1(&self) -> bool {
+        *self == ADC14IE0R::ADC14IE0_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IE1`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE1R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE1_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE1_1,
+}
+impl ADC14IE1R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE1R::ADC14IE1_0 => false,
+            ADC14IE1R::ADC14IE1_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE1R {
+        match value {
+            false => ADC14IE1R::ADC14IE1_0,
+            true => ADC14IE1R::ADC14IE1_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE1_0`"]
+    #[inline]
+    pub fn is_adc14ie1_0(&self) -> bool {
+        *self == ADC14IE1R::ADC14IE1_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE1_1`"]
+    #[inline]
+    pub fn is_adc14ie1_1(&self) -> bool {
+        *self == ADC14IE1R::ADC14IE1_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IE2`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE2R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE2_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE2_1,
+}
+impl ADC14IE2R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE2R::ADC14IE2_0 => false,
+            ADC14IE2R::ADC14IE2_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE2R {
+        match value {
+            false => ADC14IE2R::ADC14IE2_0,
+            true => ADC14IE2R::ADC14IE2_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE2_0`"]
+    #[inline]
+    pub fn is_adc14ie2_0(&self) -> bool {
+        *self == ADC14IE2R::ADC14IE2_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE2_1`"]
+    #[inline]
+    pub fn is_adc14ie2_1(&self) -> bool {
+        *self == ADC14IE2R::ADC14IE2_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IE3`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE3R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE3_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE3_1,
+}
+impl ADC14IE3R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE3R::ADC14IE3_0 => false,
+            ADC14IE3R::ADC14IE3_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE3R {
+        match value {
+            false => ADC14IE3R::ADC14IE3_0,
+            true => ADC14IE3R::ADC14IE3_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE3_0`"]
+    #[inline]
+    pub fn is_adc14ie3_0(&self) -> bool {
+        *self == ADC14IE3R::ADC14IE3_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE3_1`"]
+    #[inline]
+    pub fn is_adc14ie3_1(&self) -> bool {
+        *self == ADC14IE3R::ADC14IE3_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IE4`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE4R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE4_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE4_1,
+}
+impl ADC14IE4R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE4R::ADC14IE4_0 => false,
+            ADC14IE4R::ADC14IE4_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE4R {
+        match value {
+            false => ADC14IE4R::ADC14IE4_0,
+            true => ADC14IE4R::ADC14IE4_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE4_0`"]
+    #[inline]
+    pub fn is_adc14ie4_0(&self) -> bool {
+        *self == ADC14IE4R::ADC14IE4_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE4_1`"]
+    #[inline]
+    pub fn is_adc14ie4_1(&self) -> bool {
+        *self == ADC14IE4R::ADC14IE4_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IE5`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE5R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE5_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE5_1,
+}
+impl ADC14IE5R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE5R::ADC14IE5_0 => false,
+            ADC14IE5R::ADC14IE5_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE5R {
+        match value {
+            false => ADC14IE5R::ADC14IE5_0,
+            true => ADC14IE5R::ADC14IE5_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE5_0`"]
+    #[inline]
+    pub fn is_adc14ie5_0(&self) -> bool {
+        *self == ADC14IE5R::ADC14IE5_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE5_1`"]
+    #[inline]
+    pub fn is_adc14ie5_1(&self) -> bool {
+        *self == ADC14IE5R::ADC14IE5_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IE6`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE6R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE6_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE6_1,
+}
+impl ADC14IE6R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE6R::ADC14IE6_0 => false,
+            ADC14IE6R::ADC14IE6_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE6R {
+        match value {
+            false => ADC14IE6R::ADC14IE6_0,
+            true => ADC14IE6R::ADC14IE6_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE6_0`"]
+    #[inline]
+    pub fn is_adc14ie6_0(&self) -> bool {
+        *self == ADC14IE6R::ADC14IE6_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE6_1`"]
+    #[inline]
+    pub fn is_adc14ie6_1(&self) -> bool {
+        *self == ADC14IE6R::ADC14IE6_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IE7`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE7R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE7_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE7_1,
+}
+impl ADC14IE7R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE7R::ADC14IE7_0 => false,
+            ADC14IE7R::ADC14IE7_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE7R {
+        match value {
+            false => ADC14IE7R::ADC14IE7_0,
+            true => ADC14IE7R::ADC14IE7_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE7_0`"]
+    #[inline]
+    pub fn is_adc14ie7_0(&self) -> bool {
+        *self == ADC14IE7R::ADC14IE7_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE7_1`"]
+    #[inline]
+    pub fn is_adc14ie7_1(&self) -> bool {
+        *self == ADC14IE7R::ADC14IE7_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IE8`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE8R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE8_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE8_1,
+}
+impl ADC14IE8R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE8R::ADC14IE8_0 => false,
+            ADC14IE8R::ADC14IE8_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE8R {
+        match value {
+            false => ADC14IE8R::ADC14IE8_0,
+            true => ADC14IE8R::ADC14IE8_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE8_0`"]
+    #[inline]
+    pub fn is_adc14ie8_0(&self) -> bool {
+        *self == ADC14IE8R::ADC14IE8_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE8_1`"]
+    #[inline]
+    pub fn is_adc14ie8_1(&self) -> bool {
+        *self == ADC14IE8R::ADC14IE8_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IE9`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE9R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE9_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE9_1,
+}
+impl ADC14IE9R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE9R::ADC14IE9_0 => false,
+            ADC14IE9R::ADC14IE9_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE9R {
+        match value {
+            false => ADC14IE9R::ADC14IE9_0,
+            true => ADC14IE9R::ADC14IE9_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE9_0`"]
+    #[inline]
+    pub fn is_adc14ie9_0(&self) -> bool {
+        *self == ADC14IE9R::ADC14IE9_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE9_1`"]
+    #[inline]
+    pub fn is_adc14ie9_1(&self) -> bool {
+        *self == ADC14IE9R::ADC14IE9_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IE10`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE10R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE10_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE10_1,
+}
+impl ADC14IE10R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE10R::ADC14IE10_0 => false,
+            ADC14IE10R::ADC14IE10_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE10R {
+        match value {
+            false => ADC14IE10R::ADC14IE10_0,
+            true => ADC14IE10R::ADC14IE10_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE10_0`"]
+    #[inline]
+    pub fn is_adc14ie10_0(&self) -> bool {
+        *self == ADC14IE10R::ADC14IE10_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE10_1`"]
+    #[inline]
+    pub fn is_adc14ie10_1(&self) -> bool {
+        *self == ADC14IE10R::ADC14IE10_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IE11`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE11R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE11_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE11_1,
+}
+impl ADC14IE11R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE11R::ADC14IE11_0 => false,
+            ADC14IE11R::ADC14IE11_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE11R {
+        match value {
+            false => ADC14IE11R::ADC14IE11_0,
+            true => ADC14IE11R::ADC14IE11_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE11_0`"]
+    #[inline]
+    pub fn is_adc14ie11_0(&self) -> bool {
+        *self == ADC14IE11R::ADC14IE11_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE11_1`"]
+    #[inline]
+    pub fn is_adc14ie11_1(&self) -> bool {
+        *self == ADC14IE11R::ADC14IE11_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IE12`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE12R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE12_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE12_1,
+}
+impl ADC14IE12R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE12R::ADC14IE12_0 => false,
+            ADC14IE12R::ADC14IE12_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE12R {
+        match value {
+            false => ADC14IE12R::ADC14IE12_0,
+            true => ADC14IE12R::ADC14IE12_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE12_0`"]
+    #[inline]
+    pub fn is_adc14ie12_0(&self) -> bool {
+        *self == ADC14IE12R::ADC14IE12_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE12_1`"]
+    #[inline]
+    pub fn is_adc14ie12_1(&self) -> bool {
+        *self == ADC14IE12R::ADC14IE12_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IE13`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE13R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE13_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE13_1,
+}
+impl ADC14IE13R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE13R::ADC14IE13_0 => false,
+            ADC14IE13R::ADC14IE13_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE13R {
+        match value {
+            false => ADC14IE13R::ADC14IE13_0,
+            true => ADC14IE13R::ADC14IE13_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE13_0`"]
+    #[inline]
+    pub fn is_adc14ie13_0(&self) -> bool {
+        *self == ADC14IE13R::ADC14IE13_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE13_1`"]
+    #[inline]
+    pub fn is_adc14ie13_1(&self) -> bool {
+        *self == ADC14IE13R::ADC14IE13_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IE14`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE14R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE14_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE14_1,
+}
+impl ADC14IE14R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE14R::ADC14IE14_0 => false,
+            ADC14IE14R::ADC14IE14_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE14R {
+        match value {
+            false => ADC14IE14R::ADC14IE14_0,
+            true => ADC14IE14R::ADC14IE14_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE14_0`"]
+    #[inline]
+    pub fn is_adc14ie14_0(&self) -> bool {
+        *self == ADC14IE14R::ADC14IE14_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE14_1`"]
+    #[inline]
+    pub fn is_adc14ie14_1(&self) -> bool {
+        *self == ADC14IE14R::ADC14IE14_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IE15`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE15R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE15_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE15_1,
+}
+impl ADC14IE15R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE15R::ADC14IE15_0 => false,
+            ADC14IE15R::ADC14IE15_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE15R {
+        match value {
+            false => ADC14IE15R::ADC14IE15_0,
+            true => ADC14IE15R::ADC14IE15_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE15_0`"]
+    #[inline]
+    pub fn is_adc14ie15_0(&self) -> bool {
+        *self == ADC14IE15R::ADC14IE15_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE15_1`"]
+    #[inline]
+    pub fn is_adc14ie15_1(&self) -> bool {
+        *self == ADC14IE15R::ADC14IE15_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IE16`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE16R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE16_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE16_1,
+}
+impl ADC14IE16R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE16R::ADC14IE16_0 => false,
+            ADC14IE16R::ADC14IE16_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE16R {
+        match value {
+            false => ADC14IE16R::ADC14IE16_0,
+            true => ADC14IE16R::ADC14IE16_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE16_0`"]
+    #[inline]
+    pub fn is_adc14ie16_0(&self) -> bool {
+        *self == ADC14IE16R::ADC14IE16_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE16_1`"]
+    #[inline]
+    pub fn is_adc14ie16_1(&self) -> bool {
+        *self == ADC14IE16R::ADC14IE16_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IE17`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE17R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE17_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE17_1,
+}
+impl ADC14IE17R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE17R::ADC14IE17_0 => false,
+            ADC14IE17R::ADC14IE17_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE17R {
+        match value {
+            false => ADC14IE17R::ADC14IE17_0,
+            true => ADC14IE17R::ADC14IE17_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE17_0`"]
+    #[inline]
+    pub fn is_adc14ie17_0(&self) -> bool {
+        *self == ADC14IE17R::ADC14IE17_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE17_1`"]
+    #[inline]
+    pub fn is_adc14ie17_1(&self) -> bool {
+        *self == ADC14IE17R::ADC14IE17_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IE19`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE19R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE19_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE19_1,
+}
+impl ADC14IE19R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE19R::ADC14IE19_0 => false,
+            ADC14IE19R::ADC14IE19_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE19R {
+        match value {
+            false => ADC14IE19R::ADC14IE19_0,
+            true => ADC14IE19R::ADC14IE19_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE19_0`"]
+    #[inline]
+    pub fn is_adc14ie19_0(&self) -> bool {
+        *self == ADC14IE19R::ADC14IE19_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE19_1`"]
+    #[inline]
+    pub fn is_adc14ie19_1(&self) -> bool {
+        *self == ADC14IE19R::ADC14IE19_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IE18`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE18R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE18_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE18_1,
+}
+impl ADC14IE18R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE18R::ADC14IE18_0 => false,
+            ADC14IE18R::ADC14IE18_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE18R {
+        match value {
+            false => ADC14IE18R::ADC14IE18_0,
+            true => ADC14IE18R::ADC14IE18_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE18_0`"]
+    #[inline]
+    pub fn is_adc14ie18_0(&self) -> bool {
+        *self == ADC14IE18R::ADC14IE18_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE18_1`"]
+    #[inline]
+    pub fn is_adc14ie18_1(&self) -> bool {
+        *self == ADC14IE18R::ADC14IE18_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IE20`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE20R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE20_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE20_1,
+}
+impl ADC14IE20R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE20R::ADC14IE20_0 => false,
+            ADC14IE20R::ADC14IE20_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE20R {
+        match value {
+            false => ADC14IE20R::ADC14IE20_0,
+            true => ADC14IE20R::ADC14IE20_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE20_0`"]
+    #[inline]
+    pub fn is_adc14ie20_0(&self) -> bool {
+        *self == ADC14IE20R::ADC14IE20_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE20_1`"]
+    #[inline]
+    pub fn is_adc14ie20_1(&self) -> bool {
+        *self == ADC14IE20R::ADC14IE20_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IE21`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE21R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE21_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE21_1,
+}
+impl ADC14IE21R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE21R::ADC14IE21_0 => false,
+            ADC14IE21R::ADC14IE21_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE21R {
+        match value {
+            false => ADC14IE21R::ADC14IE21_0,
+            true => ADC14IE21R::ADC14IE21_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE21_0`"]
+    #[inline]
+    pub fn is_adc14ie21_0(&self) -> bool {
+        *self == ADC14IE21R::ADC14IE21_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE21_1`"]
+    #[inline]
+    pub fn is_adc14ie21_1(&self) -> bool {
+        *self == ADC14IE21R::ADC14IE21_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IE22`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE22R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE22_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE22_1,
+}
+impl ADC14IE22R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE22R::ADC14IE22_0 => false,
+            ADC14IE22R::ADC14IE22_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE22R {
+        match value {
+            false => ADC14IE22R::ADC14IE22_0,
+            true => ADC14IE22R::ADC14IE22_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE22_0`"]
+    #[inline]
+    pub fn is_adc14ie22_0(&self) -> bool {
+        *self == ADC14IE22R::ADC14IE22_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE22_1`"]
+    #[inline]
+    pub fn is_adc14ie22_1(&self) -> bool {
+        *self == ADC14IE22R::ADC14IE22_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IE23`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE23R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE23_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE23_1,
+}
+impl ADC14IE23R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE23R::ADC14IE23_0 => false,
+            ADC14IE23R::ADC14IE23_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE23R {
+        match value {
+            false => ADC14IE23R::ADC14IE23_0,
+            true => ADC14IE23R::ADC14IE23_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE23_0`"]
+    #[inline]
+    pub fn is_adc14ie23_0(&self) -> bool {
+        *self == ADC14IE23R::ADC14IE23_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE23_1`"]
+    #[inline]
+    pub fn is_adc14ie23_1(&self) -> bool {
+        *self == ADC14IE23R::ADC14IE23_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IE24`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE24R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE24_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE24_1,
+}
+impl ADC14IE24R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE24R::ADC14IE24_0 => false,
+            ADC14IE24R::ADC14IE24_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE24R {
+        match value {
+            false => ADC14IE24R::ADC14IE24_0,
+            true => ADC14IE24R::ADC14IE24_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE24_0`"]
+    #[inline]
+    pub fn is_adc14ie24_0(&self) -> bool {
+        *self == ADC14IE24R::ADC14IE24_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE24_1`"]
+    #[inline]
+    pub fn is_adc14ie24_1(&self) -> bool {
+        *self == ADC14IE24R::ADC14IE24_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IE25`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE25R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE25_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE25_1,
+}
+impl ADC14IE25R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE25R::ADC14IE25_0 => false,
+            ADC14IE25R::ADC14IE25_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE25R {
+        match value {
+            false => ADC14IE25R::ADC14IE25_0,
+            true => ADC14IE25R::ADC14IE25_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE25_0`"]
+    #[inline]
+    pub fn is_adc14ie25_0(&self) -> bool {
+        *self == ADC14IE25R::ADC14IE25_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE25_1`"]
+    #[inline]
+    pub fn is_adc14ie25_1(&self) -> bool {
+        *self == ADC14IE25R::ADC14IE25_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IE26`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE26R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE26_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE26_1,
+}
+impl ADC14IE26R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE26R::ADC14IE26_0 => false,
+            ADC14IE26R::ADC14IE26_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE26R {
+        match value {
+            false => ADC14IE26R::ADC14IE26_0,
+            true => ADC14IE26R::ADC14IE26_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE26_0`"]
+    #[inline]
+    pub fn is_adc14ie26_0(&self) -> bool {
+        *self == ADC14IE26R::ADC14IE26_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE26_1`"]
+    #[inline]
+    pub fn is_adc14ie26_1(&self) -> bool {
+        *self == ADC14IE26R::ADC14IE26_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IE27`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE27R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE27_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE27_1,
+}
+impl ADC14IE27R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE27R::ADC14IE27_0 => false,
+            ADC14IE27R::ADC14IE27_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE27R {
+        match value {
+            false => ADC14IE27R::ADC14IE27_0,
+            true => ADC14IE27R::ADC14IE27_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE27_0`"]
+    #[inline]
+    pub fn is_adc14ie27_0(&self) -> bool {
+        *self == ADC14IE27R::ADC14IE27_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE27_1`"]
+    #[inline]
+    pub fn is_adc14ie27_1(&self) -> bool {
+        *self == ADC14IE27R::ADC14IE27_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IE28`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE28R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE28_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE28_1,
+}
+impl ADC14IE28R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE28R::ADC14IE28_0 => false,
+            ADC14IE28R::ADC14IE28_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE28R {
+        match value {
+            false => ADC14IE28R::ADC14IE28_0,
+            true => ADC14IE28R::ADC14IE28_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE28_0`"]
+    #[inline]
+    pub fn is_adc14ie28_0(&self) -> bool {
+        *self == ADC14IE28R::ADC14IE28_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE28_1`"]
+    #[inline]
+    pub fn is_adc14ie28_1(&self) -> bool {
+        *self == ADC14IE28R::ADC14IE28_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IE29`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE29R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE29_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE29_1,
+}
+impl ADC14IE29R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE29R::ADC14IE29_0 => false,
+            ADC14IE29R::ADC14IE29_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE29R {
+        match value {
+            false => ADC14IE29R::ADC14IE29_0,
+            true => ADC14IE29R::ADC14IE29_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE29_0`"]
+    #[inline]
+    pub fn is_adc14ie29_0(&self) -> bool {
+        *self == ADC14IE29R::ADC14IE29_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE29_1`"]
+    #[inline]
+    pub fn is_adc14ie29_1(&self) -> bool {
+        *self == ADC14IE29R::ADC14IE29_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IE30`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE30R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE30_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE30_1,
+}
+impl ADC14IE30R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE30R::ADC14IE30_0 => false,
+            ADC14IE30R::ADC14IE30_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE30R {
+        match value {
+            false => ADC14IE30R::ADC14IE30_0,
+            true => ADC14IE30R::ADC14IE30_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE30_0`"]
+    #[inline]
+    pub fn is_adc14ie30_0(&self) -> bool {
+        *self == ADC14IE30R::ADC14IE30_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE30_1`"]
+    #[inline]
+    pub fn is_adc14ie30_1(&self) -> bool {
+        *self == ADC14IE30R::ADC14IE30_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IE31`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IE31R {
+    #[doc = "Interrupt disabled"]
+    ADC14IE31_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE31_1,
+}
+impl ADC14IE31R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IE31R::ADC14IE31_0 => false,
+            ADC14IE31R::ADC14IE31_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IE31R {
+        match value {
+            false => ADC14IE31R::ADC14IE31_0,
+            true => ADC14IE31R::ADC14IE31_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE31_0`"]
+    #[inline]
+    pub fn is_adc14ie31_0(&self) -> bool {
+        *self == ADC14IE31R::ADC14IE31_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IE31_1`"]
+    #[inline]
+    pub fn is_adc14ie31_1(&self) -> bool {
+        *self == ADC14IE31R::ADC14IE31_1
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE0`"]
+pub enum ADC14IE0W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE0_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE0_1,
+}
+impl ADC14IE0W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE0W::ADC14IE0_0 => false,
+            ADC14IE0W::ADC14IE0_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE0W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE0W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie0_0(self) -> &'a mut W {
+        self.variant(ADC14IE0W::ADC14IE0_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie0_1(self) -> &'a mut W {
+        self.variant(ADC14IE0W::ADC14IE0_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE1`"]
+pub enum ADC14IE1W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE1_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE1_1,
+}
+impl ADC14IE1W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE1W::ADC14IE1_0 => false,
+            ADC14IE1W::ADC14IE1_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE1W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE1W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie1_0(self) -> &'a mut W {
+        self.variant(ADC14IE1W::ADC14IE1_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie1_1(self) -> &'a mut W {
+        self.variant(ADC14IE1W::ADC14IE1_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE2`"]
+pub enum ADC14IE2W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE2_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE2_1,
+}
+impl ADC14IE2W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE2W::ADC14IE2_0 => false,
+            ADC14IE2W::ADC14IE2_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE2W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE2W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie2_0(self) -> &'a mut W {
+        self.variant(ADC14IE2W::ADC14IE2_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie2_1(self) -> &'a mut W {
+        self.variant(ADC14IE2W::ADC14IE2_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE3`"]
+pub enum ADC14IE3W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE3_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE3_1,
+}
+impl ADC14IE3W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE3W::ADC14IE3_0 => false,
+            ADC14IE3W::ADC14IE3_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE3W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE3W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie3_0(self) -> &'a mut W {
+        self.variant(ADC14IE3W::ADC14IE3_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie3_1(self) -> &'a mut W {
+        self.variant(ADC14IE3W::ADC14IE3_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE4`"]
+pub enum ADC14IE4W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE4_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE4_1,
+}
+impl ADC14IE4W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE4W::ADC14IE4_0 => false,
+            ADC14IE4W::ADC14IE4_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE4W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE4W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE4W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie4_0(self) -> &'a mut W {
+        self.variant(ADC14IE4W::ADC14IE4_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie4_1(self) -> &'a mut W {
+        self.variant(ADC14IE4W::ADC14IE4_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE5`"]
+pub enum ADC14IE5W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE5_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE5_1,
+}
+impl ADC14IE5W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE5W::ADC14IE5_0 => false,
+            ADC14IE5W::ADC14IE5_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE5W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE5W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE5W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie5_0(self) -> &'a mut W {
+        self.variant(ADC14IE5W::ADC14IE5_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie5_1(self) -> &'a mut W {
+        self.variant(ADC14IE5W::ADC14IE5_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE6`"]
+pub enum ADC14IE6W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE6_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE6_1,
+}
+impl ADC14IE6W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE6W::ADC14IE6_0 => false,
+            ADC14IE6W::ADC14IE6_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE6W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE6W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE6W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie6_0(self) -> &'a mut W {
+        self.variant(ADC14IE6W::ADC14IE6_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie6_1(self) -> &'a mut W {
+        self.variant(ADC14IE6W::ADC14IE6_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE7`"]
+pub enum ADC14IE7W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE7_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE7_1,
+}
+impl ADC14IE7W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE7W::ADC14IE7_0 => false,
+            ADC14IE7W::ADC14IE7_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE7W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE7W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE7W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie7_0(self) -> &'a mut W {
+        self.variant(ADC14IE7W::ADC14IE7_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie7_1(self) -> &'a mut W {
+        self.variant(ADC14IE7W::ADC14IE7_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE8`"]
+pub enum ADC14IE8W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE8_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE8_1,
+}
+impl ADC14IE8W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE8W::ADC14IE8_0 => false,
+            ADC14IE8W::ADC14IE8_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE8W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE8W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE8W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie8_0(self) -> &'a mut W {
+        self.variant(ADC14IE8W::ADC14IE8_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie8_1(self) -> &'a mut W {
+        self.variant(ADC14IE8W::ADC14IE8_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE9`"]
+pub enum ADC14IE9W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE9_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE9_1,
+}
+impl ADC14IE9W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE9W::ADC14IE9_0 => false,
+            ADC14IE9W::ADC14IE9_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE9W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE9W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE9W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie9_0(self) -> &'a mut W {
+        self.variant(ADC14IE9W::ADC14IE9_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie9_1(self) -> &'a mut W {
+        self.variant(ADC14IE9W::ADC14IE9_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE10`"]
+pub enum ADC14IE10W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE10_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE10_1,
+}
+impl ADC14IE10W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE10W::ADC14IE10_0 => false,
+            ADC14IE10W::ADC14IE10_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE10W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE10W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE10W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie10_0(self) -> &'a mut W {
+        self.variant(ADC14IE10W::ADC14IE10_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie10_1(self) -> &'a mut W {
+        self.variant(ADC14IE10W::ADC14IE10_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE11`"]
+pub enum ADC14IE11W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE11_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE11_1,
+}
+impl ADC14IE11W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE11W::ADC14IE11_0 => false,
+            ADC14IE11W::ADC14IE11_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE11W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE11W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE11W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie11_0(self) -> &'a mut W {
+        self.variant(ADC14IE11W::ADC14IE11_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie11_1(self) -> &'a mut W {
+        self.variant(ADC14IE11W::ADC14IE11_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE12`"]
+pub enum ADC14IE12W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE12_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE12_1,
+}
+impl ADC14IE12W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE12W::ADC14IE12_0 => false,
+            ADC14IE12W::ADC14IE12_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE12W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE12W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE12W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie12_0(self) -> &'a mut W {
+        self.variant(ADC14IE12W::ADC14IE12_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie12_1(self) -> &'a mut W {
+        self.variant(ADC14IE12W::ADC14IE12_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE13`"]
+pub enum ADC14IE13W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE13_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE13_1,
+}
+impl ADC14IE13W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE13W::ADC14IE13_0 => false,
+            ADC14IE13W::ADC14IE13_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE13W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE13W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE13W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie13_0(self) -> &'a mut W {
+        self.variant(ADC14IE13W::ADC14IE13_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie13_1(self) -> &'a mut W {
+        self.variant(ADC14IE13W::ADC14IE13_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE14`"]
+pub enum ADC14IE14W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE14_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE14_1,
+}
+impl ADC14IE14W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE14W::ADC14IE14_0 => false,
+            ADC14IE14W::ADC14IE14_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE14W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE14W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE14W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie14_0(self) -> &'a mut W {
+        self.variant(ADC14IE14W::ADC14IE14_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie14_1(self) -> &'a mut W {
+        self.variant(ADC14IE14W::ADC14IE14_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE15`"]
+pub enum ADC14IE15W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE15_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE15_1,
+}
+impl ADC14IE15W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE15W::ADC14IE15_0 => false,
+            ADC14IE15W::ADC14IE15_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE15W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE15W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE15W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie15_0(self) -> &'a mut W {
+        self.variant(ADC14IE15W::ADC14IE15_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie15_1(self) -> &'a mut W {
+        self.variant(ADC14IE15W::ADC14IE15_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE16`"]
+pub enum ADC14IE16W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE16_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE16_1,
+}
+impl ADC14IE16W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE16W::ADC14IE16_0 => false,
+            ADC14IE16W::ADC14IE16_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE16W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE16W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE16W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie16_0(self) -> &'a mut W {
+        self.variant(ADC14IE16W::ADC14IE16_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie16_1(self) -> &'a mut W {
+        self.variant(ADC14IE16W::ADC14IE16_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 16;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE17`"]
+pub enum ADC14IE17W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE17_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE17_1,
+}
+impl ADC14IE17W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE17W::ADC14IE17_0 => false,
+            ADC14IE17W::ADC14IE17_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE17W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE17W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE17W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie17_0(self) -> &'a mut W {
+        self.variant(ADC14IE17W::ADC14IE17_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie17_1(self) -> &'a mut W {
+        self.variant(ADC14IE17W::ADC14IE17_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 17;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE19`"]
+pub enum ADC14IE19W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE19_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE19_1,
+}
+impl ADC14IE19W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE19W::ADC14IE19_0 => false,
+            ADC14IE19W::ADC14IE19_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE19W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE19W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE19W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie19_0(self) -> &'a mut W {
+        self.variant(ADC14IE19W::ADC14IE19_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie19_1(self) -> &'a mut W {
+        self.variant(ADC14IE19W::ADC14IE19_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 19;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE18`"]
+pub enum ADC14IE18W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE18_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE18_1,
+}
+impl ADC14IE18W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE18W::ADC14IE18_0 => false,
+            ADC14IE18W::ADC14IE18_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE18W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE18W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE18W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie18_0(self) -> &'a mut W {
+        self.variant(ADC14IE18W::ADC14IE18_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie18_1(self) -> &'a mut W {
+        self.variant(ADC14IE18W::ADC14IE18_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 18;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE20`"]
+pub enum ADC14IE20W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE20_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE20_1,
+}
+impl ADC14IE20W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE20W::ADC14IE20_0 => false,
+            ADC14IE20W::ADC14IE20_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE20W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE20W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE20W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie20_0(self) -> &'a mut W {
+        self.variant(ADC14IE20W::ADC14IE20_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie20_1(self) -> &'a mut W {
+        self.variant(ADC14IE20W::ADC14IE20_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 20;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE21`"]
+pub enum ADC14IE21W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE21_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE21_1,
+}
+impl ADC14IE21W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE21W::ADC14IE21_0 => false,
+            ADC14IE21W::ADC14IE21_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE21W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE21W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE21W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie21_0(self) -> &'a mut W {
+        self.variant(ADC14IE21W::ADC14IE21_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie21_1(self) -> &'a mut W {
+        self.variant(ADC14IE21W::ADC14IE21_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 21;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE22`"]
+pub enum ADC14IE22W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE22_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE22_1,
+}
+impl ADC14IE22W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE22W::ADC14IE22_0 => false,
+            ADC14IE22W::ADC14IE22_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE22W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE22W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE22W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie22_0(self) -> &'a mut W {
+        self.variant(ADC14IE22W::ADC14IE22_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie22_1(self) -> &'a mut W {
+        self.variant(ADC14IE22W::ADC14IE22_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 22;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE23`"]
+pub enum ADC14IE23W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE23_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE23_1,
+}
+impl ADC14IE23W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE23W::ADC14IE23_0 => false,
+            ADC14IE23W::ADC14IE23_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE23W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE23W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE23W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie23_0(self) -> &'a mut W {
+        self.variant(ADC14IE23W::ADC14IE23_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie23_1(self) -> &'a mut W {
+        self.variant(ADC14IE23W::ADC14IE23_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 23;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE24`"]
+pub enum ADC14IE24W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE24_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE24_1,
+}
+impl ADC14IE24W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE24W::ADC14IE24_0 => false,
+            ADC14IE24W::ADC14IE24_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE24W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE24W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE24W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie24_0(self) -> &'a mut W {
+        self.variant(ADC14IE24W::ADC14IE24_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie24_1(self) -> &'a mut W {
+        self.variant(ADC14IE24W::ADC14IE24_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 24;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE25`"]
+pub enum ADC14IE25W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE25_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE25_1,
+}
+impl ADC14IE25W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE25W::ADC14IE25_0 => false,
+            ADC14IE25W::ADC14IE25_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE25W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE25W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE25W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie25_0(self) -> &'a mut W {
+        self.variant(ADC14IE25W::ADC14IE25_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie25_1(self) -> &'a mut W {
+        self.variant(ADC14IE25W::ADC14IE25_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 25;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE26`"]
+pub enum ADC14IE26W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE26_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE26_1,
+}
+impl ADC14IE26W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE26W::ADC14IE26_0 => false,
+            ADC14IE26W::ADC14IE26_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE26W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE26W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE26W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie26_0(self) -> &'a mut W {
+        self.variant(ADC14IE26W::ADC14IE26_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie26_1(self) -> &'a mut W {
+        self.variant(ADC14IE26W::ADC14IE26_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 26;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE27`"]
+pub enum ADC14IE27W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE27_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE27_1,
+}
+impl ADC14IE27W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE27W::ADC14IE27_0 => false,
+            ADC14IE27W::ADC14IE27_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE27W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE27W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE27W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie27_0(self) -> &'a mut W {
+        self.variant(ADC14IE27W::ADC14IE27_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie27_1(self) -> &'a mut W {
+        self.variant(ADC14IE27W::ADC14IE27_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 27;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE28`"]
+pub enum ADC14IE28W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE28_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE28_1,
+}
+impl ADC14IE28W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE28W::ADC14IE28_0 => false,
+            ADC14IE28W::ADC14IE28_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE28W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE28W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE28W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie28_0(self) -> &'a mut W {
+        self.variant(ADC14IE28W::ADC14IE28_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie28_1(self) -> &'a mut W {
+        self.variant(ADC14IE28W::ADC14IE28_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 28;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE29`"]
+pub enum ADC14IE29W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE29_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE29_1,
+}
+impl ADC14IE29W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE29W::ADC14IE29_0 => false,
+            ADC14IE29W::ADC14IE29_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE29W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE29W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE29W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie29_0(self) -> &'a mut W {
+        self.variant(ADC14IE29W::ADC14IE29_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie29_1(self) -> &'a mut W {
+        self.variant(ADC14IE29W::ADC14IE29_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 29;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE30`"]
+pub enum ADC14IE30W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE30_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE30_1,
+}
+impl ADC14IE30W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE30W::ADC14IE30_0 => false,
+            ADC14IE30W::ADC14IE30_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE30W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE30W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE30W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie30_0(self) -> &'a mut W {
+        self.variant(ADC14IE30W::ADC14IE30_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie30_1(self) -> &'a mut W {
+        self.variant(ADC14IE30W::ADC14IE30_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 30;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IE31`"]
+pub enum ADC14IE31W {
+    #[doc = "Interrupt disabled"]
+    ADC14IE31_0,
+    #[doc = "Interrupt enabled"]
+    ADC14IE31_1,
+}
+impl ADC14IE31W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14IE31W::ADC14IE31_0 => false,
+            ADC14IE31W::ADC14IE31_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IE31W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IE31W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IE31W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ie31_0(self) -> &'a mut W {
+        self.variant(ADC14IE31W::ADC14IE31_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ie31_1(self) -> &'a mut W {
+        self.variant(ADC14IE31W::ADC14IE31_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 31;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie0(&self) -> ADC14IE0R {
+        ADC14IE0R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie1(&self) -> ADC14IE1R {
+        ADC14IE1R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie2(&self) -> ADC14IE2R {
+        ADC14IE2R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 3 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie3(&self) -> ADC14IE3R {
+        ADC14IE3R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 4 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie4(&self) -> ADC14IE4R {
+        ADC14IE4R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 5 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie5(&self) -> ADC14IE5R {
+        ADC14IE5R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 6 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie6(&self) -> ADC14IE6R {
+        ADC14IE6R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 7 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie7(&self) -> ADC14IE7R {
+        ADC14IE7R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 8 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie8(&self) -> ADC14IE8R {
+        ADC14IE8R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 9 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie9(&self) -> ADC14IE9R {
+        ADC14IE9R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 10 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie10(&self) -> ADC14IE10R {
+        ADC14IE10R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 11 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie11(&self) -> ADC14IE11R {
+        ADC14IE11R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 12 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie12(&self) -> ADC14IE12R {
+        ADC14IE12R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 13 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie13(&self) -> ADC14IE13R {
+        ADC14IE13R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 14 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie14(&self) -> ADC14IE14R {
+        ADC14IE14R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 15 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie15(&self) -> ADC14IE15R {
+        ADC14IE15R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 16 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie16(&self) -> ADC14IE16R {
+        ADC14IE16R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 17 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie17(&self) -> ADC14IE17R {
+        ADC14IE17R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 17;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 19 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie19(&self) -> ADC14IE19R {
+        ADC14IE19R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 19;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 18 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie18(&self) -> ADC14IE18R {
+        ADC14IE18R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 18;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 20 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie20(&self) -> ADC14IE20R {
+        ADC14IE20R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 20;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 21 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie21(&self) -> ADC14IE21R {
+        ADC14IE21R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 21;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 22 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie22(&self) -> ADC14IE22R {
+        ADC14IE22R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 22;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 23 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie23(&self) -> ADC14IE23R {
+        ADC14IE23R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 23;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 24 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie24(&self) -> ADC14IE24R {
+        ADC14IE24R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 24;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 25 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie25(&self) -> ADC14IE25R {
+        ADC14IE25R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 25;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 26 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie26(&self) -> ADC14IE26R {
+        ADC14IE26R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 26;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 27 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie27(&self) -> ADC14IE27R {
+        ADC14IE27R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 27;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 28 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie28(&self) -> ADC14IE28R {
+        ADC14IE28R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 28;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 29 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie29(&self) -> ADC14IE29R {
+        ADC14IE29R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 29;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 30 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie30(&self) -> ADC14IE30R {
+        ADC14IE30R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 30;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 31 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie31(&self) -> ADC14IE31R {
+        ADC14IE31R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 31;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie0(&mut self) -> _ADC14IE0W {
+        _ADC14IE0W { w: self }
+    }
+    #[doc = "Bit 1 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie1(&mut self) -> _ADC14IE1W {
+        _ADC14IE1W { w: self }
+    }
+    #[doc = "Bit 2 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie2(&mut self) -> _ADC14IE2W {
+        _ADC14IE2W { w: self }
+    }
+    #[doc = "Bit 3 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie3(&mut self) -> _ADC14IE3W {
+        _ADC14IE3W { w: self }
+    }
+    #[doc = "Bit 4 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie4(&mut self) -> _ADC14IE4W {
+        _ADC14IE4W { w: self }
+    }
+    #[doc = "Bit 5 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie5(&mut self) -> _ADC14IE5W {
+        _ADC14IE5W { w: self }
+    }
+    #[doc = "Bit 6 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie6(&mut self) -> _ADC14IE6W {
+        _ADC14IE6W { w: self }
+    }
+    #[doc = "Bit 7 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie7(&mut self) -> _ADC14IE7W {
+        _ADC14IE7W { w: self }
+    }
+    #[doc = "Bit 8 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie8(&mut self) -> _ADC14IE8W {
+        _ADC14IE8W { w: self }
+    }
+    #[doc = "Bit 9 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie9(&mut self) -> _ADC14IE9W {
+        _ADC14IE9W { w: self }
+    }
+    #[doc = "Bit 10 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie10(&mut self) -> _ADC14IE10W {
+        _ADC14IE10W { w: self }
+    }
+    #[doc = "Bit 11 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie11(&mut self) -> _ADC14IE11W {
+        _ADC14IE11W { w: self }
+    }
+    #[doc = "Bit 12 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie12(&mut self) -> _ADC14IE12W {
+        _ADC14IE12W { w: self }
+    }
+    #[doc = "Bit 13 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie13(&mut self) -> _ADC14IE13W {
+        _ADC14IE13W { w: self }
+    }
+    #[doc = "Bit 14 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie14(&mut self) -> _ADC14IE14W {
+        _ADC14IE14W { w: self }
+    }
+    #[doc = "Bit 15 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie15(&mut self) -> _ADC14IE15W {
+        _ADC14IE15W { w: self }
+    }
+    #[doc = "Bit 16 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie16(&mut self) -> _ADC14IE16W {
+        _ADC14IE16W { w: self }
+    }
+    #[doc = "Bit 17 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie17(&mut self) -> _ADC14IE17W {
+        _ADC14IE17W { w: self }
+    }
+    #[doc = "Bit 19 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie19(&mut self) -> _ADC14IE19W {
+        _ADC14IE19W { w: self }
+    }
+    #[doc = "Bit 18 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie18(&mut self) -> _ADC14IE18W {
+        _ADC14IE18W { w: self }
+    }
+    #[doc = "Bit 20 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie20(&mut self) -> _ADC14IE20W {
+        _ADC14IE20W { w: self }
+    }
+    #[doc = "Bit 21 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie21(&mut self) -> _ADC14IE21W {
+        _ADC14IE21W { w: self }
+    }
+    #[doc = "Bit 22 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie22(&mut self) -> _ADC14IE22W {
+        _ADC14IE22W { w: self }
+    }
+    #[doc = "Bit 23 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie23(&mut self) -> _ADC14IE23W {
+        _ADC14IE23W { w: self }
+    }
+    #[doc = "Bit 24 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie24(&mut self) -> _ADC14IE24W {
+        _ADC14IE24W { w: self }
+    }
+    #[doc = "Bit 25 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie25(&mut self) -> _ADC14IE25W {
+        _ADC14IE25W { w: self }
+    }
+    #[doc = "Bit 26 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie26(&mut self) -> _ADC14IE26W {
+        _ADC14IE26W { w: self }
+    }
+    #[doc = "Bit 27 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie27(&mut self) -> _ADC14IE27W {
+        _ADC14IE27W { w: self }
+    }
+    #[doc = "Bit 28 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie28(&mut self) -> _ADC14IE28W {
+        _ADC14IE28W { w: self }
+    }
+    #[doc = "Bit 29 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie29(&mut self) -> _ADC14IE29W {
+        _ADC14IE29W { w: self }
+    }
+    #[doc = "Bit 30 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie30(&mut self) -> _ADC14IE30W {
+        _ADC14IE30W { w: self }
+    }
+    #[doc = "Bit 31 - Interrupt enable"]
+    #[inline]
+    pub fn adc14ie31(&mut self) -> _ADC14IE31W {
+        _ADC14IE31W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/adc14/adc14ier1.rs b/example-source/msp432p401r/src/adc14/adc14ier1.rs
new file mode 100644
index 0000000..95dae29
--- /dev/null
+++ b/example-source/msp432p401r/src/adc14/adc14ier1.rs
@@ -0,0 +1,778 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::ADC14IER1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `ADC14INIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14INIER {
+    #[doc = "Interrupt disabled"]
+    ADC14INIE_0,
+    #[doc = "Interrupt enabled"]
+    ADC14INIE_1,
+}
+impl ADC14INIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14INIER::ADC14INIE_0 => false,
+            ADC14INIER::ADC14INIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14INIER {
+        match value {
+            false => ADC14INIER::ADC14INIE_0,
+            true => ADC14INIER::ADC14INIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14INIE_0`"]
+    #[inline]
+    pub fn is_adc14inie_0(&self) -> bool {
+        *self == ADC14INIER::ADC14INIE_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14INIE_1`"]
+    #[inline]
+    pub fn is_adc14inie_1(&self) -> bool {
+        *self == ADC14INIER::ADC14INIE_1
+    }
+}
+#[doc = "Possible values of the field `ADC14LOIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14LOIER {
+    #[doc = "Interrupt disabled"]
+    ADC14LOIE_0,
+    #[doc = "Interrupt enabled"]
+    ADC14LOIE_1,
+}
+impl ADC14LOIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14LOIER::ADC14LOIE_0 => false,
+            ADC14LOIER::ADC14LOIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14LOIER {
+        match value {
+            false => ADC14LOIER::ADC14LOIE_0,
+            true => ADC14LOIER::ADC14LOIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14LOIE_0`"]
+    #[inline]
+    pub fn is_adc14loie_0(&self) -> bool {
+        *self == ADC14LOIER::ADC14LOIE_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14LOIE_1`"]
+    #[inline]
+    pub fn is_adc14loie_1(&self) -> bool {
+        *self == ADC14LOIER::ADC14LOIE_1
+    }
+}
+#[doc = "Possible values of the field `ADC14HIIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14HIIER {
+    #[doc = "Interrupt disabled"]
+    ADC14HIIE_0,
+    #[doc = "Interrupt enabled"]
+    ADC14HIIE_1,
+}
+impl ADC14HIIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14HIIER::ADC14HIIE_0 => false,
+            ADC14HIIER::ADC14HIIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14HIIER {
+        match value {
+            false => ADC14HIIER::ADC14HIIE_0,
+            true => ADC14HIIER::ADC14HIIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14HIIE_0`"]
+    #[inline]
+    pub fn is_adc14hiie_0(&self) -> bool {
+        *self == ADC14HIIER::ADC14HIIE_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14HIIE_1`"]
+    #[inline]
+    pub fn is_adc14hiie_1(&self) -> bool {
+        *self == ADC14HIIER::ADC14HIIE_1
+    }
+}
+#[doc = "Possible values of the field `ADC14OVIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14OVIER {
+    #[doc = "Interrupt disabled"]
+    ADC14OVIE_0,
+    #[doc = "Interrupt enabled"]
+    ADC14OVIE_1,
+}
+impl ADC14OVIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14OVIER::ADC14OVIE_0 => false,
+            ADC14OVIER::ADC14OVIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14OVIER {
+        match value {
+            false => ADC14OVIER::ADC14OVIE_0,
+            true => ADC14OVIER::ADC14OVIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14OVIE_0`"]
+    #[inline]
+    pub fn is_adc14ovie_0(&self) -> bool {
+        *self == ADC14OVIER::ADC14OVIE_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14OVIE_1`"]
+    #[inline]
+    pub fn is_adc14ovie_1(&self) -> bool {
+        *self == ADC14OVIER::ADC14OVIE_1
+    }
+}
+#[doc = "Possible values of the field `ADC14TOVIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14TOVIER {
+    #[doc = "Interrupt disabled"]
+    ADC14TOVIE_0,
+    #[doc = "Interrupt enabled"]
+    ADC14TOVIE_1,
+}
+impl ADC14TOVIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14TOVIER::ADC14TOVIE_0 => false,
+            ADC14TOVIER::ADC14TOVIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14TOVIER {
+        match value {
+            false => ADC14TOVIER::ADC14TOVIE_0,
+            true => ADC14TOVIER::ADC14TOVIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14TOVIE_0`"]
+    #[inline]
+    pub fn is_adc14tovie_0(&self) -> bool {
+        *self == ADC14TOVIER::ADC14TOVIE_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14TOVIE_1`"]
+    #[inline]
+    pub fn is_adc14tovie_1(&self) -> bool {
+        *self == ADC14TOVIER::ADC14TOVIE_1
+    }
+}
+#[doc = "Possible values of the field `ADC14RDYIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14RDYIER {
+    #[doc = "Interrupt disabled"]
+    ADC14RDYIE_0,
+    #[doc = "Interrupt enabled"]
+    ADC14RDYIE_1,
+}
+impl ADC14RDYIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14RDYIER::ADC14RDYIE_0 => false,
+            ADC14RDYIER::ADC14RDYIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14RDYIER {
+        match value {
+            false => ADC14RDYIER::ADC14RDYIE_0,
+            true => ADC14RDYIER::ADC14RDYIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14RDYIE_0`"]
+    #[inline]
+    pub fn is_adc14rdyie_0(&self) -> bool {
+        *self == ADC14RDYIER::ADC14RDYIE_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14RDYIE_1`"]
+    #[inline]
+    pub fn is_adc14rdyie_1(&self) -> bool {
+        *self == ADC14RDYIER::ADC14RDYIE_1
+    }
+}
+#[doc = "Values that can be written to the field `ADC14INIE`"]
+pub enum ADC14INIEW {
+    #[doc = "Interrupt disabled"]
+    ADC14INIE_0,
+    #[doc = "Interrupt enabled"]
+    ADC14INIE_1,
+}
+impl ADC14INIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14INIEW::ADC14INIE_0 => false,
+            ADC14INIEW::ADC14INIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14INIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14INIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14INIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14inie_0(self) -> &'a mut W {
+        self.variant(ADC14INIEW::ADC14INIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14inie_1(self) -> &'a mut W {
+        self.variant(ADC14INIEW::ADC14INIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14LOIE`"]
+pub enum ADC14LOIEW {
+    #[doc = "Interrupt disabled"]
+    ADC14LOIE_0,
+    #[doc = "Interrupt enabled"]
+    ADC14LOIE_1,
+}
+impl ADC14LOIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14LOIEW::ADC14LOIE_0 => false,
+            ADC14LOIEW::ADC14LOIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14LOIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14LOIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14LOIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14loie_0(self) -> &'a mut W {
+        self.variant(ADC14LOIEW::ADC14LOIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14loie_1(self) -> &'a mut W {
+        self.variant(ADC14LOIEW::ADC14LOIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14HIIE`"]
+pub enum ADC14HIIEW {
+    #[doc = "Interrupt disabled"]
+    ADC14HIIE_0,
+    #[doc = "Interrupt enabled"]
+    ADC14HIIE_1,
+}
+impl ADC14HIIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14HIIEW::ADC14HIIE_0 => false,
+            ADC14HIIEW::ADC14HIIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14HIIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14HIIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14HIIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14hiie_0(self) -> &'a mut W {
+        self.variant(ADC14HIIEW::ADC14HIIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14hiie_1(self) -> &'a mut W {
+        self.variant(ADC14HIIEW::ADC14HIIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14OVIE`"]
+pub enum ADC14OVIEW {
+    #[doc = "Interrupt disabled"]
+    ADC14OVIE_0,
+    #[doc = "Interrupt enabled"]
+    ADC14OVIE_1,
+}
+impl ADC14OVIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14OVIEW::ADC14OVIE_0 => false,
+            ADC14OVIEW::ADC14OVIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14OVIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14OVIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14OVIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14ovie_0(self) -> &'a mut W {
+        self.variant(ADC14OVIEW::ADC14OVIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14ovie_1(self) -> &'a mut W {
+        self.variant(ADC14OVIEW::ADC14OVIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14TOVIE`"]
+pub enum ADC14TOVIEW {
+    #[doc = "Interrupt disabled"]
+    ADC14TOVIE_0,
+    #[doc = "Interrupt enabled"]
+    ADC14TOVIE_1,
+}
+impl ADC14TOVIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14TOVIEW::ADC14TOVIE_0 => false,
+            ADC14TOVIEW::ADC14TOVIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14TOVIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14TOVIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14TOVIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14tovie_0(self) -> &'a mut W {
+        self.variant(ADC14TOVIEW::ADC14TOVIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14tovie_1(self) -> &'a mut W {
+        self.variant(ADC14TOVIEW::ADC14TOVIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14RDYIE`"]
+pub enum ADC14RDYIEW {
+    #[doc = "Interrupt disabled"]
+    ADC14RDYIE_0,
+    #[doc = "Interrupt enabled"]
+    ADC14RDYIE_1,
+}
+impl ADC14RDYIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14RDYIEW::ADC14RDYIE_0 => false,
+            ADC14RDYIEW::ADC14RDYIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14RDYIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14RDYIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14RDYIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn adc14rdyie_0(self) -> &'a mut W {
+        self.variant(ADC14RDYIEW::ADC14RDYIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn adc14rdyie_1(self) -> &'a mut W {
+        self.variant(ADC14RDYIEW::ADC14RDYIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 1 - Interrupt enable for ADC14MEMx within comparator window"]
+    #[inline]
+    pub fn adc14inie(&self) -> ADC14INIER {
+        ADC14INIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - Interrupt enable for ADC14MEMx below comparator window"]
+    #[inline]
+    pub fn adc14loie(&self) -> ADC14LOIER {
+        ADC14LOIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 3 - Interrupt enable for ADC14MEMx above comparator window"]
+    #[inline]
+    pub fn adc14hiie(&self) -> ADC14HIIER {
+        ADC14HIIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 4 - ADC14MEMx overflow-interrupt enable"]
+    #[inline]
+    pub fn adc14ovie(&self) -> ADC14OVIER {
+        ADC14OVIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 5 - ADC14 conversion-time-overflow interrupt enable"]
+    #[inline]
+    pub fn adc14tovie(&self) -> ADC14TOVIER {
+        ADC14TOVIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 6 - ADC14 local buffered reference ready interrupt enable"]
+    #[inline]
+    pub fn adc14rdyie(&self) -> ADC14RDYIER {
+        ADC14RDYIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 1 - Interrupt enable for ADC14MEMx within comparator window"]
+    #[inline]
+    pub fn adc14inie(&mut self) -> _ADC14INIEW {
+        _ADC14INIEW { w: self }
+    }
+    #[doc = "Bit 2 - Interrupt enable for ADC14MEMx below comparator window"]
+    #[inline]
+    pub fn adc14loie(&mut self) -> _ADC14LOIEW {
+        _ADC14LOIEW { w: self }
+    }
+    #[doc = "Bit 3 - Interrupt enable for ADC14MEMx above comparator window"]
+    #[inline]
+    pub fn adc14hiie(&mut self) -> _ADC14HIIEW {
+        _ADC14HIIEW { w: self }
+    }
+    #[doc = "Bit 4 - ADC14MEMx overflow-interrupt enable"]
+    #[inline]
+    pub fn adc14ovie(&mut self) -> _ADC14OVIEW {
+        _ADC14OVIEW { w: self }
+    }
+    #[doc = "Bit 5 - ADC14 conversion-time-overflow interrupt enable"]
+    #[inline]
+    pub fn adc14tovie(&mut self) -> _ADC14TOVIEW {
+        _ADC14TOVIEW { w: self }
+    }
+    #[doc = "Bit 6 - ADC14 local buffered reference ready interrupt enable"]
+    #[inline]
+    pub fn adc14rdyie(&mut self) -> _ADC14RDYIEW {
+        _ADC14RDYIEW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/adc14/adc14ifgr0.rs b/example-source/msp432p401r/src/adc14/adc14ifgr0.rs
new file mode 100644
index 0000000..7f5e2b4
--- /dev/null
+++ b/example-source/msp432p401r/src/adc14/adc14ifgr0.rs
@@ -0,0 +1,1812 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::ADC14IFGR0 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG0`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG0R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG0_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG0_1,
+}
+impl ADC14IFG0R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG0R::ADC14IFG0_0 => false,
+            ADC14IFG0R::ADC14IFG0_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG0R {
+        match value {
+            false => ADC14IFG0R::ADC14IFG0_0,
+            true => ADC14IFG0R::ADC14IFG0_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG0_0`"]
+    #[inline]
+    pub fn is_adc14ifg0_0(&self) -> bool {
+        *self == ADC14IFG0R::ADC14IFG0_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG0_1`"]
+    #[inline]
+    pub fn is_adc14ifg0_1(&self) -> bool {
+        *self == ADC14IFG0R::ADC14IFG0_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG1`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG1R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG1_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG1_1,
+}
+impl ADC14IFG1R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG1R::ADC14IFG1_0 => false,
+            ADC14IFG1R::ADC14IFG1_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG1R {
+        match value {
+            false => ADC14IFG1R::ADC14IFG1_0,
+            true => ADC14IFG1R::ADC14IFG1_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG1_0`"]
+    #[inline]
+    pub fn is_adc14ifg1_0(&self) -> bool {
+        *self == ADC14IFG1R::ADC14IFG1_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG1_1`"]
+    #[inline]
+    pub fn is_adc14ifg1_1(&self) -> bool {
+        *self == ADC14IFG1R::ADC14IFG1_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG2`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG2R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG2_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG2_1,
+}
+impl ADC14IFG2R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG2R::ADC14IFG2_0 => false,
+            ADC14IFG2R::ADC14IFG2_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG2R {
+        match value {
+            false => ADC14IFG2R::ADC14IFG2_0,
+            true => ADC14IFG2R::ADC14IFG2_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG2_0`"]
+    #[inline]
+    pub fn is_adc14ifg2_0(&self) -> bool {
+        *self == ADC14IFG2R::ADC14IFG2_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG2_1`"]
+    #[inline]
+    pub fn is_adc14ifg2_1(&self) -> bool {
+        *self == ADC14IFG2R::ADC14IFG2_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG3`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG3R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG3_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG3_1,
+}
+impl ADC14IFG3R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG3R::ADC14IFG3_0 => false,
+            ADC14IFG3R::ADC14IFG3_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG3R {
+        match value {
+            false => ADC14IFG3R::ADC14IFG3_0,
+            true => ADC14IFG3R::ADC14IFG3_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG3_0`"]
+    #[inline]
+    pub fn is_adc14ifg3_0(&self) -> bool {
+        *self == ADC14IFG3R::ADC14IFG3_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG3_1`"]
+    #[inline]
+    pub fn is_adc14ifg3_1(&self) -> bool {
+        *self == ADC14IFG3R::ADC14IFG3_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG4`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG4R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG4_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG4_1,
+}
+impl ADC14IFG4R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG4R::ADC14IFG4_0 => false,
+            ADC14IFG4R::ADC14IFG4_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG4R {
+        match value {
+            false => ADC14IFG4R::ADC14IFG4_0,
+            true => ADC14IFG4R::ADC14IFG4_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG4_0`"]
+    #[inline]
+    pub fn is_adc14ifg4_0(&self) -> bool {
+        *self == ADC14IFG4R::ADC14IFG4_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG4_1`"]
+    #[inline]
+    pub fn is_adc14ifg4_1(&self) -> bool {
+        *self == ADC14IFG4R::ADC14IFG4_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG5`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG5R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG5_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG5_1,
+}
+impl ADC14IFG5R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG5R::ADC14IFG5_0 => false,
+            ADC14IFG5R::ADC14IFG5_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG5R {
+        match value {
+            false => ADC14IFG5R::ADC14IFG5_0,
+            true => ADC14IFG5R::ADC14IFG5_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG5_0`"]
+    #[inline]
+    pub fn is_adc14ifg5_0(&self) -> bool {
+        *self == ADC14IFG5R::ADC14IFG5_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG5_1`"]
+    #[inline]
+    pub fn is_adc14ifg5_1(&self) -> bool {
+        *self == ADC14IFG5R::ADC14IFG5_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG6`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG6R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG6_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG6_1,
+}
+impl ADC14IFG6R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG6R::ADC14IFG6_0 => false,
+            ADC14IFG6R::ADC14IFG6_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG6R {
+        match value {
+            false => ADC14IFG6R::ADC14IFG6_0,
+            true => ADC14IFG6R::ADC14IFG6_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG6_0`"]
+    #[inline]
+    pub fn is_adc14ifg6_0(&self) -> bool {
+        *self == ADC14IFG6R::ADC14IFG6_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG6_1`"]
+    #[inline]
+    pub fn is_adc14ifg6_1(&self) -> bool {
+        *self == ADC14IFG6R::ADC14IFG6_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG7`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG7R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG7_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG7_1,
+}
+impl ADC14IFG7R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG7R::ADC14IFG7_0 => false,
+            ADC14IFG7R::ADC14IFG7_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG7R {
+        match value {
+            false => ADC14IFG7R::ADC14IFG7_0,
+            true => ADC14IFG7R::ADC14IFG7_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG7_0`"]
+    #[inline]
+    pub fn is_adc14ifg7_0(&self) -> bool {
+        *self == ADC14IFG7R::ADC14IFG7_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG7_1`"]
+    #[inline]
+    pub fn is_adc14ifg7_1(&self) -> bool {
+        *self == ADC14IFG7R::ADC14IFG7_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG8`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG8R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG8_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG8_1,
+}
+impl ADC14IFG8R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG8R::ADC14IFG8_0 => false,
+            ADC14IFG8R::ADC14IFG8_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG8R {
+        match value {
+            false => ADC14IFG8R::ADC14IFG8_0,
+            true => ADC14IFG8R::ADC14IFG8_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG8_0`"]
+    #[inline]
+    pub fn is_adc14ifg8_0(&self) -> bool {
+        *self == ADC14IFG8R::ADC14IFG8_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG8_1`"]
+    #[inline]
+    pub fn is_adc14ifg8_1(&self) -> bool {
+        *self == ADC14IFG8R::ADC14IFG8_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG9`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG9R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG9_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG9_1,
+}
+impl ADC14IFG9R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG9R::ADC14IFG9_0 => false,
+            ADC14IFG9R::ADC14IFG9_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG9R {
+        match value {
+            false => ADC14IFG9R::ADC14IFG9_0,
+            true => ADC14IFG9R::ADC14IFG9_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG9_0`"]
+    #[inline]
+    pub fn is_adc14ifg9_0(&self) -> bool {
+        *self == ADC14IFG9R::ADC14IFG9_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG9_1`"]
+    #[inline]
+    pub fn is_adc14ifg9_1(&self) -> bool {
+        *self == ADC14IFG9R::ADC14IFG9_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG10`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG10R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG10_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG10_1,
+}
+impl ADC14IFG10R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG10R::ADC14IFG10_0 => false,
+            ADC14IFG10R::ADC14IFG10_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG10R {
+        match value {
+            false => ADC14IFG10R::ADC14IFG10_0,
+            true => ADC14IFG10R::ADC14IFG10_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG10_0`"]
+    #[inline]
+    pub fn is_adc14ifg10_0(&self) -> bool {
+        *self == ADC14IFG10R::ADC14IFG10_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG10_1`"]
+    #[inline]
+    pub fn is_adc14ifg10_1(&self) -> bool {
+        *self == ADC14IFG10R::ADC14IFG10_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG11`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG11R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG11_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG11_1,
+}
+impl ADC14IFG11R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG11R::ADC14IFG11_0 => false,
+            ADC14IFG11R::ADC14IFG11_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG11R {
+        match value {
+            false => ADC14IFG11R::ADC14IFG11_0,
+            true => ADC14IFG11R::ADC14IFG11_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG11_0`"]
+    #[inline]
+    pub fn is_adc14ifg11_0(&self) -> bool {
+        *self == ADC14IFG11R::ADC14IFG11_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG11_1`"]
+    #[inline]
+    pub fn is_adc14ifg11_1(&self) -> bool {
+        *self == ADC14IFG11R::ADC14IFG11_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG12`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG12R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG12_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG12_1,
+}
+impl ADC14IFG12R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG12R::ADC14IFG12_0 => false,
+            ADC14IFG12R::ADC14IFG12_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG12R {
+        match value {
+            false => ADC14IFG12R::ADC14IFG12_0,
+            true => ADC14IFG12R::ADC14IFG12_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG12_0`"]
+    #[inline]
+    pub fn is_adc14ifg12_0(&self) -> bool {
+        *self == ADC14IFG12R::ADC14IFG12_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG12_1`"]
+    #[inline]
+    pub fn is_adc14ifg12_1(&self) -> bool {
+        *self == ADC14IFG12R::ADC14IFG12_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG13`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG13R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG13_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG13_1,
+}
+impl ADC14IFG13R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG13R::ADC14IFG13_0 => false,
+            ADC14IFG13R::ADC14IFG13_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG13R {
+        match value {
+            false => ADC14IFG13R::ADC14IFG13_0,
+            true => ADC14IFG13R::ADC14IFG13_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG13_0`"]
+    #[inline]
+    pub fn is_adc14ifg13_0(&self) -> bool {
+        *self == ADC14IFG13R::ADC14IFG13_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG13_1`"]
+    #[inline]
+    pub fn is_adc14ifg13_1(&self) -> bool {
+        *self == ADC14IFG13R::ADC14IFG13_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG14`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG14R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG14_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG14_1,
+}
+impl ADC14IFG14R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG14R::ADC14IFG14_0 => false,
+            ADC14IFG14R::ADC14IFG14_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG14R {
+        match value {
+            false => ADC14IFG14R::ADC14IFG14_0,
+            true => ADC14IFG14R::ADC14IFG14_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG14_0`"]
+    #[inline]
+    pub fn is_adc14ifg14_0(&self) -> bool {
+        *self == ADC14IFG14R::ADC14IFG14_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG14_1`"]
+    #[inline]
+    pub fn is_adc14ifg14_1(&self) -> bool {
+        *self == ADC14IFG14R::ADC14IFG14_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG15`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG15R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG15_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG15_1,
+}
+impl ADC14IFG15R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG15R::ADC14IFG15_0 => false,
+            ADC14IFG15R::ADC14IFG15_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG15R {
+        match value {
+            false => ADC14IFG15R::ADC14IFG15_0,
+            true => ADC14IFG15R::ADC14IFG15_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG15_0`"]
+    #[inline]
+    pub fn is_adc14ifg15_0(&self) -> bool {
+        *self == ADC14IFG15R::ADC14IFG15_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG15_1`"]
+    #[inline]
+    pub fn is_adc14ifg15_1(&self) -> bool {
+        *self == ADC14IFG15R::ADC14IFG15_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG16`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG16R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG16_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG16_1,
+}
+impl ADC14IFG16R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG16R::ADC14IFG16_0 => false,
+            ADC14IFG16R::ADC14IFG16_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG16R {
+        match value {
+            false => ADC14IFG16R::ADC14IFG16_0,
+            true => ADC14IFG16R::ADC14IFG16_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG16_0`"]
+    #[inline]
+    pub fn is_adc14ifg16_0(&self) -> bool {
+        *self == ADC14IFG16R::ADC14IFG16_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG16_1`"]
+    #[inline]
+    pub fn is_adc14ifg16_1(&self) -> bool {
+        *self == ADC14IFG16R::ADC14IFG16_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG17`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG17R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG17_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG17_1,
+}
+impl ADC14IFG17R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG17R::ADC14IFG17_0 => false,
+            ADC14IFG17R::ADC14IFG17_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG17R {
+        match value {
+            false => ADC14IFG17R::ADC14IFG17_0,
+            true => ADC14IFG17R::ADC14IFG17_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG17_0`"]
+    #[inline]
+    pub fn is_adc14ifg17_0(&self) -> bool {
+        *self == ADC14IFG17R::ADC14IFG17_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG17_1`"]
+    #[inline]
+    pub fn is_adc14ifg17_1(&self) -> bool {
+        *self == ADC14IFG17R::ADC14IFG17_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG18`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG18R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG18_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG18_1,
+}
+impl ADC14IFG18R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG18R::ADC14IFG18_0 => false,
+            ADC14IFG18R::ADC14IFG18_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG18R {
+        match value {
+            false => ADC14IFG18R::ADC14IFG18_0,
+            true => ADC14IFG18R::ADC14IFG18_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG18_0`"]
+    #[inline]
+    pub fn is_adc14ifg18_0(&self) -> bool {
+        *self == ADC14IFG18R::ADC14IFG18_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG18_1`"]
+    #[inline]
+    pub fn is_adc14ifg18_1(&self) -> bool {
+        *self == ADC14IFG18R::ADC14IFG18_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG19`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG19R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG19_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG19_1,
+}
+impl ADC14IFG19R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG19R::ADC14IFG19_0 => false,
+            ADC14IFG19R::ADC14IFG19_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG19R {
+        match value {
+            false => ADC14IFG19R::ADC14IFG19_0,
+            true => ADC14IFG19R::ADC14IFG19_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG19_0`"]
+    #[inline]
+    pub fn is_adc14ifg19_0(&self) -> bool {
+        *self == ADC14IFG19R::ADC14IFG19_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG19_1`"]
+    #[inline]
+    pub fn is_adc14ifg19_1(&self) -> bool {
+        *self == ADC14IFG19R::ADC14IFG19_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG20`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG20R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG20_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG20_1,
+}
+impl ADC14IFG20R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG20R::ADC14IFG20_0 => false,
+            ADC14IFG20R::ADC14IFG20_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG20R {
+        match value {
+            false => ADC14IFG20R::ADC14IFG20_0,
+            true => ADC14IFG20R::ADC14IFG20_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG20_0`"]
+    #[inline]
+    pub fn is_adc14ifg20_0(&self) -> bool {
+        *self == ADC14IFG20R::ADC14IFG20_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG20_1`"]
+    #[inline]
+    pub fn is_adc14ifg20_1(&self) -> bool {
+        *self == ADC14IFG20R::ADC14IFG20_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG21`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG21R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG21_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG21_1,
+}
+impl ADC14IFG21R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG21R::ADC14IFG21_0 => false,
+            ADC14IFG21R::ADC14IFG21_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG21R {
+        match value {
+            false => ADC14IFG21R::ADC14IFG21_0,
+            true => ADC14IFG21R::ADC14IFG21_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG21_0`"]
+    #[inline]
+    pub fn is_adc14ifg21_0(&self) -> bool {
+        *self == ADC14IFG21R::ADC14IFG21_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG21_1`"]
+    #[inline]
+    pub fn is_adc14ifg21_1(&self) -> bool {
+        *self == ADC14IFG21R::ADC14IFG21_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG22`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG22R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG22_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG22_1,
+}
+impl ADC14IFG22R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG22R::ADC14IFG22_0 => false,
+            ADC14IFG22R::ADC14IFG22_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG22R {
+        match value {
+            false => ADC14IFG22R::ADC14IFG22_0,
+            true => ADC14IFG22R::ADC14IFG22_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG22_0`"]
+    #[inline]
+    pub fn is_adc14ifg22_0(&self) -> bool {
+        *self == ADC14IFG22R::ADC14IFG22_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG22_1`"]
+    #[inline]
+    pub fn is_adc14ifg22_1(&self) -> bool {
+        *self == ADC14IFG22R::ADC14IFG22_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG23`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG23R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG23_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG23_1,
+}
+impl ADC14IFG23R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG23R::ADC14IFG23_0 => false,
+            ADC14IFG23R::ADC14IFG23_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG23R {
+        match value {
+            false => ADC14IFG23R::ADC14IFG23_0,
+            true => ADC14IFG23R::ADC14IFG23_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG23_0`"]
+    #[inline]
+    pub fn is_adc14ifg23_0(&self) -> bool {
+        *self == ADC14IFG23R::ADC14IFG23_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG23_1`"]
+    #[inline]
+    pub fn is_adc14ifg23_1(&self) -> bool {
+        *self == ADC14IFG23R::ADC14IFG23_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG24`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG24R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG24_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG24_1,
+}
+impl ADC14IFG24R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG24R::ADC14IFG24_0 => false,
+            ADC14IFG24R::ADC14IFG24_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG24R {
+        match value {
+            false => ADC14IFG24R::ADC14IFG24_0,
+            true => ADC14IFG24R::ADC14IFG24_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG24_0`"]
+    #[inline]
+    pub fn is_adc14ifg24_0(&self) -> bool {
+        *self == ADC14IFG24R::ADC14IFG24_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG24_1`"]
+    #[inline]
+    pub fn is_adc14ifg24_1(&self) -> bool {
+        *self == ADC14IFG24R::ADC14IFG24_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG25`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG25R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG25_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG25_1,
+}
+impl ADC14IFG25R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG25R::ADC14IFG25_0 => false,
+            ADC14IFG25R::ADC14IFG25_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG25R {
+        match value {
+            false => ADC14IFG25R::ADC14IFG25_0,
+            true => ADC14IFG25R::ADC14IFG25_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG25_0`"]
+    #[inline]
+    pub fn is_adc14ifg25_0(&self) -> bool {
+        *self == ADC14IFG25R::ADC14IFG25_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG25_1`"]
+    #[inline]
+    pub fn is_adc14ifg25_1(&self) -> bool {
+        *self == ADC14IFG25R::ADC14IFG25_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG26`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG26R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG26_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG26_1,
+}
+impl ADC14IFG26R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG26R::ADC14IFG26_0 => false,
+            ADC14IFG26R::ADC14IFG26_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG26R {
+        match value {
+            false => ADC14IFG26R::ADC14IFG26_0,
+            true => ADC14IFG26R::ADC14IFG26_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG26_0`"]
+    #[inline]
+    pub fn is_adc14ifg26_0(&self) -> bool {
+        *self == ADC14IFG26R::ADC14IFG26_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG26_1`"]
+    #[inline]
+    pub fn is_adc14ifg26_1(&self) -> bool {
+        *self == ADC14IFG26R::ADC14IFG26_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG27`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG27R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG27_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG27_1,
+}
+impl ADC14IFG27R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG27R::ADC14IFG27_0 => false,
+            ADC14IFG27R::ADC14IFG27_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG27R {
+        match value {
+            false => ADC14IFG27R::ADC14IFG27_0,
+            true => ADC14IFG27R::ADC14IFG27_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG27_0`"]
+    #[inline]
+    pub fn is_adc14ifg27_0(&self) -> bool {
+        *self == ADC14IFG27R::ADC14IFG27_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG27_1`"]
+    #[inline]
+    pub fn is_adc14ifg27_1(&self) -> bool {
+        *self == ADC14IFG27R::ADC14IFG27_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG28`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG28R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG28_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG28_1,
+}
+impl ADC14IFG28R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG28R::ADC14IFG28_0 => false,
+            ADC14IFG28R::ADC14IFG28_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG28R {
+        match value {
+            false => ADC14IFG28R::ADC14IFG28_0,
+            true => ADC14IFG28R::ADC14IFG28_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG28_0`"]
+    #[inline]
+    pub fn is_adc14ifg28_0(&self) -> bool {
+        *self == ADC14IFG28R::ADC14IFG28_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG28_1`"]
+    #[inline]
+    pub fn is_adc14ifg28_1(&self) -> bool {
+        *self == ADC14IFG28R::ADC14IFG28_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG29`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG29R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG29_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG29_1,
+}
+impl ADC14IFG29R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG29R::ADC14IFG29_0 => false,
+            ADC14IFG29R::ADC14IFG29_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG29R {
+        match value {
+            false => ADC14IFG29R::ADC14IFG29_0,
+            true => ADC14IFG29R::ADC14IFG29_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG29_0`"]
+    #[inline]
+    pub fn is_adc14ifg29_0(&self) -> bool {
+        *self == ADC14IFG29R::ADC14IFG29_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG29_1`"]
+    #[inline]
+    pub fn is_adc14ifg29_1(&self) -> bool {
+        *self == ADC14IFG29R::ADC14IFG29_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG30`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG30R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG30_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG30_1,
+}
+impl ADC14IFG30R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG30R::ADC14IFG30_0 => false,
+            ADC14IFG30R::ADC14IFG30_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG30R {
+        match value {
+            false => ADC14IFG30R::ADC14IFG30_0,
+            true => ADC14IFG30R::ADC14IFG30_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG30_0`"]
+    #[inline]
+    pub fn is_adc14ifg30_0(&self) -> bool {
+        *self == ADC14IFG30R::ADC14IFG30_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG30_1`"]
+    #[inline]
+    pub fn is_adc14ifg30_1(&self) -> bool {
+        *self == ADC14IFG30R::ADC14IFG30_1
+    }
+}
+#[doc = "Possible values of the field `ADC14IFG31`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IFG31R {
+    #[doc = "No interrupt pending"]
+    ADC14IFG31_0,
+    #[doc = "Interrupt pending"]
+    ADC14IFG31_1,
+}
+impl ADC14IFG31R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14IFG31R::ADC14IFG31_0 => false,
+            ADC14IFG31R::ADC14IFG31_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14IFG31R {
+        match value {
+            false => ADC14IFG31R::ADC14IFG31_0,
+            true => ADC14IFG31R::ADC14IFG31_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG31_0`"]
+    #[inline]
+    pub fn is_adc14ifg31_0(&self) -> bool {
+        *self == ADC14IFG31R::ADC14IFG31_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IFG31_1`"]
+    #[inline]
+    pub fn is_adc14ifg31_1(&self) -> bool {
+        *self == ADC14IFG31R::ADC14IFG31_1
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - ADC14MEM0 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg0(&self) -> ADC14IFG0R {
+        ADC14IFG0R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - ADC14MEM1 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg1(&self) -> ADC14IFG1R {
+        ADC14IFG1R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - ADC14MEM2 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg2(&self) -> ADC14IFG2R {
+        ADC14IFG2R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 3 - ADC14MEM3 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg3(&self) -> ADC14IFG3R {
+        ADC14IFG3R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 4 - ADC14MEM4 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg4(&self) -> ADC14IFG4R {
+        ADC14IFG4R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 5 - ADC14MEM5 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg5(&self) -> ADC14IFG5R {
+        ADC14IFG5R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 6 - ADC14MEM6 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg6(&self) -> ADC14IFG6R {
+        ADC14IFG6R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 7 - ADC14MEM7 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg7(&self) -> ADC14IFG7R {
+        ADC14IFG7R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 8 - ADC14MEM8 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg8(&self) -> ADC14IFG8R {
+        ADC14IFG8R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 9 - ADC14MEM9 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg9(&self) -> ADC14IFG9R {
+        ADC14IFG9R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 10 - ADC14MEM10 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg10(&self) -> ADC14IFG10R {
+        ADC14IFG10R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 11 - ADC14MEM11 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg11(&self) -> ADC14IFG11R {
+        ADC14IFG11R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 12 - ADC14MEM12 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg12(&self) -> ADC14IFG12R {
+        ADC14IFG12R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 13 - ADC14MEM13 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg13(&self) -> ADC14IFG13R {
+        ADC14IFG13R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 14 - ADC14MEM14 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg14(&self) -> ADC14IFG14R {
+        ADC14IFG14R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 15 - ADC14MEM15 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg15(&self) -> ADC14IFG15R {
+        ADC14IFG15R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 16 - ADC14MEM16 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg16(&self) -> ADC14IFG16R {
+        ADC14IFG16R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 17 - ADC14MEM17 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg17(&self) -> ADC14IFG17R {
+        ADC14IFG17R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 17;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 18 - ADC14MEM18 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg18(&self) -> ADC14IFG18R {
+        ADC14IFG18R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 18;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 19 - ADC14MEM19 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg19(&self) -> ADC14IFG19R {
+        ADC14IFG19R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 19;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 20 - ADC14MEM20 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg20(&self) -> ADC14IFG20R {
+        ADC14IFG20R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 20;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 21 - ADC14MEM21 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg21(&self) -> ADC14IFG21R {
+        ADC14IFG21R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 21;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 22 - ADC14MEM22 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg22(&self) -> ADC14IFG22R {
+        ADC14IFG22R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 22;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 23 - ADC14MEM23 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg23(&self) -> ADC14IFG23R {
+        ADC14IFG23R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 23;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 24 - ADC14MEM24 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg24(&self) -> ADC14IFG24R {
+        ADC14IFG24R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 24;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 25 - ADC14MEM25 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg25(&self) -> ADC14IFG25R {
+        ADC14IFG25R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 25;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 26 - ADC14MEM26 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg26(&self) -> ADC14IFG26R {
+        ADC14IFG26R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 26;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 27 - ADC14MEM27 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg27(&self) -> ADC14IFG27R {
+        ADC14IFG27R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 27;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 28 - ADC14MEM28 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg28(&self) -> ADC14IFG28R {
+        ADC14IFG28R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 28;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 29 - ADC14MEM29 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg29(&self) -> ADC14IFG29R {
+        ADC14IFG29R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 29;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 30 - ADC14MEM30 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg30(&self) -> ADC14IFG30R {
+        ADC14IFG30R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 30;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 31 - ADC14MEM31 interrupt flag"]
+    #[inline]
+    pub fn adc14ifg31(&self) -> ADC14IFG31R {
+        ADC14IFG31R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 31;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/adc14/adc14ifgr1.rs b/example-source/msp432p401r/src/adc14/adc14ifgr1.rs
new file mode 100644
index 0000000..be0f9cf
--- /dev/null
+++ b/example-source/msp432p401r/src/adc14/adc14ifgr1.rs
@@ -0,0 +1,356 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::ADC14IFGR1 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `ADC14INIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14INIFGR {
+    #[doc = "No interrupt pending"]
+    ADC14INIFG_0,
+    #[doc = "Interrupt pending"]
+    ADC14INIFG_1,
+}
+impl ADC14INIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14INIFGR::ADC14INIFG_0 => false,
+            ADC14INIFGR::ADC14INIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14INIFGR {
+        match value {
+            false => ADC14INIFGR::ADC14INIFG_0,
+            true => ADC14INIFGR::ADC14INIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14INIFG_0`"]
+    #[inline]
+    pub fn is_adc14inifg_0(&self) -> bool {
+        *self == ADC14INIFGR::ADC14INIFG_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14INIFG_1`"]
+    #[inline]
+    pub fn is_adc14inifg_1(&self) -> bool {
+        *self == ADC14INIFGR::ADC14INIFG_1
+    }
+}
+#[doc = "Possible values of the field `ADC14LOIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14LOIFGR {
+    #[doc = "No interrupt pending"]
+    ADC14LOIFG_0,
+    #[doc = "Interrupt pending"]
+    ADC14LOIFG_1,
+}
+impl ADC14LOIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14LOIFGR::ADC14LOIFG_0 => false,
+            ADC14LOIFGR::ADC14LOIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14LOIFGR {
+        match value {
+            false => ADC14LOIFGR::ADC14LOIFG_0,
+            true => ADC14LOIFGR::ADC14LOIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14LOIFG_0`"]
+    #[inline]
+    pub fn is_adc14loifg_0(&self) -> bool {
+        *self == ADC14LOIFGR::ADC14LOIFG_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14LOIFG_1`"]
+    #[inline]
+    pub fn is_adc14loifg_1(&self) -> bool {
+        *self == ADC14LOIFGR::ADC14LOIFG_1
+    }
+}
+#[doc = "Possible values of the field `ADC14HIIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14HIIFGR {
+    #[doc = "No interrupt pending"]
+    ADC14HIIFG_0,
+    #[doc = "Interrupt pending"]
+    ADC14HIIFG_1,
+}
+impl ADC14HIIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14HIIFGR::ADC14HIIFG_0 => false,
+            ADC14HIIFGR::ADC14HIIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14HIIFGR {
+        match value {
+            false => ADC14HIIFGR::ADC14HIIFG_0,
+            true => ADC14HIIFGR::ADC14HIIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14HIIFG_0`"]
+    #[inline]
+    pub fn is_adc14hiifg_0(&self) -> bool {
+        *self == ADC14HIIFGR::ADC14HIIFG_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14HIIFG_1`"]
+    #[inline]
+    pub fn is_adc14hiifg_1(&self) -> bool {
+        *self == ADC14HIIFGR::ADC14HIIFG_1
+    }
+}
+#[doc = "Possible values of the field `ADC14OVIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14OVIFGR {
+    #[doc = "No interrupt pending"]
+    ADC14OVIFG_0,
+    #[doc = "Interrupt pending"]
+    ADC14OVIFG_1,
+}
+impl ADC14OVIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14OVIFGR::ADC14OVIFG_0 => false,
+            ADC14OVIFGR::ADC14OVIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14OVIFGR {
+        match value {
+            false => ADC14OVIFGR::ADC14OVIFG_0,
+            true => ADC14OVIFGR::ADC14OVIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14OVIFG_0`"]
+    #[inline]
+    pub fn is_adc14ovifg_0(&self) -> bool {
+        *self == ADC14OVIFGR::ADC14OVIFG_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14OVIFG_1`"]
+    #[inline]
+    pub fn is_adc14ovifg_1(&self) -> bool {
+        *self == ADC14OVIFGR::ADC14OVIFG_1
+    }
+}
+#[doc = "Possible values of the field `ADC14TOVIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14TOVIFGR {
+    #[doc = "No interrupt pending"]
+    ADC14TOVIFG_0,
+    #[doc = "Interrupt pending"]
+    ADC14TOVIFG_1,
+}
+impl ADC14TOVIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14TOVIFGR::ADC14TOVIFG_0 => false,
+            ADC14TOVIFGR::ADC14TOVIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14TOVIFGR {
+        match value {
+            false => ADC14TOVIFGR::ADC14TOVIFG_0,
+            true => ADC14TOVIFGR::ADC14TOVIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14TOVIFG_0`"]
+    #[inline]
+    pub fn is_adc14tovifg_0(&self) -> bool {
+        *self == ADC14TOVIFGR::ADC14TOVIFG_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14TOVIFG_1`"]
+    #[inline]
+    pub fn is_adc14tovifg_1(&self) -> bool {
+        *self == ADC14TOVIFGR::ADC14TOVIFG_1
+    }
+}
+#[doc = "Possible values of the field `ADC14RDYIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14RDYIFGR {
+    #[doc = "No interrupt pending"]
+    ADC14RDYIFG_0,
+    #[doc = "Interrupt pending"]
+    ADC14RDYIFG_1,
+}
+impl ADC14RDYIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14RDYIFGR::ADC14RDYIFG_0 => false,
+            ADC14RDYIFGR::ADC14RDYIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14RDYIFGR {
+        match value {
+            false => ADC14RDYIFGR::ADC14RDYIFG_0,
+            true => ADC14RDYIFGR::ADC14RDYIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14RDYIFG_0`"]
+    #[inline]
+    pub fn is_adc14rdyifg_0(&self) -> bool {
+        *self == ADC14RDYIFGR::ADC14RDYIFG_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14RDYIFG_1`"]
+    #[inline]
+    pub fn is_adc14rdyifg_1(&self) -> bool {
+        *self == ADC14RDYIFGR::ADC14RDYIFG_1
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 1 - Interrupt flag for ADC14MEMx within comparator window"]
+    #[inline]
+    pub fn adc14inifg(&self) -> ADC14INIFGR {
+        ADC14INIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - Interrupt flag for ADC14MEMx below comparator window"]
+    #[inline]
+    pub fn adc14loifg(&self) -> ADC14LOIFGR {
+        ADC14LOIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 3 - Interrupt flag for ADC14MEMx above comparator window"]
+    #[inline]
+    pub fn adc14hiifg(&self) -> ADC14HIIFGR {
+        ADC14HIIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 4 - ADC14MEMx overflow interrupt flag"]
+    #[inline]
+    pub fn adc14ovifg(&self) -> ADC14OVIFGR {
+        ADC14OVIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 5 - ADC14 conversion time overflow interrupt flag"]
+    #[inline]
+    pub fn adc14tovifg(&self) -> ADC14TOVIFGR {
+        ADC14TOVIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 6 - ADC14 local buffered reference ready interrupt flag"]
+    #[inline]
+    pub fn adc14rdyifg(&self) -> ADC14RDYIFGR {
+        ADC14RDYIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/adc14/adc14iv.rs b/example-source/msp432p401r/src/adc14/adc14iv.rs
new file mode 100644
index 0000000..fb98fb6
--- /dev/null
+++ b/example-source/msp432p401r/src/adc14/adc14iv.rs
@@ -0,0 +1,796 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::ADC14IV {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `ADC14IV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14IVR {
+    #[doc = "No interrupt pending"]
+    ADC14IV_0,
+    #[doc = "Interrupt Source: ADC14MEMx overflow; Interrupt Flag: ADC14OVIFG; Interrupt Priority: Highest"]
+    ADC14IV_2,
+    #[doc = "Interrupt Source: Conversion time overflow; Interrupt Flag: ADC14TOVIFG"]
+    ADC14IV_4,
+    #[doc = "Interrupt Source: ADC14 window high interrupt flag; Interrupt Flag: ADC14HIIFG"]
+    ADC14IV_6,
+    #[doc = "Interrupt Source: ADC14 window low interrupt flag; Interrupt Flag: ADC14LOIFG"]
+    ADC14IV_8,
+    #[doc = "Interrupt Source: ADC14 in-window interrupt flag; Interrupt Flag: ADC14INIFG"]
+    ADC14IV_10,
+    #[doc = "Interrupt Source: ADC14MEM0 interrupt flag; Interrupt Flag: ADC14IFG0"]
+    ADC14IV_12,
+    #[doc = "Interrupt Source: ADC14MEM1 interrupt flag; Interrupt Flag: ADC14IFG1"]
+    ADC14IV_14,
+    #[doc = "Interrupt Source: ADC14MEM2 interrupt flag; Interrupt Flag: ADC14IFG2"]
+    ADC14IV_16,
+    #[doc = "Interrupt Source: ADC14MEM3 interrupt flag; Interrupt Flag: ADC14IFG3"]
+    ADC14IV_18,
+    #[doc = "Interrupt Source: ADC14MEM4 interrupt flag; Interrupt Flag: ADC14IFG4"]
+    ADC14IV_20,
+    #[doc = "Interrupt Source: ADC14MEM5 interrupt flag; Interrupt Flag: ADC14IFG5"]
+    ADC14IV_22,
+    #[doc = "Interrupt Source: ADC14MEM6 interrupt flag; Interrupt Flag: ADC14IFG6"]
+    ADC14IV_24,
+    #[doc = "Interrupt Source: ADC14MEM7 interrupt flag; Interrupt Flag: ADC14IFG7"]
+    ADC14IV_26,
+    #[doc = "Interrupt Source: ADC14MEM8 interrupt flag; Interrupt Flag: ADC14IFG8"]
+    ADC14IV_28,
+    #[doc = "Interrupt Source: ADC14MEM9 interrupt flag; Interrupt Flag: ADC14IFG9"]
+    ADC14IV_30,
+    #[doc = "Interrupt Source: ADC14MEM10 interrupt flag; Interrupt Flag: ADC14IFG10"]
+    ADC14IV_32,
+    #[doc = "Interrupt Source: ADC14MEM11 interrupt flag; Interrupt Flag: ADC14IFG11"]
+    ADC14IV_34,
+    #[doc = "Interrupt Source: ADC14MEM12 interrupt flag; Interrupt Flag: ADC14IFG12"]
+    ADC14IV_36,
+    #[doc = "Interrupt Source: ADC14MEM13 interrupt flag; Interrupt Flag: ADC14IFG13"]
+    ADC14IV_38,
+    #[doc = "Interrupt Source: ADC14MEM14 interrupt flag; Interrupt Flag: ADC14IFG14"]
+    ADC14IV_40,
+    #[doc = "Interrupt Source: ADC14MEM15 interrupt flag; Interrupt Flag: ADC14IFG15"]
+    ADC14IV_42,
+    #[doc = "Interrupt Source: ADC14MEM16 interrupt flag; Interrupt Flag: ADC14IFG16"]
+    ADC14IV_44,
+    #[doc = "Interrupt Source: ADC14MEM17 interrupt flag; Interrupt Flag: ADC14IFG17"]
+    ADC14IV_46,
+    #[doc = "Interrupt Source: ADC14MEM18 interrupt flag; Interrupt Flag: ADC14IFG18"]
+    ADC14IV_48,
+    #[doc = "Interrupt Source: ADC14MEM19 interrupt flag; Interrupt Flag: ADC14IFG19"]
+    ADC14IV_50,
+    #[doc = "Interrupt Source: ADC14MEM20 interrupt flag; Interrupt Flag: ADC14IFG20"]
+    ADC14IV_52,
+    #[doc = "Interrupt Source: ADC14MEM22 interrupt flag; Interrupt Flag: ADC14IFG22"]
+    ADC14IV_54,
+    #[doc = "Interrupt Source: ADC14MEM22 interrupt flag; Interrupt Flag: ADC14IFG22"]
+    ADC14IV_56,
+    #[doc = "Interrupt Source: ADC14MEM23 interrupt flag; Interrupt Flag: ADC14IFG23"]
+    ADC14IV_58,
+    #[doc = "Interrupt Source: ADC14MEM24 interrupt flag; Interrupt Flag: ADC14IFG24"]
+    ADC14IV_60,
+    #[doc = "Interrupt Source: ADC14MEM25 interrupt flag; Interrupt Flag: ADC14IFG25"]
+    ADC14IV_62,
+    #[doc = "Interrupt Source: ADC14MEM26 interrupt flag; Interrupt Flag: ADC14IFG26"]
+    ADC14IV_64,
+    #[doc = "Interrupt Source: ADC14MEM27 interrupt flag; Interrupt Flag: ADC14IFG27"]
+    ADC14IV_66,
+    #[doc = "Interrupt Source: ADC14MEM28 interrupt flag; Interrupt Flag: ADC14IFG28"]
+    ADC14IV_68,
+    #[doc = "Interrupt Source: ADC14MEM29 interrupt flag; Interrupt Flag: ADC14IFG29"]
+    ADC14IV_70,
+    #[doc = "Interrupt Source: ADC14MEM30 interrupt flag; Interrupt Flag: ADC14IFG30"]
+    ADC14IV_72,
+    #[doc = "Interrupt Source: ADC14MEM31 interrupt flag; Interrupt Flag: ADC14IFG31"]
+    ADC14IV_74,
+    #[doc = "Interrupt Source: ADC14RDYIFG interrupt flag; Interrupt Flag: ADC14RDYIFG; Interrupt Priority: Lowest"]
+    ADC14IV_76,
+    #[doc = r" Reserved"]
+    _Reserved(u32),
+}
+impl ADC14IVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        match *self {
+            ADC14IVR::ADC14IV_0 => 0,
+            ADC14IVR::ADC14IV_2 => 2,
+            ADC14IVR::ADC14IV_4 => 4,
+            ADC14IVR::ADC14IV_6 => 6,
+            ADC14IVR::ADC14IV_8 => 8,
+            ADC14IVR::ADC14IV_10 => 10,
+            ADC14IVR::ADC14IV_12 => 12,
+            ADC14IVR::ADC14IV_14 => 14,
+            ADC14IVR::ADC14IV_16 => 16,
+            ADC14IVR::ADC14IV_18 => 18,
+            ADC14IVR::ADC14IV_20 => 20,
+            ADC14IVR::ADC14IV_22 => 22,
+            ADC14IVR::ADC14IV_24 => 24,
+            ADC14IVR::ADC14IV_26 => 26,
+            ADC14IVR::ADC14IV_28 => 28,
+            ADC14IVR::ADC14IV_30 => 30,
+            ADC14IVR::ADC14IV_32 => 32,
+            ADC14IVR::ADC14IV_34 => 34,
+            ADC14IVR::ADC14IV_36 => 36,
+            ADC14IVR::ADC14IV_38 => 38,
+            ADC14IVR::ADC14IV_40 => 40,
+            ADC14IVR::ADC14IV_42 => 42,
+            ADC14IVR::ADC14IV_44 => 44,
+            ADC14IVR::ADC14IV_46 => 46,
+            ADC14IVR::ADC14IV_48 => 48,
+            ADC14IVR::ADC14IV_50 => 50,
+            ADC14IVR::ADC14IV_52 => 52,
+            ADC14IVR::ADC14IV_54 => 54,
+            ADC14IVR::ADC14IV_56 => 56,
+            ADC14IVR::ADC14IV_58 => 58,
+            ADC14IVR::ADC14IV_60 => 60,
+            ADC14IVR::ADC14IV_62 => 62,
+            ADC14IVR::ADC14IV_64 => 64,
+            ADC14IVR::ADC14IV_66 => 66,
+            ADC14IVR::ADC14IV_68 => 68,
+            ADC14IVR::ADC14IV_70 => 70,
+            ADC14IVR::ADC14IV_72 => 72,
+            ADC14IVR::ADC14IV_74 => 74,
+            ADC14IVR::ADC14IV_76 => 76,
+            ADC14IVR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u32) -> ADC14IVR {
+        match value {
+            0 => ADC14IVR::ADC14IV_0,
+            2 => ADC14IVR::ADC14IV_2,
+            4 => ADC14IVR::ADC14IV_4,
+            6 => ADC14IVR::ADC14IV_6,
+            8 => ADC14IVR::ADC14IV_8,
+            10 => ADC14IVR::ADC14IV_10,
+            12 => ADC14IVR::ADC14IV_12,
+            14 => ADC14IVR::ADC14IV_14,
+            16 => ADC14IVR::ADC14IV_16,
+            18 => ADC14IVR::ADC14IV_18,
+            20 => ADC14IVR::ADC14IV_20,
+            22 => ADC14IVR::ADC14IV_22,
+            24 => ADC14IVR::ADC14IV_24,
+            26 => ADC14IVR::ADC14IV_26,
+            28 => ADC14IVR::ADC14IV_28,
+            30 => ADC14IVR::ADC14IV_30,
+            32 => ADC14IVR::ADC14IV_32,
+            34 => ADC14IVR::ADC14IV_34,
+            36 => ADC14IVR::ADC14IV_36,
+            38 => ADC14IVR::ADC14IV_38,
+            40 => ADC14IVR::ADC14IV_40,
+            42 => ADC14IVR::ADC14IV_42,
+            44 => ADC14IVR::ADC14IV_44,
+            46 => ADC14IVR::ADC14IV_46,
+            48 => ADC14IVR::ADC14IV_48,
+            50 => ADC14IVR::ADC14IV_50,
+            52 => ADC14IVR::ADC14IV_52,
+            54 => ADC14IVR::ADC14IV_54,
+            56 => ADC14IVR::ADC14IV_56,
+            58 => ADC14IVR::ADC14IV_58,
+            60 => ADC14IVR::ADC14IV_60,
+            62 => ADC14IVR::ADC14IV_62,
+            64 => ADC14IVR::ADC14IV_64,
+            66 => ADC14IVR::ADC14IV_66,
+            68 => ADC14IVR::ADC14IV_68,
+            70 => ADC14IVR::ADC14IV_70,
+            72 => ADC14IVR::ADC14IV_72,
+            74 => ADC14IVR::ADC14IV_74,
+            76 => ADC14IVR::ADC14IV_76,
+            i => ADC14IVR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_0`"]
+    #[inline]
+    pub fn is_adc14iv_0(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_2`"]
+    #[inline]
+    pub fn is_adc14iv_2(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_2
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_4`"]
+    #[inline]
+    pub fn is_adc14iv_4(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_4
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_6`"]
+    #[inline]
+    pub fn is_adc14iv_6(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_6
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_8`"]
+    #[inline]
+    pub fn is_adc14iv_8(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_8
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_10`"]
+    #[inline]
+    pub fn is_adc14iv_10(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_10
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_12`"]
+    #[inline]
+    pub fn is_adc14iv_12(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_12
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_14`"]
+    #[inline]
+    pub fn is_adc14iv_14(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_14
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_16`"]
+    #[inline]
+    pub fn is_adc14iv_16(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_16
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_18`"]
+    #[inline]
+    pub fn is_adc14iv_18(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_18
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_20`"]
+    #[inline]
+    pub fn is_adc14iv_20(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_20
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_22`"]
+    #[inline]
+    pub fn is_adc14iv_22(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_22
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_24`"]
+    #[inline]
+    pub fn is_adc14iv_24(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_24
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_26`"]
+    #[inline]
+    pub fn is_adc14iv_26(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_26
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_28`"]
+    #[inline]
+    pub fn is_adc14iv_28(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_28
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_30`"]
+    #[inline]
+    pub fn is_adc14iv_30(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_30
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_32`"]
+    #[inline]
+    pub fn is_adc14iv_32(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_32
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_34`"]
+    #[inline]
+    pub fn is_adc14iv_34(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_34
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_36`"]
+    #[inline]
+    pub fn is_adc14iv_36(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_36
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_38`"]
+    #[inline]
+    pub fn is_adc14iv_38(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_38
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_40`"]
+    #[inline]
+    pub fn is_adc14iv_40(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_40
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_42`"]
+    #[inline]
+    pub fn is_adc14iv_42(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_42
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_44`"]
+    #[inline]
+    pub fn is_adc14iv_44(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_44
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_46`"]
+    #[inline]
+    pub fn is_adc14iv_46(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_46
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_48`"]
+    #[inline]
+    pub fn is_adc14iv_48(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_48
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_50`"]
+    #[inline]
+    pub fn is_adc14iv_50(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_50
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_52`"]
+    #[inline]
+    pub fn is_adc14iv_52(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_52
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_54`"]
+    #[inline]
+    pub fn is_adc14iv_54(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_54
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_56`"]
+    #[inline]
+    pub fn is_adc14iv_56(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_56
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_58`"]
+    #[inline]
+    pub fn is_adc14iv_58(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_58
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_60`"]
+    #[inline]
+    pub fn is_adc14iv_60(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_60
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_62`"]
+    #[inline]
+    pub fn is_adc14iv_62(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_62
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_64`"]
+    #[inline]
+    pub fn is_adc14iv_64(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_64
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_66`"]
+    #[inline]
+    pub fn is_adc14iv_66(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_66
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_68`"]
+    #[inline]
+    pub fn is_adc14iv_68(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_68
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_70`"]
+    #[inline]
+    pub fn is_adc14iv_70(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_70
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_72`"]
+    #[inline]
+    pub fn is_adc14iv_72(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_72
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_74`"]
+    #[inline]
+    pub fn is_adc14iv_74(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_74
+    }
+    #[doc = "Checks if the value of the field is `ADC14IV_76`"]
+    #[inline]
+    pub fn is_adc14iv_76(&self) -> bool {
+        *self == ADC14IVR::ADC14IV_76
+    }
+}
+#[doc = "Values that can be written to the field `ADC14IV`"]
+pub enum ADC14IVW {
+    #[doc = "No interrupt pending"]
+    ADC14IV_0,
+    #[doc = "Interrupt Source: ADC14MEMx overflow; Interrupt Flag: ADC14OVIFG; Interrupt Priority: Highest"]
+    ADC14IV_2,
+    #[doc = "Interrupt Source: Conversion time overflow; Interrupt Flag: ADC14TOVIFG"]
+    ADC14IV_4,
+    #[doc = "Interrupt Source: ADC14 window high interrupt flag; Interrupt Flag: ADC14HIIFG"]
+    ADC14IV_6,
+    #[doc = "Interrupt Source: ADC14 window low interrupt flag; Interrupt Flag: ADC14LOIFG"]
+    ADC14IV_8,
+    #[doc = "Interrupt Source: ADC14 in-window interrupt flag; Interrupt Flag: ADC14INIFG"]
+    ADC14IV_10,
+    #[doc = "Interrupt Source: ADC14MEM0 interrupt flag; Interrupt Flag: ADC14IFG0"]
+    ADC14IV_12,
+    #[doc = "Interrupt Source: ADC14MEM1 interrupt flag; Interrupt Flag: ADC14IFG1"]
+    ADC14IV_14,
+    #[doc = "Interrupt Source: ADC14MEM2 interrupt flag; Interrupt Flag: ADC14IFG2"]
+    ADC14IV_16,
+    #[doc = "Interrupt Source: ADC14MEM3 interrupt flag; Interrupt Flag: ADC14IFG3"]
+    ADC14IV_18,
+    #[doc = "Interrupt Source: ADC14MEM4 interrupt flag; Interrupt Flag: ADC14IFG4"]
+    ADC14IV_20,
+    #[doc = "Interrupt Source: ADC14MEM5 interrupt flag; Interrupt Flag: ADC14IFG5"]
+    ADC14IV_22,
+    #[doc = "Interrupt Source: ADC14MEM6 interrupt flag; Interrupt Flag: ADC14IFG6"]
+    ADC14IV_24,
+    #[doc = "Interrupt Source: ADC14MEM7 interrupt flag; Interrupt Flag: ADC14IFG7"]
+    ADC14IV_26,
+    #[doc = "Interrupt Source: ADC14MEM8 interrupt flag; Interrupt Flag: ADC14IFG8"]
+    ADC14IV_28,
+    #[doc = "Interrupt Source: ADC14MEM9 interrupt flag; Interrupt Flag: ADC14IFG9"]
+    ADC14IV_30,
+    #[doc = "Interrupt Source: ADC14MEM10 interrupt flag; Interrupt Flag: ADC14IFG10"]
+    ADC14IV_32,
+    #[doc = "Interrupt Source: ADC14MEM11 interrupt flag; Interrupt Flag: ADC14IFG11"]
+    ADC14IV_34,
+    #[doc = "Interrupt Source: ADC14MEM12 interrupt flag; Interrupt Flag: ADC14IFG12"]
+    ADC14IV_36,
+    #[doc = "Interrupt Source: ADC14MEM13 interrupt flag; Interrupt Flag: ADC14IFG13"]
+    ADC14IV_38,
+    #[doc = "Interrupt Source: ADC14MEM14 interrupt flag; Interrupt Flag: ADC14IFG14"]
+    ADC14IV_40,
+    #[doc = "Interrupt Source: ADC14MEM15 interrupt flag; Interrupt Flag: ADC14IFG15"]
+    ADC14IV_42,
+    #[doc = "Interrupt Source: ADC14MEM16 interrupt flag; Interrupt Flag: ADC14IFG16"]
+    ADC14IV_44,
+    #[doc = "Interrupt Source: ADC14MEM17 interrupt flag; Interrupt Flag: ADC14IFG17"]
+    ADC14IV_46,
+    #[doc = "Interrupt Source: ADC14MEM18 interrupt flag; Interrupt Flag: ADC14IFG18"]
+    ADC14IV_48,
+    #[doc = "Interrupt Source: ADC14MEM19 interrupt flag; Interrupt Flag: ADC14IFG19"]
+    ADC14IV_50,
+    #[doc = "Interrupt Source: ADC14MEM20 interrupt flag; Interrupt Flag: ADC14IFG20"]
+    ADC14IV_52,
+    #[doc = "Interrupt Source: ADC14MEM22 interrupt flag; Interrupt Flag: ADC14IFG22"]
+    ADC14IV_54,
+    #[doc = "Interrupt Source: ADC14MEM22 interrupt flag; Interrupt Flag: ADC14IFG22"]
+    ADC14IV_56,
+    #[doc = "Interrupt Source: ADC14MEM23 interrupt flag; Interrupt Flag: ADC14IFG23"]
+    ADC14IV_58,
+    #[doc = "Interrupt Source: ADC14MEM24 interrupt flag; Interrupt Flag: ADC14IFG24"]
+    ADC14IV_60,
+    #[doc = "Interrupt Source: ADC14MEM25 interrupt flag; Interrupt Flag: ADC14IFG25"]
+    ADC14IV_62,
+    #[doc = "Interrupt Source: ADC14MEM26 interrupt flag; Interrupt Flag: ADC14IFG26"]
+    ADC14IV_64,
+    #[doc = "Interrupt Source: ADC14MEM27 interrupt flag; Interrupt Flag: ADC14IFG27"]
+    ADC14IV_66,
+    #[doc = "Interrupt Source: ADC14MEM28 interrupt flag; Interrupt Flag: ADC14IFG28"]
+    ADC14IV_68,
+    #[doc = "Interrupt Source: ADC14MEM29 interrupt flag; Interrupt Flag: ADC14IFG29"]
+    ADC14IV_70,
+    #[doc = "Interrupt Source: ADC14MEM30 interrupt flag; Interrupt Flag: ADC14IFG30"]
+    ADC14IV_72,
+    #[doc = "Interrupt Source: ADC14MEM31 interrupt flag; Interrupt Flag: ADC14IFG31"]
+    ADC14IV_74,
+    #[doc = "Interrupt Source: ADC14RDYIFG interrupt flag; Interrupt Flag: ADC14RDYIFG; Interrupt Priority: Lowest"]
+    ADC14IV_76,
+}
+impl ADC14IVW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u32 {
+        match *self {
+            ADC14IVW::ADC14IV_0 => 0,
+            ADC14IVW::ADC14IV_2 => 2,
+            ADC14IVW::ADC14IV_4 => 4,
+            ADC14IVW::ADC14IV_6 => 6,
+            ADC14IVW::ADC14IV_8 => 8,
+            ADC14IVW::ADC14IV_10 => 10,
+            ADC14IVW::ADC14IV_12 => 12,
+            ADC14IVW::ADC14IV_14 => 14,
+            ADC14IVW::ADC14IV_16 => 16,
+            ADC14IVW::ADC14IV_18 => 18,
+            ADC14IVW::ADC14IV_20 => 20,
+            ADC14IVW::ADC14IV_22 => 22,
+            ADC14IVW::ADC14IV_24 => 24,
+            ADC14IVW::ADC14IV_26 => 26,
+            ADC14IVW::ADC14IV_28 => 28,
+            ADC14IVW::ADC14IV_30 => 30,
+            ADC14IVW::ADC14IV_32 => 32,
+            ADC14IVW::ADC14IV_34 => 34,
+            ADC14IVW::ADC14IV_36 => 36,
+            ADC14IVW::ADC14IV_38 => 38,
+            ADC14IVW::ADC14IV_40 => 40,
+            ADC14IVW::ADC14IV_42 => 42,
+            ADC14IVW::ADC14IV_44 => 44,
+            ADC14IVW::ADC14IV_46 => 46,
+            ADC14IVW::ADC14IV_48 => 48,
+            ADC14IVW::ADC14IV_50 => 50,
+            ADC14IVW::ADC14IV_52 => 52,
+            ADC14IVW::ADC14IV_54 => 54,
+            ADC14IVW::ADC14IV_56 => 56,
+            ADC14IVW::ADC14IV_58 => 58,
+            ADC14IVW::ADC14IV_60 => 60,
+            ADC14IVW::ADC14IV_62 => 62,
+            ADC14IVW::ADC14IV_64 => 64,
+            ADC14IVW::ADC14IV_66 => 66,
+            ADC14IVW::ADC14IV_68 => 68,
+            ADC14IVW::ADC14IV_70 => 70,
+            ADC14IVW::ADC14IV_72 => 72,
+            ADC14IVW::ADC14IV_74 => 74,
+            ADC14IVW::ADC14IV_76 => 76,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14IVW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14IVW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14IVW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn adc14iv_0(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_0)
+    }
+    #[doc = "Interrupt Source: ADC14MEMx overflow; Interrupt Flag: ADC14OVIFG; Interrupt Priority: Highest"]
+    #[inline]
+    pub fn adc14iv_2(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_2)
+    }
+    #[doc = "Interrupt Source: Conversion time overflow; Interrupt Flag: ADC14TOVIFG"]
+    #[inline]
+    pub fn adc14iv_4(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_4)
+    }
+    #[doc = "Interrupt Source: ADC14 window high interrupt flag; Interrupt Flag: ADC14HIIFG"]
+    #[inline]
+    pub fn adc14iv_6(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_6)
+    }
+    #[doc = "Interrupt Source: ADC14 window low interrupt flag; Interrupt Flag: ADC14LOIFG"]
+    #[inline]
+    pub fn adc14iv_8(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_8)
+    }
+    #[doc = "Interrupt Source: ADC14 in-window interrupt flag; Interrupt Flag: ADC14INIFG"]
+    #[inline]
+    pub fn adc14iv_10(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_10)
+    }
+    #[doc = "Interrupt Source: ADC14MEM0 interrupt flag; Interrupt Flag: ADC14IFG0"]
+    #[inline]
+    pub fn adc14iv_12(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_12)
+    }
+    #[doc = "Interrupt Source: ADC14MEM1 interrupt flag; Interrupt Flag: ADC14IFG1"]
+    #[inline]
+    pub fn adc14iv_14(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_14)
+    }
+    #[doc = "Interrupt Source: ADC14MEM2 interrupt flag; Interrupt Flag: ADC14IFG2"]
+    #[inline]
+    pub fn adc14iv_16(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_16)
+    }
+    #[doc = "Interrupt Source: ADC14MEM3 interrupt flag; Interrupt Flag: ADC14IFG3"]
+    #[inline]
+    pub fn adc14iv_18(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_18)
+    }
+    #[doc = "Interrupt Source: ADC14MEM4 interrupt flag; Interrupt Flag: ADC14IFG4"]
+    #[inline]
+    pub fn adc14iv_20(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_20)
+    }
+    #[doc = "Interrupt Source: ADC14MEM5 interrupt flag; Interrupt Flag: ADC14IFG5"]
+    #[inline]
+    pub fn adc14iv_22(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_22)
+    }
+    #[doc = "Interrupt Source: ADC14MEM6 interrupt flag; Interrupt Flag: ADC14IFG6"]
+    #[inline]
+    pub fn adc14iv_24(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_24)
+    }
+    #[doc = "Interrupt Source: ADC14MEM7 interrupt flag; Interrupt Flag: ADC14IFG7"]
+    #[inline]
+    pub fn adc14iv_26(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_26)
+    }
+    #[doc = "Interrupt Source: ADC14MEM8 interrupt flag; Interrupt Flag: ADC14IFG8"]
+    #[inline]
+    pub fn adc14iv_28(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_28)
+    }
+    #[doc = "Interrupt Source: ADC14MEM9 interrupt flag; Interrupt Flag: ADC14IFG9"]
+    #[inline]
+    pub fn adc14iv_30(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_30)
+    }
+    #[doc = "Interrupt Source: ADC14MEM10 interrupt flag; Interrupt Flag: ADC14IFG10"]
+    #[inline]
+    pub fn adc14iv_32(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_32)
+    }
+    #[doc = "Interrupt Source: ADC14MEM11 interrupt flag; Interrupt Flag: ADC14IFG11"]
+    #[inline]
+    pub fn adc14iv_34(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_34)
+    }
+    #[doc = "Interrupt Source: ADC14MEM12 interrupt flag; Interrupt Flag: ADC14IFG12"]
+    #[inline]
+    pub fn adc14iv_36(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_36)
+    }
+    #[doc = "Interrupt Source: ADC14MEM13 interrupt flag; Interrupt Flag: ADC14IFG13"]
+    #[inline]
+    pub fn adc14iv_38(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_38)
+    }
+    #[doc = "Interrupt Source: ADC14MEM14 interrupt flag; Interrupt Flag: ADC14IFG14"]
+    #[inline]
+    pub fn adc14iv_40(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_40)
+    }
+    #[doc = "Interrupt Source: ADC14MEM15 interrupt flag; Interrupt Flag: ADC14IFG15"]
+    #[inline]
+    pub fn adc14iv_42(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_42)
+    }
+    #[doc = "Interrupt Source: ADC14MEM16 interrupt flag; Interrupt Flag: ADC14IFG16"]
+    #[inline]
+    pub fn adc14iv_44(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_44)
+    }
+    #[doc = "Interrupt Source: ADC14MEM17 interrupt flag; Interrupt Flag: ADC14IFG17"]
+    #[inline]
+    pub fn adc14iv_46(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_46)
+    }
+    #[doc = "Interrupt Source: ADC14MEM18 interrupt flag; Interrupt Flag: ADC14IFG18"]
+    #[inline]
+    pub fn adc14iv_48(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_48)
+    }
+    #[doc = "Interrupt Source: ADC14MEM19 interrupt flag; Interrupt Flag: ADC14IFG19"]
+    #[inline]
+    pub fn adc14iv_50(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_50)
+    }
+    #[doc = "Interrupt Source: ADC14MEM20 interrupt flag; Interrupt Flag: ADC14IFG20"]
+    #[inline]
+    pub fn adc14iv_52(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_52)
+    }
+    #[doc = "Interrupt Source: ADC14MEM22 interrupt flag; Interrupt Flag: ADC14IFG22"]
+    #[inline]
+    pub fn adc14iv_54(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_54)
+    }
+    #[doc = "Interrupt Source: ADC14MEM22 interrupt flag; Interrupt Flag: ADC14IFG22"]
+    #[inline]
+    pub fn adc14iv_56(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_56)
+    }
+    #[doc = "Interrupt Source: ADC14MEM23 interrupt flag; Interrupt Flag: ADC14IFG23"]
+    #[inline]
+    pub fn adc14iv_58(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_58)
+    }
+    #[doc = "Interrupt Source: ADC14MEM24 interrupt flag; Interrupt Flag: ADC14IFG24"]
+    #[inline]
+    pub fn adc14iv_60(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_60)
+    }
+    #[doc = "Interrupt Source: ADC14MEM25 interrupt flag; Interrupt Flag: ADC14IFG25"]
+    #[inline]
+    pub fn adc14iv_62(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_62)
+    }
+    #[doc = "Interrupt Source: ADC14MEM26 interrupt flag; Interrupt Flag: ADC14IFG26"]
+    #[inline]
+    pub fn adc14iv_64(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_64)
+    }
+    #[doc = "Interrupt Source: ADC14MEM27 interrupt flag; Interrupt Flag: ADC14IFG27"]
+    #[inline]
+    pub fn adc14iv_66(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_66)
+    }
+    #[doc = "Interrupt Source: ADC14MEM28 interrupt flag; Interrupt Flag: ADC14IFG28"]
+    #[inline]
+    pub fn adc14iv_68(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_68)
+    }
+    #[doc = "Interrupt Source: ADC14MEM29 interrupt flag; Interrupt Flag: ADC14IFG29"]
+    #[inline]
+    pub fn adc14iv_70(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_70)
+    }
+    #[doc = "Interrupt Source: ADC14MEM30 interrupt flag; Interrupt Flag: ADC14IFG30"]
+    #[inline]
+    pub fn adc14iv_72(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_72)
+    }
+    #[doc = "Interrupt Source: ADC14MEM31 interrupt flag; Interrupt Flag: ADC14IFG31"]
+    #[inline]
+    pub fn adc14iv_74(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_74)
+    }
+    #[doc = "Interrupt Source: ADC14RDYIFG interrupt flag; Interrupt Flag: ADC14RDYIFG; Interrupt Priority: Lowest"]
+    #[inline]
+    pub fn adc14iv_76(self) -> &'a mut W {
+        self.variant(ADC14IVW::ADC14IV_76)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - ADC14 interrupt vector value"]
+    #[inline]
+    pub fn adc14iv(&self) -> ADC14IVR {
+        ADC14IVR::_from({
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - ADC14 interrupt vector value"]
+    #[inline]
+    pub fn adc14iv(&mut self) -> _ADC14IVW {
+        _ADC14IVW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/adc14/adc14lo0.rs b/example-source/msp432p401r/src/adc14/adc14lo0.rs
new file mode 100644
index 0000000..ebb7ae5
--- /dev/null
+++ b/example-source/msp432p401r/src/adc14/adc14lo0.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::ADC14LO0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ADC14LO0R {
+    bits: u16,
+}
+impl ADC14LO0R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14LO0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14LO0W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Low threshold 0"]
+    #[inline]
+    pub fn adc14lo0(&self) -> ADC14LO0R {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        ADC14LO0R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Low threshold 0"]
+    #[inline]
+    pub fn adc14lo0(&mut self) -> _ADC14LO0W {
+        _ADC14LO0W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/adc14/adc14lo1.rs b/example-source/msp432p401r/src/adc14/adc14lo1.rs
new file mode 100644
index 0000000..7d736b2
--- /dev/null
+++ b/example-source/msp432p401r/src/adc14/adc14lo1.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::ADC14LO1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ADC14LO1R {
+    bits: u16,
+}
+impl ADC14LO1R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14LO1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14LO1W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Low threshold 1"]
+    #[inline]
+    pub fn adc14lo1(&self) -> ADC14LO1R {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        ADC14LO1R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Low threshold 1"]
+    #[inline]
+    pub fn adc14lo1(&mut self) -> _ADC14LO1W {
+        _ADC14LO1W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/adc14/adc14mctl.rs b/example-source/msp432p401r/src/adc14/adc14mctl.rs
new file mode 100644
index 0000000..4eaf51d
--- /dev/null
+++ b/example-source/msp432p401r/src/adc14/adc14mctl.rs
@@ -0,0 +1,1289 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::ADC14MCTL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `ADC14INCH`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14INCHR {
+    #[doc = "If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1"]
+    ADC14INCH_0,
+    #[doc = "If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1"]
+    ADC14INCH_1,
+    #[doc = "If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3"]
+    ADC14INCH_2,
+    #[doc = "If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3"]
+    ADC14INCH_3,
+    #[doc = "If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5"]
+    ADC14INCH_4,
+    #[doc = "If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5"]
+    ADC14INCH_5,
+    #[doc = "If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7"]
+    ADC14INCH_6,
+    #[doc = "If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7"]
+    ADC14INCH_7,
+    #[doc = "If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9"]
+    ADC14INCH_8,
+    #[doc = "If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9"]
+    ADC14INCH_9,
+    #[doc = "If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11"]
+    ADC14INCH_10,
+    #[doc = "If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11"]
+    ADC14INCH_11,
+    #[doc = "If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13"]
+    ADC14INCH_12,
+    #[doc = "If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13"]
+    ADC14INCH_13,
+    #[doc = "If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15"]
+    ADC14INCH_14,
+    #[doc = "If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15"]
+    ADC14INCH_15,
+    #[doc = "If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17"]
+    ADC14INCH_16,
+    #[doc = "If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17"]
+    ADC14INCH_17,
+    #[doc = "If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19"]
+    ADC14INCH_18,
+    #[doc = "If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19"]
+    ADC14INCH_19,
+    #[doc = "If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21"]
+    ADC14INCH_20,
+    #[doc = "If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21"]
+    ADC14INCH_21,
+    #[doc = "If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23"]
+    ADC14INCH_22,
+    #[doc = "If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23"]
+    ADC14INCH_23,
+    #[doc = "If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25"]
+    ADC14INCH_24,
+    #[doc = "If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25"]
+    ADC14INCH_25,
+    #[doc = "If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27"]
+    ADC14INCH_26,
+    #[doc = "If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27"]
+    ADC14INCH_27,
+    #[doc = "If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29"]
+    ADC14INCH_28,
+    #[doc = "If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29"]
+    ADC14INCH_29,
+    #[doc = "If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31"]
+    ADC14INCH_30,
+    #[doc = "If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31"]
+    ADC14INCH_31,
+}
+impl ADC14INCHR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            ADC14INCHR::ADC14INCH_0 => 0,
+            ADC14INCHR::ADC14INCH_1 => 1,
+            ADC14INCHR::ADC14INCH_2 => 2,
+            ADC14INCHR::ADC14INCH_3 => 3,
+            ADC14INCHR::ADC14INCH_4 => 4,
+            ADC14INCHR::ADC14INCH_5 => 5,
+            ADC14INCHR::ADC14INCH_6 => 6,
+            ADC14INCHR::ADC14INCH_7 => 7,
+            ADC14INCHR::ADC14INCH_8 => 8,
+            ADC14INCHR::ADC14INCH_9 => 9,
+            ADC14INCHR::ADC14INCH_10 => 10,
+            ADC14INCHR::ADC14INCH_11 => 11,
+            ADC14INCHR::ADC14INCH_12 => 12,
+            ADC14INCHR::ADC14INCH_13 => 13,
+            ADC14INCHR::ADC14INCH_14 => 14,
+            ADC14INCHR::ADC14INCH_15 => 15,
+            ADC14INCHR::ADC14INCH_16 => 16,
+            ADC14INCHR::ADC14INCH_17 => 17,
+            ADC14INCHR::ADC14INCH_18 => 18,
+            ADC14INCHR::ADC14INCH_19 => 19,
+            ADC14INCHR::ADC14INCH_20 => 20,
+            ADC14INCHR::ADC14INCH_21 => 21,
+            ADC14INCHR::ADC14INCH_22 => 22,
+            ADC14INCHR::ADC14INCH_23 => 23,
+            ADC14INCHR::ADC14INCH_24 => 24,
+            ADC14INCHR::ADC14INCH_25 => 25,
+            ADC14INCHR::ADC14INCH_26 => 26,
+            ADC14INCHR::ADC14INCH_27 => 27,
+            ADC14INCHR::ADC14INCH_28 => 28,
+            ADC14INCHR::ADC14INCH_29 => 29,
+            ADC14INCHR::ADC14INCH_30 => 30,
+            ADC14INCHR::ADC14INCH_31 => 31,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> ADC14INCHR {
+        match value {
+            0 => ADC14INCHR::ADC14INCH_0,
+            1 => ADC14INCHR::ADC14INCH_1,
+            2 => ADC14INCHR::ADC14INCH_2,
+            3 => ADC14INCHR::ADC14INCH_3,
+            4 => ADC14INCHR::ADC14INCH_4,
+            5 => ADC14INCHR::ADC14INCH_5,
+            6 => ADC14INCHR::ADC14INCH_6,
+            7 => ADC14INCHR::ADC14INCH_7,
+            8 => ADC14INCHR::ADC14INCH_8,
+            9 => ADC14INCHR::ADC14INCH_9,
+            10 => ADC14INCHR::ADC14INCH_10,
+            11 => ADC14INCHR::ADC14INCH_11,
+            12 => ADC14INCHR::ADC14INCH_12,
+            13 => ADC14INCHR::ADC14INCH_13,
+            14 => ADC14INCHR::ADC14INCH_14,
+            15 => ADC14INCHR::ADC14INCH_15,
+            16 => ADC14INCHR::ADC14INCH_16,
+            17 => ADC14INCHR::ADC14INCH_17,
+            18 => ADC14INCHR::ADC14INCH_18,
+            19 => ADC14INCHR::ADC14INCH_19,
+            20 => ADC14INCHR::ADC14INCH_20,
+            21 => ADC14INCHR::ADC14INCH_21,
+            22 => ADC14INCHR::ADC14INCH_22,
+            23 => ADC14INCHR::ADC14INCH_23,
+            24 => ADC14INCHR::ADC14INCH_24,
+            25 => ADC14INCHR::ADC14INCH_25,
+            26 => ADC14INCHR::ADC14INCH_26,
+            27 => ADC14INCHR::ADC14INCH_27,
+            28 => ADC14INCHR::ADC14INCH_28,
+            29 => ADC14INCHR::ADC14INCH_29,
+            30 => ADC14INCHR::ADC14INCH_30,
+            31 => ADC14INCHR::ADC14INCH_31,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_0`"]
+    #[inline]
+    pub fn is_adc14inch_0(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_1`"]
+    #[inline]
+    pub fn is_adc14inch_1(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_1
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_2`"]
+    #[inline]
+    pub fn is_adc14inch_2(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_2
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_3`"]
+    #[inline]
+    pub fn is_adc14inch_3(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_3
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_4`"]
+    #[inline]
+    pub fn is_adc14inch_4(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_4
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_5`"]
+    #[inline]
+    pub fn is_adc14inch_5(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_5
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_6`"]
+    #[inline]
+    pub fn is_adc14inch_6(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_6
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_7`"]
+    #[inline]
+    pub fn is_adc14inch_7(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_7
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_8`"]
+    #[inline]
+    pub fn is_adc14inch_8(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_8
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_9`"]
+    #[inline]
+    pub fn is_adc14inch_9(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_9
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_10`"]
+    #[inline]
+    pub fn is_adc14inch_10(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_10
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_11`"]
+    #[inline]
+    pub fn is_adc14inch_11(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_11
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_12`"]
+    #[inline]
+    pub fn is_adc14inch_12(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_12
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_13`"]
+    #[inline]
+    pub fn is_adc14inch_13(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_13
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_14`"]
+    #[inline]
+    pub fn is_adc14inch_14(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_14
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_15`"]
+    #[inline]
+    pub fn is_adc14inch_15(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_15
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_16`"]
+    #[inline]
+    pub fn is_adc14inch_16(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_16
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_17`"]
+    #[inline]
+    pub fn is_adc14inch_17(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_17
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_18`"]
+    #[inline]
+    pub fn is_adc14inch_18(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_18
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_19`"]
+    #[inline]
+    pub fn is_adc14inch_19(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_19
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_20`"]
+    #[inline]
+    pub fn is_adc14inch_20(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_20
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_21`"]
+    #[inline]
+    pub fn is_adc14inch_21(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_21
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_22`"]
+    #[inline]
+    pub fn is_adc14inch_22(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_22
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_23`"]
+    #[inline]
+    pub fn is_adc14inch_23(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_23
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_24`"]
+    #[inline]
+    pub fn is_adc14inch_24(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_24
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_25`"]
+    #[inline]
+    pub fn is_adc14inch_25(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_25
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_26`"]
+    #[inline]
+    pub fn is_adc14inch_26(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_26
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_27`"]
+    #[inline]
+    pub fn is_adc14inch_27(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_27
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_28`"]
+    #[inline]
+    pub fn is_adc14inch_28(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_28
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_29`"]
+    #[inline]
+    pub fn is_adc14inch_29(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_29
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_30`"]
+    #[inline]
+    pub fn is_adc14inch_30(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_30
+    }
+    #[doc = "Checks if the value of the field is `ADC14INCH_31`"]
+    #[inline]
+    pub fn is_adc14inch_31(&self) -> bool {
+        *self == ADC14INCHR::ADC14INCH_31
+    }
+}
+#[doc = "Possible values of the field `ADC14EOS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14EOSR {
+    #[doc = "Not end of sequence"]
+    ADC14EOS_0,
+    #[doc = "End of sequence"]
+    ADC14EOS_1,
+}
+impl ADC14EOSR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14EOSR::ADC14EOS_0 => false,
+            ADC14EOSR::ADC14EOS_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14EOSR {
+        match value {
+            false => ADC14EOSR::ADC14EOS_0,
+            true => ADC14EOSR::ADC14EOS_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14EOS_0`"]
+    #[inline]
+    pub fn is_adc14eos_0(&self) -> bool {
+        *self == ADC14EOSR::ADC14EOS_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14EOS_1`"]
+    #[inline]
+    pub fn is_adc14eos_1(&self) -> bool {
+        *self == ADC14EOSR::ADC14EOS_1
+    }
+}
+#[doc = "Possible values of the field `ADC14VRSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14VRSELR {
+    #[doc = "V(R+) = AVCC, V(R-) = AVSS"]
+    ADC14VRSEL_0,
+    #[doc = "V(R+) = VREF buffered, V(R-) = AVSS"]
+    ADC14VRSEL_1,
+    #[doc = "V(R+) = VeREF+, V(R-) = VeREF-"]
+    ADC14VRSEL_14,
+    #[doc = "V(R+) = VeREF+ buffered, V(R-) = VeREF"]
+    ADC14VRSEL_15,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl ADC14VRSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            ADC14VRSELR::ADC14VRSEL_0 => 0,
+            ADC14VRSELR::ADC14VRSEL_1 => 1,
+            ADC14VRSELR::ADC14VRSEL_14 => 14,
+            ADC14VRSELR::ADC14VRSEL_15 => 15,
+            ADC14VRSELR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> ADC14VRSELR {
+        match value {
+            0 => ADC14VRSELR::ADC14VRSEL_0,
+            1 => ADC14VRSELR::ADC14VRSEL_1,
+            14 => ADC14VRSELR::ADC14VRSEL_14,
+            15 => ADC14VRSELR::ADC14VRSEL_15,
+            i => ADC14VRSELR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14VRSEL_0`"]
+    #[inline]
+    pub fn is_adc14vrsel_0(&self) -> bool {
+        *self == ADC14VRSELR::ADC14VRSEL_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14VRSEL_1`"]
+    #[inline]
+    pub fn is_adc14vrsel_1(&self) -> bool {
+        *self == ADC14VRSELR::ADC14VRSEL_1
+    }
+    #[doc = "Checks if the value of the field is `ADC14VRSEL_14`"]
+    #[inline]
+    pub fn is_adc14vrsel_14(&self) -> bool {
+        *self == ADC14VRSELR::ADC14VRSEL_14
+    }
+    #[doc = "Checks if the value of the field is `ADC14VRSEL_15`"]
+    #[inline]
+    pub fn is_adc14vrsel_15(&self) -> bool {
+        *self == ADC14VRSELR::ADC14VRSEL_15
+    }
+}
+#[doc = "Possible values of the field `ADC14DIF`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14DIFR {
+    #[doc = "Single-ended mode enabled"]
+    ADC14DIF_0,
+    #[doc = "Differential mode enabled"]
+    ADC14DIF_1,
+}
+impl ADC14DIFR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14DIFR::ADC14DIF_0 => false,
+            ADC14DIFR::ADC14DIF_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14DIFR {
+        match value {
+            false => ADC14DIFR::ADC14DIF_0,
+            true => ADC14DIFR::ADC14DIF_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14DIF_0`"]
+    #[inline]
+    pub fn is_adc14dif_0(&self) -> bool {
+        *self == ADC14DIFR::ADC14DIF_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14DIF_1`"]
+    #[inline]
+    pub fn is_adc14dif_1(&self) -> bool {
+        *self == ADC14DIFR::ADC14DIF_1
+    }
+}
+#[doc = "Possible values of the field `ADC14WINC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14WINCR {
+    #[doc = "Comparator window disabled"]
+    ADC14WINC_0,
+    #[doc = "Comparator window enabled"]
+    ADC14WINC_1,
+}
+impl ADC14WINCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14WINCR::ADC14WINC_0 => false,
+            ADC14WINCR::ADC14WINC_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14WINCR {
+        match value {
+            false => ADC14WINCR::ADC14WINC_0,
+            true => ADC14WINCR::ADC14WINC_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14WINC_0`"]
+    #[inline]
+    pub fn is_adc14winc_0(&self) -> bool {
+        *self == ADC14WINCR::ADC14WINC_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14WINC_1`"]
+    #[inline]
+    pub fn is_adc14winc_1(&self) -> bool {
+        *self == ADC14WINCR::ADC14WINC_1
+    }
+}
+#[doc = "Possible values of the field `ADC14WINCTH`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC14WINCTHR {
+    #[doc = "Use window comparator thresholds 0, ADC14LO0 and ADC14HI0"]
+    ADC14WINCTH_0,
+    #[doc = "Use window comparator thresholds 1, ADC14LO1 and ADC14HI1"]
+    ADC14WINCTH_1,
+}
+impl ADC14WINCTHR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC14WINCTHR::ADC14WINCTH_0 => false,
+            ADC14WINCTHR::ADC14WINCTH_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC14WINCTHR {
+        match value {
+            false => ADC14WINCTHR::ADC14WINCTH_0,
+            true => ADC14WINCTHR::ADC14WINCTH_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ADC14WINCTH_0`"]
+    #[inline]
+    pub fn is_adc14wincth_0(&self) -> bool {
+        *self == ADC14WINCTHR::ADC14WINCTH_0
+    }
+    #[doc = "Checks if the value of the field is `ADC14WINCTH_1`"]
+    #[inline]
+    pub fn is_adc14wincth_1(&self) -> bool {
+        *self == ADC14WINCTHR::ADC14WINCTH_1
+    }
+}
+#[doc = "Values that can be written to the field `ADC14INCH`"]
+pub enum ADC14INCHW {
+    #[doc = "If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1"]
+    ADC14INCH_0,
+    #[doc = "If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1"]
+    ADC14INCH_1,
+    #[doc = "If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3"]
+    ADC14INCH_2,
+    #[doc = "If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3"]
+    ADC14INCH_3,
+    #[doc = "If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5"]
+    ADC14INCH_4,
+    #[doc = "If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5"]
+    ADC14INCH_5,
+    #[doc = "If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7"]
+    ADC14INCH_6,
+    #[doc = "If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7"]
+    ADC14INCH_7,
+    #[doc = "If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9"]
+    ADC14INCH_8,
+    #[doc = "If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9"]
+    ADC14INCH_9,
+    #[doc = "If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11"]
+    ADC14INCH_10,
+    #[doc = "If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11"]
+    ADC14INCH_11,
+    #[doc = "If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13"]
+    ADC14INCH_12,
+    #[doc = "If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13"]
+    ADC14INCH_13,
+    #[doc = "If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15"]
+    ADC14INCH_14,
+    #[doc = "If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15"]
+    ADC14INCH_15,
+    #[doc = "If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17"]
+    ADC14INCH_16,
+    #[doc = "If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17"]
+    ADC14INCH_17,
+    #[doc = "If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19"]
+    ADC14INCH_18,
+    #[doc = "If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19"]
+    ADC14INCH_19,
+    #[doc = "If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21"]
+    ADC14INCH_20,
+    #[doc = "If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21"]
+    ADC14INCH_21,
+    #[doc = "If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23"]
+    ADC14INCH_22,
+    #[doc = "If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23"]
+    ADC14INCH_23,
+    #[doc = "If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25"]
+    ADC14INCH_24,
+    #[doc = "If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25"]
+    ADC14INCH_25,
+    #[doc = "If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27"]
+    ADC14INCH_26,
+    #[doc = "If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27"]
+    ADC14INCH_27,
+    #[doc = "If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29"]
+    ADC14INCH_28,
+    #[doc = "If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29"]
+    ADC14INCH_29,
+    #[doc = "If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31"]
+    ADC14INCH_30,
+    #[doc = "If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31"]
+    ADC14INCH_31,
+}
+impl ADC14INCHW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            ADC14INCHW::ADC14INCH_0 => 0,
+            ADC14INCHW::ADC14INCH_1 => 1,
+            ADC14INCHW::ADC14INCH_2 => 2,
+            ADC14INCHW::ADC14INCH_3 => 3,
+            ADC14INCHW::ADC14INCH_4 => 4,
+            ADC14INCHW::ADC14INCH_5 => 5,
+            ADC14INCHW::ADC14INCH_6 => 6,
+            ADC14INCHW::ADC14INCH_7 => 7,
+            ADC14INCHW::ADC14INCH_8 => 8,
+            ADC14INCHW::ADC14INCH_9 => 9,
+            ADC14INCHW::ADC14INCH_10 => 10,
+            ADC14INCHW::ADC14INCH_11 => 11,
+            ADC14INCHW::ADC14INCH_12 => 12,
+            ADC14INCHW::ADC14INCH_13 => 13,
+            ADC14INCHW::ADC14INCH_14 => 14,
+            ADC14INCHW::ADC14INCH_15 => 15,
+            ADC14INCHW::ADC14INCH_16 => 16,
+            ADC14INCHW::ADC14INCH_17 => 17,
+            ADC14INCHW::ADC14INCH_18 => 18,
+            ADC14INCHW::ADC14INCH_19 => 19,
+            ADC14INCHW::ADC14INCH_20 => 20,
+            ADC14INCHW::ADC14INCH_21 => 21,
+            ADC14INCHW::ADC14INCH_22 => 22,
+            ADC14INCHW::ADC14INCH_23 => 23,
+            ADC14INCHW::ADC14INCH_24 => 24,
+            ADC14INCHW::ADC14INCH_25 => 25,
+            ADC14INCHW::ADC14INCH_26 => 26,
+            ADC14INCHW::ADC14INCH_27 => 27,
+            ADC14INCHW::ADC14INCH_28 => 28,
+            ADC14INCHW::ADC14INCH_29 => 29,
+            ADC14INCHW::ADC14INCH_30 => 30,
+            ADC14INCHW::ADC14INCH_31 => 31,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14INCHW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14INCHW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14INCHW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1"]
+    #[inline]
+    pub fn adc14inch_0(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_0)
+    }
+    #[doc = "If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1"]
+    #[inline]
+    pub fn adc14inch_1(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_1)
+    }
+    #[doc = "If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3"]
+    #[inline]
+    pub fn adc14inch_2(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_2)
+    }
+    #[doc = "If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3"]
+    #[inline]
+    pub fn adc14inch_3(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_3)
+    }
+    #[doc = "If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5"]
+    #[inline]
+    pub fn adc14inch_4(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_4)
+    }
+    #[doc = "If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5"]
+    #[inline]
+    pub fn adc14inch_5(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_5)
+    }
+    #[doc = "If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7"]
+    #[inline]
+    pub fn adc14inch_6(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_6)
+    }
+    #[doc = "If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7"]
+    #[inline]
+    pub fn adc14inch_7(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_7)
+    }
+    #[doc = "If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9"]
+    #[inline]
+    pub fn adc14inch_8(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_8)
+    }
+    #[doc = "If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9"]
+    #[inline]
+    pub fn adc14inch_9(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_9)
+    }
+    #[doc = "If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11"]
+    #[inline]
+    pub fn adc14inch_10(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_10)
+    }
+    #[doc = "If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11"]
+    #[inline]
+    pub fn adc14inch_11(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_11)
+    }
+    #[doc = "If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13"]
+    #[inline]
+    pub fn adc14inch_12(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_12)
+    }
+    #[doc = "If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13"]
+    #[inline]
+    pub fn adc14inch_13(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_13)
+    }
+    #[doc = "If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15"]
+    #[inline]
+    pub fn adc14inch_14(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_14)
+    }
+    #[doc = "If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15"]
+    #[inline]
+    pub fn adc14inch_15(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_15)
+    }
+    #[doc = "If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17"]
+    #[inline]
+    pub fn adc14inch_16(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_16)
+    }
+    #[doc = "If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17"]
+    #[inline]
+    pub fn adc14inch_17(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_17)
+    }
+    #[doc = "If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19"]
+    #[inline]
+    pub fn adc14inch_18(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_18)
+    }
+    #[doc = "If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19"]
+    #[inline]
+    pub fn adc14inch_19(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_19)
+    }
+    #[doc = "If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21"]
+    #[inline]
+    pub fn adc14inch_20(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_20)
+    }
+    #[doc = "If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21"]
+    #[inline]
+    pub fn adc14inch_21(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_21)
+    }
+    #[doc = "If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23"]
+    #[inline]
+    pub fn adc14inch_22(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_22)
+    }
+    #[doc = "If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23"]
+    #[inline]
+    pub fn adc14inch_23(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_23)
+    }
+    #[doc = "If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25"]
+    #[inline]
+    pub fn adc14inch_24(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_24)
+    }
+    #[doc = "If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25"]
+    #[inline]
+    pub fn adc14inch_25(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_25)
+    }
+    #[doc = "If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27"]
+    #[inline]
+    pub fn adc14inch_26(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_26)
+    }
+    #[doc = "If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27"]
+    #[inline]
+    pub fn adc14inch_27(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_27)
+    }
+    #[doc = "If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29"]
+    #[inline]
+    pub fn adc14inch_28(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_28)
+    }
+    #[doc = "If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29"]
+    #[inline]
+    pub fn adc14inch_29(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_29)
+    }
+    #[doc = "If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31"]
+    #[inline]
+    pub fn adc14inch_30(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_30)
+    }
+    #[doc = "If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31"]
+    #[inline]
+    pub fn adc14inch_31(self) -> &'a mut W {
+        self.variant(ADC14INCHW::ADC14INCH_31)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 31;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14EOS`"]
+pub enum ADC14EOSW {
+    #[doc = "Not end of sequence"]
+    ADC14EOS_0,
+    #[doc = "End of sequence"]
+    ADC14EOS_1,
+}
+impl ADC14EOSW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14EOSW::ADC14EOS_0 => false,
+            ADC14EOSW::ADC14EOS_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14EOSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14EOSW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14EOSW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Not end of sequence"]
+    #[inline]
+    pub fn adc14eos_0(self) -> &'a mut W {
+        self.variant(ADC14EOSW::ADC14EOS_0)
+    }
+    #[doc = "End of sequence"]
+    #[inline]
+    pub fn adc14eos_1(self) -> &'a mut W {
+        self.variant(ADC14EOSW::ADC14EOS_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14VRSEL`"]
+pub enum ADC14VRSELW {
+    #[doc = "V(R+) = AVCC, V(R-) = AVSS"]
+    ADC14VRSEL_0,
+    #[doc = "V(R+) = VREF buffered, V(R-) = AVSS"]
+    ADC14VRSEL_1,
+    #[doc = "V(R+) = VeREF+, V(R-) = VeREF-"]
+    ADC14VRSEL_14,
+    #[doc = "V(R+) = VeREF+ buffered, V(R-) = VeREF"]
+    ADC14VRSEL_15,
+}
+impl ADC14VRSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            ADC14VRSELW::ADC14VRSEL_0 => 0,
+            ADC14VRSELW::ADC14VRSEL_1 => 1,
+            ADC14VRSELW::ADC14VRSEL_14 => 14,
+            ADC14VRSELW::ADC14VRSEL_15 => 15,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14VRSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14VRSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14VRSELW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "V(R+) = AVCC, V(R-) = AVSS"]
+    #[inline]
+    pub fn adc14vrsel_0(self) -> &'a mut W {
+        self.variant(ADC14VRSELW::ADC14VRSEL_0)
+    }
+    #[doc = "V(R+) = VREF buffered, V(R-) = AVSS"]
+    #[inline]
+    pub fn adc14vrsel_1(self) -> &'a mut W {
+        self.variant(ADC14VRSELW::ADC14VRSEL_1)
+    }
+    #[doc = "V(R+) = VeREF+, V(R-) = VeREF-"]
+    #[inline]
+    pub fn adc14vrsel_14(self) -> &'a mut W {
+        self.variant(ADC14VRSELW::ADC14VRSEL_14)
+    }
+    #[doc = "V(R+) = VeREF+ buffered, V(R-) = VeREF"]
+    #[inline]
+    pub fn adc14vrsel_15(self) -> &'a mut W {
+        self.variant(ADC14VRSELW::ADC14VRSEL_15)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14DIF`"]
+pub enum ADC14DIFW {
+    #[doc = "Single-ended mode enabled"]
+    ADC14DIF_0,
+    #[doc = "Differential mode enabled"]
+    ADC14DIF_1,
+}
+impl ADC14DIFW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14DIFW::ADC14DIF_0 => false,
+            ADC14DIFW::ADC14DIF_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14DIFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14DIFW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14DIFW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Single-ended mode enabled"]
+    #[inline]
+    pub fn adc14dif_0(self) -> &'a mut W {
+        self.variant(ADC14DIFW::ADC14DIF_0)
+    }
+    #[doc = "Differential mode enabled"]
+    #[inline]
+    pub fn adc14dif_1(self) -> &'a mut W {
+        self.variant(ADC14DIFW::ADC14DIF_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14WINC`"]
+pub enum ADC14WINCW {
+    #[doc = "Comparator window disabled"]
+    ADC14WINC_0,
+    #[doc = "Comparator window enabled"]
+    ADC14WINC_1,
+}
+impl ADC14WINCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14WINCW::ADC14WINC_0 => false,
+            ADC14WINCW::ADC14WINC_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14WINCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14WINCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14WINCW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Comparator window disabled"]
+    #[inline]
+    pub fn adc14winc_0(self) -> &'a mut W {
+        self.variant(ADC14WINCW::ADC14WINC_0)
+    }
+    #[doc = "Comparator window enabled"]
+    #[inline]
+    pub fn adc14winc_1(self) -> &'a mut W {
+        self.variant(ADC14WINCW::ADC14WINC_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC14WINCTH`"]
+pub enum ADC14WINCTHW {
+    #[doc = "Use window comparator thresholds 0, ADC14LO0 and ADC14HI0"]
+    ADC14WINCTH_0,
+    #[doc = "Use window comparator thresholds 1, ADC14LO1 and ADC14HI1"]
+    ADC14WINCTH_1,
+}
+impl ADC14WINCTHW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC14WINCTHW::ADC14WINCTH_0 => false,
+            ADC14WINCTHW::ADC14WINCTH_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC14WINCTHW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC14WINCTHW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC14WINCTHW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Use window comparator thresholds 0, ADC14LO0 and ADC14HI0"]
+    #[inline]
+    pub fn adc14wincth_0(self) -> &'a mut W {
+        self.variant(ADC14WINCTHW::ADC14WINCTH_0)
+    }
+    #[doc = "Use window comparator thresholds 1, ADC14LO1 and ADC14HI1"]
+    #[inline]
+    pub fn adc14wincth_1(self) -> &'a mut W {
+        self.variant(ADC14WINCTHW::ADC14WINCTH_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:4 - Input channel select"]
+    #[inline]
+    pub fn adc14inch(&self) -> ADC14INCHR {
+        ADC14INCHR::_from({
+            const MASK: u8 = 31;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 7 - End of sequence"]
+    #[inline]
+    pub fn adc14eos(&self) -> ADC14EOSR {
+        ADC14EOSR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 8:11 - Selects combinations of V(R+) and V(R-) sources"]
+    #[inline]
+    pub fn adc14vrsel(&self) -> ADC14VRSELR {
+        ADC14VRSELR::_from({
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 13 - Differential mode"]
+    #[inline]
+    pub fn adc14dif(&self) -> ADC14DIFR {
+        ADC14DIFR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 14 - Comparator window enable"]
+    #[inline]
+    pub fn adc14winc(&self) -> ADC14WINCR {
+        ADC14WINCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 15 - Window comparator threshold register selection"]
+    #[inline]
+    pub fn adc14wincth(&self) -> ADC14WINCTHR {
+        ADC14WINCTHR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:4 - Input channel select"]
+    #[inline]
+    pub fn adc14inch(&mut self) -> _ADC14INCHW {
+        _ADC14INCHW { w: self }
+    }
+    #[doc = "Bit 7 - End of sequence"]
+    #[inline]
+    pub fn adc14eos(&mut self) -> _ADC14EOSW {
+        _ADC14EOSW { w: self }
+    }
+    #[doc = "Bits 8:11 - Selects combinations of V(R+) and V(R-) sources"]
+    #[inline]
+    pub fn adc14vrsel(&mut self) -> _ADC14VRSELW {
+        _ADC14VRSELW { w: self }
+    }
+    #[doc = "Bit 13 - Differential mode"]
+    #[inline]
+    pub fn adc14dif(&mut self) -> _ADC14DIFW {
+        _ADC14DIFW { w: self }
+    }
+    #[doc = "Bit 14 - Comparator window enable"]
+    #[inline]
+    pub fn adc14winc(&mut self) -> _ADC14WINCW {
+        _ADC14WINCW { w: self }
+    }
+    #[doc = "Bit 15 - Window comparator threshold register selection"]
+    #[inline]
+    pub fn adc14wincth(&mut self) -> _ADC14WINCTHW {
+        _ADC14WINCTHW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/adc14/adc14mem.rs b/example-source/msp432p401r/src/adc14/adc14mem.rs
new file mode 100644
index 0000000..5533320
--- /dev/null
+++ b/example-source/msp432p401r/src/adc14/adc14mem.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::ADC14MEM {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CONVERSION_RESULTSR {
+    bits: u16,
+}
+impl CONVERSION_RESULTSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CONVERSION_RESULTSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CONVERSION_RESULTSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Conversion Result"]
+    #[inline]
+    pub fn conversion_results(&self) -> CONVERSION_RESULTSR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        CONVERSION_RESULTSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Conversion Result"]
+    #[inline]
+    pub fn conversion_results(&mut self) -> _CONVERSION_RESULTSW {
+        _CONVERSION_RESULTSW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/aes256.rs b/example-source/msp432p401r/src/aes256.rs
new file mode 100644
index 0000000..172bf44
--- /dev/null
+++ b/example-source/msp432p401r/src/aes256.rs
@@ -0,0 +1,68 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - AES Accelerator Control Register 0"]
+    pub aesactl0: AESACTL0,
+    #[doc = "0x02 - AES Accelerator Control Register 1"]
+    pub aesactl1: AESACTL1,
+    #[doc = "0x04 - AES Accelerator Status Register"]
+    pub aesastat: AESASTAT,
+    #[doc = "0x06 - AES Accelerator Key Register"]
+    pub aesakey: AESAKEY,
+    #[doc = "0x08 - AES Accelerator Data In Register"]
+    pub aesadin: AESADIN,
+    #[doc = "0x0a - AES Accelerator Data Out Register"]
+    pub aesadout: AESADOUT,
+    #[doc = "0x0c - AES Accelerator XORed Data In Register"]
+    pub aesaxdin: AESAXDIN,
+    #[doc = "0x0e - AES Accelerator XORed Data In Register"]
+    pub aesaxin: AESAXIN,
+}
+#[doc = "AES Accelerator Control Register 0"]
+pub struct AESACTL0 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "AES Accelerator Control Register 0"]
+pub mod aesactl0;
+#[doc = "AES Accelerator Control Register 1"]
+pub struct AESACTL1 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "AES Accelerator Control Register 1"]
+pub mod aesactl1;
+#[doc = "AES Accelerator Status Register"]
+pub struct AESASTAT {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "AES Accelerator Status Register"]
+pub mod aesastat;
+#[doc = "AES Accelerator Key Register"]
+pub struct AESAKEY {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "AES Accelerator Key Register"]
+pub mod aesakey;
+#[doc = "AES Accelerator Data In Register"]
+pub struct AESADIN {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "AES Accelerator Data In Register"]
+pub mod aesadin;
+#[doc = "AES Accelerator Data Out Register"]
+pub struct AESADOUT {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "AES Accelerator Data Out Register"]
+pub mod aesadout;
+#[doc = "AES Accelerator XORed Data In Register"]
+pub struct AESAXDIN {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "AES Accelerator XORed Data In Register"]
+pub mod aesaxdin;
+#[doc = "AES Accelerator XORed Data In Register"]
+pub struct AESAXIN {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "AES Accelerator XORed Data In Register"]
+pub mod aesaxin;
diff --git a/example-source/msp432p401r/src/aes256/aesactl0.rs b/example-source/msp432p401r/src/aes256/aesactl0.rs
new file mode 100644
index 0000000..c6ce78c
--- /dev/null
+++ b/example-source/msp432p401r/src/aes256/aesactl0.rs
@@ -0,0 +1,1051 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::AESACTL0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `AESOPx`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum AESOPXR {
+    #[doc = "Encryption"]
+    AESOPX_0,
+    #[doc = "Decryption. The provided key is the same key used for encryption"]
+    AESOPX_1,
+    #[doc = "Generate first round key required for decryption"]
+    AESOPX_2,
+    #[doc = "Decryption. The provided key is the first round key required for decryption"]
+    AESOPX_3,
+}
+impl AESOPXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            AESOPXR::AESOPX_0 => 0,
+            AESOPXR::AESOPX_1 => 1,
+            AESOPXR::AESOPX_2 => 2,
+            AESOPXR::AESOPX_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> AESOPXR {
+        match value {
+            0 => AESOPXR::AESOPX_0,
+            1 => AESOPXR::AESOPX_1,
+            2 => AESOPXR::AESOPX_2,
+            3 => AESOPXR::AESOPX_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `AESOPX_0`"]
+    #[inline]
+    pub fn is_aesopx_0(&self) -> bool {
+        *self == AESOPXR::AESOPX_0
+    }
+    #[doc = "Checks if the value of the field is `AESOPX_1`"]
+    #[inline]
+    pub fn is_aesopx_1(&self) -> bool {
+        *self == AESOPXR::AESOPX_1
+    }
+    #[doc = "Checks if the value of the field is `AESOPX_2`"]
+    #[inline]
+    pub fn is_aesopx_2(&self) -> bool {
+        *self == AESOPXR::AESOPX_2
+    }
+    #[doc = "Checks if the value of the field is `AESOPX_3`"]
+    #[inline]
+    pub fn is_aesopx_3(&self) -> bool {
+        *self == AESOPXR::AESOPX_3
+    }
+}
+#[doc = "Possible values of the field `AESKLx`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum AESKLXR {
+    #[doc = "AES128. The key size is 128 bit"]
+    AESKLX_0,
+    #[doc = "AES192. The key size is 192 bit."]
+    AESKLX_1,
+    #[doc = "AES256. The key size is 256 bit"]
+    AESKLX_2,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl AESKLXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            AESKLXR::AESKLX_0 => 0,
+            AESKLXR::AESKLX_1 => 1,
+            AESKLXR::AESKLX_2 => 2,
+            AESKLXR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> AESKLXR {
+        match value {
+            0 => AESKLXR::AESKLX_0,
+            1 => AESKLXR::AESKLX_1,
+            2 => AESKLXR::AESKLX_2,
+            i => AESKLXR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `AESKLX_0`"]
+    #[inline]
+    pub fn is_aesklx_0(&self) -> bool {
+        *self == AESKLXR::AESKLX_0
+    }
+    #[doc = "Checks if the value of the field is `AESKLX_1`"]
+    #[inline]
+    pub fn is_aesklx_1(&self) -> bool {
+        *self == AESKLXR::AESKLX_1
+    }
+    #[doc = "Checks if the value of the field is `AESKLX_2`"]
+    #[inline]
+    pub fn is_aesklx_2(&self) -> bool {
+        *self == AESKLXR::AESKLX_2
+    }
+}
+#[doc = "Possible values of the field `AESCMx`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum AESCMXR {
+    #[doc = "ECB"]
+    AESCMX_0,
+    #[doc = "CBC"]
+    AESCMX_1,
+    #[doc = "OFB"]
+    AESCMX_2,
+    #[doc = "CFB"]
+    AESCMX_3,
+}
+impl AESCMXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            AESCMXR::AESCMX_0 => 0,
+            AESCMXR::AESCMX_1 => 1,
+            AESCMXR::AESCMX_2 => 2,
+            AESCMXR::AESCMX_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> AESCMXR {
+        match value {
+            0 => AESCMXR::AESCMX_0,
+            1 => AESCMXR::AESCMX_1,
+            2 => AESCMXR::AESCMX_2,
+            3 => AESCMXR::AESCMX_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `AESCMX_0`"]
+    #[inline]
+    pub fn is_aescmx_0(&self) -> bool {
+        *self == AESCMXR::AESCMX_0
+    }
+    #[doc = "Checks if the value of the field is `AESCMX_1`"]
+    #[inline]
+    pub fn is_aescmx_1(&self) -> bool {
+        *self == AESCMXR::AESCMX_1
+    }
+    #[doc = "Checks if the value of the field is `AESCMX_2`"]
+    #[inline]
+    pub fn is_aescmx_2(&self) -> bool {
+        *self == AESCMXR::AESCMX_2
+    }
+    #[doc = "Checks if the value of the field is `AESCMX_3`"]
+    #[inline]
+    pub fn is_aescmx_3(&self) -> bool {
+        *self == AESCMXR::AESCMX_3
+    }
+}
+#[doc = "Possible values of the field `AESSWRST`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum AESSWRSTR {
+    #[doc = "No reset"]
+    AESSWRST_0,
+    #[doc = "Reset AES accelerator module"]
+    AESSWRST_1,
+}
+impl AESSWRSTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            AESSWRSTR::AESSWRST_0 => false,
+            AESSWRSTR::AESSWRST_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> AESSWRSTR {
+        match value {
+            false => AESSWRSTR::AESSWRST_0,
+            true => AESSWRSTR::AESSWRST_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `AESSWRST_0`"]
+    #[inline]
+    pub fn is_aesswrst_0(&self) -> bool {
+        *self == AESSWRSTR::AESSWRST_0
+    }
+    #[doc = "Checks if the value of the field is `AESSWRST_1`"]
+    #[inline]
+    pub fn is_aesswrst_1(&self) -> bool {
+        *self == AESSWRSTR::AESSWRST_1
+    }
+}
+#[doc = "Possible values of the field `AESRDYIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum AESRDYIFGR {
+    #[doc = "No interrupt pending"]
+    AESRDYIFG_0,
+    #[doc = "Interrupt pending"]
+    AESRDYIFG_1,
+}
+impl AESRDYIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            AESRDYIFGR::AESRDYIFG_0 => false,
+            AESRDYIFGR::AESRDYIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> AESRDYIFGR {
+        match value {
+            false => AESRDYIFGR::AESRDYIFG_0,
+            true => AESRDYIFGR::AESRDYIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `AESRDYIFG_0`"]
+    #[inline]
+    pub fn is_aesrdyifg_0(&self) -> bool {
+        *self == AESRDYIFGR::AESRDYIFG_0
+    }
+    #[doc = "Checks if the value of the field is `AESRDYIFG_1`"]
+    #[inline]
+    pub fn is_aesrdyifg_1(&self) -> bool {
+        *self == AESRDYIFGR::AESRDYIFG_1
+    }
+}
+#[doc = "Possible values of the field `AESERRFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum AESERRFGR {
+    #[doc = "No error"]
+    AESERRFG_0,
+    #[doc = "Error occurred"]
+    AESERRFG_1,
+}
+impl AESERRFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            AESERRFGR::AESERRFG_0 => false,
+            AESERRFGR::AESERRFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> AESERRFGR {
+        match value {
+            false => AESERRFGR::AESERRFG_0,
+            true => AESERRFGR::AESERRFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `AESERRFG_0`"]
+    #[inline]
+    pub fn is_aeserrfg_0(&self) -> bool {
+        *self == AESERRFGR::AESERRFG_0
+    }
+    #[doc = "Checks if the value of the field is `AESERRFG_1`"]
+    #[inline]
+    pub fn is_aeserrfg_1(&self) -> bool {
+        *self == AESERRFGR::AESERRFG_1
+    }
+}
+#[doc = "Possible values of the field `AESRDYIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum AESRDYIER {
+    #[doc = "Interrupt disabled"]
+    AESRDYIE_0,
+    #[doc = "Interrupt enabled"]
+    AESRDYIE_1,
+}
+impl AESRDYIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            AESRDYIER::AESRDYIE_0 => false,
+            AESRDYIER::AESRDYIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> AESRDYIER {
+        match value {
+            false => AESRDYIER::AESRDYIE_0,
+            true => AESRDYIER::AESRDYIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `AESRDYIE_0`"]
+    #[inline]
+    pub fn is_aesrdyie_0(&self) -> bool {
+        *self == AESRDYIER::AESRDYIE_0
+    }
+    #[doc = "Checks if the value of the field is `AESRDYIE_1`"]
+    #[inline]
+    pub fn is_aesrdyie_1(&self) -> bool {
+        *self == AESRDYIER::AESRDYIE_1
+    }
+}
+#[doc = "Possible values of the field `AESCMEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum AESCMENR {
+    #[doc = "No DMA triggers are generated"]
+    AESCMEN_0,
+    #[doc = "DMA ciphermode support operation is enabled and the corresponding DMA triggers are generated"]
+    AESCMEN_1,
+}
+impl AESCMENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            AESCMENR::AESCMEN_0 => false,
+            AESCMENR::AESCMEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> AESCMENR {
+        match value {
+            false => AESCMENR::AESCMEN_0,
+            true => AESCMENR::AESCMEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `AESCMEN_0`"]
+    #[inline]
+    pub fn is_aescmen_0(&self) -> bool {
+        *self == AESCMENR::AESCMEN_0
+    }
+    #[doc = "Checks if the value of the field is `AESCMEN_1`"]
+    #[inline]
+    pub fn is_aescmen_1(&self) -> bool {
+        *self == AESCMENR::AESCMEN_1
+    }
+}
+#[doc = "Values that can be written to the field `AESOPx`"]
+pub enum AESOPXW {
+    #[doc = "Encryption"]
+    AESOPX_0,
+    #[doc = "Decryption. The provided key is the same key used for encryption"]
+    AESOPX_1,
+    #[doc = "Generate first round key required for decryption"]
+    AESOPX_2,
+    #[doc = "Decryption. The provided key is the first round key required for decryption"]
+    AESOPX_3,
+}
+impl AESOPXW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            AESOPXW::AESOPX_0 => 0,
+            AESOPXW::AESOPX_1 => 1,
+            AESOPXW::AESOPX_2 => 2,
+            AESOPXW::AESOPX_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AESOPXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AESOPXW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: AESOPXW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Encryption"]
+    #[inline]
+    pub fn aesopx_0(self) -> &'a mut W {
+        self.variant(AESOPXW::AESOPX_0)
+    }
+    #[doc = "Decryption. The provided key is the same key used for encryption"]
+    #[inline]
+    pub fn aesopx_1(self) -> &'a mut W {
+        self.variant(AESOPXW::AESOPX_1)
+    }
+    #[doc = "Generate first round key required for decryption"]
+    #[inline]
+    pub fn aesopx_2(self) -> &'a mut W {
+        self.variant(AESOPXW::AESOPX_2)
+    }
+    #[doc = "Decryption. The provided key is the first round key required for decryption"]
+    #[inline]
+    pub fn aesopx_3(self) -> &'a mut W {
+        self.variant(AESOPXW::AESOPX_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `AESKLx`"]
+pub enum AESKLXW {
+    #[doc = "AES128. The key size is 128 bit"]
+    AESKLX_0,
+    #[doc = "AES192. The key size is 192 bit."]
+    AESKLX_1,
+    #[doc = "AES256. The key size is 256 bit"]
+    AESKLX_2,
+}
+impl AESKLXW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            AESKLXW::AESKLX_0 => 0,
+            AESKLXW::AESKLX_1 => 1,
+            AESKLXW::AESKLX_2 => 2,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AESKLXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AESKLXW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: AESKLXW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "AES128. The key size is 128 bit"]
+    #[inline]
+    pub fn aesklx_0(self) -> &'a mut W {
+        self.variant(AESKLXW::AESKLX_0)
+    }
+    #[doc = "AES192. The key size is 192 bit."]
+    #[inline]
+    pub fn aesklx_1(self) -> &'a mut W {
+        self.variant(AESKLXW::AESKLX_1)
+    }
+    #[doc = "AES256. The key size is 256 bit"]
+    #[inline]
+    pub fn aesklx_2(self) -> &'a mut W {
+        self.variant(AESKLXW::AESKLX_2)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `AESCMx`"]
+pub enum AESCMXW {
+    #[doc = "ECB"]
+    AESCMX_0,
+    #[doc = "CBC"]
+    AESCMX_1,
+    #[doc = "OFB"]
+    AESCMX_2,
+    #[doc = "CFB"]
+    AESCMX_3,
+}
+impl AESCMXW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            AESCMXW::AESCMX_0 => 0,
+            AESCMXW::AESCMX_1 => 1,
+            AESCMXW::AESCMX_2 => 2,
+            AESCMXW::AESCMX_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AESCMXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AESCMXW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: AESCMXW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "ECB"]
+    #[inline]
+    pub fn aescmx_0(self) -> &'a mut W {
+        self.variant(AESCMXW::AESCMX_0)
+    }
+    #[doc = "CBC"]
+    #[inline]
+    pub fn aescmx_1(self) -> &'a mut W {
+        self.variant(AESCMXW::AESCMX_1)
+    }
+    #[doc = "OFB"]
+    #[inline]
+    pub fn aescmx_2(self) -> &'a mut W {
+        self.variant(AESCMXW::AESCMX_2)
+    }
+    #[doc = "CFB"]
+    #[inline]
+    pub fn aescmx_3(self) -> &'a mut W {
+        self.variant(AESCMXW::AESCMX_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `AESSWRST`"]
+pub enum AESSWRSTW {
+    #[doc = "No reset"]
+    AESSWRST_0,
+    #[doc = "Reset AES accelerator module"]
+    AESSWRST_1,
+}
+impl AESSWRSTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            AESSWRSTW::AESSWRST_0 => false,
+            AESSWRSTW::AESSWRST_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AESSWRSTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AESSWRSTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: AESSWRSTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No reset"]
+    #[inline]
+    pub fn aesswrst_0(self) -> &'a mut W {
+        self.variant(AESSWRSTW::AESSWRST_0)
+    }
+    #[doc = "Reset AES accelerator module"]
+    #[inline]
+    pub fn aesswrst_1(self) -> &'a mut W {
+        self.variant(AESSWRSTW::AESSWRST_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `AESRDYIFG`"]
+pub enum AESRDYIFGW {
+    #[doc = "No interrupt pending"]
+    AESRDYIFG_0,
+    #[doc = "Interrupt pending"]
+    AESRDYIFG_1,
+}
+impl AESRDYIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            AESRDYIFGW::AESRDYIFG_0 => false,
+            AESRDYIFGW::AESRDYIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AESRDYIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AESRDYIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: AESRDYIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn aesrdyifg_0(self) -> &'a mut W {
+        self.variant(AESRDYIFGW::AESRDYIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn aesrdyifg_1(self) -> &'a mut W {
+        self.variant(AESRDYIFGW::AESRDYIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `AESERRFG`"]
+pub enum AESERRFGW {
+    #[doc = "No error"]
+    AESERRFG_0,
+    #[doc = "Error occurred"]
+    AESERRFG_1,
+}
+impl AESERRFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            AESERRFGW::AESERRFG_0 => false,
+            AESERRFGW::AESERRFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AESERRFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AESERRFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: AESERRFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No error"]
+    #[inline]
+    pub fn aeserrfg_0(self) -> &'a mut W {
+        self.variant(AESERRFGW::AESERRFG_0)
+    }
+    #[doc = "Error occurred"]
+    #[inline]
+    pub fn aeserrfg_1(self) -> &'a mut W {
+        self.variant(AESERRFGW::AESERRFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `AESRDYIE`"]
+pub enum AESRDYIEW {
+    #[doc = "Interrupt disabled"]
+    AESRDYIE_0,
+    #[doc = "Interrupt enabled"]
+    AESRDYIE_1,
+}
+impl AESRDYIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            AESRDYIEW::AESRDYIE_0 => false,
+            AESRDYIEW::AESRDYIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AESRDYIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AESRDYIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: AESRDYIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn aesrdyie_0(self) -> &'a mut W {
+        self.variant(AESRDYIEW::AESRDYIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn aesrdyie_1(self) -> &'a mut W {
+        self.variant(AESRDYIEW::AESRDYIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `AESCMEN`"]
+pub enum AESCMENW {
+    #[doc = "No DMA triggers are generated"]
+    AESCMEN_0,
+    #[doc = "DMA ciphermode support operation is enabled and the corresponding DMA triggers are generated"]
+    AESCMEN_1,
+}
+impl AESCMENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            AESCMENW::AESCMEN_0 => false,
+            AESCMENW::AESCMEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AESCMENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AESCMENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: AESCMENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No DMA triggers are generated"]
+    #[inline]
+    pub fn aescmen_0(self) -> &'a mut W {
+        self.variant(AESCMENW::AESCMEN_0)
+    }
+    #[doc = "DMA ciphermode support operation is enabled and the corresponding DMA triggers are generated"]
+    #[inline]
+    pub fn aescmen_1(self) -> &'a mut W {
+        self.variant(AESCMENW::AESCMEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:1 - AES operation"]
+    #[inline]
+    pub fn aesopx(&self) -> AESOPXR {
+        AESOPXR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bits 2:3 - AES key length"]
+    #[inline]
+    pub fn aesklx(&self) -> AESKLXR {
+        AESKLXR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bits 5:6 - AES cipher mode select"]
+    #[inline]
+    pub fn aescmx(&self) -> AESCMXR {
+        AESCMXR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 7 - AES software reset"]
+    #[inline]
+    pub fn aesswrst(&self) -> AESSWRSTR {
+        AESSWRSTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 8 - AES ready interrupt flag"]
+    #[inline]
+    pub fn aesrdyifg(&self) -> AESRDYIFGR {
+        AESRDYIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 11 - AES error flag"]
+    #[inline]
+    pub fn aeserrfg(&self) -> AESERRFGR {
+        AESERRFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 12 - AES ready interrupt enable"]
+    #[inline]
+    pub fn aesrdyie(&self) -> AESRDYIER {
+        AESRDYIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 15 - AES cipher mode enable"]
+    #[inline]
+    pub fn aescmen(&self) -> AESCMENR {
+        AESCMENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:1 - AES operation"]
+    #[inline]
+    pub fn aesopx(&mut self) -> _AESOPXW {
+        _AESOPXW { w: self }
+    }
+    #[doc = "Bits 2:3 - AES key length"]
+    #[inline]
+    pub fn aesklx(&mut self) -> _AESKLXW {
+        _AESKLXW { w: self }
+    }
+    #[doc = "Bits 5:6 - AES cipher mode select"]
+    #[inline]
+    pub fn aescmx(&mut self) -> _AESCMXW {
+        _AESCMXW { w: self }
+    }
+    #[doc = "Bit 7 - AES software reset"]
+    #[inline]
+    pub fn aesswrst(&mut self) -> _AESSWRSTW {
+        _AESSWRSTW { w: self }
+    }
+    #[doc = "Bit 8 - AES ready interrupt flag"]
+    #[inline]
+    pub fn aesrdyifg(&mut self) -> _AESRDYIFGW {
+        _AESRDYIFGW { w: self }
+    }
+    #[doc = "Bit 11 - AES error flag"]
+    #[inline]
+    pub fn aeserrfg(&mut self) -> _AESERRFGW {
+        _AESERRFGW { w: self }
+    }
+    #[doc = "Bit 12 - AES ready interrupt enable"]
+    #[inline]
+    pub fn aesrdyie(&mut self) -> _AESRDYIEW {
+        _AESRDYIEW { w: self }
+    }
+    #[doc = "Bit 15 - AES cipher mode enable"]
+    #[inline]
+    pub fn aescmen(&mut self) -> _AESCMENW {
+        _AESCMENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/aes256/aesactl1.rs b/example-source/msp432p401r/src/aes256/aesactl1.rs
new file mode 100644
index 0000000..a0330f5
--- /dev/null
+++ b/example-source/msp432p401r/src/aes256/aesactl1.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::AESACTL1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct AESBLKCNTXR {
+    bits: u8,
+}
+impl AESBLKCNTXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AESBLKCNTXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AESBLKCNTXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Cipher Block Counter"]
+    #[inline]
+    pub fn aesblkcntx(&self) -> AESBLKCNTXR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        AESBLKCNTXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Cipher Block Counter"]
+    #[inline]
+    pub fn aesblkcntx(&mut self) -> _AESBLKCNTXW {
+        _AESBLKCNTXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/aes256/aesadin.rs b/example-source/msp432p401r/src/aes256/aesadin.rs
new file mode 100644
index 0000000..5787499
--- /dev/null
+++ b/example-source/msp432p401r/src/aes256/aesadin.rs
@@ -0,0 +1,69 @@
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::AESADIN {
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AESDIN0XW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AESDIN0XW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AESDIN1XW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AESDIN1XW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - AES data in byte n when AESADIN is written as half-word"]
+    #[inline]
+    pub fn aesdin0x(&mut self) -> _AESDIN0XW {
+        _AESDIN0XW { w: self }
+    }
+    #[doc = "Bits 8:15 - AES data in byte n+1 when AESADIN is written as half-word"]
+    #[inline]
+    pub fn aesdin1x(&mut self) -> _AESDIN1XW {
+        _AESDIN1XW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/aes256/aesadout.rs b/example-source/msp432p401r/src/aes256/aesadout.rs
new file mode 100644
index 0000000..d3a3577
--- /dev/null
+++ b/example-source/msp432p401r/src/aes256/aesadout.rs
@@ -0,0 +1,69 @@
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::AESADOUT {
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AESDOUT0XW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AESDOUT0XW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AESDOUT1XW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AESDOUT1XW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - AES data out byte n when AESADOUT is read as half-word"]
+    #[inline]
+    pub fn aesdout0x(&mut self) -> _AESDOUT0XW {
+        _AESDOUT0XW { w: self }
+    }
+    #[doc = "Bits 8:15 - AES data out byte n+1 when AESADOUT is read as half-word"]
+    #[inline]
+    pub fn aesdout1x(&mut self) -> _AESDOUT1XW {
+        _AESDOUT1XW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/aes256/aesakey.rs b/example-source/msp432p401r/src/aes256/aesakey.rs
new file mode 100644
index 0000000..d59ba97
--- /dev/null
+++ b/example-source/msp432p401r/src/aes256/aesakey.rs
@@ -0,0 +1,69 @@
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::AESAKEY {
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AESKEY0XW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AESKEY0XW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AESKEY1XW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AESKEY1XW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - AES key byte n when AESAKEY is written as half-word"]
+    #[inline]
+    pub fn aeskey0x(&mut self) -> _AESKEY0XW {
+        _AESKEY0XW { w: self }
+    }
+    #[doc = "Bits 8:15 - AES key byte n+1 when AESAKEY is written as half-word"]
+    #[inline]
+    pub fn aeskey1x(&mut self) -> _AESKEY1XW {
+        _AESKEY1XW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/aes256/aesastat.rs b/example-source/msp432p401r/src/aes256/aesastat.rs
new file mode 100644
index 0000000..b6e04d6
--- /dev/null
+++ b/example-source/msp432p401r/src/aes256/aesastat.rs
@@ -0,0 +1,540 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::AESASTAT {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `AESBUSY`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum AESBUSYR {
+    #[doc = "Not busy"]
+    AESBUSY_0,
+    #[doc = "Busy"]
+    AESBUSY_1,
+}
+impl AESBUSYR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            AESBUSYR::AESBUSY_0 => false,
+            AESBUSYR::AESBUSY_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> AESBUSYR {
+        match value {
+            false => AESBUSYR::AESBUSY_0,
+            true => AESBUSYR::AESBUSY_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `AESBUSY_0`"]
+    #[inline]
+    pub fn is_aesbusy_0(&self) -> bool {
+        *self == AESBUSYR::AESBUSY_0
+    }
+    #[doc = "Checks if the value of the field is `AESBUSY_1`"]
+    #[inline]
+    pub fn is_aesbusy_1(&self) -> bool {
+        *self == AESBUSYR::AESBUSY_1
+    }
+}
+#[doc = "Possible values of the field `AESKEYWR`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum AESKEYWRR {
+    #[doc = "Not all bytes written"]
+    AESKEYWR_0,
+    #[doc = "All bytes written"]
+    AESKEYWR_1,
+}
+impl AESKEYWRR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            AESKEYWRR::AESKEYWR_0 => false,
+            AESKEYWRR::AESKEYWR_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> AESKEYWRR {
+        match value {
+            false => AESKEYWRR::AESKEYWR_0,
+            true => AESKEYWRR::AESKEYWR_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `AESKEYWR_0`"]
+    #[inline]
+    pub fn is_aeskeywr_0(&self) -> bool {
+        *self == AESKEYWRR::AESKEYWR_0
+    }
+    #[doc = "Checks if the value of the field is `AESKEYWR_1`"]
+    #[inline]
+    pub fn is_aeskeywr_1(&self) -> bool {
+        *self == AESKEYWRR::AESKEYWR_1
+    }
+}
+#[doc = "Possible values of the field `AESDINWR`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum AESDINWRR {
+    #[doc = "Not all bytes written"]
+    AESDINWR_0,
+    #[doc = "All bytes written"]
+    AESDINWR_1,
+}
+impl AESDINWRR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            AESDINWRR::AESDINWR_0 => false,
+            AESDINWRR::AESDINWR_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> AESDINWRR {
+        match value {
+            false => AESDINWRR::AESDINWR_0,
+            true => AESDINWRR::AESDINWR_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `AESDINWR_0`"]
+    #[inline]
+    pub fn is_aesdinwr_0(&self) -> bool {
+        *self == AESDINWRR::AESDINWR_0
+    }
+    #[doc = "Checks if the value of the field is `AESDINWR_1`"]
+    #[inline]
+    pub fn is_aesdinwr_1(&self) -> bool {
+        *self == AESDINWRR::AESDINWR_1
+    }
+}
+#[doc = "Possible values of the field `AESDOUTRD`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum AESDOUTRDR {
+    #[doc = "Not all bytes read"]
+    AESDOUTRD_0,
+    #[doc = "All bytes read"]
+    AESDOUTRD_1,
+}
+impl AESDOUTRDR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            AESDOUTRDR::AESDOUTRD_0 => false,
+            AESDOUTRDR::AESDOUTRD_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> AESDOUTRDR {
+        match value {
+            false => AESDOUTRDR::AESDOUTRD_0,
+            true => AESDOUTRDR::AESDOUTRD_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `AESDOUTRD_0`"]
+    #[inline]
+    pub fn is_aesdoutrd_0(&self) -> bool {
+        *self == AESDOUTRDR::AESDOUTRD_0
+    }
+    #[doc = "Checks if the value of the field is `AESDOUTRD_1`"]
+    #[inline]
+    pub fn is_aesdoutrd_1(&self) -> bool {
+        *self == AESDOUTRDR::AESDOUTRD_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct AESKEYCNTXR {
+    bits: u8,
+}
+impl AESKEYCNTXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct AESDINCNTXR {
+    bits: u8,
+}
+impl AESDINCNTXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct AESDOUTCNTXR {
+    bits: u8,
+}
+impl AESDOUTCNTXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Values that can be written to the field `AESBUSY`"]
+pub enum AESBUSYW {
+    #[doc = "Not busy"]
+    AESBUSY_0,
+    #[doc = "Busy"]
+    AESBUSY_1,
+}
+impl AESBUSYW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            AESBUSYW::AESBUSY_0 => false,
+            AESBUSYW::AESBUSY_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AESBUSYW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AESBUSYW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: AESBUSYW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Not busy"]
+    #[inline]
+    pub fn aesbusy_0(self) -> &'a mut W {
+        self.variant(AESBUSYW::AESBUSY_0)
+    }
+    #[doc = "Busy"]
+    #[inline]
+    pub fn aesbusy_1(self) -> &'a mut W {
+        self.variant(AESBUSYW::AESBUSY_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `AESKEYWR`"]
+pub enum AESKEYWRW {
+    #[doc = "Not all bytes written"]
+    AESKEYWR_0,
+    #[doc = "All bytes written"]
+    AESKEYWR_1,
+}
+impl AESKEYWRW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            AESKEYWRW::AESKEYWR_0 => false,
+            AESKEYWRW::AESKEYWR_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AESKEYWRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AESKEYWRW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: AESKEYWRW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Not all bytes written"]
+    #[inline]
+    pub fn aeskeywr_0(self) -> &'a mut W {
+        self.variant(AESKEYWRW::AESKEYWR_0)
+    }
+    #[doc = "All bytes written"]
+    #[inline]
+    pub fn aeskeywr_1(self) -> &'a mut W {
+        self.variant(AESKEYWRW::AESKEYWR_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `AESDINWR`"]
+pub enum AESDINWRW {
+    #[doc = "Not all bytes written"]
+    AESDINWR_0,
+    #[doc = "All bytes written"]
+    AESDINWR_1,
+}
+impl AESDINWRW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            AESDINWRW::AESDINWR_0 => false,
+            AESDINWRW::AESDINWR_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AESDINWRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AESDINWRW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: AESDINWRW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Not all bytes written"]
+    #[inline]
+    pub fn aesdinwr_0(self) -> &'a mut W {
+        self.variant(AESDINWRW::AESDINWR_0)
+    }
+    #[doc = "All bytes written"]
+    #[inline]
+    pub fn aesdinwr_1(self) -> &'a mut W {
+        self.variant(AESDINWRW::AESDINWR_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - AES accelerator module busy"]
+    #[inline]
+    pub fn aesbusy(&self) -> AESBUSYR {
+        AESBUSYR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - All 16 bytes written to AESAKEY"]
+    #[inline]
+    pub fn aeskeywr(&self) -> AESKEYWRR {
+        AESKEYWRR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - All 16 bytes written to AESADIN, AESAXDIN or AESAXIN"]
+    #[inline]
+    pub fn aesdinwr(&self) -> AESDINWRR {
+        AESDINWRR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - All 16 bytes read from AESADOUT"]
+    #[inline]
+    pub fn aesdoutrd(&self) -> AESDOUTRDR {
+        AESDOUTRDR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 4:7 - Bytes written via AESAKEY for AESKLx=00, half-words written via AESAKEY"]
+    #[inline]
+    pub fn aeskeycntx(&self) -> AESKEYCNTXR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        AESKEYCNTXR { bits }
+    }
+    #[doc = "Bits 8:11 - Bytes written via AESADIN, AESAXDIN or AESAXIN"]
+    #[inline]
+    pub fn aesdincntx(&self) -> AESDINCNTXR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        AESDINCNTXR { bits }
+    }
+    #[doc = "Bits 12:15 - Bytes read via AESADOUT"]
+    #[inline]
+    pub fn aesdoutcntx(&self) -> AESDOUTCNTXR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        AESDOUTCNTXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - AES accelerator module busy"]
+    #[inline]
+    pub fn aesbusy(&mut self) -> _AESBUSYW {
+        _AESBUSYW { w: self }
+    }
+    #[doc = "Bit 1 - All 16 bytes written to AESAKEY"]
+    #[inline]
+    pub fn aeskeywr(&mut self) -> _AESKEYWRW {
+        _AESKEYWRW { w: self }
+    }
+    #[doc = "Bit 2 - All 16 bytes written to AESADIN, AESAXDIN or AESAXIN"]
+    #[inline]
+    pub fn aesdinwr(&mut self) -> _AESDINWRW {
+        _AESDINWRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/aes256/aesaxdin.rs b/example-source/msp432p401r/src/aes256/aesaxdin.rs
new file mode 100644
index 0000000..1d1cd59
--- /dev/null
+++ b/example-source/msp432p401r/src/aes256/aesaxdin.rs
@@ -0,0 +1,69 @@
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::AESAXDIN {
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AESXDIN0XW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AESXDIN0XW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AESXDIN1XW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AESXDIN1XW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - AES data in byte n when AESAXDIN is written as half-word"]
+    #[inline]
+    pub fn aesxdin0x(&mut self) -> _AESXDIN0XW {
+        _AESXDIN0XW { w: self }
+    }
+    #[doc = "Bits 8:15 - AES data in byte n+1 when AESAXDIN is written as half-word"]
+    #[inline]
+    pub fn aesxdin1x(&mut self) -> _AESXDIN1XW {
+        _AESXDIN1XW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/aes256/aesaxin.rs b/example-source/msp432p401r/src/aes256/aesaxin.rs
new file mode 100644
index 0000000..c244572
--- /dev/null
+++ b/example-source/msp432p401r/src/aes256/aesaxin.rs
@@ -0,0 +1,69 @@
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::AESAXIN {
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AESXIN0XW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AESXIN0XW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AESXIN1XW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AESXIN1XW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - AES data in byte n when AESAXIN is written as half-word"]
+    #[inline]
+    pub fn aesxin0x(&mut self) -> _AESXIN0XW {
+        _AESXIN0XW { w: self }
+    }
+    #[doc = "Bits 8:15 - AES data in byte n+1 when AESAXIN is written as half-word"]
+    #[inline]
+    pub fn aesxin1x(&mut self) -> _AESXIN1XW {
+        _AESXIN1XW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/captio0.rs b/example-source/msp432p401r/src/captio0.rs
new file mode 100644
index 0000000..b77fb03
--- /dev/null
+++ b/example-source/msp432p401r/src/captio0.rs
@@ -0,0 +1,13 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    _reserved0: [u8; 14usize],
+    #[doc = "0x0e - Capacitive Touch IO x Control Register"]
+    pub captiox_ctl: CAPTIOXCTL,
+}
+#[doc = "Capacitive Touch IO x Control Register"]
+pub struct CAPTIOXCTL {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Capacitive Touch IO x Control Register"]
+pub mod captiox_ctl;
diff --git a/example-source/msp432p401r/src/captio0/captiox_ctl.rs b/example-source/msp432p401r/src/captio0/captiox_ctl.rs
new file mode 100644
index 0000000..b00e88f
--- /dev/null
+++ b/example-source/msp432p401r/src/captio0/captiox_ctl.rs
@@ -0,0 +1,783 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::CAPTIOXCTL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `CAPTIOPISELx`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CAPTIOPISELXR {
+    #[doc = "Px.0"]
+    CAPTIOPISELX_0,
+    #[doc = "Px.1"]
+    CAPTIOPISELX_1,
+    #[doc = "Px.2"]
+    CAPTIOPISELX_2,
+    #[doc = "Px.3"]
+    CAPTIOPISELX_3,
+    #[doc = "Px.4"]
+    CAPTIOPISELX_4,
+    #[doc = "Px.5"]
+    CAPTIOPISELX_5,
+    #[doc = "Px.6"]
+    CAPTIOPISELX_6,
+    #[doc = "Px.7"]
+    CAPTIOPISELX_7,
+}
+impl CAPTIOPISELXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            CAPTIOPISELXR::CAPTIOPISELX_0 => 0,
+            CAPTIOPISELXR::CAPTIOPISELX_1 => 1,
+            CAPTIOPISELXR::CAPTIOPISELX_2 => 2,
+            CAPTIOPISELXR::CAPTIOPISELX_3 => 3,
+            CAPTIOPISELXR::CAPTIOPISELX_4 => 4,
+            CAPTIOPISELXR::CAPTIOPISELX_5 => 5,
+            CAPTIOPISELXR::CAPTIOPISELX_6 => 6,
+            CAPTIOPISELXR::CAPTIOPISELX_7 => 7,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> CAPTIOPISELXR {
+        match value {
+            0 => CAPTIOPISELXR::CAPTIOPISELX_0,
+            1 => CAPTIOPISELXR::CAPTIOPISELX_1,
+            2 => CAPTIOPISELXR::CAPTIOPISELX_2,
+            3 => CAPTIOPISELXR::CAPTIOPISELX_3,
+            4 => CAPTIOPISELXR::CAPTIOPISELX_4,
+            5 => CAPTIOPISELXR::CAPTIOPISELX_5,
+            6 => CAPTIOPISELXR::CAPTIOPISELX_6,
+            7 => CAPTIOPISELXR::CAPTIOPISELX_7,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPISELX_0`"]
+    #[inline]
+    pub fn is_captiopiselx_0(&self) -> bool {
+        *self == CAPTIOPISELXR::CAPTIOPISELX_0
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPISELX_1`"]
+    #[inline]
+    pub fn is_captiopiselx_1(&self) -> bool {
+        *self == CAPTIOPISELXR::CAPTIOPISELX_1
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPISELX_2`"]
+    #[inline]
+    pub fn is_captiopiselx_2(&self) -> bool {
+        *self == CAPTIOPISELXR::CAPTIOPISELX_2
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPISELX_3`"]
+    #[inline]
+    pub fn is_captiopiselx_3(&self) -> bool {
+        *self == CAPTIOPISELXR::CAPTIOPISELX_3
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPISELX_4`"]
+    #[inline]
+    pub fn is_captiopiselx_4(&self) -> bool {
+        *self == CAPTIOPISELXR::CAPTIOPISELX_4
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPISELX_5`"]
+    #[inline]
+    pub fn is_captiopiselx_5(&self) -> bool {
+        *self == CAPTIOPISELXR::CAPTIOPISELX_5
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPISELX_6`"]
+    #[inline]
+    pub fn is_captiopiselx_6(&self) -> bool {
+        *self == CAPTIOPISELXR::CAPTIOPISELX_6
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPISELX_7`"]
+    #[inline]
+    pub fn is_captiopiselx_7(&self) -> bool {
+        *self == CAPTIOPISELXR::CAPTIOPISELX_7
+    }
+}
+#[doc = "Possible values of the field `CAPTIOPOSELx`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CAPTIOPOSELXR {
+    #[doc = "Px = PJ"]
+    CAPTIOPOSELX_0,
+    #[doc = "Px = P1"]
+    CAPTIOPOSELX_1,
+    #[doc = "Px = P2"]
+    CAPTIOPOSELX_2,
+    #[doc = "Px = P3"]
+    CAPTIOPOSELX_3,
+    #[doc = "Px = P4"]
+    CAPTIOPOSELX_4,
+    #[doc = "Px = P5"]
+    CAPTIOPOSELX_5,
+    #[doc = "Px = P6"]
+    CAPTIOPOSELX_6,
+    #[doc = "Px = P7"]
+    CAPTIOPOSELX_7,
+    #[doc = "Px = P8"]
+    CAPTIOPOSELX_8,
+    #[doc = "Px = P9"]
+    CAPTIOPOSELX_9,
+    #[doc = "Px = P10"]
+    CAPTIOPOSELX_10,
+    #[doc = "Px = P11"]
+    CAPTIOPOSELX_11,
+    #[doc = "Px = P12"]
+    CAPTIOPOSELX_12,
+    #[doc = "Px = P13"]
+    CAPTIOPOSELX_13,
+    #[doc = "Px = P14"]
+    CAPTIOPOSELX_14,
+    #[doc = "Px = P15"]
+    CAPTIOPOSELX_15,
+}
+impl CAPTIOPOSELXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            CAPTIOPOSELXR::CAPTIOPOSELX_0 => 0,
+            CAPTIOPOSELXR::CAPTIOPOSELX_1 => 1,
+            CAPTIOPOSELXR::CAPTIOPOSELX_2 => 2,
+            CAPTIOPOSELXR::CAPTIOPOSELX_3 => 3,
+            CAPTIOPOSELXR::CAPTIOPOSELX_4 => 4,
+            CAPTIOPOSELXR::CAPTIOPOSELX_5 => 5,
+            CAPTIOPOSELXR::CAPTIOPOSELX_6 => 6,
+            CAPTIOPOSELXR::CAPTIOPOSELX_7 => 7,
+            CAPTIOPOSELXR::CAPTIOPOSELX_8 => 8,
+            CAPTIOPOSELXR::CAPTIOPOSELX_9 => 9,
+            CAPTIOPOSELXR::CAPTIOPOSELX_10 => 10,
+            CAPTIOPOSELXR::CAPTIOPOSELX_11 => 11,
+            CAPTIOPOSELXR::CAPTIOPOSELX_12 => 12,
+            CAPTIOPOSELXR::CAPTIOPOSELX_13 => 13,
+            CAPTIOPOSELXR::CAPTIOPOSELX_14 => 14,
+            CAPTIOPOSELXR::CAPTIOPOSELX_15 => 15,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> CAPTIOPOSELXR {
+        match value {
+            0 => CAPTIOPOSELXR::CAPTIOPOSELX_0,
+            1 => CAPTIOPOSELXR::CAPTIOPOSELX_1,
+            2 => CAPTIOPOSELXR::CAPTIOPOSELX_2,
+            3 => CAPTIOPOSELXR::CAPTIOPOSELX_3,
+            4 => CAPTIOPOSELXR::CAPTIOPOSELX_4,
+            5 => CAPTIOPOSELXR::CAPTIOPOSELX_5,
+            6 => CAPTIOPOSELXR::CAPTIOPOSELX_6,
+            7 => CAPTIOPOSELXR::CAPTIOPOSELX_7,
+            8 => CAPTIOPOSELXR::CAPTIOPOSELX_8,
+            9 => CAPTIOPOSELXR::CAPTIOPOSELX_9,
+            10 => CAPTIOPOSELXR::CAPTIOPOSELX_10,
+            11 => CAPTIOPOSELXR::CAPTIOPOSELX_11,
+            12 => CAPTIOPOSELXR::CAPTIOPOSELX_12,
+            13 => CAPTIOPOSELXR::CAPTIOPOSELX_13,
+            14 => CAPTIOPOSELXR::CAPTIOPOSELX_14,
+            15 => CAPTIOPOSELXR::CAPTIOPOSELX_15,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_0`"]
+    #[inline]
+    pub fn is_captioposelx_0(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_0
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_1`"]
+    #[inline]
+    pub fn is_captioposelx_1(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_1
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_2`"]
+    #[inline]
+    pub fn is_captioposelx_2(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_2
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_3`"]
+    #[inline]
+    pub fn is_captioposelx_3(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_3
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_4`"]
+    #[inline]
+    pub fn is_captioposelx_4(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_4
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_5`"]
+    #[inline]
+    pub fn is_captioposelx_5(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_5
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_6`"]
+    #[inline]
+    pub fn is_captioposelx_6(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_6
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_7`"]
+    #[inline]
+    pub fn is_captioposelx_7(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_7
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_8`"]
+    #[inline]
+    pub fn is_captioposelx_8(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_8
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_9`"]
+    #[inline]
+    pub fn is_captioposelx_9(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_9
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_10`"]
+    #[inline]
+    pub fn is_captioposelx_10(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_10
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_11`"]
+    #[inline]
+    pub fn is_captioposelx_11(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_11
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_12`"]
+    #[inline]
+    pub fn is_captioposelx_12(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_12
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_13`"]
+    #[inline]
+    pub fn is_captioposelx_13(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_13
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_14`"]
+    #[inline]
+    pub fn is_captioposelx_14(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_14
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_15`"]
+    #[inline]
+    pub fn is_captioposelx_15(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_15
+    }
+}
+#[doc = "Possible values of the field `CAPTIOEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CAPTIOENR {
+    #[doc = "All Capacitive Touch IOs are disabled. Signal towards timers is 0."]
+    CAPTIOEN_0,
+    #[doc = "Selected Capacitive Touch IO is enabled"]
+    CAPTIOEN_1,
+}
+impl CAPTIOENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CAPTIOENR::CAPTIOEN_0 => false,
+            CAPTIOENR::CAPTIOEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CAPTIOENR {
+        match value {
+            false => CAPTIOENR::CAPTIOEN_0,
+            true => CAPTIOENR::CAPTIOEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOEN_0`"]
+    #[inline]
+    pub fn is_captioen_0(&self) -> bool {
+        *self == CAPTIOENR::CAPTIOEN_0
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOEN_1`"]
+    #[inline]
+    pub fn is_captioen_1(&self) -> bool {
+        *self == CAPTIOENR::CAPTIOEN_1
+    }
+}
+#[doc = "Possible values of the field `CAPTIOSTATE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CAPTIOSTATER {
+    #[doc = "Curent state 0 or Capacitive Touch IO is disabled"]
+    CAPTIOSTATE_0,
+    #[doc = "Current state 1"]
+    CAPTIOSTATE_1,
+}
+impl CAPTIOSTATER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CAPTIOSTATER::CAPTIOSTATE_0 => false,
+            CAPTIOSTATER::CAPTIOSTATE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CAPTIOSTATER {
+        match value {
+            false => CAPTIOSTATER::CAPTIOSTATE_0,
+            true => CAPTIOSTATER::CAPTIOSTATE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOSTATE_0`"]
+    #[inline]
+    pub fn is_captiostate_0(&self) -> bool {
+        *self == CAPTIOSTATER::CAPTIOSTATE_0
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOSTATE_1`"]
+    #[inline]
+    pub fn is_captiostate_1(&self) -> bool {
+        *self == CAPTIOSTATER::CAPTIOSTATE_1
+    }
+}
+#[doc = "Values that can be written to the field `CAPTIOPISELx`"]
+pub enum CAPTIOPISELXW {
+    #[doc = "Px.0"]
+    CAPTIOPISELX_0,
+    #[doc = "Px.1"]
+    CAPTIOPISELX_1,
+    #[doc = "Px.2"]
+    CAPTIOPISELX_2,
+    #[doc = "Px.3"]
+    CAPTIOPISELX_3,
+    #[doc = "Px.4"]
+    CAPTIOPISELX_4,
+    #[doc = "Px.5"]
+    CAPTIOPISELX_5,
+    #[doc = "Px.6"]
+    CAPTIOPISELX_6,
+    #[doc = "Px.7"]
+    CAPTIOPISELX_7,
+}
+impl CAPTIOPISELXW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            CAPTIOPISELXW::CAPTIOPISELX_0 => 0,
+            CAPTIOPISELXW::CAPTIOPISELX_1 => 1,
+            CAPTIOPISELXW::CAPTIOPISELX_2 => 2,
+            CAPTIOPISELXW::CAPTIOPISELX_3 => 3,
+            CAPTIOPISELXW::CAPTIOPISELX_4 => 4,
+            CAPTIOPISELXW::CAPTIOPISELX_5 => 5,
+            CAPTIOPISELXW::CAPTIOPISELX_6 => 6,
+            CAPTIOPISELXW::CAPTIOPISELX_7 => 7,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CAPTIOPISELXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CAPTIOPISELXW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CAPTIOPISELXW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Px.0"]
+    #[inline]
+    pub fn captiopiselx_0(self) -> &'a mut W {
+        self.variant(CAPTIOPISELXW::CAPTIOPISELX_0)
+    }
+    #[doc = "Px.1"]
+    #[inline]
+    pub fn captiopiselx_1(self) -> &'a mut W {
+        self.variant(CAPTIOPISELXW::CAPTIOPISELX_1)
+    }
+    #[doc = "Px.2"]
+    #[inline]
+    pub fn captiopiselx_2(self) -> &'a mut W {
+        self.variant(CAPTIOPISELXW::CAPTIOPISELX_2)
+    }
+    #[doc = "Px.3"]
+    #[inline]
+    pub fn captiopiselx_3(self) -> &'a mut W {
+        self.variant(CAPTIOPISELXW::CAPTIOPISELX_3)
+    }
+    #[doc = "Px.4"]
+    #[inline]
+    pub fn captiopiselx_4(self) -> &'a mut W {
+        self.variant(CAPTIOPISELXW::CAPTIOPISELX_4)
+    }
+    #[doc = "Px.5"]
+    #[inline]
+    pub fn captiopiselx_5(self) -> &'a mut W {
+        self.variant(CAPTIOPISELXW::CAPTIOPISELX_5)
+    }
+    #[doc = "Px.6"]
+    #[inline]
+    pub fn captiopiselx_6(self) -> &'a mut W {
+        self.variant(CAPTIOPISELXW::CAPTIOPISELX_6)
+    }
+    #[doc = "Px.7"]
+    #[inline]
+    pub fn captiopiselx_7(self) -> &'a mut W {
+        self.variant(CAPTIOPISELXW::CAPTIOPISELX_7)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CAPTIOPOSELx`"]
+pub enum CAPTIOPOSELXW {
+    #[doc = "Px = PJ"]
+    CAPTIOPOSELX_0,
+    #[doc = "Px = P1"]
+    CAPTIOPOSELX_1,
+    #[doc = "Px = P2"]
+    CAPTIOPOSELX_2,
+    #[doc = "Px = P3"]
+    CAPTIOPOSELX_3,
+    #[doc = "Px = P4"]
+    CAPTIOPOSELX_4,
+    #[doc = "Px = P5"]
+    CAPTIOPOSELX_5,
+    #[doc = "Px = P6"]
+    CAPTIOPOSELX_6,
+    #[doc = "Px = P7"]
+    CAPTIOPOSELX_7,
+    #[doc = "Px = P8"]
+    CAPTIOPOSELX_8,
+    #[doc = "Px = P9"]
+    CAPTIOPOSELX_9,
+    #[doc = "Px = P10"]
+    CAPTIOPOSELX_10,
+    #[doc = "Px = P11"]
+    CAPTIOPOSELX_11,
+    #[doc = "Px = P12"]
+    CAPTIOPOSELX_12,
+    #[doc = "Px = P13"]
+    CAPTIOPOSELX_13,
+    #[doc = "Px = P14"]
+    CAPTIOPOSELX_14,
+    #[doc = "Px = P15"]
+    CAPTIOPOSELX_15,
+}
+impl CAPTIOPOSELXW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            CAPTIOPOSELXW::CAPTIOPOSELX_0 => 0,
+            CAPTIOPOSELXW::CAPTIOPOSELX_1 => 1,
+            CAPTIOPOSELXW::CAPTIOPOSELX_2 => 2,
+            CAPTIOPOSELXW::CAPTIOPOSELX_3 => 3,
+            CAPTIOPOSELXW::CAPTIOPOSELX_4 => 4,
+            CAPTIOPOSELXW::CAPTIOPOSELX_5 => 5,
+            CAPTIOPOSELXW::CAPTIOPOSELX_6 => 6,
+            CAPTIOPOSELXW::CAPTIOPOSELX_7 => 7,
+            CAPTIOPOSELXW::CAPTIOPOSELX_8 => 8,
+            CAPTIOPOSELXW::CAPTIOPOSELX_9 => 9,
+            CAPTIOPOSELXW::CAPTIOPOSELX_10 => 10,
+            CAPTIOPOSELXW::CAPTIOPOSELX_11 => 11,
+            CAPTIOPOSELXW::CAPTIOPOSELX_12 => 12,
+            CAPTIOPOSELXW::CAPTIOPOSELX_13 => 13,
+            CAPTIOPOSELXW::CAPTIOPOSELX_14 => 14,
+            CAPTIOPOSELXW::CAPTIOPOSELX_15 => 15,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CAPTIOPOSELXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CAPTIOPOSELXW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CAPTIOPOSELXW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Px = PJ"]
+    #[inline]
+    pub fn captioposelx_0(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_0)
+    }
+    #[doc = "Px = P1"]
+    #[inline]
+    pub fn captioposelx_1(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_1)
+    }
+    #[doc = "Px = P2"]
+    #[inline]
+    pub fn captioposelx_2(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_2)
+    }
+    #[doc = "Px = P3"]
+    #[inline]
+    pub fn captioposelx_3(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_3)
+    }
+    #[doc = "Px = P4"]
+    #[inline]
+    pub fn captioposelx_4(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_4)
+    }
+    #[doc = "Px = P5"]
+    #[inline]
+    pub fn captioposelx_5(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_5)
+    }
+    #[doc = "Px = P6"]
+    #[inline]
+    pub fn captioposelx_6(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_6)
+    }
+    #[doc = "Px = P7"]
+    #[inline]
+    pub fn captioposelx_7(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_7)
+    }
+    #[doc = "Px = P8"]
+    #[inline]
+    pub fn captioposelx_8(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_8)
+    }
+    #[doc = "Px = P9"]
+    #[inline]
+    pub fn captioposelx_9(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_9)
+    }
+    #[doc = "Px = P10"]
+    #[inline]
+    pub fn captioposelx_10(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_10)
+    }
+    #[doc = "Px = P11"]
+    #[inline]
+    pub fn captioposelx_11(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_11)
+    }
+    #[doc = "Px = P12"]
+    #[inline]
+    pub fn captioposelx_12(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_12)
+    }
+    #[doc = "Px = P13"]
+    #[inline]
+    pub fn captioposelx_13(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_13)
+    }
+    #[doc = "Px = P14"]
+    #[inline]
+    pub fn captioposelx_14(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_14)
+    }
+    #[doc = "Px = P15"]
+    #[inline]
+    pub fn captioposelx_15(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_15)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CAPTIOEN`"]
+pub enum CAPTIOENW {
+    #[doc = "All Capacitive Touch IOs are disabled. Signal towards timers is 0."]
+    CAPTIOEN_0,
+    #[doc = "Selected Capacitive Touch IO is enabled"]
+    CAPTIOEN_1,
+}
+impl CAPTIOENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CAPTIOENW::CAPTIOEN_0 => false,
+            CAPTIOENW::CAPTIOEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CAPTIOENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CAPTIOENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CAPTIOENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "All Capacitive Touch IOs are disabled. Signal towards timers is 0."]
+    #[inline]
+    pub fn captioen_0(self) -> &'a mut W {
+        self.variant(CAPTIOENW::CAPTIOEN_0)
+    }
+    #[doc = "Selected Capacitive Touch IO is enabled"]
+    #[inline]
+    pub fn captioen_1(self) -> &'a mut W {
+        self.variant(CAPTIOENW::CAPTIOEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 1:3 - Capacitive Touch IO pin select"]
+    #[inline]
+    pub fn captiopiselx(&self) -> CAPTIOPISELXR {
+        CAPTIOPISELXR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bits 4:7 - Capacitive Touch IO port select"]
+    #[inline]
+    pub fn captioposelx(&self) -> CAPTIOPOSELXR {
+        CAPTIOPOSELXR::_from({
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 8 - Capacitive Touch IO enable"]
+    #[inline]
+    pub fn captioen(&self) -> CAPTIOENR {
+        CAPTIOENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 9 - Capacitive Touch IO state"]
+    #[inline]
+    pub fn captiostate(&self) -> CAPTIOSTATER {
+        CAPTIOSTATER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 1:3 - Capacitive Touch IO pin select"]
+    #[inline]
+    pub fn captiopiselx(&mut self) -> _CAPTIOPISELXW {
+        _CAPTIOPISELXW { w: self }
+    }
+    #[doc = "Bits 4:7 - Capacitive Touch IO port select"]
+    #[inline]
+    pub fn captioposelx(&mut self) -> _CAPTIOPOSELXW {
+        _CAPTIOPOSELXW { w: self }
+    }
+    #[doc = "Bit 8 - Capacitive Touch IO enable"]
+    #[inline]
+    pub fn captioen(&mut self) -> _CAPTIOENW {
+        _CAPTIOENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/captio1.rs b/example-source/msp432p401r/src/captio1.rs
new file mode 100644
index 0000000..b77fb03
--- /dev/null
+++ b/example-source/msp432p401r/src/captio1.rs
@@ -0,0 +1,13 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    _reserved0: [u8; 14usize],
+    #[doc = "0x0e - Capacitive Touch IO x Control Register"]
+    pub captiox_ctl: CAPTIOXCTL,
+}
+#[doc = "Capacitive Touch IO x Control Register"]
+pub struct CAPTIOXCTL {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Capacitive Touch IO x Control Register"]
+pub mod captiox_ctl;
diff --git a/example-source/msp432p401r/src/captio1/captiox_ctl.rs b/example-source/msp432p401r/src/captio1/captiox_ctl.rs
new file mode 100644
index 0000000..b00e88f
--- /dev/null
+++ b/example-source/msp432p401r/src/captio1/captiox_ctl.rs
@@ -0,0 +1,783 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::CAPTIOXCTL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `CAPTIOPISELx`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CAPTIOPISELXR {
+    #[doc = "Px.0"]
+    CAPTIOPISELX_0,
+    #[doc = "Px.1"]
+    CAPTIOPISELX_1,
+    #[doc = "Px.2"]
+    CAPTIOPISELX_2,
+    #[doc = "Px.3"]
+    CAPTIOPISELX_3,
+    #[doc = "Px.4"]
+    CAPTIOPISELX_4,
+    #[doc = "Px.5"]
+    CAPTIOPISELX_5,
+    #[doc = "Px.6"]
+    CAPTIOPISELX_6,
+    #[doc = "Px.7"]
+    CAPTIOPISELX_7,
+}
+impl CAPTIOPISELXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            CAPTIOPISELXR::CAPTIOPISELX_0 => 0,
+            CAPTIOPISELXR::CAPTIOPISELX_1 => 1,
+            CAPTIOPISELXR::CAPTIOPISELX_2 => 2,
+            CAPTIOPISELXR::CAPTIOPISELX_3 => 3,
+            CAPTIOPISELXR::CAPTIOPISELX_4 => 4,
+            CAPTIOPISELXR::CAPTIOPISELX_5 => 5,
+            CAPTIOPISELXR::CAPTIOPISELX_6 => 6,
+            CAPTIOPISELXR::CAPTIOPISELX_7 => 7,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> CAPTIOPISELXR {
+        match value {
+            0 => CAPTIOPISELXR::CAPTIOPISELX_0,
+            1 => CAPTIOPISELXR::CAPTIOPISELX_1,
+            2 => CAPTIOPISELXR::CAPTIOPISELX_2,
+            3 => CAPTIOPISELXR::CAPTIOPISELX_3,
+            4 => CAPTIOPISELXR::CAPTIOPISELX_4,
+            5 => CAPTIOPISELXR::CAPTIOPISELX_5,
+            6 => CAPTIOPISELXR::CAPTIOPISELX_6,
+            7 => CAPTIOPISELXR::CAPTIOPISELX_7,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPISELX_0`"]
+    #[inline]
+    pub fn is_captiopiselx_0(&self) -> bool {
+        *self == CAPTIOPISELXR::CAPTIOPISELX_0
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPISELX_1`"]
+    #[inline]
+    pub fn is_captiopiselx_1(&self) -> bool {
+        *self == CAPTIOPISELXR::CAPTIOPISELX_1
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPISELX_2`"]
+    #[inline]
+    pub fn is_captiopiselx_2(&self) -> bool {
+        *self == CAPTIOPISELXR::CAPTIOPISELX_2
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPISELX_3`"]
+    #[inline]
+    pub fn is_captiopiselx_3(&self) -> bool {
+        *self == CAPTIOPISELXR::CAPTIOPISELX_3
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPISELX_4`"]
+    #[inline]
+    pub fn is_captiopiselx_4(&self) -> bool {
+        *self == CAPTIOPISELXR::CAPTIOPISELX_4
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPISELX_5`"]
+    #[inline]
+    pub fn is_captiopiselx_5(&self) -> bool {
+        *self == CAPTIOPISELXR::CAPTIOPISELX_5
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPISELX_6`"]
+    #[inline]
+    pub fn is_captiopiselx_6(&self) -> bool {
+        *self == CAPTIOPISELXR::CAPTIOPISELX_6
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPISELX_7`"]
+    #[inline]
+    pub fn is_captiopiselx_7(&self) -> bool {
+        *self == CAPTIOPISELXR::CAPTIOPISELX_7
+    }
+}
+#[doc = "Possible values of the field `CAPTIOPOSELx`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CAPTIOPOSELXR {
+    #[doc = "Px = PJ"]
+    CAPTIOPOSELX_0,
+    #[doc = "Px = P1"]
+    CAPTIOPOSELX_1,
+    #[doc = "Px = P2"]
+    CAPTIOPOSELX_2,
+    #[doc = "Px = P3"]
+    CAPTIOPOSELX_3,
+    #[doc = "Px = P4"]
+    CAPTIOPOSELX_4,
+    #[doc = "Px = P5"]
+    CAPTIOPOSELX_5,
+    #[doc = "Px = P6"]
+    CAPTIOPOSELX_6,
+    #[doc = "Px = P7"]
+    CAPTIOPOSELX_7,
+    #[doc = "Px = P8"]
+    CAPTIOPOSELX_8,
+    #[doc = "Px = P9"]
+    CAPTIOPOSELX_9,
+    #[doc = "Px = P10"]
+    CAPTIOPOSELX_10,
+    #[doc = "Px = P11"]
+    CAPTIOPOSELX_11,
+    #[doc = "Px = P12"]
+    CAPTIOPOSELX_12,
+    #[doc = "Px = P13"]
+    CAPTIOPOSELX_13,
+    #[doc = "Px = P14"]
+    CAPTIOPOSELX_14,
+    #[doc = "Px = P15"]
+    CAPTIOPOSELX_15,
+}
+impl CAPTIOPOSELXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            CAPTIOPOSELXR::CAPTIOPOSELX_0 => 0,
+            CAPTIOPOSELXR::CAPTIOPOSELX_1 => 1,
+            CAPTIOPOSELXR::CAPTIOPOSELX_2 => 2,
+            CAPTIOPOSELXR::CAPTIOPOSELX_3 => 3,
+            CAPTIOPOSELXR::CAPTIOPOSELX_4 => 4,
+            CAPTIOPOSELXR::CAPTIOPOSELX_5 => 5,
+            CAPTIOPOSELXR::CAPTIOPOSELX_6 => 6,
+            CAPTIOPOSELXR::CAPTIOPOSELX_7 => 7,
+            CAPTIOPOSELXR::CAPTIOPOSELX_8 => 8,
+            CAPTIOPOSELXR::CAPTIOPOSELX_9 => 9,
+            CAPTIOPOSELXR::CAPTIOPOSELX_10 => 10,
+            CAPTIOPOSELXR::CAPTIOPOSELX_11 => 11,
+            CAPTIOPOSELXR::CAPTIOPOSELX_12 => 12,
+            CAPTIOPOSELXR::CAPTIOPOSELX_13 => 13,
+            CAPTIOPOSELXR::CAPTIOPOSELX_14 => 14,
+            CAPTIOPOSELXR::CAPTIOPOSELX_15 => 15,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> CAPTIOPOSELXR {
+        match value {
+            0 => CAPTIOPOSELXR::CAPTIOPOSELX_0,
+            1 => CAPTIOPOSELXR::CAPTIOPOSELX_1,
+            2 => CAPTIOPOSELXR::CAPTIOPOSELX_2,
+            3 => CAPTIOPOSELXR::CAPTIOPOSELX_3,
+            4 => CAPTIOPOSELXR::CAPTIOPOSELX_4,
+            5 => CAPTIOPOSELXR::CAPTIOPOSELX_5,
+            6 => CAPTIOPOSELXR::CAPTIOPOSELX_6,
+            7 => CAPTIOPOSELXR::CAPTIOPOSELX_7,
+            8 => CAPTIOPOSELXR::CAPTIOPOSELX_8,
+            9 => CAPTIOPOSELXR::CAPTIOPOSELX_9,
+            10 => CAPTIOPOSELXR::CAPTIOPOSELX_10,
+            11 => CAPTIOPOSELXR::CAPTIOPOSELX_11,
+            12 => CAPTIOPOSELXR::CAPTIOPOSELX_12,
+            13 => CAPTIOPOSELXR::CAPTIOPOSELX_13,
+            14 => CAPTIOPOSELXR::CAPTIOPOSELX_14,
+            15 => CAPTIOPOSELXR::CAPTIOPOSELX_15,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_0`"]
+    #[inline]
+    pub fn is_captioposelx_0(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_0
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_1`"]
+    #[inline]
+    pub fn is_captioposelx_1(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_1
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_2`"]
+    #[inline]
+    pub fn is_captioposelx_2(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_2
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_3`"]
+    #[inline]
+    pub fn is_captioposelx_3(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_3
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_4`"]
+    #[inline]
+    pub fn is_captioposelx_4(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_4
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_5`"]
+    #[inline]
+    pub fn is_captioposelx_5(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_5
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_6`"]
+    #[inline]
+    pub fn is_captioposelx_6(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_6
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_7`"]
+    #[inline]
+    pub fn is_captioposelx_7(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_7
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_8`"]
+    #[inline]
+    pub fn is_captioposelx_8(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_8
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_9`"]
+    #[inline]
+    pub fn is_captioposelx_9(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_9
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_10`"]
+    #[inline]
+    pub fn is_captioposelx_10(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_10
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_11`"]
+    #[inline]
+    pub fn is_captioposelx_11(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_11
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_12`"]
+    #[inline]
+    pub fn is_captioposelx_12(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_12
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_13`"]
+    #[inline]
+    pub fn is_captioposelx_13(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_13
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_14`"]
+    #[inline]
+    pub fn is_captioposelx_14(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_14
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOPOSELX_15`"]
+    #[inline]
+    pub fn is_captioposelx_15(&self) -> bool {
+        *self == CAPTIOPOSELXR::CAPTIOPOSELX_15
+    }
+}
+#[doc = "Possible values of the field `CAPTIOEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CAPTIOENR {
+    #[doc = "All Capacitive Touch IOs are disabled. Signal towards timers is 0."]
+    CAPTIOEN_0,
+    #[doc = "Selected Capacitive Touch IO is enabled"]
+    CAPTIOEN_1,
+}
+impl CAPTIOENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CAPTIOENR::CAPTIOEN_0 => false,
+            CAPTIOENR::CAPTIOEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CAPTIOENR {
+        match value {
+            false => CAPTIOENR::CAPTIOEN_0,
+            true => CAPTIOENR::CAPTIOEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOEN_0`"]
+    #[inline]
+    pub fn is_captioen_0(&self) -> bool {
+        *self == CAPTIOENR::CAPTIOEN_0
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOEN_1`"]
+    #[inline]
+    pub fn is_captioen_1(&self) -> bool {
+        *self == CAPTIOENR::CAPTIOEN_1
+    }
+}
+#[doc = "Possible values of the field `CAPTIOSTATE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CAPTIOSTATER {
+    #[doc = "Curent state 0 or Capacitive Touch IO is disabled"]
+    CAPTIOSTATE_0,
+    #[doc = "Current state 1"]
+    CAPTIOSTATE_1,
+}
+impl CAPTIOSTATER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CAPTIOSTATER::CAPTIOSTATE_0 => false,
+            CAPTIOSTATER::CAPTIOSTATE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CAPTIOSTATER {
+        match value {
+            false => CAPTIOSTATER::CAPTIOSTATE_0,
+            true => CAPTIOSTATER::CAPTIOSTATE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOSTATE_0`"]
+    #[inline]
+    pub fn is_captiostate_0(&self) -> bool {
+        *self == CAPTIOSTATER::CAPTIOSTATE_0
+    }
+    #[doc = "Checks if the value of the field is `CAPTIOSTATE_1`"]
+    #[inline]
+    pub fn is_captiostate_1(&self) -> bool {
+        *self == CAPTIOSTATER::CAPTIOSTATE_1
+    }
+}
+#[doc = "Values that can be written to the field `CAPTIOPISELx`"]
+pub enum CAPTIOPISELXW {
+    #[doc = "Px.0"]
+    CAPTIOPISELX_0,
+    #[doc = "Px.1"]
+    CAPTIOPISELX_1,
+    #[doc = "Px.2"]
+    CAPTIOPISELX_2,
+    #[doc = "Px.3"]
+    CAPTIOPISELX_3,
+    #[doc = "Px.4"]
+    CAPTIOPISELX_4,
+    #[doc = "Px.5"]
+    CAPTIOPISELX_5,
+    #[doc = "Px.6"]
+    CAPTIOPISELX_6,
+    #[doc = "Px.7"]
+    CAPTIOPISELX_7,
+}
+impl CAPTIOPISELXW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            CAPTIOPISELXW::CAPTIOPISELX_0 => 0,
+            CAPTIOPISELXW::CAPTIOPISELX_1 => 1,
+            CAPTIOPISELXW::CAPTIOPISELX_2 => 2,
+            CAPTIOPISELXW::CAPTIOPISELX_3 => 3,
+            CAPTIOPISELXW::CAPTIOPISELX_4 => 4,
+            CAPTIOPISELXW::CAPTIOPISELX_5 => 5,
+            CAPTIOPISELXW::CAPTIOPISELX_6 => 6,
+            CAPTIOPISELXW::CAPTIOPISELX_7 => 7,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CAPTIOPISELXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CAPTIOPISELXW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CAPTIOPISELXW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Px.0"]
+    #[inline]
+    pub fn captiopiselx_0(self) -> &'a mut W {
+        self.variant(CAPTIOPISELXW::CAPTIOPISELX_0)
+    }
+    #[doc = "Px.1"]
+    #[inline]
+    pub fn captiopiselx_1(self) -> &'a mut W {
+        self.variant(CAPTIOPISELXW::CAPTIOPISELX_1)
+    }
+    #[doc = "Px.2"]
+    #[inline]
+    pub fn captiopiselx_2(self) -> &'a mut W {
+        self.variant(CAPTIOPISELXW::CAPTIOPISELX_2)
+    }
+    #[doc = "Px.3"]
+    #[inline]
+    pub fn captiopiselx_3(self) -> &'a mut W {
+        self.variant(CAPTIOPISELXW::CAPTIOPISELX_3)
+    }
+    #[doc = "Px.4"]
+    #[inline]
+    pub fn captiopiselx_4(self) -> &'a mut W {
+        self.variant(CAPTIOPISELXW::CAPTIOPISELX_4)
+    }
+    #[doc = "Px.5"]
+    #[inline]
+    pub fn captiopiselx_5(self) -> &'a mut W {
+        self.variant(CAPTIOPISELXW::CAPTIOPISELX_5)
+    }
+    #[doc = "Px.6"]
+    #[inline]
+    pub fn captiopiselx_6(self) -> &'a mut W {
+        self.variant(CAPTIOPISELXW::CAPTIOPISELX_6)
+    }
+    #[doc = "Px.7"]
+    #[inline]
+    pub fn captiopiselx_7(self) -> &'a mut W {
+        self.variant(CAPTIOPISELXW::CAPTIOPISELX_7)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CAPTIOPOSELx`"]
+pub enum CAPTIOPOSELXW {
+    #[doc = "Px = PJ"]
+    CAPTIOPOSELX_0,
+    #[doc = "Px = P1"]
+    CAPTIOPOSELX_1,
+    #[doc = "Px = P2"]
+    CAPTIOPOSELX_2,
+    #[doc = "Px = P3"]
+    CAPTIOPOSELX_3,
+    #[doc = "Px = P4"]
+    CAPTIOPOSELX_4,
+    #[doc = "Px = P5"]
+    CAPTIOPOSELX_5,
+    #[doc = "Px = P6"]
+    CAPTIOPOSELX_6,
+    #[doc = "Px = P7"]
+    CAPTIOPOSELX_7,
+    #[doc = "Px = P8"]
+    CAPTIOPOSELX_8,
+    #[doc = "Px = P9"]
+    CAPTIOPOSELX_9,
+    #[doc = "Px = P10"]
+    CAPTIOPOSELX_10,
+    #[doc = "Px = P11"]
+    CAPTIOPOSELX_11,
+    #[doc = "Px = P12"]
+    CAPTIOPOSELX_12,
+    #[doc = "Px = P13"]
+    CAPTIOPOSELX_13,
+    #[doc = "Px = P14"]
+    CAPTIOPOSELX_14,
+    #[doc = "Px = P15"]
+    CAPTIOPOSELX_15,
+}
+impl CAPTIOPOSELXW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            CAPTIOPOSELXW::CAPTIOPOSELX_0 => 0,
+            CAPTIOPOSELXW::CAPTIOPOSELX_1 => 1,
+            CAPTIOPOSELXW::CAPTIOPOSELX_2 => 2,
+            CAPTIOPOSELXW::CAPTIOPOSELX_3 => 3,
+            CAPTIOPOSELXW::CAPTIOPOSELX_4 => 4,
+            CAPTIOPOSELXW::CAPTIOPOSELX_5 => 5,
+            CAPTIOPOSELXW::CAPTIOPOSELX_6 => 6,
+            CAPTIOPOSELXW::CAPTIOPOSELX_7 => 7,
+            CAPTIOPOSELXW::CAPTIOPOSELX_8 => 8,
+            CAPTIOPOSELXW::CAPTIOPOSELX_9 => 9,
+            CAPTIOPOSELXW::CAPTIOPOSELX_10 => 10,
+            CAPTIOPOSELXW::CAPTIOPOSELX_11 => 11,
+            CAPTIOPOSELXW::CAPTIOPOSELX_12 => 12,
+            CAPTIOPOSELXW::CAPTIOPOSELX_13 => 13,
+            CAPTIOPOSELXW::CAPTIOPOSELX_14 => 14,
+            CAPTIOPOSELXW::CAPTIOPOSELX_15 => 15,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CAPTIOPOSELXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CAPTIOPOSELXW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CAPTIOPOSELXW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Px = PJ"]
+    #[inline]
+    pub fn captioposelx_0(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_0)
+    }
+    #[doc = "Px = P1"]
+    #[inline]
+    pub fn captioposelx_1(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_1)
+    }
+    #[doc = "Px = P2"]
+    #[inline]
+    pub fn captioposelx_2(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_2)
+    }
+    #[doc = "Px = P3"]
+    #[inline]
+    pub fn captioposelx_3(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_3)
+    }
+    #[doc = "Px = P4"]
+    #[inline]
+    pub fn captioposelx_4(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_4)
+    }
+    #[doc = "Px = P5"]
+    #[inline]
+    pub fn captioposelx_5(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_5)
+    }
+    #[doc = "Px = P6"]
+    #[inline]
+    pub fn captioposelx_6(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_6)
+    }
+    #[doc = "Px = P7"]
+    #[inline]
+    pub fn captioposelx_7(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_7)
+    }
+    #[doc = "Px = P8"]
+    #[inline]
+    pub fn captioposelx_8(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_8)
+    }
+    #[doc = "Px = P9"]
+    #[inline]
+    pub fn captioposelx_9(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_9)
+    }
+    #[doc = "Px = P10"]
+    #[inline]
+    pub fn captioposelx_10(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_10)
+    }
+    #[doc = "Px = P11"]
+    #[inline]
+    pub fn captioposelx_11(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_11)
+    }
+    #[doc = "Px = P12"]
+    #[inline]
+    pub fn captioposelx_12(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_12)
+    }
+    #[doc = "Px = P13"]
+    #[inline]
+    pub fn captioposelx_13(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_13)
+    }
+    #[doc = "Px = P14"]
+    #[inline]
+    pub fn captioposelx_14(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_14)
+    }
+    #[doc = "Px = P15"]
+    #[inline]
+    pub fn captioposelx_15(self) -> &'a mut W {
+        self.variant(CAPTIOPOSELXW::CAPTIOPOSELX_15)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CAPTIOEN`"]
+pub enum CAPTIOENW {
+    #[doc = "All Capacitive Touch IOs are disabled. Signal towards timers is 0."]
+    CAPTIOEN_0,
+    #[doc = "Selected Capacitive Touch IO is enabled"]
+    CAPTIOEN_1,
+}
+impl CAPTIOENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CAPTIOENW::CAPTIOEN_0 => false,
+            CAPTIOENW::CAPTIOEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CAPTIOENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CAPTIOENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CAPTIOENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "All Capacitive Touch IOs are disabled. Signal towards timers is 0."]
+    #[inline]
+    pub fn captioen_0(self) -> &'a mut W {
+        self.variant(CAPTIOENW::CAPTIOEN_0)
+    }
+    #[doc = "Selected Capacitive Touch IO is enabled"]
+    #[inline]
+    pub fn captioen_1(self) -> &'a mut W {
+        self.variant(CAPTIOENW::CAPTIOEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 1:3 - Capacitive Touch IO pin select"]
+    #[inline]
+    pub fn captiopiselx(&self) -> CAPTIOPISELXR {
+        CAPTIOPISELXR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bits 4:7 - Capacitive Touch IO port select"]
+    #[inline]
+    pub fn captioposelx(&self) -> CAPTIOPOSELXR {
+        CAPTIOPOSELXR::_from({
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 8 - Capacitive Touch IO enable"]
+    #[inline]
+    pub fn captioen(&self) -> CAPTIOENR {
+        CAPTIOENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 9 - Capacitive Touch IO state"]
+    #[inline]
+    pub fn captiostate(&self) -> CAPTIOSTATER {
+        CAPTIOSTATER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 1:3 - Capacitive Touch IO pin select"]
+    #[inline]
+    pub fn captiopiselx(&mut self) -> _CAPTIOPISELXW {
+        _CAPTIOPISELXW { w: self }
+    }
+    #[doc = "Bits 4:7 - Capacitive Touch IO port select"]
+    #[inline]
+    pub fn captioposelx(&mut self) -> _CAPTIOPOSELXW {
+        _CAPTIOPOSELXW { w: self }
+    }
+    #[doc = "Bit 8 - Capacitive Touch IO enable"]
+    #[inline]
+    pub fn captioen(&mut self) -> _CAPTIOENW {
+        _CAPTIOENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/comp_e0.rs b/example-source/msp432p401r/src/comp_e0.rs
new file mode 100644
index 0000000..e551fe3
--- /dev/null
+++ b/example-source/msp432p401r/src/comp_e0.rs
@@ -0,0 +1,53 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - Comparator Control Register 0"]
+    pub cex_ctl0: CEXCTL0,
+    #[doc = "0x02 - Comparator Control Register 1"]
+    pub cex_ctl1: CEXCTL1,
+    #[doc = "0x04 - Comparator Control Register 2"]
+    pub cex_ctl2: CEXCTL2,
+    #[doc = "0x06 - Comparator Control Register 3"]
+    pub cex_ctl3: CEXCTL3,
+    _reserved0: [u8; 4usize],
+    #[doc = "0x0c - Comparator Interrupt Control Register"]
+    pub cex_int: CEXINT,
+    #[doc = "0x0e - Comparator Interrupt Vector Word Register"]
+    pub cex_iv: CEXIV,
+}
+#[doc = "Comparator Control Register 0"]
+pub struct CEXCTL0 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Comparator Control Register 0"]
+pub mod cex_ctl0;
+#[doc = "Comparator Control Register 1"]
+pub struct CEXCTL1 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Comparator Control Register 1"]
+pub mod cex_ctl1;
+#[doc = "Comparator Control Register 2"]
+pub struct CEXCTL2 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Comparator Control Register 2"]
+pub mod cex_ctl2;
+#[doc = "Comparator Control Register 3"]
+pub struct CEXCTL3 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Comparator Control Register 3"]
+pub mod cex_ctl3;
+#[doc = "Comparator Interrupt Control Register"]
+pub struct CEXINT {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Comparator Interrupt Control Register"]
+pub mod cex_int;
+#[doc = "Comparator Interrupt Vector Word Register"]
+pub struct CEXIV {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Comparator Interrupt Vector Word Register"]
+pub mod cex_iv;
diff --git a/example-source/msp432p401r/src/comp_e0/cex_ctl0.rs b/example-source/msp432p401r/src/comp_e0/cex_ctl0.rs
new file mode 100644
index 0000000..fabaa87
--- /dev/null
+++ b/example-source/msp432p401r/src/comp_e0/cex_ctl0.rs
@@ -0,0 +1,982 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::CEXCTL0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `CEIPSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEIPSELR {
+    #[doc = "Channel 0 selected"]
+    CEIPSEL_0,
+    #[doc = "Channel 1 selected"]
+    CEIPSEL_1,
+    #[doc = "Channel 2 selected"]
+    CEIPSEL_2,
+    #[doc = "Channel 3 selected"]
+    CEIPSEL_3,
+    #[doc = "Channel 4 selected"]
+    CEIPSEL_4,
+    #[doc = "Channel 5 selected"]
+    CEIPSEL_5,
+    #[doc = "Channel 6 selected"]
+    CEIPSEL_6,
+    #[doc = "Channel 7 selected"]
+    CEIPSEL_7,
+    #[doc = "Channel 8 selected"]
+    CEIPSEL_8,
+    #[doc = "Channel 9 selected"]
+    CEIPSEL_9,
+    #[doc = "Channel 10 selected"]
+    CEIPSEL_10,
+    #[doc = "Channel 11 selected"]
+    CEIPSEL_11,
+    #[doc = "Channel 12 selected"]
+    CEIPSEL_12,
+    #[doc = "Channel 13 selected"]
+    CEIPSEL_13,
+    #[doc = "Channel 14 selected"]
+    CEIPSEL_14,
+    #[doc = "Channel 15 selected"]
+    CEIPSEL_15,
+}
+impl CEIPSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            CEIPSELR::CEIPSEL_0 => 0,
+            CEIPSELR::CEIPSEL_1 => 1,
+            CEIPSELR::CEIPSEL_2 => 2,
+            CEIPSELR::CEIPSEL_3 => 3,
+            CEIPSELR::CEIPSEL_4 => 4,
+            CEIPSELR::CEIPSEL_5 => 5,
+            CEIPSELR::CEIPSEL_6 => 6,
+            CEIPSELR::CEIPSEL_7 => 7,
+            CEIPSELR::CEIPSEL_8 => 8,
+            CEIPSELR::CEIPSEL_9 => 9,
+            CEIPSELR::CEIPSEL_10 => 10,
+            CEIPSELR::CEIPSEL_11 => 11,
+            CEIPSELR::CEIPSEL_12 => 12,
+            CEIPSELR::CEIPSEL_13 => 13,
+            CEIPSELR::CEIPSEL_14 => 14,
+            CEIPSELR::CEIPSEL_15 => 15,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> CEIPSELR {
+        match value {
+            0 => CEIPSELR::CEIPSEL_0,
+            1 => CEIPSELR::CEIPSEL_1,
+            2 => CEIPSELR::CEIPSEL_2,
+            3 => CEIPSELR::CEIPSEL_3,
+            4 => CEIPSELR::CEIPSEL_4,
+            5 => CEIPSELR::CEIPSEL_5,
+            6 => CEIPSELR::CEIPSEL_6,
+            7 => CEIPSELR::CEIPSEL_7,
+            8 => CEIPSELR::CEIPSEL_8,
+            9 => CEIPSELR::CEIPSEL_9,
+            10 => CEIPSELR::CEIPSEL_10,
+            11 => CEIPSELR::CEIPSEL_11,
+            12 => CEIPSELR::CEIPSEL_12,
+            13 => CEIPSELR::CEIPSEL_13,
+            14 => CEIPSELR::CEIPSEL_14,
+            15 => CEIPSELR::CEIPSEL_15,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_0`"]
+    #[inline]
+    pub fn is_ceipsel_0(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_0
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_1`"]
+    #[inline]
+    pub fn is_ceipsel_1(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_1
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_2`"]
+    #[inline]
+    pub fn is_ceipsel_2(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_2
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_3`"]
+    #[inline]
+    pub fn is_ceipsel_3(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_3
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_4`"]
+    #[inline]
+    pub fn is_ceipsel_4(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_4
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_5`"]
+    #[inline]
+    pub fn is_ceipsel_5(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_5
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_6`"]
+    #[inline]
+    pub fn is_ceipsel_6(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_6
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_7`"]
+    #[inline]
+    pub fn is_ceipsel_7(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_7
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_8`"]
+    #[inline]
+    pub fn is_ceipsel_8(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_8
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_9`"]
+    #[inline]
+    pub fn is_ceipsel_9(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_9
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_10`"]
+    #[inline]
+    pub fn is_ceipsel_10(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_10
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_11`"]
+    #[inline]
+    pub fn is_ceipsel_11(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_11
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_12`"]
+    #[inline]
+    pub fn is_ceipsel_12(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_12
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_13`"]
+    #[inline]
+    pub fn is_ceipsel_13(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_13
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_14`"]
+    #[inline]
+    pub fn is_ceipsel_14(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_14
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_15`"]
+    #[inline]
+    pub fn is_ceipsel_15(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_15
+    }
+}
+#[doc = "Possible values of the field `CEIPEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEIPENR {
+    #[doc = "Selected analog input channel for V+ terminal is disabled"]
+    CEIPEN_0,
+    #[doc = "Selected analog input channel for V+ terminal is enabled"]
+    CEIPEN_1,
+}
+impl CEIPENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEIPENR::CEIPEN_0 => false,
+            CEIPENR::CEIPEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEIPENR {
+        match value {
+            false => CEIPENR::CEIPEN_0,
+            true => CEIPENR::CEIPEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEIPEN_0`"]
+    #[inline]
+    pub fn is_ceipen_0(&self) -> bool {
+        *self == CEIPENR::CEIPEN_0
+    }
+    #[doc = "Checks if the value of the field is `CEIPEN_1`"]
+    #[inline]
+    pub fn is_ceipen_1(&self) -> bool {
+        *self == CEIPENR::CEIPEN_1
+    }
+}
+#[doc = "Possible values of the field `CEIMSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEIMSELR {
+    #[doc = "Channel 0 selected"]
+    CEIMSEL_0,
+    #[doc = "Channel 1 selected"]
+    CEIMSEL_1,
+    #[doc = "Channel 2 selected"]
+    CEIMSEL_2,
+    #[doc = "Channel 3 selected"]
+    CEIMSEL_3,
+    #[doc = "Channel 4 selected"]
+    CEIMSEL_4,
+    #[doc = "Channel 5 selected"]
+    CEIMSEL_5,
+    #[doc = "Channel 6 selected"]
+    CEIMSEL_6,
+    #[doc = "Channel 7 selected"]
+    CEIMSEL_7,
+    #[doc = "Channel 8 selected"]
+    CEIMSEL_8,
+    #[doc = "Channel 9 selected"]
+    CEIMSEL_9,
+    #[doc = "Channel 10 selected"]
+    CEIMSEL_10,
+    #[doc = "Channel 11 selected"]
+    CEIMSEL_11,
+    #[doc = "Channel 12 selected"]
+    CEIMSEL_12,
+    #[doc = "Channel 13 selected"]
+    CEIMSEL_13,
+    #[doc = "Channel 14 selected"]
+    CEIMSEL_14,
+    #[doc = "Channel 15 selected"]
+    CEIMSEL_15,
+}
+impl CEIMSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            CEIMSELR::CEIMSEL_0 => 0,
+            CEIMSELR::CEIMSEL_1 => 1,
+            CEIMSELR::CEIMSEL_2 => 2,
+            CEIMSELR::CEIMSEL_3 => 3,
+            CEIMSELR::CEIMSEL_4 => 4,
+            CEIMSELR::CEIMSEL_5 => 5,
+            CEIMSELR::CEIMSEL_6 => 6,
+            CEIMSELR::CEIMSEL_7 => 7,
+            CEIMSELR::CEIMSEL_8 => 8,
+            CEIMSELR::CEIMSEL_9 => 9,
+            CEIMSELR::CEIMSEL_10 => 10,
+            CEIMSELR::CEIMSEL_11 => 11,
+            CEIMSELR::CEIMSEL_12 => 12,
+            CEIMSELR::CEIMSEL_13 => 13,
+            CEIMSELR::CEIMSEL_14 => 14,
+            CEIMSELR::CEIMSEL_15 => 15,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> CEIMSELR {
+        match value {
+            0 => CEIMSELR::CEIMSEL_0,
+            1 => CEIMSELR::CEIMSEL_1,
+            2 => CEIMSELR::CEIMSEL_2,
+            3 => CEIMSELR::CEIMSEL_3,
+            4 => CEIMSELR::CEIMSEL_4,
+            5 => CEIMSELR::CEIMSEL_5,
+            6 => CEIMSELR::CEIMSEL_6,
+            7 => CEIMSELR::CEIMSEL_7,
+            8 => CEIMSELR::CEIMSEL_8,
+            9 => CEIMSELR::CEIMSEL_9,
+            10 => CEIMSELR::CEIMSEL_10,
+            11 => CEIMSELR::CEIMSEL_11,
+            12 => CEIMSELR::CEIMSEL_12,
+            13 => CEIMSELR::CEIMSEL_13,
+            14 => CEIMSELR::CEIMSEL_14,
+            15 => CEIMSELR::CEIMSEL_15,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_0`"]
+    #[inline]
+    pub fn is_ceimsel_0(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_0
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_1`"]
+    #[inline]
+    pub fn is_ceimsel_1(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_1
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_2`"]
+    #[inline]
+    pub fn is_ceimsel_2(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_2
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_3`"]
+    #[inline]
+    pub fn is_ceimsel_3(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_3
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_4`"]
+    #[inline]
+    pub fn is_ceimsel_4(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_4
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_5`"]
+    #[inline]
+    pub fn is_ceimsel_5(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_5
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_6`"]
+    #[inline]
+    pub fn is_ceimsel_6(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_6
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_7`"]
+    #[inline]
+    pub fn is_ceimsel_7(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_7
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_8`"]
+    #[inline]
+    pub fn is_ceimsel_8(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_8
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_9`"]
+    #[inline]
+    pub fn is_ceimsel_9(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_9
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_10`"]
+    #[inline]
+    pub fn is_ceimsel_10(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_10
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_11`"]
+    #[inline]
+    pub fn is_ceimsel_11(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_11
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_12`"]
+    #[inline]
+    pub fn is_ceimsel_12(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_12
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_13`"]
+    #[inline]
+    pub fn is_ceimsel_13(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_13
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_14`"]
+    #[inline]
+    pub fn is_ceimsel_14(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_14
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_15`"]
+    #[inline]
+    pub fn is_ceimsel_15(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_15
+    }
+}
+#[doc = "Possible values of the field `CEIMEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEIMENR {
+    #[doc = "Selected analog input channel for V- terminal is disabled"]
+    CEIMEN_0,
+    #[doc = "Selected analog input channel for V- terminal is enabled"]
+    CEIMEN_1,
+}
+impl CEIMENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEIMENR::CEIMEN_0 => false,
+            CEIMENR::CEIMEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEIMENR {
+        match value {
+            false => CEIMENR::CEIMEN_0,
+            true => CEIMENR::CEIMEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEIMEN_0`"]
+    #[inline]
+    pub fn is_ceimen_0(&self) -> bool {
+        *self == CEIMENR::CEIMEN_0
+    }
+    #[doc = "Checks if the value of the field is `CEIMEN_1`"]
+    #[inline]
+    pub fn is_ceimen_1(&self) -> bool {
+        *self == CEIMENR::CEIMEN_1
+    }
+}
+#[doc = "Values that can be written to the field `CEIPSEL`"]
+pub enum CEIPSELW {
+    #[doc = "Channel 0 selected"]
+    CEIPSEL_0,
+    #[doc = "Channel 1 selected"]
+    CEIPSEL_1,
+    #[doc = "Channel 2 selected"]
+    CEIPSEL_2,
+    #[doc = "Channel 3 selected"]
+    CEIPSEL_3,
+    #[doc = "Channel 4 selected"]
+    CEIPSEL_4,
+    #[doc = "Channel 5 selected"]
+    CEIPSEL_5,
+    #[doc = "Channel 6 selected"]
+    CEIPSEL_6,
+    #[doc = "Channel 7 selected"]
+    CEIPSEL_7,
+    #[doc = "Channel 8 selected"]
+    CEIPSEL_8,
+    #[doc = "Channel 9 selected"]
+    CEIPSEL_9,
+    #[doc = "Channel 10 selected"]
+    CEIPSEL_10,
+    #[doc = "Channel 11 selected"]
+    CEIPSEL_11,
+    #[doc = "Channel 12 selected"]
+    CEIPSEL_12,
+    #[doc = "Channel 13 selected"]
+    CEIPSEL_13,
+    #[doc = "Channel 14 selected"]
+    CEIPSEL_14,
+    #[doc = "Channel 15 selected"]
+    CEIPSEL_15,
+}
+impl CEIPSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            CEIPSELW::CEIPSEL_0 => 0,
+            CEIPSELW::CEIPSEL_1 => 1,
+            CEIPSELW::CEIPSEL_2 => 2,
+            CEIPSELW::CEIPSEL_3 => 3,
+            CEIPSELW::CEIPSEL_4 => 4,
+            CEIPSELW::CEIPSEL_5 => 5,
+            CEIPSELW::CEIPSEL_6 => 6,
+            CEIPSELW::CEIPSEL_7 => 7,
+            CEIPSELW::CEIPSEL_8 => 8,
+            CEIPSELW::CEIPSEL_9 => 9,
+            CEIPSELW::CEIPSEL_10 => 10,
+            CEIPSELW::CEIPSEL_11 => 11,
+            CEIPSELW::CEIPSEL_12 => 12,
+            CEIPSELW::CEIPSEL_13 => 13,
+            CEIPSELW::CEIPSEL_14 => 14,
+            CEIPSELW::CEIPSEL_15 => 15,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEIPSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEIPSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEIPSELW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Channel 0 selected"]
+    #[inline]
+    pub fn ceipsel_0(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_0)
+    }
+    #[doc = "Channel 1 selected"]
+    #[inline]
+    pub fn ceipsel_1(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_1)
+    }
+    #[doc = "Channel 2 selected"]
+    #[inline]
+    pub fn ceipsel_2(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_2)
+    }
+    #[doc = "Channel 3 selected"]
+    #[inline]
+    pub fn ceipsel_3(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_3)
+    }
+    #[doc = "Channel 4 selected"]
+    #[inline]
+    pub fn ceipsel_4(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_4)
+    }
+    #[doc = "Channel 5 selected"]
+    #[inline]
+    pub fn ceipsel_5(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_5)
+    }
+    #[doc = "Channel 6 selected"]
+    #[inline]
+    pub fn ceipsel_6(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_6)
+    }
+    #[doc = "Channel 7 selected"]
+    #[inline]
+    pub fn ceipsel_7(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_7)
+    }
+    #[doc = "Channel 8 selected"]
+    #[inline]
+    pub fn ceipsel_8(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_8)
+    }
+    #[doc = "Channel 9 selected"]
+    #[inline]
+    pub fn ceipsel_9(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_9)
+    }
+    #[doc = "Channel 10 selected"]
+    #[inline]
+    pub fn ceipsel_10(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_10)
+    }
+    #[doc = "Channel 11 selected"]
+    #[inline]
+    pub fn ceipsel_11(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_11)
+    }
+    #[doc = "Channel 12 selected"]
+    #[inline]
+    pub fn ceipsel_12(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_12)
+    }
+    #[doc = "Channel 13 selected"]
+    #[inline]
+    pub fn ceipsel_13(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_13)
+    }
+    #[doc = "Channel 14 selected"]
+    #[inline]
+    pub fn ceipsel_14(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_14)
+    }
+    #[doc = "Channel 15 selected"]
+    #[inline]
+    pub fn ceipsel_15(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_15)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEIPEN`"]
+pub enum CEIPENW {
+    #[doc = "Selected analog input channel for V+ terminal is disabled"]
+    CEIPEN_0,
+    #[doc = "Selected analog input channel for V+ terminal is enabled"]
+    CEIPEN_1,
+}
+impl CEIPENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEIPENW::CEIPEN_0 => false,
+            CEIPENW::CEIPEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEIPENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEIPENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEIPENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Selected analog input channel for V+ terminal is disabled"]
+    #[inline]
+    pub fn ceipen_0(self) -> &'a mut W {
+        self.variant(CEIPENW::CEIPEN_0)
+    }
+    #[doc = "Selected analog input channel for V+ terminal is enabled"]
+    #[inline]
+    pub fn ceipen_1(self) -> &'a mut W {
+        self.variant(CEIPENW::CEIPEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEIMSEL`"]
+pub enum CEIMSELW {
+    #[doc = "Channel 0 selected"]
+    CEIMSEL_0,
+    #[doc = "Channel 1 selected"]
+    CEIMSEL_1,
+    #[doc = "Channel 2 selected"]
+    CEIMSEL_2,
+    #[doc = "Channel 3 selected"]
+    CEIMSEL_3,
+    #[doc = "Channel 4 selected"]
+    CEIMSEL_4,
+    #[doc = "Channel 5 selected"]
+    CEIMSEL_5,
+    #[doc = "Channel 6 selected"]
+    CEIMSEL_6,
+    #[doc = "Channel 7 selected"]
+    CEIMSEL_7,
+    #[doc = "Channel 8 selected"]
+    CEIMSEL_8,
+    #[doc = "Channel 9 selected"]
+    CEIMSEL_9,
+    #[doc = "Channel 10 selected"]
+    CEIMSEL_10,
+    #[doc = "Channel 11 selected"]
+    CEIMSEL_11,
+    #[doc = "Channel 12 selected"]
+    CEIMSEL_12,
+    #[doc = "Channel 13 selected"]
+    CEIMSEL_13,
+    #[doc = "Channel 14 selected"]
+    CEIMSEL_14,
+    #[doc = "Channel 15 selected"]
+    CEIMSEL_15,
+}
+impl CEIMSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            CEIMSELW::CEIMSEL_0 => 0,
+            CEIMSELW::CEIMSEL_1 => 1,
+            CEIMSELW::CEIMSEL_2 => 2,
+            CEIMSELW::CEIMSEL_3 => 3,
+            CEIMSELW::CEIMSEL_4 => 4,
+            CEIMSELW::CEIMSEL_5 => 5,
+            CEIMSELW::CEIMSEL_6 => 6,
+            CEIMSELW::CEIMSEL_7 => 7,
+            CEIMSELW::CEIMSEL_8 => 8,
+            CEIMSELW::CEIMSEL_9 => 9,
+            CEIMSELW::CEIMSEL_10 => 10,
+            CEIMSELW::CEIMSEL_11 => 11,
+            CEIMSELW::CEIMSEL_12 => 12,
+            CEIMSELW::CEIMSEL_13 => 13,
+            CEIMSELW::CEIMSEL_14 => 14,
+            CEIMSELW::CEIMSEL_15 => 15,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEIMSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEIMSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEIMSELW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Channel 0 selected"]
+    #[inline]
+    pub fn ceimsel_0(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_0)
+    }
+    #[doc = "Channel 1 selected"]
+    #[inline]
+    pub fn ceimsel_1(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_1)
+    }
+    #[doc = "Channel 2 selected"]
+    #[inline]
+    pub fn ceimsel_2(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_2)
+    }
+    #[doc = "Channel 3 selected"]
+    #[inline]
+    pub fn ceimsel_3(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_3)
+    }
+    #[doc = "Channel 4 selected"]
+    #[inline]
+    pub fn ceimsel_4(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_4)
+    }
+    #[doc = "Channel 5 selected"]
+    #[inline]
+    pub fn ceimsel_5(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_5)
+    }
+    #[doc = "Channel 6 selected"]
+    #[inline]
+    pub fn ceimsel_6(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_6)
+    }
+    #[doc = "Channel 7 selected"]
+    #[inline]
+    pub fn ceimsel_7(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_7)
+    }
+    #[doc = "Channel 8 selected"]
+    #[inline]
+    pub fn ceimsel_8(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_8)
+    }
+    #[doc = "Channel 9 selected"]
+    #[inline]
+    pub fn ceimsel_9(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_9)
+    }
+    #[doc = "Channel 10 selected"]
+    #[inline]
+    pub fn ceimsel_10(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_10)
+    }
+    #[doc = "Channel 11 selected"]
+    #[inline]
+    pub fn ceimsel_11(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_11)
+    }
+    #[doc = "Channel 12 selected"]
+    #[inline]
+    pub fn ceimsel_12(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_12)
+    }
+    #[doc = "Channel 13 selected"]
+    #[inline]
+    pub fn ceimsel_13(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_13)
+    }
+    #[doc = "Channel 14 selected"]
+    #[inline]
+    pub fn ceimsel_14(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_14)
+    }
+    #[doc = "Channel 15 selected"]
+    #[inline]
+    pub fn ceimsel_15(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_15)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEIMEN`"]
+pub enum CEIMENW {
+    #[doc = "Selected analog input channel for V- terminal is disabled"]
+    CEIMEN_0,
+    #[doc = "Selected analog input channel for V- terminal is enabled"]
+    CEIMEN_1,
+}
+impl CEIMENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEIMENW::CEIMEN_0 => false,
+            CEIMENW::CEIMEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEIMENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEIMENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEIMENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Selected analog input channel for V- terminal is disabled"]
+    #[inline]
+    pub fn ceimen_0(self) -> &'a mut W {
+        self.variant(CEIMENW::CEIMEN_0)
+    }
+    #[doc = "Selected analog input channel for V- terminal is enabled"]
+    #[inline]
+    pub fn ceimen_1(self) -> &'a mut W {
+        self.variant(CEIMENW::CEIMEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:3 - Channel input selected for the V+ terminal"]
+    #[inline]
+    pub fn ceipsel(&self) -> CEIPSELR {
+        CEIPSELR::_from({
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 7 - Channel input enable for the V+ terminal"]
+    #[inline]
+    pub fn ceipen(&self) -> CEIPENR {
+        CEIPENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 8:11 - Channel input selected for the - terminal"]
+    #[inline]
+    pub fn ceimsel(&self) -> CEIMSELR {
+        CEIMSELR::_from({
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 15 - Channel input enable for the - terminal"]
+    #[inline]
+    pub fn ceimen(&self) -> CEIMENR {
+        CEIMENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:3 - Channel input selected for the V+ terminal"]
+    #[inline]
+    pub fn ceipsel(&mut self) -> _CEIPSELW {
+        _CEIPSELW { w: self }
+    }
+    #[doc = "Bit 7 - Channel input enable for the V+ terminal"]
+    #[inline]
+    pub fn ceipen(&mut self) -> _CEIPENW {
+        _CEIPENW { w: self }
+    }
+    #[doc = "Bits 8:11 - Channel input selected for the - terminal"]
+    #[inline]
+    pub fn ceimsel(&mut self) -> _CEIMSELW {
+        _CEIMSELW { w: self }
+    }
+    #[doc = "Bit 15 - Channel input enable for the - terminal"]
+    #[inline]
+    pub fn ceimen(&mut self) -> _CEIMENW {
+        _CEIMENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/comp_e0/cex_ctl1.rs b/example-source/msp432p401r/src/comp_e0/cex_ctl1.rs
new file mode 100644
index 0000000..4b485b5
--- /dev/null
+++ b/example-source/msp432p401r/src/comp_e0/cex_ctl1.rs
@@ -0,0 +1,1271 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::CEXCTL1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CEOUTR {
+    bits: bool,
+}
+impl CEOUTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `CEOUTPOL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEOUTPOLR {
+    #[doc = "Noninverted"]
+    CEOUTPOL_0,
+    #[doc = "Inverted"]
+    CEOUTPOL_1,
+}
+impl CEOUTPOLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEOUTPOLR::CEOUTPOL_0 => false,
+            CEOUTPOLR::CEOUTPOL_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEOUTPOLR {
+        match value {
+            false => CEOUTPOLR::CEOUTPOL_0,
+            true => CEOUTPOLR::CEOUTPOL_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEOUTPOL_0`"]
+    #[inline]
+    pub fn is_ceoutpol_0(&self) -> bool {
+        *self == CEOUTPOLR::CEOUTPOL_0
+    }
+    #[doc = "Checks if the value of the field is `CEOUTPOL_1`"]
+    #[inline]
+    pub fn is_ceoutpol_1(&self) -> bool {
+        *self == CEOUTPOLR::CEOUTPOL_1
+    }
+}
+#[doc = "Possible values of the field `CEF`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEFR {
+    #[doc = "Comparator output is not filtered"]
+    CEF_0,
+    #[doc = "Comparator output is filtered"]
+    CEF_1,
+}
+impl CEFR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEFR::CEF_0 => false,
+            CEFR::CEF_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEFR {
+        match value {
+            false => CEFR::CEF_0,
+            true => CEFR::CEF_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEF_0`"]
+    #[inline]
+    pub fn is_cef_0(&self) -> bool {
+        *self == CEFR::CEF_0
+    }
+    #[doc = "Checks if the value of the field is `CEF_1`"]
+    #[inline]
+    pub fn is_cef_1(&self) -> bool {
+        *self == CEFR::CEF_1
+    }
+}
+#[doc = "Possible values of the field `CEIES`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEIESR {
+    #[doc = "Rising edge for CEIFG, falling edge for CEIIFG"]
+    CEIES_0,
+    #[doc = "Falling edge for CEIFG, rising edge for CEIIFG"]
+    CEIES_1,
+}
+impl CEIESR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEIESR::CEIES_0 => false,
+            CEIESR::CEIES_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEIESR {
+        match value {
+            false => CEIESR::CEIES_0,
+            true => CEIESR::CEIES_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEIES_0`"]
+    #[inline]
+    pub fn is_ceies_0(&self) -> bool {
+        *self == CEIESR::CEIES_0
+    }
+    #[doc = "Checks if the value of the field is `CEIES_1`"]
+    #[inline]
+    pub fn is_ceies_1(&self) -> bool {
+        *self == CEIESR::CEIES_1
+    }
+}
+#[doc = "Possible values of the field `CESHORT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CESHORTR {
+    #[doc = "Inputs not shorted"]
+    CESHORT_0,
+    #[doc = "Inputs shorted"]
+    CESHORT_1,
+}
+impl CESHORTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CESHORTR::CESHORT_0 => false,
+            CESHORTR::CESHORT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CESHORTR {
+        match value {
+            false => CESHORTR::CESHORT_0,
+            true => CESHORTR::CESHORT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CESHORT_0`"]
+    #[inline]
+    pub fn is_ceshort_0(&self) -> bool {
+        *self == CESHORTR::CESHORT_0
+    }
+    #[doc = "Checks if the value of the field is `CESHORT_1`"]
+    #[inline]
+    pub fn is_ceshort_1(&self) -> bool {
+        *self == CESHORTR::CESHORT_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CEEXR {
+    bits: bool,
+}
+impl CEEXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `CEFDLY`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEFDLYR {
+    #[doc = "Typical filter delay of TBD (450) ns"]
+    CEFDLY_0,
+    #[doc = "Typical filter delay of TBD (900) ns"]
+    CEFDLY_1,
+    #[doc = "Typical filter delay of TBD (1800) ns"]
+    CEFDLY_2,
+    #[doc = "Typical filter delay of TBD (3600) ns"]
+    CEFDLY_3,
+}
+impl CEFDLYR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            CEFDLYR::CEFDLY_0 => 0,
+            CEFDLYR::CEFDLY_1 => 1,
+            CEFDLYR::CEFDLY_2 => 2,
+            CEFDLYR::CEFDLY_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> CEFDLYR {
+        match value {
+            0 => CEFDLYR::CEFDLY_0,
+            1 => CEFDLYR::CEFDLY_1,
+            2 => CEFDLYR::CEFDLY_2,
+            3 => CEFDLYR::CEFDLY_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEFDLY_0`"]
+    #[inline]
+    pub fn is_cefdly_0(&self) -> bool {
+        *self == CEFDLYR::CEFDLY_0
+    }
+    #[doc = "Checks if the value of the field is `CEFDLY_1`"]
+    #[inline]
+    pub fn is_cefdly_1(&self) -> bool {
+        *self == CEFDLYR::CEFDLY_1
+    }
+    #[doc = "Checks if the value of the field is `CEFDLY_2`"]
+    #[inline]
+    pub fn is_cefdly_2(&self) -> bool {
+        *self == CEFDLYR::CEFDLY_2
+    }
+    #[doc = "Checks if the value of the field is `CEFDLY_3`"]
+    #[inline]
+    pub fn is_cefdly_3(&self) -> bool {
+        *self == CEFDLYR::CEFDLY_3
+    }
+}
+#[doc = "Possible values of the field `CEPWRMD`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPWRMDR {
+    #[doc = "High-speed mode"]
+    CEPWRMD_0,
+    #[doc = "Normal mode"]
+    CEPWRMD_1,
+    #[doc = "Ultra-low power mode"]
+    CEPWRMD_2,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl CEPWRMDR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            CEPWRMDR::CEPWRMD_0 => 0,
+            CEPWRMDR::CEPWRMD_1 => 1,
+            CEPWRMDR::CEPWRMD_2 => 2,
+            CEPWRMDR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> CEPWRMDR {
+        match value {
+            0 => CEPWRMDR::CEPWRMD_0,
+            1 => CEPWRMDR::CEPWRMD_1,
+            2 => CEPWRMDR::CEPWRMD_2,
+            i => CEPWRMDR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPWRMD_0`"]
+    #[inline]
+    pub fn is_cepwrmd_0(&self) -> bool {
+        *self == CEPWRMDR::CEPWRMD_0
+    }
+    #[doc = "Checks if the value of the field is `CEPWRMD_1`"]
+    #[inline]
+    pub fn is_cepwrmd_1(&self) -> bool {
+        *self == CEPWRMDR::CEPWRMD_1
+    }
+    #[doc = "Checks if the value of the field is `CEPWRMD_2`"]
+    #[inline]
+    pub fn is_cepwrmd_2(&self) -> bool {
+        *self == CEPWRMDR::CEPWRMD_2
+    }
+}
+#[doc = "Possible values of the field `CEON`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEONR {
+    #[doc = "Off"]
+    CEON_0,
+    #[doc = "On"]
+    CEON_1,
+}
+impl CEONR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEONR::CEON_0 => false,
+            CEONR::CEON_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEONR {
+        match value {
+            false => CEONR::CEON_0,
+            true => CEONR::CEON_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEON_0`"]
+    #[inline]
+    pub fn is_ceon_0(&self) -> bool {
+        *self == CEONR::CEON_0
+    }
+    #[doc = "Checks if the value of the field is `CEON_1`"]
+    #[inline]
+    pub fn is_ceon_1(&self) -> bool {
+        *self == CEONR::CEON_1
+    }
+}
+#[doc = "Possible values of the field `CEMRVL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEMRVLR {
+    #[doc = "VREF0 is selected if CERS = 00, 01, or 10"]
+    CEMRVL_0,
+    #[doc = "VREF1 is selected if CERS = 00, 01, or 10"]
+    CEMRVL_1,
+}
+impl CEMRVLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEMRVLR::CEMRVL_0 => false,
+            CEMRVLR::CEMRVL_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEMRVLR {
+        match value {
+            false => CEMRVLR::CEMRVL_0,
+            true => CEMRVLR::CEMRVL_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEMRVL_0`"]
+    #[inline]
+    pub fn is_cemrvl_0(&self) -> bool {
+        *self == CEMRVLR::CEMRVL_0
+    }
+    #[doc = "Checks if the value of the field is `CEMRVL_1`"]
+    #[inline]
+    pub fn is_cemrvl_1(&self) -> bool {
+        *self == CEMRVLR::CEMRVL_1
+    }
+}
+#[doc = "Possible values of the field `CEMRVS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEMRVSR {
+    #[doc = "Comparator output state selects between VREF0 or VREF1"]
+    CEMRVS_0,
+    #[doc = "CEMRVL selects between VREF0 or VREF1"]
+    CEMRVS_1,
+}
+impl CEMRVSR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEMRVSR::CEMRVS_0 => false,
+            CEMRVSR::CEMRVS_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEMRVSR {
+        match value {
+            false => CEMRVSR::CEMRVS_0,
+            true => CEMRVSR::CEMRVS_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEMRVS_0`"]
+    #[inline]
+    pub fn is_cemrvs_0(&self) -> bool {
+        *self == CEMRVSR::CEMRVS_0
+    }
+    #[doc = "Checks if the value of the field is `CEMRVS_1`"]
+    #[inline]
+    pub fn is_cemrvs_1(&self) -> bool {
+        *self == CEMRVSR::CEMRVS_1
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEOUTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEOUTW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEOUTPOL`"]
+pub enum CEOUTPOLW {
+    #[doc = "Noninverted"]
+    CEOUTPOL_0,
+    #[doc = "Inverted"]
+    CEOUTPOL_1,
+}
+impl CEOUTPOLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEOUTPOLW::CEOUTPOL_0 => false,
+            CEOUTPOLW::CEOUTPOL_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEOUTPOLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEOUTPOLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEOUTPOLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Noninverted"]
+    #[inline]
+    pub fn ceoutpol_0(self) -> &'a mut W {
+        self.variant(CEOUTPOLW::CEOUTPOL_0)
+    }
+    #[doc = "Inverted"]
+    #[inline]
+    pub fn ceoutpol_1(self) -> &'a mut W {
+        self.variant(CEOUTPOLW::CEOUTPOL_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEF`"]
+pub enum CEFW {
+    #[doc = "Comparator output is not filtered"]
+    CEF_0,
+    #[doc = "Comparator output is filtered"]
+    CEF_1,
+}
+impl CEFW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEFW::CEF_0 => false,
+            CEFW::CEF_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEFW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEFW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Comparator output is not filtered"]
+    #[inline]
+    pub fn cef_0(self) -> &'a mut W {
+        self.variant(CEFW::CEF_0)
+    }
+    #[doc = "Comparator output is filtered"]
+    #[inline]
+    pub fn cef_1(self) -> &'a mut W {
+        self.variant(CEFW::CEF_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEIES`"]
+pub enum CEIESW {
+    #[doc = "Rising edge for CEIFG, falling edge for CEIIFG"]
+    CEIES_0,
+    #[doc = "Falling edge for CEIFG, rising edge for CEIIFG"]
+    CEIES_1,
+}
+impl CEIESW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEIESW::CEIES_0 => false,
+            CEIESW::CEIES_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEIESW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEIESW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEIESW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Rising edge for CEIFG, falling edge for CEIIFG"]
+    #[inline]
+    pub fn ceies_0(self) -> &'a mut W {
+        self.variant(CEIESW::CEIES_0)
+    }
+    #[doc = "Falling edge for CEIFG, rising edge for CEIIFG"]
+    #[inline]
+    pub fn ceies_1(self) -> &'a mut W {
+        self.variant(CEIESW::CEIES_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CESHORT`"]
+pub enum CESHORTW {
+    #[doc = "Inputs not shorted"]
+    CESHORT_0,
+    #[doc = "Inputs shorted"]
+    CESHORT_1,
+}
+impl CESHORTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CESHORTW::CESHORT_0 => false,
+            CESHORTW::CESHORT_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CESHORTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CESHORTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CESHORTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Inputs not shorted"]
+    #[inline]
+    pub fn ceshort_0(self) -> &'a mut W {
+        self.variant(CESHORTW::CESHORT_0)
+    }
+    #[doc = "Inputs shorted"]
+    #[inline]
+    pub fn ceshort_1(self) -> &'a mut W {
+        self.variant(CESHORTW::CESHORT_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEEXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEEXW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEFDLY`"]
+pub enum CEFDLYW {
+    #[doc = "Typical filter delay of TBD (450) ns"]
+    CEFDLY_0,
+    #[doc = "Typical filter delay of TBD (900) ns"]
+    CEFDLY_1,
+    #[doc = "Typical filter delay of TBD (1800) ns"]
+    CEFDLY_2,
+    #[doc = "Typical filter delay of TBD (3600) ns"]
+    CEFDLY_3,
+}
+impl CEFDLYW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            CEFDLYW::CEFDLY_0 => 0,
+            CEFDLYW::CEFDLY_1 => 1,
+            CEFDLYW::CEFDLY_2 => 2,
+            CEFDLYW::CEFDLY_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEFDLYW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEFDLYW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEFDLYW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Typical filter delay of TBD (450) ns"]
+    #[inline]
+    pub fn cefdly_0(self) -> &'a mut W {
+        self.variant(CEFDLYW::CEFDLY_0)
+    }
+    #[doc = "Typical filter delay of TBD (900) ns"]
+    #[inline]
+    pub fn cefdly_1(self) -> &'a mut W {
+        self.variant(CEFDLYW::CEFDLY_1)
+    }
+    #[doc = "Typical filter delay of TBD (1800) ns"]
+    #[inline]
+    pub fn cefdly_2(self) -> &'a mut W {
+        self.variant(CEFDLYW::CEFDLY_2)
+    }
+    #[doc = "Typical filter delay of TBD (3600) ns"]
+    #[inline]
+    pub fn cefdly_3(self) -> &'a mut W {
+        self.variant(CEFDLYW::CEFDLY_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPWRMD`"]
+pub enum CEPWRMDW {
+    #[doc = "High-speed mode"]
+    CEPWRMD_0,
+    #[doc = "Normal mode"]
+    CEPWRMD_1,
+    #[doc = "Ultra-low power mode"]
+    CEPWRMD_2,
+}
+impl CEPWRMDW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            CEPWRMDW::CEPWRMD_0 => 0,
+            CEPWRMDW::CEPWRMD_1 => 1,
+            CEPWRMDW::CEPWRMD_2 => 2,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPWRMDW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPWRMDW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPWRMDW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "High-speed mode"]
+    #[inline]
+    pub fn cepwrmd_0(self) -> &'a mut W {
+        self.variant(CEPWRMDW::CEPWRMD_0)
+    }
+    #[doc = "Normal mode"]
+    #[inline]
+    pub fn cepwrmd_1(self) -> &'a mut W {
+        self.variant(CEPWRMDW::CEPWRMD_1)
+    }
+    #[doc = "Ultra-low power mode"]
+    #[inline]
+    pub fn cepwrmd_2(self) -> &'a mut W {
+        self.variant(CEPWRMDW::CEPWRMD_2)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEON`"]
+pub enum CEONW {
+    #[doc = "Off"]
+    CEON_0,
+    #[doc = "On"]
+    CEON_1,
+}
+impl CEONW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEONW::CEON_0 => false,
+            CEONW::CEON_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEONW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEONW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEONW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Off"]
+    #[inline]
+    pub fn ceon_0(self) -> &'a mut W {
+        self.variant(CEONW::CEON_0)
+    }
+    #[doc = "On"]
+    #[inline]
+    pub fn ceon_1(self) -> &'a mut W {
+        self.variant(CEONW::CEON_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEMRVL`"]
+pub enum CEMRVLW {
+    #[doc = "VREF0 is selected if CERS = 00, 01, or 10"]
+    CEMRVL_0,
+    #[doc = "VREF1 is selected if CERS = 00, 01, or 10"]
+    CEMRVL_1,
+}
+impl CEMRVLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEMRVLW::CEMRVL_0 => false,
+            CEMRVLW::CEMRVL_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEMRVLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEMRVLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEMRVLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "VREF0 is selected if CERS = 00, 01, or 10"]
+    #[inline]
+    pub fn cemrvl_0(self) -> &'a mut W {
+        self.variant(CEMRVLW::CEMRVL_0)
+    }
+    #[doc = "VREF1 is selected if CERS = 00, 01, or 10"]
+    #[inline]
+    pub fn cemrvl_1(self) -> &'a mut W {
+        self.variant(CEMRVLW::CEMRVL_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEMRVS`"]
+pub enum CEMRVSW {
+    #[doc = "Comparator output state selects between VREF0 or VREF1"]
+    CEMRVS_0,
+    #[doc = "CEMRVL selects between VREF0 or VREF1"]
+    CEMRVS_1,
+}
+impl CEMRVSW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEMRVSW::CEMRVS_0 => false,
+            CEMRVSW::CEMRVS_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEMRVSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEMRVSW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEMRVSW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Comparator output state selects between VREF0 or VREF1"]
+    #[inline]
+    pub fn cemrvs_0(self) -> &'a mut W {
+        self.variant(CEMRVSW::CEMRVS_0)
+    }
+    #[doc = "CEMRVL selects between VREF0 or VREF1"]
+    #[inline]
+    pub fn cemrvs_1(self) -> &'a mut W {
+        self.variant(CEMRVSW::CEMRVS_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Comparator output value"]
+    #[inline]
+    pub fn ceout(&self) -> CEOUTR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        };
+        CEOUTR { bits }
+    }
+    #[doc = "Bit 1 - Comparator output polarity"]
+    #[inline]
+    pub fn ceoutpol(&self) -> CEOUTPOLR {
+        CEOUTPOLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - Comparator output filter"]
+    #[inline]
+    pub fn cef(&self) -> CEFR {
+        CEFR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Interrupt edge select for CEIIFG and CEIFG"]
+    #[inline]
+    pub fn ceies(&self) -> CEIESR {
+        CEIESR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 4 - Input short"]
+    #[inline]
+    pub fn ceshort(&self) -> CESHORTR {
+        CESHORTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - Exchange"]
+    #[inline]
+    pub fn ceex(&self) -> CEEXR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        };
+        CEEXR { bits }
+    }
+    #[doc = "Bits 6:7 - Filter delay"]
+    #[inline]
+    pub fn cefdly(&self) -> CEFDLYR {
+        CEFDLYR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bits 8:9 - Power Mode"]
+    #[inline]
+    pub fn cepwrmd(&self) -> CEPWRMDR {
+        CEPWRMDR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 10 - Comparator On"]
+    #[inline]
+    pub fn ceon(&self) -> CEONR {
+        CEONR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 11 - This bit is valid of CEMRVS is set to 1"]
+    #[inline]
+    pub fn cemrvl(&self) -> CEMRVLR {
+        CEMRVLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 12 - This bit defines if the comparator output selects between VREF0 or VREF1 if CERS = 00, 01, or 10."]
+    #[inline]
+    pub fn cemrvs(&self) -> CEMRVSR {
+        CEMRVSR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Comparator output value"]
+    #[inline]
+    pub fn ceout(&mut self) -> _CEOUTW {
+        _CEOUTW { w: self }
+    }
+    #[doc = "Bit 1 - Comparator output polarity"]
+    #[inline]
+    pub fn ceoutpol(&mut self) -> _CEOUTPOLW {
+        _CEOUTPOLW { w: self }
+    }
+    #[doc = "Bit 2 - Comparator output filter"]
+    #[inline]
+    pub fn cef(&mut self) -> _CEFW {
+        _CEFW { w: self }
+    }
+    #[doc = "Bit 3 - Interrupt edge select for CEIIFG and CEIFG"]
+    #[inline]
+    pub fn ceies(&mut self) -> _CEIESW {
+        _CEIESW { w: self }
+    }
+    #[doc = "Bit 4 - Input short"]
+    #[inline]
+    pub fn ceshort(&mut self) -> _CESHORTW {
+        _CESHORTW { w: self }
+    }
+    #[doc = "Bit 5 - Exchange"]
+    #[inline]
+    pub fn ceex(&mut self) -> _CEEXW {
+        _CEEXW { w: self }
+    }
+    #[doc = "Bits 6:7 - Filter delay"]
+    #[inline]
+    pub fn cefdly(&mut self) -> _CEFDLYW {
+        _CEFDLYW { w: self }
+    }
+    #[doc = "Bits 8:9 - Power Mode"]
+    #[inline]
+    pub fn cepwrmd(&mut self) -> _CEPWRMDW {
+        _CEPWRMDW { w: self }
+    }
+    #[doc = "Bit 10 - Comparator On"]
+    #[inline]
+    pub fn ceon(&mut self) -> _CEONW {
+        _CEONW { w: self }
+    }
+    #[doc = "Bit 11 - This bit is valid of CEMRVS is set to 1"]
+    #[inline]
+    pub fn cemrvl(&mut self) -> _CEMRVLW {
+        _CEMRVLW { w: self }
+    }
+    #[doc = "Bit 12 - This bit defines if the comparator output selects between VREF0 or VREF1 if CERS = 00, 01, or 10."]
+    #[inline]
+    pub fn cemrvs(&mut self) -> _CEMRVSW {
+        _CEMRVSW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/comp_e0/cex_ctl2.rs b/example-source/msp432p401r/src/comp_e0/cex_ctl2.rs
new file mode 100644
index 0000000..44b7f1f
--- /dev/null
+++ b/example-source/msp432p401r/src/comp_e0/cex_ctl2.rs
@@ -0,0 +1,1798 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::CEXCTL2 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `CEREF0`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEREF0R {
+    #[doc = "Reference resistor tap for setting 0."]
+    CEREF0_0,
+    #[doc = "Reference resistor tap for setting 1."]
+    CEREF0_1,
+    #[doc = "Reference resistor tap for setting 2."]
+    CEREF0_2,
+    #[doc = "Reference resistor tap for setting 3."]
+    CEREF0_3,
+    #[doc = "Reference resistor tap for setting 4."]
+    CEREF0_4,
+    #[doc = "Reference resistor tap for setting 5."]
+    CEREF0_5,
+    #[doc = "Reference resistor tap for setting 6."]
+    CEREF0_6,
+    #[doc = "Reference resistor tap for setting 7."]
+    CEREF0_7,
+    #[doc = "Reference resistor tap for setting 8."]
+    CEREF0_8,
+    #[doc = "Reference resistor tap for setting 9."]
+    CEREF0_9,
+    #[doc = "Reference resistor tap for setting 10."]
+    CEREF0_10,
+    #[doc = "Reference resistor tap for setting 11."]
+    CEREF0_11,
+    #[doc = "Reference resistor tap for setting 12."]
+    CEREF0_12,
+    #[doc = "Reference resistor tap for setting 13."]
+    CEREF0_13,
+    #[doc = "Reference resistor tap for setting 14."]
+    CEREF0_14,
+    #[doc = "Reference resistor tap for setting 15."]
+    CEREF0_15,
+    #[doc = "Reference resistor tap for setting 16."]
+    CEREF0_16,
+    #[doc = "Reference resistor tap for setting 17."]
+    CEREF0_17,
+    #[doc = "Reference resistor tap for setting 18."]
+    CEREF0_18,
+    #[doc = "Reference resistor tap for setting 19."]
+    CEREF0_19,
+    #[doc = "Reference resistor tap for setting 20."]
+    CEREF0_20,
+    #[doc = "Reference resistor tap for setting 21."]
+    CEREF0_21,
+    #[doc = "Reference resistor tap for setting 22."]
+    CEREF0_22,
+    #[doc = "Reference resistor tap for setting 23."]
+    CEREF0_23,
+    #[doc = "Reference resistor tap for setting 24."]
+    CEREF0_24,
+    #[doc = "Reference resistor tap for setting 25."]
+    CEREF0_25,
+    #[doc = "Reference resistor tap for setting 26."]
+    CEREF0_26,
+    #[doc = "Reference resistor tap for setting 27."]
+    CEREF0_27,
+    #[doc = "Reference resistor tap for setting 28."]
+    CEREF0_28,
+    #[doc = "Reference resistor tap for setting 29."]
+    CEREF0_29,
+    #[doc = "Reference resistor tap for setting 30."]
+    CEREF0_30,
+    #[doc = "Reference resistor tap for setting 31."]
+    CEREF0_31,
+}
+impl CEREF0R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            CEREF0R::CEREF0_0 => 0,
+            CEREF0R::CEREF0_1 => 1,
+            CEREF0R::CEREF0_2 => 2,
+            CEREF0R::CEREF0_3 => 3,
+            CEREF0R::CEREF0_4 => 4,
+            CEREF0R::CEREF0_5 => 5,
+            CEREF0R::CEREF0_6 => 6,
+            CEREF0R::CEREF0_7 => 7,
+            CEREF0R::CEREF0_8 => 8,
+            CEREF0R::CEREF0_9 => 9,
+            CEREF0R::CEREF0_10 => 10,
+            CEREF0R::CEREF0_11 => 11,
+            CEREF0R::CEREF0_12 => 12,
+            CEREF0R::CEREF0_13 => 13,
+            CEREF0R::CEREF0_14 => 14,
+            CEREF0R::CEREF0_15 => 15,
+            CEREF0R::CEREF0_16 => 16,
+            CEREF0R::CEREF0_17 => 17,
+            CEREF0R::CEREF0_18 => 18,
+            CEREF0R::CEREF0_19 => 19,
+            CEREF0R::CEREF0_20 => 20,
+            CEREF0R::CEREF0_21 => 21,
+            CEREF0R::CEREF0_22 => 22,
+            CEREF0R::CEREF0_23 => 23,
+            CEREF0R::CEREF0_24 => 24,
+            CEREF0R::CEREF0_25 => 25,
+            CEREF0R::CEREF0_26 => 26,
+            CEREF0R::CEREF0_27 => 27,
+            CEREF0R::CEREF0_28 => 28,
+            CEREF0R::CEREF0_29 => 29,
+            CEREF0R::CEREF0_30 => 30,
+            CEREF0R::CEREF0_31 => 31,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> CEREF0R {
+        match value {
+            0 => CEREF0R::CEREF0_0,
+            1 => CEREF0R::CEREF0_1,
+            2 => CEREF0R::CEREF0_2,
+            3 => CEREF0R::CEREF0_3,
+            4 => CEREF0R::CEREF0_4,
+            5 => CEREF0R::CEREF0_5,
+            6 => CEREF0R::CEREF0_6,
+            7 => CEREF0R::CEREF0_7,
+            8 => CEREF0R::CEREF0_8,
+            9 => CEREF0R::CEREF0_9,
+            10 => CEREF0R::CEREF0_10,
+            11 => CEREF0R::CEREF0_11,
+            12 => CEREF0R::CEREF0_12,
+            13 => CEREF0R::CEREF0_13,
+            14 => CEREF0R::CEREF0_14,
+            15 => CEREF0R::CEREF0_15,
+            16 => CEREF0R::CEREF0_16,
+            17 => CEREF0R::CEREF0_17,
+            18 => CEREF0R::CEREF0_18,
+            19 => CEREF0R::CEREF0_19,
+            20 => CEREF0R::CEREF0_20,
+            21 => CEREF0R::CEREF0_21,
+            22 => CEREF0R::CEREF0_22,
+            23 => CEREF0R::CEREF0_23,
+            24 => CEREF0R::CEREF0_24,
+            25 => CEREF0R::CEREF0_25,
+            26 => CEREF0R::CEREF0_26,
+            27 => CEREF0R::CEREF0_27,
+            28 => CEREF0R::CEREF0_28,
+            29 => CEREF0R::CEREF0_29,
+            30 => CEREF0R::CEREF0_30,
+            31 => CEREF0R::CEREF0_31,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_0`"]
+    #[inline]
+    pub fn is_ceref0_0(&self) -> bool {
+        *self == CEREF0R::CEREF0_0
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_1`"]
+    #[inline]
+    pub fn is_ceref0_1(&self) -> bool {
+        *self == CEREF0R::CEREF0_1
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_2`"]
+    #[inline]
+    pub fn is_ceref0_2(&self) -> bool {
+        *self == CEREF0R::CEREF0_2
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_3`"]
+    #[inline]
+    pub fn is_ceref0_3(&self) -> bool {
+        *self == CEREF0R::CEREF0_3
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_4`"]
+    #[inline]
+    pub fn is_ceref0_4(&self) -> bool {
+        *self == CEREF0R::CEREF0_4
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_5`"]
+    #[inline]
+    pub fn is_ceref0_5(&self) -> bool {
+        *self == CEREF0R::CEREF0_5
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_6`"]
+    #[inline]
+    pub fn is_ceref0_6(&self) -> bool {
+        *self == CEREF0R::CEREF0_6
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_7`"]
+    #[inline]
+    pub fn is_ceref0_7(&self) -> bool {
+        *self == CEREF0R::CEREF0_7
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_8`"]
+    #[inline]
+    pub fn is_ceref0_8(&self) -> bool {
+        *self == CEREF0R::CEREF0_8
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_9`"]
+    #[inline]
+    pub fn is_ceref0_9(&self) -> bool {
+        *self == CEREF0R::CEREF0_9
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_10`"]
+    #[inline]
+    pub fn is_ceref0_10(&self) -> bool {
+        *self == CEREF0R::CEREF0_10
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_11`"]
+    #[inline]
+    pub fn is_ceref0_11(&self) -> bool {
+        *self == CEREF0R::CEREF0_11
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_12`"]
+    #[inline]
+    pub fn is_ceref0_12(&self) -> bool {
+        *self == CEREF0R::CEREF0_12
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_13`"]
+    #[inline]
+    pub fn is_ceref0_13(&self) -> bool {
+        *self == CEREF0R::CEREF0_13
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_14`"]
+    #[inline]
+    pub fn is_ceref0_14(&self) -> bool {
+        *self == CEREF0R::CEREF0_14
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_15`"]
+    #[inline]
+    pub fn is_ceref0_15(&self) -> bool {
+        *self == CEREF0R::CEREF0_15
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_16`"]
+    #[inline]
+    pub fn is_ceref0_16(&self) -> bool {
+        *self == CEREF0R::CEREF0_16
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_17`"]
+    #[inline]
+    pub fn is_ceref0_17(&self) -> bool {
+        *self == CEREF0R::CEREF0_17
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_18`"]
+    #[inline]
+    pub fn is_ceref0_18(&self) -> bool {
+        *self == CEREF0R::CEREF0_18
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_19`"]
+    #[inline]
+    pub fn is_ceref0_19(&self) -> bool {
+        *self == CEREF0R::CEREF0_19
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_20`"]
+    #[inline]
+    pub fn is_ceref0_20(&self) -> bool {
+        *self == CEREF0R::CEREF0_20
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_21`"]
+    #[inline]
+    pub fn is_ceref0_21(&self) -> bool {
+        *self == CEREF0R::CEREF0_21
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_22`"]
+    #[inline]
+    pub fn is_ceref0_22(&self) -> bool {
+        *self == CEREF0R::CEREF0_22
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_23`"]
+    #[inline]
+    pub fn is_ceref0_23(&self) -> bool {
+        *self == CEREF0R::CEREF0_23
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_24`"]
+    #[inline]
+    pub fn is_ceref0_24(&self) -> bool {
+        *self == CEREF0R::CEREF0_24
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_25`"]
+    #[inline]
+    pub fn is_ceref0_25(&self) -> bool {
+        *self == CEREF0R::CEREF0_25
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_26`"]
+    #[inline]
+    pub fn is_ceref0_26(&self) -> bool {
+        *self == CEREF0R::CEREF0_26
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_27`"]
+    #[inline]
+    pub fn is_ceref0_27(&self) -> bool {
+        *self == CEREF0R::CEREF0_27
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_28`"]
+    #[inline]
+    pub fn is_ceref0_28(&self) -> bool {
+        *self == CEREF0R::CEREF0_28
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_29`"]
+    #[inline]
+    pub fn is_ceref0_29(&self) -> bool {
+        *self == CEREF0R::CEREF0_29
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_30`"]
+    #[inline]
+    pub fn is_ceref0_30(&self) -> bool {
+        *self == CEREF0R::CEREF0_30
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_31`"]
+    #[inline]
+    pub fn is_ceref0_31(&self) -> bool {
+        *self == CEREF0R::CEREF0_31
+    }
+}
+#[doc = "Possible values of the field `CERSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CERSELR {
+    #[doc = "When CEEX = 0, VREF is applied to the V+ terminal; When CEEX = 1, VREF is applied to the V- terminal"]
+    CERSEL_0,
+    #[doc = "When CEEX = 0, VREF is applied to the V- terminal; When CEEX = 1, VREF is applied to the V+ terminal"]
+    CERSEL_1,
+}
+impl CERSELR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CERSELR::CERSEL_0 => false,
+            CERSELR::CERSEL_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CERSELR {
+        match value {
+            false => CERSELR::CERSEL_0,
+            true => CERSELR::CERSEL_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CERSEL_0`"]
+    #[inline]
+    pub fn is_cersel_0(&self) -> bool {
+        *self == CERSELR::CERSEL_0
+    }
+    #[doc = "Checks if the value of the field is `CERSEL_1`"]
+    #[inline]
+    pub fn is_cersel_1(&self) -> bool {
+        *self == CERSELR::CERSEL_1
+    }
+}
+#[doc = "Possible values of the field `CERS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CERSR {
+    #[doc = "No current is drawn by the reference circuitry"]
+    CERS_0,
+    #[doc = "VCC applied to the resistor ladder"]
+    CERS_1,
+    #[doc = "Shared reference voltage applied to the resistor ladder"]
+    CERS_2,
+    #[doc = "Shared reference voltage supplied to V(CREF). Resistor ladder is off"]
+    CERS_3,
+}
+impl CERSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            CERSR::CERS_0 => 0,
+            CERSR::CERS_1 => 1,
+            CERSR::CERS_2 => 2,
+            CERSR::CERS_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> CERSR {
+        match value {
+            0 => CERSR::CERS_0,
+            1 => CERSR::CERS_1,
+            2 => CERSR::CERS_2,
+            3 => CERSR::CERS_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `CERS_0`"]
+    #[inline]
+    pub fn is_cers_0(&self) -> bool {
+        *self == CERSR::CERS_0
+    }
+    #[doc = "Checks if the value of the field is `CERS_1`"]
+    #[inline]
+    pub fn is_cers_1(&self) -> bool {
+        *self == CERSR::CERS_1
+    }
+    #[doc = "Checks if the value of the field is `CERS_2`"]
+    #[inline]
+    pub fn is_cers_2(&self) -> bool {
+        *self == CERSR::CERS_2
+    }
+    #[doc = "Checks if the value of the field is `CERS_3`"]
+    #[inline]
+    pub fn is_cers_3(&self) -> bool {
+        *self == CERSR::CERS_3
+    }
+}
+#[doc = "Possible values of the field `CEREF1`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEREF1R {
+    #[doc = "Reference resistor tap for setting 0."]
+    CEREF1_0,
+    #[doc = "Reference resistor tap for setting 1."]
+    CEREF1_1,
+    #[doc = "Reference resistor tap for setting 2."]
+    CEREF1_2,
+    #[doc = "Reference resistor tap for setting 3."]
+    CEREF1_3,
+    #[doc = "Reference resistor tap for setting 4."]
+    CEREF1_4,
+    #[doc = "Reference resistor tap for setting 5."]
+    CEREF1_5,
+    #[doc = "Reference resistor tap for setting 6."]
+    CEREF1_6,
+    #[doc = "Reference resistor tap for setting 7."]
+    CEREF1_7,
+    #[doc = "Reference resistor tap for setting 8."]
+    CEREF1_8,
+    #[doc = "Reference resistor tap for setting 9."]
+    CEREF1_9,
+    #[doc = "Reference resistor tap for setting 10."]
+    CEREF1_10,
+    #[doc = "Reference resistor tap for setting 11."]
+    CEREF1_11,
+    #[doc = "Reference resistor tap for setting 12."]
+    CEREF1_12,
+    #[doc = "Reference resistor tap for setting 13."]
+    CEREF1_13,
+    #[doc = "Reference resistor tap for setting 14."]
+    CEREF1_14,
+    #[doc = "Reference resistor tap for setting 15."]
+    CEREF1_15,
+    #[doc = "Reference resistor tap for setting 16."]
+    CEREF1_16,
+    #[doc = "Reference resistor tap for setting 17."]
+    CEREF1_17,
+    #[doc = "Reference resistor tap for setting 18."]
+    CEREF1_18,
+    #[doc = "Reference resistor tap for setting 19."]
+    CEREF1_19,
+    #[doc = "Reference resistor tap for setting 20."]
+    CEREF1_20,
+    #[doc = "Reference resistor tap for setting 21."]
+    CEREF1_21,
+    #[doc = "Reference resistor tap for setting 22."]
+    CEREF1_22,
+    #[doc = "Reference resistor tap for setting 23."]
+    CEREF1_23,
+    #[doc = "Reference resistor tap for setting 24."]
+    CEREF1_24,
+    #[doc = "Reference resistor tap for setting 25."]
+    CEREF1_25,
+    #[doc = "Reference resistor tap for setting 26."]
+    CEREF1_26,
+    #[doc = "Reference resistor tap for setting 27."]
+    CEREF1_27,
+    #[doc = "Reference resistor tap for setting 28."]
+    CEREF1_28,
+    #[doc = "Reference resistor tap for setting 29."]
+    CEREF1_29,
+    #[doc = "Reference resistor tap for setting 30."]
+    CEREF1_30,
+    #[doc = "Reference resistor tap for setting 31."]
+    CEREF1_31,
+}
+impl CEREF1R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            CEREF1R::CEREF1_0 => 0,
+            CEREF1R::CEREF1_1 => 1,
+            CEREF1R::CEREF1_2 => 2,
+            CEREF1R::CEREF1_3 => 3,
+            CEREF1R::CEREF1_4 => 4,
+            CEREF1R::CEREF1_5 => 5,
+            CEREF1R::CEREF1_6 => 6,
+            CEREF1R::CEREF1_7 => 7,
+            CEREF1R::CEREF1_8 => 8,
+            CEREF1R::CEREF1_9 => 9,
+            CEREF1R::CEREF1_10 => 10,
+            CEREF1R::CEREF1_11 => 11,
+            CEREF1R::CEREF1_12 => 12,
+            CEREF1R::CEREF1_13 => 13,
+            CEREF1R::CEREF1_14 => 14,
+            CEREF1R::CEREF1_15 => 15,
+            CEREF1R::CEREF1_16 => 16,
+            CEREF1R::CEREF1_17 => 17,
+            CEREF1R::CEREF1_18 => 18,
+            CEREF1R::CEREF1_19 => 19,
+            CEREF1R::CEREF1_20 => 20,
+            CEREF1R::CEREF1_21 => 21,
+            CEREF1R::CEREF1_22 => 22,
+            CEREF1R::CEREF1_23 => 23,
+            CEREF1R::CEREF1_24 => 24,
+            CEREF1R::CEREF1_25 => 25,
+            CEREF1R::CEREF1_26 => 26,
+            CEREF1R::CEREF1_27 => 27,
+            CEREF1R::CEREF1_28 => 28,
+            CEREF1R::CEREF1_29 => 29,
+            CEREF1R::CEREF1_30 => 30,
+            CEREF1R::CEREF1_31 => 31,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> CEREF1R {
+        match value {
+            0 => CEREF1R::CEREF1_0,
+            1 => CEREF1R::CEREF1_1,
+            2 => CEREF1R::CEREF1_2,
+            3 => CEREF1R::CEREF1_3,
+            4 => CEREF1R::CEREF1_4,
+            5 => CEREF1R::CEREF1_5,
+            6 => CEREF1R::CEREF1_6,
+            7 => CEREF1R::CEREF1_7,
+            8 => CEREF1R::CEREF1_8,
+            9 => CEREF1R::CEREF1_9,
+            10 => CEREF1R::CEREF1_10,
+            11 => CEREF1R::CEREF1_11,
+            12 => CEREF1R::CEREF1_12,
+            13 => CEREF1R::CEREF1_13,
+            14 => CEREF1R::CEREF1_14,
+            15 => CEREF1R::CEREF1_15,
+            16 => CEREF1R::CEREF1_16,
+            17 => CEREF1R::CEREF1_17,
+            18 => CEREF1R::CEREF1_18,
+            19 => CEREF1R::CEREF1_19,
+            20 => CEREF1R::CEREF1_20,
+            21 => CEREF1R::CEREF1_21,
+            22 => CEREF1R::CEREF1_22,
+            23 => CEREF1R::CEREF1_23,
+            24 => CEREF1R::CEREF1_24,
+            25 => CEREF1R::CEREF1_25,
+            26 => CEREF1R::CEREF1_26,
+            27 => CEREF1R::CEREF1_27,
+            28 => CEREF1R::CEREF1_28,
+            29 => CEREF1R::CEREF1_29,
+            30 => CEREF1R::CEREF1_30,
+            31 => CEREF1R::CEREF1_31,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_0`"]
+    #[inline]
+    pub fn is_ceref1_0(&self) -> bool {
+        *self == CEREF1R::CEREF1_0
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_1`"]
+    #[inline]
+    pub fn is_ceref1_1(&self) -> bool {
+        *self == CEREF1R::CEREF1_1
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_2`"]
+    #[inline]
+    pub fn is_ceref1_2(&self) -> bool {
+        *self == CEREF1R::CEREF1_2
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_3`"]
+    #[inline]
+    pub fn is_ceref1_3(&self) -> bool {
+        *self == CEREF1R::CEREF1_3
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_4`"]
+    #[inline]
+    pub fn is_ceref1_4(&self) -> bool {
+        *self == CEREF1R::CEREF1_4
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_5`"]
+    #[inline]
+    pub fn is_ceref1_5(&self) -> bool {
+        *self == CEREF1R::CEREF1_5
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_6`"]
+    #[inline]
+    pub fn is_ceref1_6(&self) -> bool {
+        *self == CEREF1R::CEREF1_6
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_7`"]
+    #[inline]
+    pub fn is_ceref1_7(&self) -> bool {
+        *self == CEREF1R::CEREF1_7
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_8`"]
+    #[inline]
+    pub fn is_ceref1_8(&self) -> bool {
+        *self == CEREF1R::CEREF1_8
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_9`"]
+    #[inline]
+    pub fn is_ceref1_9(&self) -> bool {
+        *self == CEREF1R::CEREF1_9
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_10`"]
+    #[inline]
+    pub fn is_ceref1_10(&self) -> bool {
+        *self == CEREF1R::CEREF1_10
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_11`"]
+    #[inline]
+    pub fn is_ceref1_11(&self) -> bool {
+        *self == CEREF1R::CEREF1_11
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_12`"]
+    #[inline]
+    pub fn is_ceref1_12(&self) -> bool {
+        *self == CEREF1R::CEREF1_12
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_13`"]
+    #[inline]
+    pub fn is_ceref1_13(&self) -> bool {
+        *self == CEREF1R::CEREF1_13
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_14`"]
+    #[inline]
+    pub fn is_ceref1_14(&self) -> bool {
+        *self == CEREF1R::CEREF1_14
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_15`"]
+    #[inline]
+    pub fn is_ceref1_15(&self) -> bool {
+        *self == CEREF1R::CEREF1_15
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_16`"]
+    #[inline]
+    pub fn is_ceref1_16(&self) -> bool {
+        *self == CEREF1R::CEREF1_16
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_17`"]
+    #[inline]
+    pub fn is_ceref1_17(&self) -> bool {
+        *self == CEREF1R::CEREF1_17
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_18`"]
+    #[inline]
+    pub fn is_ceref1_18(&self) -> bool {
+        *self == CEREF1R::CEREF1_18
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_19`"]
+    #[inline]
+    pub fn is_ceref1_19(&self) -> bool {
+        *self == CEREF1R::CEREF1_19
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_20`"]
+    #[inline]
+    pub fn is_ceref1_20(&self) -> bool {
+        *self == CEREF1R::CEREF1_20
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_21`"]
+    #[inline]
+    pub fn is_ceref1_21(&self) -> bool {
+        *self == CEREF1R::CEREF1_21
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_22`"]
+    #[inline]
+    pub fn is_ceref1_22(&self) -> bool {
+        *self == CEREF1R::CEREF1_22
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_23`"]
+    #[inline]
+    pub fn is_ceref1_23(&self) -> bool {
+        *self == CEREF1R::CEREF1_23
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_24`"]
+    #[inline]
+    pub fn is_ceref1_24(&self) -> bool {
+        *self == CEREF1R::CEREF1_24
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_25`"]
+    #[inline]
+    pub fn is_ceref1_25(&self) -> bool {
+        *self == CEREF1R::CEREF1_25
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_26`"]
+    #[inline]
+    pub fn is_ceref1_26(&self) -> bool {
+        *self == CEREF1R::CEREF1_26
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_27`"]
+    #[inline]
+    pub fn is_ceref1_27(&self) -> bool {
+        *self == CEREF1R::CEREF1_27
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_28`"]
+    #[inline]
+    pub fn is_ceref1_28(&self) -> bool {
+        *self == CEREF1R::CEREF1_28
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_29`"]
+    #[inline]
+    pub fn is_ceref1_29(&self) -> bool {
+        *self == CEREF1R::CEREF1_29
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_30`"]
+    #[inline]
+    pub fn is_ceref1_30(&self) -> bool {
+        *self == CEREF1R::CEREF1_30
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_31`"]
+    #[inline]
+    pub fn is_ceref1_31(&self) -> bool {
+        *self == CEREF1R::CEREF1_31
+    }
+}
+#[doc = "Possible values of the field `CEREFL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEREFLR {
+    #[doc = "Reference amplifier is disabled. No reference voltage is requested"]
+    CEREFL_0,
+    #[doc = "1.2 V is selected as shared reference voltage input"]
+    CEREFL_1,
+    #[doc = "2.0 V is selected as shared reference voltage input"]
+    CEREFL_2,
+    #[doc = "2.5 V is selected as shared reference voltage input"]
+    CEREFL_3,
+}
+impl CEREFLR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            CEREFLR::CEREFL_0 => 0,
+            CEREFLR::CEREFL_1 => 1,
+            CEREFLR::CEREFL_2 => 2,
+            CEREFLR::CEREFL_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> CEREFLR {
+        match value {
+            0 => CEREFLR::CEREFL_0,
+            1 => CEREFLR::CEREFL_1,
+            2 => CEREFLR::CEREFL_2,
+            3 => CEREFLR::CEREFL_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEREFL_0`"]
+    #[inline]
+    pub fn is_cerefl_0(&self) -> bool {
+        *self == CEREFLR::CEREFL_0
+    }
+    #[doc = "Checks if the value of the field is `CEREFL_1`"]
+    #[inline]
+    pub fn is_cerefl_1(&self) -> bool {
+        *self == CEREFLR::CEREFL_1
+    }
+    #[doc = "Checks if the value of the field is `CEREFL_2`"]
+    #[inline]
+    pub fn is_cerefl_2(&self) -> bool {
+        *self == CEREFLR::CEREFL_2
+    }
+    #[doc = "Checks if the value of the field is `CEREFL_3`"]
+    #[inline]
+    pub fn is_cerefl_3(&self) -> bool {
+        *self == CEREFLR::CEREFL_3
+    }
+}
+#[doc = "Possible values of the field `CEREFACC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEREFACCR {
+    #[doc = "Static mode"]
+    CEREFACC_0,
+    #[doc = "Clocked (low power, low accuracy) mode"]
+    CEREFACC_1,
+}
+impl CEREFACCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEREFACCR::CEREFACC_0 => false,
+            CEREFACCR::CEREFACC_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEREFACCR {
+        match value {
+            false => CEREFACCR::CEREFACC_0,
+            true => CEREFACCR::CEREFACC_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEREFACC_0`"]
+    #[inline]
+    pub fn is_cerefacc_0(&self) -> bool {
+        *self == CEREFACCR::CEREFACC_0
+    }
+    #[doc = "Checks if the value of the field is `CEREFACC_1`"]
+    #[inline]
+    pub fn is_cerefacc_1(&self) -> bool {
+        *self == CEREFACCR::CEREFACC_1
+    }
+}
+#[doc = "Values that can be written to the field `CEREF0`"]
+pub enum CEREF0W {
+    #[doc = "Reference resistor tap for setting 0."]
+    CEREF0_0,
+    #[doc = "Reference resistor tap for setting 1."]
+    CEREF0_1,
+    #[doc = "Reference resistor tap for setting 2."]
+    CEREF0_2,
+    #[doc = "Reference resistor tap for setting 3."]
+    CEREF0_3,
+    #[doc = "Reference resistor tap for setting 4."]
+    CEREF0_4,
+    #[doc = "Reference resistor tap for setting 5."]
+    CEREF0_5,
+    #[doc = "Reference resistor tap for setting 6."]
+    CEREF0_6,
+    #[doc = "Reference resistor tap for setting 7."]
+    CEREF0_7,
+    #[doc = "Reference resistor tap for setting 8."]
+    CEREF0_8,
+    #[doc = "Reference resistor tap for setting 9."]
+    CEREF0_9,
+    #[doc = "Reference resistor tap for setting 10."]
+    CEREF0_10,
+    #[doc = "Reference resistor tap for setting 11."]
+    CEREF0_11,
+    #[doc = "Reference resistor tap for setting 12."]
+    CEREF0_12,
+    #[doc = "Reference resistor tap for setting 13."]
+    CEREF0_13,
+    #[doc = "Reference resistor tap for setting 14."]
+    CEREF0_14,
+    #[doc = "Reference resistor tap for setting 15."]
+    CEREF0_15,
+    #[doc = "Reference resistor tap for setting 16."]
+    CEREF0_16,
+    #[doc = "Reference resistor tap for setting 17."]
+    CEREF0_17,
+    #[doc = "Reference resistor tap for setting 18."]
+    CEREF0_18,
+    #[doc = "Reference resistor tap for setting 19."]
+    CEREF0_19,
+    #[doc = "Reference resistor tap for setting 20."]
+    CEREF0_20,
+    #[doc = "Reference resistor tap for setting 21."]
+    CEREF0_21,
+    #[doc = "Reference resistor tap for setting 22."]
+    CEREF0_22,
+    #[doc = "Reference resistor tap for setting 23."]
+    CEREF0_23,
+    #[doc = "Reference resistor tap for setting 24."]
+    CEREF0_24,
+    #[doc = "Reference resistor tap for setting 25."]
+    CEREF0_25,
+    #[doc = "Reference resistor tap for setting 26."]
+    CEREF0_26,
+    #[doc = "Reference resistor tap for setting 27."]
+    CEREF0_27,
+    #[doc = "Reference resistor tap for setting 28."]
+    CEREF0_28,
+    #[doc = "Reference resistor tap for setting 29."]
+    CEREF0_29,
+    #[doc = "Reference resistor tap for setting 30."]
+    CEREF0_30,
+    #[doc = "Reference resistor tap for setting 31."]
+    CEREF0_31,
+}
+impl CEREF0W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            CEREF0W::CEREF0_0 => 0,
+            CEREF0W::CEREF0_1 => 1,
+            CEREF0W::CEREF0_2 => 2,
+            CEREF0W::CEREF0_3 => 3,
+            CEREF0W::CEREF0_4 => 4,
+            CEREF0W::CEREF0_5 => 5,
+            CEREF0W::CEREF0_6 => 6,
+            CEREF0W::CEREF0_7 => 7,
+            CEREF0W::CEREF0_8 => 8,
+            CEREF0W::CEREF0_9 => 9,
+            CEREF0W::CEREF0_10 => 10,
+            CEREF0W::CEREF0_11 => 11,
+            CEREF0W::CEREF0_12 => 12,
+            CEREF0W::CEREF0_13 => 13,
+            CEREF0W::CEREF0_14 => 14,
+            CEREF0W::CEREF0_15 => 15,
+            CEREF0W::CEREF0_16 => 16,
+            CEREF0W::CEREF0_17 => 17,
+            CEREF0W::CEREF0_18 => 18,
+            CEREF0W::CEREF0_19 => 19,
+            CEREF0W::CEREF0_20 => 20,
+            CEREF0W::CEREF0_21 => 21,
+            CEREF0W::CEREF0_22 => 22,
+            CEREF0W::CEREF0_23 => 23,
+            CEREF0W::CEREF0_24 => 24,
+            CEREF0W::CEREF0_25 => 25,
+            CEREF0W::CEREF0_26 => 26,
+            CEREF0W::CEREF0_27 => 27,
+            CEREF0W::CEREF0_28 => 28,
+            CEREF0W::CEREF0_29 => 29,
+            CEREF0W::CEREF0_30 => 30,
+            CEREF0W::CEREF0_31 => 31,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEREF0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEREF0W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEREF0W) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Reference resistor tap for setting 0."]
+    #[inline]
+    pub fn ceref0_0(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_0)
+    }
+    #[doc = "Reference resistor tap for setting 1."]
+    #[inline]
+    pub fn ceref0_1(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_1)
+    }
+    #[doc = "Reference resistor tap for setting 2."]
+    #[inline]
+    pub fn ceref0_2(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_2)
+    }
+    #[doc = "Reference resistor tap for setting 3."]
+    #[inline]
+    pub fn ceref0_3(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_3)
+    }
+    #[doc = "Reference resistor tap for setting 4."]
+    #[inline]
+    pub fn ceref0_4(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_4)
+    }
+    #[doc = "Reference resistor tap for setting 5."]
+    #[inline]
+    pub fn ceref0_5(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_5)
+    }
+    #[doc = "Reference resistor tap for setting 6."]
+    #[inline]
+    pub fn ceref0_6(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_6)
+    }
+    #[doc = "Reference resistor tap for setting 7."]
+    #[inline]
+    pub fn ceref0_7(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_7)
+    }
+    #[doc = "Reference resistor tap for setting 8."]
+    #[inline]
+    pub fn ceref0_8(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_8)
+    }
+    #[doc = "Reference resistor tap for setting 9."]
+    #[inline]
+    pub fn ceref0_9(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_9)
+    }
+    #[doc = "Reference resistor tap for setting 10."]
+    #[inline]
+    pub fn ceref0_10(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_10)
+    }
+    #[doc = "Reference resistor tap for setting 11."]
+    #[inline]
+    pub fn ceref0_11(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_11)
+    }
+    #[doc = "Reference resistor tap for setting 12."]
+    #[inline]
+    pub fn ceref0_12(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_12)
+    }
+    #[doc = "Reference resistor tap for setting 13."]
+    #[inline]
+    pub fn ceref0_13(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_13)
+    }
+    #[doc = "Reference resistor tap for setting 14."]
+    #[inline]
+    pub fn ceref0_14(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_14)
+    }
+    #[doc = "Reference resistor tap for setting 15."]
+    #[inline]
+    pub fn ceref0_15(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_15)
+    }
+    #[doc = "Reference resistor tap for setting 16."]
+    #[inline]
+    pub fn ceref0_16(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_16)
+    }
+    #[doc = "Reference resistor tap for setting 17."]
+    #[inline]
+    pub fn ceref0_17(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_17)
+    }
+    #[doc = "Reference resistor tap for setting 18."]
+    #[inline]
+    pub fn ceref0_18(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_18)
+    }
+    #[doc = "Reference resistor tap for setting 19."]
+    #[inline]
+    pub fn ceref0_19(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_19)
+    }
+    #[doc = "Reference resistor tap for setting 20."]
+    #[inline]
+    pub fn ceref0_20(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_20)
+    }
+    #[doc = "Reference resistor tap for setting 21."]
+    #[inline]
+    pub fn ceref0_21(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_21)
+    }
+    #[doc = "Reference resistor tap for setting 22."]
+    #[inline]
+    pub fn ceref0_22(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_22)
+    }
+    #[doc = "Reference resistor tap for setting 23."]
+    #[inline]
+    pub fn ceref0_23(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_23)
+    }
+    #[doc = "Reference resistor tap for setting 24."]
+    #[inline]
+    pub fn ceref0_24(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_24)
+    }
+    #[doc = "Reference resistor tap for setting 25."]
+    #[inline]
+    pub fn ceref0_25(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_25)
+    }
+    #[doc = "Reference resistor tap for setting 26."]
+    #[inline]
+    pub fn ceref0_26(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_26)
+    }
+    #[doc = "Reference resistor tap for setting 27."]
+    #[inline]
+    pub fn ceref0_27(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_27)
+    }
+    #[doc = "Reference resistor tap for setting 28."]
+    #[inline]
+    pub fn ceref0_28(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_28)
+    }
+    #[doc = "Reference resistor tap for setting 29."]
+    #[inline]
+    pub fn ceref0_29(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_29)
+    }
+    #[doc = "Reference resistor tap for setting 30."]
+    #[inline]
+    pub fn ceref0_30(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_30)
+    }
+    #[doc = "Reference resistor tap for setting 31."]
+    #[inline]
+    pub fn ceref0_31(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_31)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 31;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CERSEL`"]
+pub enum CERSELW {
+    #[doc = "When CEEX = 0, VREF is applied to the V+ terminal; When CEEX = 1, VREF is applied to the V- terminal"]
+    CERSEL_0,
+    #[doc = "When CEEX = 0, VREF is applied to the V- terminal; When CEEX = 1, VREF is applied to the V+ terminal"]
+    CERSEL_1,
+}
+impl CERSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CERSELW::CERSEL_0 => false,
+            CERSELW::CERSEL_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CERSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CERSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CERSELW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "When CEEX = 0, VREF is applied to the V+ terminal; When CEEX = 1, VREF is applied to the V- terminal"]
+    #[inline]
+    pub fn cersel_0(self) -> &'a mut W {
+        self.variant(CERSELW::CERSEL_0)
+    }
+    #[doc = "When CEEX = 0, VREF is applied to the V- terminal; When CEEX = 1, VREF is applied to the V+ terminal"]
+    #[inline]
+    pub fn cersel_1(self) -> &'a mut W {
+        self.variant(CERSELW::CERSEL_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CERS`"]
+pub enum CERSW {
+    #[doc = "No current is drawn by the reference circuitry"]
+    CERS_0,
+    #[doc = "VCC applied to the resistor ladder"]
+    CERS_1,
+    #[doc = "Shared reference voltage applied to the resistor ladder"]
+    CERS_2,
+    #[doc = "Shared reference voltage supplied to V(CREF). Resistor ladder is off"]
+    CERS_3,
+}
+impl CERSW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            CERSW::CERS_0 => 0,
+            CERSW::CERS_1 => 1,
+            CERSW::CERS_2 => 2,
+            CERSW::CERS_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CERSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CERSW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CERSW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "No current is drawn by the reference circuitry"]
+    #[inline]
+    pub fn cers_0(self) -> &'a mut W {
+        self.variant(CERSW::CERS_0)
+    }
+    #[doc = "VCC applied to the resistor ladder"]
+    #[inline]
+    pub fn cers_1(self) -> &'a mut W {
+        self.variant(CERSW::CERS_1)
+    }
+    #[doc = "Shared reference voltage applied to the resistor ladder"]
+    #[inline]
+    pub fn cers_2(self) -> &'a mut W {
+        self.variant(CERSW::CERS_2)
+    }
+    #[doc = "Shared reference voltage supplied to V(CREF). Resistor ladder is off"]
+    #[inline]
+    pub fn cers_3(self) -> &'a mut W {
+        self.variant(CERSW::CERS_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEREF1`"]
+pub enum CEREF1W {
+    #[doc = "Reference resistor tap for setting 0."]
+    CEREF1_0,
+    #[doc = "Reference resistor tap for setting 1."]
+    CEREF1_1,
+    #[doc = "Reference resistor tap for setting 2."]
+    CEREF1_2,
+    #[doc = "Reference resistor tap for setting 3."]
+    CEREF1_3,
+    #[doc = "Reference resistor tap for setting 4."]
+    CEREF1_4,
+    #[doc = "Reference resistor tap for setting 5."]
+    CEREF1_5,
+    #[doc = "Reference resistor tap for setting 6."]
+    CEREF1_6,
+    #[doc = "Reference resistor tap for setting 7."]
+    CEREF1_7,
+    #[doc = "Reference resistor tap for setting 8."]
+    CEREF1_8,
+    #[doc = "Reference resistor tap for setting 9."]
+    CEREF1_9,
+    #[doc = "Reference resistor tap for setting 10."]
+    CEREF1_10,
+    #[doc = "Reference resistor tap for setting 11."]
+    CEREF1_11,
+    #[doc = "Reference resistor tap for setting 12."]
+    CEREF1_12,
+    #[doc = "Reference resistor tap for setting 13."]
+    CEREF1_13,
+    #[doc = "Reference resistor tap for setting 14."]
+    CEREF1_14,
+    #[doc = "Reference resistor tap for setting 15."]
+    CEREF1_15,
+    #[doc = "Reference resistor tap for setting 16."]
+    CEREF1_16,
+    #[doc = "Reference resistor tap for setting 17."]
+    CEREF1_17,
+    #[doc = "Reference resistor tap for setting 18."]
+    CEREF1_18,
+    #[doc = "Reference resistor tap for setting 19."]
+    CEREF1_19,
+    #[doc = "Reference resistor tap for setting 20."]
+    CEREF1_20,
+    #[doc = "Reference resistor tap for setting 21."]
+    CEREF1_21,
+    #[doc = "Reference resistor tap for setting 22."]
+    CEREF1_22,
+    #[doc = "Reference resistor tap for setting 23."]
+    CEREF1_23,
+    #[doc = "Reference resistor tap for setting 24."]
+    CEREF1_24,
+    #[doc = "Reference resistor tap for setting 25."]
+    CEREF1_25,
+    #[doc = "Reference resistor tap for setting 26."]
+    CEREF1_26,
+    #[doc = "Reference resistor tap for setting 27."]
+    CEREF1_27,
+    #[doc = "Reference resistor tap for setting 28."]
+    CEREF1_28,
+    #[doc = "Reference resistor tap for setting 29."]
+    CEREF1_29,
+    #[doc = "Reference resistor tap for setting 30."]
+    CEREF1_30,
+    #[doc = "Reference resistor tap for setting 31."]
+    CEREF1_31,
+}
+impl CEREF1W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            CEREF1W::CEREF1_0 => 0,
+            CEREF1W::CEREF1_1 => 1,
+            CEREF1W::CEREF1_2 => 2,
+            CEREF1W::CEREF1_3 => 3,
+            CEREF1W::CEREF1_4 => 4,
+            CEREF1W::CEREF1_5 => 5,
+            CEREF1W::CEREF1_6 => 6,
+            CEREF1W::CEREF1_7 => 7,
+            CEREF1W::CEREF1_8 => 8,
+            CEREF1W::CEREF1_9 => 9,
+            CEREF1W::CEREF1_10 => 10,
+            CEREF1W::CEREF1_11 => 11,
+            CEREF1W::CEREF1_12 => 12,
+            CEREF1W::CEREF1_13 => 13,
+            CEREF1W::CEREF1_14 => 14,
+            CEREF1W::CEREF1_15 => 15,
+            CEREF1W::CEREF1_16 => 16,
+            CEREF1W::CEREF1_17 => 17,
+            CEREF1W::CEREF1_18 => 18,
+            CEREF1W::CEREF1_19 => 19,
+            CEREF1W::CEREF1_20 => 20,
+            CEREF1W::CEREF1_21 => 21,
+            CEREF1W::CEREF1_22 => 22,
+            CEREF1W::CEREF1_23 => 23,
+            CEREF1W::CEREF1_24 => 24,
+            CEREF1W::CEREF1_25 => 25,
+            CEREF1W::CEREF1_26 => 26,
+            CEREF1W::CEREF1_27 => 27,
+            CEREF1W::CEREF1_28 => 28,
+            CEREF1W::CEREF1_29 => 29,
+            CEREF1W::CEREF1_30 => 30,
+            CEREF1W::CEREF1_31 => 31,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEREF1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEREF1W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEREF1W) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Reference resistor tap for setting 0."]
+    #[inline]
+    pub fn ceref1_0(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_0)
+    }
+    #[doc = "Reference resistor tap for setting 1."]
+    #[inline]
+    pub fn ceref1_1(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_1)
+    }
+    #[doc = "Reference resistor tap for setting 2."]
+    #[inline]
+    pub fn ceref1_2(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_2)
+    }
+    #[doc = "Reference resistor tap for setting 3."]
+    #[inline]
+    pub fn ceref1_3(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_3)
+    }
+    #[doc = "Reference resistor tap for setting 4."]
+    #[inline]
+    pub fn ceref1_4(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_4)
+    }
+    #[doc = "Reference resistor tap for setting 5."]
+    #[inline]
+    pub fn ceref1_5(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_5)
+    }
+    #[doc = "Reference resistor tap for setting 6."]
+    #[inline]
+    pub fn ceref1_6(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_6)
+    }
+    #[doc = "Reference resistor tap for setting 7."]
+    #[inline]
+    pub fn ceref1_7(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_7)
+    }
+    #[doc = "Reference resistor tap for setting 8."]
+    #[inline]
+    pub fn ceref1_8(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_8)
+    }
+    #[doc = "Reference resistor tap for setting 9."]
+    #[inline]
+    pub fn ceref1_9(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_9)
+    }
+    #[doc = "Reference resistor tap for setting 10."]
+    #[inline]
+    pub fn ceref1_10(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_10)
+    }
+    #[doc = "Reference resistor tap for setting 11."]
+    #[inline]
+    pub fn ceref1_11(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_11)
+    }
+    #[doc = "Reference resistor tap for setting 12."]
+    #[inline]
+    pub fn ceref1_12(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_12)
+    }
+    #[doc = "Reference resistor tap for setting 13."]
+    #[inline]
+    pub fn ceref1_13(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_13)
+    }
+    #[doc = "Reference resistor tap for setting 14."]
+    #[inline]
+    pub fn ceref1_14(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_14)
+    }
+    #[doc = "Reference resistor tap for setting 15."]
+    #[inline]
+    pub fn ceref1_15(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_15)
+    }
+    #[doc = "Reference resistor tap for setting 16."]
+    #[inline]
+    pub fn ceref1_16(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_16)
+    }
+    #[doc = "Reference resistor tap for setting 17."]
+    #[inline]
+    pub fn ceref1_17(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_17)
+    }
+    #[doc = "Reference resistor tap for setting 18."]
+    #[inline]
+    pub fn ceref1_18(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_18)
+    }
+    #[doc = "Reference resistor tap for setting 19."]
+    #[inline]
+    pub fn ceref1_19(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_19)
+    }
+    #[doc = "Reference resistor tap for setting 20."]
+    #[inline]
+    pub fn ceref1_20(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_20)
+    }
+    #[doc = "Reference resistor tap for setting 21."]
+    #[inline]
+    pub fn ceref1_21(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_21)
+    }
+    #[doc = "Reference resistor tap for setting 22."]
+    #[inline]
+    pub fn ceref1_22(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_22)
+    }
+    #[doc = "Reference resistor tap for setting 23."]
+    #[inline]
+    pub fn ceref1_23(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_23)
+    }
+    #[doc = "Reference resistor tap for setting 24."]
+    #[inline]
+    pub fn ceref1_24(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_24)
+    }
+    #[doc = "Reference resistor tap for setting 25."]
+    #[inline]
+    pub fn ceref1_25(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_25)
+    }
+    #[doc = "Reference resistor tap for setting 26."]
+    #[inline]
+    pub fn ceref1_26(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_26)
+    }
+    #[doc = "Reference resistor tap for setting 27."]
+    #[inline]
+    pub fn ceref1_27(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_27)
+    }
+    #[doc = "Reference resistor tap for setting 28."]
+    #[inline]
+    pub fn ceref1_28(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_28)
+    }
+    #[doc = "Reference resistor tap for setting 29."]
+    #[inline]
+    pub fn ceref1_29(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_29)
+    }
+    #[doc = "Reference resistor tap for setting 30."]
+    #[inline]
+    pub fn ceref1_30(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_30)
+    }
+    #[doc = "Reference resistor tap for setting 31."]
+    #[inline]
+    pub fn ceref1_31(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_31)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 31;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEREFL`"]
+pub enum CEREFLW {
+    #[doc = "Reference amplifier is disabled. No reference voltage is requested"]
+    CEREFL_0,
+    #[doc = "1.2 V is selected as shared reference voltage input"]
+    CEREFL_1,
+    #[doc = "2.0 V is selected as shared reference voltage input"]
+    CEREFL_2,
+    #[doc = "2.5 V is selected as shared reference voltage input"]
+    CEREFL_3,
+}
+impl CEREFLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            CEREFLW::CEREFL_0 => 0,
+            CEREFLW::CEREFL_1 => 1,
+            CEREFLW::CEREFL_2 => 2,
+            CEREFLW::CEREFL_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEREFLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEREFLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEREFLW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Reference amplifier is disabled. No reference voltage is requested"]
+    #[inline]
+    pub fn cerefl_0(self) -> &'a mut W {
+        self.variant(CEREFLW::CEREFL_0)
+    }
+    #[doc = "1.2 V is selected as shared reference voltage input"]
+    #[inline]
+    pub fn cerefl_1(self) -> &'a mut W {
+        self.variant(CEREFLW::CEREFL_1)
+    }
+    #[doc = "2.0 V is selected as shared reference voltage input"]
+    #[inline]
+    pub fn cerefl_2(self) -> &'a mut W {
+        self.variant(CEREFLW::CEREFL_2)
+    }
+    #[doc = "2.5 V is selected as shared reference voltage input"]
+    #[inline]
+    pub fn cerefl_3(self) -> &'a mut W {
+        self.variant(CEREFLW::CEREFL_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEREFACC`"]
+pub enum CEREFACCW {
+    #[doc = "Static mode"]
+    CEREFACC_0,
+    #[doc = "Clocked (low power, low accuracy) mode"]
+    CEREFACC_1,
+}
+impl CEREFACCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEREFACCW::CEREFACC_0 => false,
+            CEREFACCW::CEREFACC_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEREFACCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEREFACCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEREFACCW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Static mode"]
+    #[inline]
+    pub fn cerefacc_0(self) -> &'a mut W {
+        self.variant(CEREFACCW::CEREFACC_0)
+    }
+    #[doc = "Clocked (low power, low accuracy) mode"]
+    #[inline]
+    pub fn cerefacc_1(self) -> &'a mut W {
+        self.variant(CEREFACCW::CEREFACC_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:4 - Reference resistor tap 0"]
+    #[inline]
+    pub fn ceref0(&self) -> CEREF0R {
+        CEREF0R::_from({
+            const MASK: u8 = 31;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 5 - Reference select"]
+    #[inline]
+    pub fn cersel(&self) -> CERSELR {
+        CERSELR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 6:7 - Reference source"]
+    #[inline]
+    pub fn cers(&self) -> CERSR {
+        CERSR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bits 8:12 - Reference resistor tap 1"]
+    #[inline]
+    pub fn ceref1(&self) -> CEREF1R {
+        CEREF1R::_from({
+            const MASK: u8 = 31;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bits 13:14 - Reference voltage level"]
+    #[inline]
+    pub fn cerefl(&self) -> CEREFLR {
+        CEREFLR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 15 - Reference accuracy"]
+    #[inline]
+    pub fn cerefacc(&self) -> CEREFACCR {
+        CEREFACCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:4 - Reference resistor tap 0"]
+    #[inline]
+    pub fn ceref0(&mut self) -> _CEREF0W {
+        _CEREF0W { w: self }
+    }
+    #[doc = "Bit 5 - Reference select"]
+    #[inline]
+    pub fn cersel(&mut self) -> _CERSELW {
+        _CERSELW { w: self }
+    }
+    #[doc = "Bits 6:7 - Reference source"]
+    #[inline]
+    pub fn cers(&mut self) -> _CERSW {
+        _CERSW { w: self }
+    }
+    #[doc = "Bits 8:12 - Reference resistor tap 1"]
+    #[inline]
+    pub fn ceref1(&mut self) -> _CEREF1W {
+        _CEREF1W { w: self }
+    }
+    #[doc = "Bits 13:14 - Reference voltage level"]
+    #[inline]
+    pub fn cerefl(&mut self) -> _CEREFLW {
+        _CEREFLW { w: self }
+    }
+    #[doc = "Bit 15 - Reference accuracy"]
+    #[inline]
+    pub fn cerefacc(&mut self) -> _CEREFACCW {
+        _CEREFACCW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/comp_e0/cex_ctl3.rs b/example-source/msp432p401r/src/comp_e0/cex_ctl3.rs
new file mode 100644
index 0000000..fb1efc5
--- /dev/null
+++ b/example-source/msp432p401r/src/comp_e0/cex_ctl3.rs
@@ -0,0 +1,1968 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::CEXCTL3 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `CEPD0`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD0R {
+    #[doc = "The input buffer is enabled"]
+    CEPD0_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD0_1,
+}
+impl CEPD0R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD0R::CEPD0_0 => false,
+            CEPD0R::CEPD0_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD0R {
+        match value {
+            false => CEPD0R::CEPD0_0,
+            true => CEPD0R::CEPD0_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD0_0`"]
+    #[inline]
+    pub fn is_cepd0_0(&self) -> bool {
+        *self == CEPD0R::CEPD0_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD0_1`"]
+    #[inline]
+    pub fn is_cepd0_1(&self) -> bool {
+        *self == CEPD0R::CEPD0_1
+    }
+}
+#[doc = "Possible values of the field `CEPD1`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD1R {
+    #[doc = "The input buffer is enabled"]
+    CEPD1_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD1_1,
+}
+impl CEPD1R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD1R::CEPD1_0 => false,
+            CEPD1R::CEPD1_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD1R {
+        match value {
+            false => CEPD1R::CEPD1_0,
+            true => CEPD1R::CEPD1_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD1_0`"]
+    #[inline]
+    pub fn is_cepd1_0(&self) -> bool {
+        *self == CEPD1R::CEPD1_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD1_1`"]
+    #[inline]
+    pub fn is_cepd1_1(&self) -> bool {
+        *self == CEPD1R::CEPD1_1
+    }
+}
+#[doc = "Possible values of the field `CEPD2`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD2R {
+    #[doc = "The input buffer is enabled"]
+    CEPD2_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD2_1,
+}
+impl CEPD2R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD2R::CEPD2_0 => false,
+            CEPD2R::CEPD2_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD2R {
+        match value {
+            false => CEPD2R::CEPD2_0,
+            true => CEPD2R::CEPD2_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD2_0`"]
+    #[inline]
+    pub fn is_cepd2_0(&self) -> bool {
+        *self == CEPD2R::CEPD2_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD2_1`"]
+    #[inline]
+    pub fn is_cepd2_1(&self) -> bool {
+        *self == CEPD2R::CEPD2_1
+    }
+}
+#[doc = "Possible values of the field `CEPD3`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD3R {
+    #[doc = "The input buffer is enabled"]
+    CEPD3_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD3_1,
+}
+impl CEPD3R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD3R::CEPD3_0 => false,
+            CEPD3R::CEPD3_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD3R {
+        match value {
+            false => CEPD3R::CEPD3_0,
+            true => CEPD3R::CEPD3_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD3_0`"]
+    #[inline]
+    pub fn is_cepd3_0(&self) -> bool {
+        *self == CEPD3R::CEPD3_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD3_1`"]
+    #[inline]
+    pub fn is_cepd3_1(&self) -> bool {
+        *self == CEPD3R::CEPD3_1
+    }
+}
+#[doc = "Possible values of the field `CEPD4`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD4R {
+    #[doc = "The input buffer is enabled"]
+    CEPD4_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD4_1,
+}
+impl CEPD4R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD4R::CEPD4_0 => false,
+            CEPD4R::CEPD4_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD4R {
+        match value {
+            false => CEPD4R::CEPD4_0,
+            true => CEPD4R::CEPD4_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD4_0`"]
+    #[inline]
+    pub fn is_cepd4_0(&self) -> bool {
+        *self == CEPD4R::CEPD4_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD4_1`"]
+    #[inline]
+    pub fn is_cepd4_1(&self) -> bool {
+        *self == CEPD4R::CEPD4_1
+    }
+}
+#[doc = "Possible values of the field `CEPD5`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD5R {
+    #[doc = "The input buffer is enabled"]
+    CEPD5_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD5_1,
+}
+impl CEPD5R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD5R::CEPD5_0 => false,
+            CEPD5R::CEPD5_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD5R {
+        match value {
+            false => CEPD5R::CEPD5_0,
+            true => CEPD5R::CEPD5_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD5_0`"]
+    #[inline]
+    pub fn is_cepd5_0(&self) -> bool {
+        *self == CEPD5R::CEPD5_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD5_1`"]
+    #[inline]
+    pub fn is_cepd5_1(&self) -> bool {
+        *self == CEPD5R::CEPD5_1
+    }
+}
+#[doc = "Possible values of the field `CEPD6`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD6R {
+    #[doc = "The input buffer is enabled"]
+    CEPD6_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD6_1,
+}
+impl CEPD6R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD6R::CEPD6_0 => false,
+            CEPD6R::CEPD6_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD6R {
+        match value {
+            false => CEPD6R::CEPD6_0,
+            true => CEPD6R::CEPD6_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD6_0`"]
+    #[inline]
+    pub fn is_cepd6_0(&self) -> bool {
+        *self == CEPD6R::CEPD6_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD6_1`"]
+    #[inline]
+    pub fn is_cepd6_1(&self) -> bool {
+        *self == CEPD6R::CEPD6_1
+    }
+}
+#[doc = "Possible values of the field `CEPD7`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD7R {
+    #[doc = "The input buffer is enabled"]
+    CEPD7_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD7_1,
+}
+impl CEPD7R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD7R::CEPD7_0 => false,
+            CEPD7R::CEPD7_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD7R {
+        match value {
+            false => CEPD7R::CEPD7_0,
+            true => CEPD7R::CEPD7_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD7_0`"]
+    #[inline]
+    pub fn is_cepd7_0(&self) -> bool {
+        *self == CEPD7R::CEPD7_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD7_1`"]
+    #[inline]
+    pub fn is_cepd7_1(&self) -> bool {
+        *self == CEPD7R::CEPD7_1
+    }
+}
+#[doc = "Possible values of the field `CEPD8`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD8R {
+    #[doc = "The input buffer is enabled"]
+    CEPD8_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD8_1,
+}
+impl CEPD8R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD8R::CEPD8_0 => false,
+            CEPD8R::CEPD8_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD8R {
+        match value {
+            false => CEPD8R::CEPD8_0,
+            true => CEPD8R::CEPD8_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD8_0`"]
+    #[inline]
+    pub fn is_cepd8_0(&self) -> bool {
+        *self == CEPD8R::CEPD8_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD8_1`"]
+    #[inline]
+    pub fn is_cepd8_1(&self) -> bool {
+        *self == CEPD8R::CEPD8_1
+    }
+}
+#[doc = "Possible values of the field `CEPD9`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD9R {
+    #[doc = "The input buffer is enabled"]
+    CEPD9_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD9_1,
+}
+impl CEPD9R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD9R::CEPD9_0 => false,
+            CEPD9R::CEPD9_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD9R {
+        match value {
+            false => CEPD9R::CEPD9_0,
+            true => CEPD9R::CEPD9_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD9_0`"]
+    #[inline]
+    pub fn is_cepd9_0(&self) -> bool {
+        *self == CEPD9R::CEPD9_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD9_1`"]
+    #[inline]
+    pub fn is_cepd9_1(&self) -> bool {
+        *self == CEPD9R::CEPD9_1
+    }
+}
+#[doc = "Possible values of the field `CEPD10`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD10R {
+    #[doc = "The input buffer is enabled"]
+    CEPD10_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD10_1,
+}
+impl CEPD10R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD10R::CEPD10_0 => false,
+            CEPD10R::CEPD10_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD10R {
+        match value {
+            false => CEPD10R::CEPD10_0,
+            true => CEPD10R::CEPD10_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD10_0`"]
+    #[inline]
+    pub fn is_cepd10_0(&self) -> bool {
+        *self == CEPD10R::CEPD10_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD10_1`"]
+    #[inline]
+    pub fn is_cepd10_1(&self) -> bool {
+        *self == CEPD10R::CEPD10_1
+    }
+}
+#[doc = "Possible values of the field `CEPD11`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD11R {
+    #[doc = "The input buffer is enabled"]
+    CEPD11_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD11_1,
+}
+impl CEPD11R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD11R::CEPD11_0 => false,
+            CEPD11R::CEPD11_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD11R {
+        match value {
+            false => CEPD11R::CEPD11_0,
+            true => CEPD11R::CEPD11_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD11_0`"]
+    #[inline]
+    pub fn is_cepd11_0(&self) -> bool {
+        *self == CEPD11R::CEPD11_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD11_1`"]
+    #[inline]
+    pub fn is_cepd11_1(&self) -> bool {
+        *self == CEPD11R::CEPD11_1
+    }
+}
+#[doc = "Possible values of the field `CEPD12`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD12R {
+    #[doc = "The input buffer is enabled"]
+    CEPD12_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD12_1,
+}
+impl CEPD12R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD12R::CEPD12_0 => false,
+            CEPD12R::CEPD12_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD12R {
+        match value {
+            false => CEPD12R::CEPD12_0,
+            true => CEPD12R::CEPD12_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD12_0`"]
+    #[inline]
+    pub fn is_cepd12_0(&self) -> bool {
+        *self == CEPD12R::CEPD12_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD12_1`"]
+    #[inline]
+    pub fn is_cepd12_1(&self) -> bool {
+        *self == CEPD12R::CEPD12_1
+    }
+}
+#[doc = "Possible values of the field `CEPD13`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD13R {
+    #[doc = "The input buffer is enabled"]
+    CEPD13_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD13_1,
+}
+impl CEPD13R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD13R::CEPD13_0 => false,
+            CEPD13R::CEPD13_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD13R {
+        match value {
+            false => CEPD13R::CEPD13_0,
+            true => CEPD13R::CEPD13_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD13_0`"]
+    #[inline]
+    pub fn is_cepd13_0(&self) -> bool {
+        *self == CEPD13R::CEPD13_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD13_1`"]
+    #[inline]
+    pub fn is_cepd13_1(&self) -> bool {
+        *self == CEPD13R::CEPD13_1
+    }
+}
+#[doc = "Possible values of the field `CEPD14`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD14R {
+    #[doc = "The input buffer is enabled"]
+    CEPD14_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD14_1,
+}
+impl CEPD14R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD14R::CEPD14_0 => false,
+            CEPD14R::CEPD14_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD14R {
+        match value {
+            false => CEPD14R::CEPD14_0,
+            true => CEPD14R::CEPD14_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD14_0`"]
+    #[inline]
+    pub fn is_cepd14_0(&self) -> bool {
+        *self == CEPD14R::CEPD14_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD14_1`"]
+    #[inline]
+    pub fn is_cepd14_1(&self) -> bool {
+        *self == CEPD14R::CEPD14_1
+    }
+}
+#[doc = "Possible values of the field `CEPD15`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD15R {
+    #[doc = "The input buffer is enabled"]
+    CEPD15_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD15_1,
+}
+impl CEPD15R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD15R::CEPD15_0 => false,
+            CEPD15R::CEPD15_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD15R {
+        match value {
+            false => CEPD15R::CEPD15_0,
+            true => CEPD15R::CEPD15_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD15_0`"]
+    #[inline]
+    pub fn is_cepd15_0(&self) -> bool {
+        *self == CEPD15R::CEPD15_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD15_1`"]
+    #[inline]
+    pub fn is_cepd15_1(&self) -> bool {
+        *self == CEPD15R::CEPD15_1
+    }
+}
+#[doc = "Values that can be written to the field `CEPD0`"]
+pub enum CEPD0W {
+    #[doc = "The input buffer is enabled"]
+    CEPD0_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD0_1,
+}
+impl CEPD0W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD0W::CEPD0_0 => false,
+            CEPD0W::CEPD0_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD0W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD0W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd0_0(self) -> &'a mut W {
+        self.variant(CEPD0W::CEPD0_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd0_1(self) -> &'a mut W {
+        self.variant(CEPD0W::CEPD0_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPD1`"]
+pub enum CEPD1W {
+    #[doc = "The input buffer is enabled"]
+    CEPD1_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD1_1,
+}
+impl CEPD1W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD1W::CEPD1_0 => false,
+            CEPD1W::CEPD1_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD1W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD1W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd1_0(self) -> &'a mut W {
+        self.variant(CEPD1W::CEPD1_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd1_1(self) -> &'a mut W {
+        self.variant(CEPD1W::CEPD1_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPD2`"]
+pub enum CEPD2W {
+    #[doc = "The input buffer is enabled"]
+    CEPD2_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD2_1,
+}
+impl CEPD2W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD2W::CEPD2_0 => false,
+            CEPD2W::CEPD2_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD2W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD2W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd2_0(self) -> &'a mut W {
+        self.variant(CEPD2W::CEPD2_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd2_1(self) -> &'a mut W {
+        self.variant(CEPD2W::CEPD2_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPD3`"]
+pub enum CEPD3W {
+    #[doc = "The input buffer is enabled"]
+    CEPD3_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD3_1,
+}
+impl CEPD3W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD3W::CEPD3_0 => false,
+            CEPD3W::CEPD3_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD3W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD3W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd3_0(self) -> &'a mut W {
+        self.variant(CEPD3W::CEPD3_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd3_1(self) -> &'a mut W {
+        self.variant(CEPD3W::CEPD3_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPD4`"]
+pub enum CEPD4W {
+    #[doc = "The input buffer is enabled"]
+    CEPD4_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD4_1,
+}
+impl CEPD4W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD4W::CEPD4_0 => false,
+            CEPD4W::CEPD4_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD4W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD4W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD4W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd4_0(self) -> &'a mut W {
+        self.variant(CEPD4W::CEPD4_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd4_1(self) -> &'a mut W {
+        self.variant(CEPD4W::CEPD4_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPD5`"]
+pub enum CEPD5W {
+    #[doc = "The input buffer is enabled"]
+    CEPD5_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD5_1,
+}
+impl CEPD5W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD5W::CEPD5_0 => false,
+            CEPD5W::CEPD5_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD5W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD5W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD5W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd5_0(self) -> &'a mut W {
+        self.variant(CEPD5W::CEPD5_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd5_1(self) -> &'a mut W {
+        self.variant(CEPD5W::CEPD5_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPD6`"]
+pub enum CEPD6W {
+    #[doc = "The input buffer is enabled"]
+    CEPD6_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD6_1,
+}
+impl CEPD6W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD6W::CEPD6_0 => false,
+            CEPD6W::CEPD6_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD6W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD6W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD6W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd6_0(self) -> &'a mut W {
+        self.variant(CEPD6W::CEPD6_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd6_1(self) -> &'a mut W {
+        self.variant(CEPD6W::CEPD6_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPD7`"]
+pub enum CEPD7W {
+    #[doc = "The input buffer is enabled"]
+    CEPD7_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD7_1,
+}
+impl CEPD7W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD7W::CEPD7_0 => false,
+            CEPD7W::CEPD7_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD7W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD7W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD7W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd7_0(self) -> &'a mut W {
+        self.variant(CEPD7W::CEPD7_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd7_1(self) -> &'a mut W {
+        self.variant(CEPD7W::CEPD7_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPD8`"]
+pub enum CEPD8W {
+    #[doc = "The input buffer is enabled"]
+    CEPD8_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD8_1,
+}
+impl CEPD8W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD8W::CEPD8_0 => false,
+            CEPD8W::CEPD8_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD8W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD8W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD8W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd8_0(self) -> &'a mut W {
+        self.variant(CEPD8W::CEPD8_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd8_1(self) -> &'a mut W {
+        self.variant(CEPD8W::CEPD8_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPD9`"]
+pub enum CEPD9W {
+    #[doc = "The input buffer is enabled"]
+    CEPD9_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD9_1,
+}
+impl CEPD9W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD9W::CEPD9_0 => false,
+            CEPD9W::CEPD9_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD9W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD9W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD9W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd9_0(self) -> &'a mut W {
+        self.variant(CEPD9W::CEPD9_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd9_1(self) -> &'a mut W {
+        self.variant(CEPD9W::CEPD9_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPD10`"]
+pub enum CEPD10W {
+    #[doc = "The input buffer is enabled"]
+    CEPD10_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD10_1,
+}
+impl CEPD10W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD10W::CEPD10_0 => false,
+            CEPD10W::CEPD10_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD10W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD10W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD10W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd10_0(self) -> &'a mut W {
+        self.variant(CEPD10W::CEPD10_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd10_1(self) -> &'a mut W {
+        self.variant(CEPD10W::CEPD10_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPD11`"]
+pub enum CEPD11W {
+    #[doc = "The input buffer is enabled"]
+    CEPD11_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD11_1,
+}
+impl CEPD11W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD11W::CEPD11_0 => false,
+            CEPD11W::CEPD11_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD11W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD11W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD11W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd11_0(self) -> &'a mut W {
+        self.variant(CEPD11W::CEPD11_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd11_1(self) -> &'a mut W {
+        self.variant(CEPD11W::CEPD11_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPD12`"]
+pub enum CEPD12W {
+    #[doc = "The input buffer is enabled"]
+    CEPD12_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD12_1,
+}
+impl CEPD12W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD12W::CEPD12_0 => false,
+            CEPD12W::CEPD12_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD12W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD12W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD12W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd12_0(self) -> &'a mut W {
+        self.variant(CEPD12W::CEPD12_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd12_1(self) -> &'a mut W {
+        self.variant(CEPD12W::CEPD12_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPD13`"]
+pub enum CEPD13W {
+    #[doc = "The input buffer is enabled"]
+    CEPD13_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD13_1,
+}
+impl CEPD13W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD13W::CEPD13_0 => false,
+            CEPD13W::CEPD13_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD13W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD13W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD13W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd13_0(self) -> &'a mut W {
+        self.variant(CEPD13W::CEPD13_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd13_1(self) -> &'a mut W {
+        self.variant(CEPD13W::CEPD13_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPD14`"]
+pub enum CEPD14W {
+    #[doc = "The input buffer is enabled"]
+    CEPD14_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD14_1,
+}
+impl CEPD14W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD14W::CEPD14_0 => false,
+            CEPD14W::CEPD14_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD14W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD14W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD14W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd14_0(self) -> &'a mut W {
+        self.variant(CEPD14W::CEPD14_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd14_1(self) -> &'a mut W {
+        self.variant(CEPD14W::CEPD14_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPD15`"]
+pub enum CEPD15W {
+    #[doc = "The input buffer is enabled"]
+    CEPD15_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD15_1,
+}
+impl CEPD15W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD15W::CEPD15_0 => false,
+            CEPD15W::CEPD15_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD15W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD15W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD15W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd15_0(self) -> &'a mut W {
+        self.variant(CEPD15W::CEPD15_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd15_1(self) -> &'a mut W {
+        self.variant(CEPD15W::CEPD15_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Port disable"]
+    #[inline]
+    pub fn cepd0(&self) -> CEPD0R {
+        CEPD0R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Port disable"]
+    #[inline]
+    pub fn cepd1(&self) -> CEPD1R {
+        CEPD1R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - Port disable"]
+    #[inline]
+    pub fn cepd2(&self) -> CEPD2R {
+        CEPD2R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Port disable"]
+    #[inline]
+    pub fn cepd3(&self) -> CEPD3R {
+        CEPD3R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 4 - Port disable"]
+    #[inline]
+    pub fn cepd4(&self) -> CEPD4R {
+        CEPD4R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - Port disable"]
+    #[inline]
+    pub fn cepd5(&self) -> CEPD5R {
+        CEPD5R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 6 - Port disable"]
+    #[inline]
+    pub fn cepd6(&self) -> CEPD6R {
+        CEPD6R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 7 - Port disable"]
+    #[inline]
+    pub fn cepd7(&self) -> CEPD7R {
+        CEPD7R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 8 - Port disable"]
+    #[inline]
+    pub fn cepd8(&self) -> CEPD8R {
+        CEPD8R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 9 - Port disable"]
+    #[inline]
+    pub fn cepd9(&self) -> CEPD9R {
+        CEPD9R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 10 - Port disable"]
+    #[inline]
+    pub fn cepd10(&self) -> CEPD10R {
+        CEPD10R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 11 - Port disable"]
+    #[inline]
+    pub fn cepd11(&self) -> CEPD11R {
+        CEPD11R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 12 - Port disable"]
+    #[inline]
+    pub fn cepd12(&self) -> CEPD12R {
+        CEPD12R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 13 - Port disable"]
+    #[inline]
+    pub fn cepd13(&self) -> CEPD13R {
+        CEPD13R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 14 - Port disable"]
+    #[inline]
+    pub fn cepd14(&self) -> CEPD14R {
+        CEPD14R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 15 - Port disable"]
+    #[inline]
+    pub fn cepd15(&self) -> CEPD15R {
+        CEPD15R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Port disable"]
+    #[inline]
+    pub fn cepd0(&mut self) -> _CEPD0W {
+        _CEPD0W { w: self }
+    }
+    #[doc = "Bit 1 - Port disable"]
+    #[inline]
+    pub fn cepd1(&mut self) -> _CEPD1W {
+        _CEPD1W { w: self }
+    }
+    #[doc = "Bit 2 - Port disable"]
+    #[inline]
+    pub fn cepd2(&mut self) -> _CEPD2W {
+        _CEPD2W { w: self }
+    }
+    #[doc = "Bit 3 - Port disable"]
+    #[inline]
+    pub fn cepd3(&mut self) -> _CEPD3W {
+        _CEPD3W { w: self }
+    }
+    #[doc = "Bit 4 - Port disable"]
+    #[inline]
+    pub fn cepd4(&mut self) -> _CEPD4W {
+        _CEPD4W { w: self }
+    }
+    #[doc = "Bit 5 - Port disable"]
+    #[inline]
+    pub fn cepd5(&mut self) -> _CEPD5W {
+        _CEPD5W { w: self }
+    }
+    #[doc = "Bit 6 - Port disable"]
+    #[inline]
+    pub fn cepd6(&mut self) -> _CEPD6W {
+        _CEPD6W { w: self }
+    }
+    #[doc = "Bit 7 - Port disable"]
+    #[inline]
+    pub fn cepd7(&mut self) -> _CEPD7W {
+        _CEPD7W { w: self }
+    }
+    #[doc = "Bit 8 - Port disable"]
+    #[inline]
+    pub fn cepd8(&mut self) -> _CEPD8W {
+        _CEPD8W { w: self }
+    }
+    #[doc = "Bit 9 - Port disable"]
+    #[inline]
+    pub fn cepd9(&mut self) -> _CEPD9W {
+        _CEPD9W { w: self }
+    }
+    #[doc = "Bit 10 - Port disable"]
+    #[inline]
+    pub fn cepd10(&mut self) -> _CEPD10W {
+        _CEPD10W { w: self }
+    }
+    #[doc = "Bit 11 - Port disable"]
+    #[inline]
+    pub fn cepd11(&mut self) -> _CEPD11W {
+        _CEPD11W { w: self }
+    }
+    #[doc = "Bit 12 - Port disable"]
+    #[inline]
+    pub fn cepd12(&mut self) -> _CEPD12W {
+        _CEPD12W { w: self }
+    }
+    #[doc = "Bit 13 - Port disable"]
+    #[inline]
+    pub fn cepd13(&mut self) -> _CEPD13W {
+        _CEPD13W { w: self }
+    }
+    #[doc = "Bit 14 - Port disable"]
+    #[inline]
+    pub fn cepd14(&mut self) -> _CEPD14W {
+        _CEPD14W { w: self }
+    }
+    #[doc = "Bit 15 - Port disable"]
+    #[inline]
+    pub fn cepd15(&mut self) -> _CEPD15W {
+        _CEPD15W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/comp_e0/cex_int.rs b/example-source/msp432p401r/src/comp_e0/cex_int.rs
new file mode 100644
index 0000000..04e3d31
--- /dev/null
+++ b/example-source/msp432p401r/src/comp_e0/cex_int.rs
@@ -0,0 +1,778 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::CEXINT {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `CEIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEIFGR {
+    #[doc = "No interrupt pending"]
+    CEIFG_0,
+    #[doc = "Interrupt pending"]
+    CEIFG_1,
+}
+impl CEIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEIFGR::CEIFG_0 => false,
+            CEIFGR::CEIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEIFGR {
+        match value {
+            false => CEIFGR::CEIFG_0,
+            true => CEIFGR::CEIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEIFG_0`"]
+    #[inline]
+    pub fn is_ceifg_0(&self) -> bool {
+        *self == CEIFGR::CEIFG_0
+    }
+    #[doc = "Checks if the value of the field is `CEIFG_1`"]
+    #[inline]
+    pub fn is_ceifg_1(&self) -> bool {
+        *self == CEIFGR::CEIFG_1
+    }
+}
+#[doc = "Possible values of the field `CEIIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEIIFGR {
+    #[doc = "No interrupt pending"]
+    CEIIFG_0,
+    #[doc = "Interrupt pending"]
+    CEIIFG_1,
+}
+impl CEIIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEIIFGR::CEIIFG_0 => false,
+            CEIIFGR::CEIIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEIIFGR {
+        match value {
+            false => CEIIFGR::CEIIFG_0,
+            true => CEIIFGR::CEIIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEIIFG_0`"]
+    #[inline]
+    pub fn is_ceiifg_0(&self) -> bool {
+        *self == CEIIFGR::CEIIFG_0
+    }
+    #[doc = "Checks if the value of the field is `CEIIFG_1`"]
+    #[inline]
+    pub fn is_ceiifg_1(&self) -> bool {
+        *self == CEIIFGR::CEIIFG_1
+    }
+}
+#[doc = "Possible values of the field `CERDYIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CERDYIFGR {
+    #[doc = "No interrupt pending"]
+    CERDYIFG_0,
+    #[doc = "Interrupt pending"]
+    CERDYIFG_1,
+}
+impl CERDYIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CERDYIFGR::CERDYIFG_0 => false,
+            CERDYIFGR::CERDYIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CERDYIFGR {
+        match value {
+            false => CERDYIFGR::CERDYIFG_0,
+            true => CERDYIFGR::CERDYIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CERDYIFG_0`"]
+    #[inline]
+    pub fn is_cerdyifg_0(&self) -> bool {
+        *self == CERDYIFGR::CERDYIFG_0
+    }
+    #[doc = "Checks if the value of the field is `CERDYIFG_1`"]
+    #[inline]
+    pub fn is_cerdyifg_1(&self) -> bool {
+        *self == CERDYIFGR::CERDYIFG_1
+    }
+}
+#[doc = "Possible values of the field `CEIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEIER {
+    #[doc = "Interrupt disabled"]
+    CEIE_0,
+    #[doc = "Interrupt enabled"]
+    CEIE_1,
+}
+impl CEIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEIER::CEIE_0 => false,
+            CEIER::CEIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEIER {
+        match value {
+            false => CEIER::CEIE_0,
+            true => CEIER::CEIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEIE_0`"]
+    #[inline]
+    pub fn is_ceie_0(&self) -> bool {
+        *self == CEIER::CEIE_0
+    }
+    #[doc = "Checks if the value of the field is `CEIE_1`"]
+    #[inline]
+    pub fn is_ceie_1(&self) -> bool {
+        *self == CEIER::CEIE_1
+    }
+}
+#[doc = "Possible values of the field `CEIIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEIIER {
+    #[doc = "Interrupt disabled"]
+    CEIIE_0,
+    #[doc = "Interrupt enabled"]
+    CEIIE_1,
+}
+impl CEIIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEIIER::CEIIE_0 => false,
+            CEIIER::CEIIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEIIER {
+        match value {
+            false => CEIIER::CEIIE_0,
+            true => CEIIER::CEIIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEIIE_0`"]
+    #[inline]
+    pub fn is_ceiie_0(&self) -> bool {
+        *self == CEIIER::CEIIE_0
+    }
+    #[doc = "Checks if the value of the field is `CEIIE_1`"]
+    #[inline]
+    pub fn is_ceiie_1(&self) -> bool {
+        *self == CEIIER::CEIIE_1
+    }
+}
+#[doc = "Possible values of the field `CERDYIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CERDYIER {
+    #[doc = "Interrupt disabled"]
+    CERDYIE_0,
+    #[doc = "Interrupt enabled"]
+    CERDYIE_1,
+}
+impl CERDYIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CERDYIER::CERDYIE_0 => false,
+            CERDYIER::CERDYIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CERDYIER {
+        match value {
+            false => CERDYIER::CERDYIE_0,
+            true => CERDYIER::CERDYIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CERDYIE_0`"]
+    #[inline]
+    pub fn is_cerdyie_0(&self) -> bool {
+        *self == CERDYIER::CERDYIE_0
+    }
+    #[doc = "Checks if the value of the field is `CERDYIE_1`"]
+    #[inline]
+    pub fn is_cerdyie_1(&self) -> bool {
+        *self == CERDYIER::CERDYIE_1
+    }
+}
+#[doc = "Values that can be written to the field `CEIFG`"]
+pub enum CEIFGW {
+    #[doc = "No interrupt pending"]
+    CEIFG_0,
+    #[doc = "Interrupt pending"]
+    CEIFG_1,
+}
+impl CEIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEIFGW::CEIFG_0 => false,
+            CEIFGW::CEIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ceifg_0(self) -> &'a mut W {
+        self.variant(CEIFGW::CEIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ceifg_1(self) -> &'a mut W {
+        self.variant(CEIFGW::CEIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEIIFG`"]
+pub enum CEIIFGW {
+    #[doc = "No interrupt pending"]
+    CEIIFG_0,
+    #[doc = "Interrupt pending"]
+    CEIIFG_1,
+}
+impl CEIIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEIIFGW::CEIIFG_0 => false,
+            CEIIFGW::CEIIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEIIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEIIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEIIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ceiifg_0(self) -> &'a mut W {
+        self.variant(CEIIFGW::CEIIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ceiifg_1(self) -> &'a mut W {
+        self.variant(CEIIFGW::CEIIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CERDYIFG`"]
+pub enum CERDYIFGW {
+    #[doc = "No interrupt pending"]
+    CERDYIFG_0,
+    #[doc = "Interrupt pending"]
+    CERDYIFG_1,
+}
+impl CERDYIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CERDYIFGW::CERDYIFG_0 => false,
+            CERDYIFGW::CERDYIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CERDYIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CERDYIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CERDYIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn cerdyifg_0(self) -> &'a mut W {
+        self.variant(CERDYIFGW::CERDYIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn cerdyifg_1(self) -> &'a mut W {
+        self.variant(CERDYIFGW::CERDYIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEIE`"]
+pub enum CEIEW {
+    #[doc = "Interrupt disabled"]
+    CEIE_0,
+    #[doc = "Interrupt enabled"]
+    CEIE_1,
+}
+impl CEIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEIEW::CEIE_0 => false,
+            CEIEW::CEIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ceie_0(self) -> &'a mut W {
+        self.variant(CEIEW::CEIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ceie_1(self) -> &'a mut W {
+        self.variant(CEIEW::CEIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEIIE`"]
+pub enum CEIIEW {
+    #[doc = "Interrupt disabled"]
+    CEIIE_0,
+    #[doc = "Interrupt enabled"]
+    CEIIE_1,
+}
+impl CEIIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEIIEW::CEIIE_0 => false,
+            CEIIEW::CEIIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEIIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEIIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEIIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ceiie_0(self) -> &'a mut W {
+        self.variant(CEIIEW::CEIIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ceiie_1(self) -> &'a mut W {
+        self.variant(CEIIEW::CEIIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CERDYIE`"]
+pub enum CERDYIEW {
+    #[doc = "Interrupt disabled"]
+    CERDYIE_0,
+    #[doc = "Interrupt enabled"]
+    CERDYIE_1,
+}
+impl CERDYIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CERDYIEW::CERDYIE_0 => false,
+            CERDYIEW::CERDYIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CERDYIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CERDYIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CERDYIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn cerdyie_0(self) -> &'a mut W {
+        self.variant(CERDYIEW::CERDYIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn cerdyie_1(self) -> &'a mut W {
+        self.variant(CERDYIEW::CERDYIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Comparator output interrupt flag"]
+    #[inline]
+    pub fn ceifg(&self) -> CEIFGR {
+        CEIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Comparator output inverted interrupt flag"]
+    #[inline]
+    pub fn ceiifg(&self) -> CEIIFGR {
+        CEIIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 4 - Comparator ready interrupt flag"]
+    #[inline]
+    pub fn cerdyifg(&self) -> CERDYIFGR {
+        CERDYIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 8 - Comparator output interrupt enable"]
+    #[inline]
+    pub fn ceie(&self) -> CEIER {
+        CEIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 9 - Comparator output interrupt enable inverted polarity"]
+    #[inline]
+    pub fn ceiie(&self) -> CEIIER {
+        CEIIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 12 - Comparator ready interrupt enable"]
+    #[inline]
+    pub fn cerdyie(&self) -> CERDYIER {
+        CERDYIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Comparator output interrupt flag"]
+    #[inline]
+    pub fn ceifg(&mut self) -> _CEIFGW {
+        _CEIFGW { w: self }
+    }
+    #[doc = "Bit 1 - Comparator output inverted interrupt flag"]
+    #[inline]
+    pub fn ceiifg(&mut self) -> _CEIIFGW {
+        _CEIIFGW { w: self }
+    }
+    #[doc = "Bit 4 - Comparator ready interrupt flag"]
+    #[inline]
+    pub fn cerdyifg(&mut self) -> _CERDYIFGW {
+        _CERDYIFGW { w: self }
+    }
+    #[doc = "Bit 8 - Comparator output interrupt enable"]
+    #[inline]
+    pub fn ceie(&mut self) -> _CEIEW {
+        _CEIEW { w: self }
+    }
+    #[doc = "Bit 9 - Comparator output interrupt enable inverted polarity"]
+    #[inline]
+    pub fn ceiie(&mut self) -> _CEIIEW {
+        _CEIIEW { w: self }
+    }
+    #[doc = "Bit 12 - Comparator ready interrupt enable"]
+    #[inline]
+    pub fn cerdyie(&mut self) -> _CERDYIEW {
+        _CERDYIEW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/comp_e0/cex_iv.rs b/example-source/msp432p401r/src/comp_e0/cex_iv.rs
new file mode 100644
index 0000000..af3dc02
--- /dev/null
+++ b/example-source/msp432p401r/src/comp_e0/cex_iv.rs
@@ -0,0 +1,88 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::CEXIV {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `CEIV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEIVR {
+    #[doc = "No interrupt pending"]
+    CEIV_0,
+    #[doc = "Interrupt Source: CEOUT interrupt; Interrupt Flag: CEIFG; Interrupt Priority: Highest"]
+    CEIV_2,
+    #[doc = "Interrupt Source: CEOUT interrupt inverted polarity; Interrupt Flag: CEIIFG"]
+    CEIV_4,
+    #[doc = "Interrupt Source: Comparator ready interrupt; Interrupt Flag: CERDYIFG; Interrupt Priority: Lowest"]
+    CEIV_10,
+    #[doc = r" Reserved"]
+    _Reserved(u16),
+}
+impl CEIVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        match *self {
+            CEIVR::CEIV_0 => 0,
+            CEIVR::CEIV_2 => 2,
+            CEIVR::CEIV_4 => 4,
+            CEIVR::CEIV_10 => 10,
+            CEIVR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u16) -> CEIVR {
+        match value {
+            0 => CEIVR::CEIV_0,
+            2 => CEIVR::CEIV_2,
+            4 => CEIVR::CEIV_4,
+            10 => CEIVR::CEIV_10,
+            i => CEIVR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEIV_0`"]
+    #[inline]
+    pub fn is_ceiv_0(&self) -> bool {
+        *self == CEIVR::CEIV_0
+    }
+    #[doc = "Checks if the value of the field is `CEIV_2`"]
+    #[inline]
+    pub fn is_ceiv_2(&self) -> bool {
+        *self == CEIVR::CEIV_2
+    }
+    #[doc = "Checks if the value of the field is `CEIV_4`"]
+    #[inline]
+    pub fn is_ceiv_4(&self) -> bool {
+        *self == CEIVR::CEIV_4
+    }
+    #[doc = "Checks if the value of the field is `CEIV_10`"]
+    #[inline]
+    pub fn is_ceiv_10(&self) -> bool {
+        *self == CEIVR::CEIV_10
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Comparator interrupt vector word register"]
+    #[inline]
+    pub fn ceiv(&self) -> CEIVR {
+        CEIVR::_from({
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/comp_e1.rs b/example-source/msp432p401r/src/comp_e1.rs
new file mode 100644
index 0000000..e551fe3
--- /dev/null
+++ b/example-source/msp432p401r/src/comp_e1.rs
@@ -0,0 +1,53 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - Comparator Control Register 0"]
+    pub cex_ctl0: CEXCTL0,
+    #[doc = "0x02 - Comparator Control Register 1"]
+    pub cex_ctl1: CEXCTL1,
+    #[doc = "0x04 - Comparator Control Register 2"]
+    pub cex_ctl2: CEXCTL2,
+    #[doc = "0x06 - Comparator Control Register 3"]
+    pub cex_ctl3: CEXCTL3,
+    _reserved0: [u8; 4usize],
+    #[doc = "0x0c - Comparator Interrupt Control Register"]
+    pub cex_int: CEXINT,
+    #[doc = "0x0e - Comparator Interrupt Vector Word Register"]
+    pub cex_iv: CEXIV,
+}
+#[doc = "Comparator Control Register 0"]
+pub struct CEXCTL0 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Comparator Control Register 0"]
+pub mod cex_ctl0;
+#[doc = "Comparator Control Register 1"]
+pub struct CEXCTL1 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Comparator Control Register 1"]
+pub mod cex_ctl1;
+#[doc = "Comparator Control Register 2"]
+pub struct CEXCTL2 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Comparator Control Register 2"]
+pub mod cex_ctl2;
+#[doc = "Comparator Control Register 3"]
+pub struct CEXCTL3 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Comparator Control Register 3"]
+pub mod cex_ctl3;
+#[doc = "Comparator Interrupt Control Register"]
+pub struct CEXINT {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Comparator Interrupt Control Register"]
+pub mod cex_int;
+#[doc = "Comparator Interrupt Vector Word Register"]
+pub struct CEXIV {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Comparator Interrupt Vector Word Register"]
+pub mod cex_iv;
diff --git a/example-source/msp432p401r/src/comp_e1/cex_ctl0.rs b/example-source/msp432p401r/src/comp_e1/cex_ctl0.rs
new file mode 100644
index 0000000..fabaa87
--- /dev/null
+++ b/example-source/msp432p401r/src/comp_e1/cex_ctl0.rs
@@ -0,0 +1,982 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::CEXCTL0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `CEIPSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEIPSELR {
+    #[doc = "Channel 0 selected"]
+    CEIPSEL_0,
+    #[doc = "Channel 1 selected"]
+    CEIPSEL_1,
+    #[doc = "Channel 2 selected"]
+    CEIPSEL_2,
+    #[doc = "Channel 3 selected"]
+    CEIPSEL_3,
+    #[doc = "Channel 4 selected"]
+    CEIPSEL_4,
+    #[doc = "Channel 5 selected"]
+    CEIPSEL_5,
+    #[doc = "Channel 6 selected"]
+    CEIPSEL_6,
+    #[doc = "Channel 7 selected"]
+    CEIPSEL_7,
+    #[doc = "Channel 8 selected"]
+    CEIPSEL_8,
+    #[doc = "Channel 9 selected"]
+    CEIPSEL_9,
+    #[doc = "Channel 10 selected"]
+    CEIPSEL_10,
+    #[doc = "Channel 11 selected"]
+    CEIPSEL_11,
+    #[doc = "Channel 12 selected"]
+    CEIPSEL_12,
+    #[doc = "Channel 13 selected"]
+    CEIPSEL_13,
+    #[doc = "Channel 14 selected"]
+    CEIPSEL_14,
+    #[doc = "Channel 15 selected"]
+    CEIPSEL_15,
+}
+impl CEIPSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            CEIPSELR::CEIPSEL_0 => 0,
+            CEIPSELR::CEIPSEL_1 => 1,
+            CEIPSELR::CEIPSEL_2 => 2,
+            CEIPSELR::CEIPSEL_3 => 3,
+            CEIPSELR::CEIPSEL_4 => 4,
+            CEIPSELR::CEIPSEL_5 => 5,
+            CEIPSELR::CEIPSEL_6 => 6,
+            CEIPSELR::CEIPSEL_7 => 7,
+            CEIPSELR::CEIPSEL_8 => 8,
+            CEIPSELR::CEIPSEL_9 => 9,
+            CEIPSELR::CEIPSEL_10 => 10,
+            CEIPSELR::CEIPSEL_11 => 11,
+            CEIPSELR::CEIPSEL_12 => 12,
+            CEIPSELR::CEIPSEL_13 => 13,
+            CEIPSELR::CEIPSEL_14 => 14,
+            CEIPSELR::CEIPSEL_15 => 15,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> CEIPSELR {
+        match value {
+            0 => CEIPSELR::CEIPSEL_0,
+            1 => CEIPSELR::CEIPSEL_1,
+            2 => CEIPSELR::CEIPSEL_2,
+            3 => CEIPSELR::CEIPSEL_3,
+            4 => CEIPSELR::CEIPSEL_4,
+            5 => CEIPSELR::CEIPSEL_5,
+            6 => CEIPSELR::CEIPSEL_6,
+            7 => CEIPSELR::CEIPSEL_7,
+            8 => CEIPSELR::CEIPSEL_8,
+            9 => CEIPSELR::CEIPSEL_9,
+            10 => CEIPSELR::CEIPSEL_10,
+            11 => CEIPSELR::CEIPSEL_11,
+            12 => CEIPSELR::CEIPSEL_12,
+            13 => CEIPSELR::CEIPSEL_13,
+            14 => CEIPSELR::CEIPSEL_14,
+            15 => CEIPSELR::CEIPSEL_15,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_0`"]
+    #[inline]
+    pub fn is_ceipsel_0(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_0
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_1`"]
+    #[inline]
+    pub fn is_ceipsel_1(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_1
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_2`"]
+    #[inline]
+    pub fn is_ceipsel_2(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_2
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_3`"]
+    #[inline]
+    pub fn is_ceipsel_3(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_3
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_4`"]
+    #[inline]
+    pub fn is_ceipsel_4(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_4
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_5`"]
+    #[inline]
+    pub fn is_ceipsel_5(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_5
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_6`"]
+    #[inline]
+    pub fn is_ceipsel_6(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_6
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_7`"]
+    #[inline]
+    pub fn is_ceipsel_7(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_7
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_8`"]
+    #[inline]
+    pub fn is_ceipsel_8(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_8
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_9`"]
+    #[inline]
+    pub fn is_ceipsel_9(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_9
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_10`"]
+    #[inline]
+    pub fn is_ceipsel_10(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_10
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_11`"]
+    #[inline]
+    pub fn is_ceipsel_11(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_11
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_12`"]
+    #[inline]
+    pub fn is_ceipsel_12(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_12
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_13`"]
+    #[inline]
+    pub fn is_ceipsel_13(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_13
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_14`"]
+    #[inline]
+    pub fn is_ceipsel_14(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_14
+    }
+    #[doc = "Checks if the value of the field is `CEIPSEL_15`"]
+    #[inline]
+    pub fn is_ceipsel_15(&self) -> bool {
+        *self == CEIPSELR::CEIPSEL_15
+    }
+}
+#[doc = "Possible values of the field `CEIPEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEIPENR {
+    #[doc = "Selected analog input channel for V+ terminal is disabled"]
+    CEIPEN_0,
+    #[doc = "Selected analog input channel for V+ terminal is enabled"]
+    CEIPEN_1,
+}
+impl CEIPENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEIPENR::CEIPEN_0 => false,
+            CEIPENR::CEIPEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEIPENR {
+        match value {
+            false => CEIPENR::CEIPEN_0,
+            true => CEIPENR::CEIPEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEIPEN_0`"]
+    #[inline]
+    pub fn is_ceipen_0(&self) -> bool {
+        *self == CEIPENR::CEIPEN_0
+    }
+    #[doc = "Checks if the value of the field is `CEIPEN_1`"]
+    #[inline]
+    pub fn is_ceipen_1(&self) -> bool {
+        *self == CEIPENR::CEIPEN_1
+    }
+}
+#[doc = "Possible values of the field `CEIMSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEIMSELR {
+    #[doc = "Channel 0 selected"]
+    CEIMSEL_0,
+    #[doc = "Channel 1 selected"]
+    CEIMSEL_1,
+    #[doc = "Channel 2 selected"]
+    CEIMSEL_2,
+    #[doc = "Channel 3 selected"]
+    CEIMSEL_3,
+    #[doc = "Channel 4 selected"]
+    CEIMSEL_4,
+    #[doc = "Channel 5 selected"]
+    CEIMSEL_5,
+    #[doc = "Channel 6 selected"]
+    CEIMSEL_6,
+    #[doc = "Channel 7 selected"]
+    CEIMSEL_7,
+    #[doc = "Channel 8 selected"]
+    CEIMSEL_8,
+    #[doc = "Channel 9 selected"]
+    CEIMSEL_9,
+    #[doc = "Channel 10 selected"]
+    CEIMSEL_10,
+    #[doc = "Channel 11 selected"]
+    CEIMSEL_11,
+    #[doc = "Channel 12 selected"]
+    CEIMSEL_12,
+    #[doc = "Channel 13 selected"]
+    CEIMSEL_13,
+    #[doc = "Channel 14 selected"]
+    CEIMSEL_14,
+    #[doc = "Channel 15 selected"]
+    CEIMSEL_15,
+}
+impl CEIMSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            CEIMSELR::CEIMSEL_0 => 0,
+            CEIMSELR::CEIMSEL_1 => 1,
+            CEIMSELR::CEIMSEL_2 => 2,
+            CEIMSELR::CEIMSEL_3 => 3,
+            CEIMSELR::CEIMSEL_4 => 4,
+            CEIMSELR::CEIMSEL_5 => 5,
+            CEIMSELR::CEIMSEL_6 => 6,
+            CEIMSELR::CEIMSEL_7 => 7,
+            CEIMSELR::CEIMSEL_8 => 8,
+            CEIMSELR::CEIMSEL_9 => 9,
+            CEIMSELR::CEIMSEL_10 => 10,
+            CEIMSELR::CEIMSEL_11 => 11,
+            CEIMSELR::CEIMSEL_12 => 12,
+            CEIMSELR::CEIMSEL_13 => 13,
+            CEIMSELR::CEIMSEL_14 => 14,
+            CEIMSELR::CEIMSEL_15 => 15,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> CEIMSELR {
+        match value {
+            0 => CEIMSELR::CEIMSEL_0,
+            1 => CEIMSELR::CEIMSEL_1,
+            2 => CEIMSELR::CEIMSEL_2,
+            3 => CEIMSELR::CEIMSEL_3,
+            4 => CEIMSELR::CEIMSEL_4,
+            5 => CEIMSELR::CEIMSEL_5,
+            6 => CEIMSELR::CEIMSEL_6,
+            7 => CEIMSELR::CEIMSEL_7,
+            8 => CEIMSELR::CEIMSEL_8,
+            9 => CEIMSELR::CEIMSEL_9,
+            10 => CEIMSELR::CEIMSEL_10,
+            11 => CEIMSELR::CEIMSEL_11,
+            12 => CEIMSELR::CEIMSEL_12,
+            13 => CEIMSELR::CEIMSEL_13,
+            14 => CEIMSELR::CEIMSEL_14,
+            15 => CEIMSELR::CEIMSEL_15,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_0`"]
+    #[inline]
+    pub fn is_ceimsel_0(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_0
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_1`"]
+    #[inline]
+    pub fn is_ceimsel_1(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_1
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_2`"]
+    #[inline]
+    pub fn is_ceimsel_2(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_2
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_3`"]
+    #[inline]
+    pub fn is_ceimsel_3(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_3
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_4`"]
+    #[inline]
+    pub fn is_ceimsel_4(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_4
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_5`"]
+    #[inline]
+    pub fn is_ceimsel_5(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_5
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_6`"]
+    #[inline]
+    pub fn is_ceimsel_6(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_6
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_7`"]
+    #[inline]
+    pub fn is_ceimsel_7(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_7
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_8`"]
+    #[inline]
+    pub fn is_ceimsel_8(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_8
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_9`"]
+    #[inline]
+    pub fn is_ceimsel_9(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_9
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_10`"]
+    #[inline]
+    pub fn is_ceimsel_10(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_10
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_11`"]
+    #[inline]
+    pub fn is_ceimsel_11(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_11
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_12`"]
+    #[inline]
+    pub fn is_ceimsel_12(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_12
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_13`"]
+    #[inline]
+    pub fn is_ceimsel_13(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_13
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_14`"]
+    #[inline]
+    pub fn is_ceimsel_14(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_14
+    }
+    #[doc = "Checks if the value of the field is `CEIMSEL_15`"]
+    #[inline]
+    pub fn is_ceimsel_15(&self) -> bool {
+        *self == CEIMSELR::CEIMSEL_15
+    }
+}
+#[doc = "Possible values of the field `CEIMEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEIMENR {
+    #[doc = "Selected analog input channel for V- terminal is disabled"]
+    CEIMEN_0,
+    #[doc = "Selected analog input channel for V- terminal is enabled"]
+    CEIMEN_1,
+}
+impl CEIMENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEIMENR::CEIMEN_0 => false,
+            CEIMENR::CEIMEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEIMENR {
+        match value {
+            false => CEIMENR::CEIMEN_0,
+            true => CEIMENR::CEIMEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEIMEN_0`"]
+    #[inline]
+    pub fn is_ceimen_0(&self) -> bool {
+        *self == CEIMENR::CEIMEN_0
+    }
+    #[doc = "Checks if the value of the field is `CEIMEN_1`"]
+    #[inline]
+    pub fn is_ceimen_1(&self) -> bool {
+        *self == CEIMENR::CEIMEN_1
+    }
+}
+#[doc = "Values that can be written to the field `CEIPSEL`"]
+pub enum CEIPSELW {
+    #[doc = "Channel 0 selected"]
+    CEIPSEL_0,
+    #[doc = "Channel 1 selected"]
+    CEIPSEL_1,
+    #[doc = "Channel 2 selected"]
+    CEIPSEL_2,
+    #[doc = "Channel 3 selected"]
+    CEIPSEL_3,
+    #[doc = "Channel 4 selected"]
+    CEIPSEL_4,
+    #[doc = "Channel 5 selected"]
+    CEIPSEL_5,
+    #[doc = "Channel 6 selected"]
+    CEIPSEL_6,
+    #[doc = "Channel 7 selected"]
+    CEIPSEL_7,
+    #[doc = "Channel 8 selected"]
+    CEIPSEL_8,
+    #[doc = "Channel 9 selected"]
+    CEIPSEL_9,
+    #[doc = "Channel 10 selected"]
+    CEIPSEL_10,
+    #[doc = "Channel 11 selected"]
+    CEIPSEL_11,
+    #[doc = "Channel 12 selected"]
+    CEIPSEL_12,
+    #[doc = "Channel 13 selected"]
+    CEIPSEL_13,
+    #[doc = "Channel 14 selected"]
+    CEIPSEL_14,
+    #[doc = "Channel 15 selected"]
+    CEIPSEL_15,
+}
+impl CEIPSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            CEIPSELW::CEIPSEL_0 => 0,
+            CEIPSELW::CEIPSEL_1 => 1,
+            CEIPSELW::CEIPSEL_2 => 2,
+            CEIPSELW::CEIPSEL_3 => 3,
+            CEIPSELW::CEIPSEL_4 => 4,
+            CEIPSELW::CEIPSEL_5 => 5,
+            CEIPSELW::CEIPSEL_6 => 6,
+            CEIPSELW::CEIPSEL_7 => 7,
+            CEIPSELW::CEIPSEL_8 => 8,
+            CEIPSELW::CEIPSEL_9 => 9,
+            CEIPSELW::CEIPSEL_10 => 10,
+            CEIPSELW::CEIPSEL_11 => 11,
+            CEIPSELW::CEIPSEL_12 => 12,
+            CEIPSELW::CEIPSEL_13 => 13,
+            CEIPSELW::CEIPSEL_14 => 14,
+            CEIPSELW::CEIPSEL_15 => 15,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEIPSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEIPSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEIPSELW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Channel 0 selected"]
+    #[inline]
+    pub fn ceipsel_0(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_0)
+    }
+    #[doc = "Channel 1 selected"]
+    #[inline]
+    pub fn ceipsel_1(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_1)
+    }
+    #[doc = "Channel 2 selected"]
+    #[inline]
+    pub fn ceipsel_2(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_2)
+    }
+    #[doc = "Channel 3 selected"]
+    #[inline]
+    pub fn ceipsel_3(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_3)
+    }
+    #[doc = "Channel 4 selected"]
+    #[inline]
+    pub fn ceipsel_4(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_4)
+    }
+    #[doc = "Channel 5 selected"]
+    #[inline]
+    pub fn ceipsel_5(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_5)
+    }
+    #[doc = "Channel 6 selected"]
+    #[inline]
+    pub fn ceipsel_6(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_6)
+    }
+    #[doc = "Channel 7 selected"]
+    #[inline]
+    pub fn ceipsel_7(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_7)
+    }
+    #[doc = "Channel 8 selected"]
+    #[inline]
+    pub fn ceipsel_8(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_8)
+    }
+    #[doc = "Channel 9 selected"]
+    #[inline]
+    pub fn ceipsel_9(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_9)
+    }
+    #[doc = "Channel 10 selected"]
+    #[inline]
+    pub fn ceipsel_10(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_10)
+    }
+    #[doc = "Channel 11 selected"]
+    #[inline]
+    pub fn ceipsel_11(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_11)
+    }
+    #[doc = "Channel 12 selected"]
+    #[inline]
+    pub fn ceipsel_12(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_12)
+    }
+    #[doc = "Channel 13 selected"]
+    #[inline]
+    pub fn ceipsel_13(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_13)
+    }
+    #[doc = "Channel 14 selected"]
+    #[inline]
+    pub fn ceipsel_14(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_14)
+    }
+    #[doc = "Channel 15 selected"]
+    #[inline]
+    pub fn ceipsel_15(self) -> &'a mut W {
+        self.variant(CEIPSELW::CEIPSEL_15)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEIPEN`"]
+pub enum CEIPENW {
+    #[doc = "Selected analog input channel for V+ terminal is disabled"]
+    CEIPEN_0,
+    #[doc = "Selected analog input channel for V+ terminal is enabled"]
+    CEIPEN_1,
+}
+impl CEIPENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEIPENW::CEIPEN_0 => false,
+            CEIPENW::CEIPEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEIPENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEIPENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEIPENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Selected analog input channel for V+ terminal is disabled"]
+    #[inline]
+    pub fn ceipen_0(self) -> &'a mut W {
+        self.variant(CEIPENW::CEIPEN_0)
+    }
+    #[doc = "Selected analog input channel for V+ terminal is enabled"]
+    #[inline]
+    pub fn ceipen_1(self) -> &'a mut W {
+        self.variant(CEIPENW::CEIPEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEIMSEL`"]
+pub enum CEIMSELW {
+    #[doc = "Channel 0 selected"]
+    CEIMSEL_0,
+    #[doc = "Channel 1 selected"]
+    CEIMSEL_1,
+    #[doc = "Channel 2 selected"]
+    CEIMSEL_2,
+    #[doc = "Channel 3 selected"]
+    CEIMSEL_3,
+    #[doc = "Channel 4 selected"]
+    CEIMSEL_4,
+    #[doc = "Channel 5 selected"]
+    CEIMSEL_5,
+    #[doc = "Channel 6 selected"]
+    CEIMSEL_6,
+    #[doc = "Channel 7 selected"]
+    CEIMSEL_7,
+    #[doc = "Channel 8 selected"]
+    CEIMSEL_8,
+    #[doc = "Channel 9 selected"]
+    CEIMSEL_9,
+    #[doc = "Channel 10 selected"]
+    CEIMSEL_10,
+    #[doc = "Channel 11 selected"]
+    CEIMSEL_11,
+    #[doc = "Channel 12 selected"]
+    CEIMSEL_12,
+    #[doc = "Channel 13 selected"]
+    CEIMSEL_13,
+    #[doc = "Channel 14 selected"]
+    CEIMSEL_14,
+    #[doc = "Channel 15 selected"]
+    CEIMSEL_15,
+}
+impl CEIMSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            CEIMSELW::CEIMSEL_0 => 0,
+            CEIMSELW::CEIMSEL_1 => 1,
+            CEIMSELW::CEIMSEL_2 => 2,
+            CEIMSELW::CEIMSEL_3 => 3,
+            CEIMSELW::CEIMSEL_4 => 4,
+            CEIMSELW::CEIMSEL_5 => 5,
+            CEIMSELW::CEIMSEL_6 => 6,
+            CEIMSELW::CEIMSEL_7 => 7,
+            CEIMSELW::CEIMSEL_8 => 8,
+            CEIMSELW::CEIMSEL_9 => 9,
+            CEIMSELW::CEIMSEL_10 => 10,
+            CEIMSELW::CEIMSEL_11 => 11,
+            CEIMSELW::CEIMSEL_12 => 12,
+            CEIMSELW::CEIMSEL_13 => 13,
+            CEIMSELW::CEIMSEL_14 => 14,
+            CEIMSELW::CEIMSEL_15 => 15,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEIMSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEIMSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEIMSELW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Channel 0 selected"]
+    #[inline]
+    pub fn ceimsel_0(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_0)
+    }
+    #[doc = "Channel 1 selected"]
+    #[inline]
+    pub fn ceimsel_1(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_1)
+    }
+    #[doc = "Channel 2 selected"]
+    #[inline]
+    pub fn ceimsel_2(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_2)
+    }
+    #[doc = "Channel 3 selected"]
+    #[inline]
+    pub fn ceimsel_3(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_3)
+    }
+    #[doc = "Channel 4 selected"]
+    #[inline]
+    pub fn ceimsel_4(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_4)
+    }
+    #[doc = "Channel 5 selected"]
+    #[inline]
+    pub fn ceimsel_5(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_5)
+    }
+    #[doc = "Channel 6 selected"]
+    #[inline]
+    pub fn ceimsel_6(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_6)
+    }
+    #[doc = "Channel 7 selected"]
+    #[inline]
+    pub fn ceimsel_7(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_7)
+    }
+    #[doc = "Channel 8 selected"]
+    #[inline]
+    pub fn ceimsel_8(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_8)
+    }
+    #[doc = "Channel 9 selected"]
+    #[inline]
+    pub fn ceimsel_9(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_9)
+    }
+    #[doc = "Channel 10 selected"]
+    #[inline]
+    pub fn ceimsel_10(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_10)
+    }
+    #[doc = "Channel 11 selected"]
+    #[inline]
+    pub fn ceimsel_11(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_11)
+    }
+    #[doc = "Channel 12 selected"]
+    #[inline]
+    pub fn ceimsel_12(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_12)
+    }
+    #[doc = "Channel 13 selected"]
+    #[inline]
+    pub fn ceimsel_13(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_13)
+    }
+    #[doc = "Channel 14 selected"]
+    #[inline]
+    pub fn ceimsel_14(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_14)
+    }
+    #[doc = "Channel 15 selected"]
+    #[inline]
+    pub fn ceimsel_15(self) -> &'a mut W {
+        self.variant(CEIMSELW::CEIMSEL_15)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEIMEN`"]
+pub enum CEIMENW {
+    #[doc = "Selected analog input channel for V- terminal is disabled"]
+    CEIMEN_0,
+    #[doc = "Selected analog input channel for V- terminal is enabled"]
+    CEIMEN_1,
+}
+impl CEIMENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEIMENW::CEIMEN_0 => false,
+            CEIMENW::CEIMEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEIMENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEIMENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEIMENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Selected analog input channel for V- terminal is disabled"]
+    #[inline]
+    pub fn ceimen_0(self) -> &'a mut W {
+        self.variant(CEIMENW::CEIMEN_0)
+    }
+    #[doc = "Selected analog input channel for V- terminal is enabled"]
+    #[inline]
+    pub fn ceimen_1(self) -> &'a mut W {
+        self.variant(CEIMENW::CEIMEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:3 - Channel input selected for the V+ terminal"]
+    #[inline]
+    pub fn ceipsel(&self) -> CEIPSELR {
+        CEIPSELR::_from({
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 7 - Channel input enable for the V+ terminal"]
+    #[inline]
+    pub fn ceipen(&self) -> CEIPENR {
+        CEIPENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 8:11 - Channel input selected for the - terminal"]
+    #[inline]
+    pub fn ceimsel(&self) -> CEIMSELR {
+        CEIMSELR::_from({
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 15 - Channel input enable for the - terminal"]
+    #[inline]
+    pub fn ceimen(&self) -> CEIMENR {
+        CEIMENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:3 - Channel input selected for the V+ terminal"]
+    #[inline]
+    pub fn ceipsel(&mut self) -> _CEIPSELW {
+        _CEIPSELW { w: self }
+    }
+    #[doc = "Bit 7 - Channel input enable for the V+ terminal"]
+    #[inline]
+    pub fn ceipen(&mut self) -> _CEIPENW {
+        _CEIPENW { w: self }
+    }
+    #[doc = "Bits 8:11 - Channel input selected for the - terminal"]
+    #[inline]
+    pub fn ceimsel(&mut self) -> _CEIMSELW {
+        _CEIMSELW { w: self }
+    }
+    #[doc = "Bit 15 - Channel input enable for the - terminal"]
+    #[inline]
+    pub fn ceimen(&mut self) -> _CEIMENW {
+        _CEIMENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/comp_e1/cex_ctl1.rs b/example-source/msp432p401r/src/comp_e1/cex_ctl1.rs
new file mode 100644
index 0000000..4b485b5
--- /dev/null
+++ b/example-source/msp432p401r/src/comp_e1/cex_ctl1.rs
@@ -0,0 +1,1271 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::CEXCTL1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CEOUTR {
+    bits: bool,
+}
+impl CEOUTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `CEOUTPOL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEOUTPOLR {
+    #[doc = "Noninverted"]
+    CEOUTPOL_0,
+    #[doc = "Inverted"]
+    CEOUTPOL_1,
+}
+impl CEOUTPOLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEOUTPOLR::CEOUTPOL_0 => false,
+            CEOUTPOLR::CEOUTPOL_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEOUTPOLR {
+        match value {
+            false => CEOUTPOLR::CEOUTPOL_0,
+            true => CEOUTPOLR::CEOUTPOL_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEOUTPOL_0`"]
+    #[inline]
+    pub fn is_ceoutpol_0(&self) -> bool {
+        *self == CEOUTPOLR::CEOUTPOL_0
+    }
+    #[doc = "Checks if the value of the field is `CEOUTPOL_1`"]
+    #[inline]
+    pub fn is_ceoutpol_1(&self) -> bool {
+        *self == CEOUTPOLR::CEOUTPOL_1
+    }
+}
+#[doc = "Possible values of the field `CEF`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEFR {
+    #[doc = "Comparator output is not filtered"]
+    CEF_0,
+    #[doc = "Comparator output is filtered"]
+    CEF_1,
+}
+impl CEFR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEFR::CEF_0 => false,
+            CEFR::CEF_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEFR {
+        match value {
+            false => CEFR::CEF_0,
+            true => CEFR::CEF_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEF_0`"]
+    #[inline]
+    pub fn is_cef_0(&self) -> bool {
+        *self == CEFR::CEF_0
+    }
+    #[doc = "Checks if the value of the field is `CEF_1`"]
+    #[inline]
+    pub fn is_cef_1(&self) -> bool {
+        *self == CEFR::CEF_1
+    }
+}
+#[doc = "Possible values of the field `CEIES`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEIESR {
+    #[doc = "Rising edge for CEIFG, falling edge for CEIIFG"]
+    CEIES_0,
+    #[doc = "Falling edge for CEIFG, rising edge for CEIIFG"]
+    CEIES_1,
+}
+impl CEIESR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEIESR::CEIES_0 => false,
+            CEIESR::CEIES_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEIESR {
+        match value {
+            false => CEIESR::CEIES_0,
+            true => CEIESR::CEIES_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEIES_0`"]
+    #[inline]
+    pub fn is_ceies_0(&self) -> bool {
+        *self == CEIESR::CEIES_0
+    }
+    #[doc = "Checks if the value of the field is `CEIES_1`"]
+    #[inline]
+    pub fn is_ceies_1(&self) -> bool {
+        *self == CEIESR::CEIES_1
+    }
+}
+#[doc = "Possible values of the field `CESHORT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CESHORTR {
+    #[doc = "Inputs not shorted"]
+    CESHORT_0,
+    #[doc = "Inputs shorted"]
+    CESHORT_1,
+}
+impl CESHORTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CESHORTR::CESHORT_0 => false,
+            CESHORTR::CESHORT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CESHORTR {
+        match value {
+            false => CESHORTR::CESHORT_0,
+            true => CESHORTR::CESHORT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CESHORT_0`"]
+    #[inline]
+    pub fn is_ceshort_0(&self) -> bool {
+        *self == CESHORTR::CESHORT_0
+    }
+    #[doc = "Checks if the value of the field is `CESHORT_1`"]
+    #[inline]
+    pub fn is_ceshort_1(&self) -> bool {
+        *self == CESHORTR::CESHORT_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CEEXR {
+    bits: bool,
+}
+impl CEEXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `CEFDLY`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEFDLYR {
+    #[doc = "Typical filter delay of TBD (450) ns"]
+    CEFDLY_0,
+    #[doc = "Typical filter delay of TBD (900) ns"]
+    CEFDLY_1,
+    #[doc = "Typical filter delay of TBD (1800) ns"]
+    CEFDLY_2,
+    #[doc = "Typical filter delay of TBD (3600) ns"]
+    CEFDLY_3,
+}
+impl CEFDLYR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            CEFDLYR::CEFDLY_0 => 0,
+            CEFDLYR::CEFDLY_1 => 1,
+            CEFDLYR::CEFDLY_2 => 2,
+            CEFDLYR::CEFDLY_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> CEFDLYR {
+        match value {
+            0 => CEFDLYR::CEFDLY_0,
+            1 => CEFDLYR::CEFDLY_1,
+            2 => CEFDLYR::CEFDLY_2,
+            3 => CEFDLYR::CEFDLY_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEFDLY_0`"]
+    #[inline]
+    pub fn is_cefdly_0(&self) -> bool {
+        *self == CEFDLYR::CEFDLY_0
+    }
+    #[doc = "Checks if the value of the field is `CEFDLY_1`"]
+    #[inline]
+    pub fn is_cefdly_1(&self) -> bool {
+        *self == CEFDLYR::CEFDLY_1
+    }
+    #[doc = "Checks if the value of the field is `CEFDLY_2`"]
+    #[inline]
+    pub fn is_cefdly_2(&self) -> bool {
+        *self == CEFDLYR::CEFDLY_2
+    }
+    #[doc = "Checks if the value of the field is `CEFDLY_3`"]
+    #[inline]
+    pub fn is_cefdly_3(&self) -> bool {
+        *self == CEFDLYR::CEFDLY_3
+    }
+}
+#[doc = "Possible values of the field `CEPWRMD`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPWRMDR {
+    #[doc = "High-speed mode"]
+    CEPWRMD_0,
+    #[doc = "Normal mode"]
+    CEPWRMD_1,
+    #[doc = "Ultra-low power mode"]
+    CEPWRMD_2,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl CEPWRMDR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            CEPWRMDR::CEPWRMD_0 => 0,
+            CEPWRMDR::CEPWRMD_1 => 1,
+            CEPWRMDR::CEPWRMD_2 => 2,
+            CEPWRMDR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> CEPWRMDR {
+        match value {
+            0 => CEPWRMDR::CEPWRMD_0,
+            1 => CEPWRMDR::CEPWRMD_1,
+            2 => CEPWRMDR::CEPWRMD_2,
+            i => CEPWRMDR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPWRMD_0`"]
+    #[inline]
+    pub fn is_cepwrmd_0(&self) -> bool {
+        *self == CEPWRMDR::CEPWRMD_0
+    }
+    #[doc = "Checks if the value of the field is `CEPWRMD_1`"]
+    #[inline]
+    pub fn is_cepwrmd_1(&self) -> bool {
+        *self == CEPWRMDR::CEPWRMD_1
+    }
+    #[doc = "Checks if the value of the field is `CEPWRMD_2`"]
+    #[inline]
+    pub fn is_cepwrmd_2(&self) -> bool {
+        *self == CEPWRMDR::CEPWRMD_2
+    }
+}
+#[doc = "Possible values of the field `CEON`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEONR {
+    #[doc = "Off"]
+    CEON_0,
+    #[doc = "On"]
+    CEON_1,
+}
+impl CEONR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEONR::CEON_0 => false,
+            CEONR::CEON_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEONR {
+        match value {
+            false => CEONR::CEON_0,
+            true => CEONR::CEON_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEON_0`"]
+    #[inline]
+    pub fn is_ceon_0(&self) -> bool {
+        *self == CEONR::CEON_0
+    }
+    #[doc = "Checks if the value of the field is `CEON_1`"]
+    #[inline]
+    pub fn is_ceon_1(&self) -> bool {
+        *self == CEONR::CEON_1
+    }
+}
+#[doc = "Possible values of the field `CEMRVL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEMRVLR {
+    #[doc = "VREF0 is selected if CERS = 00, 01, or 10"]
+    CEMRVL_0,
+    #[doc = "VREF1 is selected if CERS = 00, 01, or 10"]
+    CEMRVL_1,
+}
+impl CEMRVLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEMRVLR::CEMRVL_0 => false,
+            CEMRVLR::CEMRVL_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEMRVLR {
+        match value {
+            false => CEMRVLR::CEMRVL_0,
+            true => CEMRVLR::CEMRVL_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEMRVL_0`"]
+    #[inline]
+    pub fn is_cemrvl_0(&self) -> bool {
+        *self == CEMRVLR::CEMRVL_0
+    }
+    #[doc = "Checks if the value of the field is `CEMRVL_1`"]
+    #[inline]
+    pub fn is_cemrvl_1(&self) -> bool {
+        *self == CEMRVLR::CEMRVL_1
+    }
+}
+#[doc = "Possible values of the field `CEMRVS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEMRVSR {
+    #[doc = "Comparator output state selects between VREF0 or VREF1"]
+    CEMRVS_0,
+    #[doc = "CEMRVL selects between VREF0 or VREF1"]
+    CEMRVS_1,
+}
+impl CEMRVSR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEMRVSR::CEMRVS_0 => false,
+            CEMRVSR::CEMRVS_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEMRVSR {
+        match value {
+            false => CEMRVSR::CEMRVS_0,
+            true => CEMRVSR::CEMRVS_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEMRVS_0`"]
+    #[inline]
+    pub fn is_cemrvs_0(&self) -> bool {
+        *self == CEMRVSR::CEMRVS_0
+    }
+    #[doc = "Checks if the value of the field is `CEMRVS_1`"]
+    #[inline]
+    pub fn is_cemrvs_1(&self) -> bool {
+        *self == CEMRVSR::CEMRVS_1
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEOUTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEOUTW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEOUTPOL`"]
+pub enum CEOUTPOLW {
+    #[doc = "Noninverted"]
+    CEOUTPOL_0,
+    #[doc = "Inverted"]
+    CEOUTPOL_1,
+}
+impl CEOUTPOLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEOUTPOLW::CEOUTPOL_0 => false,
+            CEOUTPOLW::CEOUTPOL_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEOUTPOLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEOUTPOLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEOUTPOLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Noninverted"]
+    #[inline]
+    pub fn ceoutpol_0(self) -> &'a mut W {
+        self.variant(CEOUTPOLW::CEOUTPOL_0)
+    }
+    #[doc = "Inverted"]
+    #[inline]
+    pub fn ceoutpol_1(self) -> &'a mut W {
+        self.variant(CEOUTPOLW::CEOUTPOL_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEF`"]
+pub enum CEFW {
+    #[doc = "Comparator output is not filtered"]
+    CEF_0,
+    #[doc = "Comparator output is filtered"]
+    CEF_1,
+}
+impl CEFW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEFW::CEF_0 => false,
+            CEFW::CEF_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEFW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEFW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Comparator output is not filtered"]
+    #[inline]
+    pub fn cef_0(self) -> &'a mut W {
+        self.variant(CEFW::CEF_0)
+    }
+    #[doc = "Comparator output is filtered"]
+    #[inline]
+    pub fn cef_1(self) -> &'a mut W {
+        self.variant(CEFW::CEF_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEIES`"]
+pub enum CEIESW {
+    #[doc = "Rising edge for CEIFG, falling edge for CEIIFG"]
+    CEIES_0,
+    #[doc = "Falling edge for CEIFG, rising edge for CEIIFG"]
+    CEIES_1,
+}
+impl CEIESW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEIESW::CEIES_0 => false,
+            CEIESW::CEIES_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEIESW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEIESW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEIESW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Rising edge for CEIFG, falling edge for CEIIFG"]
+    #[inline]
+    pub fn ceies_0(self) -> &'a mut W {
+        self.variant(CEIESW::CEIES_0)
+    }
+    #[doc = "Falling edge for CEIFG, rising edge for CEIIFG"]
+    #[inline]
+    pub fn ceies_1(self) -> &'a mut W {
+        self.variant(CEIESW::CEIES_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CESHORT`"]
+pub enum CESHORTW {
+    #[doc = "Inputs not shorted"]
+    CESHORT_0,
+    #[doc = "Inputs shorted"]
+    CESHORT_1,
+}
+impl CESHORTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CESHORTW::CESHORT_0 => false,
+            CESHORTW::CESHORT_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CESHORTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CESHORTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CESHORTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Inputs not shorted"]
+    #[inline]
+    pub fn ceshort_0(self) -> &'a mut W {
+        self.variant(CESHORTW::CESHORT_0)
+    }
+    #[doc = "Inputs shorted"]
+    #[inline]
+    pub fn ceshort_1(self) -> &'a mut W {
+        self.variant(CESHORTW::CESHORT_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEEXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEEXW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEFDLY`"]
+pub enum CEFDLYW {
+    #[doc = "Typical filter delay of TBD (450) ns"]
+    CEFDLY_0,
+    #[doc = "Typical filter delay of TBD (900) ns"]
+    CEFDLY_1,
+    #[doc = "Typical filter delay of TBD (1800) ns"]
+    CEFDLY_2,
+    #[doc = "Typical filter delay of TBD (3600) ns"]
+    CEFDLY_3,
+}
+impl CEFDLYW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            CEFDLYW::CEFDLY_0 => 0,
+            CEFDLYW::CEFDLY_1 => 1,
+            CEFDLYW::CEFDLY_2 => 2,
+            CEFDLYW::CEFDLY_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEFDLYW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEFDLYW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEFDLYW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Typical filter delay of TBD (450) ns"]
+    #[inline]
+    pub fn cefdly_0(self) -> &'a mut W {
+        self.variant(CEFDLYW::CEFDLY_0)
+    }
+    #[doc = "Typical filter delay of TBD (900) ns"]
+    #[inline]
+    pub fn cefdly_1(self) -> &'a mut W {
+        self.variant(CEFDLYW::CEFDLY_1)
+    }
+    #[doc = "Typical filter delay of TBD (1800) ns"]
+    #[inline]
+    pub fn cefdly_2(self) -> &'a mut W {
+        self.variant(CEFDLYW::CEFDLY_2)
+    }
+    #[doc = "Typical filter delay of TBD (3600) ns"]
+    #[inline]
+    pub fn cefdly_3(self) -> &'a mut W {
+        self.variant(CEFDLYW::CEFDLY_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPWRMD`"]
+pub enum CEPWRMDW {
+    #[doc = "High-speed mode"]
+    CEPWRMD_0,
+    #[doc = "Normal mode"]
+    CEPWRMD_1,
+    #[doc = "Ultra-low power mode"]
+    CEPWRMD_2,
+}
+impl CEPWRMDW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            CEPWRMDW::CEPWRMD_0 => 0,
+            CEPWRMDW::CEPWRMD_1 => 1,
+            CEPWRMDW::CEPWRMD_2 => 2,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPWRMDW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPWRMDW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPWRMDW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "High-speed mode"]
+    #[inline]
+    pub fn cepwrmd_0(self) -> &'a mut W {
+        self.variant(CEPWRMDW::CEPWRMD_0)
+    }
+    #[doc = "Normal mode"]
+    #[inline]
+    pub fn cepwrmd_1(self) -> &'a mut W {
+        self.variant(CEPWRMDW::CEPWRMD_1)
+    }
+    #[doc = "Ultra-low power mode"]
+    #[inline]
+    pub fn cepwrmd_2(self) -> &'a mut W {
+        self.variant(CEPWRMDW::CEPWRMD_2)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEON`"]
+pub enum CEONW {
+    #[doc = "Off"]
+    CEON_0,
+    #[doc = "On"]
+    CEON_1,
+}
+impl CEONW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEONW::CEON_0 => false,
+            CEONW::CEON_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEONW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEONW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEONW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Off"]
+    #[inline]
+    pub fn ceon_0(self) -> &'a mut W {
+        self.variant(CEONW::CEON_0)
+    }
+    #[doc = "On"]
+    #[inline]
+    pub fn ceon_1(self) -> &'a mut W {
+        self.variant(CEONW::CEON_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEMRVL`"]
+pub enum CEMRVLW {
+    #[doc = "VREF0 is selected if CERS = 00, 01, or 10"]
+    CEMRVL_0,
+    #[doc = "VREF1 is selected if CERS = 00, 01, or 10"]
+    CEMRVL_1,
+}
+impl CEMRVLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEMRVLW::CEMRVL_0 => false,
+            CEMRVLW::CEMRVL_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEMRVLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEMRVLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEMRVLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "VREF0 is selected if CERS = 00, 01, or 10"]
+    #[inline]
+    pub fn cemrvl_0(self) -> &'a mut W {
+        self.variant(CEMRVLW::CEMRVL_0)
+    }
+    #[doc = "VREF1 is selected if CERS = 00, 01, or 10"]
+    #[inline]
+    pub fn cemrvl_1(self) -> &'a mut W {
+        self.variant(CEMRVLW::CEMRVL_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEMRVS`"]
+pub enum CEMRVSW {
+    #[doc = "Comparator output state selects between VREF0 or VREF1"]
+    CEMRVS_0,
+    #[doc = "CEMRVL selects between VREF0 or VREF1"]
+    CEMRVS_1,
+}
+impl CEMRVSW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEMRVSW::CEMRVS_0 => false,
+            CEMRVSW::CEMRVS_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEMRVSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEMRVSW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEMRVSW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Comparator output state selects between VREF0 or VREF1"]
+    #[inline]
+    pub fn cemrvs_0(self) -> &'a mut W {
+        self.variant(CEMRVSW::CEMRVS_0)
+    }
+    #[doc = "CEMRVL selects between VREF0 or VREF1"]
+    #[inline]
+    pub fn cemrvs_1(self) -> &'a mut W {
+        self.variant(CEMRVSW::CEMRVS_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Comparator output value"]
+    #[inline]
+    pub fn ceout(&self) -> CEOUTR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        };
+        CEOUTR { bits }
+    }
+    #[doc = "Bit 1 - Comparator output polarity"]
+    #[inline]
+    pub fn ceoutpol(&self) -> CEOUTPOLR {
+        CEOUTPOLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - Comparator output filter"]
+    #[inline]
+    pub fn cef(&self) -> CEFR {
+        CEFR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Interrupt edge select for CEIIFG and CEIFG"]
+    #[inline]
+    pub fn ceies(&self) -> CEIESR {
+        CEIESR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 4 - Input short"]
+    #[inline]
+    pub fn ceshort(&self) -> CESHORTR {
+        CESHORTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - Exchange"]
+    #[inline]
+    pub fn ceex(&self) -> CEEXR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        };
+        CEEXR { bits }
+    }
+    #[doc = "Bits 6:7 - Filter delay"]
+    #[inline]
+    pub fn cefdly(&self) -> CEFDLYR {
+        CEFDLYR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bits 8:9 - Power Mode"]
+    #[inline]
+    pub fn cepwrmd(&self) -> CEPWRMDR {
+        CEPWRMDR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 10 - Comparator On"]
+    #[inline]
+    pub fn ceon(&self) -> CEONR {
+        CEONR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 11 - This bit is valid of CEMRVS is set to 1"]
+    #[inline]
+    pub fn cemrvl(&self) -> CEMRVLR {
+        CEMRVLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 12 - This bit defines if the comparator output selects between VREF0 or VREF1 if CERS = 00, 01, or 10."]
+    #[inline]
+    pub fn cemrvs(&self) -> CEMRVSR {
+        CEMRVSR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Comparator output value"]
+    #[inline]
+    pub fn ceout(&mut self) -> _CEOUTW {
+        _CEOUTW { w: self }
+    }
+    #[doc = "Bit 1 - Comparator output polarity"]
+    #[inline]
+    pub fn ceoutpol(&mut self) -> _CEOUTPOLW {
+        _CEOUTPOLW { w: self }
+    }
+    #[doc = "Bit 2 - Comparator output filter"]
+    #[inline]
+    pub fn cef(&mut self) -> _CEFW {
+        _CEFW { w: self }
+    }
+    #[doc = "Bit 3 - Interrupt edge select for CEIIFG and CEIFG"]
+    #[inline]
+    pub fn ceies(&mut self) -> _CEIESW {
+        _CEIESW { w: self }
+    }
+    #[doc = "Bit 4 - Input short"]
+    #[inline]
+    pub fn ceshort(&mut self) -> _CESHORTW {
+        _CESHORTW { w: self }
+    }
+    #[doc = "Bit 5 - Exchange"]
+    #[inline]
+    pub fn ceex(&mut self) -> _CEEXW {
+        _CEEXW { w: self }
+    }
+    #[doc = "Bits 6:7 - Filter delay"]
+    #[inline]
+    pub fn cefdly(&mut self) -> _CEFDLYW {
+        _CEFDLYW { w: self }
+    }
+    #[doc = "Bits 8:9 - Power Mode"]
+    #[inline]
+    pub fn cepwrmd(&mut self) -> _CEPWRMDW {
+        _CEPWRMDW { w: self }
+    }
+    #[doc = "Bit 10 - Comparator On"]
+    #[inline]
+    pub fn ceon(&mut self) -> _CEONW {
+        _CEONW { w: self }
+    }
+    #[doc = "Bit 11 - This bit is valid of CEMRVS is set to 1"]
+    #[inline]
+    pub fn cemrvl(&mut self) -> _CEMRVLW {
+        _CEMRVLW { w: self }
+    }
+    #[doc = "Bit 12 - This bit defines if the comparator output selects between VREF0 or VREF1 if CERS = 00, 01, or 10."]
+    #[inline]
+    pub fn cemrvs(&mut self) -> _CEMRVSW {
+        _CEMRVSW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/comp_e1/cex_ctl2.rs b/example-source/msp432p401r/src/comp_e1/cex_ctl2.rs
new file mode 100644
index 0000000..44b7f1f
--- /dev/null
+++ b/example-source/msp432p401r/src/comp_e1/cex_ctl2.rs
@@ -0,0 +1,1798 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::CEXCTL2 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `CEREF0`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEREF0R {
+    #[doc = "Reference resistor tap for setting 0."]
+    CEREF0_0,
+    #[doc = "Reference resistor tap for setting 1."]
+    CEREF0_1,
+    #[doc = "Reference resistor tap for setting 2."]
+    CEREF0_2,
+    #[doc = "Reference resistor tap for setting 3."]
+    CEREF0_3,
+    #[doc = "Reference resistor tap for setting 4."]
+    CEREF0_4,
+    #[doc = "Reference resistor tap for setting 5."]
+    CEREF0_5,
+    #[doc = "Reference resistor tap for setting 6."]
+    CEREF0_6,
+    #[doc = "Reference resistor tap for setting 7."]
+    CEREF0_7,
+    #[doc = "Reference resistor tap for setting 8."]
+    CEREF0_8,
+    #[doc = "Reference resistor tap for setting 9."]
+    CEREF0_9,
+    #[doc = "Reference resistor tap for setting 10."]
+    CEREF0_10,
+    #[doc = "Reference resistor tap for setting 11."]
+    CEREF0_11,
+    #[doc = "Reference resistor tap for setting 12."]
+    CEREF0_12,
+    #[doc = "Reference resistor tap for setting 13."]
+    CEREF0_13,
+    #[doc = "Reference resistor tap for setting 14."]
+    CEREF0_14,
+    #[doc = "Reference resistor tap for setting 15."]
+    CEREF0_15,
+    #[doc = "Reference resistor tap for setting 16."]
+    CEREF0_16,
+    #[doc = "Reference resistor tap for setting 17."]
+    CEREF0_17,
+    #[doc = "Reference resistor tap for setting 18."]
+    CEREF0_18,
+    #[doc = "Reference resistor tap for setting 19."]
+    CEREF0_19,
+    #[doc = "Reference resistor tap for setting 20."]
+    CEREF0_20,
+    #[doc = "Reference resistor tap for setting 21."]
+    CEREF0_21,
+    #[doc = "Reference resistor tap for setting 22."]
+    CEREF0_22,
+    #[doc = "Reference resistor tap for setting 23."]
+    CEREF0_23,
+    #[doc = "Reference resistor tap for setting 24."]
+    CEREF0_24,
+    #[doc = "Reference resistor tap for setting 25."]
+    CEREF0_25,
+    #[doc = "Reference resistor tap for setting 26."]
+    CEREF0_26,
+    #[doc = "Reference resistor tap for setting 27."]
+    CEREF0_27,
+    #[doc = "Reference resistor tap for setting 28."]
+    CEREF0_28,
+    #[doc = "Reference resistor tap for setting 29."]
+    CEREF0_29,
+    #[doc = "Reference resistor tap for setting 30."]
+    CEREF0_30,
+    #[doc = "Reference resistor tap for setting 31."]
+    CEREF0_31,
+}
+impl CEREF0R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            CEREF0R::CEREF0_0 => 0,
+            CEREF0R::CEREF0_1 => 1,
+            CEREF0R::CEREF0_2 => 2,
+            CEREF0R::CEREF0_3 => 3,
+            CEREF0R::CEREF0_4 => 4,
+            CEREF0R::CEREF0_5 => 5,
+            CEREF0R::CEREF0_6 => 6,
+            CEREF0R::CEREF0_7 => 7,
+            CEREF0R::CEREF0_8 => 8,
+            CEREF0R::CEREF0_9 => 9,
+            CEREF0R::CEREF0_10 => 10,
+            CEREF0R::CEREF0_11 => 11,
+            CEREF0R::CEREF0_12 => 12,
+            CEREF0R::CEREF0_13 => 13,
+            CEREF0R::CEREF0_14 => 14,
+            CEREF0R::CEREF0_15 => 15,
+            CEREF0R::CEREF0_16 => 16,
+            CEREF0R::CEREF0_17 => 17,
+            CEREF0R::CEREF0_18 => 18,
+            CEREF0R::CEREF0_19 => 19,
+            CEREF0R::CEREF0_20 => 20,
+            CEREF0R::CEREF0_21 => 21,
+            CEREF0R::CEREF0_22 => 22,
+            CEREF0R::CEREF0_23 => 23,
+            CEREF0R::CEREF0_24 => 24,
+            CEREF0R::CEREF0_25 => 25,
+            CEREF0R::CEREF0_26 => 26,
+            CEREF0R::CEREF0_27 => 27,
+            CEREF0R::CEREF0_28 => 28,
+            CEREF0R::CEREF0_29 => 29,
+            CEREF0R::CEREF0_30 => 30,
+            CEREF0R::CEREF0_31 => 31,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> CEREF0R {
+        match value {
+            0 => CEREF0R::CEREF0_0,
+            1 => CEREF0R::CEREF0_1,
+            2 => CEREF0R::CEREF0_2,
+            3 => CEREF0R::CEREF0_3,
+            4 => CEREF0R::CEREF0_4,
+            5 => CEREF0R::CEREF0_5,
+            6 => CEREF0R::CEREF0_6,
+            7 => CEREF0R::CEREF0_7,
+            8 => CEREF0R::CEREF0_8,
+            9 => CEREF0R::CEREF0_9,
+            10 => CEREF0R::CEREF0_10,
+            11 => CEREF0R::CEREF0_11,
+            12 => CEREF0R::CEREF0_12,
+            13 => CEREF0R::CEREF0_13,
+            14 => CEREF0R::CEREF0_14,
+            15 => CEREF0R::CEREF0_15,
+            16 => CEREF0R::CEREF0_16,
+            17 => CEREF0R::CEREF0_17,
+            18 => CEREF0R::CEREF0_18,
+            19 => CEREF0R::CEREF0_19,
+            20 => CEREF0R::CEREF0_20,
+            21 => CEREF0R::CEREF0_21,
+            22 => CEREF0R::CEREF0_22,
+            23 => CEREF0R::CEREF0_23,
+            24 => CEREF0R::CEREF0_24,
+            25 => CEREF0R::CEREF0_25,
+            26 => CEREF0R::CEREF0_26,
+            27 => CEREF0R::CEREF0_27,
+            28 => CEREF0R::CEREF0_28,
+            29 => CEREF0R::CEREF0_29,
+            30 => CEREF0R::CEREF0_30,
+            31 => CEREF0R::CEREF0_31,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_0`"]
+    #[inline]
+    pub fn is_ceref0_0(&self) -> bool {
+        *self == CEREF0R::CEREF0_0
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_1`"]
+    #[inline]
+    pub fn is_ceref0_1(&self) -> bool {
+        *self == CEREF0R::CEREF0_1
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_2`"]
+    #[inline]
+    pub fn is_ceref0_2(&self) -> bool {
+        *self == CEREF0R::CEREF0_2
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_3`"]
+    #[inline]
+    pub fn is_ceref0_3(&self) -> bool {
+        *self == CEREF0R::CEREF0_3
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_4`"]
+    #[inline]
+    pub fn is_ceref0_4(&self) -> bool {
+        *self == CEREF0R::CEREF0_4
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_5`"]
+    #[inline]
+    pub fn is_ceref0_5(&self) -> bool {
+        *self == CEREF0R::CEREF0_5
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_6`"]
+    #[inline]
+    pub fn is_ceref0_6(&self) -> bool {
+        *self == CEREF0R::CEREF0_6
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_7`"]
+    #[inline]
+    pub fn is_ceref0_7(&self) -> bool {
+        *self == CEREF0R::CEREF0_7
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_8`"]
+    #[inline]
+    pub fn is_ceref0_8(&self) -> bool {
+        *self == CEREF0R::CEREF0_8
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_9`"]
+    #[inline]
+    pub fn is_ceref0_9(&self) -> bool {
+        *self == CEREF0R::CEREF0_9
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_10`"]
+    #[inline]
+    pub fn is_ceref0_10(&self) -> bool {
+        *self == CEREF0R::CEREF0_10
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_11`"]
+    #[inline]
+    pub fn is_ceref0_11(&self) -> bool {
+        *self == CEREF0R::CEREF0_11
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_12`"]
+    #[inline]
+    pub fn is_ceref0_12(&self) -> bool {
+        *self == CEREF0R::CEREF0_12
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_13`"]
+    #[inline]
+    pub fn is_ceref0_13(&self) -> bool {
+        *self == CEREF0R::CEREF0_13
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_14`"]
+    #[inline]
+    pub fn is_ceref0_14(&self) -> bool {
+        *self == CEREF0R::CEREF0_14
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_15`"]
+    #[inline]
+    pub fn is_ceref0_15(&self) -> bool {
+        *self == CEREF0R::CEREF0_15
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_16`"]
+    #[inline]
+    pub fn is_ceref0_16(&self) -> bool {
+        *self == CEREF0R::CEREF0_16
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_17`"]
+    #[inline]
+    pub fn is_ceref0_17(&self) -> bool {
+        *self == CEREF0R::CEREF0_17
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_18`"]
+    #[inline]
+    pub fn is_ceref0_18(&self) -> bool {
+        *self == CEREF0R::CEREF0_18
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_19`"]
+    #[inline]
+    pub fn is_ceref0_19(&self) -> bool {
+        *self == CEREF0R::CEREF0_19
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_20`"]
+    #[inline]
+    pub fn is_ceref0_20(&self) -> bool {
+        *self == CEREF0R::CEREF0_20
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_21`"]
+    #[inline]
+    pub fn is_ceref0_21(&self) -> bool {
+        *self == CEREF0R::CEREF0_21
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_22`"]
+    #[inline]
+    pub fn is_ceref0_22(&self) -> bool {
+        *self == CEREF0R::CEREF0_22
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_23`"]
+    #[inline]
+    pub fn is_ceref0_23(&self) -> bool {
+        *self == CEREF0R::CEREF0_23
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_24`"]
+    #[inline]
+    pub fn is_ceref0_24(&self) -> bool {
+        *self == CEREF0R::CEREF0_24
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_25`"]
+    #[inline]
+    pub fn is_ceref0_25(&self) -> bool {
+        *self == CEREF0R::CEREF0_25
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_26`"]
+    #[inline]
+    pub fn is_ceref0_26(&self) -> bool {
+        *self == CEREF0R::CEREF0_26
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_27`"]
+    #[inline]
+    pub fn is_ceref0_27(&self) -> bool {
+        *self == CEREF0R::CEREF0_27
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_28`"]
+    #[inline]
+    pub fn is_ceref0_28(&self) -> bool {
+        *self == CEREF0R::CEREF0_28
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_29`"]
+    #[inline]
+    pub fn is_ceref0_29(&self) -> bool {
+        *self == CEREF0R::CEREF0_29
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_30`"]
+    #[inline]
+    pub fn is_ceref0_30(&self) -> bool {
+        *self == CEREF0R::CEREF0_30
+    }
+    #[doc = "Checks if the value of the field is `CEREF0_31`"]
+    #[inline]
+    pub fn is_ceref0_31(&self) -> bool {
+        *self == CEREF0R::CEREF0_31
+    }
+}
+#[doc = "Possible values of the field `CERSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CERSELR {
+    #[doc = "When CEEX = 0, VREF is applied to the V+ terminal; When CEEX = 1, VREF is applied to the V- terminal"]
+    CERSEL_0,
+    #[doc = "When CEEX = 0, VREF is applied to the V- terminal; When CEEX = 1, VREF is applied to the V+ terminal"]
+    CERSEL_1,
+}
+impl CERSELR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CERSELR::CERSEL_0 => false,
+            CERSELR::CERSEL_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CERSELR {
+        match value {
+            false => CERSELR::CERSEL_0,
+            true => CERSELR::CERSEL_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CERSEL_0`"]
+    #[inline]
+    pub fn is_cersel_0(&self) -> bool {
+        *self == CERSELR::CERSEL_0
+    }
+    #[doc = "Checks if the value of the field is `CERSEL_1`"]
+    #[inline]
+    pub fn is_cersel_1(&self) -> bool {
+        *self == CERSELR::CERSEL_1
+    }
+}
+#[doc = "Possible values of the field `CERS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CERSR {
+    #[doc = "No current is drawn by the reference circuitry"]
+    CERS_0,
+    #[doc = "VCC applied to the resistor ladder"]
+    CERS_1,
+    #[doc = "Shared reference voltage applied to the resistor ladder"]
+    CERS_2,
+    #[doc = "Shared reference voltage supplied to V(CREF). Resistor ladder is off"]
+    CERS_3,
+}
+impl CERSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            CERSR::CERS_0 => 0,
+            CERSR::CERS_1 => 1,
+            CERSR::CERS_2 => 2,
+            CERSR::CERS_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> CERSR {
+        match value {
+            0 => CERSR::CERS_0,
+            1 => CERSR::CERS_1,
+            2 => CERSR::CERS_2,
+            3 => CERSR::CERS_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `CERS_0`"]
+    #[inline]
+    pub fn is_cers_0(&self) -> bool {
+        *self == CERSR::CERS_0
+    }
+    #[doc = "Checks if the value of the field is `CERS_1`"]
+    #[inline]
+    pub fn is_cers_1(&self) -> bool {
+        *self == CERSR::CERS_1
+    }
+    #[doc = "Checks if the value of the field is `CERS_2`"]
+    #[inline]
+    pub fn is_cers_2(&self) -> bool {
+        *self == CERSR::CERS_2
+    }
+    #[doc = "Checks if the value of the field is `CERS_3`"]
+    #[inline]
+    pub fn is_cers_3(&self) -> bool {
+        *self == CERSR::CERS_3
+    }
+}
+#[doc = "Possible values of the field `CEREF1`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEREF1R {
+    #[doc = "Reference resistor tap for setting 0."]
+    CEREF1_0,
+    #[doc = "Reference resistor tap for setting 1."]
+    CEREF1_1,
+    #[doc = "Reference resistor tap for setting 2."]
+    CEREF1_2,
+    #[doc = "Reference resistor tap for setting 3."]
+    CEREF1_3,
+    #[doc = "Reference resistor tap for setting 4."]
+    CEREF1_4,
+    #[doc = "Reference resistor tap for setting 5."]
+    CEREF1_5,
+    #[doc = "Reference resistor tap for setting 6."]
+    CEREF1_6,
+    #[doc = "Reference resistor tap for setting 7."]
+    CEREF1_7,
+    #[doc = "Reference resistor tap for setting 8."]
+    CEREF1_8,
+    #[doc = "Reference resistor tap for setting 9."]
+    CEREF1_9,
+    #[doc = "Reference resistor tap for setting 10."]
+    CEREF1_10,
+    #[doc = "Reference resistor tap for setting 11."]
+    CEREF1_11,
+    #[doc = "Reference resistor tap for setting 12."]
+    CEREF1_12,
+    #[doc = "Reference resistor tap for setting 13."]
+    CEREF1_13,
+    #[doc = "Reference resistor tap for setting 14."]
+    CEREF1_14,
+    #[doc = "Reference resistor tap for setting 15."]
+    CEREF1_15,
+    #[doc = "Reference resistor tap for setting 16."]
+    CEREF1_16,
+    #[doc = "Reference resistor tap for setting 17."]
+    CEREF1_17,
+    #[doc = "Reference resistor tap for setting 18."]
+    CEREF1_18,
+    #[doc = "Reference resistor tap for setting 19."]
+    CEREF1_19,
+    #[doc = "Reference resistor tap for setting 20."]
+    CEREF1_20,
+    #[doc = "Reference resistor tap for setting 21."]
+    CEREF1_21,
+    #[doc = "Reference resistor tap for setting 22."]
+    CEREF1_22,
+    #[doc = "Reference resistor tap for setting 23."]
+    CEREF1_23,
+    #[doc = "Reference resistor tap for setting 24."]
+    CEREF1_24,
+    #[doc = "Reference resistor tap for setting 25."]
+    CEREF1_25,
+    #[doc = "Reference resistor tap for setting 26."]
+    CEREF1_26,
+    #[doc = "Reference resistor tap for setting 27."]
+    CEREF1_27,
+    #[doc = "Reference resistor tap for setting 28."]
+    CEREF1_28,
+    #[doc = "Reference resistor tap for setting 29."]
+    CEREF1_29,
+    #[doc = "Reference resistor tap for setting 30."]
+    CEREF1_30,
+    #[doc = "Reference resistor tap for setting 31."]
+    CEREF1_31,
+}
+impl CEREF1R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            CEREF1R::CEREF1_0 => 0,
+            CEREF1R::CEREF1_1 => 1,
+            CEREF1R::CEREF1_2 => 2,
+            CEREF1R::CEREF1_3 => 3,
+            CEREF1R::CEREF1_4 => 4,
+            CEREF1R::CEREF1_5 => 5,
+            CEREF1R::CEREF1_6 => 6,
+            CEREF1R::CEREF1_7 => 7,
+            CEREF1R::CEREF1_8 => 8,
+            CEREF1R::CEREF1_9 => 9,
+            CEREF1R::CEREF1_10 => 10,
+            CEREF1R::CEREF1_11 => 11,
+            CEREF1R::CEREF1_12 => 12,
+            CEREF1R::CEREF1_13 => 13,
+            CEREF1R::CEREF1_14 => 14,
+            CEREF1R::CEREF1_15 => 15,
+            CEREF1R::CEREF1_16 => 16,
+            CEREF1R::CEREF1_17 => 17,
+            CEREF1R::CEREF1_18 => 18,
+            CEREF1R::CEREF1_19 => 19,
+            CEREF1R::CEREF1_20 => 20,
+            CEREF1R::CEREF1_21 => 21,
+            CEREF1R::CEREF1_22 => 22,
+            CEREF1R::CEREF1_23 => 23,
+            CEREF1R::CEREF1_24 => 24,
+            CEREF1R::CEREF1_25 => 25,
+            CEREF1R::CEREF1_26 => 26,
+            CEREF1R::CEREF1_27 => 27,
+            CEREF1R::CEREF1_28 => 28,
+            CEREF1R::CEREF1_29 => 29,
+            CEREF1R::CEREF1_30 => 30,
+            CEREF1R::CEREF1_31 => 31,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> CEREF1R {
+        match value {
+            0 => CEREF1R::CEREF1_0,
+            1 => CEREF1R::CEREF1_1,
+            2 => CEREF1R::CEREF1_2,
+            3 => CEREF1R::CEREF1_3,
+            4 => CEREF1R::CEREF1_4,
+            5 => CEREF1R::CEREF1_5,
+            6 => CEREF1R::CEREF1_6,
+            7 => CEREF1R::CEREF1_7,
+            8 => CEREF1R::CEREF1_8,
+            9 => CEREF1R::CEREF1_9,
+            10 => CEREF1R::CEREF1_10,
+            11 => CEREF1R::CEREF1_11,
+            12 => CEREF1R::CEREF1_12,
+            13 => CEREF1R::CEREF1_13,
+            14 => CEREF1R::CEREF1_14,
+            15 => CEREF1R::CEREF1_15,
+            16 => CEREF1R::CEREF1_16,
+            17 => CEREF1R::CEREF1_17,
+            18 => CEREF1R::CEREF1_18,
+            19 => CEREF1R::CEREF1_19,
+            20 => CEREF1R::CEREF1_20,
+            21 => CEREF1R::CEREF1_21,
+            22 => CEREF1R::CEREF1_22,
+            23 => CEREF1R::CEREF1_23,
+            24 => CEREF1R::CEREF1_24,
+            25 => CEREF1R::CEREF1_25,
+            26 => CEREF1R::CEREF1_26,
+            27 => CEREF1R::CEREF1_27,
+            28 => CEREF1R::CEREF1_28,
+            29 => CEREF1R::CEREF1_29,
+            30 => CEREF1R::CEREF1_30,
+            31 => CEREF1R::CEREF1_31,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_0`"]
+    #[inline]
+    pub fn is_ceref1_0(&self) -> bool {
+        *self == CEREF1R::CEREF1_0
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_1`"]
+    #[inline]
+    pub fn is_ceref1_1(&self) -> bool {
+        *self == CEREF1R::CEREF1_1
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_2`"]
+    #[inline]
+    pub fn is_ceref1_2(&self) -> bool {
+        *self == CEREF1R::CEREF1_2
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_3`"]
+    #[inline]
+    pub fn is_ceref1_3(&self) -> bool {
+        *self == CEREF1R::CEREF1_3
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_4`"]
+    #[inline]
+    pub fn is_ceref1_4(&self) -> bool {
+        *self == CEREF1R::CEREF1_4
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_5`"]
+    #[inline]
+    pub fn is_ceref1_5(&self) -> bool {
+        *self == CEREF1R::CEREF1_5
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_6`"]
+    #[inline]
+    pub fn is_ceref1_6(&self) -> bool {
+        *self == CEREF1R::CEREF1_6
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_7`"]
+    #[inline]
+    pub fn is_ceref1_7(&self) -> bool {
+        *self == CEREF1R::CEREF1_7
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_8`"]
+    #[inline]
+    pub fn is_ceref1_8(&self) -> bool {
+        *self == CEREF1R::CEREF1_8
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_9`"]
+    #[inline]
+    pub fn is_ceref1_9(&self) -> bool {
+        *self == CEREF1R::CEREF1_9
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_10`"]
+    #[inline]
+    pub fn is_ceref1_10(&self) -> bool {
+        *self == CEREF1R::CEREF1_10
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_11`"]
+    #[inline]
+    pub fn is_ceref1_11(&self) -> bool {
+        *self == CEREF1R::CEREF1_11
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_12`"]
+    #[inline]
+    pub fn is_ceref1_12(&self) -> bool {
+        *self == CEREF1R::CEREF1_12
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_13`"]
+    #[inline]
+    pub fn is_ceref1_13(&self) -> bool {
+        *self == CEREF1R::CEREF1_13
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_14`"]
+    #[inline]
+    pub fn is_ceref1_14(&self) -> bool {
+        *self == CEREF1R::CEREF1_14
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_15`"]
+    #[inline]
+    pub fn is_ceref1_15(&self) -> bool {
+        *self == CEREF1R::CEREF1_15
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_16`"]
+    #[inline]
+    pub fn is_ceref1_16(&self) -> bool {
+        *self == CEREF1R::CEREF1_16
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_17`"]
+    #[inline]
+    pub fn is_ceref1_17(&self) -> bool {
+        *self == CEREF1R::CEREF1_17
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_18`"]
+    #[inline]
+    pub fn is_ceref1_18(&self) -> bool {
+        *self == CEREF1R::CEREF1_18
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_19`"]
+    #[inline]
+    pub fn is_ceref1_19(&self) -> bool {
+        *self == CEREF1R::CEREF1_19
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_20`"]
+    #[inline]
+    pub fn is_ceref1_20(&self) -> bool {
+        *self == CEREF1R::CEREF1_20
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_21`"]
+    #[inline]
+    pub fn is_ceref1_21(&self) -> bool {
+        *self == CEREF1R::CEREF1_21
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_22`"]
+    #[inline]
+    pub fn is_ceref1_22(&self) -> bool {
+        *self == CEREF1R::CEREF1_22
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_23`"]
+    #[inline]
+    pub fn is_ceref1_23(&self) -> bool {
+        *self == CEREF1R::CEREF1_23
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_24`"]
+    #[inline]
+    pub fn is_ceref1_24(&self) -> bool {
+        *self == CEREF1R::CEREF1_24
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_25`"]
+    #[inline]
+    pub fn is_ceref1_25(&self) -> bool {
+        *self == CEREF1R::CEREF1_25
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_26`"]
+    #[inline]
+    pub fn is_ceref1_26(&self) -> bool {
+        *self == CEREF1R::CEREF1_26
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_27`"]
+    #[inline]
+    pub fn is_ceref1_27(&self) -> bool {
+        *self == CEREF1R::CEREF1_27
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_28`"]
+    #[inline]
+    pub fn is_ceref1_28(&self) -> bool {
+        *self == CEREF1R::CEREF1_28
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_29`"]
+    #[inline]
+    pub fn is_ceref1_29(&self) -> bool {
+        *self == CEREF1R::CEREF1_29
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_30`"]
+    #[inline]
+    pub fn is_ceref1_30(&self) -> bool {
+        *self == CEREF1R::CEREF1_30
+    }
+    #[doc = "Checks if the value of the field is `CEREF1_31`"]
+    #[inline]
+    pub fn is_ceref1_31(&self) -> bool {
+        *self == CEREF1R::CEREF1_31
+    }
+}
+#[doc = "Possible values of the field `CEREFL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEREFLR {
+    #[doc = "Reference amplifier is disabled. No reference voltage is requested"]
+    CEREFL_0,
+    #[doc = "1.2 V is selected as shared reference voltage input"]
+    CEREFL_1,
+    #[doc = "2.0 V is selected as shared reference voltage input"]
+    CEREFL_2,
+    #[doc = "2.5 V is selected as shared reference voltage input"]
+    CEREFL_3,
+}
+impl CEREFLR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            CEREFLR::CEREFL_0 => 0,
+            CEREFLR::CEREFL_1 => 1,
+            CEREFLR::CEREFL_2 => 2,
+            CEREFLR::CEREFL_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> CEREFLR {
+        match value {
+            0 => CEREFLR::CEREFL_0,
+            1 => CEREFLR::CEREFL_1,
+            2 => CEREFLR::CEREFL_2,
+            3 => CEREFLR::CEREFL_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEREFL_0`"]
+    #[inline]
+    pub fn is_cerefl_0(&self) -> bool {
+        *self == CEREFLR::CEREFL_0
+    }
+    #[doc = "Checks if the value of the field is `CEREFL_1`"]
+    #[inline]
+    pub fn is_cerefl_1(&self) -> bool {
+        *self == CEREFLR::CEREFL_1
+    }
+    #[doc = "Checks if the value of the field is `CEREFL_2`"]
+    #[inline]
+    pub fn is_cerefl_2(&self) -> bool {
+        *self == CEREFLR::CEREFL_2
+    }
+    #[doc = "Checks if the value of the field is `CEREFL_3`"]
+    #[inline]
+    pub fn is_cerefl_3(&self) -> bool {
+        *self == CEREFLR::CEREFL_3
+    }
+}
+#[doc = "Possible values of the field `CEREFACC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEREFACCR {
+    #[doc = "Static mode"]
+    CEREFACC_0,
+    #[doc = "Clocked (low power, low accuracy) mode"]
+    CEREFACC_1,
+}
+impl CEREFACCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEREFACCR::CEREFACC_0 => false,
+            CEREFACCR::CEREFACC_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEREFACCR {
+        match value {
+            false => CEREFACCR::CEREFACC_0,
+            true => CEREFACCR::CEREFACC_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEREFACC_0`"]
+    #[inline]
+    pub fn is_cerefacc_0(&self) -> bool {
+        *self == CEREFACCR::CEREFACC_0
+    }
+    #[doc = "Checks if the value of the field is `CEREFACC_1`"]
+    #[inline]
+    pub fn is_cerefacc_1(&self) -> bool {
+        *self == CEREFACCR::CEREFACC_1
+    }
+}
+#[doc = "Values that can be written to the field `CEREF0`"]
+pub enum CEREF0W {
+    #[doc = "Reference resistor tap for setting 0."]
+    CEREF0_0,
+    #[doc = "Reference resistor tap for setting 1."]
+    CEREF0_1,
+    #[doc = "Reference resistor tap for setting 2."]
+    CEREF0_2,
+    #[doc = "Reference resistor tap for setting 3."]
+    CEREF0_3,
+    #[doc = "Reference resistor tap for setting 4."]
+    CEREF0_4,
+    #[doc = "Reference resistor tap for setting 5."]
+    CEREF0_5,
+    #[doc = "Reference resistor tap for setting 6."]
+    CEREF0_6,
+    #[doc = "Reference resistor tap for setting 7."]
+    CEREF0_7,
+    #[doc = "Reference resistor tap for setting 8."]
+    CEREF0_8,
+    #[doc = "Reference resistor tap for setting 9."]
+    CEREF0_9,
+    #[doc = "Reference resistor tap for setting 10."]
+    CEREF0_10,
+    #[doc = "Reference resistor tap for setting 11."]
+    CEREF0_11,
+    #[doc = "Reference resistor tap for setting 12."]
+    CEREF0_12,
+    #[doc = "Reference resistor tap for setting 13."]
+    CEREF0_13,
+    #[doc = "Reference resistor tap for setting 14."]
+    CEREF0_14,
+    #[doc = "Reference resistor tap for setting 15."]
+    CEREF0_15,
+    #[doc = "Reference resistor tap for setting 16."]
+    CEREF0_16,
+    #[doc = "Reference resistor tap for setting 17."]
+    CEREF0_17,
+    #[doc = "Reference resistor tap for setting 18."]
+    CEREF0_18,
+    #[doc = "Reference resistor tap for setting 19."]
+    CEREF0_19,
+    #[doc = "Reference resistor tap for setting 20."]
+    CEREF0_20,
+    #[doc = "Reference resistor tap for setting 21."]
+    CEREF0_21,
+    #[doc = "Reference resistor tap for setting 22."]
+    CEREF0_22,
+    #[doc = "Reference resistor tap for setting 23."]
+    CEREF0_23,
+    #[doc = "Reference resistor tap for setting 24."]
+    CEREF0_24,
+    #[doc = "Reference resistor tap for setting 25."]
+    CEREF0_25,
+    #[doc = "Reference resistor tap for setting 26."]
+    CEREF0_26,
+    #[doc = "Reference resistor tap for setting 27."]
+    CEREF0_27,
+    #[doc = "Reference resistor tap for setting 28."]
+    CEREF0_28,
+    #[doc = "Reference resistor tap for setting 29."]
+    CEREF0_29,
+    #[doc = "Reference resistor tap for setting 30."]
+    CEREF0_30,
+    #[doc = "Reference resistor tap for setting 31."]
+    CEREF0_31,
+}
+impl CEREF0W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            CEREF0W::CEREF0_0 => 0,
+            CEREF0W::CEREF0_1 => 1,
+            CEREF0W::CEREF0_2 => 2,
+            CEREF0W::CEREF0_3 => 3,
+            CEREF0W::CEREF0_4 => 4,
+            CEREF0W::CEREF0_5 => 5,
+            CEREF0W::CEREF0_6 => 6,
+            CEREF0W::CEREF0_7 => 7,
+            CEREF0W::CEREF0_8 => 8,
+            CEREF0W::CEREF0_9 => 9,
+            CEREF0W::CEREF0_10 => 10,
+            CEREF0W::CEREF0_11 => 11,
+            CEREF0W::CEREF0_12 => 12,
+            CEREF0W::CEREF0_13 => 13,
+            CEREF0W::CEREF0_14 => 14,
+            CEREF0W::CEREF0_15 => 15,
+            CEREF0W::CEREF0_16 => 16,
+            CEREF0W::CEREF0_17 => 17,
+            CEREF0W::CEREF0_18 => 18,
+            CEREF0W::CEREF0_19 => 19,
+            CEREF0W::CEREF0_20 => 20,
+            CEREF0W::CEREF0_21 => 21,
+            CEREF0W::CEREF0_22 => 22,
+            CEREF0W::CEREF0_23 => 23,
+            CEREF0W::CEREF0_24 => 24,
+            CEREF0W::CEREF0_25 => 25,
+            CEREF0W::CEREF0_26 => 26,
+            CEREF0W::CEREF0_27 => 27,
+            CEREF0W::CEREF0_28 => 28,
+            CEREF0W::CEREF0_29 => 29,
+            CEREF0W::CEREF0_30 => 30,
+            CEREF0W::CEREF0_31 => 31,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEREF0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEREF0W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEREF0W) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Reference resistor tap for setting 0."]
+    #[inline]
+    pub fn ceref0_0(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_0)
+    }
+    #[doc = "Reference resistor tap for setting 1."]
+    #[inline]
+    pub fn ceref0_1(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_1)
+    }
+    #[doc = "Reference resistor tap for setting 2."]
+    #[inline]
+    pub fn ceref0_2(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_2)
+    }
+    #[doc = "Reference resistor tap for setting 3."]
+    #[inline]
+    pub fn ceref0_3(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_3)
+    }
+    #[doc = "Reference resistor tap for setting 4."]
+    #[inline]
+    pub fn ceref0_4(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_4)
+    }
+    #[doc = "Reference resistor tap for setting 5."]
+    #[inline]
+    pub fn ceref0_5(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_5)
+    }
+    #[doc = "Reference resistor tap for setting 6."]
+    #[inline]
+    pub fn ceref0_6(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_6)
+    }
+    #[doc = "Reference resistor tap for setting 7."]
+    #[inline]
+    pub fn ceref0_7(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_7)
+    }
+    #[doc = "Reference resistor tap for setting 8."]
+    #[inline]
+    pub fn ceref0_8(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_8)
+    }
+    #[doc = "Reference resistor tap for setting 9."]
+    #[inline]
+    pub fn ceref0_9(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_9)
+    }
+    #[doc = "Reference resistor tap for setting 10."]
+    #[inline]
+    pub fn ceref0_10(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_10)
+    }
+    #[doc = "Reference resistor tap for setting 11."]
+    #[inline]
+    pub fn ceref0_11(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_11)
+    }
+    #[doc = "Reference resistor tap for setting 12."]
+    #[inline]
+    pub fn ceref0_12(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_12)
+    }
+    #[doc = "Reference resistor tap for setting 13."]
+    #[inline]
+    pub fn ceref0_13(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_13)
+    }
+    #[doc = "Reference resistor tap for setting 14."]
+    #[inline]
+    pub fn ceref0_14(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_14)
+    }
+    #[doc = "Reference resistor tap for setting 15."]
+    #[inline]
+    pub fn ceref0_15(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_15)
+    }
+    #[doc = "Reference resistor tap for setting 16."]
+    #[inline]
+    pub fn ceref0_16(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_16)
+    }
+    #[doc = "Reference resistor tap for setting 17."]
+    #[inline]
+    pub fn ceref0_17(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_17)
+    }
+    #[doc = "Reference resistor tap for setting 18."]
+    #[inline]
+    pub fn ceref0_18(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_18)
+    }
+    #[doc = "Reference resistor tap for setting 19."]
+    #[inline]
+    pub fn ceref0_19(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_19)
+    }
+    #[doc = "Reference resistor tap for setting 20."]
+    #[inline]
+    pub fn ceref0_20(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_20)
+    }
+    #[doc = "Reference resistor tap for setting 21."]
+    #[inline]
+    pub fn ceref0_21(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_21)
+    }
+    #[doc = "Reference resistor tap for setting 22."]
+    #[inline]
+    pub fn ceref0_22(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_22)
+    }
+    #[doc = "Reference resistor tap for setting 23."]
+    #[inline]
+    pub fn ceref0_23(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_23)
+    }
+    #[doc = "Reference resistor tap for setting 24."]
+    #[inline]
+    pub fn ceref0_24(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_24)
+    }
+    #[doc = "Reference resistor tap for setting 25."]
+    #[inline]
+    pub fn ceref0_25(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_25)
+    }
+    #[doc = "Reference resistor tap for setting 26."]
+    #[inline]
+    pub fn ceref0_26(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_26)
+    }
+    #[doc = "Reference resistor tap for setting 27."]
+    #[inline]
+    pub fn ceref0_27(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_27)
+    }
+    #[doc = "Reference resistor tap for setting 28."]
+    #[inline]
+    pub fn ceref0_28(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_28)
+    }
+    #[doc = "Reference resistor tap for setting 29."]
+    #[inline]
+    pub fn ceref0_29(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_29)
+    }
+    #[doc = "Reference resistor tap for setting 30."]
+    #[inline]
+    pub fn ceref0_30(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_30)
+    }
+    #[doc = "Reference resistor tap for setting 31."]
+    #[inline]
+    pub fn ceref0_31(self) -> &'a mut W {
+        self.variant(CEREF0W::CEREF0_31)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 31;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CERSEL`"]
+pub enum CERSELW {
+    #[doc = "When CEEX = 0, VREF is applied to the V+ terminal; When CEEX = 1, VREF is applied to the V- terminal"]
+    CERSEL_0,
+    #[doc = "When CEEX = 0, VREF is applied to the V- terminal; When CEEX = 1, VREF is applied to the V+ terminal"]
+    CERSEL_1,
+}
+impl CERSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CERSELW::CERSEL_0 => false,
+            CERSELW::CERSEL_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CERSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CERSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CERSELW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "When CEEX = 0, VREF is applied to the V+ terminal; When CEEX = 1, VREF is applied to the V- terminal"]
+    #[inline]
+    pub fn cersel_0(self) -> &'a mut W {
+        self.variant(CERSELW::CERSEL_0)
+    }
+    #[doc = "When CEEX = 0, VREF is applied to the V- terminal; When CEEX = 1, VREF is applied to the V+ terminal"]
+    #[inline]
+    pub fn cersel_1(self) -> &'a mut W {
+        self.variant(CERSELW::CERSEL_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CERS`"]
+pub enum CERSW {
+    #[doc = "No current is drawn by the reference circuitry"]
+    CERS_0,
+    #[doc = "VCC applied to the resistor ladder"]
+    CERS_1,
+    #[doc = "Shared reference voltage applied to the resistor ladder"]
+    CERS_2,
+    #[doc = "Shared reference voltage supplied to V(CREF). Resistor ladder is off"]
+    CERS_3,
+}
+impl CERSW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            CERSW::CERS_0 => 0,
+            CERSW::CERS_1 => 1,
+            CERSW::CERS_2 => 2,
+            CERSW::CERS_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CERSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CERSW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CERSW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "No current is drawn by the reference circuitry"]
+    #[inline]
+    pub fn cers_0(self) -> &'a mut W {
+        self.variant(CERSW::CERS_0)
+    }
+    #[doc = "VCC applied to the resistor ladder"]
+    #[inline]
+    pub fn cers_1(self) -> &'a mut W {
+        self.variant(CERSW::CERS_1)
+    }
+    #[doc = "Shared reference voltage applied to the resistor ladder"]
+    #[inline]
+    pub fn cers_2(self) -> &'a mut W {
+        self.variant(CERSW::CERS_2)
+    }
+    #[doc = "Shared reference voltage supplied to V(CREF). Resistor ladder is off"]
+    #[inline]
+    pub fn cers_3(self) -> &'a mut W {
+        self.variant(CERSW::CERS_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEREF1`"]
+pub enum CEREF1W {
+    #[doc = "Reference resistor tap for setting 0."]
+    CEREF1_0,
+    #[doc = "Reference resistor tap for setting 1."]
+    CEREF1_1,
+    #[doc = "Reference resistor tap for setting 2."]
+    CEREF1_2,
+    #[doc = "Reference resistor tap for setting 3."]
+    CEREF1_3,
+    #[doc = "Reference resistor tap for setting 4."]
+    CEREF1_4,
+    #[doc = "Reference resistor tap for setting 5."]
+    CEREF1_5,
+    #[doc = "Reference resistor tap for setting 6."]
+    CEREF1_6,
+    #[doc = "Reference resistor tap for setting 7."]
+    CEREF1_7,
+    #[doc = "Reference resistor tap for setting 8."]
+    CEREF1_8,
+    #[doc = "Reference resistor tap for setting 9."]
+    CEREF1_9,
+    #[doc = "Reference resistor tap for setting 10."]
+    CEREF1_10,
+    #[doc = "Reference resistor tap for setting 11."]
+    CEREF1_11,
+    #[doc = "Reference resistor tap for setting 12."]
+    CEREF1_12,
+    #[doc = "Reference resistor tap for setting 13."]
+    CEREF1_13,
+    #[doc = "Reference resistor tap for setting 14."]
+    CEREF1_14,
+    #[doc = "Reference resistor tap for setting 15."]
+    CEREF1_15,
+    #[doc = "Reference resistor tap for setting 16."]
+    CEREF1_16,
+    #[doc = "Reference resistor tap for setting 17."]
+    CEREF1_17,
+    #[doc = "Reference resistor tap for setting 18."]
+    CEREF1_18,
+    #[doc = "Reference resistor tap for setting 19."]
+    CEREF1_19,
+    #[doc = "Reference resistor tap for setting 20."]
+    CEREF1_20,
+    #[doc = "Reference resistor tap for setting 21."]
+    CEREF1_21,
+    #[doc = "Reference resistor tap for setting 22."]
+    CEREF1_22,
+    #[doc = "Reference resistor tap for setting 23."]
+    CEREF1_23,
+    #[doc = "Reference resistor tap for setting 24."]
+    CEREF1_24,
+    #[doc = "Reference resistor tap for setting 25."]
+    CEREF1_25,
+    #[doc = "Reference resistor tap for setting 26."]
+    CEREF1_26,
+    #[doc = "Reference resistor tap for setting 27."]
+    CEREF1_27,
+    #[doc = "Reference resistor tap for setting 28."]
+    CEREF1_28,
+    #[doc = "Reference resistor tap for setting 29."]
+    CEREF1_29,
+    #[doc = "Reference resistor tap for setting 30."]
+    CEREF1_30,
+    #[doc = "Reference resistor tap for setting 31."]
+    CEREF1_31,
+}
+impl CEREF1W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            CEREF1W::CEREF1_0 => 0,
+            CEREF1W::CEREF1_1 => 1,
+            CEREF1W::CEREF1_2 => 2,
+            CEREF1W::CEREF1_3 => 3,
+            CEREF1W::CEREF1_4 => 4,
+            CEREF1W::CEREF1_5 => 5,
+            CEREF1W::CEREF1_6 => 6,
+            CEREF1W::CEREF1_7 => 7,
+            CEREF1W::CEREF1_8 => 8,
+            CEREF1W::CEREF1_9 => 9,
+            CEREF1W::CEREF1_10 => 10,
+            CEREF1W::CEREF1_11 => 11,
+            CEREF1W::CEREF1_12 => 12,
+            CEREF1W::CEREF1_13 => 13,
+            CEREF1W::CEREF1_14 => 14,
+            CEREF1W::CEREF1_15 => 15,
+            CEREF1W::CEREF1_16 => 16,
+            CEREF1W::CEREF1_17 => 17,
+            CEREF1W::CEREF1_18 => 18,
+            CEREF1W::CEREF1_19 => 19,
+            CEREF1W::CEREF1_20 => 20,
+            CEREF1W::CEREF1_21 => 21,
+            CEREF1W::CEREF1_22 => 22,
+            CEREF1W::CEREF1_23 => 23,
+            CEREF1W::CEREF1_24 => 24,
+            CEREF1W::CEREF1_25 => 25,
+            CEREF1W::CEREF1_26 => 26,
+            CEREF1W::CEREF1_27 => 27,
+            CEREF1W::CEREF1_28 => 28,
+            CEREF1W::CEREF1_29 => 29,
+            CEREF1W::CEREF1_30 => 30,
+            CEREF1W::CEREF1_31 => 31,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEREF1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEREF1W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEREF1W) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Reference resistor tap for setting 0."]
+    #[inline]
+    pub fn ceref1_0(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_0)
+    }
+    #[doc = "Reference resistor tap for setting 1."]
+    #[inline]
+    pub fn ceref1_1(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_1)
+    }
+    #[doc = "Reference resistor tap for setting 2."]
+    #[inline]
+    pub fn ceref1_2(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_2)
+    }
+    #[doc = "Reference resistor tap for setting 3."]
+    #[inline]
+    pub fn ceref1_3(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_3)
+    }
+    #[doc = "Reference resistor tap for setting 4."]
+    #[inline]
+    pub fn ceref1_4(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_4)
+    }
+    #[doc = "Reference resistor tap for setting 5."]
+    #[inline]
+    pub fn ceref1_5(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_5)
+    }
+    #[doc = "Reference resistor tap for setting 6."]
+    #[inline]
+    pub fn ceref1_6(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_6)
+    }
+    #[doc = "Reference resistor tap for setting 7."]
+    #[inline]
+    pub fn ceref1_7(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_7)
+    }
+    #[doc = "Reference resistor tap for setting 8."]
+    #[inline]
+    pub fn ceref1_8(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_8)
+    }
+    #[doc = "Reference resistor tap for setting 9."]
+    #[inline]
+    pub fn ceref1_9(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_9)
+    }
+    #[doc = "Reference resistor tap for setting 10."]
+    #[inline]
+    pub fn ceref1_10(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_10)
+    }
+    #[doc = "Reference resistor tap for setting 11."]
+    #[inline]
+    pub fn ceref1_11(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_11)
+    }
+    #[doc = "Reference resistor tap for setting 12."]
+    #[inline]
+    pub fn ceref1_12(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_12)
+    }
+    #[doc = "Reference resistor tap for setting 13."]
+    #[inline]
+    pub fn ceref1_13(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_13)
+    }
+    #[doc = "Reference resistor tap for setting 14."]
+    #[inline]
+    pub fn ceref1_14(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_14)
+    }
+    #[doc = "Reference resistor tap for setting 15."]
+    #[inline]
+    pub fn ceref1_15(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_15)
+    }
+    #[doc = "Reference resistor tap for setting 16."]
+    #[inline]
+    pub fn ceref1_16(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_16)
+    }
+    #[doc = "Reference resistor tap for setting 17."]
+    #[inline]
+    pub fn ceref1_17(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_17)
+    }
+    #[doc = "Reference resistor tap for setting 18."]
+    #[inline]
+    pub fn ceref1_18(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_18)
+    }
+    #[doc = "Reference resistor tap for setting 19."]
+    #[inline]
+    pub fn ceref1_19(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_19)
+    }
+    #[doc = "Reference resistor tap for setting 20."]
+    #[inline]
+    pub fn ceref1_20(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_20)
+    }
+    #[doc = "Reference resistor tap for setting 21."]
+    #[inline]
+    pub fn ceref1_21(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_21)
+    }
+    #[doc = "Reference resistor tap for setting 22."]
+    #[inline]
+    pub fn ceref1_22(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_22)
+    }
+    #[doc = "Reference resistor tap for setting 23."]
+    #[inline]
+    pub fn ceref1_23(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_23)
+    }
+    #[doc = "Reference resistor tap for setting 24."]
+    #[inline]
+    pub fn ceref1_24(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_24)
+    }
+    #[doc = "Reference resistor tap for setting 25."]
+    #[inline]
+    pub fn ceref1_25(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_25)
+    }
+    #[doc = "Reference resistor tap for setting 26."]
+    #[inline]
+    pub fn ceref1_26(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_26)
+    }
+    #[doc = "Reference resistor tap for setting 27."]
+    #[inline]
+    pub fn ceref1_27(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_27)
+    }
+    #[doc = "Reference resistor tap for setting 28."]
+    #[inline]
+    pub fn ceref1_28(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_28)
+    }
+    #[doc = "Reference resistor tap for setting 29."]
+    #[inline]
+    pub fn ceref1_29(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_29)
+    }
+    #[doc = "Reference resistor tap for setting 30."]
+    #[inline]
+    pub fn ceref1_30(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_30)
+    }
+    #[doc = "Reference resistor tap for setting 31."]
+    #[inline]
+    pub fn ceref1_31(self) -> &'a mut W {
+        self.variant(CEREF1W::CEREF1_31)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 31;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEREFL`"]
+pub enum CEREFLW {
+    #[doc = "Reference amplifier is disabled. No reference voltage is requested"]
+    CEREFL_0,
+    #[doc = "1.2 V is selected as shared reference voltage input"]
+    CEREFL_1,
+    #[doc = "2.0 V is selected as shared reference voltage input"]
+    CEREFL_2,
+    #[doc = "2.5 V is selected as shared reference voltage input"]
+    CEREFL_3,
+}
+impl CEREFLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            CEREFLW::CEREFL_0 => 0,
+            CEREFLW::CEREFL_1 => 1,
+            CEREFLW::CEREFL_2 => 2,
+            CEREFLW::CEREFL_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEREFLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEREFLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEREFLW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Reference amplifier is disabled. No reference voltage is requested"]
+    #[inline]
+    pub fn cerefl_0(self) -> &'a mut W {
+        self.variant(CEREFLW::CEREFL_0)
+    }
+    #[doc = "1.2 V is selected as shared reference voltage input"]
+    #[inline]
+    pub fn cerefl_1(self) -> &'a mut W {
+        self.variant(CEREFLW::CEREFL_1)
+    }
+    #[doc = "2.0 V is selected as shared reference voltage input"]
+    #[inline]
+    pub fn cerefl_2(self) -> &'a mut W {
+        self.variant(CEREFLW::CEREFL_2)
+    }
+    #[doc = "2.5 V is selected as shared reference voltage input"]
+    #[inline]
+    pub fn cerefl_3(self) -> &'a mut W {
+        self.variant(CEREFLW::CEREFL_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEREFACC`"]
+pub enum CEREFACCW {
+    #[doc = "Static mode"]
+    CEREFACC_0,
+    #[doc = "Clocked (low power, low accuracy) mode"]
+    CEREFACC_1,
+}
+impl CEREFACCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEREFACCW::CEREFACC_0 => false,
+            CEREFACCW::CEREFACC_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEREFACCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEREFACCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEREFACCW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Static mode"]
+    #[inline]
+    pub fn cerefacc_0(self) -> &'a mut W {
+        self.variant(CEREFACCW::CEREFACC_0)
+    }
+    #[doc = "Clocked (low power, low accuracy) mode"]
+    #[inline]
+    pub fn cerefacc_1(self) -> &'a mut W {
+        self.variant(CEREFACCW::CEREFACC_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:4 - Reference resistor tap 0"]
+    #[inline]
+    pub fn ceref0(&self) -> CEREF0R {
+        CEREF0R::_from({
+            const MASK: u8 = 31;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 5 - Reference select"]
+    #[inline]
+    pub fn cersel(&self) -> CERSELR {
+        CERSELR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 6:7 - Reference source"]
+    #[inline]
+    pub fn cers(&self) -> CERSR {
+        CERSR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bits 8:12 - Reference resistor tap 1"]
+    #[inline]
+    pub fn ceref1(&self) -> CEREF1R {
+        CEREF1R::_from({
+            const MASK: u8 = 31;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bits 13:14 - Reference voltage level"]
+    #[inline]
+    pub fn cerefl(&self) -> CEREFLR {
+        CEREFLR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 15 - Reference accuracy"]
+    #[inline]
+    pub fn cerefacc(&self) -> CEREFACCR {
+        CEREFACCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:4 - Reference resistor tap 0"]
+    #[inline]
+    pub fn ceref0(&mut self) -> _CEREF0W {
+        _CEREF0W { w: self }
+    }
+    #[doc = "Bit 5 - Reference select"]
+    #[inline]
+    pub fn cersel(&mut self) -> _CERSELW {
+        _CERSELW { w: self }
+    }
+    #[doc = "Bits 6:7 - Reference source"]
+    #[inline]
+    pub fn cers(&mut self) -> _CERSW {
+        _CERSW { w: self }
+    }
+    #[doc = "Bits 8:12 - Reference resistor tap 1"]
+    #[inline]
+    pub fn ceref1(&mut self) -> _CEREF1W {
+        _CEREF1W { w: self }
+    }
+    #[doc = "Bits 13:14 - Reference voltage level"]
+    #[inline]
+    pub fn cerefl(&mut self) -> _CEREFLW {
+        _CEREFLW { w: self }
+    }
+    #[doc = "Bit 15 - Reference accuracy"]
+    #[inline]
+    pub fn cerefacc(&mut self) -> _CEREFACCW {
+        _CEREFACCW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/comp_e1/cex_ctl3.rs b/example-source/msp432p401r/src/comp_e1/cex_ctl3.rs
new file mode 100644
index 0000000..fb1efc5
--- /dev/null
+++ b/example-source/msp432p401r/src/comp_e1/cex_ctl3.rs
@@ -0,0 +1,1968 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::CEXCTL3 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `CEPD0`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD0R {
+    #[doc = "The input buffer is enabled"]
+    CEPD0_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD0_1,
+}
+impl CEPD0R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD0R::CEPD0_0 => false,
+            CEPD0R::CEPD0_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD0R {
+        match value {
+            false => CEPD0R::CEPD0_0,
+            true => CEPD0R::CEPD0_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD0_0`"]
+    #[inline]
+    pub fn is_cepd0_0(&self) -> bool {
+        *self == CEPD0R::CEPD0_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD0_1`"]
+    #[inline]
+    pub fn is_cepd0_1(&self) -> bool {
+        *self == CEPD0R::CEPD0_1
+    }
+}
+#[doc = "Possible values of the field `CEPD1`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD1R {
+    #[doc = "The input buffer is enabled"]
+    CEPD1_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD1_1,
+}
+impl CEPD1R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD1R::CEPD1_0 => false,
+            CEPD1R::CEPD1_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD1R {
+        match value {
+            false => CEPD1R::CEPD1_0,
+            true => CEPD1R::CEPD1_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD1_0`"]
+    #[inline]
+    pub fn is_cepd1_0(&self) -> bool {
+        *self == CEPD1R::CEPD1_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD1_1`"]
+    #[inline]
+    pub fn is_cepd1_1(&self) -> bool {
+        *self == CEPD1R::CEPD1_1
+    }
+}
+#[doc = "Possible values of the field `CEPD2`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD2R {
+    #[doc = "The input buffer is enabled"]
+    CEPD2_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD2_1,
+}
+impl CEPD2R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD2R::CEPD2_0 => false,
+            CEPD2R::CEPD2_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD2R {
+        match value {
+            false => CEPD2R::CEPD2_0,
+            true => CEPD2R::CEPD2_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD2_0`"]
+    #[inline]
+    pub fn is_cepd2_0(&self) -> bool {
+        *self == CEPD2R::CEPD2_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD2_1`"]
+    #[inline]
+    pub fn is_cepd2_1(&self) -> bool {
+        *self == CEPD2R::CEPD2_1
+    }
+}
+#[doc = "Possible values of the field `CEPD3`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD3R {
+    #[doc = "The input buffer is enabled"]
+    CEPD3_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD3_1,
+}
+impl CEPD3R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD3R::CEPD3_0 => false,
+            CEPD3R::CEPD3_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD3R {
+        match value {
+            false => CEPD3R::CEPD3_0,
+            true => CEPD3R::CEPD3_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD3_0`"]
+    #[inline]
+    pub fn is_cepd3_0(&self) -> bool {
+        *self == CEPD3R::CEPD3_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD3_1`"]
+    #[inline]
+    pub fn is_cepd3_1(&self) -> bool {
+        *self == CEPD3R::CEPD3_1
+    }
+}
+#[doc = "Possible values of the field `CEPD4`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD4R {
+    #[doc = "The input buffer is enabled"]
+    CEPD4_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD4_1,
+}
+impl CEPD4R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD4R::CEPD4_0 => false,
+            CEPD4R::CEPD4_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD4R {
+        match value {
+            false => CEPD4R::CEPD4_0,
+            true => CEPD4R::CEPD4_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD4_0`"]
+    #[inline]
+    pub fn is_cepd4_0(&self) -> bool {
+        *self == CEPD4R::CEPD4_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD4_1`"]
+    #[inline]
+    pub fn is_cepd4_1(&self) -> bool {
+        *self == CEPD4R::CEPD4_1
+    }
+}
+#[doc = "Possible values of the field `CEPD5`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD5R {
+    #[doc = "The input buffer is enabled"]
+    CEPD5_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD5_1,
+}
+impl CEPD5R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD5R::CEPD5_0 => false,
+            CEPD5R::CEPD5_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD5R {
+        match value {
+            false => CEPD5R::CEPD5_0,
+            true => CEPD5R::CEPD5_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD5_0`"]
+    #[inline]
+    pub fn is_cepd5_0(&self) -> bool {
+        *self == CEPD5R::CEPD5_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD5_1`"]
+    #[inline]
+    pub fn is_cepd5_1(&self) -> bool {
+        *self == CEPD5R::CEPD5_1
+    }
+}
+#[doc = "Possible values of the field `CEPD6`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD6R {
+    #[doc = "The input buffer is enabled"]
+    CEPD6_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD6_1,
+}
+impl CEPD6R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD6R::CEPD6_0 => false,
+            CEPD6R::CEPD6_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD6R {
+        match value {
+            false => CEPD6R::CEPD6_0,
+            true => CEPD6R::CEPD6_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD6_0`"]
+    #[inline]
+    pub fn is_cepd6_0(&self) -> bool {
+        *self == CEPD6R::CEPD6_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD6_1`"]
+    #[inline]
+    pub fn is_cepd6_1(&self) -> bool {
+        *self == CEPD6R::CEPD6_1
+    }
+}
+#[doc = "Possible values of the field `CEPD7`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD7R {
+    #[doc = "The input buffer is enabled"]
+    CEPD7_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD7_1,
+}
+impl CEPD7R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD7R::CEPD7_0 => false,
+            CEPD7R::CEPD7_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD7R {
+        match value {
+            false => CEPD7R::CEPD7_0,
+            true => CEPD7R::CEPD7_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD7_0`"]
+    #[inline]
+    pub fn is_cepd7_0(&self) -> bool {
+        *self == CEPD7R::CEPD7_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD7_1`"]
+    #[inline]
+    pub fn is_cepd7_1(&self) -> bool {
+        *self == CEPD7R::CEPD7_1
+    }
+}
+#[doc = "Possible values of the field `CEPD8`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD8R {
+    #[doc = "The input buffer is enabled"]
+    CEPD8_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD8_1,
+}
+impl CEPD8R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD8R::CEPD8_0 => false,
+            CEPD8R::CEPD8_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD8R {
+        match value {
+            false => CEPD8R::CEPD8_0,
+            true => CEPD8R::CEPD8_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD8_0`"]
+    #[inline]
+    pub fn is_cepd8_0(&self) -> bool {
+        *self == CEPD8R::CEPD8_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD8_1`"]
+    #[inline]
+    pub fn is_cepd8_1(&self) -> bool {
+        *self == CEPD8R::CEPD8_1
+    }
+}
+#[doc = "Possible values of the field `CEPD9`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD9R {
+    #[doc = "The input buffer is enabled"]
+    CEPD9_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD9_1,
+}
+impl CEPD9R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD9R::CEPD9_0 => false,
+            CEPD9R::CEPD9_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD9R {
+        match value {
+            false => CEPD9R::CEPD9_0,
+            true => CEPD9R::CEPD9_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD9_0`"]
+    #[inline]
+    pub fn is_cepd9_0(&self) -> bool {
+        *self == CEPD9R::CEPD9_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD9_1`"]
+    #[inline]
+    pub fn is_cepd9_1(&self) -> bool {
+        *self == CEPD9R::CEPD9_1
+    }
+}
+#[doc = "Possible values of the field `CEPD10`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD10R {
+    #[doc = "The input buffer is enabled"]
+    CEPD10_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD10_1,
+}
+impl CEPD10R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD10R::CEPD10_0 => false,
+            CEPD10R::CEPD10_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD10R {
+        match value {
+            false => CEPD10R::CEPD10_0,
+            true => CEPD10R::CEPD10_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD10_0`"]
+    #[inline]
+    pub fn is_cepd10_0(&self) -> bool {
+        *self == CEPD10R::CEPD10_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD10_1`"]
+    #[inline]
+    pub fn is_cepd10_1(&self) -> bool {
+        *self == CEPD10R::CEPD10_1
+    }
+}
+#[doc = "Possible values of the field `CEPD11`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD11R {
+    #[doc = "The input buffer is enabled"]
+    CEPD11_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD11_1,
+}
+impl CEPD11R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD11R::CEPD11_0 => false,
+            CEPD11R::CEPD11_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD11R {
+        match value {
+            false => CEPD11R::CEPD11_0,
+            true => CEPD11R::CEPD11_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD11_0`"]
+    #[inline]
+    pub fn is_cepd11_0(&self) -> bool {
+        *self == CEPD11R::CEPD11_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD11_1`"]
+    #[inline]
+    pub fn is_cepd11_1(&self) -> bool {
+        *self == CEPD11R::CEPD11_1
+    }
+}
+#[doc = "Possible values of the field `CEPD12`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD12R {
+    #[doc = "The input buffer is enabled"]
+    CEPD12_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD12_1,
+}
+impl CEPD12R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD12R::CEPD12_0 => false,
+            CEPD12R::CEPD12_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD12R {
+        match value {
+            false => CEPD12R::CEPD12_0,
+            true => CEPD12R::CEPD12_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD12_0`"]
+    #[inline]
+    pub fn is_cepd12_0(&self) -> bool {
+        *self == CEPD12R::CEPD12_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD12_1`"]
+    #[inline]
+    pub fn is_cepd12_1(&self) -> bool {
+        *self == CEPD12R::CEPD12_1
+    }
+}
+#[doc = "Possible values of the field `CEPD13`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD13R {
+    #[doc = "The input buffer is enabled"]
+    CEPD13_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD13_1,
+}
+impl CEPD13R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD13R::CEPD13_0 => false,
+            CEPD13R::CEPD13_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD13R {
+        match value {
+            false => CEPD13R::CEPD13_0,
+            true => CEPD13R::CEPD13_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD13_0`"]
+    #[inline]
+    pub fn is_cepd13_0(&self) -> bool {
+        *self == CEPD13R::CEPD13_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD13_1`"]
+    #[inline]
+    pub fn is_cepd13_1(&self) -> bool {
+        *self == CEPD13R::CEPD13_1
+    }
+}
+#[doc = "Possible values of the field `CEPD14`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD14R {
+    #[doc = "The input buffer is enabled"]
+    CEPD14_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD14_1,
+}
+impl CEPD14R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD14R::CEPD14_0 => false,
+            CEPD14R::CEPD14_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD14R {
+        match value {
+            false => CEPD14R::CEPD14_0,
+            true => CEPD14R::CEPD14_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD14_0`"]
+    #[inline]
+    pub fn is_cepd14_0(&self) -> bool {
+        *self == CEPD14R::CEPD14_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD14_1`"]
+    #[inline]
+    pub fn is_cepd14_1(&self) -> bool {
+        *self == CEPD14R::CEPD14_1
+    }
+}
+#[doc = "Possible values of the field `CEPD15`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEPD15R {
+    #[doc = "The input buffer is enabled"]
+    CEPD15_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD15_1,
+}
+impl CEPD15R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEPD15R::CEPD15_0 => false,
+            CEPD15R::CEPD15_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEPD15R {
+        match value {
+            false => CEPD15R::CEPD15_0,
+            true => CEPD15R::CEPD15_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEPD15_0`"]
+    #[inline]
+    pub fn is_cepd15_0(&self) -> bool {
+        *self == CEPD15R::CEPD15_0
+    }
+    #[doc = "Checks if the value of the field is `CEPD15_1`"]
+    #[inline]
+    pub fn is_cepd15_1(&self) -> bool {
+        *self == CEPD15R::CEPD15_1
+    }
+}
+#[doc = "Values that can be written to the field `CEPD0`"]
+pub enum CEPD0W {
+    #[doc = "The input buffer is enabled"]
+    CEPD0_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD0_1,
+}
+impl CEPD0W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD0W::CEPD0_0 => false,
+            CEPD0W::CEPD0_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD0W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD0W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd0_0(self) -> &'a mut W {
+        self.variant(CEPD0W::CEPD0_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd0_1(self) -> &'a mut W {
+        self.variant(CEPD0W::CEPD0_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPD1`"]
+pub enum CEPD1W {
+    #[doc = "The input buffer is enabled"]
+    CEPD1_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD1_1,
+}
+impl CEPD1W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD1W::CEPD1_0 => false,
+            CEPD1W::CEPD1_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD1W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD1W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd1_0(self) -> &'a mut W {
+        self.variant(CEPD1W::CEPD1_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd1_1(self) -> &'a mut W {
+        self.variant(CEPD1W::CEPD1_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPD2`"]
+pub enum CEPD2W {
+    #[doc = "The input buffer is enabled"]
+    CEPD2_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD2_1,
+}
+impl CEPD2W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD2W::CEPD2_0 => false,
+            CEPD2W::CEPD2_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD2W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD2W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd2_0(self) -> &'a mut W {
+        self.variant(CEPD2W::CEPD2_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd2_1(self) -> &'a mut W {
+        self.variant(CEPD2W::CEPD2_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPD3`"]
+pub enum CEPD3W {
+    #[doc = "The input buffer is enabled"]
+    CEPD3_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD3_1,
+}
+impl CEPD3W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD3W::CEPD3_0 => false,
+            CEPD3W::CEPD3_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD3W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD3W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd3_0(self) -> &'a mut W {
+        self.variant(CEPD3W::CEPD3_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd3_1(self) -> &'a mut W {
+        self.variant(CEPD3W::CEPD3_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPD4`"]
+pub enum CEPD4W {
+    #[doc = "The input buffer is enabled"]
+    CEPD4_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD4_1,
+}
+impl CEPD4W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD4W::CEPD4_0 => false,
+            CEPD4W::CEPD4_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD4W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD4W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD4W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd4_0(self) -> &'a mut W {
+        self.variant(CEPD4W::CEPD4_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd4_1(self) -> &'a mut W {
+        self.variant(CEPD4W::CEPD4_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPD5`"]
+pub enum CEPD5W {
+    #[doc = "The input buffer is enabled"]
+    CEPD5_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD5_1,
+}
+impl CEPD5W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD5W::CEPD5_0 => false,
+            CEPD5W::CEPD5_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD5W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD5W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD5W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd5_0(self) -> &'a mut W {
+        self.variant(CEPD5W::CEPD5_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd5_1(self) -> &'a mut W {
+        self.variant(CEPD5W::CEPD5_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPD6`"]
+pub enum CEPD6W {
+    #[doc = "The input buffer is enabled"]
+    CEPD6_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD6_1,
+}
+impl CEPD6W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD6W::CEPD6_0 => false,
+            CEPD6W::CEPD6_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD6W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD6W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD6W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd6_0(self) -> &'a mut W {
+        self.variant(CEPD6W::CEPD6_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd6_1(self) -> &'a mut W {
+        self.variant(CEPD6W::CEPD6_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPD7`"]
+pub enum CEPD7W {
+    #[doc = "The input buffer is enabled"]
+    CEPD7_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD7_1,
+}
+impl CEPD7W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD7W::CEPD7_0 => false,
+            CEPD7W::CEPD7_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD7W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD7W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD7W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd7_0(self) -> &'a mut W {
+        self.variant(CEPD7W::CEPD7_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd7_1(self) -> &'a mut W {
+        self.variant(CEPD7W::CEPD7_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPD8`"]
+pub enum CEPD8W {
+    #[doc = "The input buffer is enabled"]
+    CEPD8_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD8_1,
+}
+impl CEPD8W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD8W::CEPD8_0 => false,
+            CEPD8W::CEPD8_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD8W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD8W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD8W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd8_0(self) -> &'a mut W {
+        self.variant(CEPD8W::CEPD8_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd8_1(self) -> &'a mut W {
+        self.variant(CEPD8W::CEPD8_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPD9`"]
+pub enum CEPD9W {
+    #[doc = "The input buffer is enabled"]
+    CEPD9_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD9_1,
+}
+impl CEPD9W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD9W::CEPD9_0 => false,
+            CEPD9W::CEPD9_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD9W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD9W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD9W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd9_0(self) -> &'a mut W {
+        self.variant(CEPD9W::CEPD9_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd9_1(self) -> &'a mut W {
+        self.variant(CEPD9W::CEPD9_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPD10`"]
+pub enum CEPD10W {
+    #[doc = "The input buffer is enabled"]
+    CEPD10_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD10_1,
+}
+impl CEPD10W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD10W::CEPD10_0 => false,
+            CEPD10W::CEPD10_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD10W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD10W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD10W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd10_0(self) -> &'a mut W {
+        self.variant(CEPD10W::CEPD10_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd10_1(self) -> &'a mut W {
+        self.variant(CEPD10W::CEPD10_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPD11`"]
+pub enum CEPD11W {
+    #[doc = "The input buffer is enabled"]
+    CEPD11_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD11_1,
+}
+impl CEPD11W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD11W::CEPD11_0 => false,
+            CEPD11W::CEPD11_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD11W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD11W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD11W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd11_0(self) -> &'a mut W {
+        self.variant(CEPD11W::CEPD11_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd11_1(self) -> &'a mut W {
+        self.variant(CEPD11W::CEPD11_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPD12`"]
+pub enum CEPD12W {
+    #[doc = "The input buffer is enabled"]
+    CEPD12_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD12_1,
+}
+impl CEPD12W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD12W::CEPD12_0 => false,
+            CEPD12W::CEPD12_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD12W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD12W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD12W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd12_0(self) -> &'a mut W {
+        self.variant(CEPD12W::CEPD12_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd12_1(self) -> &'a mut W {
+        self.variant(CEPD12W::CEPD12_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPD13`"]
+pub enum CEPD13W {
+    #[doc = "The input buffer is enabled"]
+    CEPD13_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD13_1,
+}
+impl CEPD13W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD13W::CEPD13_0 => false,
+            CEPD13W::CEPD13_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD13W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD13W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD13W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd13_0(self) -> &'a mut W {
+        self.variant(CEPD13W::CEPD13_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd13_1(self) -> &'a mut W {
+        self.variant(CEPD13W::CEPD13_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPD14`"]
+pub enum CEPD14W {
+    #[doc = "The input buffer is enabled"]
+    CEPD14_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD14_1,
+}
+impl CEPD14W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD14W::CEPD14_0 => false,
+            CEPD14W::CEPD14_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD14W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD14W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD14W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd14_0(self) -> &'a mut W {
+        self.variant(CEPD14W::CEPD14_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd14_1(self) -> &'a mut W {
+        self.variant(CEPD14W::CEPD14_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEPD15`"]
+pub enum CEPD15W {
+    #[doc = "The input buffer is enabled"]
+    CEPD15_0,
+    #[doc = "The input buffer is disabled"]
+    CEPD15_1,
+}
+impl CEPD15W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEPD15W::CEPD15_0 => false,
+            CEPD15W::CEPD15_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEPD15W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEPD15W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEPD15W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The input buffer is enabled"]
+    #[inline]
+    pub fn cepd15_0(self) -> &'a mut W {
+        self.variant(CEPD15W::CEPD15_0)
+    }
+    #[doc = "The input buffer is disabled"]
+    #[inline]
+    pub fn cepd15_1(self) -> &'a mut W {
+        self.variant(CEPD15W::CEPD15_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Port disable"]
+    #[inline]
+    pub fn cepd0(&self) -> CEPD0R {
+        CEPD0R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Port disable"]
+    #[inline]
+    pub fn cepd1(&self) -> CEPD1R {
+        CEPD1R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - Port disable"]
+    #[inline]
+    pub fn cepd2(&self) -> CEPD2R {
+        CEPD2R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Port disable"]
+    #[inline]
+    pub fn cepd3(&self) -> CEPD3R {
+        CEPD3R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 4 - Port disable"]
+    #[inline]
+    pub fn cepd4(&self) -> CEPD4R {
+        CEPD4R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - Port disable"]
+    #[inline]
+    pub fn cepd5(&self) -> CEPD5R {
+        CEPD5R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 6 - Port disable"]
+    #[inline]
+    pub fn cepd6(&self) -> CEPD6R {
+        CEPD6R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 7 - Port disable"]
+    #[inline]
+    pub fn cepd7(&self) -> CEPD7R {
+        CEPD7R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 8 - Port disable"]
+    #[inline]
+    pub fn cepd8(&self) -> CEPD8R {
+        CEPD8R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 9 - Port disable"]
+    #[inline]
+    pub fn cepd9(&self) -> CEPD9R {
+        CEPD9R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 10 - Port disable"]
+    #[inline]
+    pub fn cepd10(&self) -> CEPD10R {
+        CEPD10R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 11 - Port disable"]
+    #[inline]
+    pub fn cepd11(&self) -> CEPD11R {
+        CEPD11R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 12 - Port disable"]
+    #[inline]
+    pub fn cepd12(&self) -> CEPD12R {
+        CEPD12R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 13 - Port disable"]
+    #[inline]
+    pub fn cepd13(&self) -> CEPD13R {
+        CEPD13R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 14 - Port disable"]
+    #[inline]
+    pub fn cepd14(&self) -> CEPD14R {
+        CEPD14R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 15 - Port disable"]
+    #[inline]
+    pub fn cepd15(&self) -> CEPD15R {
+        CEPD15R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Port disable"]
+    #[inline]
+    pub fn cepd0(&mut self) -> _CEPD0W {
+        _CEPD0W { w: self }
+    }
+    #[doc = "Bit 1 - Port disable"]
+    #[inline]
+    pub fn cepd1(&mut self) -> _CEPD1W {
+        _CEPD1W { w: self }
+    }
+    #[doc = "Bit 2 - Port disable"]
+    #[inline]
+    pub fn cepd2(&mut self) -> _CEPD2W {
+        _CEPD2W { w: self }
+    }
+    #[doc = "Bit 3 - Port disable"]
+    #[inline]
+    pub fn cepd3(&mut self) -> _CEPD3W {
+        _CEPD3W { w: self }
+    }
+    #[doc = "Bit 4 - Port disable"]
+    #[inline]
+    pub fn cepd4(&mut self) -> _CEPD4W {
+        _CEPD4W { w: self }
+    }
+    #[doc = "Bit 5 - Port disable"]
+    #[inline]
+    pub fn cepd5(&mut self) -> _CEPD5W {
+        _CEPD5W { w: self }
+    }
+    #[doc = "Bit 6 - Port disable"]
+    #[inline]
+    pub fn cepd6(&mut self) -> _CEPD6W {
+        _CEPD6W { w: self }
+    }
+    #[doc = "Bit 7 - Port disable"]
+    #[inline]
+    pub fn cepd7(&mut self) -> _CEPD7W {
+        _CEPD7W { w: self }
+    }
+    #[doc = "Bit 8 - Port disable"]
+    #[inline]
+    pub fn cepd8(&mut self) -> _CEPD8W {
+        _CEPD8W { w: self }
+    }
+    #[doc = "Bit 9 - Port disable"]
+    #[inline]
+    pub fn cepd9(&mut self) -> _CEPD9W {
+        _CEPD9W { w: self }
+    }
+    #[doc = "Bit 10 - Port disable"]
+    #[inline]
+    pub fn cepd10(&mut self) -> _CEPD10W {
+        _CEPD10W { w: self }
+    }
+    #[doc = "Bit 11 - Port disable"]
+    #[inline]
+    pub fn cepd11(&mut self) -> _CEPD11W {
+        _CEPD11W { w: self }
+    }
+    #[doc = "Bit 12 - Port disable"]
+    #[inline]
+    pub fn cepd12(&mut self) -> _CEPD12W {
+        _CEPD12W { w: self }
+    }
+    #[doc = "Bit 13 - Port disable"]
+    #[inline]
+    pub fn cepd13(&mut self) -> _CEPD13W {
+        _CEPD13W { w: self }
+    }
+    #[doc = "Bit 14 - Port disable"]
+    #[inline]
+    pub fn cepd14(&mut self) -> _CEPD14W {
+        _CEPD14W { w: self }
+    }
+    #[doc = "Bit 15 - Port disable"]
+    #[inline]
+    pub fn cepd15(&mut self) -> _CEPD15W {
+        _CEPD15W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/comp_e1/cex_int.rs b/example-source/msp432p401r/src/comp_e1/cex_int.rs
new file mode 100644
index 0000000..04e3d31
--- /dev/null
+++ b/example-source/msp432p401r/src/comp_e1/cex_int.rs
@@ -0,0 +1,778 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::CEXINT {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `CEIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEIFGR {
+    #[doc = "No interrupt pending"]
+    CEIFG_0,
+    #[doc = "Interrupt pending"]
+    CEIFG_1,
+}
+impl CEIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEIFGR::CEIFG_0 => false,
+            CEIFGR::CEIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEIFGR {
+        match value {
+            false => CEIFGR::CEIFG_0,
+            true => CEIFGR::CEIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEIFG_0`"]
+    #[inline]
+    pub fn is_ceifg_0(&self) -> bool {
+        *self == CEIFGR::CEIFG_0
+    }
+    #[doc = "Checks if the value of the field is `CEIFG_1`"]
+    #[inline]
+    pub fn is_ceifg_1(&self) -> bool {
+        *self == CEIFGR::CEIFG_1
+    }
+}
+#[doc = "Possible values of the field `CEIIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEIIFGR {
+    #[doc = "No interrupt pending"]
+    CEIIFG_0,
+    #[doc = "Interrupt pending"]
+    CEIIFG_1,
+}
+impl CEIIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEIIFGR::CEIIFG_0 => false,
+            CEIIFGR::CEIIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEIIFGR {
+        match value {
+            false => CEIIFGR::CEIIFG_0,
+            true => CEIIFGR::CEIIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEIIFG_0`"]
+    #[inline]
+    pub fn is_ceiifg_0(&self) -> bool {
+        *self == CEIIFGR::CEIIFG_0
+    }
+    #[doc = "Checks if the value of the field is `CEIIFG_1`"]
+    #[inline]
+    pub fn is_ceiifg_1(&self) -> bool {
+        *self == CEIIFGR::CEIIFG_1
+    }
+}
+#[doc = "Possible values of the field `CERDYIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CERDYIFGR {
+    #[doc = "No interrupt pending"]
+    CERDYIFG_0,
+    #[doc = "Interrupt pending"]
+    CERDYIFG_1,
+}
+impl CERDYIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CERDYIFGR::CERDYIFG_0 => false,
+            CERDYIFGR::CERDYIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CERDYIFGR {
+        match value {
+            false => CERDYIFGR::CERDYIFG_0,
+            true => CERDYIFGR::CERDYIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CERDYIFG_0`"]
+    #[inline]
+    pub fn is_cerdyifg_0(&self) -> bool {
+        *self == CERDYIFGR::CERDYIFG_0
+    }
+    #[doc = "Checks if the value of the field is `CERDYIFG_1`"]
+    #[inline]
+    pub fn is_cerdyifg_1(&self) -> bool {
+        *self == CERDYIFGR::CERDYIFG_1
+    }
+}
+#[doc = "Possible values of the field `CEIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEIER {
+    #[doc = "Interrupt disabled"]
+    CEIE_0,
+    #[doc = "Interrupt enabled"]
+    CEIE_1,
+}
+impl CEIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEIER::CEIE_0 => false,
+            CEIER::CEIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEIER {
+        match value {
+            false => CEIER::CEIE_0,
+            true => CEIER::CEIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEIE_0`"]
+    #[inline]
+    pub fn is_ceie_0(&self) -> bool {
+        *self == CEIER::CEIE_0
+    }
+    #[doc = "Checks if the value of the field is `CEIE_1`"]
+    #[inline]
+    pub fn is_ceie_1(&self) -> bool {
+        *self == CEIER::CEIE_1
+    }
+}
+#[doc = "Possible values of the field `CEIIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEIIER {
+    #[doc = "Interrupt disabled"]
+    CEIIE_0,
+    #[doc = "Interrupt enabled"]
+    CEIIE_1,
+}
+impl CEIIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CEIIER::CEIIE_0 => false,
+            CEIIER::CEIIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CEIIER {
+        match value {
+            false => CEIIER::CEIIE_0,
+            true => CEIIER::CEIIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEIIE_0`"]
+    #[inline]
+    pub fn is_ceiie_0(&self) -> bool {
+        *self == CEIIER::CEIIE_0
+    }
+    #[doc = "Checks if the value of the field is `CEIIE_1`"]
+    #[inline]
+    pub fn is_ceiie_1(&self) -> bool {
+        *self == CEIIER::CEIIE_1
+    }
+}
+#[doc = "Possible values of the field `CERDYIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CERDYIER {
+    #[doc = "Interrupt disabled"]
+    CERDYIE_0,
+    #[doc = "Interrupt enabled"]
+    CERDYIE_1,
+}
+impl CERDYIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CERDYIER::CERDYIE_0 => false,
+            CERDYIER::CERDYIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CERDYIER {
+        match value {
+            false => CERDYIER::CERDYIE_0,
+            true => CERDYIER::CERDYIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CERDYIE_0`"]
+    #[inline]
+    pub fn is_cerdyie_0(&self) -> bool {
+        *self == CERDYIER::CERDYIE_0
+    }
+    #[doc = "Checks if the value of the field is `CERDYIE_1`"]
+    #[inline]
+    pub fn is_cerdyie_1(&self) -> bool {
+        *self == CERDYIER::CERDYIE_1
+    }
+}
+#[doc = "Values that can be written to the field `CEIFG`"]
+pub enum CEIFGW {
+    #[doc = "No interrupt pending"]
+    CEIFG_0,
+    #[doc = "Interrupt pending"]
+    CEIFG_1,
+}
+impl CEIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEIFGW::CEIFG_0 => false,
+            CEIFGW::CEIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ceifg_0(self) -> &'a mut W {
+        self.variant(CEIFGW::CEIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ceifg_1(self) -> &'a mut W {
+        self.variant(CEIFGW::CEIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEIIFG`"]
+pub enum CEIIFGW {
+    #[doc = "No interrupt pending"]
+    CEIIFG_0,
+    #[doc = "Interrupt pending"]
+    CEIIFG_1,
+}
+impl CEIIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEIIFGW::CEIIFG_0 => false,
+            CEIIFGW::CEIIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEIIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEIIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEIIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ceiifg_0(self) -> &'a mut W {
+        self.variant(CEIIFGW::CEIIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ceiifg_1(self) -> &'a mut W {
+        self.variant(CEIIFGW::CEIIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CERDYIFG`"]
+pub enum CERDYIFGW {
+    #[doc = "No interrupt pending"]
+    CERDYIFG_0,
+    #[doc = "Interrupt pending"]
+    CERDYIFG_1,
+}
+impl CERDYIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CERDYIFGW::CERDYIFG_0 => false,
+            CERDYIFGW::CERDYIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CERDYIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CERDYIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CERDYIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn cerdyifg_0(self) -> &'a mut W {
+        self.variant(CERDYIFGW::CERDYIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn cerdyifg_1(self) -> &'a mut W {
+        self.variant(CERDYIFGW::CERDYIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEIE`"]
+pub enum CEIEW {
+    #[doc = "Interrupt disabled"]
+    CEIE_0,
+    #[doc = "Interrupt enabled"]
+    CEIE_1,
+}
+impl CEIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEIEW::CEIE_0 => false,
+            CEIEW::CEIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ceie_0(self) -> &'a mut W {
+        self.variant(CEIEW::CEIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ceie_1(self) -> &'a mut W {
+        self.variant(CEIEW::CEIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CEIIE`"]
+pub enum CEIIEW {
+    #[doc = "Interrupt disabled"]
+    CEIIE_0,
+    #[doc = "Interrupt enabled"]
+    CEIIE_1,
+}
+impl CEIIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CEIIEW::CEIIE_0 => false,
+            CEIIEW::CEIIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CEIIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CEIIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CEIIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ceiie_0(self) -> &'a mut W {
+        self.variant(CEIIEW::CEIIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ceiie_1(self) -> &'a mut W {
+        self.variant(CEIIEW::CEIIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CERDYIE`"]
+pub enum CERDYIEW {
+    #[doc = "Interrupt disabled"]
+    CERDYIE_0,
+    #[doc = "Interrupt enabled"]
+    CERDYIE_1,
+}
+impl CERDYIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CERDYIEW::CERDYIE_0 => false,
+            CERDYIEW::CERDYIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CERDYIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CERDYIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CERDYIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn cerdyie_0(self) -> &'a mut W {
+        self.variant(CERDYIEW::CERDYIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn cerdyie_1(self) -> &'a mut W {
+        self.variant(CERDYIEW::CERDYIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Comparator output interrupt flag"]
+    #[inline]
+    pub fn ceifg(&self) -> CEIFGR {
+        CEIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Comparator output inverted interrupt flag"]
+    #[inline]
+    pub fn ceiifg(&self) -> CEIIFGR {
+        CEIIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 4 - Comparator ready interrupt flag"]
+    #[inline]
+    pub fn cerdyifg(&self) -> CERDYIFGR {
+        CERDYIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 8 - Comparator output interrupt enable"]
+    #[inline]
+    pub fn ceie(&self) -> CEIER {
+        CEIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 9 - Comparator output interrupt enable inverted polarity"]
+    #[inline]
+    pub fn ceiie(&self) -> CEIIER {
+        CEIIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 12 - Comparator ready interrupt enable"]
+    #[inline]
+    pub fn cerdyie(&self) -> CERDYIER {
+        CERDYIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Comparator output interrupt flag"]
+    #[inline]
+    pub fn ceifg(&mut self) -> _CEIFGW {
+        _CEIFGW { w: self }
+    }
+    #[doc = "Bit 1 - Comparator output inverted interrupt flag"]
+    #[inline]
+    pub fn ceiifg(&mut self) -> _CEIIFGW {
+        _CEIIFGW { w: self }
+    }
+    #[doc = "Bit 4 - Comparator ready interrupt flag"]
+    #[inline]
+    pub fn cerdyifg(&mut self) -> _CERDYIFGW {
+        _CERDYIFGW { w: self }
+    }
+    #[doc = "Bit 8 - Comparator output interrupt enable"]
+    #[inline]
+    pub fn ceie(&mut self) -> _CEIEW {
+        _CEIEW { w: self }
+    }
+    #[doc = "Bit 9 - Comparator output interrupt enable inverted polarity"]
+    #[inline]
+    pub fn ceiie(&mut self) -> _CEIIEW {
+        _CEIIEW { w: self }
+    }
+    #[doc = "Bit 12 - Comparator ready interrupt enable"]
+    #[inline]
+    pub fn cerdyie(&mut self) -> _CERDYIEW {
+        _CERDYIEW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/comp_e1/cex_iv.rs b/example-source/msp432p401r/src/comp_e1/cex_iv.rs
new file mode 100644
index 0000000..af3dc02
--- /dev/null
+++ b/example-source/msp432p401r/src/comp_e1/cex_iv.rs
@@ -0,0 +1,88 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::CEXIV {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `CEIV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CEIVR {
+    #[doc = "No interrupt pending"]
+    CEIV_0,
+    #[doc = "Interrupt Source: CEOUT interrupt; Interrupt Flag: CEIFG; Interrupt Priority: Highest"]
+    CEIV_2,
+    #[doc = "Interrupt Source: CEOUT interrupt inverted polarity; Interrupt Flag: CEIIFG"]
+    CEIV_4,
+    #[doc = "Interrupt Source: Comparator ready interrupt; Interrupt Flag: CERDYIFG; Interrupt Priority: Lowest"]
+    CEIV_10,
+    #[doc = r" Reserved"]
+    _Reserved(u16),
+}
+impl CEIVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        match *self {
+            CEIVR::CEIV_0 => 0,
+            CEIVR::CEIV_2 => 2,
+            CEIVR::CEIV_4 => 4,
+            CEIVR::CEIV_10 => 10,
+            CEIVR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u16) -> CEIVR {
+        match value {
+            0 => CEIVR::CEIV_0,
+            2 => CEIVR::CEIV_2,
+            4 => CEIVR::CEIV_4,
+            10 => CEIVR::CEIV_10,
+            i => CEIVR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `CEIV_0`"]
+    #[inline]
+    pub fn is_ceiv_0(&self) -> bool {
+        *self == CEIVR::CEIV_0
+    }
+    #[doc = "Checks if the value of the field is `CEIV_2`"]
+    #[inline]
+    pub fn is_ceiv_2(&self) -> bool {
+        *self == CEIVR::CEIV_2
+    }
+    #[doc = "Checks if the value of the field is `CEIV_4`"]
+    #[inline]
+    pub fn is_ceiv_4(&self) -> bool {
+        *self == CEIVR::CEIV_4
+    }
+    #[doc = "Checks if the value of the field is `CEIV_10`"]
+    #[inline]
+    pub fn is_ceiv_10(&self) -> bool {
+        *self == CEIVR::CEIV_10
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Comparator interrupt vector word register"]
+    #[inline]
+    pub fn ceiv(&self) -> CEIVR {
+        CEIVR::_from({
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/crc32.rs b/example-source/msp432p401r/src/crc32.rs
new file mode 100644
index 0000000..5c07d3b
--- /dev/null
+++ b/example-source/msp432p401r/src/crc32.rs
@@ -0,0 +1,89 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - Data Input for CRC32 Signature Computation"]
+    pub crc32di: CRC32DI,
+    _reserved0: [u8; 2usize],
+    #[doc = "0x04 - Data In Reverse for CRC32 Computation"]
+    pub crc32dirb: CRC32DIRB,
+    _reserved1: [u8; 2usize],
+    #[doc = "0x08 - CRC32 Initialization and Result, lower 16 bits"]
+    pub crc32inires_lo: CRC32INIRES_LO,
+    #[doc = "0x0a - CRC32 Initialization and Result, upper 16 bits"]
+    pub crc32inires_hi: CRC32INIRES_HI,
+    #[doc = "0x0c - CRC32 Result Reverse, lower 16 bits"]
+    pub crc32resr_lo: CRC32RESR_LO,
+    #[doc = "0x0e - CRC32 Result Reverse, Upper 16 bits"]
+    pub crc32resr_hi: CRC32RESR_HI,
+    #[doc = "0x10 - Data Input for CRC16 computation"]
+    pub crc16di: CRC16DI,
+    _reserved2: [u8; 2usize],
+    #[doc = "0x14 - CRC16 Data In Reverse"]
+    pub crc16dirb: CRC16DIRB,
+    _reserved3: [u8; 2usize],
+    #[doc = "0x18 - CRC16 Initialization and Result register"]
+    pub crc16inires: CRC16INIRES,
+    _reserved4: [u8; 4usize],
+    #[doc = "0x1e - CRC16 Result Reverse"]
+    pub crc16resr: CRC16RESR,
+}
+#[doc = "Data Input for CRC32 Signature Computation"]
+pub struct CRC32DI {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Data Input for CRC32 Signature Computation"]
+pub mod crc32di;
+#[doc = "Data In Reverse for CRC32 Computation"]
+pub struct CRC32DIRB {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Data In Reverse for CRC32 Computation"]
+pub mod crc32dirb;
+#[doc = "CRC32 Initialization and Result, lower 16 bits"]
+pub struct CRC32INIRES_LO {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "CRC32 Initialization and Result, lower 16 bits"]
+pub mod crc32inires_lo;
+#[doc = "CRC32 Initialization and Result, upper 16 bits"]
+pub struct CRC32INIRES_HI {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "CRC32 Initialization and Result, upper 16 bits"]
+pub mod crc32inires_hi;
+#[doc = "CRC32 Result Reverse, lower 16 bits"]
+pub struct CRC32RESR_LO {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "CRC32 Result Reverse, lower 16 bits"]
+pub mod crc32resr_lo;
+#[doc = "CRC32 Result Reverse, Upper 16 bits"]
+pub struct CRC32RESR_HI {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "CRC32 Result Reverse, Upper 16 bits"]
+pub mod crc32resr_hi;
+#[doc = "Data Input for CRC16 computation"]
+pub struct CRC16DI {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Data Input for CRC16 computation"]
+pub mod crc16di;
+#[doc = "CRC16 Data In Reverse"]
+pub struct CRC16DIRB {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "CRC16 Data In Reverse"]
+pub mod crc16dirb;
+#[doc = "CRC16 Initialization and Result register"]
+pub struct CRC16INIRES {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "CRC16 Initialization and Result register"]
+pub mod crc16inires;
+#[doc = "CRC16 Result Reverse"]
+pub struct CRC16RESR {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "CRC16 Result Reverse"]
+pub mod crc16resr;
diff --git a/example-source/msp432p401r/src/crc32/crc16di.rs b/example-source/msp432p401r/src/crc32/crc16di.rs
new file mode 100644
index 0000000..5a133ff
--- /dev/null
+++ b/example-source/msp432p401r/src/crc32/crc16di.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::CRC16DI {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CRC16DIR {
+    bits: u16,
+}
+impl CRC16DIR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CRC16DIW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CRC16DIW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - CRC16 data in"]
+    #[inline]
+    pub fn crc16di(&self) -> CRC16DIR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        CRC16DIR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - CRC16 data in"]
+    #[inline]
+    pub fn crc16di(&mut self) -> _CRC16DIW {
+        _CRC16DIW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/crc32/crc16dirb.rs b/example-source/msp432p401r/src/crc32/crc16dirb.rs
new file mode 100644
index 0000000..5c6075f
--- /dev/null
+++ b/example-source/msp432p401r/src/crc32/crc16dirb.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::CRC16DIRB {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CRC16DIRBR {
+    bits: u16,
+}
+impl CRC16DIRBR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CRC16DIRBW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CRC16DIRBW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - CRC16 data in reverse byte"]
+    #[inline]
+    pub fn crc16dirb(&self) -> CRC16DIRBR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        CRC16DIRBR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - CRC16 data in reverse byte"]
+    #[inline]
+    pub fn crc16dirb(&mut self) -> _CRC16DIRBW {
+        _CRC16DIRBW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/crc32/crc16inires.rs b/example-source/msp432p401r/src/crc32/crc16inires.rs
new file mode 100644
index 0000000..e8ecf73
--- /dev/null
+++ b/example-source/msp432p401r/src/crc32/crc16inires.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::CRC16INIRES {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CRC16INIRESR {
+    bits: u16,
+}
+impl CRC16INIRESR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CRC16INIRESW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CRC16INIRESW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - CRC16 initialization and result"]
+    #[inline]
+    pub fn crc16inires(&self) -> CRC16INIRESR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        CRC16INIRESR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 65535 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - CRC16 initialization and result"]
+    #[inline]
+    pub fn crc16inires(&mut self) -> _CRC16INIRESW {
+        _CRC16INIRESW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/crc32/crc16resr.rs b/example-source/msp432p401r/src/crc32/crc16resr.rs
new file mode 100644
index 0000000..99f7063
--- /dev/null
+++ b/example-source/msp432p401r/src/crc32/crc16resr.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::CRC16RESR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CRC16RESRR {
+    bits: u16,
+}
+impl CRC16RESRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CRC16RESRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CRC16RESRW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - CRC16 reverse result"]
+    #[inline]
+    pub fn crc16resr(&self) -> CRC16RESRR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        CRC16RESRR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 65535 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - CRC16 reverse result"]
+    #[inline]
+    pub fn crc16resr(&mut self) -> _CRC16RESRW {
+        _CRC16RESRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/crc32/crc32di.rs b/example-source/msp432p401r/src/crc32/crc32di.rs
new file mode 100644
index 0000000..814e69d
--- /dev/null
+++ b/example-source/msp432p401r/src/crc32/crc32di.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::CRC32DI {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CRC32DIR {
+    bits: u16,
+}
+impl CRC32DIR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CRC32DIW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CRC32DIW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Data input register"]
+    #[inline]
+    pub fn crc32di(&self) -> CRC32DIR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        CRC32DIR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Data input register"]
+    #[inline]
+    pub fn crc32di(&mut self) -> _CRC32DIW {
+        _CRC32DIW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/crc32/crc32dirb.rs b/example-source/msp432p401r/src/crc32/crc32dirb.rs
new file mode 100644
index 0000000..af75716
--- /dev/null
+++ b/example-source/msp432p401r/src/crc32/crc32dirb.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::CRC32DIRB {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CRC32DIRBR {
+    bits: u16,
+}
+impl CRC32DIRBR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CRC32DIRBW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CRC32DIRBW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Data input register reversed"]
+    #[inline]
+    pub fn crc32dirb(&self) -> CRC32DIRBR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        CRC32DIRBR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Data input register reversed"]
+    #[inline]
+    pub fn crc32dirb(&mut self) -> _CRC32DIRBW {
+        _CRC32DIRBW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/crc32/crc32inires_hi.rs b/example-source/msp432p401r/src/crc32/crc32inires_hi.rs
new file mode 100644
index 0000000..756c6f1
--- /dev/null
+++ b/example-source/msp432p401r/src/crc32/crc32inires_hi.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::CRC32INIRES_HI {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CRC32INIRES_HIR {
+    bits: u16,
+}
+impl CRC32INIRES_HIR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CRC32INIRES_HIW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CRC32INIRES_HIW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - CRC32 initialization and result, upper 16 bits"]
+    #[inline]
+    pub fn crc32inires_hi(&self) -> CRC32INIRES_HIR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        CRC32INIRES_HIR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - CRC32 initialization and result, upper 16 bits"]
+    #[inline]
+    pub fn crc32inires_hi(&mut self) -> _CRC32INIRES_HIW {
+        _CRC32INIRES_HIW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/crc32/crc32inires_lo.rs b/example-source/msp432p401r/src/crc32/crc32inires_lo.rs
new file mode 100644
index 0000000..4eb7538
--- /dev/null
+++ b/example-source/msp432p401r/src/crc32/crc32inires_lo.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::CRC32INIRES_LO {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CRC32INIRES_LOR {
+    bits: u16,
+}
+impl CRC32INIRES_LOR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CRC32INIRES_LOW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CRC32INIRES_LOW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - CRC32 initialization and result, lower 16 bits"]
+    #[inline]
+    pub fn crc32inires_lo(&self) -> CRC32INIRES_LOR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        CRC32INIRES_LOR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - CRC32 initialization and result, lower 16 bits"]
+    #[inline]
+    pub fn crc32inires_lo(&mut self) -> _CRC32INIRES_LOW {
+        _CRC32INIRES_LOW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/crc32/crc32resr_hi.rs b/example-source/msp432p401r/src/crc32/crc32resr_hi.rs
new file mode 100644
index 0000000..f8d95eb
--- /dev/null
+++ b/example-source/msp432p401r/src/crc32/crc32resr_hi.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::CRC32RESR_HI {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CRC32RESR_HIR {
+    bits: u16,
+}
+impl CRC32RESR_HIR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CRC32RESR_HIW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CRC32RESR_HIW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - CRC32 reverse result, upper 16 bits"]
+    #[inline]
+    pub fn crc32resr_hi(&self) -> CRC32RESR_HIR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        CRC32RESR_HIR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 65535 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - CRC32 reverse result, upper 16 bits"]
+    #[inline]
+    pub fn crc32resr_hi(&mut self) -> _CRC32RESR_HIW {
+        _CRC32RESR_HIW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/crc32/crc32resr_lo.rs b/example-source/msp432p401r/src/crc32/crc32resr_lo.rs
new file mode 100644
index 0000000..065452d
--- /dev/null
+++ b/example-source/msp432p401r/src/crc32/crc32resr_lo.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::CRC32RESR_LO {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CRC32RESR_LOR {
+    bits: u16,
+}
+impl CRC32RESR_LOR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CRC32RESR_LOW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CRC32RESR_LOW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - CRC32 reverse result, lower 16 bits"]
+    #[inline]
+    pub fn crc32resr_lo(&self) -> CRC32RESR_LOR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        CRC32RESR_LOR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 65535 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - CRC32 reverse result, lower 16 bits"]
+    #[inline]
+    pub fn crc32resr_lo(&mut self) -> _CRC32RESR_LOW {
+        _CRC32RESR_LOW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/cs.rs b/example-source/msp432p401r/src/cs.rs
new file mode 100644
index 0000000..9b5ffcc
--- /dev/null
+++ b/example-source/msp432p401r/src/cs.rs
@@ -0,0 +1,114 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - Key Register"]
+    pub cskey: CSKEY,
+    #[doc = "0x04 - Control 0 Register"]
+    pub csctl0: CSCTL0,
+    #[doc = "0x08 - Control 1 Register"]
+    pub csctl1: CSCTL1,
+    #[doc = "0x0c - Control 2 Register"]
+    pub csctl2: CSCTL2,
+    #[doc = "0x10 - Control 3 Register"]
+    pub csctl3: CSCTL3,
+    _reserved0: [u8; 28usize],
+    #[doc = "0x30 - Clock Enable Register"]
+    pub csclken: CSCLKEN,
+    #[doc = "0x34 - Status Register"]
+    pub csstat: CSSTAT,
+    _reserved1: [u8; 8usize],
+    #[doc = "0x40 - Interrupt Enable Register"]
+    pub csie: CSIE,
+    _reserved2: [u8; 4usize],
+    #[doc = "0x48 - Interrupt Flag Register"]
+    pub csifg: CSIFG,
+    _reserved3: [u8; 4usize],
+    #[doc = "0x50 - Clear Interrupt Flag Register"]
+    pub csclrifg: CSCLRIFG,
+    _reserved4: [u8; 4usize],
+    #[doc = "0x58 - Set Interrupt Flag Register"]
+    pub cssetifg: CSSETIFG,
+    _reserved5: [u8; 4usize],
+    #[doc = "0x60 - DCO External Resistor Cailbration 0 Register"]
+    pub csdcoercal0: CSDCOERCAL0,
+    #[doc = "0x64 - DCO External Resistor Calibration 1 Register"]
+    pub csdcoercal1: CSDCOERCAL1,
+}
+#[doc = "Key Register"]
+pub struct CSKEY {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Key Register"]
+pub mod cskey;
+#[doc = "Control 0 Register"]
+pub struct CSCTL0 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Control 0 Register"]
+pub mod csctl0;
+#[doc = "Control 1 Register"]
+pub struct CSCTL1 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Control 1 Register"]
+pub mod csctl1;
+#[doc = "Control 2 Register"]
+pub struct CSCTL2 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Control 2 Register"]
+pub mod csctl2;
+#[doc = "Control 3 Register"]
+pub struct CSCTL3 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Control 3 Register"]
+pub mod csctl3;
+#[doc = "Clock Enable Register"]
+pub struct CSCLKEN {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Clock Enable Register"]
+pub mod csclken;
+#[doc = "Status Register"]
+pub struct CSSTAT {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Status Register"]
+pub mod csstat;
+#[doc = "Interrupt Enable Register"]
+pub struct CSIE {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Interrupt Enable Register"]
+pub mod csie;
+#[doc = "Interrupt Flag Register"]
+pub struct CSIFG {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Interrupt Flag Register"]
+pub mod csifg;
+#[doc = "Clear Interrupt Flag Register"]
+pub struct CSCLRIFG {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Clear Interrupt Flag Register"]
+pub mod csclrifg;
+#[doc = "Set Interrupt Flag Register"]
+pub struct CSSETIFG {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Set Interrupt Flag Register"]
+pub mod cssetifg;
+#[doc = "DCO External Resistor Cailbration 0 Register"]
+pub struct CSDCOERCAL0 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "DCO External Resistor Cailbration 0 Register"]
+pub mod csdcoercal0;
+#[doc = "DCO External Resistor Calibration 1 Register"]
+pub struct CSDCOERCAL1 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "DCO External Resistor Calibration 1 Register"]
+pub mod csdcoercal1;
diff --git a/example-source/msp432p401r/src/cs/csclken.rs b/example-source/msp432p401r/src/cs/csclken.rs
new file mode 100644
index 0000000..c3892ec
--- /dev/null
+++ b/example-source/msp432p401r/src/cs/csclken.rs
@@ -0,0 +1,1016 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CSCLKEN {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `ACLK_EN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ACLK_ENR {
+    #[doc = "ACLK disabled regardless of conditional clock requests"]
+    ACLK_EN_0,
+    #[doc = "ACLK enabled based on any conditional clock requests"]
+    ACLK_EN_1,
+}
+impl ACLK_ENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ACLK_ENR::ACLK_EN_0 => false,
+            ACLK_ENR::ACLK_EN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ACLK_ENR {
+        match value {
+            false => ACLK_ENR::ACLK_EN_0,
+            true => ACLK_ENR::ACLK_EN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ACLK_EN_0`"]
+    #[inline]
+    pub fn is_aclk_en_0(&self) -> bool {
+        *self == ACLK_ENR::ACLK_EN_0
+    }
+    #[doc = "Checks if the value of the field is `ACLK_EN_1`"]
+    #[inline]
+    pub fn is_aclk_en_1(&self) -> bool {
+        *self == ACLK_ENR::ACLK_EN_1
+    }
+}
+#[doc = "Possible values of the field `MCLK_EN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum MCLK_ENR {
+    #[doc = "MCLK disabled regardless of conditional clock requests"]
+    MCLK_EN_0,
+    #[doc = "MCLK enabled based on any conditional clock requests"]
+    MCLK_EN_1,
+}
+impl MCLK_ENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            MCLK_ENR::MCLK_EN_0 => false,
+            MCLK_ENR::MCLK_EN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> MCLK_ENR {
+        match value {
+            false => MCLK_ENR::MCLK_EN_0,
+            true => MCLK_ENR::MCLK_EN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `MCLK_EN_0`"]
+    #[inline]
+    pub fn is_mclk_en_0(&self) -> bool {
+        *self == MCLK_ENR::MCLK_EN_0
+    }
+    #[doc = "Checks if the value of the field is `MCLK_EN_1`"]
+    #[inline]
+    pub fn is_mclk_en_1(&self) -> bool {
+        *self == MCLK_ENR::MCLK_EN_1
+    }
+}
+#[doc = "Possible values of the field `HSMCLK_EN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HSMCLK_ENR {
+    #[doc = "HSMCLK disabled regardless of conditional clock requests"]
+    HSMCLK_EN_0,
+    #[doc = "HSMCLK enabled based on any conditional clock requests"]
+    HSMCLK_EN_1,
+}
+impl HSMCLK_ENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            HSMCLK_ENR::HSMCLK_EN_0 => false,
+            HSMCLK_ENR::HSMCLK_EN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> HSMCLK_ENR {
+        match value {
+            false => HSMCLK_ENR::HSMCLK_EN_0,
+            true => HSMCLK_ENR::HSMCLK_EN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `HSMCLK_EN_0`"]
+    #[inline]
+    pub fn is_hsmclk_en_0(&self) -> bool {
+        *self == HSMCLK_ENR::HSMCLK_EN_0
+    }
+    #[doc = "Checks if the value of the field is `HSMCLK_EN_1`"]
+    #[inline]
+    pub fn is_hsmclk_en_1(&self) -> bool {
+        *self == HSMCLK_ENR::HSMCLK_EN_1
+    }
+}
+#[doc = "Possible values of the field `SMCLK_EN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SMCLK_ENR {
+    #[doc = "SMCLK disabled regardless of conditional clock requests."]
+    SMCLK_EN_0,
+    #[doc = "SMCLK enabled based on any conditional clock requests"]
+    SMCLK_EN_1,
+}
+impl SMCLK_ENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            SMCLK_ENR::SMCLK_EN_0 => false,
+            SMCLK_ENR::SMCLK_EN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> SMCLK_ENR {
+        match value {
+            false => SMCLK_ENR::SMCLK_EN_0,
+            true => SMCLK_ENR::SMCLK_EN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SMCLK_EN_0`"]
+    #[inline]
+    pub fn is_smclk_en_0(&self) -> bool {
+        *self == SMCLK_ENR::SMCLK_EN_0
+    }
+    #[doc = "Checks if the value of the field is `SMCLK_EN_1`"]
+    #[inline]
+    pub fn is_smclk_en_1(&self) -> bool {
+        *self == SMCLK_ENR::SMCLK_EN_1
+    }
+}
+#[doc = "Possible values of the field `VLO_EN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum VLO_ENR {
+    #[doc = "VLO is on only if it is used as a source for ACLK, MCLK, HSMCLK or SMCLK."]
+    VLO_EN_0,
+    #[doc = "VLO is on"]
+    VLO_EN_1,
+}
+impl VLO_ENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            VLO_ENR::VLO_EN_0 => false,
+            VLO_ENR::VLO_EN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> VLO_ENR {
+        match value {
+            false => VLO_ENR::VLO_EN_0,
+            true => VLO_ENR::VLO_EN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `VLO_EN_0`"]
+    #[inline]
+    pub fn is_vlo_en_0(&self) -> bool {
+        *self == VLO_ENR::VLO_EN_0
+    }
+    #[doc = "Checks if the value of the field is `VLO_EN_1`"]
+    #[inline]
+    pub fn is_vlo_en_1(&self) -> bool {
+        *self == VLO_ENR::VLO_EN_1
+    }
+}
+#[doc = "Possible values of the field `REFO_EN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum REFO_ENR {
+    #[doc = "REFO is on only if it is used as a source for ACLK, MCLK, HSMCLK or SMCLK"]
+    REFO_EN_0,
+    #[doc = "REFO is on"]
+    REFO_EN_1,
+}
+impl REFO_ENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            REFO_ENR::REFO_EN_0 => false,
+            REFO_ENR::REFO_EN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> REFO_ENR {
+        match value {
+            false => REFO_ENR::REFO_EN_0,
+            true => REFO_ENR::REFO_EN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `REFO_EN_0`"]
+    #[inline]
+    pub fn is_refo_en_0(&self) -> bool {
+        *self == REFO_ENR::REFO_EN_0
+    }
+    #[doc = "Checks if the value of the field is `REFO_EN_1`"]
+    #[inline]
+    pub fn is_refo_en_1(&self) -> bool {
+        *self == REFO_ENR::REFO_EN_1
+    }
+}
+#[doc = "Possible values of the field `MODOSC_EN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum MODOSC_ENR {
+    #[doc = "MODOSC is on only if it is used as a source for ACLK, MCLK, HSMCLK or SMCLK"]
+    MODOSC_EN_0,
+    #[doc = "MODOSC is on"]
+    MODOSC_EN_1,
+}
+impl MODOSC_ENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            MODOSC_ENR::MODOSC_EN_0 => false,
+            MODOSC_ENR::MODOSC_EN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> MODOSC_ENR {
+        match value {
+            false => MODOSC_ENR::MODOSC_EN_0,
+            true => MODOSC_ENR::MODOSC_EN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `MODOSC_EN_0`"]
+    #[inline]
+    pub fn is_modosc_en_0(&self) -> bool {
+        *self == MODOSC_ENR::MODOSC_EN_0
+    }
+    #[doc = "Checks if the value of the field is `MODOSC_EN_1`"]
+    #[inline]
+    pub fn is_modosc_en_1(&self) -> bool {
+        *self == MODOSC_ENR::MODOSC_EN_1
+    }
+}
+#[doc = "Possible values of the field `REFOFSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum REFOFSELR {
+    #[doc = "32 kHz"]
+    REFOFSEL_0,
+    #[doc = "128 kHz"]
+    REFOFSEL_1,
+}
+impl REFOFSELR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            REFOFSELR::REFOFSEL_0 => false,
+            REFOFSELR::REFOFSEL_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> REFOFSELR {
+        match value {
+            false => REFOFSELR::REFOFSEL_0,
+            true => REFOFSELR::REFOFSEL_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `REFOFSEL_0`"]
+    #[inline]
+    pub fn is_refofsel_0(&self) -> bool {
+        *self == REFOFSELR::REFOFSEL_0
+    }
+    #[doc = "Checks if the value of the field is `REFOFSEL_1`"]
+    #[inline]
+    pub fn is_refofsel_1(&self) -> bool {
+        *self == REFOFSELR::REFOFSEL_1
+    }
+}
+#[doc = "Values that can be written to the field `ACLK_EN`"]
+pub enum ACLK_ENW {
+    #[doc = "ACLK disabled regardless of conditional clock requests"]
+    ACLK_EN_0,
+    #[doc = "ACLK enabled based on any conditional clock requests"]
+    ACLK_EN_1,
+}
+impl ACLK_ENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ACLK_ENW::ACLK_EN_0 => false,
+            ACLK_ENW::ACLK_EN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ACLK_ENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ACLK_ENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ACLK_ENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "ACLK disabled regardless of conditional clock requests"]
+    #[inline]
+    pub fn aclk_en_0(self) -> &'a mut W {
+        self.variant(ACLK_ENW::ACLK_EN_0)
+    }
+    #[doc = "ACLK enabled based on any conditional clock requests"]
+    #[inline]
+    pub fn aclk_en_1(self) -> &'a mut W {
+        self.variant(ACLK_ENW::ACLK_EN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `MCLK_EN`"]
+pub enum MCLK_ENW {
+    #[doc = "MCLK disabled regardless of conditional clock requests"]
+    MCLK_EN_0,
+    #[doc = "MCLK enabled based on any conditional clock requests"]
+    MCLK_EN_1,
+}
+impl MCLK_ENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            MCLK_ENW::MCLK_EN_0 => false,
+            MCLK_ENW::MCLK_EN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MCLK_ENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MCLK_ENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: MCLK_ENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "MCLK disabled regardless of conditional clock requests"]
+    #[inline]
+    pub fn mclk_en_0(self) -> &'a mut W {
+        self.variant(MCLK_ENW::MCLK_EN_0)
+    }
+    #[doc = "MCLK enabled based on any conditional clock requests"]
+    #[inline]
+    pub fn mclk_en_1(self) -> &'a mut W {
+        self.variant(MCLK_ENW::MCLK_EN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `HSMCLK_EN`"]
+pub enum HSMCLK_ENW {
+    #[doc = "HSMCLK disabled regardless of conditional clock requests"]
+    HSMCLK_EN_0,
+    #[doc = "HSMCLK enabled based on any conditional clock requests"]
+    HSMCLK_EN_1,
+}
+impl HSMCLK_ENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            HSMCLK_ENW::HSMCLK_EN_0 => false,
+            HSMCLK_ENW::HSMCLK_EN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _HSMCLK_ENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _HSMCLK_ENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: HSMCLK_ENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "HSMCLK disabled regardless of conditional clock requests"]
+    #[inline]
+    pub fn hsmclk_en_0(self) -> &'a mut W {
+        self.variant(HSMCLK_ENW::HSMCLK_EN_0)
+    }
+    #[doc = "HSMCLK enabled based on any conditional clock requests"]
+    #[inline]
+    pub fn hsmclk_en_1(self) -> &'a mut W {
+        self.variant(HSMCLK_ENW::HSMCLK_EN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `SMCLK_EN`"]
+pub enum SMCLK_ENW {
+    #[doc = "SMCLK disabled regardless of conditional clock requests."]
+    SMCLK_EN_0,
+    #[doc = "SMCLK enabled based on any conditional clock requests"]
+    SMCLK_EN_1,
+}
+impl SMCLK_ENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            SMCLK_ENW::SMCLK_EN_0 => false,
+            SMCLK_ENW::SMCLK_EN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SMCLK_ENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SMCLK_ENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SMCLK_ENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "SMCLK disabled regardless of conditional clock requests."]
+    #[inline]
+    pub fn smclk_en_0(self) -> &'a mut W {
+        self.variant(SMCLK_ENW::SMCLK_EN_0)
+    }
+    #[doc = "SMCLK enabled based on any conditional clock requests"]
+    #[inline]
+    pub fn smclk_en_1(self) -> &'a mut W {
+        self.variant(SMCLK_ENW::SMCLK_EN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `VLO_EN`"]
+pub enum VLO_ENW {
+    #[doc = "VLO is on only if it is used as a source for ACLK, MCLK, HSMCLK or SMCLK."]
+    VLO_EN_0,
+    #[doc = "VLO is on"]
+    VLO_EN_1,
+}
+impl VLO_ENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            VLO_ENW::VLO_EN_0 => false,
+            VLO_ENW::VLO_EN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _VLO_ENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _VLO_ENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: VLO_ENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "VLO is on only if it is used as a source for ACLK, MCLK, HSMCLK or SMCLK."]
+    #[inline]
+    pub fn vlo_en_0(self) -> &'a mut W {
+        self.variant(VLO_ENW::VLO_EN_0)
+    }
+    #[doc = "VLO is on"]
+    #[inline]
+    pub fn vlo_en_1(self) -> &'a mut W {
+        self.variant(VLO_ENW::VLO_EN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `REFO_EN`"]
+pub enum REFO_ENW {
+    #[doc = "REFO is on only if it is used as a source for ACLK, MCLK, HSMCLK or SMCLK"]
+    REFO_EN_0,
+    #[doc = "REFO is on"]
+    REFO_EN_1,
+}
+impl REFO_ENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            REFO_ENW::REFO_EN_0 => false,
+            REFO_ENW::REFO_EN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _REFO_ENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _REFO_ENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: REFO_ENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "REFO is on only if it is used as a source for ACLK, MCLK, HSMCLK or SMCLK"]
+    #[inline]
+    pub fn refo_en_0(self) -> &'a mut W {
+        self.variant(REFO_ENW::REFO_EN_0)
+    }
+    #[doc = "REFO is on"]
+    #[inline]
+    pub fn refo_en_1(self) -> &'a mut W {
+        self.variant(REFO_ENW::REFO_EN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `MODOSC_EN`"]
+pub enum MODOSC_ENW {
+    #[doc = "MODOSC is on only if it is used as a source for ACLK, MCLK, HSMCLK or SMCLK"]
+    MODOSC_EN_0,
+    #[doc = "MODOSC is on"]
+    MODOSC_EN_1,
+}
+impl MODOSC_ENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            MODOSC_ENW::MODOSC_EN_0 => false,
+            MODOSC_ENW::MODOSC_EN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MODOSC_ENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MODOSC_ENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: MODOSC_ENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "MODOSC is on only if it is used as a source for ACLK, MCLK, HSMCLK or SMCLK"]
+    #[inline]
+    pub fn modosc_en_0(self) -> &'a mut W {
+        self.variant(MODOSC_ENW::MODOSC_EN_0)
+    }
+    #[doc = "MODOSC is on"]
+    #[inline]
+    pub fn modosc_en_1(self) -> &'a mut W {
+        self.variant(MODOSC_ENW::MODOSC_EN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `REFOFSEL`"]
+pub enum REFOFSELW {
+    #[doc = "32 kHz"]
+    REFOFSEL_0,
+    #[doc = "128 kHz"]
+    REFOFSEL_1,
+}
+impl REFOFSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            REFOFSELW::REFOFSEL_0 => false,
+            REFOFSELW::REFOFSEL_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _REFOFSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _REFOFSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: REFOFSELW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "32 kHz"]
+    #[inline]
+    pub fn refofsel_0(self) -> &'a mut W {
+        self.variant(REFOFSELW::REFOFSEL_0)
+    }
+    #[doc = "128 kHz"]
+    #[inline]
+    pub fn refofsel_1(self) -> &'a mut W {
+        self.variant(REFOFSELW::REFOFSEL_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - ACLK system clock conditional request enable"]
+    #[inline]
+    pub fn aclk_en(&self) -> ACLK_ENR {
+        ACLK_ENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - MCLK system clock conditional request enable"]
+    #[inline]
+    pub fn mclk_en(&self) -> MCLK_ENR {
+        MCLK_ENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - HSMCLK system clock conditional request enable"]
+    #[inline]
+    pub fn hsmclk_en(&self) -> HSMCLK_ENR {
+        HSMCLK_ENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 3 - SMCLK system clock conditional request enable"]
+    #[inline]
+    pub fn smclk_en(&self) -> SMCLK_ENR {
+        SMCLK_ENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 8 - Turns on the VLO oscillator"]
+    #[inline]
+    pub fn vlo_en(&self) -> VLO_ENR {
+        VLO_ENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 9 - Turns on the REFO oscillator"]
+    #[inline]
+    pub fn refo_en(&self) -> REFO_ENR {
+        REFO_ENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 10 - Turns on the MODOSC oscillator"]
+    #[inline]
+    pub fn modosc_en(&self) -> MODOSC_ENR {
+        MODOSC_ENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 15 - Selects REFO nominal frequency"]
+    #[inline]
+    pub fn refofsel(&self) -> REFOFSELR {
+        REFOFSELR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 15 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - ACLK system clock conditional request enable"]
+    #[inline]
+    pub fn aclk_en(&mut self) -> _ACLK_ENW {
+        _ACLK_ENW { w: self }
+    }
+    #[doc = "Bit 1 - MCLK system clock conditional request enable"]
+    #[inline]
+    pub fn mclk_en(&mut self) -> _MCLK_ENW {
+        _MCLK_ENW { w: self }
+    }
+    #[doc = "Bit 2 - HSMCLK system clock conditional request enable"]
+    #[inline]
+    pub fn hsmclk_en(&mut self) -> _HSMCLK_ENW {
+        _HSMCLK_ENW { w: self }
+    }
+    #[doc = "Bit 3 - SMCLK system clock conditional request enable"]
+    #[inline]
+    pub fn smclk_en(&mut self) -> _SMCLK_ENW {
+        _SMCLK_ENW { w: self }
+    }
+    #[doc = "Bit 8 - Turns on the VLO oscillator"]
+    #[inline]
+    pub fn vlo_en(&mut self) -> _VLO_ENW {
+        _VLO_ENW { w: self }
+    }
+    #[doc = "Bit 9 - Turns on the REFO oscillator"]
+    #[inline]
+    pub fn refo_en(&mut self) -> _REFO_ENW {
+        _REFO_ENW { w: self }
+    }
+    #[doc = "Bit 10 - Turns on the MODOSC oscillator"]
+    #[inline]
+    pub fn modosc_en(&mut self) -> _MODOSC_ENW {
+        _MODOSC_ENW { w: self }
+    }
+    #[doc = "Bit 15 - Selects REFO nominal frequency"]
+    #[inline]
+    pub fn refofsel(&mut self) -> _REFOFSELW {
+        _REFOFSELW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/cs/csclrifg.rs b/example-source/msp432p401r/src/cs/csclrifg.rs
new file mode 100644
index 0000000..3107cbf
--- /dev/null
+++ b/example-source/msp432p401r/src/cs/csclrifg.rs
@@ -0,0 +1,722 @@
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CSCLRIFG {
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+}
+#[doc = "Values that can be written to the field `CLR_LFXTIFG`"]
+pub enum CLR_LFXTIFGW {
+    #[doc = "No effect"]
+    CLR_LFXTIFG_0,
+    #[doc = "Clear pending interrupt flag"]
+    CLR_LFXTIFG_1,
+}
+impl CLR_LFXTIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLR_LFXTIFGW::CLR_LFXTIFG_0 => false,
+            CLR_LFXTIFGW::CLR_LFXTIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLR_LFXTIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLR_LFXTIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLR_LFXTIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No effect"]
+    #[inline]
+    pub fn clr_lfxtifg_0(self) -> &'a mut W {
+        self.variant(CLR_LFXTIFGW::CLR_LFXTIFG_0)
+    }
+    #[doc = "Clear pending interrupt flag"]
+    #[inline]
+    pub fn clr_lfxtifg_1(self) -> &'a mut W {
+        self.variant(CLR_LFXTIFGW::CLR_LFXTIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLR_HFXTIFG`"]
+pub enum CLR_HFXTIFGW {
+    #[doc = "No effect"]
+    CLR_HFXTIFG_0,
+    #[doc = "Clear pending interrupt flag"]
+    CLR_HFXTIFG_1,
+}
+impl CLR_HFXTIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLR_HFXTIFGW::CLR_HFXTIFG_0 => false,
+            CLR_HFXTIFGW::CLR_HFXTIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLR_HFXTIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLR_HFXTIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLR_HFXTIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No effect"]
+    #[inline]
+    pub fn clr_hfxtifg_0(self) -> &'a mut W {
+        self.variant(CLR_HFXTIFGW::CLR_HFXTIFG_0)
+    }
+    #[doc = "Clear pending interrupt flag"]
+    #[inline]
+    pub fn clr_hfxtifg_1(self) -> &'a mut W {
+        self.variant(CLR_HFXTIFGW::CLR_HFXTIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLR_HFXT2IFG`"]
+pub enum CLR_HFXT2IFGW {
+    #[doc = "No effect"]
+    CLR_HFXT2IFG_0,
+    #[doc = "Clear pending interrupt flag"]
+    CLR_HFXT2IFG_1,
+}
+impl CLR_HFXT2IFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLR_HFXT2IFGW::CLR_HFXT2IFG_0 => false,
+            CLR_HFXT2IFGW::CLR_HFXT2IFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLR_HFXT2IFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLR_HFXT2IFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLR_HFXT2IFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No effect"]
+    #[inline]
+    pub fn clr_hfxt2ifg_0(self) -> &'a mut W {
+        self.variant(CLR_HFXT2IFGW::CLR_HFXT2IFG_0)
+    }
+    #[doc = "Clear pending interrupt flag"]
+    #[inline]
+    pub fn clr_hfxt2ifg_1(self) -> &'a mut W {
+        self.variant(CLR_HFXT2IFGW::CLR_HFXT2IFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLR_DCOR_OPNIFG`"]
+pub enum CLR_DCOR_OPNIFGW {
+    #[doc = "No effect"]
+    CLR_DCOR_OPNIFG_0,
+    #[doc = "Clear pending interrupt flag"]
+    CLR_DCOR_OPNIFG_1,
+}
+impl CLR_DCOR_OPNIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLR_DCOR_OPNIFGW::CLR_DCOR_OPNIFG_0 => false,
+            CLR_DCOR_OPNIFGW::CLR_DCOR_OPNIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLR_DCOR_OPNIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLR_DCOR_OPNIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLR_DCOR_OPNIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No effect"]
+    #[inline]
+    pub fn clr_dcor_opnifg_0(self) -> &'a mut W {
+        self.variant(CLR_DCOR_OPNIFGW::CLR_DCOR_OPNIFG_0)
+    }
+    #[doc = "Clear pending interrupt flag"]
+    #[inline]
+    pub fn clr_dcor_opnifg_1(self) -> &'a mut W {
+        self.variant(CLR_DCOR_OPNIFGW::CLR_DCOR_OPNIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLR_CALIFG`"]
+pub enum CLR_CALIFGW {
+    #[doc = "No effect"]
+    CLR_CALIFG_0,
+    #[doc = "Clear pending interrupt flag"]
+    CLR_CALIFG_1,
+}
+impl CLR_CALIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLR_CALIFGW::CLR_CALIFG_0 => false,
+            CLR_CALIFGW::CLR_CALIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLR_CALIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLR_CALIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLR_CALIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No effect"]
+    #[inline]
+    pub fn clr_califg_0(self) -> &'a mut W {
+        self.variant(CLR_CALIFGW::CLR_CALIFG_0)
+    }
+    #[doc = "Clear pending interrupt flag"]
+    #[inline]
+    pub fn clr_califg_1(self) -> &'a mut W {
+        self.variant(CLR_CALIFGW::CLR_CALIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLR_FCNTLFIFG`"]
+pub enum CLR_FCNTLFIFGW {
+    #[doc = "No effect"]
+    CLR_FCNTLFIFG_0,
+    #[doc = "Clear pending interrupt flag"]
+    CLR_FCNTLFIFG_1,
+}
+impl CLR_FCNTLFIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLR_FCNTLFIFGW::CLR_FCNTLFIFG_0 => false,
+            CLR_FCNTLFIFGW::CLR_FCNTLFIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLR_FCNTLFIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLR_FCNTLFIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLR_FCNTLFIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No effect"]
+    #[inline]
+    pub fn clr_fcntlfifg_0(self) -> &'a mut W {
+        self.variant(CLR_FCNTLFIFGW::CLR_FCNTLFIFG_0)
+    }
+    #[doc = "Clear pending interrupt flag"]
+    #[inline]
+    pub fn clr_fcntlfifg_1(self) -> &'a mut W {
+        self.variant(CLR_FCNTLFIFGW::CLR_FCNTLFIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLR_FCNTHFIFG`"]
+pub enum CLR_FCNTHFIFGW {
+    #[doc = "No effect"]
+    CLR_FCNTHFIFG_0,
+    #[doc = "Clear pending interrupt flag"]
+    CLR_FCNTHFIFG_1,
+}
+impl CLR_FCNTHFIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLR_FCNTHFIFGW::CLR_FCNTHFIFG_0 => false,
+            CLR_FCNTHFIFGW::CLR_FCNTHFIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLR_FCNTHFIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLR_FCNTHFIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLR_FCNTHFIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No effect"]
+    #[inline]
+    pub fn clr_fcnthfifg_0(self) -> &'a mut W {
+        self.variant(CLR_FCNTHFIFGW::CLR_FCNTHFIFG_0)
+    }
+    #[doc = "Clear pending interrupt flag"]
+    #[inline]
+    pub fn clr_fcnthfifg_1(self) -> &'a mut W {
+        self.variant(CLR_FCNTHFIFGW::CLR_FCNTHFIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLR_FCNTHF2IFG`"]
+pub enum CLR_FCNTHF2IFGW {
+    #[doc = "No effect"]
+    CLR_FCNTHF2IFG_0,
+    #[doc = "Clear pending interrupt flag"]
+    CLR_FCNTHF2IFG_1,
+}
+impl CLR_FCNTHF2IFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLR_FCNTHF2IFGW::CLR_FCNTHF2IFG_0 => false,
+            CLR_FCNTHF2IFGW::CLR_FCNTHF2IFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLR_FCNTHF2IFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLR_FCNTHF2IFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLR_FCNTHF2IFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No effect"]
+    #[inline]
+    pub fn clr_fcnthf2ifg_0(self) -> &'a mut W {
+        self.variant(CLR_FCNTHF2IFGW::CLR_FCNTHF2IFG_0)
+    }
+    #[doc = "Clear pending interrupt flag"]
+    #[inline]
+    pub fn clr_fcnthf2ifg_1(self) -> &'a mut W {
+        self.variant(CLR_FCNTHF2IFGW::CLR_FCNTHF2IFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLR_PLLOOLIFG`"]
+pub enum CLR_PLLOOLIFGW {
+    #[doc = "No effect"]
+    CLR_PLLOOLIFG_0,
+    #[doc = "Clear pending interrupt flag"]
+    CLR_PLLOOLIFG_1,
+}
+impl CLR_PLLOOLIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLR_PLLOOLIFGW::CLR_PLLOOLIFG_0 => false,
+            CLR_PLLOOLIFGW::CLR_PLLOOLIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLR_PLLOOLIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLR_PLLOOLIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLR_PLLOOLIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No effect"]
+    #[inline]
+    pub fn clr_plloolifg_0(self) -> &'a mut W {
+        self.variant(CLR_PLLOOLIFGW::CLR_PLLOOLIFG_0)
+    }
+    #[doc = "Clear pending interrupt flag"]
+    #[inline]
+    pub fn clr_plloolifg_1(self) -> &'a mut W {
+        self.variant(CLR_PLLOOLIFGW::CLR_PLLOOLIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLR_PLLLOSIFG`"]
+pub enum CLR_PLLLOSIFGW {
+    #[doc = "No effect"]
+    CLR_PLLLOSIFG_0,
+    #[doc = "Clear pending interrupt flag"]
+    CLR_PLLLOSIFG_1,
+}
+impl CLR_PLLLOSIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLR_PLLLOSIFGW::CLR_PLLLOSIFG_0 => false,
+            CLR_PLLLOSIFGW::CLR_PLLLOSIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLR_PLLLOSIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLR_PLLLOSIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLR_PLLLOSIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No effect"]
+    #[inline]
+    pub fn clr_plllosifg_0(self) -> &'a mut W {
+        self.variant(CLR_PLLLOSIFGW::CLR_PLLLOSIFG_0)
+    }
+    #[doc = "Clear pending interrupt flag"]
+    #[inline]
+    pub fn clr_plllosifg_1(self) -> &'a mut W {
+        self.variant(CLR_PLLLOSIFGW::CLR_PLLLOSIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CLR_PLLOORIFG`"]
+pub enum CLR_PLLOORIFGW {
+    #[doc = "No effect"]
+    CLR_PLLOORIFG_0,
+    #[doc = "Clear pending interrupt flag"]
+    CLR_PLLOORIFG_1,
+}
+impl CLR_PLLOORIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLR_PLLOORIFGW::CLR_PLLOORIFG_0 => false,
+            CLR_PLLOORIFGW::CLR_PLLOORIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLR_PLLOORIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLR_PLLOORIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLR_PLLOORIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No effect"]
+    #[inline]
+    pub fn clr_plloorifg_0(self) -> &'a mut W {
+        self.variant(CLR_PLLOORIFGW::CLR_PLLOORIFG_0)
+    }
+    #[doc = "Clear pending interrupt flag"]
+    #[inline]
+    pub fn clr_plloorifg_1(self) -> &'a mut W {
+        self.variant(CLR_PLLOORIFGW::CLR_PLLOORIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Clear LFXT oscillator fault interrupt flag"]
+    #[inline]
+    pub fn clr_lfxtifg(&mut self) -> _CLR_LFXTIFGW {
+        _CLR_LFXTIFGW { w: self }
+    }
+    #[doc = "Bit 1 - Clear HFXT oscillator fault interrupt flag"]
+    #[inline]
+    pub fn clr_hfxtifg(&mut self) -> _CLR_HFXTIFGW {
+        _CLR_HFXTIFGW { w: self }
+    }
+    #[doc = "Bit 2 - Clear HFXT2 oscillator fault interrupt flag"]
+    #[inline]
+    pub fn clr_hfxt2ifg(&mut self) -> _CLR_HFXT2IFGW {
+        _CLR_HFXT2IFGW { w: self }
+    }
+    #[doc = "Bit 6 - Clear DCO external resistor open circuit fault interrupt flag."]
+    #[inline]
+    pub fn clr_dcor_opnifg(&mut self) -> _CLR_DCOR_OPNIFGW {
+        _CLR_DCOR_OPNIFGW { w: self }
+    }
+    #[doc = "Bit 15 - REFCNT period counter clear interrupt flag"]
+    #[inline]
+    pub fn clr_califg(&mut self) -> _CLR_CALIFGW {
+        _CLR_CALIFGW { w: self }
+    }
+    #[doc = "Bit 8 - Start fault counter clear interrupt flag LFXT"]
+    #[inline]
+    pub fn clr_fcntlfifg(&mut self) -> _CLR_FCNTLFIFGW {
+        _CLR_FCNTLFIFGW { w: self }
+    }
+    #[doc = "Bit 9 - Start fault counter clear interrupt flag HFXT"]
+    #[inline]
+    pub fn clr_fcnthfifg(&mut self) -> _CLR_FCNTHFIFGW {
+        _CLR_FCNTHFIFGW { w: self }
+    }
+    #[doc = "Bit 10 - Start fault counter clear interrupt flag HFXT2"]
+    #[inline]
+    pub fn clr_fcnthf2ifg(&mut self) -> _CLR_FCNTHF2IFGW {
+        _CLR_FCNTHF2IFGW { w: self }
+    }
+    #[doc = "Bit 12 - PLL out-of-lock clear interrupt flag"]
+    #[inline]
+    pub fn clr_plloolifg(&mut self) -> _CLR_PLLOOLIFGW {
+        _CLR_PLLOOLIFGW { w: self }
+    }
+    #[doc = "Bit 13 - PLL loss-of-signal clear interrupt flag"]
+    #[inline]
+    pub fn clr_plllosifg(&mut self) -> _CLR_PLLLOSIFGW {
+        _CLR_PLLLOSIFGW { w: self }
+    }
+    #[doc = "Bit 14 - PLL out-of-range clear interrupt flag"]
+    #[inline]
+    pub fn clr_plloorifg(&mut self) -> _CLR_PLLOORIFGW {
+        _CLR_PLLOORIFGW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/cs/csctl0.rs b/example-source/msp432p401r/src/cs/csctl0.rs
new file mode 100644
index 0000000..c0a1052
--- /dev/null
+++ b/example-source/msp432p401r/src/cs/csctl0.rs
@@ -0,0 +1,514 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CSCTL0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DCOTUNER {
+    bits: u16,
+}
+impl DCOTUNER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `DCORSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DCORSELR {
+    #[doc = "Nominal DCO Frequency Range (MHz): 1 to 2"]
+    DCORSEL_0,
+    #[doc = "Nominal DCO Frequency Range (MHz): 2 to 4"]
+    DCORSEL_1,
+    #[doc = "Nominal DCO Frequency Range (MHz): 4 to 8"]
+    DCORSEL_2,
+    #[doc = "Nominal DCO Frequency Range (MHz): 8 to 16"]
+    DCORSEL_3,
+    #[doc = "Nominal DCO Frequency Range (MHz): 16 to 32"]
+    DCORSEL_4,
+    #[doc = "Nominal DCO Frequency Range (MHz): 32 to 64"]
+    DCORSEL_5,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl DCORSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            DCORSELR::DCORSEL_0 => 0,
+            DCORSELR::DCORSEL_1 => 1,
+            DCORSELR::DCORSEL_2 => 2,
+            DCORSELR::DCORSEL_3 => 3,
+            DCORSELR::DCORSEL_4 => 4,
+            DCORSELR::DCORSEL_5 => 5,
+            DCORSELR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> DCORSELR {
+        match value {
+            0 => DCORSELR::DCORSEL_0,
+            1 => DCORSELR::DCORSEL_1,
+            2 => DCORSELR::DCORSEL_2,
+            3 => DCORSELR::DCORSEL_3,
+            4 => DCORSELR::DCORSEL_4,
+            5 => DCORSELR::DCORSEL_5,
+            i => DCORSELR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `DCORSEL_0`"]
+    #[inline]
+    pub fn is_dcorsel_0(&self) -> bool {
+        *self == DCORSELR::DCORSEL_0
+    }
+    #[doc = "Checks if the value of the field is `DCORSEL_1`"]
+    #[inline]
+    pub fn is_dcorsel_1(&self) -> bool {
+        *self == DCORSELR::DCORSEL_1
+    }
+    #[doc = "Checks if the value of the field is `DCORSEL_2`"]
+    #[inline]
+    pub fn is_dcorsel_2(&self) -> bool {
+        *self == DCORSELR::DCORSEL_2
+    }
+    #[doc = "Checks if the value of the field is `DCORSEL_3`"]
+    #[inline]
+    pub fn is_dcorsel_3(&self) -> bool {
+        *self == DCORSELR::DCORSEL_3
+    }
+    #[doc = "Checks if the value of the field is `DCORSEL_4`"]
+    #[inline]
+    pub fn is_dcorsel_4(&self) -> bool {
+        *self == DCORSELR::DCORSEL_4
+    }
+    #[doc = "Checks if the value of the field is `DCORSEL_5`"]
+    #[inline]
+    pub fn is_dcorsel_5(&self) -> bool {
+        *self == DCORSELR::DCORSEL_5
+    }
+}
+#[doc = "Possible values of the field `DCORES`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DCORESR {
+    #[doc = "Internal resistor mode"]
+    DCORES_0,
+    #[doc = "External resistor mode"]
+    DCORES_1,
+}
+impl DCORESR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            DCORESR::DCORES_0 => false,
+            DCORESR::DCORES_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> DCORESR {
+        match value {
+            false => DCORESR::DCORES_0,
+            true => DCORESR::DCORES_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DCORES_0`"]
+    #[inline]
+    pub fn is_dcores_0(&self) -> bool {
+        *self == DCORESR::DCORES_0
+    }
+    #[doc = "Checks if the value of the field is `DCORES_1`"]
+    #[inline]
+    pub fn is_dcores_1(&self) -> bool {
+        *self == DCORESR::DCORES_1
+    }
+}
+#[doc = "Possible values of the field `DCOEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DCOENR {
+    #[doc = "DCO is on if it is used as a source for MCLK, HSMCLK , or SMCLK and clock is requested, otherwise it is disabled."]
+    DCOEN_0,
+    #[doc = "DCO is on"]
+    DCOEN_1,
+}
+impl DCOENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            DCOENR::DCOEN_0 => false,
+            DCOENR::DCOEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> DCOENR {
+        match value {
+            false => DCOENR::DCOEN_0,
+            true => DCOENR::DCOEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DCOEN_0`"]
+    #[inline]
+    pub fn is_dcoen_0(&self) -> bool {
+        *self == DCOENR::DCOEN_0
+    }
+    #[doc = "Checks if the value of the field is `DCOEN_1`"]
+    #[inline]
+    pub fn is_dcoen_1(&self) -> bool {
+        *self == DCOENR::DCOEN_1
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DCOTUNEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DCOTUNEW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `DCORSEL`"]
+pub enum DCORSELW {
+    #[doc = "Nominal DCO Frequency Range (MHz): 1 to 2"]
+    DCORSEL_0,
+    #[doc = "Nominal DCO Frequency Range (MHz): 2 to 4"]
+    DCORSEL_1,
+    #[doc = "Nominal DCO Frequency Range (MHz): 4 to 8"]
+    DCORSEL_2,
+    #[doc = "Nominal DCO Frequency Range (MHz): 8 to 16"]
+    DCORSEL_3,
+    #[doc = "Nominal DCO Frequency Range (MHz): 16 to 32"]
+    DCORSEL_4,
+    #[doc = "Nominal DCO Frequency Range (MHz): 32 to 64"]
+    DCORSEL_5,
+}
+impl DCORSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            DCORSELW::DCORSEL_0 => 0,
+            DCORSELW::DCORSEL_1 => 1,
+            DCORSELW::DCORSEL_2 => 2,
+            DCORSELW::DCORSEL_3 => 3,
+            DCORSELW::DCORSEL_4 => 4,
+            DCORSELW::DCORSEL_5 => 5,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DCORSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DCORSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: DCORSELW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "Nominal DCO Frequency Range (MHz): 1 to 2"]
+    #[inline]
+    pub fn dcorsel_0(self) -> &'a mut W {
+        self.variant(DCORSELW::DCORSEL_0)
+    }
+    #[doc = "Nominal DCO Frequency Range (MHz): 2 to 4"]
+    #[inline]
+    pub fn dcorsel_1(self) -> &'a mut W {
+        self.variant(DCORSELW::DCORSEL_1)
+    }
+    #[doc = "Nominal DCO Frequency Range (MHz): 4 to 8"]
+    #[inline]
+    pub fn dcorsel_2(self) -> &'a mut W {
+        self.variant(DCORSELW::DCORSEL_2)
+    }
+    #[doc = "Nominal DCO Frequency Range (MHz): 8 to 16"]
+    #[inline]
+    pub fn dcorsel_3(self) -> &'a mut W {
+        self.variant(DCORSELW::DCORSEL_3)
+    }
+    #[doc = "Nominal DCO Frequency Range (MHz): 16 to 32"]
+    #[inline]
+    pub fn dcorsel_4(self) -> &'a mut W {
+        self.variant(DCORSELW::DCORSEL_4)
+    }
+    #[doc = "Nominal DCO Frequency Range (MHz): 32 to 64"]
+    #[inline]
+    pub fn dcorsel_5(self) -> &'a mut W {
+        self.variant(DCORSELW::DCORSEL_5)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 16;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `DCORES`"]
+pub enum DCORESW {
+    #[doc = "Internal resistor mode"]
+    DCORES_0,
+    #[doc = "External resistor mode"]
+    DCORES_1,
+}
+impl DCORESW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            DCORESW::DCORES_0 => false,
+            DCORESW::DCORES_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DCORESW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DCORESW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: DCORESW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Internal resistor mode"]
+    #[inline]
+    pub fn dcores_0(self) -> &'a mut W {
+        self.variant(DCORESW::DCORES_0)
+    }
+    #[doc = "External resistor mode"]
+    #[inline]
+    pub fn dcores_1(self) -> &'a mut W {
+        self.variant(DCORESW::DCORES_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 22;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `DCOEN`"]
+pub enum DCOENW {
+    #[doc = "DCO is on if it is used as a source for MCLK, HSMCLK , or SMCLK and clock is requested, otherwise it is disabled."]
+    DCOEN_0,
+    #[doc = "DCO is on"]
+    DCOEN_1,
+}
+impl DCOENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            DCOENW::DCOEN_0 => false,
+            DCOENW::DCOEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DCOENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DCOENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: DCOENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "DCO is on if it is used as a source for MCLK, HSMCLK , or SMCLK and clock is requested, otherwise it is disabled."]
+    #[inline]
+    pub fn dcoen_0(self) -> &'a mut W {
+        self.variant(DCOENW::DCOEN_0)
+    }
+    #[doc = "DCO is on"]
+    #[inline]
+    pub fn dcoen_1(self) -> &'a mut W {
+        self.variant(DCOENW::DCOEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 23;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - DCO frequency tuning select"]
+    #[inline]
+    pub fn dcotune(&self) -> DCOTUNER {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        DCOTUNER { bits }
+    }
+    #[doc = "Bits 16:18 - DCO frequency range select"]
+    #[inline]
+    pub fn dcorsel(&self) -> DCORSELR {
+        DCORSELR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 22 - Enables the DCO external resistor mode"]
+    #[inline]
+    pub fn dcores(&self) -> DCORESR {
+        DCORESR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 22;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 23 - Enables the DCO oscillator"]
+    #[inline]
+    pub fn dcoen(&self) -> DCOENR {
+        DCOENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 23;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 65536 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:9 - DCO frequency tuning select"]
+    #[inline]
+    pub fn dcotune(&mut self) -> _DCOTUNEW {
+        _DCOTUNEW { w: self }
+    }
+    #[doc = "Bits 16:18 - DCO frequency range select"]
+    #[inline]
+    pub fn dcorsel(&mut self) -> _DCORSELW {
+        _DCORSELW { w: self }
+    }
+    #[doc = "Bit 22 - Enables the DCO external resistor mode"]
+    #[inline]
+    pub fn dcores(&mut self) -> _DCORESW {
+        _DCORESW { w: self }
+    }
+    #[doc = "Bit 23 - Enables the DCO oscillator"]
+    #[inline]
+    pub fn dcoen(&mut self) -> _DCOENW {
+        _DCOENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/cs/csctl1.rs b/example-source/msp432p401r/src/cs/csctl1.rs
new file mode 100644
index 0000000..b579484
--- /dev/null
+++ b/example-source/msp432p401r/src/cs/csctl1.rs
@@ -0,0 +1,1611 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CSCTL1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `SELM`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SELMR {
+    #[doc = "when LFXT available, otherwise REFOCLK"]
+    SELM_0,
+    #[doc = "undocumented"]
+    SELM_1,
+    #[doc = "undocumented"]
+    SELM_2,
+    #[doc = "undocumented"]
+    SELM_3,
+    #[doc = "undocumented"]
+    SELM_4,
+    #[doc = "when HFXT available, otherwise DCOCLK"]
+    SELM_5,
+    #[doc = "when HFXT2 available, otherwise DCOCLK"]
+    SELM_6,
+    #[doc = "for future use. Defaults to DCOCLK. Not recommended for use\r\r\nto ensure future compatibilities."]
+    SELM_7,
+}
+impl SELMR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            SELMR::SELM_0 => 0,
+            SELMR::SELM_1 => 1,
+            SELMR::SELM_2 => 2,
+            SELMR::SELM_3 => 3,
+            SELMR::SELM_4 => 4,
+            SELMR::SELM_5 => 5,
+            SELMR::SELM_6 => 6,
+            SELMR::SELM_7 => 7,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> SELMR {
+        match value {
+            0 => SELMR::SELM_0,
+            1 => SELMR::SELM_1,
+            2 => SELMR::SELM_2,
+            3 => SELMR::SELM_3,
+            4 => SELMR::SELM_4,
+            5 => SELMR::SELM_5,
+            6 => SELMR::SELM_6,
+            7 => SELMR::SELM_7,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `SELM_0`"]
+    #[inline]
+    pub fn is_selm_0(&self) -> bool {
+        *self == SELMR::SELM_0
+    }
+    #[doc = "Checks if the value of the field is `SELM_1`"]
+    #[inline]
+    pub fn is_selm_1(&self) -> bool {
+        *self == SELMR::SELM_1
+    }
+    #[doc = "Checks if the value of the field is `SELM_2`"]
+    #[inline]
+    pub fn is_selm_2(&self) -> bool {
+        *self == SELMR::SELM_2
+    }
+    #[doc = "Checks if the value of the field is `SELM_3`"]
+    #[inline]
+    pub fn is_selm_3(&self) -> bool {
+        *self == SELMR::SELM_3
+    }
+    #[doc = "Checks if the value of the field is `SELM_4`"]
+    #[inline]
+    pub fn is_selm_4(&self) -> bool {
+        *self == SELMR::SELM_4
+    }
+    #[doc = "Checks if the value of the field is `SELM_5`"]
+    #[inline]
+    pub fn is_selm_5(&self) -> bool {
+        *self == SELMR::SELM_5
+    }
+    #[doc = "Checks if the value of the field is `SELM_6`"]
+    #[inline]
+    pub fn is_selm_6(&self) -> bool {
+        *self == SELMR::SELM_6
+    }
+    #[doc = "Checks if the value of the field is `SELM_7`"]
+    #[inline]
+    pub fn is_selm_7(&self) -> bool {
+        *self == SELMR::SELM_7
+    }
+}
+#[doc = "Possible values of the field `SELS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SELSR {
+    #[doc = "when LFXT available, otherwise REFOCLK"]
+    SELS_0,
+    #[doc = "undocumented"]
+    SELS_1,
+    #[doc = "undocumented"]
+    SELS_2,
+    #[doc = "undocumented"]
+    SELS_3,
+    #[doc = "undocumented"]
+    SELS_4,
+    #[doc = "when HFXT available, otherwise DCOCLK"]
+    SELS_5,
+    #[doc = "when HFXT2 available, otherwise DCOCLK"]
+    SELS_6,
+    #[doc = "for furture use. Defaults to DCOCLK. Do not use to ensure future compatibilities."]
+    SELS_7,
+}
+impl SELSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            SELSR::SELS_0 => 0,
+            SELSR::SELS_1 => 1,
+            SELSR::SELS_2 => 2,
+            SELSR::SELS_3 => 3,
+            SELSR::SELS_4 => 4,
+            SELSR::SELS_5 => 5,
+            SELSR::SELS_6 => 6,
+            SELSR::SELS_7 => 7,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> SELSR {
+        match value {
+            0 => SELSR::SELS_0,
+            1 => SELSR::SELS_1,
+            2 => SELSR::SELS_2,
+            3 => SELSR::SELS_3,
+            4 => SELSR::SELS_4,
+            5 => SELSR::SELS_5,
+            6 => SELSR::SELS_6,
+            7 => SELSR::SELS_7,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `SELS_0`"]
+    #[inline]
+    pub fn is_sels_0(&self) -> bool {
+        *self == SELSR::SELS_0
+    }
+    #[doc = "Checks if the value of the field is `SELS_1`"]
+    #[inline]
+    pub fn is_sels_1(&self) -> bool {
+        *self == SELSR::SELS_1
+    }
+    #[doc = "Checks if the value of the field is `SELS_2`"]
+    #[inline]
+    pub fn is_sels_2(&self) -> bool {
+        *self == SELSR::SELS_2
+    }
+    #[doc = "Checks if the value of the field is `SELS_3`"]
+    #[inline]
+    pub fn is_sels_3(&self) -> bool {
+        *self == SELSR::SELS_3
+    }
+    #[doc = "Checks if the value of the field is `SELS_4`"]
+    #[inline]
+    pub fn is_sels_4(&self) -> bool {
+        *self == SELSR::SELS_4
+    }
+    #[doc = "Checks if the value of the field is `SELS_5`"]
+    #[inline]
+    pub fn is_sels_5(&self) -> bool {
+        *self == SELSR::SELS_5
+    }
+    #[doc = "Checks if the value of the field is `SELS_6`"]
+    #[inline]
+    pub fn is_sels_6(&self) -> bool {
+        *self == SELSR::SELS_6
+    }
+    #[doc = "Checks if the value of the field is `SELS_7`"]
+    #[inline]
+    pub fn is_sels_7(&self) -> bool {
+        *self == SELSR::SELS_7
+    }
+}
+#[doc = "Possible values of the field `SELA`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SELAR {
+    #[doc = "when LFXT available, otherwise REFOCLK"]
+    SELA_0,
+    #[doc = "undocumented"]
+    SELA_1,
+    #[doc = "undocumented"]
+    SELA_2,
+    #[doc = "for future use. Defaults to REFOCLK. Not recommended\r\r\nfor use to ensure future compatibilities."]
+    SELA_3,
+    #[doc = "for future use. Defaults to REFOCLK. Not recommended\r\r\nfor use to ensure future compatibilities."]
+    SELA_4,
+    #[doc = "for future use. Defaults to REFOCLK. Not recommended\r\r\nfor use to ensure future compatibilities."]
+    SELA_5,
+    #[doc = "for future use. Defaults to REFOCLK. Not recommended\r\r\nfor use to ensure future compatibilities."]
+    SELA_6,
+    #[doc = "for future use. Defaults to REFOCLK. Not recommended\r\r\nfor use to ensure future compatibilities."]
+    SELA_7,
+}
+impl SELAR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            SELAR::SELA_0 => 0,
+            SELAR::SELA_1 => 1,
+            SELAR::SELA_2 => 2,
+            SELAR::SELA_3 => 3,
+            SELAR::SELA_4 => 4,
+            SELAR::SELA_5 => 5,
+            SELAR::SELA_6 => 6,
+            SELAR::SELA_7 => 7,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> SELAR {
+        match value {
+            0 => SELAR::SELA_0,
+            1 => SELAR::SELA_1,
+            2 => SELAR::SELA_2,
+            3 => SELAR::SELA_3,
+            4 => SELAR::SELA_4,
+            5 => SELAR::SELA_5,
+            6 => SELAR::SELA_6,
+            7 => SELAR::SELA_7,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `SELA_0`"]
+    #[inline]
+    pub fn is_sela_0(&self) -> bool {
+        *self == SELAR::SELA_0
+    }
+    #[doc = "Checks if the value of the field is `SELA_1`"]
+    #[inline]
+    pub fn is_sela_1(&self) -> bool {
+        *self == SELAR::SELA_1
+    }
+    #[doc = "Checks if the value of the field is `SELA_2`"]
+    #[inline]
+    pub fn is_sela_2(&self) -> bool {
+        *self == SELAR::SELA_2
+    }
+    #[doc = "Checks if the value of the field is `SELA_3`"]
+    #[inline]
+    pub fn is_sela_3(&self) -> bool {
+        *self == SELAR::SELA_3
+    }
+    #[doc = "Checks if the value of the field is `SELA_4`"]
+    #[inline]
+    pub fn is_sela_4(&self) -> bool {
+        *self == SELAR::SELA_4
+    }
+    #[doc = "Checks if the value of the field is `SELA_5`"]
+    #[inline]
+    pub fn is_sela_5(&self) -> bool {
+        *self == SELAR::SELA_5
+    }
+    #[doc = "Checks if the value of the field is `SELA_6`"]
+    #[inline]
+    pub fn is_sela_6(&self) -> bool {
+        *self == SELAR::SELA_6
+    }
+    #[doc = "Checks if the value of the field is `SELA_7`"]
+    #[inline]
+    pub fn is_sela_7(&self) -> bool {
+        *self == SELAR::SELA_7
+    }
+}
+#[doc = "Possible values of the field `SELB`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SELBR {
+    #[doc = "LFXTCLK"]
+    SELB_0,
+    #[doc = "REFOCLK"]
+    SELB_1,
+}
+impl SELBR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            SELBR::SELB_0 => false,
+            SELBR::SELB_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> SELBR {
+        match value {
+            false => SELBR::SELB_0,
+            true => SELBR::SELB_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SELB_0`"]
+    #[inline]
+    pub fn is_selb_0(&self) -> bool {
+        *self == SELBR::SELB_0
+    }
+    #[doc = "Checks if the value of the field is `SELB_1`"]
+    #[inline]
+    pub fn is_selb_1(&self) -> bool {
+        *self == SELBR::SELB_1
+    }
+}
+#[doc = "Possible values of the field `DIVM`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DIVMR {
+    #[doc = "f(MCLK)/1"]
+    DIVM_0,
+    #[doc = "f(MCLK)/2"]
+    DIVM_1,
+    #[doc = "f(MCLK)/4"]
+    DIVM_2,
+    #[doc = "f(MCLK)/8"]
+    DIVM_3,
+    #[doc = "f(MCLK)/16"]
+    DIVM_4,
+    #[doc = "f(MCLK)/32"]
+    DIVM_5,
+    #[doc = "f(MCLK)/64"]
+    DIVM_6,
+    #[doc = "f(MCLK)/128"]
+    DIVM_7,
+}
+impl DIVMR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            DIVMR::DIVM_0 => 0,
+            DIVMR::DIVM_1 => 1,
+            DIVMR::DIVM_2 => 2,
+            DIVMR::DIVM_3 => 3,
+            DIVMR::DIVM_4 => 4,
+            DIVMR::DIVM_5 => 5,
+            DIVMR::DIVM_6 => 6,
+            DIVMR::DIVM_7 => 7,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> DIVMR {
+        match value {
+            0 => DIVMR::DIVM_0,
+            1 => DIVMR::DIVM_1,
+            2 => DIVMR::DIVM_2,
+            3 => DIVMR::DIVM_3,
+            4 => DIVMR::DIVM_4,
+            5 => DIVMR::DIVM_5,
+            6 => DIVMR::DIVM_6,
+            7 => DIVMR::DIVM_7,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `DIVM_0`"]
+    #[inline]
+    pub fn is_divm_0(&self) -> bool {
+        *self == DIVMR::DIVM_0
+    }
+    #[doc = "Checks if the value of the field is `DIVM_1`"]
+    #[inline]
+    pub fn is_divm_1(&self) -> bool {
+        *self == DIVMR::DIVM_1
+    }
+    #[doc = "Checks if the value of the field is `DIVM_2`"]
+    #[inline]
+    pub fn is_divm_2(&self) -> bool {
+        *self == DIVMR::DIVM_2
+    }
+    #[doc = "Checks if the value of the field is `DIVM_3`"]
+    #[inline]
+    pub fn is_divm_3(&self) -> bool {
+        *self == DIVMR::DIVM_3
+    }
+    #[doc = "Checks if the value of the field is `DIVM_4`"]
+    #[inline]
+    pub fn is_divm_4(&self) -> bool {
+        *self == DIVMR::DIVM_4
+    }
+    #[doc = "Checks if the value of the field is `DIVM_5`"]
+    #[inline]
+    pub fn is_divm_5(&self) -> bool {
+        *self == DIVMR::DIVM_5
+    }
+    #[doc = "Checks if the value of the field is `DIVM_6`"]
+    #[inline]
+    pub fn is_divm_6(&self) -> bool {
+        *self == DIVMR::DIVM_6
+    }
+    #[doc = "Checks if the value of the field is `DIVM_7`"]
+    #[inline]
+    pub fn is_divm_7(&self) -> bool {
+        *self == DIVMR::DIVM_7
+    }
+}
+#[doc = "Possible values of the field `DIVHS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DIVHSR {
+    #[doc = "f(HSMCLK)/1"]
+    DIVHS_0,
+    #[doc = "f(HSMCLK)/2"]
+    DIVHS_1,
+    #[doc = "f(HSMCLK)/4"]
+    DIVHS_2,
+    #[doc = "f(HSMCLK)/8"]
+    DIVHS_3,
+    #[doc = "f(HSMCLK)/16"]
+    DIVHS_4,
+    #[doc = "f(HSMCLK)/32"]
+    DIVHS_5,
+    #[doc = "f(HSMCLK)/64"]
+    DIVHS_6,
+    #[doc = "f(HSMCLK)/128"]
+    DIVHS_7,
+}
+impl DIVHSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            DIVHSR::DIVHS_0 => 0,
+            DIVHSR::DIVHS_1 => 1,
+            DIVHSR::DIVHS_2 => 2,
+            DIVHSR::DIVHS_3 => 3,
+            DIVHSR::DIVHS_4 => 4,
+            DIVHSR::DIVHS_5 => 5,
+            DIVHSR::DIVHS_6 => 6,
+            DIVHSR::DIVHS_7 => 7,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> DIVHSR {
+        match value {
+            0 => DIVHSR::DIVHS_0,
+            1 => DIVHSR::DIVHS_1,
+            2 => DIVHSR::DIVHS_2,
+            3 => DIVHSR::DIVHS_3,
+            4 => DIVHSR::DIVHS_4,
+            5 => DIVHSR::DIVHS_5,
+            6 => DIVHSR::DIVHS_6,
+            7 => DIVHSR::DIVHS_7,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `DIVHS_0`"]
+    #[inline]
+    pub fn is_divhs_0(&self) -> bool {
+        *self == DIVHSR::DIVHS_0
+    }
+    #[doc = "Checks if the value of the field is `DIVHS_1`"]
+    #[inline]
+    pub fn is_divhs_1(&self) -> bool {
+        *self == DIVHSR::DIVHS_1
+    }
+    #[doc = "Checks if the value of the field is `DIVHS_2`"]
+    #[inline]
+    pub fn is_divhs_2(&self) -> bool {
+        *self == DIVHSR::DIVHS_2
+    }
+    #[doc = "Checks if the value of the field is `DIVHS_3`"]
+    #[inline]
+    pub fn is_divhs_3(&self) -> bool {
+        *self == DIVHSR::DIVHS_3
+    }
+    #[doc = "Checks if the value of the field is `DIVHS_4`"]
+    #[inline]
+    pub fn is_divhs_4(&self) -> bool {
+        *self == DIVHSR::DIVHS_4
+    }
+    #[doc = "Checks if the value of the field is `DIVHS_5`"]
+    #[inline]
+    pub fn is_divhs_5(&self) -> bool {
+        *self == DIVHSR::DIVHS_5
+    }
+    #[doc = "Checks if the value of the field is `DIVHS_6`"]
+    #[inline]
+    pub fn is_divhs_6(&self) -> bool {
+        *self == DIVHSR::DIVHS_6
+    }
+    #[doc = "Checks if the value of the field is `DIVHS_7`"]
+    #[inline]
+    pub fn is_divhs_7(&self) -> bool {
+        *self == DIVHSR::DIVHS_7
+    }
+}
+#[doc = "Possible values of the field `DIVA`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DIVAR {
+    #[doc = "f(ACLK)/1"]
+    DIVA_0,
+    #[doc = "f(ACLK)/2"]
+    DIVA_1,
+    #[doc = "f(ACLK)/4"]
+    DIVA_2,
+    #[doc = "f(ACLK)/8"]
+    DIVA_3,
+    #[doc = "f(ACLK)/16"]
+    DIVA_4,
+    #[doc = "f(ACLK)/32"]
+    DIVA_5,
+    #[doc = "f(ACLK)/64"]
+    DIVA_6,
+    #[doc = "f(ACLK)/128"]
+    DIVA_7,
+}
+impl DIVAR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            DIVAR::DIVA_0 => 0,
+            DIVAR::DIVA_1 => 1,
+            DIVAR::DIVA_2 => 2,
+            DIVAR::DIVA_3 => 3,
+            DIVAR::DIVA_4 => 4,
+            DIVAR::DIVA_5 => 5,
+            DIVAR::DIVA_6 => 6,
+            DIVAR::DIVA_7 => 7,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> DIVAR {
+        match value {
+            0 => DIVAR::DIVA_0,
+            1 => DIVAR::DIVA_1,
+            2 => DIVAR::DIVA_2,
+            3 => DIVAR::DIVA_3,
+            4 => DIVAR::DIVA_4,
+            5 => DIVAR::DIVA_5,
+            6 => DIVAR::DIVA_6,
+            7 => DIVAR::DIVA_7,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `DIVA_0`"]
+    #[inline]
+    pub fn is_diva_0(&self) -> bool {
+        *self == DIVAR::DIVA_0
+    }
+    #[doc = "Checks if the value of the field is `DIVA_1`"]
+    #[inline]
+    pub fn is_diva_1(&self) -> bool {
+        *self == DIVAR::DIVA_1
+    }
+    #[doc = "Checks if the value of the field is `DIVA_2`"]
+    #[inline]
+    pub fn is_diva_2(&self) -> bool {
+        *self == DIVAR::DIVA_2
+    }
+    #[doc = "Checks if the value of the field is `DIVA_3`"]
+    #[inline]
+    pub fn is_diva_3(&self) -> bool {
+        *self == DIVAR::DIVA_3
+    }
+    #[doc = "Checks if the value of the field is `DIVA_4`"]
+    #[inline]
+    pub fn is_diva_4(&self) -> bool {
+        *self == DIVAR::DIVA_4
+    }
+    #[doc = "Checks if the value of the field is `DIVA_5`"]
+    #[inline]
+    pub fn is_diva_5(&self) -> bool {
+        *self == DIVAR::DIVA_5
+    }
+    #[doc = "Checks if the value of the field is `DIVA_6`"]
+    #[inline]
+    pub fn is_diva_6(&self) -> bool {
+        *self == DIVAR::DIVA_6
+    }
+    #[doc = "Checks if the value of the field is `DIVA_7`"]
+    #[inline]
+    pub fn is_diva_7(&self) -> bool {
+        *self == DIVAR::DIVA_7
+    }
+}
+#[doc = "Possible values of the field `DIVS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DIVSR {
+    #[doc = "f(SMCLK)/1"]
+    DIVS_0,
+    #[doc = "f(SMCLK)/2"]
+    DIVS_1,
+    #[doc = "f(SMCLK)/4"]
+    DIVS_2,
+    #[doc = "f(SMCLK)/8"]
+    DIVS_3,
+    #[doc = "f(SMCLK)/16"]
+    DIVS_4,
+    #[doc = "f(SMCLK)/32"]
+    DIVS_5,
+    #[doc = "f(SMCLK)/64"]
+    DIVS_6,
+    #[doc = "f(SMCLK)/128"]
+    DIVS_7,
+}
+impl DIVSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            DIVSR::DIVS_0 => 0,
+            DIVSR::DIVS_1 => 1,
+            DIVSR::DIVS_2 => 2,
+            DIVSR::DIVS_3 => 3,
+            DIVSR::DIVS_4 => 4,
+            DIVSR::DIVS_5 => 5,
+            DIVSR::DIVS_6 => 6,
+            DIVSR::DIVS_7 => 7,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> DIVSR {
+        match value {
+            0 => DIVSR::DIVS_0,
+            1 => DIVSR::DIVS_1,
+            2 => DIVSR::DIVS_2,
+            3 => DIVSR::DIVS_3,
+            4 => DIVSR::DIVS_4,
+            5 => DIVSR::DIVS_5,
+            6 => DIVSR::DIVS_6,
+            7 => DIVSR::DIVS_7,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `DIVS_0`"]
+    #[inline]
+    pub fn is_divs_0(&self) -> bool {
+        *self == DIVSR::DIVS_0
+    }
+    #[doc = "Checks if the value of the field is `DIVS_1`"]
+    #[inline]
+    pub fn is_divs_1(&self) -> bool {
+        *self == DIVSR::DIVS_1
+    }
+    #[doc = "Checks if the value of the field is `DIVS_2`"]
+    #[inline]
+    pub fn is_divs_2(&self) -> bool {
+        *self == DIVSR::DIVS_2
+    }
+    #[doc = "Checks if the value of the field is `DIVS_3`"]
+    #[inline]
+    pub fn is_divs_3(&self) -> bool {
+        *self == DIVSR::DIVS_3
+    }
+    #[doc = "Checks if the value of the field is `DIVS_4`"]
+    #[inline]
+    pub fn is_divs_4(&self) -> bool {
+        *self == DIVSR::DIVS_4
+    }
+    #[doc = "Checks if the value of the field is `DIVS_5`"]
+    #[inline]
+    pub fn is_divs_5(&self) -> bool {
+        *self == DIVSR::DIVS_5
+    }
+    #[doc = "Checks if the value of the field is `DIVS_6`"]
+    #[inline]
+    pub fn is_divs_6(&self) -> bool {
+        *self == DIVSR::DIVS_6
+    }
+    #[doc = "Checks if the value of the field is `DIVS_7`"]
+    #[inline]
+    pub fn is_divs_7(&self) -> bool {
+        *self == DIVSR::DIVS_7
+    }
+}
+#[doc = "Values that can be written to the field `SELM`"]
+pub enum SELMW {
+    #[doc = "when LFXT available, otherwise REFOCLK"]
+    SELM_0,
+    #[doc = "`1`"]
+    SELM_1,
+    #[doc = "`10`"]
+    SELM_2,
+    #[doc = "`11`"]
+    SELM_3,
+    #[doc = "`100`"]
+    SELM_4,
+    #[doc = "when HFXT available, otherwise DCOCLK"]
+    SELM_5,
+    #[doc = "when HFXT2 available, otherwise DCOCLK"]
+    SELM_6,
+    #[doc = "for future use. Defaults to DCOCLK. Not recommended for use\r\r\nto ensure future compatibilities."]
+    SELM_7,
+}
+impl SELMW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            SELMW::SELM_0 => 0,
+            SELMW::SELM_1 => 1,
+            SELMW::SELM_2 => 2,
+            SELMW::SELM_3 => 3,
+            SELMW::SELM_4 => 4,
+            SELMW::SELM_5 => 5,
+            SELMW::SELM_6 => 6,
+            SELMW::SELM_7 => 7,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SELMW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SELMW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SELMW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "when LFXT available, otherwise REFOCLK"]
+    #[inline]
+    pub fn selm_0(self) -> &'a mut W {
+        self.variant(SELMW::SELM_0)
+    }
+    #[doc = "`1`"]
+    #[inline]
+    pub fn selm_1(self) -> &'a mut W {
+        self.variant(SELMW::SELM_1)
+    }
+    #[doc = "`10`"]
+    #[inline]
+    pub fn selm_2(self) -> &'a mut W {
+        self.variant(SELMW::SELM_2)
+    }
+    #[doc = "`11`"]
+    #[inline]
+    pub fn selm_3(self) -> &'a mut W {
+        self.variant(SELMW::SELM_3)
+    }
+    #[doc = "`100`"]
+    #[inline]
+    pub fn selm_4(self) -> &'a mut W {
+        self.variant(SELMW::SELM_4)
+    }
+    #[doc = "when HFXT available, otherwise DCOCLK"]
+    #[inline]
+    pub fn selm_5(self) -> &'a mut W {
+        self.variant(SELMW::SELM_5)
+    }
+    #[doc = "when HFXT2 available, otherwise DCOCLK"]
+    #[inline]
+    pub fn selm_6(self) -> &'a mut W {
+        self.variant(SELMW::SELM_6)
+    }
+    #[doc = "for future use. Defaults to DCOCLK. Not recommended for use to ensure future compatibilities."]
+    #[inline]
+    pub fn selm_7(self) -> &'a mut W {
+        self.variant(SELMW::SELM_7)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `SELS`"]
+pub enum SELSW {
+    #[doc = "when LFXT available, otherwise REFOCLK"]
+    SELS_0,
+    #[doc = "`1`"]
+    SELS_1,
+    #[doc = "`10`"]
+    SELS_2,
+    #[doc = "`11`"]
+    SELS_3,
+    #[doc = "`100`"]
+    SELS_4,
+    #[doc = "when HFXT available, otherwise DCOCLK"]
+    SELS_5,
+    #[doc = "when HFXT2 available, otherwise DCOCLK"]
+    SELS_6,
+    #[doc = "for furture use. Defaults to DCOCLK. Do not use to ensure future compatibilities."]
+    SELS_7,
+}
+impl SELSW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            SELSW::SELS_0 => 0,
+            SELSW::SELS_1 => 1,
+            SELSW::SELS_2 => 2,
+            SELSW::SELS_3 => 3,
+            SELSW::SELS_4 => 4,
+            SELSW::SELS_5 => 5,
+            SELSW::SELS_6 => 6,
+            SELSW::SELS_7 => 7,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SELSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SELSW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SELSW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "when LFXT available, otherwise REFOCLK"]
+    #[inline]
+    pub fn sels_0(self) -> &'a mut W {
+        self.variant(SELSW::SELS_0)
+    }
+    #[doc = "`1`"]
+    #[inline]
+    pub fn sels_1(self) -> &'a mut W {
+        self.variant(SELSW::SELS_1)
+    }
+    #[doc = "`10`"]
+    #[inline]
+    pub fn sels_2(self) -> &'a mut W {
+        self.variant(SELSW::SELS_2)
+    }
+    #[doc = "`11`"]
+    #[inline]
+    pub fn sels_3(self) -> &'a mut W {
+        self.variant(SELSW::SELS_3)
+    }
+    #[doc = "`100`"]
+    #[inline]
+    pub fn sels_4(self) -> &'a mut W {
+        self.variant(SELSW::SELS_4)
+    }
+    #[doc = "when HFXT available, otherwise DCOCLK"]
+    #[inline]
+    pub fn sels_5(self) -> &'a mut W {
+        self.variant(SELSW::SELS_5)
+    }
+    #[doc = "when HFXT2 available, otherwise DCOCLK"]
+    #[inline]
+    pub fn sels_6(self) -> &'a mut W {
+        self.variant(SELSW::SELS_6)
+    }
+    #[doc = "for furture use. Defaults to DCOCLK. Do not use to ensure future compatibilities."]
+    #[inline]
+    pub fn sels_7(self) -> &'a mut W {
+        self.variant(SELSW::SELS_7)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `SELA`"]
+pub enum SELAW {
+    #[doc = "when LFXT available, otherwise REFOCLK"]
+    SELA_0,
+    #[doc = "`1`"]
+    SELA_1,
+    #[doc = "`10`"]
+    SELA_2,
+    #[doc = "for future use. Defaults to REFOCLK. Not recommended\r\r\nfor use to ensure future compatibilities."]
+    SELA_3,
+    #[doc = "for future use. Defaults to REFOCLK. Not recommended\r\r\nfor use to ensure future compatibilities."]
+    SELA_4,
+    #[doc = "for future use. Defaults to REFOCLK. Not recommended\r\r\nfor use to ensure future compatibilities."]
+    SELA_5,
+    #[doc = "for future use. Defaults to REFOCLK. Not recommended\r\r\nfor use to ensure future compatibilities."]
+    SELA_6,
+    #[doc = "for future use. Defaults to REFOCLK. Not recommended\r\r\nfor use to ensure future compatibilities."]
+    SELA_7,
+}
+impl SELAW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            SELAW::SELA_0 => 0,
+            SELAW::SELA_1 => 1,
+            SELAW::SELA_2 => 2,
+            SELAW::SELA_3 => 3,
+            SELAW::SELA_4 => 4,
+            SELAW::SELA_5 => 5,
+            SELAW::SELA_6 => 6,
+            SELAW::SELA_7 => 7,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SELAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SELAW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SELAW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "when LFXT available, otherwise REFOCLK"]
+    #[inline]
+    pub fn sela_0(self) -> &'a mut W {
+        self.variant(SELAW::SELA_0)
+    }
+    #[doc = "`1`"]
+    #[inline]
+    pub fn sela_1(self) -> &'a mut W {
+        self.variant(SELAW::SELA_1)
+    }
+    #[doc = "`10`"]
+    #[inline]
+    pub fn sela_2(self) -> &'a mut W {
+        self.variant(SELAW::SELA_2)
+    }
+    #[doc = "for future use. Defaults to REFOCLK. Not recommended for use to ensure future compatibilities."]
+    #[inline]
+    pub fn sela_3(self) -> &'a mut W {
+        self.variant(SELAW::SELA_3)
+    }
+    #[doc = "for future use. Defaults to REFOCLK. Not recommended for use to ensure future compatibilities."]
+    #[inline]
+    pub fn sela_4(self) -> &'a mut W {
+        self.variant(SELAW::SELA_4)
+    }
+    #[doc = "for future use. Defaults to REFOCLK. Not recommended for use to ensure future compatibilities."]
+    #[inline]
+    pub fn sela_5(self) -> &'a mut W {
+        self.variant(SELAW::SELA_5)
+    }
+    #[doc = "for future use. Defaults to REFOCLK. Not recommended for use to ensure future compatibilities."]
+    #[inline]
+    pub fn sela_6(self) -> &'a mut W {
+        self.variant(SELAW::SELA_6)
+    }
+    #[doc = "for future use. Defaults to REFOCLK. Not recommended for use to ensure future compatibilities."]
+    #[inline]
+    pub fn sela_7(self) -> &'a mut W {
+        self.variant(SELAW::SELA_7)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `SELB`"]
+pub enum SELBW {
+    #[doc = "LFXTCLK"]
+    SELB_0,
+    #[doc = "REFOCLK"]
+    SELB_1,
+}
+impl SELBW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            SELBW::SELB_0 => false,
+            SELBW::SELB_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SELBW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SELBW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SELBW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "LFXTCLK"]
+    #[inline]
+    pub fn selb_0(self) -> &'a mut W {
+        self.variant(SELBW::SELB_0)
+    }
+    #[doc = "REFOCLK"]
+    #[inline]
+    pub fn selb_1(self) -> &'a mut W {
+        self.variant(SELBW::SELB_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `DIVM`"]
+pub enum DIVMW {
+    #[doc = "f(MCLK)/1"]
+    DIVM_0,
+    #[doc = "f(MCLK)/2"]
+    DIVM_1,
+    #[doc = "f(MCLK)/4"]
+    DIVM_2,
+    #[doc = "f(MCLK)/8"]
+    DIVM_3,
+    #[doc = "f(MCLK)/16"]
+    DIVM_4,
+    #[doc = "f(MCLK)/32"]
+    DIVM_5,
+    #[doc = "f(MCLK)/64"]
+    DIVM_6,
+    #[doc = "f(MCLK)/128"]
+    DIVM_7,
+}
+impl DIVMW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            DIVMW::DIVM_0 => 0,
+            DIVMW::DIVM_1 => 1,
+            DIVMW::DIVM_2 => 2,
+            DIVMW::DIVM_3 => 3,
+            DIVMW::DIVM_4 => 4,
+            DIVMW::DIVM_5 => 5,
+            DIVMW::DIVM_6 => 6,
+            DIVMW::DIVM_7 => 7,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DIVMW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DIVMW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: DIVMW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "f(MCLK)/1"]
+    #[inline]
+    pub fn divm_0(self) -> &'a mut W {
+        self.variant(DIVMW::DIVM_0)
+    }
+    #[doc = "f(MCLK)/2"]
+    #[inline]
+    pub fn divm_1(self) -> &'a mut W {
+        self.variant(DIVMW::DIVM_1)
+    }
+    #[doc = "f(MCLK)/4"]
+    #[inline]
+    pub fn divm_2(self) -> &'a mut W {
+        self.variant(DIVMW::DIVM_2)
+    }
+    #[doc = "f(MCLK)/8"]
+    #[inline]
+    pub fn divm_3(self) -> &'a mut W {
+        self.variant(DIVMW::DIVM_3)
+    }
+    #[doc = "f(MCLK)/16"]
+    #[inline]
+    pub fn divm_4(self) -> &'a mut W {
+        self.variant(DIVMW::DIVM_4)
+    }
+    #[doc = "f(MCLK)/32"]
+    #[inline]
+    pub fn divm_5(self) -> &'a mut W {
+        self.variant(DIVMW::DIVM_5)
+    }
+    #[doc = "f(MCLK)/64"]
+    #[inline]
+    pub fn divm_6(self) -> &'a mut W {
+        self.variant(DIVMW::DIVM_6)
+    }
+    #[doc = "f(MCLK)/128"]
+    #[inline]
+    pub fn divm_7(self) -> &'a mut W {
+        self.variant(DIVMW::DIVM_7)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 16;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `DIVHS`"]
+pub enum DIVHSW {
+    #[doc = "f(HSMCLK)/1"]
+    DIVHS_0,
+    #[doc = "f(HSMCLK)/2"]
+    DIVHS_1,
+    #[doc = "f(HSMCLK)/4"]
+    DIVHS_2,
+    #[doc = "f(HSMCLK)/8"]
+    DIVHS_3,
+    #[doc = "f(HSMCLK)/16"]
+    DIVHS_4,
+    #[doc = "f(HSMCLK)/32"]
+    DIVHS_5,
+    #[doc = "f(HSMCLK)/64"]
+    DIVHS_6,
+    #[doc = "f(HSMCLK)/128"]
+    DIVHS_7,
+}
+impl DIVHSW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            DIVHSW::DIVHS_0 => 0,
+            DIVHSW::DIVHS_1 => 1,
+            DIVHSW::DIVHS_2 => 2,
+            DIVHSW::DIVHS_3 => 3,
+            DIVHSW::DIVHS_4 => 4,
+            DIVHSW::DIVHS_5 => 5,
+            DIVHSW::DIVHS_6 => 6,
+            DIVHSW::DIVHS_7 => 7,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DIVHSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DIVHSW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: DIVHSW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "f(HSMCLK)/1"]
+    #[inline]
+    pub fn divhs_0(self) -> &'a mut W {
+        self.variant(DIVHSW::DIVHS_0)
+    }
+    #[doc = "f(HSMCLK)/2"]
+    #[inline]
+    pub fn divhs_1(self) -> &'a mut W {
+        self.variant(DIVHSW::DIVHS_1)
+    }
+    #[doc = "f(HSMCLK)/4"]
+    #[inline]
+    pub fn divhs_2(self) -> &'a mut W {
+        self.variant(DIVHSW::DIVHS_2)
+    }
+    #[doc = "f(HSMCLK)/8"]
+    #[inline]
+    pub fn divhs_3(self) -> &'a mut W {
+        self.variant(DIVHSW::DIVHS_3)
+    }
+    #[doc = "f(HSMCLK)/16"]
+    #[inline]
+    pub fn divhs_4(self) -> &'a mut W {
+        self.variant(DIVHSW::DIVHS_4)
+    }
+    #[doc = "f(HSMCLK)/32"]
+    #[inline]
+    pub fn divhs_5(self) -> &'a mut W {
+        self.variant(DIVHSW::DIVHS_5)
+    }
+    #[doc = "f(HSMCLK)/64"]
+    #[inline]
+    pub fn divhs_6(self) -> &'a mut W {
+        self.variant(DIVHSW::DIVHS_6)
+    }
+    #[doc = "f(HSMCLK)/128"]
+    #[inline]
+    pub fn divhs_7(self) -> &'a mut W {
+        self.variant(DIVHSW::DIVHS_7)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 20;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `DIVA`"]
+pub enum DIVAW {
+    #[doc = "f(ACLK)/1"]
+    DIVA_0,
+    #[doc = "f(ACLK)/2"]
+    DIVA_1,
+    #[doc = "f(ACLK)/4"]
+    DIVA_2,
+    #[doc = "f(ACLK)/8"]
+    DIVA_3,
+    #[doc = "f(ACLK)/16"]
+    DIVA_4,
+    #[doc = "f(ACLK)/32"]
+    DIVA_5,
+    #[doc = "f(ACLK)/64"]
+    DIVA_6,
+    #[doc = "f(ACLK)/128"]
+    DIVA_7,
+}
+impl DIVAW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            DIVAW::DIVA_0 => 0,
+            DIVAW::DIVA_1 => 1,
+            DIVAW::DIVA_2 => 2,
+            DIVAW::DIVA_3 => 3,
+            DIVAW::DIVA_4 => 4,
+            DIVAW::DIVA_5 => 5,
+            DIVAW::DIVA_6 => 6,
+            DIVAW::DIVA_7 => 7,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DIVAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DIVAW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: DIVAW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "f(ACLK)/1"]
+    #[inline]
+    pub fn diva_0(self) -> &'a mut W {
+        self.variant(DIVAW::DIVA_0)
+    }
+    #[doc = "f(ACLK)/2"]
+    #[inline]
+    pub fn diva_1(self) -> &'a mut W {
+        self.variant(DIVAW::DIVA_1)
+    }
+    #[doc = "f(ACLK)/4"]
+    #[inline]
+    pub fn diva_2(self) -> &'a mut W {
+        self.variant(DIVAW::DIVA_2)
+    }
+    #[doc = "f(ACLK)/8"]
+    #[inline]
+    pub fn diva_3(self) -> &'a mut W {
+        self.variant(DIVAW::DIVA_3)
+    }
+    #[doc = "f(ACLK)/16"]
+    #[inline]
+    pub fn diva_4(self) -> &'a mut W {
+        self.variant(DIVAW::DIVA_4)
+    }
+    #[doc = "f(ACLK)/32"]
+    #[inline]
+    pub fn diva_5(self) -> &'a mut W {
+        self.variant(DIVAW::DIVA_5)
+    }
+    #[doc = "f(ACLK)/64"]
+    #[inline]
+    pub fn diva_6(self) -> &'a mut W {
+        self.variant(DIVAW::DIVA_6)
+    }
+    #[doc = "f(ACLK)/128"]
+    #[inline]
+    pub fn diva_7(self) -> &'a mut W {
+        self.variant(DIVAW::DIVA_7)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 24;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `DIVS`"]
+pub enum DIVSW {
+    #[doc = "f(SMCLK)/1"]
+    DIVS_0,
+    #[doc = "f(SMCLK)/2"]
+    DIVS_1,
+    #[doc = "f(SMCLK)/4"]
+    DIVS_2,
+    #[doc = "f(SMCLK)/8"]
+    DIVS_3,
+    #[doc = "f(SMCLK)/16"]
+    DIVS_4,
+    #[doc = "f(SMCLK)/32"]
+    DIVS_5,
+    #[doc = "f(SMCLK)/64"]
+    DIVS_6,
+    #[doc = "f(SMCLK)/128"]
+    DIVS_7,
+}
+impl DIVSW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            DIVSW::DIVS_0 => 0,
+            DIVSW::DIVS_1 => 1,
+            DIVSW::DIVS_2 => 2,
+            DIVSW::DIVS_3 => 3,
+            DIVSW::DIVS_4 => 4,
+            DIVSW::DIVS_5 => 5,
+            DIVSW::DIVS_6 => 6,
+            DIVSW::DIVS_7 => 7,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DIVSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DIVSW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: DIVSW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "f(SMCLK)/1"]
+    #[inline]
+    pub fn divs_0(self) -> &'a mut W {
+        self.variant(DIVSW::DIVS_0)
+    }
+    #[doc = "f(SMCLK)/2"]
+    #[inline]
+    pub fn divs_1(self) -> &'a mut W {
+        self.variant(DIVSW::DIVS_1)
+    }
+    #[doc = "f(SMCLK)/4"]
+    #[inline]
+    pub fn divs_2(self) -> &'a mut W {
+        self.variant(DIVSW::DIVS_2)
+    }
+    #[doc = "f(SMCLK)/8"]
+    #[inline]
+    pub fn divs_3(self) -> &'a mut W {
+        self.variant(DIVSW::DIVS_3)
+    }
+    #[doc = "f(SMCLK)/16"]
+    #[inline]
+    pub fn divs_4(self) -> &'a mut W {
+        self.variant(DIVSW::DIVS_4)
+    }
+    #[doc = "f(SMCLK)/32"]
+    #[inline]
+    pub fn divs_5(self) -> &'a mut W {
+        self.variant(DIVSW::DIVS_5)
+    }
+    #[doc = "f(SMCLK)/64"]
+    #[inline]
+    pub fn divs_6(self) -> &'a mut W {
+        self.variant(DIVSW::DIVS_6)
+    }
+    #[doc = "f(SMCLK)/128"]
+    #[inline]
+    pub fn divs_7(self) -> &'a mut W {
+        self.variant(DIVSW::DIVS_7)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 28;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:2 - Selects the MCLK source"]
+    #[inline]
+    pub fn selm(&self) -> SELMR {
+        SELMR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 4:6 - Selects the SMCLK and HSMCLK source"]
+    #[inline]
+    pub fn sels(&self) -> SELSR {
+        SELSR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 8:10 - Selects the ACLK source"]
+    #[inline]
+    pub fn sela(&self) -> SELAR {
+        SELAR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 12 - Selects the BCLK source"]
+    #[inline]
+    pub fn selb(&self) -> SELBR {
+        SELBR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 16:18 - MCLK source divider"]
+    #[inline]
+    pub fn divm(&self) -> DIVMR {
+        DIVMR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 20:22 - HSMCLK source divider"]
+    #[inline]
+    pub fn divhs(&self) -> DIVHSR {
+        DIVHSR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 20;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 24:26 - ACLK source divider"]
+    #[inline]
+    pub fn diva(&self) -> DIVAR {
+        DIVAR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 24;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 28:30 - SMCLK source divider"]
+    #[inline]
+    pub fn divs(&self) -> DIVSR {
+        DIVSR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 28;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 51 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:2 - Selects the MCLK source"]
+    #[inline]
+    pub fn selm(&mut self) -> _SELMW {
+        _SELMW { w: self }
+    }
+    #[doc = "Bits 4:6 - Selects the SMCLK and HSMCLK source"]
+    #[inline]
+    pub fn sels(&mut self) -> _SELSW {
+        _SELSW { w: self }
+    }
+    #[doc = "Bits 8:10 - Selects the ACLK source"]
+    #[inline]
+    pub fn sela(&mut self) -> _SELAW {
+        _SELAW { w: self }
+    }
+    #[doc = "Bit 12 - Selects the BCLK source"]
+    #[inline]
+    pub fn selb(&mut self) -> _SELBW {
+        _SELBW { w: self }
+    }
+    #[doc = "Bits 16:18 - MCLK source divider"]
+    #[inline]
+    pub fn divm(&mut self) -> _DIVMW {
+        _DIVMW { w: self }
+    }
+    #[doc = "Bits 20:22 - HSMCLK source divider"]
+    #[inline]
+    pub fn divhs(&mut self) -> _DIVHSW {
+        _DIVHSW { w: self }
+    }
+    #[doc = "Bits 24:26 - ACLK source divider"]
+    #[inline]
+    pub fn diva(&mut self) -> _DIVAW {
+        _DIVAW { w: self }
+    }
+    #[doc = "Bits 28:30 - SMCLK source divider"]
+    #[inline]
+    pub fn divs(&mut self) -> _DIVSW {
+        _DIVSW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/cs/csctl2.rs b/example-source/msp432p401r/src/cs/csctl2.rs
new file mode 100644
index 0000000..598c963
--- /dev/null
+++ b/example-source/msp432p401r/src/cs/csctl2.rs
@@ -0,0 +1,1102 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CSCTL2 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `LFXTDRIVE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LFXTDRIVER {
+    #[doc = "Lowest drive strength and current consumption LFXT oscillator."]
+    LFXTDRIVE_0,
+    #[doc = "Increased drive strength LFXT oscillator."]
+    LFXTDRIVE_1,
+    #[doc = "Increased drive strength LFXT oscillator."]
+    LFXTDRIVE_2,
+    #[doc = "Maximum drive strength and maximum current consumption LFXT oscillator."]
+    LFXTDRIVE_3,
+}
+impl LFXTDRIVER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            LFXTDRIVER::LFXTDRIVE_0 => 0,
+            LFXTDRIVER::LFXTDRIVE_1 => 1,
+            LFXTDRIVER::LFXTDRIVE_2 => 2,
+            LFXTDRIVER::LFXTDRIVE_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> LFXTDRIVER {
+        match value {
+            0 => LFXTDRIVER::LFXTDRIVE_0,
+            1 => LFXTDRIVER::LFXTDRIVE_1,
+            2 => LFXTDRIVER::LFXTDRIVE_2,
+            3 => LFXTDRIVER::LFXTDRIVE_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `LFXTDRIVE_0`"]
+    #[inline]
+    pub fn is_lfxtdrive_0(&self) -> bool {
+        *self == LFXTDRIVER::LFXTDRIVE_0
+    }
+    #[doc = "Checks if the value of the field is `LFXTDRIVE_1`"]
+    #[inline]
+    pub fn is_lfxtdrive_1(&self) -> bool {
+        *self == LFXTDRIVER::LFXTDRIVE_1
+    }
+    #[doc = "Checks if the value of the field is `LFXTDRIVE_2`"]
+    #[inline]
+    pub fn is_lfxtdrive_2(&self) -> bool {
+        *self == LFXTDRIVER::LFXTDRIVE_2
+    }
+    #[doc = "Checks if the value of the field is `LFXTDRIVE_3`"]
+    #[inline]
+    pub fn is_lfxtdrive_3(&self) -> bool {
+        *self == LFXTDRIVER::LFXTDRIVE_3
+    }
+}
+#[doc = "Possible values of the field `LFXTAGCOFF`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LFXTAGCOFFR {
+    #[doc = "AGC enabled."]
+    LFXTAGCOFF_0,
+    #[doc = "AGC disabled."]
+    LFXTAGCOFF_1,
+}
+impl LFXTAGCOFFR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            LFXTAGCOFFR::LFXTAGCOFF_0 => false,
+            LFXTAGCOFFR::LFXTAGCOFF_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> LFXTAGCOFFR {
+        match value {
+            false => LFXTAGCOFFR::LFXTAGCOFF_0,
+            true => LFXTAGCOFFR::LFXTAGCOFF_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `LFXTAGCOFF_0`"]
+    #[inline]
+    pub fn is_lfxtagcoff_0(&self) -> bool {
+        *self == LFXTAGCOFFR::LFXTAGCOFF_0
+    }
+    #[doc = "Checks if the value of the field is `LFXTAGCOFF_1`"]
+    #[inline]
+    pub fn is_lfxtagcoff_1(&self) -> bool {
+        *self == LFXTAGCOFFR::LFXTAGCOFF_1
+    }
+}
+#[doc = "Possible values of the field `LFXT_EN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LFXT_ENR {
+    #[doc = "LFXT is on if it is used as a source for ACLK, MCLK, HSMCLK , or SMCLK\r\r\nand is selected via the port selection and not in bypass mode of operation."]
+    LFXT_EN_0,
+    #[doc = "LFXT is on if LFXT is selected via the port selection and LFXT is not in\r\r\nbypass mode of operation."]
+    LFXT_EN_1,
+}
+impl LFXT_ENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            LFXT_ENR::LFXT_EN_0 => false,
+            LFXT_ENR::LFXT_EN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> LFXT_ENR {
+        match value {
+            false => LFXT_ENR::LFXT_EN_0,
+            true => LFXT_ENR::LFXT_EN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `LFXT_EN_0`"]
+    #[inline]
+    pub fn is_lfxt_en_0(&self) -> bool {
+        *self == LFXT_ENR::LFXT_EN_0
+    }
+    #[doc = "Checks if the value of the field is `LFXT_EN_1`"]
+    #[inline]
+    pub fn is_lfxt_en_1(&self) -> bool {
+        *self == LFXT_ENR::LFXT_EN_1
+    }
+}
+#[doc = "Possible values of the field `LFXTBYPASS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LFXTBYPASSR {
+    #[doc = "LFXT sourced by external crystal."]
+    LFXTBYPASS_0,
+    #[doc = "LFXT sourced by external square wave."]
+    LFXTBYPASS_1,
+}
+impl LFXTBYPASSR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            LFXTBYPASSR::LFXTBYPASS_0 => false,
+            LFXTBYPASSR::LFXTBYPASS_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> LFXTBYPASSR {
+        match value {
+            false => LFXTBYPASSR::LFXTBYPASS_0,
+            true => LFXTBYPASSR::LFXTBYPASS_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `LFXTBYPASS_0`"]
+    #[inline]
+    pub fn is_lfxtbypass_0(&self) -> bool {
+        *self == LFXTBYPASSR::LFXTBYPASS_0
+    }
+    #[doc = "Checks if the value of the field is `LFXTBYPASS_1`"]
+    #[inline]
+    pub fn is_lfxtbypass_1(&self) -> bool {
+        *self == LFXTBYPASSR::LFXTBYPASS_1
+    }
+}
+#[doc = "Possible values of the field `HFXTDRIVE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HFXTDRIVER {
+    #[doc = "To be used for HFXTFREQ setting 000b"]
+    HFXTDRIVE_0,
+    #[doc = "To be used for HFXTFREQ settings 001b to 110b"]
+    HFXTDRIVE_1,
+}
+impl HFXTDRIVER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            HFXTDRIVER::HFXTDRIVE_0 => false,
+            HFXTDRIVER::HFXTDRIVE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> HFXTDRIVER {
+        match value {
+            false => HFXTDRIVER::HFXTDRIVE_0,
+            true => HFXTDRIVER::HFXTDRIVE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `HFXTDRIVE_0`"]
+    #[inline]
+    pub fn is_hfxtdrive_0(&self) -> bool {
+        *self == HFXTDRIVER::HFXTDRIVE_0
+    }
+    #[doc = "Checks if the value of the field is `HFXTDRIVE_1`"]
+    #[inline]
+    pub fn is_hfxtdrive_1(&self) -> bool {
+        *self == HFXTDRIVER::HFXTDRIVE_1
+    }
+}
+#[doc = "Possible values of the field `HFXTFREQ`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HFXTFREQR {
+    #[doc = "1 MHz to 4 MHz"]
+    HFXTFREQ_0,
+    #[doc = ">4 MHz to 8 MHz"]
+    HFXTFREQ_1,
+    #[doc = ">8 MHz to 16 MHz"]
+    HFXTFREQ_2,
+    #[doc = ">16 MHz to 24 MHz"]
+    HFXTFREQ_3,
+    #[doc = ">24 MHz to 32 MHz"]
+    HFXTFREQ_4,
+    #[doc = ">32 MHz to 40 MHz"]
+    HFXTFREQ_5,
+    #[doc = ">40 MHz to 48 MHz"]
+    HFXTFREQ_6,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl HFXTFREQR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            HFXTFREQR::HFXTFREQ_0 => 0,
+            HFXTFREQR::HFXTFREQ_1 => 1,
+            HFXTFREQR::HFXTFREQ_2 => 2,
+            HFXTFREQR::HFXTFREQ_3 => 3,
+            HFXTFREQR::HFXTFREQ_4 => 4,
+            HFXTFREQR::HFXTFREQ_5 => 5,
+            HFXTFREQR::HFXTFREQ_6 => 6,
+            HFXTFREQR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> HFXTFREQR {
+        match value {
+            0 => HFXTFREQR::HFXTFREQ_0,
+            1 => HFXTFREQR::HFXTFREQ_1,
+            2 => HFXTFREQR::HFXTFREQ_2,
+            3 => HFXTFREQR::HFXTFREQ_3,
+            4 => HFXTFREQR::HFXTFREQ_4,
+            5 => HFXTFREQR::HFXTFREQ_5,
+            6 => HFXTFREQR::HFXTFREQ_6,
+            i => HFXTFREQR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `HFXTFREQ_0`"]
+    #[inline]
+    pub fn is_hfxtfreq_0(&self) -> bool {
+        *self == HFXTFREQR::HFXTFREQ_0
+    }
+    #[doc = "Checks if the value of the field is `HFXTFREQ_1`"]
+    #[inline]
+    pub fn is_hfxtfreq_1(&self) -> bool {
+        *self == HFXTFREQR::HFXTFREQ_1
+    }
+    #[doc = "Checks if the value of the field is `HFXTFREQ_2`"]
+    #[inline]
+    pub fn is_hfxtfreq_2(&self) -> bool {
+        *self == HFXTFREQR::HFXTFREQ_2
+    }
+    #[doc = "Checks if the value of the field is `HFXTFREQ_3`"]
+    #[inline]
+    pub fn is_hfxtfreq_3(&self) -> bool {
+        *self == HFXTFREQR::HFXTFREQ_3
+    }
+    #[doc = "Checks if the value of the field is `HFXTFREQ_4`"]
+    #[inline]
+    pub fn is_hfxtfreq_4(&self) -> bool {
+        *self == HFXTFREQR::HFXTFREQ_4
+    }
+    #[doc = "Checks if the value of the field is `HFXTFREQ_5`"]
+    #[inline]
+    pub fn is_hfxtfreq_5(&self) -> bool {
+        *self == HFXTFREQR::HFXTFREQ_5
+    }
+    #[doc = "Checks if the value of the field is `HFXTFREQ_6`"]
+    #[inline]
+    pub fn is_hfxtfreq_6(&self) -> bool {
+        *self == HFXTFREQR::HFXTFREQ_6
+    }
+}
+#[doc = "Possible values of the field `HFXT_EN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HFXT_ENR {
+    #[doc = "HFXT is on if it is used as a source for MCLK, HSMCLK , or SMCLK and is selected via the port selection and not in bypass mode of operation."]
+    HFXT_EN_0,
+    #[doc = "HFXT is on if HFXT is selected via the port selection and HFXT is not in bypass mode of operation."]
+    HFXT_EN_1,
+}
+impl HFXT_ENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            HFXT_ENR::HFXT_EN_0 => false,
+            HFXT_ENR::HFXT_EN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> HFXT_ENR {
+        match value {
+            false => HFXT_ENR::HFXT_EN_0,
+            true => HFXT_ENR::HFXT_EN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `HFXT_EN_0`"]
+    #[inline]
+    pub fn is_hfxt_en_0(&self) -> bool {
+        *self == HFXT_ENR::HFXT_EN_0
+    }
+    #[doc = "Checks if the value of the field is `HFXT_EN_1`"]
+    #[inline]
+    pub fn is_hfxt_en_1(&self) -> bool {
+        *self == HFXT_ENR::HFXT_EN_1
+    }
+}
+#[doc = "Possible values of the field `HFXTBYPASS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HFXTBYPASSR {
+    #[doc = "HFXT sourced by external crystal."]
+    HFXTBYPASS_0,
+    #[doc = "HFXT sourced by external square wave."]
+    HFXTBYPASS_1,
+}
+impl HFXTBYPASSR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            HFXTBYPASSR::HFXTBYPASS_0 => false,
+            HFXTBYPASSR::HFXTBYPASS_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> HFXTBYPASSR {
+        match value {
+            false => HFXTBYPASSR::HFXTBYPASS_0,
+            true => HFXTBYPASSR::HFXTBYPASS_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `HFXTBYPASS_0`"]
+    #[inline]
+    pub fn is_hfxtbypass_0(&self) -> bool {
+        *self == HFXTBYPASSR::HFXTBYPASS_0
+    }
+    #[doc = "Checks if the value of the field is `HFXTBYPASS_1`"]
+    #[inline]
+    pub fn is_hfxtbypass_1(&self) -> bool {
+        *self == HFXTBYPASSR::HFXTBYPASS_1
+    }
+}
+#[doc = "Values that can be written to the field `LFXTDRIVE`"]
+pub enum LFXTDRIVEW {
+    #[doc = "Lowest drive strength and current consumption LFXT oscillator."]
+    LFXTDRIVE_0,
+    #[doc = "Increased drive strength LFXT oscillator."]
+    LFXTDRIVE_1,
+    #[doc = "Increased drive strength LFXT oscillator."]
+    LFXTDRIVE_2,
+    #[doc = "Maximum drive strength and maximum current consumption LFXT oscillator."]
+    LFXTDRIVE_3,
+}
+impl LFXTDRIVEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            LFXTDRIVEW::LFXTDRIVE_0 => 0,
+            LFXTDRIVEW::LFXTDRIVE_1 => 1,
+            LFXTDRIVEW::LFXTDRIVE_2 => 2,
+            LFXTDRIVEW::LFXTDRIVE_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _LFXTDRIVEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _LFXTDRIVEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: LFXTDRIVEW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Lowest drive strength and current consumption LFXT oscillator."]
+    #[inline]
+    pub fn lfxtdrive_0(self) -> &'a mut W {
+        self.variant(LFXTDRIVEW::LFXTDRIVE_0)
+    }
+    #[doc = "Increased drive strength LFXT oscillator."]
+    #[inline]
+    pub fn lfxtdrive_1(self) -> &'a mut W {
+        self.variant(LFXTDRIVEW::LFXTDRIVE_1)
+    }
+    #[doc = "Increased drive strength LFXT oscillator."]
+    #[inline]
+    pub fn lfxtdrive_2(self) -> &'a mut W {
+        self.variant(LFXTDRIVEW::LFXTDRIVE_2)
+    }
+    #[doc = "Maximum drive strength and maximum current consumption LFXT oscillator."]
+    #[inline]
+    pub fn lfxtdrive_3(self) -> &'a mut W {
+        self.variant(LFXTDRIVEW::LFXTDRIVE_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `LFXTAGCOFF`"]
+pub enum LFXTAGCOFFW {
+    #[doc = "AGC enabled."]
+    LFXTAGCOFF_0,
+    #[doc = "AGC disabled."]
+    LFXTAGCOFF_1,
+}
+impl LFXTAGCOFFW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            LFXTAGCOFFW::LFXTAGCOFF_0 => false,
+            LFXTAGCOFFW::LFXTAGCOFF_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _LFXTAGCOFFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _LFXTAGCOFFW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: LFXTAGCOFFW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "AGC enabled."]
+    #[inline]
+    pub fn lfxtagcoff_0(self) -> &'a mut W {
+        self.variant(LFXTAGCOFFW::LFXTAGCOFF_0)
+    }
+    #[doc = "AGC disabled."]
+    #[inline]
+    pub fn lfxtagcoff_1(self) -> &'a mut W {
+        self.variant(LFXTAGCOFFW::LFXTAGCOFF_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `LFXT_EN`"]
+pub enum LFXT_ENW {
+    #[doc = "LFXT is on if it is used as a source for ACLK, MCLK, HSMCLK , or SMCLK\r\r\nand is selected via the port selection and not in bypass mode of operation."]
+    LFXT_EN_0,
+    #[doc = "LFXT is on if LFXT is selected via the port selection and LFXT is not in\r\r\nbypass mode of operation."]
+    LFXT_EN_1,
+}
+impl LFXT_ENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            LFXT_ENW::LFXT_EN_0 => false,
+            LFXT_ENW::LFXT_EN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _LFXT_ENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _LFXT_ENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: LFXT_ENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "LFXT is on if it is used as a source for ACLK, MCLK, HSMCLK , or SMCLK and is selected via the port selection and not in bypass mode of operation."]
+    #[inline]
+    pub fn lfxt_en_0(self) -> &'a mut W {
+        self.variant(LFXT_ENW::LFXT_EN_0)
+    }
+    #[doc = "LFXT is on if LFXT is selected via the port selection and LFXT is not in bypass mode of operation."]
+    #[inline]
+    pub fn lfxt_en_1(self) -> &'a mut W {
+        self.variant(LFXT_ENW::LFXT_EN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `LFXTBYPASS`"]
+pub enum LFXTBYPASSW {
+    #[doc = "LFXT sourced by external crystal."]
+    LFXTBYPASS_0,
+    #[doc = "LFXT sourced by external square wave."]
+    LFXTBYPASS_1,
+}
+impl LFXTBYPASSW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            LFXTBYPASSW::LFXTBYPASS_0 => false,
+            LFXTBYPASSW::LFXTBYPASS_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _LFXTBYPASSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _LFXTBYPASSW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: LFXTBYPASSW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "LFXT sourced by external crystal."]
+    #[inline]
+    pub fn lfxtbypass_0(self) -> &'a mut W {
+        self.variant(LFXTBYPASSW::LFXTBYPASS_0)
+    }
+    #[doc = "LFXT sourced by external square wave."]
+    #[inline]
+    pub fn lfxtbypass_1(self) -> &'a mut W {
+        self.variant(LFXTBYPASSW::LFXTBYPASS_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `HFXTDRIVE`"]
+pub enum HFXTDRIVEW {
+    #[doc = "To be used for HFXTFREQ setting 000b"]
+    HFXTDRIVE_0,
+    #[doc = "To be used for HFXTFREQ settings 001b to 110b"]
+    HFXTDRIVE_1,
+}
+impl HFXTDRIVEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            HFXTDRIVEW::HFXTDRIVE_0 => false,
+            HFXTDRIVEW::HFXTDRIVE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _HFXTDRIVEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _HFXTDRIVEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: HFXTDRIVEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "To be used for HFXTFREQ setting 000b"]
+    #[inline]
+    pub fn hfxtdrive_0(self) -> &'a mut W {
+        self.variant(HFXTDRIVEW::HFXTDRIVE_0)
+    }
+    #[doc = "To be used for HFXTFREQ settings 001b to 110b"]
+    #[inline]
+    pub fn hfxtdrive_1(self) -> &'a mut W {
+        self.variant(HFXTDRIVEW::HFXTDRIVE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 16;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `HFXTFREQ`"]
+pub enum HFXTFREQW {
+    #[doc = "1 MHz to 4 MHz"]
+    HFXTFREQ_0,
+    #[doc = ">4 MHz to 8 MHz"]
+    HFXTFREQ_1,
+    #[doc = ">8 MHz to 16 MHz"]
+    HFXTFREQ_2,
+    #[doc = ">16 MHz to 24 MHz"]
+    HFXTFREQ_3,
+    #[doc = ">24 MHz to 32 MHz"]
+    HFXTFREQ_4,
+    #[doc = ">32 MHz to 40 MHz"]
+    HFXTFREQ_5,
+    #[doc = ">40 MHz to 48 MHz"]
+    HFXTFREQ_6,
+}
+impl HFXTFREQW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            HFXTFREQW::HFXTFREQ_0 => 0,
+            HFXTFREQW::HFXTFREQ_1 => 1,
+            HFXTFREQW::HFXTFREQ_2 => 2,
+            HFXTFREQW::HFXTFREQ_3 => 3,
+            HFXTFREQW::HFXTFREQ_4 => 4,
+            HFXTFREQW::HFXTFREQ_5 => 5,
+            HFXTFREQW::HFXTFREQ_6 => 6,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _HFXTFREQW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _HFXTFREQW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: HFXTFREQW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "1 MHz to 4 MHz"]
+    #[inline]
+    pub fn hfxtfreq_0(self) -> &'a mut W {
+        self.variant(HFXTFREQW::HFXTFREQ_0)
+    }
+    #[doc = ">4 MHz to 8 MHz"]
+    #[inline]
+    pub fn hfxtfreq_1(self) -> &'a mut W {
+        self.variant(HFXTFREQW::HFXTFREQ_1)
+    }
+    #[doc = ">8 MHz to 16 MHz"]
+    #[inline]
+    pub fn hfxtfreq_2(self) -> &'a mut W {
+        self.variant(HFXTFREQW::HFXTFREQ_2)
+    }
+    #[doc = ">16 MHz to 24 MHz"]
+    #[inline]
+    pub fn hfxtfreq_3(self) -> &'a mut W {
+        self.variant(HFXTFREQW::HFXTFREQ_3)
+    }
+    #[doc = ">24 MHz to 32 MHz"]
+    #[inline]
+    pub fn hfxtfreq_4(self) -> &'a mut W {
+        self.variant(HFXTFREQW::HFXTFREQ_4)
+    }
+    #[doc = ">32 MHz to 40 MHz"]
+    #[inline]
+    pub fn hfxtfreq_5(self) -> &'a mut W {
+        self.variant(HFXTFREQW::HFXTFREQ_5)
+    }
+    #[doc = ">40 MHz to 48 MHz"]
+    #[inline]
+    pub fn hfxtfreq_6(self) -> &'a mut W {
+        self.variant(HFXTFREQW::HFXTFREQ_6)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 20;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `HFXT_EN`"]
+pub enum HFXT_ENW {
+    #[doc = "HFXT is on if it is used as a source for MCLK, HSMCLK , or SMCLK and is selected via the port selection and not in bypass mode of operation."]
+    HFXT_EN_0,
+    #[doc = "HFXT is on if HFXT is selected via the port selection and HFXT is not in bypass mode of operation."]
+    HFXT_EN_1,
+}
+impl HFXT_ENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            HFXT_ENW::HFXT_EN_0 => false,
+            HFXT_ENW::HFXT_EN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _HFXT_ENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _HFXT_ENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: HFXT_ENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "HFXT is on if it is used as a source for MCLK, HSMCLK , or SMCLK and is selected via the port selection and not in bypass mode of operation."]
+    #[inline]
+    pub fn hfxt_en_0(self) -> &'a mut W {
+        self.variant(HFXT_ENW::HFXT_EN_0)
+    }
+    #[doc = "HFXT is on if HFXT is selected via the port selection and HFXT is not in bypass mode of operation."]
+    #[inline]
+    pub fn hfxt_en_1(self) -> &'a mut W {
+        self.variant(HFXT_ENW::HFXT_EN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 24;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `HFXTBYPASS`"]
+pub enum HFXTBYPASSW {
+    #[doc = "HFXT sourced by external crystal."]
+    HFXTBYPASS_0,
+    #[doc = "HFXT sourced by external square wave."]
+    HFXTBYPASS_1,
+}
+impl HFXTBYPASSW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            HFXTBYPASSW::HFXTBYPASS_0 => false,
+            HFXTBYPASSW::HFXTBYPASS_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _HFXTBYPASSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _HFXTBYPASSW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: HFXTBYPASSW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "HFXT sourced by external crystal."]
+    #[inline]
+    pub fn hfxtbypass_0(self) -> &'a mut W {
+        self.variant(HFXTBYPASSW::HFXTBYPASS_0)
+    }
+    #[doc = "HFXT sourced by external square wave."]
+    #[inline]
+    pub fn hfxtbypass_1(self) -> &'a mut W {
+        self.variant(HFXTBYPASSW::HFXTBYPASS_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 25;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:1 - LFXT oscillator current can be adjusted to its drive needs"]
+    #[inline]
+    pub fn lfxtdrive(&self) -> LFXTDRIVER {
+        LFXTDRIVER::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 7 - Disables the automatic gain control of the LFXT crystal"]
+    #[inline]
+    pub fn lfxtagcoff(&self) -> LFXTAGCOFFR {
+        LFXTAGCOFFR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 8 - Turns on the LFXT oscillator regardless if used as a clock resource"]
+    #[inline]
+    pub fn lfxt_en(&self) -> LFXT_ENR {
+        LFXT_ENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 9 - LFXT bypass select"]
+    #[inline]
+    pub fn lfxtbypass(&self) -> LFXTBYPASSR {
+        LFXTBYPASSR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 16 - HFXT oscillator drive selection"]
+    #[inline]
+    pub fn hfxtdrive(&self) -> HFXTDRIVER {
+        HFXTDRIVER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 20:22 - HFXT frequency selection"]
+    #[inline]
+    pub fn hfxtfreq(&self) -> HFXTFREQR {
+        HFXTFREQR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 20;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 24 - Turns on the HFXT oscillator regardless if used as a clock resource"]
+    #[inline]
+    pub fn hfxt_en(&self) -> HFXT_ENR {
+        HFXT_ENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 24;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 25 - HFXT bypass select"]
+    #[inline]
+    pub fn hfxtbypass(&self) -> HFXTBYPASSR {
+        HFXTBYPASSR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 25;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 65539 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:1 - LFXT oscillator current can be adjusted to its drive needs"]
+    #[inline]
+    pub fn lfxtdrive(&mut self) -> _LFXTDRIVEW {
+        _LFXTDRIVEW { w: self }
+    }
+    #[doc = "Bit 7 - Disables the automatic gain control of the LFXT crystal"]
+    #[inline]
+    pub fn lfxtagcoff(&mut self) -> _LFXTAGCOFFW {
+        _LFXTAGCOFFW { w: self }
+    }
+    #[doc = "Bit 8 - Turns on the LFXT oscillator regardless if used as a clock resource"]
+    #[inline]
+    pub fn lfxt_en(&mut self) -> _LFXT_ENW {
+        _LFXT_ENW { w: self }
+    }
+    #[doc = "Bit 9 - LFXT bypass select"]
+    #[inline]
+    pub fn lfxtbypass(&mut self) -> _LFXTBYPASSW {
+        _LFXTBYPASSW { w: self }
+    }
+    #[doc = "Bit 16 - HFXT oscillator drive selection"]
+    #[inline]
+    pub fn hfxtdrive(&mut self) -> _HFXTDRIVEW {
+        _HFXTDRIVEW { w: self }
+    }
+    #[doc = "Bits 20:22 - HFXT frequency selection"]
+    #[inline]
+    pub fn hfxtfreq(&mut self) -> _HFXTFREQW {
+        _HFXTFREQW { w: self }
+    }
+    #[doc = "Bit 24 - Turns on the HFXT oscillator regardless if used as a clock resource"]
+    #[inline]
+    pub fn hfxt_en(&mut self) -> _HFXT_ENW {
+        _HFXT_ENW { w: self }
+    }
+    #[doc = "Bit 25 - HFXT bypass select"]
+    #[inline]
+    pub fn hfxtbypass(&mut self) -> _HFXTBYPASSW {
+        _HFXTBYPASSW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/cs/csctl3.rs b/example-source/msp432p401r/src/cs/csctl3.rs
new file mode 100644
index 0000000..b244a27
--- /dev/null
+++ b/example-source/msp432p401r/src/cs/csctl3.rs
@@ -0,0 +1,1018 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CSCTL3 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `FCNTLF`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FCNTLFR {
+    #[doc = "4096 cycles"]
+    FCNTLF_0,
+    #[doc = "8192 cycles"]
+    FCNTLF_1,
+    #[doc = "16384 cycles"]
+    FCNTLF_2,
+    #[doc = "32768 cycles"]
+    FCNTLF_3,
+}
+impl FCNTLFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            FCNTLFR::FCNTLF_0 => 0,
+            FCNTLFR::FCNTLF_1 => 1,
+            FCNTLFR::FCNTLF_2 => 2,
+            FCNTLFR::FCNTLF_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> FCNTLFR {
+        match value {
+            0 => FCNTLFR::FCNTLF_0,
+            1 => FCNTLFR::FCNTLF_1,
+            2 => FCNTLFR::FCNTLF_2,
+            3 => FCNTLFR::FCNTLF_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `FCNTLF_0`"]
+    #[inline]
+    pub fn is_fcntlf_0(&self) -> bool {
+        *self == FCNTLFR::FCNTLF_0
+    }
+    #[doc = "Checks if the value of the field is `FCNTLF_1`"]
+    #[inline]
+    pub fn is_fcntlf_1(&self) -> bool {
+        *self == FCNTLFR::FCNTLF_1
+    }
+    #[doc = "Checks if the value of the field is `FCNTLF_2`"]
+    #[inline]
+    pub fn is_fcntlf_2(&self) -> bool {
+        *self == FCNTLFR::FCNTLF_2
+    }
+    #[doc = "Checks if the value of the field is `FCNTLF_3`"]
+    #[inline]
+    pub fn is_fcntlf_3(&self) -> bool {
+        *self == FCNTLFR::FCNTLF_3
+    }
+}
+#[doc = "Possible values of the field `FCNTLF_EN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FCNTLF_ENR {
+    #[doc = "Startup fault counter disabled. Counter is cleared."]
+    FCNTLF_EN_0,
+    #[doc = "Startup fault counter enabled."]
+    FCNTLF_EN_1,
+}
+impl FCNTLF_ENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            FCNTLF_ENR::FCNTLF_EN_0 => false,
+            FCNTLF_ENR::FCNTLF_EN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> FCNTLF_ENR {
+        match value {
+            false => FCNTLF_ENR::FCNTLF_EN_0,
+            true => FCNTLF_ENR::FCNTLF_EN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `FCNTLF_EN_0`"]
+    #[inline]
+    pub fn is_fcntlf_en_0(&self) -> bool {
+        *self == FCNTLF_ENR::FCNTLF_EN_0
+    }
+    #[doc = "Checks if the value of the field is `FCNTLF_EN_1`"]
+    #[inline]
+    pub fn is_fcntlf_en_1(&self) -> bool {
+        *self == FCNTLF_ENR::FCNTLF_EN_1
+    }
+}
+#[doc = "Possible values of the field `FCNTHF`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FCNTHFR {
+    #[doc = "2048 cycles"]
+    FCNTHF_0,
+    #[doc = "4096 cycles"]
+    FCNTHF_1,
+    #[doc = "8192 cycles"]
+    FCNTHF_2,
+    #[doc = "16384 cycles"]
+    FCNTHF_3,
+}
+impl FCNTHFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            FCNTHFR::FCNTHF_0 => 0,
+            FCNTHFR::FCNTHF_1 => 1,
+            FCNTHFR::FCNTHF_2 => 2,
+            FCNTHFR::FCNTHF_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> FCNTHFR {
+        match value {
+            0 => FCNTHFR::FCNTHF_0,
+            1 => FCNTHFR::FCNTHF_1,
+            2 => FCNTHFR::FCNTHF_2,
+            3 => FCNTHFR::FCNTHF_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `FCNTHF_0`"]
+    #[inline]
+    pub fn is_fcnthf_0(&self) -> bool {
+        *self == FCNTHFR::FCNTHF_0
+    }
+    #[doc = "Checks if the value of the field is `FCNTHF_1`"]
+    #[inline]
+    pub fn is_fcnthf_1(&self) -> bool {
+        *self == FCNTHFR::FCNTHF_1
+    }
+    #[doc = "Checks if the value of the field is `FCNTHF_2`"]
+    #[inline]
+    pub fn is_fcnthf_2(&self) -> bool {
+        *self == FCNTHFR::FCNTHF_2
+    }
+    #[doc = "Checks if the value of the field is `FCNTHF_3`"]
+    #[inline]
+    pub fn is_fcnthf_3(&self) -> bool {
+        *self == FCNTHFR::FCNTHF_3
+    }
+}
+#[doc = "Possible values of the field `FCNTHF_EN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FCNTHF_ENR {
+    #[doc = "Startup fault counter disabled. Counter is cleared."]
+    FCNTHF_EN_0,
+    #[doc = "Startup fault counter enabled."]
+    FCNTHF_EN_1,
+}
+impl FCNTHF_ENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            FCNTHF_ENR::FCNTHF_EN_0 => false,
+            FCNTHF_ENR::FCNTHF_EN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> FCNTHF_ENR {
+        match value {
+            false => FCNTHF_ENR::FCNTHF_EN_0,
+            true => FCNTHF_ENR::FCNTHF_EN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `FCNTHF_EN_0`"]
+    #[inline]
+    pub fn is_fcnthf_en_0(&self) -> bool {
+        *self == FCNTHF_ENR::FCNTHF_EN_0
+    }
+    #[doc = "Checks if the value of the field is `FCNTHF_EN_1`"]
+    #[inline]
+    pub fn is_fcnthf_en_1(&self) -> bool {
+        *self == FCNTHF_ENR::FCNTHF_EN_1
+    }
+}
+#[doc = "Possible values of the field `FCNTHF2`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FCNTHF2R {
+    #[doc = "2048 cycles"]
+    FCNTHF2_0,
+    #[doc = "4096 cycles"]
+    FCNTHF2_1,
+    #[doc = "8192 cycles"]
+    FCNTHF2_2,
+    #[doc = "16384 cycles"]
+    FCNTHF2_3,
+}
+impl FCNTHF2R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            FCNTHF2R::FCNTHF2_0 => 0,
+            FCNTHF2R::FCNTHF2_1 => 1,
+            FCNTHF2R::FCNTHF2_2 => 2,
+            FCNTHF2R::FCNTHF2_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> FCNTHF2R {
+        match value {
+            0 => FCNTHF2R::FCNTHF2_0,
+            1 => FCNTHF2R::FCNTHF2_1,
+            2 => FCNTHF2R::FCNTHF2_2,
+            3 => FCNTHF2R::FCNTHF2_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `FCNTHF2_0`"]
+    #[inline]
+    pub fn is_fcnthf2_0(&self) -> bool {
+        *self == FCNTHF2R::FCNTHF2_0
+    }
+    #[doc = "Checks if the value of the field is `FCNTHF2_1`"]
+    #[inline]
+    pub fn is_fcnthf2_1(&self) -> bool {
+        *self == FCNTHF2R::FCNTHF2_1
+    }
+    #[doc = "Checks if the value of the field is `FCNTHF2_2`"]
+    #[inline]
+    pub fn is_fcnthf2_2(&self) -> bool {
+        *self == FCNTHF2R::FCNTHF2_2
+    }
+    #[doc = "Checks if the value of the field is `FCNTHF2_3`"]
+    #[inline]
+    pub fn is_fcnthf2_3(&self) -> bool {
+        *self == FCNTHF2R::FCNTHF2_3
+    }
+}
+#[doc = "Possible values of the field `FCNTHF2_EN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FCNTHF2_ENR {
+    #[doc = "Startup fault counter disabled. Counter is cleared."]
+    FCNTHF2_EN_0,
+    #[doc = "Startup fault counter enabled."]
+    FCNTHF2_EN_1,
+}
+impl FCNTHF2_ENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            FCNTHF2_ENR::FCNTHF2_EN_0 => false,
+            FCNTHF2_ENR::FCNTHF2_EN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> FCNTHF2_ENR {
+        match value {
+            false => FCNTHF2_ENR::FCNTHF2_EN_0,
+            true => FCNTHF2_ENR::FCNTHF2_EN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `FCNTHF2_EN_0`"]
+    #[inline]
+    pub fn is_fcnthf2_en_0(&self) -> bool {
+        *self == FCNTHF2_ENR::FCNTHF2_EN_0
+    }
+    #[doc = "Checks if the value of the field is `FCNTHF2_EN_1`"]
+    #[inline]
+    pub fn is_fcnthf2_en_1(&self) -> bool {
+        *self == FCNTHF2_ENR::FCNTHF2_EN_1
+    }
+}
+#[doc = "Values that can be written to the field `FCNTLF`"]
+pub enum FCNTLFW {
+    #[doc = "4096 cycles"]
+    FCNTLF_0,
+    #[doc = "8192 cycles"]
+    FCNTLF_1,
+    #[doc = "16384 cycles"]
+    FCNTLF_2,
+    #[doc = "32768 cycles"]
+    FCNTLF_3,
+}
+impl FCNTLFW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            FCNTLFW::FCNTLF_0 => 0,
+            FCNTLFW::FCNTLF_1 => 1,
+            FCNTLFW::FCNTLF_2 => 2,
+            FCNTLFW::FCNTLF_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FCNTLFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FCNTLFW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: FCNTLFW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "4096 cycles"]
+    #[inline]
+    pub fn fcntlf_0(self) -> &'a mut W {
+        self.variant(FCNTLFW::FCNTLF_0)
+    }
+    #[doc = "8192 cycles"]
+    #[inline]
+    pub fn fcntlf_1(self) -> &'a mut W {
+        self.variant(FCNTLFW::FCNTLF_1)
+    }
+    #[doc = "16384 cycles"]
+    #[inline]
+    pub fn fcntlf_2(self) -> &'a mut W {
+        self.variant(FCNTLFW::FCNTLF_2)
+    }
+    #[doc = "32768 cycles"]
+    #[inline]
+    pub fn fcntlf_3(self) -> &'a mut W {
+        self.variant(FCNTLFW::FCNTLF_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `RFCNTLF`"]
+pub enum RFCNTLFW {
+    #[doc = "Not applicable. Always reads as zero due to self clearing."]
+    RFCNTLF_0,
+    #[doc = "Restarts the counter immediately."]
+    RFCNTLF_1,
+}
+impl RFCNTLFW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            RFCNTLFW::RFCNTLF_0 => false,
+            RFCNTLFW::RFCNTLF_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RFCNTLFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RFCNTLFW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: RFCNTLFW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Not applicable. Always reads as zero due to self clearing."]
+    #[inline]
+    pub fn rfcntlf_0(self) -> &'a mut W {
+        self.variant(RFCNTLFW::RFCNTLF_0)
+    }
+    #[doc = "Restarts the counter immediately."]
+    #[inline]
+    pub fn rfcntlf_1(self) -> &'a mut W {
+        self.variant(RFCNTLFW::RFCNTLF_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `FCNTLF_EN`"]
+pub enum FCNTLF_ENW {
+    #[doc = "Startup fault counter disabled. Counter is cleared."]
+    FCNTLF_EN_0,
+    #[doc = "Startup fault counter enabled."]
+    FCNTLF_EN_1,
+}
+impl FCNTLF_ENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            FCNTLF_ENW::FCNTLF_EN_0 => false,
+            FCNTLF_ENW::FCNTLF_EN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FCNTLF_ENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FCNTLF_ENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: FCNTLF_ENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Startup fault counter disabled. Counter is cleared."]
+    #[inline]
+    pub fn fcntlf_en_0(self) -> &'a mut W {
+        self.variant(FCNTLF_ENW::FCNTLF_EN_0)
+    }
+    #[doc = "Startup fault counter enabled."]
+    #[inline]
+    pub fn fcntlf_en_1(self) -> &'a mut W {
+        self.variant(FCNTLF_ENW::FCNTLF_EN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `FCNTHF`"]
+pub enum FCNTHFW {
+    #[doc = "2048 cycles"]
+    FCNTHF_0,
+    #[doc = "4096 cycles"]
+    FCNTHF_1,
+    #[doc = "8192 cycles"]
+    FCNTHF_2,
+    #[doc = "16384 cycles"]
+    FCNTHF_3,
+}
+impl FCNTHFW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            FCNTHFW::FCNTHF_0 => 0,
+            FCNTHFW::FCNTHF_1 => 1,
+            FCNTHFW::FCNTHF_2 => 2,
+            FCNTHFW::FCNTHF_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FCNTHFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FCNTHFW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: FCNTHFW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "2048 cycles"]
+    #[inline]
+    pub fn fcnthf_0(self) -> &'a mut W {
+        self.variant(FCNTHFW::FCNTHF_0)
+    }
+    #[doc = "4096 cycles"]
+    #[inline]
+    pub fn fcnthf_1(self) -> &'a mut W {
+        self.variant(FCNTHFW::FCNTHF_1)
+    }
+    #[doc = "8192 cycles"]
+    #[inline]
+    pub fn fcnthf_2(self) -> &'a mut W {
+        self.variant(FCNTHFW::FCNTHF_2)
+    }
+    #[doc = "16384 cycles"]
+    #[inline]
+    pub fn fcnthf_3(self) -> &'a mut W {
+        self.variant(FCNTHFW::FCNTHF_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `RFCNTHF`"]
+pub enum RFCNTHFW {
+    #[doc = "Not applicable. Always reads as zero due to self clearing."]
+    RFCNTHF_0,
+    #[doc = "Restarts the counter immediately."]
+    RFCNTHF_1,
+}
+impl RFCNTHFW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            RFCNTHFW::RFCNTHF_0 => false,
+            RFCNTHFW::RFCNTHF_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RFCNTHFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RFCNTHFW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: RFCNTHFW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Not applicable. Always reads as zero due to self clearing."]
+    #[inline]
+    pub fn rfcnthf_0(self) -> &'a mut W {
+        self.variant(RFCNTHFW::RFCNTHF_0)
+    }
+    #[doc = "Restarts the counter immediately."]
+    #[inline]
+    pub fn rfcnthf_1(self) -> &'a mut W {
+        self.variant(RFCNTHFW::RFCNTHF_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `FCNTHF_EN`"]
+pub enum FCNTHF_ENW {
+    #[doc = "Startup fault counter disabled. Counter is cleared."]
+    FCNTHF_EN_0,
+    #[doc = "Startup fault counter enabled."]
+    FCNTHF_EN_1,
+}
+impl FCNTHF_ENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            FCNTHF_ENW::FCNTHF_EN_0 => false,
+            FCNTHF_ENW::FCNTHF_EN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FCNTHF_ENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FCNTHF_ENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: FCNTHF_ENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Startup fault counter disabled. Counter is cleared."]
+    #[inline]
+    pub fn fcnthf_en_0(self) -> &'a mut W {
+        self.variant(FCNTHF_ENW::FCNTHF_EN_0)
+    }
+    #[doc = "Startup fault counter enabled."]
+    #[inline]
+    pub fn fcnthf_en_1(self) -> &'a mut W {
+        self.variant(FCNTHF_ENW::FCNTHF_EN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `FCNTHF2`"]
+pub enum FCNTHF2W {
+    #[doc = "2048 cycles"]
+    FCNTHF2_0,
+    #[doc = "4096 cycles"]
+    FCNTHF2_1,
+    #[doc = "8192 cycles"]
+    FCNTHF2_2,
+    #[doc = "16384 cycles"]
+    FCNTHF2_3,
+}
+impl FCNTHF2W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            FCNTHF2W::FCNTHF2_0 => 0,
+            FCNTHF2W::FCNTHF2_1 => 1,
+            FCNTHF2W::FCNTHF2_2 => 2,
+            FCNTHF2W::FCNTHF2_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FCNTHF2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FCNTHF2W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: FCNTHF2W) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "2048 cycles"]
+    #[inline]
+    pub fn fcnthf2_0(self) -> &'a mut W {
+        self.variant(FCNTHF2W::FCNTHF2_0)
+    }
+    #[doc = "4096 cycles"]
+    #[inline]
+    pub fn fcnthf2_1(self) -> &'a mut W {
+        self.variant(FCNTHF2W::FCNTHF2_1)
+    }
+    #[doc = "8192 cycles"]
+    #[inline]
+    pub fn fcnthf2_2(self) -> &'a mut W {
+        self.variant(FCNTHF2W::FCNTHF2_2)
+    }
+    #[doc = "16384 cycles"]
+    #[inline]
+    pub fn fcnthf2_3(self) -> &'a mut W {
+        self.variant(FCNTHF2W::FCNTHF2_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `RFCNTHF2`"]
+pub enum RFCNTHF2W {
+    #[doc = "Not applicable. Always reads as zero due to self clearing."]
+    RFCNTHF2_0,
+    #[doc = "Restarts the counter immediately."]
+    RFCNTHF2_1,
+}
+impl RFCNTHF2W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            RFCNTHF2W::RFCNTHF2_0 => false,
+            RFCNTHF2W::RFCNTHF2_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RFCNTHF2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RFCNTHF2W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: RFCNTHF2W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Not applicable. Always reads as zero due to self clearing."]
+    #[inline]
+    pub fn rfcnthf2_0(self) -> &'a mut W {
+        self.variant(RFCNTHF2W::RFCNTHF2_0)
+    }
+    #[doc = "Restarts the counter immediately."]
+    #[inline]
+    pub fn rfcnthf2_1(self) -> &'a mut W {
+        self.variant(RFCNTHF2W::RFCNTHF2_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `FCNTHF2_EN`"]
+pub enum FCNTHF2_ENW {
+    #[doc = "Startup fault counter disabled. Counter is cleared."]
+    FCNTHF2_EN_0,
+    #[doc = "Startup fault counter enabled."]
+    FCNTHF2_EN_1,
+}
+impl FCNTHF2_ENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            FCNTHF2_ENW::FCNTHF2_EN_0 => false,
+            FCNTHF2_ENW::FCNTHF2_EN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FCNTHF2_ENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FCNTHF2_ENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: FCNTHF2_ENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Startup fault counter disabled. Counter is cleared."]
+    #[inline]
+    pub fn fcnthf2_en_0(self) -> &'a mut W {
+        self.variant(FCNTHF2_ENW::FCNTHF2_EN_0)
+    }
+    #[doc = "Startup fault counter enabled."]
+    #[inline]
+    pub fn fcnthf2_en_1(self) -> &'a mut W {
+        self.variant(FCNTHF2_ENW::FCNTHF2_EN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:1 - Start flag counter for LFXT"]
+    #[inline]
+    pub fn fcntlf(&self) -> FCNTLFR {
+        FCNTLFR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 3 - Enable start fault counter for LFXT"]
+    #[inline]
+    pub fn fcntlf_en(&self) -> FCNTLF_ENR {
+        FCNTLF_ENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 4:5 - Start flag counter for HFXT"]
+    #[inline]
+    pub fn fcnthf(&self) -> FCNTHFR {
+        FCNTHFR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 7 - Enable start fault counter for HFXT"]
+    #[inline]
+    pub fn fcnthf_en(&self) -> FCNTHF_ENR {
+        FCNTHF_ENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 8:9 - Start flag counter for HFXT2"]
+    #[inline]
+    pub fn fcnthf2(&self) -> FCNTHF2R {
+        FCNTHF2R::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 11 - Enable start fault counter for HFXT2"]
+    #[inline]
+    pub fn fcnthf2_en(&self) -> FCNTHF2_ENR {
+        FCNTHF2_ENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 3003 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:1 - Start flag counter for LFXT"]
+    #[inline]
+    pub fn fcntlf(&mut self) -> _FCNTLFW {
+        _FCNTLFW { w: self }
+    }
+    #[doc = "Bit 2 - Reset start fault counter for LFXT"]
+    #[inline]
+    pub fn rfcntlf(&mut self) -> _RFCNTLFW {
+        _RFCNTLFW { w: self }
+    }
+    #[doc = "Bit 3 - Enable start fault counter for LFXT"]
+    #[inline]
+    pub fn fcntlf_en(&mut self) -> _FCNTLF_ENW {
+        _FCNTLF_ENW { w: self }
+    }
+    #[doc = "Bits 4:5 - Start flag counter for HFXT"]
+    #[inline]
+    pub fn fcnthf(&mut self) -> _FCNTHFW {
+        _FCNTHFW { w: self }
+    }
+    #[doc = "Bit 6 - Reset start fault counter for HFXT"]
+    #[inline]
+    pub fn rfcnthf(&mut self) -> _RFCNTHFW {
+        _RFCNTHFW { w: self }
+    }
+    #[doc = "Bit 7 - Enable start fault counter for HFXT"]
+    #[inline]
+    pub fn fcnthf_en(&mut self) -> _FCNTHF_ENW {
+        _FCNTHF_ENW { w: self }
+    }
+    #[doc = "Bits 8:9 - Start flag counter for HFXT2"]
+    #[inline]
+    pub fn fcnthf2(&mut self) -> _FCNTHF2W {
+        _FCNTHF2W { w: self }
+    }
+    #[doc = "Bit 10 - Reset start fault counter for HFXT2"]
+    #[inline]
+    pub fn rfcnthf2(&mut self) -> _RFCNTHF2W {
+        _RFCNTHF2W { w: self }
+    }
+    #[doc = "Bit 11 - Enable start fault counter for HFXT2"]
+    #[inline]
+    pub fn fcnthf2_en(&mut self) -> _FCNTHF2_ENW {
+        _FCNTHF2_ENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/cs/csdcoercal0.rs b/example-source/msp432p401r/src/cs/csdcoercal0.rs
new file mode 100644
index 0000000..dd224f8
--- /dev/null
+++ b/example-source/msp432p401r/src/cs/csdcoercal0.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CSDCOERCAL0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DCO_TCCALR {
+    bits: u8,
+}
+impl DCO_TCCALR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DCO_FCAL_RSEL04R {
+    bits: u16,
+}
+impl DCO_FCAL_RSEL04R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DCO_TCCALW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DCO_TCCALW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DCO_FCAL_RSEL04W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DCO_FCAL_RSEL04W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 16;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:1 - DCO Temperature compensation calibration"]
+    #[inline]
+    pub fn dco_tccal(&self) -> DCO_TCCALR {
+        let bits = {
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        DCO_TCCALR { bits }
+    }
+    #[doc = "Bits 16:25 - DCO frequency calibration for DCO frequency range (DCORSEL) 0 to 4."]
+    #[inline]
+    pub fn dco_fcal_rsel04(&self) -> DCO_FCAL_RSEL04R {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        DCO_FCAL_RSEL04R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 16777216 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:1 - DCO Temperature compensation calibration"]
+    #[inline]
+    pub fn dco_tccal(&mut self) -> _DCO_TCCALW {
+        _DCO_TCCALW { w: self }
+    }
+    #[doc = "Bits 16:25 - DCO frequency calibration for DCO frequency range (DCORSEL) 0 to 4."]
+    #[inline]
+    pub fn dco_fcal_rsel04(&mut self) -> _DCO_FCAL_RSEL04W {
+        _DCO_FCAL_RSEL04W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/cs/csdcoercal1.rs b/example-source/msp432p401r/src/cs/csdcoercal1.rs
new file mode 100644
index 0000000..d7a57c1
--- /dev/null
+++ b/example-source/msp432p401r/src/cs/csdcoercal1.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CSDCOERCAL1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DCO_FCAL_RSEL5R {
+    bits: u16,
+}
+impl DCO_FCAL_RSEL5R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DCO_FCAL_RSEL5W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DCO_FCAL_RSEL5W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - DCO frequency calibration for DCO frequency range (DCORSEL) 5."]
+    #[inline]
+    pub fn dco_fcal_rsel5(&self) -> DCO_FCAL_RSEL5R {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        DCO_FCAL_RSEL5R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 256 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:9 - DCO frequency calibration for DCO frequency range (DCORSEL) 5."]
+    #[inline]
+    pub fn dco_fcal_rsel5(&mut self) -> _DCO_FCAL_RSEL5W {
+        _DCO_FCAL_RSEL5W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/cs/csie.rs b/example-source/msp432p401r/src/cs/csie.rs
new file mode 100644
index 0000000..b170867
--- /dev/null
+++ b/example-source/msp432p401r/src/cs/csie.rs
@@ -0,0 +1,1373 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CSIE {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `LFXTIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LFXTIER {
+    #[doc = "Interrupt disabled"]
+    LFXTIE_0,
+    #[doc = "Interrupt enabled"]
+    LFXTIE_1,
+}
+impl LFXTIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            LFXTIER::LFXTIE_0 => false,
+            LFXTIER::LFXTIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> LFXTIER {
+        match value {
+            false => LFXTIER::LFXTIE_0,
+            true => LFXTIER::LFXTIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `LFXTIE_0`"]
+    #[inline]
+    pub fn is_lfxtie_0(&self) -> bool {
+        *self == LFXTIER::LFXTIE_0
+    }
+    #[doc = "Checks if the value of the field is `LFXTIE_1`"]
+    #[inline]
+    pub fn is_lfxtie_1(&self) -> bool {
+        *self == LFXTIER::LFXTIE_1
+    }
+}
+#[doc = "Possible values of the field `HFXTIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HFXTIER {
+    #[doc = "Interrupt disabled"]
+    HFXTIE_0,
+    #[doc = "Interrupt enabled"]
+    HFXTIE_1,
+}
+impl HFXTIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            HFXTIER::HFXTIE_0 => false,
+            HFXTIER::HFXTIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> HFXTIER {
+        match value {
+            false => HFXTIER::HFXTIE_0,
+            true => HFXTIER::HFXTIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `HFXTIE_0`"]
+    #[inline]
+    pub fn is_hfxtie_0(&self) -> bool {
+        *self == HFXTIER::HFXTIE_0
+    }
+    #[doc = "Checks if the value of the field is `HFXTIE_1`"]
+    #[inline]
+    pub fn is_hfxtie_1(&self) -> bool {
+        *self == HFXTIER::HFXTIE_1
+    }
+}
+#[doc = "Possible values of the field `HFXT2IE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HFXT2IER {
+    #[doc = "Interrupt disabled"]
+    HFXT2IE_0,
+    #[doc = "Interrupt enabled"]
+    HFXT2IE_1,
+}
+impl HFXT2IER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            HFXT2IER::HFXT2IE_0 => false,
+            HFXT2IER::HFXT2IE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> HFXT2IER {
+        match value {
+            false => HFXT2IER::HFXT2IE_0,
+            true => HFXT2IER::HFXT2IE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `HFXT2IE_0`"]
+    #[inline]
+    pub fn is_hfxt2ie_0(&self) -> bool {
+        *self == HFXT2IER::HFXT2IE_0
+    }
+    #[doc = "Checks if the value of the field is `HFXT2IE_1`"]
+    #[inline]
+    pub fn is_hfxt2ie_1(&self) -> bool {
+        *self == HFXT2IER::HFXT2IE_1
+    }
+}
+#[doc = "Possible values of the field `DCOR_OPNIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DCOR_OPNIER {
+    #[doc = "Interrupt disabled"]
+    DCOR_OPNIE_0,
+    #[doc = "Interrupt enabled"]
+    DCOR_OPNIE_1,
+}
+impl DCOR_OPNIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            DCOR_OPNIER::DCOR_OPNIE_0 => false,
+            DCOR_OPNIER::DCOR_OPNIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> DCOR_OPNIER {
+        match value {
+            false => DCOR_OPNIER::DCOR_OPNIE_0,
+            true => DCOR_OPNIER::DCOR_OPNIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DCOR_OPNIE_0`"]
+    #[inline]
+    pub fn is_dcor_opnie_0(&self) -> bool {
+        *self == DCOR_OPNIER::DCOR_OPNIE_0
+    }
+    #[doc = "Checks if the value of the field is `DCOR_OPNIE_1`"]
+    #[inline]
+    pub fn is_dcor_opnie_1(&self) -> bool {
+        *self == DCOR_OPNIER::DCOR_OPNIE_1
+    }
+}
+#[doc = "Possible values of the field `FCNTLFIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FCNTLFIER {
+    #[doc = "Interrupt disabled"]
+    FCNTLFIE_0,
+    #[doc = "Interrupt enabled"]
+    FCNTLFIE_1,
+}
+impl FCNTLFIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            FCNTLFIER::FCNTLFIE_0 => false,
+            FCNTLFIER::FCNTLFIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> FCNTLFIER {
+        match value {
+            false => FCNTLFIER::FCNTLFIE_0,
+            true => FCNTLFIER::FCNTLFIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `FCNTLFIE_0`"]
+    #[inline]
+    pub fn is_fcntlfie_0(&self) -> bool {
+        *self == FCNTLFIER::FCNTLFIE_0
+    }
+    #[doc = "Checks if the value of the field is `FCNTLFIE_1`"]
+    #[inline]
+    pub fn is_fcntlfie_1(&self) -> bool {
+        *self == FCNTLFIER::FCNTLFIE_1
+    }
+}
+#[doc = "Possible values of the field `FCNTHFIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FCNTHFIER {
+    #[doc = "Interrupt disabled"]
+    FCNTHFIE_0,
+    #[doc = "Interrupt enabled"]
+    FCNTHFIE_1,
+}
+impl FCNTHFIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            FCNTHFIER::FCNTHFIE_0 => false,
+            FCNTHFIER::FCNTHFIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> FCNTHFIER {
+        match value {
+            false => FCNTHFIER::FCNTHFIE_0,
+            true => FCNTHFIER::FCNTHFIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `FCNTHFIE_0`"]
+    #[inline]
+    pub fn is_fcnthfie_0(&self) -> bool {
+        *self == FCNTHFIER::FCNTHFIE_0
+    }
+    #[doc = "Checks if the value of the field is `FCNTHFIE_1`"]
+    #[inline]
+    pub fn is_fcnthfie_1(&self) -> bool {
+        *self == FCNTHFIER::FCNTHFIE_1
+    }
+}
+#[doc = "Possible values of the field `FCNTHF2IE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FCNTHF2IER {
+    #[doc = "Interrupt disabled"]
+    FCNTHF2IE_0,
+    #[doc = "Interrupt enabled"]
+    FCNTHF2IE_1,
+}
+impl FCNTHF2IER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            FCNTHF2IER::FCNTHF2IE_0 => false,
+            FCNTHF2IER::FCNTHF2IE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> FCNTHF2IER {
+        match value {
+            false => FCNTHF2IER::FCNTHF2IE_0,
+            true => FCNTHF2IER::FCNTHF2IE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `FCNTHF2IE_0`"]
+    #[inline]
+    pub fn is_fcnthf2ie_0(&self) -> bool {
+        *self == FCNTHF2IER::FCNTHF2IE_0
+    }
+    #[doc = "Checks if the value of the field is `FCNTHF2IE_1`"]
+    #[inline]
+    pub fn is_fcnthf2ie_1(&self) -> bool {
+        *self == FCNTHF2IER::FCNTHF2IE_1
+    }
+}
+#[doc = "Possible values of the field `PLLOOLIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PLLOOLIER {
+    #[doc = "Interrupt disabled"]
+    PLLOOLIE_0,
+    #[doc = "Interrupt enabled"]
+    PLLOOLIE_1,
+}
+impl PLLOOLIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            PLLOOLIER::PLLOOLIE_0 => false,
+            PLLOOLIER::PLLOOLIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> PLLOOLIER {
+        match value {
+            false => PLLOOLIER::PLLOOLIE_0,
+            true => PLLOOLIER::PLLOOLIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `PLLOOLIE_0`"]
+    #[inline]
+    pub fn is_plloolie_0(&self) -> bool {
+        *self == PLLOOLIER::PLLOOLIE_0
+    }
+    #[doc = "Checks if the value of the field is `PLLOOLIE_1`"]
+    #[inline]
+    pub fn is_plloolie_1(&self) -> bool {
+        *self == PLLOOLIER::PLLOOLIE_1
+    }
+}
+#[doc = "Possible values of the field `PLLLOSIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PLLLOSIER {
+    #[doc = "Interrupt disabled"]
+    PLLLOSIE_0,
+    #[doc = "Interrupt enabled"]
+    PLLLOSIE_1,
+}
+impl PLLLOSIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            PLLLOSIER::PLLLOSIE_0 => false,
+            PLLLOSIER::PLLLOSIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> PLLLOSIER {
+        match value {
+            false => PLLLOSIER::PLLLOSIE_0,
+            true => PLLLOSIER::PLLLOSIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `PLLLOSIE_0`"]
+    #[inline]
+    pub fn is_plllosie_0(&self) -> bool {
+        *self == PLLLOSIER::PLLLOSIE_0
+    }
+    #[doc = "Checks if the value of the field is `PLLLOSIE_1`"]
+    #[inline]
+    pub fn is_plllosie_1(&self) -> bool {
+        *self == PLLLOSIER::PLLLOSIE_1
+    }
+}
+#[doc = "Possible values of the field `PLLOORIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PLLOORIER {
+    #[doc = "Interrupt disabled"]
+    PLLOORIE_0,
+    #[doc = "Interrupt enabled"]
+    PLLOORIE_1,
+}
+impl PLLOORIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            PLLOORIER::PLLOORIE_0 => false,
+            PLLOORIER::PLLOORIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> PLLOORIER {
+        match value {
+            false => PLLOORIER::PLLOORIE_0,
+            true => PLLOORIER::PLLOORIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `PLLOORIE_0`"]
+    #[inline]
+    pub fn is_plloorie_0(&self) -> bool {
+        *self == PLLOORIER::PLLOORIE_0
+    }
+    #[doc = "Checks if the value of the field is `PLLOORIE_1`"]
+    #[inline]
+    pub fn is_plloorie_1(&self) -> bool {
+        *self == PLLOORIER::PLLOORIE_1
+    }
+}
+#[doc = "Possible values of the field `CALIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CALIER {
+    #[doc = "Interrupt disabled"]
+    CALIE_0,
+    #[doc = "Interrupt enabled"]
+    CALIE_1,
+}
+impl CALIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CALIER::CALIE_0 => false,
+            CALIER::CALIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CALIER {
+        match value {
+            false => CALIER::CALIE_0,
+            true => CALIER::CALIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CALIE_0`"]
+    #[inline]
+    pub fn is_calie_0(&self) -> bool {
+        *self == CALIER::CALIE_0
+    }
+    #[doc = "Checks if the value of the field is `CALIE_1`"]
+    #[inline]
+    pub fn is_calie_1(&self) -> bool {
+        *self == CALIER::CALIE_1
+    }
+}
+#[doc = "Values that can be written to the field `LFXTIE`"]
+pub enum LFXTIEW {
+    #[doc = "Interrupt disabled"]
+    LFXTIE_0,
+    #[doc = "Interrupt enabled"]
+    LFXTIE_1,
+}
+impl LFXTIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            LFXTIEW::LFXTIE_0 => false,
+            LFXTIEW::LFXTIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _LFXTIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _LFXTIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: LFXTIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn lfxtie_0(self) -> &'a mut W {
+        self.variant(LFXTIEW::LFXTIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn lfxtie_1(self) -> &'a mut W {
+        self.variant(LFXTIEW::LFXTIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `HFXTIE`"]
+pub enum HFXTIEW {
+    #[doc = "Interrupt disabled"]
+    HFXTIE_0,
+    #[doc = "Interrupt enabled"]
+    HFXTIE_1,
+}
+impl HFXTIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            HFXTIEW::HFXTIE_0 => false,
+            HFXTIEW::HFXTIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _HFXTIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _HFXTIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: HFXTIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn hfxtie_0(self) -> &'a mut W {
+        self.variant(HFXTIEW::HFXTIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn hfxtie_1(self) -> &'a mut W {
+        self.variant(HFXTIEW::HFXTIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `HFXT2IE`"]
+pub enum HFXT2IEW {
+    #[doc = "Interrupt disabled"]
+    HFXT2IE_0,
+    #[doc = "Interrupt enabled"]
+    HFXT2IE_1,
+}
+impl HFXT2IEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            HFXT2IEW::HFXT2IE_0 => false,
+            HFXT2IEW::HFXT2IE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _HFXT2IEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _HFXT2IEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: HFXT2IEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn hfxt2ie_0(self) -> &'a mut W {
+        self.variant(HFXT2IEW::HFXT2IE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn hfxt2ie_1(self) -> &'a mut W {
+        self.variant(HFXT2IEW::HFXT2IE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `DCOR_OPNIE`"]
+pub enum DCOR_OPNIEW {
+    #[doc = "Interrupt disabled"]
+    DCOR_OPNIE_0,
+    #[doc = "Interrupt enabled"]
+    DCOR_OPNIE_1,
+}
+impl DCOR_OPNIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            DCOR_OPNIEW::DCOR_OPNIE_0 => false,
+            DCOR_OPNIEW::DCOR_OPNIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DCOR_OPNIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DCOR_OPNIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: DCOR_OPNIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn dcor_opnie_0(self) -> &'a mut W {
+        self.variant(DCOR_OPNIEW::DCOR_OPNIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn dcor_opnie_1(self) -> &'a mut W {
+        self.variant(DCOR_OPNIEW::DCOR_OPNIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `FCNTLFIE`"]
+pub enum FCNTLFIEW {
+    #[doc = "Interrupt disabled"]
+    FCNTLFIE_0,
+    #[doc = "Interrupt enabled"]
+    FCNTLFIE_1,
+}
+impl FCNTLFIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            FCNTLFIEW::FCNTLFIE_0 => false,
+            FCNTLFIEW::FCNTLFIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FCNTLFIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FCNTLFIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: FCNTLFIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn fcntlfie_0(self) -> &'a mut W {
+        self.variant(FCNTLFIEW::FCNTLFIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn fcntlfie_1(self) -> &'a mut W {
+        self.variant(FCNTLFIEW::FCNTLFIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `FCNTHFIE`"]
+pub enum FCNTHFIEW {
+    #[doc = "Interrupt disabled"]
+    FCNTHFIE_0,
+    #[doc = "Interrupt enabled"]
+    FCNTHFIE_1,
+}
+impl FCNTHFIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            FCNTHFIEW::FCNTHFIE_0 => false,
+            FCNTHFIEW::FCNTHFIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FCNTHFIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FCNTHFIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: FCNTHFIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn fcnthfie_0(self) -> &'a mut W {
+        self.variant(FCNTHFIEW::FCNTHFIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn fcnthfie_1(self) -> &'a mut W {
+        self.variant(FCNTHFIEW::FCNTHFIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `FCNTHF2IE`"]
+pub enum FCNTHF2IEW {
+    #[doc = "Interrupt disabled"]
+    FCNTHF2IE_0,
+    #[doc = "Interrupt enabled"]
+    FCNTHF2IE_1,
+}
+impl FCNTHF2IEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            FCNTHF2IEW::FCNTHF2IE_0 => false,
+            FCNTHF2IEW::FCNTHF2IE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FCNTHF2IEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FCNTHF2IEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: FCNTHF2IEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn fcnthf2ie_0(self) -> &'a mut W {
+        self.variant(FCNTHF2IEW::FCNTHF2IE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn fcnthf2ie_1(self) -> &'a mut W {
+        self.variant(FCNTHF2IEW::FCNTHF2IE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `PLLOOLIE`"]
+pub enum PLLOOLIEW {
+    #[doc = "Interrupt disabled"]
+    PLLOOLIE_0,
+    #[doc = "Interrupt enabled"]
+    PLLOOLIE_1,
+}
+impl PLLOOLIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            PLLOOLIEW::PLLOOLIE_0 => false,
+            PLLOOLIEW::PLLOOLIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PLLOOLIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PLLOOLIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: PLLOOLIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn plloolie_0(self) -> &'a mut W {
+        self.variant(PLLOOLIEW::PLLOOLIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn plloolie_1(self) -> &'a mut W {
+        self.variant(PLLOOLIEW::PLLOOLIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `PLLLOSIE`"]
+pub enum PLLLOSIEW {
+    #[doc = "Interrupt disabled"]
+    PLLLOSIE_0,
+    #[doc = "Interrupt enabled"]
+    PLLLOSIE_1,
+}
+impl PLLLOSIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            PLLLOSIEW::PLLLOSIE_0 => false,
+            PLLLOSIEW::PLLLOSIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PLLLOSIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PLLLOSIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: PLLLOSIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn plllosie_0(self) -> &'a mut W {
+        self.variant(PLLLOSIEW::PLLLOSIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn plllosie_1(self) -> &'a mut W {
+        self.variant(PLLLOSIEW::PLLLOSIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `PLLOORIE`"]
+pub enum PLLOORIEW {
+    #[doc = "Interrupt disabled"]
+    PLLOORIE_0,
+    #[doc = "Interrupt enabled"]
+    PLLOORIE_1,
+}
+impl PLLOORIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            PLLOORIEW::PLLOORIE_0 => false,
+            PLLOORIEW::PLLOORIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PLLOORIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PLLOORIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: PLLOORIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn plloorie_0(self) -> &'a mut W {
+        self.variant(PLLOORIEW::PLLOORIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn plloorie_1(self) -> &'a mut W {
+        self.variant(PLLOORIEW::PLLOORIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CALIE`"]
+pub enum CALIEW {
+    #[doc = "Interrupt disabled"]
+    CALIE_0,
+    #[doc = "Interrupt enabled"]
+    CALIE_1,
+}
+impl CALIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CALIEW::CALIE_0 => false,
+            CALIEW::CALIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CALIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CALIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CALIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn calie_0(self) -> &'a mut W {
+        self.variant(CALIEW::CALIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn calie_1(self) -> &'a mut W {
+        self.variant(CALIEW::CALIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - LFXT oscillator fault flag interrupt enable"]
+    #[inline]
+    pub fn lfxtie(&self) -> LFXTIER {
+        LFXTIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - HFXT oscillator fault flag interrupt enable"]
+    #[inline]
+    pub fn hfxtie(&self) -> HFXTIER {
+        HFXTIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - HFXT2 oscillator fault flag interrupt enable"]
+    #[inline]
+    pub fn hfxt2ie(&self) -> HFXT2IER {
+        HFXT2IER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 6 - DCO external resistor open circuit fault flag interrupt enable."]
+    #[inline]
+    pub fn dcor_opnie(&self) -> DCOR_OPNIER {
+        DCOR_OPNIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 8 - Start fault counter interrupt enable LFXT"]
+    #[inline]
+    pub fn fcntlfie(&self) -> FCNTLFIER {
+        FCNTLFIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 9 - Start fault counter interrupt enable HFXT"]
+    #[inline]
+    pub fn fcnthfie(&self) -> FCNTHFIER {
+        FCNTHFIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 10 - Start fault counter interrupt enable HFXT2"]
+    #[inline]
+    pub fn fcnthf2ie(&self) -> FCNTHF2IER {
+        FCNTHF2IER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 12 - PLL out-of-lock interrupt enable"]
+    #[inline]
+    pub fn plloolie(&self) -> PLLOOLIER {
+        PLLOOLIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 13 - PLL loss-of-signal interrupt enable"]
+    #[inline]
+    pub fn plllosie(&self) -> PLLLOSIER {
+        PLLLOSIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 14 - PLL out-of-range interrupt enable"]
+    #[inline]
+    pub fn plloorie(&self) -> PLLOORIER {
+        PLLOORIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 15 - REFCNT period counter interrupt enable"]
+    #[inline]
+    pub fn calie(&self) -> CALIER {
+        CALIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - LFXT oscillator fault flag interrupt enable"]
+    #[inline]
+    pub fn lfxtie(&mut self) -> _LFXTIEW {
+        _LFXTIEW { w: self }
+    }
+    #[doc = "Bit 1 - HFXT oscillator fault flag interrupt enable"]
+    #[inline]
+    pub fn hfxtie(&mut self) -> _HFXTIEW {
+        _HFXTIEW { w: self }
+    }
+    #[doc = "Bit 2 - HFXT2 oscillator fault flag interrupt enable"]
+    #[inline]
+    pub fn hfxt2ie(&mut self) -> _HFXT2IEW {
+        _HFXT2IEW { w: self }
+    }
+    #[doc = "Bit 6 - DCO external resistor open circuit fault flag interrupt enable."]
+    #[inline]
+    pub fn dcor_opnie(&mut self) -> _DCOR_OPNIEW {
+        _DCOR_OPNIEW { w: self }
+    }
+    #[doc = "Bit 8 - Start fault counter interrupt enable LFXT"]
+    #[inline]
+    pub fn fcntlfie(&mut self) -> _FCNTLFIEW {
+        _FCNTLFIEW { w: self }
+    }
+    #[doc = "Bit 9 - Start fault counter interrupt enable HFXT"]
+    #[inline]
+    pub fn fcnthfie(&mut self) -> _FCNTHFIEW {
+        _FCNTHFIEW { w: self }
+    }
+    #[doc = "Bit 10 - Start fault counter interrupt enable HFXT2"]
+    #[inline]
+    pub fn fcnthf2ie(&mut self) -> _FCNTHF2IEW {
+        _FCNTHF2IEW { w: self }
+    }
+    #[doc = "Bit 12 - PLL out-of-lock interrupt enable"]
+    #[inline]
+    pub fn plloolie(&mut self) -> _PLLOOLIEW {
+        _PLLOOLIEW { w: self }
+    }
+    #[doc = "Bit 13 - PLL loss-of-signal interrupt enable"]
+    #[inline]
+    pub fn plllosie(&mut self) -> _PLLLOSIEW {
+        _PLLLOSIEW { w: self }
+    }
+    #[doc = "Bit 14 - PLL out-of-range interrupt enable"]
+    #[inline]
+    pub fn plloorie(&mut self) -> _PLLOORIEW {
+        _PLLOORIEW { w: self }
+    }
+    #[doc = "Bit 15 - REFCNT period counter interrupt enable"]
+    #[inline]
+    pub fn calie(&mut self) -> _CALIEW {
+        _CALIEW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/cs/csifg.rs b/example-source/msp432p401r/src/cs/csifg.rs
new file mode 100644
index 0000000..e130746
--- /dev/null
+++ b/example-source/msp432p401r/src/cs/csifg.rs
@@ -0,0 +1,692 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::CSIFG {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `LFXTIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LFXTIFGR {
+    #[doc = "No fault condition occurred after the last reset"]
+    LFXTIFG_0,
+    #[doc = "LFXT fault. A LFXT fault occurred after the last reset"]
+    LFXTIFG_1,
+}
+impl LFXTIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            LFXTIFGR::LFXTIFG_0 => false,
+            LFXTIFGR::LFXTIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> LFXTIFGR {
+        match value {
+            false => LFXTIFGR::LFXTIFG_0,
+            true => LFXTIFGR::LFXTIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `LFXTIFG_0`"]
+    #[inline]
+    pub fn is_lfxtifg_0(&self) -> bool {
+        *self == LFXTIFGR::LFXTIFG_0
+    }
+    #[doc = "Checks if the value of the field is `LFXTIFG_1`"]
+    #[inline]
+    pub fn is_lfxtifg_1(&self) -> bool {
+        *self == LFXTIFGR::LFXTIFG_1
+    }
+}
+#[doc = "Possible values of the field `HFXTIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HFXTIFGR {
+    #[doc = "No fault condition occurred after the last reset"]
+    HFXTIFG_0,
+    #[doc = "HFXT fault. A HFXT fault occurred after the last reset"]
+    HFXTIFG_1,
+}
+impl HFXTIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            HFXTIFGR::HFXTIFG_0 => false,
+            HFXTIFGR::HFXTIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> HFXTIFGR {
+        match value {
+            false => HFXTIFGR::HFXTIFG_0,
+            true => HFXTIFGR::HFXTIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `HFXTIFG_0`"]
+    #[inline]
+    pub fn is_hfxtifg_0(&self) -> bool {
+        *self == HFXTIFGR::HFXTIFG_0
+    }
+    #[doc = "Checks if the value of the field is `HFXTIFG_1`"]
+    #[inline]
+    pub fn is_hfxtifg_1(&self) -> bool {
+        *self == HFXTIFGR::HFXTIFG_1
+    }
+}
+#[doc = "Possible values of the field `HFXT2IFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HFXT2IFGR {
+    #[doc = "No fault condition occurred after the last reset"]
+    HFXT2IFG_0,
+    #[doc = "HFXT2 fault. A HFXT2 fault occurred after the last reset"]
+    HFXT2IFG_1,
+}
+impl HFXT2IFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            HFXT2IFGR::HFXT2IFG_0 => false,
+            HFXT2IFGR::HFXT2IFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> HFXT2IFGR {
+        match value {
+            false => HFXT2IFGR::HFXT2IFG_0,
+            true => HFXT2IFGR::HFXT2IFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `HFXT2IFG_0`"]
+    #[inline]
+    pub fn is_hfxt2ifg_0(&self) -> bool {
+        *self == HFXT2IFGR::HFXT2IFG_0
+    }
+    #[doc = "Checks if the value of the field is `HFXT2IFG_1`"]
+    #[inline]
+    pub fn is_hfxt2ifg_1(&self) -> bool {
+        *self == HFXT2IFGR::HFXT2IFG_1
+    }
+}
+#[doc = "Possible values of the field `DCOR_SHTIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DCOR_SHTIFGR {
+    #[doc = "DCO external resistor present"]
+    DCOR_SHTIFG_0,
+    #[doc = "DCO external resistor short circuit fault"]
+    DCOR_SHTIFG_1,
+}
+impl DCOR_SHTIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            DCOR_SHTIFGR::DCOR_SHTIFG_0 => false,
+            DCOR_SHTIFGR::DCOR_SHTIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> DCOR_SHTIFGR {
+        match value {
+            false => DCOR_SHTIFGR::DCOR_SHTIFG_0,
+            true => DCOR_SHTIFGR::DCOR_SHTIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DCOR_SHTIFG_0`"]
+    #[inline]
+    pub fn is_dcor_shtifg_0(&self) -> bool {
+        *self == DCOR_SHTIFGR::DCOR_SHTIFG_0
+    }
+    #[doc = "Checks if the value of the field is `DCOR_SHTIFG_1`"]
+    #[inline]
+    pub fn is_dcor_shtifg_1(&self) -> bool {
+        *self == DCOR_SHTIFGR::DCOR_SHTIFG_1
+    }
+}
+#[doc = "Possible values of the field `DCOR_OPNIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DCOR_OPNIFGR {
+    #[doc = "DCO external resistor present"]
+    DCOR_OPNIFG_0,
+    #[doc = "DCO external resistor open circuit fault"]
+    DCOR_OPNIFG_1,
+}
+impl DCOR_OPNIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            DCOR_OPNIFGR::DCOR_OPNIFG_0 => false,
+            DCOR_OPNIFGR::DCOR_OPNIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> DCOR_OPNIFGR {
+        match value {
+            false => DCOR_OPNIFGR::DCOR_OPNIFG_0,
+            true => DCOR_OPNIFGR::DCOR_OPNIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DCOR_OPNIFG_0`"]
+    #[inline]
+    pub fn is_dcor_opnifg_0(&self) -> bool {
+        *self == DCOR_OPNIFGR::DCOR_OPNIFG_0
+    }
+    #[doc = "Checks if the value of the field is `DCOR_OPNIFG_1`"]
+    #[inline]
+    pub fn is_dcor_opnifg_1(&self) -> bool {
+        *self == DCOR_OPNIFGR::DCOR_OPNIFG_1
+    }
+}
+#[doc = "Possible values of the field `FCNTLFIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FCNTLFIFGR {
+    #[doc = "Start counter not expired"]
+    FCNTLFIFG_0,
+    #[doc = "Start counter expired"]
+    FCNTLFIFG_1,
+}
+impl FCNTLFIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            FCNTLFIFGR::FCNTLFIFG_0 => false,
+            FCNTLFIFGR::FCNTLFIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> FCNTLFIFGR {
+        match value {
+            false => FCNTLFIFGR::FCNTLFIFG_0,
+            true => FCNTLFIFGR::FCNTLFIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `FCNTLFIFG_0`"]
+    #[inline]
+    pub fn is_fcntlfifg_0(&self) -> bool {
+        *self == FCNTLFIFGR::FCNTLFIFG_0
+    }
+    #[doc = "Checks if the value of the field is `FCNTLFIFG_1`"]
+    #[inline]
+    pub fn is_fcntlfifg_1(&self) -> bool {
+        *self == FCNTLFIFGR::FCNTLFIFG_1
+    }
+}
+#[doc = "Possible values of the field `FCNTHFIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FCNTHFIFGR {
+    #[doc = "Start counter not expired"]
+    FCNTHFIFG_0,
+    #[doc = "Start counter expired"]
+    FCNTHFIFG_1,
+}
+impl FCNTHFIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            FCNTHFIFGR::FCNTHFIFG_0 => false,
+            FCNTHFIFGR::FCNTHFIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> FCNTHFIFGR {
+        match value {
+            false => FCNTHFIFGR::FCNTHFIFG_0,
+            true => FCNTHFIFGR::FCNTHFIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `FCNTHFIFG_0`"]
+    #[inline]
+    pub fn is_fcnthfifg_0(&self) -> bool {
+        *self == FCNTHFIFGR::FCNTHFIFG_0
+    }
+    #[doc = "Checks if the value of the field is `FCNTHFIFG_1`"]
+    #[inline]
+    pub fn is_fcnthfifg_1(&self) -> bool {
+        *self == FCNTHFIFGR::FCNTHFIFG_1
+    }
+}
+#[doc = "Possible values of the field `FCNTHF2IFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FCNTHF2IFGR {
+    #[doc = "Start counter not expired"]
+    FCNTHF2IFG_0,
+    #[doc = "Start counter expired"]
+    FCNTHF2IFG_1,
+}
+impl FCNTHF2IFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            FCNTHF2IFGR::FCNTHF2IFG_0 => false,
+            FCNTHF2IFGR::FCNTHF2IFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> FCNTHF2IFGR {
+        match value {
+            false => FCNTHF2IFGR::FCNTHF2IFG_0,
+            true => FCNTHF2IFGR::FCNTHF2IFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `FCNTHF2IFG_0`"]
+    #[inline]
+    pub fn is_fcnthf2ifg_0(&self) -> bool {
+        *self == FCNTHF2IFGR::FCNTHF2IFG_0
+    }
+    #[doc = "Checks if the value of the field is `FCNTHF2IFG_1`"]
+    #[inline]
+    pub fn is_fcnthf2ifg_1(&self) -> bool {
+        *self == FCNTHF2IFGR::FCNTHF2IFG_1
+    }
+}
+#[doc = "Possible values of the field `PLLOOLIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PLLOOLIFGR {
+    #[doc = "No interrupt pending"]
+    PLLOOLIFG_0,
+    #[doc = "Interrupt pending"]
+    PLLOOLIFG_1,
+}
+impl PLLOOLIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            PLLOOLIFGR::PLLOOLIFG_0 => false,
+            PLLOOLIFGR::PLLOOLIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> PLLOOLIFGR {
+        match value {
+            false => PLLOOLIFGR::PLLOOLIFG_0,
+            true => PLLOOLIFGR::PLLOOLIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `PLLOOLIFG_0`"]
+    #[inline]
+    pub fn is_plloolifg_0(&self) -> bool {
+        *self == PLLOOLIFGR::PLLOOLIFG_0
+    }
+    #[doc = "Checks if the value of the field is `PLLOOLIFG_1`"]
+    #[inline]
+    pub fn is_plloolifg_1(&self) -> bool {
+        *self == PLLOOLIFGR::PLLOOLIFG_1
+    }
+}
+#[doc = "Possible values of the field `PLLLOSIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PLLLOSIFGR {
+    #[doc = "No interrupt pending"]
+    PLLLOSIFG_0,
+    #[doc = "Interrupt pending"]
+    PLLLOSIFG_1,
+}
+impl PLLLOSIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            PLLLOSIFGR::PLLLOSIFG_0 => false,
+            PLLLOSIFGR::PLLLOSIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> PLLLOSIFGR {
+        match value {
+            false => PLLLOSIFGR::PLLLOSIFG_0,
+            true => PLLLOSIFGR::PLLLOSIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `PLLLOSIFG_0`"]
+    #[inline]
+    pub fn is_plllosifg_0(&self) -> bool {
+        *self == PLLLOSIFGR::PLLLOSIFG_0
+    }
+    #[doc = "Checks if the value of the field is `PLLLOSIFG_1`"]
+    #[inline]
+    pub fn is_plllosifg_1(&self) -> bool {
+        *self == PLLLOSIFGR::PLLLOSIFG_1
+    }
+}
+#[doc = "Possible values of the field `PLLOORIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PLLOORIFGR {
+    #[doc = "No interrupt pending"]
+    PLLOORIFG_0,
+    #[doc = "Interrupt pending"]
+    PLLOORIFG_1,
+}
+impl PLLOORIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            PLLOORIFGR::PLLOORIFG_0 => false,
+            PLLOORIFGR::PLLOORIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> PLLOORIFGR {
+        match value {
+            false => PLLOORIFGR::PLLOORIFG_0,
+            true => PLLOORIFGR::PLLOORIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `PLLOORIFG_0`"]
+    #[inline]
+    pub fn is_plloorifg_0(&self) -> bool {
+        *self == PLLOORIFGR::PLLOORIFG_0
+    }
+    #[doc = "Checks if the value of the field is `PLLOORIFG_1`"]
+    #[inline]
+    pub fn is_plloorifg_1(&self) -> bool {
+        *self == PLLOORIFGR::PLLOORIFG_1
+    }
+}
+#[doc = "Possible values of the field `CALIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CALIFGR {
+    #[doc = "REFCNT period counter not expired"]
+    CALIFG_0,
+    #[doc = "REFCNT period counter expired"]
+    CALIFG_1,
+}
+impl CALIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CALIFGR::CALIFG_0 => false,
+            CALIFGR::CALIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CALIFGR {
+        match value {
+            false => CALIFGR::CALIFG_0,
+            true => CALIFGR::CALIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CALIFG_0`"]
+    #[inline]
+    pub fn is_califg_0(&self) -> bool {
+        *self == CALIFGR::CALIFG_0
+    }
+    #[doc = "Checks if the value of the field is `CALIFG_1`"]
+    #[inline]
+    pub fn is_califg_1(&self) -> bool {
+        *self == CALIFGR::CALIFG_1
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - LFXT oscillator fault flag"]
+    #[inline]
+    pub fn lfxtifg(&self) -> LFXTIFGR {
+        LFXTIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - HFXT oscillator fault flag"]
+    #[inline]
+    pub fn hfxtifg(&self) -> HFXTIFGR {
+        HFXTIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - HFXT2 oscillator fault flag"]
+    #[inline]
+    pub fn hfxt2ifg(&self) -> HFXT2IFGR {
+        HFXT2IFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 5 - DCO external resistor short circuit fault flag."]
+    #[inline]
+    pub fn dcor_shtifg(&self) -> DCOR_SHTIFGR {
+        DCOR_SHTIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 6 - DCO external resistor open circuit fault flag."]
+    #[inline]
+    pub fn dcor_opnifg(&self) -> DCOR_OPNIFGR {
+        DCOR_OPNIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 8 - Start fault counter interrupt flag LFXT"]
+    #[inline]
+    pub fn fcntlfifg(&self) -> FCNTLFIFGR {
+        FCNTLFIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 9 - Start fault counter interrupt flag HFXT"]
+    #[inline]
+    pub fn fcnthfifg(&self) -> FCNTHFIFGR {
+        FCNTHFIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 11 - Start fault counter interrupt flag HFXT2"]
+    #[inline]
+    pub fn fcnthf2ifg(&self) -> FCNTHF2IFGR {
+        FCNTHF2IFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 12 - PLL out-of-lock interrupt flag"]
+    #[inline]
+    pub fn plloolifg(&self) -> PLLOOLIFGR {
+        PLLOOLIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 13 - PLL loss-of-signal interrupt flag"]
+    #[inline]
+    pub fn plllosifg(&self) -> PLLLOSIFGR {
+        PLLLOSIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 14 - PLL out-of-range interrupt flag"]
+    #[inline]
+    pub fn plloorifg(&self) -> PLLOORIFGR {
+        PLLOORIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 15 - REFCNT period counter expired"]
+    #[inline]
+    pub fn califg(&self) -> CALIFGR {
+        CALIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/cs/cskey.rs b/example-source/msp432p401r/src/cs/cskey.rs
new file mode 100644
index 0000000..4e38100
--- /dev/null
+++ b/example-source/msp432p401r/src/cs/cskey.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CSKEY {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CSKEYR {
+    bits: u16,
+}
+impl CSKEYR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CSKEYW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CSKEYW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Write xxxx_695Ah to unlock"]
+    #[inline]
+    pub fn cskey(&self) -> CSKEYR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        CSKEYR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 42390 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Write xxxx_695Ah to unlock"]
+    #[inline]
+    pub fn cskey(&mut self) -> _CSKEYW {
+        _CSKEYW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/cs/cssetifg.rs b/example-source/msp432p401r/src/cs/cssetifg.rs
new file mode 100644
index 0000000..92242d3
--- /dev/null
+++ b/example-source/msp432p401r/src/cs/cssetifg.rs
@@ -0,0 +1,722 @@
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CSSETIFG {
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+}
+#[doc = "Values that can be written to the field `SET_LFXTIFG`"]
+pub enum SET_LFXTIFGW {
+    #[doc = "No effect"]
+    SET_LFXTIFG_0,
+    #[doc = "Set pending interrupt flag"]
+    SET_LFXTIFG_1,
+}
+impl SET_LFXTIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            SET_LFXTIFGW::SET_LFXTIFG_0 => false,
+            SET_LFXTIFGW::SET_LFXTIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SET_LFXTIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SET_LFXTIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SET_LFXTIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No effect"]
+    #[inline]
+    pub fn set_lfxtifg_0(self) -> &'a mut W {
+        self.variant(SET_LFXTIFGW::SET_LFXTIFG_0)
+    }
+    #[doc = "Set pending interrupt flag"]
+    #[inline]
+    pub fn set_lfxtifg_1(self) -> &'a mut W {
+        self.variant(SET_LFXTIFGW::SET_LFXTIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `SET_HFXTIFG`"]
+pub enum SET_HFXTIFGW {
+    #[doc = "No effect"]
+    SET_HFXTIFG_0,
+    #[doc = "Set pending interrupt flag"]
+    SET_HFXTIFG_1,
+}
+impl SET_HFXTIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            SET_HFXTIFGW::SET_HFXTIFG_0 => false,
+            SET_HFXTIFGW::SET_HFXTIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SET_HFXTIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SET_HFXTIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SET_HFXTIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No effect"]
+    #[inline]
+    pub fn set_hfxtifg_0(self) -> &'a mut W {
+        self.variant(SET_HFXTIFGW::SET_HFXTIFG_0)
+    }
+    #[doc = "Set pending interrupt flag"]
+    #[inline]
+    pub fn set_hfxtifg_1(self) -> &'a mut W {
+        self.variant(SET_HFXTIFGW::SET_HFXTIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `SET_HFXT2IFG`"]
+pub enum SET_HFXT2IFGW {
+    #[doc = "No effect"]
+    SET_HFXT2IFG_0,
+    #[doc = "Set pending interrupt flag"]
+    SET_HFXT2IFG_1,
+}
+impl SET_HFXT2IFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            SET_HFXT2IFGW::SET_HFXT2IFG_0 => false,
+            SET_HFXT2IFGW::SET_HFXT2IFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SET_HFXT2IFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SET_HFXT2IFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SET_HFXT2IFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No effect"]
+    #[inline]
+    pub fn set_hfxt2ifg_0(self) -> &'a mut W {
+        self.variant(SET_HFXT2IFGW::SET_HFXT2IFG_0)
+    }
+    #[doc = "Set pending interrupt flag"]
+    #[inline]
+    pub fn set_hfxt2ifg_1(self) -> &'a mut W {
+        self.variant(SET_HFXT2IFGW::SET_HFXT2IFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `SET_DCOR_OPNIFG`"]
+pub enum SET_DCOR_OPNIFGW {
+    #[doc = "No effect"]
+    SET_DCOR_OPNIFG_0,
+    #[doc = "Set pending interrupt flag"]
+    SET_DCOR_OPNIFG_1,
+}
+impl SET_DCOR_OPNIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            SET_DCOR_OPNIFGW::SET_DCOR_OPNIFG_0 => false,
+            SET_DCOR_OPNIFGW::SET_DCOR_OPNIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SET_DCOR_OPNIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SET_DCOR_OPNIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SET_DCOR_OPNIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No effect"]
+    #[inline]
+    pub fn set_dcor_opnifg_0(self) -> &'a mut W {
+        self.variant(SET_DCOR_OPNIFGW::SET_DCOR_OPNIFG_0)
+    }
+    #[doc = "Set pending interrupt flag"]
+    #[inline]
+    pub fn set_dcor_opnifg_1(self) -> &'a mut W {
+        self.variant(SET_DCOR_OPNIFGW::SET_DCOR_OPNIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `SET_CALIFG`"]
+pub enum SET_CALIFGW {
+    #[doc = "No effect"]
+    SET_CALIFG_0,
+    #[doc = "Set pending interrupt flag"]
+    SET_CALIFG_1,
+}
+impl SET_CALIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            SET_CALIFGW::SET_CALIFG_0 => false,
+            SET_CALIFGW::SET_CALIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SET_CALIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SET_CALIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SET_CALIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No effect"]
+    #[inline]
+    pub fn set_califg_0(self) -> &'a mut W {
+        self.variant(SET_CALIFGW::SET_CALIFG_0)
+    }
+    #[doc = "Set pending interrupt flag"]
+    #[inline]
+    pub fn set_califg_1(self) -> &'a mut W {
+        self.variant(SET_CALIFGW::SET_CALIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `SET_FCNTHFIFG`"]
+pub enum SET_FCNTHFIFGW {
+    #[doc = "No effect"]
+    SET_FCNTHFIFG_0,
+    #[doc = "Set pending interrupt flag"]
+    SET_FCNTHFIFG_1,
+}
+impl SET_FCNTHFIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            SET_FCNTHFIFGW::SET_FCNTHFIFG_0 => false,
+            SET_FCNTHFIFGW::SET_FCNTHFIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SET_FCNTHFIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SET_FCNTHFIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SET_FCNTHFIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No effect"]
+    #[inline]
+    pub fn set_fcnthfifg_0(self) -> &'a mut W {
+        self.variant(SET_FCNTHFIFGW::SET_FCNTHFIFG_0)
+    }
+    #[doc = "Set pending interrupt flag"]
+    #[inline]
+    pub fn set_fcnthfifg_1(self) -> &'a mut W {
+        self.variant(SET_FCNTHFIFGW::SET_FCNTHFIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `SET_FCNTHF2IFG`"]
+pub enum SET_FCNTHF2IFGW {
+    #[doc = "No effect"]
+    SET_FCNTHF2IFG_0,
+    #[doc = "Set pending interrupt flag"]
+    SET_FCNTHF2IFG_1,
+}
+impl SET_FCNTHF2IFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            SET_FCNTHF2IFGW::SET_FCNTHF2IFG_0 => false,
+            SET_FCNTHF2IFGW::SET_FCNTHF2IFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SET_FCNTHF2IFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SET_FCNTHF2IFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SET_FCNTHF2IFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No effect"]
+    #[inline]
+    pub fn set_fcnthf2ifg_0(self) -> &'a mut W {
+        self.variant(SET_FCNTHF2IFGW::SET_FCNTHF2IFG_0)
+    }
+    #[doc = "Set pending interrupt flag"]
+    #[inline]
+    pub fn set_fcnthf2ifg_1(self) -> &'a mut W {
+        self.variant(SET_FCNTHF2IFGW::SET_FCNTHF2IFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `SET_FCNTLFIFG`"]
+pub enum SET_FCNTLFIFGW {
+    #[doc = "No effect"]
+    SET_FCNTLFIFG_0,
+    #[doc = "Set pending interrupt flag"]
+    SET_FCNTLFIFG_1,
+}
+impl SET_FCNTLFIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            SET_FCNTLFIFGW::SET_FCNTLFIFG_0 => false,
+            SET_FCNTLFIFGW::SET_FCNTLFIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SET_FCNTLFIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SET_FCNTLFIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SET_FCNTLFIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No effect"]
+    #[inline]
+    pub fn set_fcntlfifg_0(self) -> &'a mut W {
+        self.variant(SET_FCNTLFIFGW::SET_FCNTLFIFG_0)
+    }
+    #[doc = "Set pending interrupt flag"]
+    #[inline]
+    pub fn set_fcntlfifg_1(self) -> &'a mut W {
+        self.variant(SET_FCNTLFIFGW::SET_FCNTLFIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `SET_PLLOOLIFG`"]
+pub enum SET_PLLOOLIFGW {
+    #[doc = "No effect"]
+    SET_PLLOOLIFG_0,
+    #[doc = "Set pending interrupt flag"]
+    SET_PLLOOLIFG_1,
+}
+impl SET_PLLOOLIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            SET_PLLOOLIFGW::SET_PLLOOLIFG_0 => false,
+            SET_PLLOOLIFGW::SET_PLLOOLIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SET_PLLOOLIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SET_PLLOOLIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SET_PLLOOLIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No effect"]
+    #[inline]
+    pub fn set_plloolifg_0(self) -> &'a mut W {
+        self.variant(SET_PLLOOLIFGW::SET_PLLOOLIFG_0)
+    }
+    #[doc = "Set pending interrupt flag"]
+    #[inline]
+    pub fn set_plloolifg_1(self) -> &'a mut W {
+        self.variant(SET_PLLOOLIFGW::SET_PLLOOLIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `SET_PLLLOSIFG`"]
+pub enum SET_PLLLOSIFGW {
+    #[doc = "No effect"]
+    SET_PLLLOSIFG_0,
+    #[doc = "Set pending interrupt flag"]
+    SET_PLLLOSIFG_1,
+}
+impl SET_PLLLOSIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            SET_PLLLOSIFGW::SET_PLLLOSIFG_0 => false,
+            SET_PLLLOSIFGW::SET_PLLLOSIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SET_PLLLOSIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SET_PLLLOSIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SET_PLLLOSIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No effect"]
+    #[inline]
+    pub fn set_plllosifg_0(self) -> &'a mut W {
+        self.variant(SET_PLLLOSIFGW::SET_PLLLOSIFG_0)
+    }
+    #[doc = "Set pending interrupt flag"]
+    #[inline]
+    pub fn set_plllosifg_1(self) -> &'a mut W {
+        self.variant(SET_PLLLOSIFGW::SET_PLLLOSIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `SET_PLLOORIFG`"]
+pub enum SET_PLLOORIFGW {
+    #[doc = "No effect"]
+    SET_PLLOORIFG_0,
+    #[doc = "Set pending interrupt flag"]
+    SET_PLLOORIFG_1,
+}
+impl SET_PLLOORIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            SET_PLLOORIFGW::SET_PLLOORIFG_0 => false,
+            SET_PLLOORIFGW::SET_PLLOORIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SET_PLLOORIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SET_PLLOORIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SET_PLLOORIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No effect"]
+    #[inline]
+    pub fn set_plloorifg_0(self) -> &'a mut W {
+        self.variant(SET_PLLOORIFGW::SET_PLLOORIFG_0)
+    }
+    #[doc = "Set pending interrupt flag"]
+    #[inline]
+    pub fn set_plloorifg_1(self) -> &'a mut W {
+        self.variant(SET_PLLOORIFGW::SET_PLLOORIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Set LFXT oscillator fault interrupt flag"]
+    #[inline]
+    pub fn set_lfxtifg(&mut self) -> _SET_LFXTIFGW {
+        _SET_LFXTIFGW { w: self }
+    }
+    #[doc = "Bit 1 - Set HFXT oscillator fault interrupt flag"]
+    #[inline]
+    pub fn set_hfxtifg(&mut self) -> _SET_HFXTIFGW {
+        _SET_HFXTIFGW { w: self }
+    }
+    #[doc = "Bit 2 - Set HFXT2 oscillator fault interrupt flag"]
+    #[inline]
+    pub fn set_hfxt2ifg(&mut self) -> _SET_HFXT2IFGW {
+        _SET_HFXT2IFGW { w: self }
+    }
+    #[doc = "Bit 6 - Set DCO external resistor open circuit fault interrupt flag."]
+    #[inline]
+    pub fn set_dcor_opnifg(&mut self) -> _SET_DCOR_OPNIFGW {
+        _SET_DCOR_OPNIFGW { w: self }
+    }
+    #[doc = "Bit 15 - REFCNT period counter set interrupt flag"]
+    #[inline]
+    pub fn set_califg(&mut self) -> _SET_CALIFGW {
+        _SET_CALIFGW { w: self }
+    }
+    #[doc = "Bit 9 - Start fault counter set interrupt flag HFXT"]
+    #[inline]
+    pub fn set_fcnthfifg(&mut self) -> _SET_FCNTHFIFGW {
+        _SET_FCNTHFIFGW { w: self }
+    }
+    #[doc = "Bit 10 - Start fault counter set interrupt flag HFXT2"]
+    #[inline]
+    pub fn set_fcnthf2ifg(&mut self) -> _SET_FCNTHF2IFGW {
+        _SET_FCNTHF2IFGW { w: self }
+    }
+    #[doc = "Bit 8 - Start fault counter set interrupt flag LFXT"]
+    #[inline]
+    pub fn set_fcntlfifg(&mut self) -> _SET_FCNTLFIFGW {
+        _SET_FCNTLFIFGW { w: self }
+    }
+    #[doc = "Bit 12 - PLL out-of-lock set interrupt flag"]
+    #[inline]
+    pub fn set_plloolifg(&mut self) -> _SET_PLLOOLIFGW {
+        _SET_PLLOOLIFGW { w: self }
+    }
+    #[doc = "Bit 13 - PLL loss-of-signal set interrupt flag"]
+    #[inline]
+    pub fn set_plllosifg(&mut self) -> _SET_PLLLOSIFGW {
+        _SET_PLLLOSIFGW { w: self }
+    }
+    #[doc = "Bit 14 - PLL out-of-range set interrupt flag"]
+    #[inline]
+    pub fn set_plloorifg(&mut self) -> _SET_PLLOORIFGW {
+        _SET_PLLOORIFGW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/cs/csstat.rs b/example-source/msp432p401r/src/cs/csstat.rs
new file mode 100644
index 0000000..6002995
--- /dev/null
+++ b/example-source/msp432p401r/src/cs/csstat.rs
@@ -0,0 +1,1196 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::CSSTAT {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `DCO_ON`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DCO_ONR {
+    #[doc = "Inactive"]
+    DCO_ON_0,
+    #[doc = "Active"]
+    DCO_ON_1,
+}
+impl DCO_ONR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            DCO_ONR::DCO_ON_0 => false,
+            DCO_ONR::DCO_ON_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> DCO_ONR {
+        match value {
+            false => DCO_ONR::DCO_ON_0,
+            true => DCO_ONR::DCO_ON_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DCO_ON_0`"]
+    #[inline]
+    pub fn is_dco_on_0(&self) -> bool {
+        *self == DCO_ONR::DCO_ON_0
+    }
+    #[doc = "Checks if the value of the field is `DCO_ON_1`"]
+    #[inline]
+    pub fn is_dco_on_1(&self) -> bool {
+        *self == DCO_ONR::DCO_ON_1
+    }
+}
+#[doc = "Possible values of the field `DCOBIAS_ON`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DCOBIAS_ONR {
+    #[doc = "Inactive"]
+    DCOBIAS_ON_0,
+    #[doc = "Active"]
+    DCOBIAS_ON_1,
+}
+impl DCOBIAS_ONR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            DCOBIAS_ONR::DCOBIAS_ON_0 => false,
+            DCOBIAS_ONR::DCOBIAS_ON_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> DCOBIAS_ONR {
+        match value {
+            false => DCOBIAS_ONR::DCOBIAS_ON_0,
+            true => DCOBIAS_ONR::DCOBIAS_ON_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DCOBIAS_ON_0`"]
+    #[inline]
+    pub fn is_dcobias_on_0(&self) -> bool {
+        *self == DCOBIAS_ONR::DCOBIAS_ON_0
+    }
+    #[doc = "Checks if the value of the field is `DCOBIAS_ON_1`"]
+    #[inline]
+    pub fn is_dcobias_on_1(&self) -> bool {
+        *self == DCOBIAS_ONR::DCOBIAS_ON_1
+    }
+}
+#[doc = "Possible values of the field `HFXT_ON`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HFXT_ONR {
+    #[doc = "Inactive"]
+    HFXT_ON_0,
+    #[doc = "Active"]
+    HFXT_ON_1,
+}
+impl HFXT_ONR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            HFXT_ONR::HFXT_ON_0 => false,
+            HFXT_ONR::HFXT_ON_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> HFXT_ONR {
+        match value {
+            false => HFXT_ONR::HFXT_ON_0,
+            true => HFXT_ONR::HFXT_ON_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `HFXT_ON_0`"]
+    #[inline]
+    pub fn is_hfxt_on_0(&self) -> bool {
+        *self == HFXT_ONR::HFXT_ON_0
+    }
+    #[doc = "Checks if the value of the field is `HFXT_ON_1`"]
+    #[inline]
+    pub fn is_hfxt_on_1(&self) -> bool {
+        *self == HFXT_ONR::HFXT_ON_1
+    }
+}
+#[doc = "Possible values of the field `HFXT2_ON`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HFXT2_ONR {
+    #[doc = "Inactive"]
+    HFXT2_ON_0,
+    #[doc = "Active"]
+    HFXT2_ON_1,
+}
+impl HFXT2_ONR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            HFXT2_ONR::HFXT2_ON_0 => false,
+            HFXT2_ONR::HFXT2_ON_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> HFXT2_ONR {
+        match value {
+            false => HFXT2_ONR::HFXT2_ON_0,
+            true => HFXT2_ONR::HFXT2_ON_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `HFXT2_ON_0`"]
+    #[inline]
+    pub fn is_hfxt2_on_0(&self) -> bool {
+        *self == HFXT2_ONR::HFXT2_ON_0
+    }
+    #[doc = "Checks if the value of the field is `HFXT2_ON_1`"]
+    #[inline]
+    pub fn is_hfxt2_on_1(&self) -> bool {
+        *self == HFXT2_ONR::HFXT2_ON_1
+    }
+}
+#[doc = "Possible values of the field `MODOSC_ON`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum MODOSC_ONR {
+    #[doc = "Inactive"]
+    MODOSC_ON_0,
+    #[doc = "Active"]
+    MODOSC_ON_1,
+}
+impl MODOSC_ONR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            MODOSC_ONR::MODOSC_ON_0 => false,
+            MODOSC_ONR::MODOSC_ON_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> MODOSC_ONR {
+        match value {
+            false => MODOSC_ONR::MODOSC_ON_0,
+            true => MODOSC_ONR::MODOSC_ON_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `MODOSC_ON_0`"]
+    #[inline]
+    pub fn is_modosc_on_0(&self) -> bool {
+        *self == MODOSC_ONR::MODOSC_ON_0
+    }
+    #[doc = "Checks if the value of the field is `MODOSC_ON_1`"]
+    #[inline]
+    pub fn is_modosc_on_1(&self) -> bool {
+        *self == MODOSC_ONR::MODOSC_ON_1
+    }
+}
+#[doc = "Possible values of the field `VLO_ON`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum VLO_ONR {
+    #[doc = "Inactive"]
+    VLO_ON_0,
+    #[doc = "Active"]
+    VLO_ON_1,
+}
+impl VLO_ONR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            VLO_ONR::VLO_ON_0 => false,
+            VLO_ONR::VLO_ON_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> VLO_ONR {
+        match value {
+            false => VLO_ONR::VLO_ON_0,
+            true => VLO_ONR::VLO_ON_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `VLO_ON_0`"]
+    #[inline]
+    pub fn is_vlo_on_0(&self) -> bool {
+        *self == VLO_ONR::VLO_ON_0
+    }
+    #[doc = "Checks if the value of the field is `VLO_ON_1`"]
+    #[inline]
+    pub fn is_vlo_on_1(&self) -> bool {
+        *self == VLO_ONR::VLO_ON_1
+    }
+}
+#[doc = "Possible values of the field `LFXT_ON`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LFXT_ONR {
+    #[doc = "Inactive"]
+    LFXT_ON_0,
+    #[doc = "Active"]
+    LFXT_ON_1,
+}
+impl LFXT_ONR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            LFXT_ONR::LFXT_ON_0 => false,
+            LFXT_ONR::LFXT_ON_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> LFXT_ONR {
+        match value {
+            false => LFXT_ONR::LFXT_ON_0,
+            true => LFXT_ONR::LFXT_ON_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `LFXT_ON_0`"]
+    #[inline]
+    pub fn is_lfxt_on_0(&self) -> bool {
+        *self == LFXT_ONR::LFXT_ON_0
+    }
+    #[doc = "Checks if the value of the field is `LFXT_ON_1`"]
+    #[inline]
+    pub fn is_lfxt_on_1(&self) -> bool {
+        *self == LFXT_ONR::LFXT_ON_1
+    }
+}
+#[doc = "Possible values of the field `REFO_ON`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum REFO_ONR {
+    #[doc = "Inactive"]
+    REFO_ON_0,
+    #[doc = "Active"]
+    REFO_ON_1,
+}
+impl REFO_ONR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            REFO_ONR::REFO_ON_0 => false,
+            REFO_ONR::REFO_ON_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> REFO_ONR {
+        match value {
+            false => REFO_ONR::REFO_ON_0,
+            true => REFO_ONR::REFO_ON_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `REFO_ON_0`"]
+    #[inline]
+    pub fn is_refo_on_0(&self) -> bool {
+        *self == REFO_ONR::REFO_ON_0
+    }
+    #[doc = "Checks if the value of the field is `REFO_ON_1`"]
+    #[inline]
+    pub fn is_refo_on_1(&self) -> bool {
+        *self == REFO_ONR::REFO_ON_1
+    }
+}
+#[doc = "Possible values of the field `ACLK_ON`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ACLK_ONR {
+    #[doc = "Inactive"]
+    ACLK_ON_0,
+    #[doc = "Active"]
+    ACLK_ON_1,
+}
+impl ACLK_ONR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ACLK_ONR::ACLK_ON_0 => false,
+            ACLK_ONR::ACLK_ON_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ACLK_ONR {
+        match value {
+            false => ACLK_ONR::ACLK_ON_0,
+            true => ACLK_ONR::ACLK_ON_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ACLK_ON_0`"]
+    #[inline]
+    pub fn is_aclk_on_0(&self) -> bool {
+        *self == ACLK_ONR::ACLK_ON_0
+    }
+    #[doc = "Checks if the value of the field is `ACLK_ON_1`"]
+    #[inline]
+    pub fn is_aclk_on_1(&self) -> bool {
+        *self == ACLK_ONR::ACLK_ON_1
+    }
+}
+#[doc = "Possible values of the field `MCLK_ON`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum MCLK_ONR {
+    #[doc = "Inactive"]
+    MCLK_ON_0,
+    #[doc = "Active"]
+    MCLK_ON_1,
+}
+impl MCLK_ONR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            MCLK_ONR::MCLK_ON_0 => false,
+            MCLK_ONR::MCLK_ON_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> MCLK_ONR {
+        match value {
+            false => MCLK_ONR::MCLK_ON_0,
+            true => MCLK_ONR::MCLK_ON_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `MCLK_ON_0`"]
+    #[inline]
+    pub fn is_mclk_on_0(&self) -> bool {
+        *self == MCLK_ONR::MCLK_ON_0
+    }
+    #[doc = "Checks if the value of the field is `MCLK_ON_1`"]
+    #[inline]
+    pub fn is_mclk_on_1(&self) -> bool {
+        *self == MCLK_ONR::MCLK_ON_1
+    }
+}
+#[doc = "Possible values of the field `HSMCLK_ON`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HSMCLK_ONR {
+    #[doc = "Inactive"]
+    HSMCLK_ON_0,
+    #[doc = "Active"]
+    HSMCLK_ON_1,
+}
+impl HSMCLK_ONR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            HSMCLK_ONR::HSMCLK_ON_0 => false,
+            HSMCLK_ONR::HSMCLK_ON_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> HSMCLK_ONR {
+        match value {
+            false => HSMCLK_ONR::HSMCLK_ON_0,
+            true => HSMCLK_ONR::HSMCLK_ON_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `HSMCLK_ON_0`"]
+    #[inline]
+    pub fn is_hsmclk_on_0(&self) -> bool {
+        *self == HSMCLK_ONR::HSMCLK_ON_0
+    }
+    #[doc = "Checks if the value of the field is `HSMCLK_ON_1`"]
+    #[inline]
+    pub fn is_hsmclk_on_1(&self) -> bool {
+        *self == HSMCLK_ONR::HSMCLK_ON_1
+    }
+}
+#[doc = "Possible values of the field `SMCLK_ON`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SMCLK_ONR {
+    #[doc = "Inactive"]
+    SMCLK_ON_0,
+    #[doc = "Active"]
+    SMCLK_ON_1,
+}
+impl SMCLK_ONR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            SMCLK_ONR::SMCLK_ON_0 => false,
+            SMCLK_ONR::SMCLK_ON_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> SMCLK_ONR {
+        match value {
+            false => SMCLK_ONR::SMCLK_ON_0,
+            true => SMCLK_ONR::SMCLK_ON_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SMCLK_ON_0`"]
+    #[inline]
+    pub fn is_smclk_on_0(&self) -> bool {
+        *self == SMCLK_ONR::SMCLK_ON_0
+    }
+    #[doc = "Checks if the value of the field is `SMCLK_ON_1`"]
+    #[inline]
+    pub fn is_smclk_on_1(&self) -> bool {
+        *self == SMCLK_ONR::SMCLK_ON_1
+    }
+}
+#[doc = "Possible values of the field `MODCLK_ON`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum MODCLK_ONR {
+    #[doc = "Inactive"]
+    MODCLK_ON_0,
+    #[doc = "Active"]
+    MODCLK_ON_1,
+}
+impl MODCLK_ONR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            MODCLK_ONR::MODCLK_ON_0 => false,
+            MODCLK_ONR::MODCLK_ON_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> MODCLK_ONR {
+        match value {
+            false => MODCLK_ONR::MODCLK_ON_0,
+            true => MODCLK_ONR::MODCLK_ON_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `MODCLK_ON_0`"]
+    #[inline]
+    pub fn is_modclk_on_0(&self) -> bool {
+        *self == MODCLK_ONR::MODCLK_ON_0
+    }
+    #[doc = "Checks if the value of the field is `MODCLK_ON_1`"]
+    #[inline]
+    pub fn is_modclk_on_1(&self) -> bool {
+        *self == MODCLK_ONR::MODCLK_ON_1
+    }
+}
+#[doc = "Possible values of the field `VLOCLK_ON`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum VLOCLK_ONR {
+    #[doc = "Inactive"]
+    VLOCLK_ON_0,
+    #[doc = "Active"]
+    VLOCLK_ON_1,
+}
+impl VLOCLK_ONR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            VLOCLK_ONR::VLOCLK_ON_0 => false,
+            VLOCLK_ONR::VLOCLK_ON_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> VLOCLK_ONR {
+        match value {
+            false => VLOCLK_ONR::VLOCLK_ON_0,
+            true => VLOCLK_ONR::VLOCLK_ON_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `VLOCLK_ON_0`"]
+    #[inline]
+    pub fn is_vloclk_on_0(&self) -> bool {
+        *self == VLOCLK_ONR::VLOCLK_ON_0
+    }
+    #[doc = "Checks if the value of the field is `VLOCLK_ON_1`"]
+    #[inline]
+    pub fn is_vloclk_on_1(&self) -> bool {
+        *self == VLOCLK_ONR::VLOCLK_ON_1
+    }
+}
+#[doc = "Possible values of the field `LFXTCLK_ON`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LFXTCLK_ONR {
+    #[doc = "Inactive"]
+    LFXTCLK_ON_0,
+    #[doc = "Active"]
+    LFXTCLK_ON_1,
+}
+impl LFXTCLK_ONR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            LFXTCLK_ONR::LFXTCLK_ON_0 => false,
+            LFXTCLK_ONR::LFXTCLK_ON_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> LFXTCLK_ONR {
+        match value {
+            false => LFXTCLK_ONR::LFXTCLK_ON_0,
+            true => LFXTCLK_ONR::LFXTCLK_ON_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `LFXTCLK_ON_0`"]
+    #[inline]
+    pub fn is_lfxtclk_on_0(&self) -> bool {
+        *self == LFXTCLK_ONR::LFXTCLK_ON_0
+    }
+    #[doc = "Checks if the value of the field is `LFXTCLK_ON_1`"]
+    #[inline]
+    pub fn is_lfxtclk_on_1(&self) -> bool {
+        *self == LFXTCLK_ONR::LFXTCLK_ON_1
+    }
+}
+#[doc = "Possible values of the field `REFOCLK_ON`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum REFOCLK_ONR {
+    #[doc = "Inactive"]
+    REFOCLK_ON_0,
+    #[doc = "Active"]
+    REFOCLK_ON_1,
+}
+impl REFOCLK_ONR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            REFOCLK_ONR::REFOCLK_ON_0 => false,
+            REFOCLK_ONR::REFOCLK_ON_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> REFOCLK_ONR {
+        match value {
+            false => REFOCLK_ONR::REFOCLK_ON_0,
+            true => REFOCLK_ONR::REFOCLK_ON_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `REFOCLK_ON_0`"]
+    #[inline]
+    pub fn is_refoclk_on_0(&self) -> bool {
+        *self == REFOCLK_ONR::REFOCLK_ON_0
+    }
+    #[doc = "Checks if the value of the field is `REFOCLK_ON_1`"]
+    #[inline]
+    pub fn is_refoclk_on_1(&self) -> bool {
+        *self == REFOCLK_ONR::REFOCLK_ON_1
+    }
+}
+#[doc = "Possible values of the field `ACLK_READY`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ACLK_READYR {
+    #[doc = "Not ready"]
+    ACLK_READY_0,
+    #[doc = "Ready"]
+    ACLK_READY_1,
+}
+impl ACLK_READYR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ACLK_READYR::ACLK_READY_0 => false,
+            ACLK_READYR::ACLK_READY_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ACLK_READYR {
+        match value {
+            false => ACLK_READYR::ACLK_READY_0,
+            true => ACLK_READYR::ACLK_READY_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ACLK_READY_0`"]
+    #[inline]
+    pub fn is_aclk_ready_0(&self) -> bool {
+        *self == ACLK_READYR::ACLK_READY_0
+    }
+    #[doc = "Checks if the value of the field is `ACLK_READY_1`"]
+    #[inline]
+    pub fn is_aclk_ready_1(&self) -> bool {
+        *self == ACLK_READYR::ACLK_READY_1
+    }
+}
+#[doc = "Possible values of the field `MCLK_READY`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum MCLK_READYR {
+    #[doc = "Not ready"]
+    MCLK_READY_0,
+    #[doc = "Ready"]
+    MCLK_READY_1,
+}
+impl MCLK_READYR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            MCLK_READYR::MCLK_READY_0 => false,
+            MCLK_READYR::MCLK_READY_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> MCLK_READYR {
+        match value {
+            false => MCLK_READYR::MCLK_READY_0,
+            true => MCLK_READYR::MCLK_READY_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `MCLK_READY_0`"]
+    #[inline]
+    pub fn is_mclk_ready_0(&self) -> bool {
+        *self == MCLK_READYR::MCLK_READY_0
+    }
+    #[doc = "Checks if the value of the field is `MCLK_READY_1`"]
+    #[inline]
+    pub fn is_mclk_ready_1(&self) -> bool {
+        *self == MCLK_READYR::MCLK_READY_1
+    }
+}
+#[doc = "Possible values of the field `HSMCLK_READY`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HSMCLK_READYR {
+    #[doc = "Not ready"]
+    HSMCLK_READY_0,
+    #[doc = "Ready"]
+    HSMCLK_READY_1,
+}
+impl HSMCLK_READYR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            HSMCLK_READYR::HSMCLK_READY_0 => false,
+            HSMCLK_READYR::HSMCLK_READY_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> HSMCLK_READYR {
+        match value {
+            false => HSMCLK_READYR::HSMCLK_READY_0,
+            true => HSMCLK_READYR::HSMCLK_READY_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `HSMCLK_READY_0`"]
+    #[inline]
+    pub fn is_hsmclk_ready_0(&self) -> bool {
+        *self == HSMCLK_READYR::HSMCLK_READY_0
+    }
+    #[doc = "Checks if the value of the field is `HSMCLK_READY_1`"]
+    #[inline]
+    pub fn is_hsmclk_ready_1(&self) -> bool {
+        *self == HSMCLK_READYR::HSMCLK_READY_1
+    }
+}
+#[doc = "Possible values of the field `SMCLK_READY`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SMCLK_READYR {
+    #[doc = "Not ready"]
+    SMCLK_READY_0,
+    #[doc = "Ready"]
+    SMCLK_READY_1,
+}
+impl SMCLK_READYR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            SMCLK_READYR::SMCLK_READY_0 => false,
+            SMCLK_READYR::SMCLK_READY_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> SMCLK_READYR {
+        match value {
+            false => SMCLK_READYR::SMCLK_READY_0,
+            true => SMCLK_READYR::SMCLK_READY_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SMCLK_READY_0`"]
+    #[inline]
+    pub fn is_smclk_ready_0(&self) -> bool {
+        *self == SMCLK_READYR::SMCLK_READY_0
+    }
+    #[doc = "Checks if the value of the field is `SMCLK_READY_1`"]
+    #[inline]
+    pub fn is_smclk_ready_1(&self) -> bool {
+        *self == SMCLK_READYR::SMCLK_READY_1
+    }
+}
+#[doc = "Possible values of the field `BCLK_READY`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum BCLK_READYR {
+    #[doc = "Not ready"]
+    BCLK_READY_0,
+    #[doc = "Ready"]
+    BCLK_READY_1,
+}
+impl BCLK_READYR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            BCLK_READYR::BCLK_READY_0 => false,
+            BCLK_READYR::BCLK_READY_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> BCLK_READYR {
+        match value {
+            false => BCLK_READYR::BCLK_READY_0,
+            true => BCLK_READYR::BCLK_READY_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `BCLK_READY_0`"]
+    #[inline]
+    pub fn is_bclk_ready_0(&self) -> bool {
+        *self == BCLK_READYR::BCLK_READY_0
+    }
+    #[doc = "Checks if the value of the field is `BCLK_READY_1`"]
+    #[inline]
+    pub fn is_bclk_ready_1(&self) -> bool {
+        *self == BCLK_READYR::BCLK_READY_1
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - DCO status"]
+    #[inline]
+    pub fn dco_on(&self) -> DCO_ONR {
+        DCO_ONR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - DCO bias status"]
+    #[inline]
+    pub fn dcobias_on(&self) -> DCOBIAS_ONR {
+        DCOBIAS_ONR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - HFXT status"]
+    #[inline]
+    pub fn hfxt_on(&self) -> HFXT_ONR {
+        HFXT_ONR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 3 - HFXT2 status"]
+    #[inline]
+    pub fn hfxt2_on(&self) -> HFXT2_ONR {
+        HFXT2_ONR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 4 - MODOSC status"]
+    #[inline]
+    pub fn modosc_on(&self) -> MODOSC_ONR {
+        MODOSC_ONR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 5 - VLO status"]
+    #[inline]
+    pub fn vlo_on(&self) -> VLO_ONR {
+        VLO_ONR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 6 - LFXT status"]
+    #[inline]
+    pub fn lfxt_on(&self) -> LFXT_ONR {
+        LFXT_ONR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 7 - REFO status"]
+    #[inline]
+    pub fn refo_on(&self) -> REFO_ONR {
+        REFO_ONR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 16 - ACLK system clock status"]
+    #[inline]
+    pub fn aclk_on(&self) -> ACLK_ONR {
+        ACLK_ONR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 17 - MCLK system clock status"]
+    #[inline]
+    pub fn mclk_on(&self) -> MCLK_ONR {
+        MCLK_ONR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 17;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 18 - HSMCLK system clock status"]
+    #[inline]
+    pub fn hsmclk_on(&self) -> HSMCLK_ONR {
+        HSMCLK_ONR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 18;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 19 - SMCLK system clock status"]
+    #[inline]
+    pub fn smclk_on(&self) -> SMCLK_ONR {
+        SMCLK_ONR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 19;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 20 - MODCLK system clock status"]
+    #[inline]
+    pub fn modclk_on(&self) -> MODCLK_ONR {
+        MODCLK_ONR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 20;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 21 - VLOCLK system clock status"]
+    #[inline]
+    pub fn vloclk_on(&self) -> VLOCLK_ONR {
+        VLOCLK_ONR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 21;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 22 - LFXTCLK system clock status"]
+    #[inline]
+    pub fn lfxtclk_on(&self) -> LFXTCLK_ONR {
+        LFXTCLK_ONR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 22;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 23 - REFOCLK system clock status"]
+    #[inline]
+    pub fn refoclk_on(&self) -> REFOCLK_ONR {
+        REFOCLK_ONR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 23;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 24 - ACLK Ready status"]
+    #[inline]
+    pub fn aclk_ready(&self) -> ACLK_READYR {
+        ACLK_READYR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 24;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 25 - MCLK Ready status"]
+    #[inline]
+    pub fn mclk_ready(&self) -> MCLK_READYR {
+        MCLK_READYR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 25;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 26 - HSMCLK Ready status"]
+    #[inline]
+    pub fn hsmclk_ready(&self) -> HSMCLK_READYR {
+        HSMCLK_READYR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 26;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 27 - SMCLK Ready status"]
+    #[inline]
+    pub fn smclk_ready(&self) -> SMCLK_READYR {
+        SMCLK_READYR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 27;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 28 - BCLK Ready status"]
+    #[inline]
+    pub fn bclk_ready(&self) -> BCLK_READYR {
+        BCLK_READYR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 28;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/dio.rs b/example-source/msp432p401r/src/dio.rs
new file mode 100644
index 0000000..37533fd
--- /dev/null
+++ b/example-source/msp432p401r/src/dio.rs
@@ -0,0 +1,595 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - Port A Input"]
+    pub pain: PAIN,
+    #[doc = "0x02 - Port A Output"]
+    pub paout: PAOUT,
+    #[doc = "0x04 - Port A Direction"]
+    pub padir: PADIR,
+    #[doc = "0x06 - Port A Resistor Enable"]
+    pub paren: PAREN,
+    #[doc = "0x08 - Port A Drive Strength"]
+    pub pads: PADS,
+    #[doc = "0x0a - Port A Select 0"]
+    pub pasel0: PASEL0,
+    #[doc = "0x0c - Port A Select 1"]
+    pub pasel1: PASEL1,
+    #[doc = "0x0e - Port 1 Interrupt Vector Register"]
+    pub p1iv: P1IV,
+    _reserved0: [u8; 6usize],
+    #[doc = "0x16 - Port A Complement Select"]
+    pub paselc: PASELC,
+    #[doc = "0x18 - Port A Interrupt Edge Select"]
+    pub paies: PAIES,
+    #[doc = "0x1a - Port A Interrupt Enable"]
+    pub paie: PAIE,
+    #[doc = "0x1c - Port A Interrupt Flag"]
+    pub paifg: PAIFG,
+    #[doc = "0x1e - Port 2 Interrupt Vector Register"]
+    pub p2iv: P2IV,
+    #[doc = "0x20 - Port B Input"]
+    pub pbin: PBIN,
+    #[doc = "0x22 - Port B Output"]
+    pub pbout: PBOUT,
+    #[doc = "0x24 - Port B Direction"]
+    pub pbdir: PBDIR,
+    #[doc = "0x26 - Port B Resistor Enable"]
+    pub pbren: PBREN,
+    #[doc = "0x28 - Port B Drive Strength"]
+    pub pbds: PBDS,
+    #[doc = "0x2a - Port B Select 0"]
+    pub pbsel0: PBSEL0,
+    #[doc = "0x2c - Port B Select 1"]
+    pub pbsel1: PBSEL1,
+    #[doc = "0x2e - Port 3 Interrupt Vector Register"]
+    pub p3iv: P3IV,
+    _reserved1: [u8; 6usize],
+    #[doc = "0x36 - Port B Complement Select"]
+    pub pbselc: PBSELC,
+    #[doc = "0x38 - Port B Interrupt Edge Select"]
+    pub pbies: PBIES,
+    #[doc = "0x3a - Port B Interrupt Enable"]
+    pub pbie: PBIE,
+    #[doc = "0x3c - Port B Interrupt Flag"]
+    pub pbifg: PBIFG,
+    #[doc = "0x3e - Port 4 Interrupt Vector Register"]
+    pub p4iv: P4IV,
+    #[doc = "0x40 - Port C Input"]
+    pub pcin: PCIN,
+    #[doc = "0x42 - Port C Output"]
+    pub pcout: PCOUT,
+    #[doc = "0x44 - Port C Direction"]
+    pub pcdir: PCDIR,
+    #[doc = "0x46 - Port C Resistor Enable"]
+    pub pcren: PCREN,
+    #[doc = "0x48 - Port C Drive Strength"]
+    pub pcds: PCDS,
+    #[doc = "0x4a - Port C Select 0"]
+    pub pcsel0: PCSEL0,
+    #[doc = "0x4c - Port C Select 1"]
+    pub pcsel1: PCSEL1,
+    #[doc = "0x4e - Port 5 Interrupt Vector Register"]
+    pub p5iv: P5IV,
+    _reserved2: [u8; 6usize],
+    #[doc = "0x56 - Port C Complement Select"]
+    pub pcselc: PCSELC,
+    #[doc = "0x58 - Port C Interrupt Edge Select"]
+    pub pcies: PCIES,
+    #[doc = "0x5a - Port C Interrupt Enable"]
+    pub pcie: PCIE,
+    #[doc = "0x5c - Port C Interrupt Flag"]
+    pub pcifg: PCIFG,
+    #[doc = "0x5e - Port 6 Interrupt Vector Register"]
+    pub p6iv: P6IV,
+    #[doc = "0x60 - Port D Input"]
+    pub pdin: PDIN,
+    #[doc = "0x62 - Port D Output"]
+    pub pdout: PDOUT,
+    #[doc = "0x64 - Port D Direction"]
+    pub pddir: PDDIR,
+    #[doc = "0x66 - Port D Resistor Enable"]
+    pub pdren: PDREN,
+    #[doc = "0x68 - Port D Drive Strength"]
+    pub pdds: PDDS,
+    #[doc = "0x6a - Port D Select 0"]
+    pub pdsel0: PDSEL0,
+    #[doc = "0x6c - Port D Select 1"]
+    pub pdsel1: PDSEL1,
+    #[doc = "0x6e - Port 7 Interrupt Vector Register"]
+    pub p7iv: P7IV,
+    _reserved3: [u8; 6usize],
+    #[doc = "0x76 - Port D Complement Select"]
+    pub pdselc: PDSELC,
+    #[doc = "0x78 - Port D Interrupt Edge Select"]
+    pub pdies: PDIES,
+    #[doc = "0x7a - Port D Interrupt Enable"]
+    pub pdie: PDIE,
+    #[doc = "0x7c - Port D Interrupt Flag"]
+    pub pdifg: PDIFG,
+    #[doc = "0x7e - Port 8 Interrupt Vector Register"]
+    pub p8iv: P8IV,
+    #[doc = "0x80 - Port E Input"]
+    pub pein: PEIN,
+    #[doc = "0x82 - Port E Output"]
+    pub peout: PEOUT,
+    #[doc = "0x84 - Port E Direction"]
+    pub pedir: PEDIR,
+    #[doc = "0x86 - Port E Resistor Enable"]
+    pub peren: PEREN,
+    #[doc = "0x88 - Port E Drive Strength"]
+    pub peds: PEDS,
+    #[doc = "0x8a - Port E Select 0"]
+    pub pesel0: PESEL0,
+    #[doc = "0x8c - Port E Select 1"]
+    pub pesel1: PESEL1,
+    #[doc = "0x8e - Port 9 Interrupt Vector Register"]
+    pub p9iv: P9IV,
+    _reserved4: [u8; 6usize],
+    #[doc = "0x96 - Port E Complement Select"]
+    pub peselc: PESELC,
+    #[doc = "0x98 - Port E Interrupt Edge Select"]
+    pub peies: PEIES,
+    #[doc = "0x9a - Port E Interrupt Enable"]
+    pub peie: PEIE,
+    #[doc = "0x9c - Port E Interrupt Flag"]
+    pub peifg: PEIFG,
+    #[doc = "0x9e - Port 10 Interrupt Vector Register"]
+    pub p10iv: P10IV,
+    _reserved5: [u8; 128usize],
+    #[doc = "0x120 - Port J Input"]
+    pub pjin: PJIN,
+    #[doc = "0x122 - Port J Output"]
+    pub pjout: PJOUT,
+    #[doc = "0x124 - Port J Direction"]
+    pub pjdir: PJDIR,
+    #[doc = "0x126 - Port J Resistor Enable"]
+    pub pjren: PJREN,
+    #[doc = "0x128 - Port J Drive Strength"]
+    pub pjds: PJDS,
+    #[doc = "0x12a - Port J Select 0"]
+    pub pjsel0: PJSEL0,
+    #[doc = "0x12c - Port J Select 1"]
+    pub pjsel1: PJSEL1,
+    _reserved6: [u8; 8usize],
+    #[doc = "0x136 - Port J Complement Select"]
+    pub pjselc: PJSELC,
+}
+#[doc = "Port A Input"]
+pub struct PAIN {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port A Input"]
+pub mod pain;
+#[doc = "Port A Output"]
+pub struct PAOUT {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port A Output"]
+pub mod paout;
+#[doc = "Port A Direction"]
+pub struct PADIR {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port A Direction"]
+pub mod padir;
+#[doc = "Port A Resistor Enable"]
+pub struct PAREN {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port A Resistor Enable"]
+pub mod paren;
+#[doc = "Port A Drive Strength"]
+pub struct PADS {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port A Drive Strength"]
+pub mod pads;
+#[doc = "Port A Select 0"]
+pub struct PASEL0 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port A Select 0"]
+pub mod pasel0;
+#[doc = "Port A Select 1"]
+pub struct PASEL1 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port A Select 1"]
+pub mod pasel1;
+#[doc = "Port 1 Interrupt Vector Register"]
+pub struct P1IV {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port 1 Interrupt Vector Register"]
+pub mod p1iv;
+#[doc = "Port A Complement Select"]
+pub struct PASELC {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port A Complement Select"]
+pub mod paselc;
+#[doc = "Port A Interrupt Edge Select"]
+pub struct PAIES {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port A Interrupt Edge Select"]
+pub mod paies;
+#[doc = "Port A Interrupt Enable"]
+pub struct PAIE {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port A Interrupt Enable"]
+pub mod paie;
+#[doc = "Port A Interrupt Flag"]
+pub struct PAIFG {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port A Interrupt Flag"]
+pub mod paifg;
+#[doc = "Port 2 Interrupt Vector Register"]
+pub struct P2IV {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port 2 Interrupt Vector Register"]
+pub mod p2iv;
+#[doc = "Port B Input"]
+pub struct PBIN {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port B Input"]
+pub mod pbin;
+#[doc = "Port B Output"]
+pub struct PBOUT {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port B Output"]
+pub mod pbout;
+#[doc = "Port B Direction"]
+pub struct PBDIR {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port B Direction"]
+pub mod pbdir;
+#[doc = "Port B Resistor Enable"]
+pub struct PBREN {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port B Resistor Enable"]
+pub mod pbren;
+#[doc = "Port B Drive Strength"]
+pub struct PBDS {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port B Drive Strength"]
+pub mod pbds;
+#[doc = "Port B Select 0"]
+pub struct PBSEL0 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port B Select 0"]
+pub mod pbsel0;
+#[doc = "Port B Select 1"]
+pub struct PBSEL1 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port B Select 1"]
+pub mod pbsel1;
+#[doc = "Port 3 Interrupt Vector Register"]
+pub struct P3IV {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port 3 Interrupt Vector Register"]
+pub mod p3iv;
+#[doc = "Port B Complement Select"]
+pub struct PBSELC {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port B Complement Select"]
+pub mod pbselc;
+#[doc = "Port B Interrupt Edge Select"]
+pub struct PBIES {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port B Interrupt Edge Select"]
+pub mod pbies;
+#[doc = "Port B Interrupt Enable"]
+pub struct PBIE {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port B Interrupt Enable"]
+pub mod pbie;
+#[doc = "Port B Interrupt Flag"]
+pub struct PBIFG {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port B Interrupt Flag"]
+pub mod pbifg;
+#[doc = "Port 4 Interrupt Vector Register"]
+pub struct P4IV {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port 4 Interrupt Vector Register"]
+pub mod p4iv;
+#[doc = "Port C Input"]
+pub struct PCIN {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port C Input"]
+pub mod pcin;
+#[doc = "Port C Output"]
+pub struct PCOUT {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port C Output"]
+pub mod pcout;
+#[doc = "Port C Direction"]
+pub struct PCDIR {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port C Direction"]
+pub mod pcdir;
+#[doc = "Port C Resistor Enable"]
+pub struct PCREN {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port C Resistor Enable"]
+pub mod pcren;
+#[doc = "Port C Drive Strength"]
+pub struct PCDS {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port C Drive Strength"]
+pub mod pcds;
+#[doc = "Port C Select 0"]
+pub struct PCSEL0 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port C Select 0"]
+pub mod pcsel0;
+#[doc = "Port C Select 1"]
+pub struct PCSEL1 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port C Select 1"]
+pub mod pcsel1;
+#[doc = "Port 5 Interrupt Vector Register"]
+pub struct P5IV {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port 5 Interrupt Vector Register"]
+pub mod p5iv;
+#[doc = "Port C Complement Select"]
+pub struct PCSELC {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port C Complement Select"]
+pub mod pcselc;
+#[doc = "Port C Interrupt Edge Select"]
+pub struct PCIES {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port C Interrupt Edge Select"]
+pub mod pcies;
+#[doc = "Port C Interrupt Enable"]
+pub struct PCIE {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port C Interrupt Enable"]
+pub mod pcie;
+#[doc = "Port C Interrupt Flag"]
+pub struct PCIFG {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port C Interrupt Flag"]
+pub mod pcifg;
+#[doc = "Port 6 Interrupt Vector Register"]
+pub struct P6IV {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port 6 Interrupt Vector Register"]
+pub mod p6iv;
+#[doc = "Port D Input"]
+pub struct PDIN {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port D Input"]
+pub mod pdin;
+#[doc = "Port D Output"]
+pub struct PDOUT {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port D Output"]
+pub mod pdout;
+#[doc = "Port D Direction"]
+pub struct PDDIR {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port D Direction"]
+pub mod pddir;
+#[doc = "Port D Resistor Enable"]
+pub struct PDREN {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port D Resistor Enable"]
+pub mod pdren;
+#[doc = "Port D Drive Strength"]
+pub struct PDDS {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port D Drive Strength"]
+pub mod pdds;
+#[doc = "Port D Select 0"]
+pub struct PDSEL0 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port D Select 0"]
+pub mod pdsel0;
+#[doc = "Port D Select 1"]
+pub struct PDSEL1 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port D Select 1"]
+pub mod pdsel1;
+#[doc = "Port 7 Interrupt Vector Register"]
+pub struct P7IV {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port 7 Interrupt Vector Register"]
+pub mod p7iv;
+#[doc = "Port D Complement Select"]
+pub struct PDSELC {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port D Complement Select"]
+pub mod pdselc;
+#[doc = "Port D Interrupt Edge Select"]
+pub struct PDIES {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port D Interrupt Edge Select"]
+pub mod pdies;
+#[doc = "Port D Interrupt Enable"]
+pub struct PDIE {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port D Interrupt Enable"]
+pub mod pdie;
+#[doc = "Port D Interrupt Flag"]
+pub struct PDIFG {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port D Interrupt Flag"]
+pub mod pdifg;
+#[doc = "Port 8 Interrupt Vector Register"]
+pub struct P8IV {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port 8 Interrupt Vector Register"]
+pub mod p8iv;
+#[doc = "Port E Input"]
+pub struct PEIN {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port E Input"]
+pub mod pein;
+#[doc = "Port E Output"]
+pub struct PEOUT {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port E Output"]
+pub mod peout;
+#[doc = "Port E Direction"]
+pub struct PEDIR {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port E Direction"]
+pub mod pedir;
+#[doc = "Port E Resistor Enable"]
+pub struct PEREN {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port E Resistor Enable"]
+pub mod peren;
+#[doc = "Port E Drive Strength"]
+pub struct PEDS {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port E Drive Strength"]
+pub mod peds;
+#[doc = "Port E Select 0"]
+pub struct PESEL0 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port E Select 0"]
+pub mod pesel0;
+#[doc = "Port E Select 1"]
+pub struct PESEL1 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port E Select 1"]
+pub mod pesel1;
+#[doc = "Port 9 Interrupt Vector Register"]
+pub struct P9IV {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port 9 Interrupt Vector Register"]
+pub mod p9iv;
+#[doc = "Port E Complement Select"]
+pub struct PESELC {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port E Complement Select"]
+pub mod peselc;
+#[doc = "Port E Interrupt Edge Select"]
+pub struct PEIES {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port E Interrupt Edge Select"]
+pub mod peies;
+#[doc = "Port E Interrupt Enable"]
+pub struct PEIE {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port E Interrupt Enable"]
+pub mod peie;
+#[doc = "Port E Interrupt Flag"]
+pub struct PEIFG {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port E Interrupt Flag"]
+pub mod peifg;
+#[doc = "Port 10 Interrupt Vector Register"]
+pub struct P10IV {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port 10 Interrupt Vector Register"]
+pub mod p10iv;
+#[doc = "Port J Input"]
+pub struct PJIN {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port J Input"]
+pub mod pjin;
+#[doc = "Port J Output"]
+pub struct PJOUT {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port J Output"]
+pub mod pjout;
+#[doc = "Port J Direction"]
+pub struct PJDIR {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port J Direction"]
+pub mod pjdir;
+#[doc = "Port J Resistor Enable"]
+pub struct PJREN {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port J Resistor Enable"]
+pub mod pjren;
+#[doc = "Port J Drive Strength"]
+pub struct PJDS {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port J Drive Strength"]
+pub mod pjds;
+#[doc = "Port J Select 0"]
+pub struct PJSEL0 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port J Select 0"]
+pub mod pjsel0;
+#[doc = "Port J Select 1"]
+pub struct PJSEL1 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port J Select 1"]
+pub mod pjsel1;
+#[doc = "Port J Complement Select"]
+pub struct PJSELC {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port J Complement Select"]
+pub mod pjselc;
diff --git a/example-source/msp432p401r/src/dio/p10iv.rs b/example-source/msp432p401r/src/dio/p10iv.rs
new file mode 100644
index 0000000..ab7ecfd
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/p10iv.rs
@@ -0,0 +1,133 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::P10IV {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `P10IV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum P10IVR {
+    #[doc = "No interrupt pending"]
+    P10IV_0,
+    #[doc = "Interrupt Source: Port 10.0 interrupt; Interrupt Flag: P10IFG0; Interrupt Priority: Highest"]
+    P10IV_2,
+    #[doc = "Interrupt Source: Port 10.1 interrupt; Interrupt Flag: P10IFG1"]
+    P10IV_4,
+    #[doc = "Interrupt Source: Port 10.2 interrupt; Interrupt Flag: P10IFG2"]
+    P10IV_6,
+    #[doc = "Interrupt Source: Port 10.3 interrupt; Interrupt Flag: P10IFG3"]
+    P10IV_8,
+    #[doc = "Interrupt Source: Port 10.4 interrupt; Interrupt Flag: P10IFG4"]
+    P10IV_10,
+    #[doc = "Interrupt Source: Port 10.5 interrupt; Interrupt Flag: P10IFG5"]
+    P10IV_12,
+    #[doc = "Interrupt Source: Port 10.6 interrupt; Interrupt Flag: P10IFG6"]
+    P10IV_14,
+    #[doc = "Interrupt Source: Port 10.7 interrupt; Interrupt Flag: P10IFG7; Interrupt Priority: Lowest"]
+    P10IV_16,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl P10IVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            P10IVR::P10IV_0 => 0,
+            P10IVR::P10IV_2 => 2,
+            P10IVR::P10IV_4 => 4,
+            P10IVR::P10IV_6 => 6,
+            P10IVR::P10IV_8 => 8,
+            P10IVR::P10IV_10 => 10,
+            P10IVR::P10IV_12 => 12,
+            P10IVR::P10IV_14 => 14,
+            P10IVR::P10IV_16 => 16,
+            P10IVR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> P10IVR {
+        match value {
+            0 => P10IVR::P10IV_0,
+            2 => P10IVR::P10IV_2,
+            4 => P10IVR::P10IV_4,
+            6 => P10IVR::P10IV_6,
+            8 => P10IVR::P10IV_8,
+            10 => P10IVR::P10IV_10,
+            12 => P10IVR::P10IV_12,
+            14 => P10IVR::P10IV_14,
+            16 => P10IVR::P10IV_16,
+            i => P10IVR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `P10IV_0`"]
+    #[inline]
+    pub fn is_p10iv_0(&self) -> bool {
+        *self == P10IVR::P10IV_0
+    }
+    #[doc = "Checks if the value of the field is `P10IV_2`"]
+    #[inline]
+    pub fn is_p10iv_2(&self) -> bool {
+        *self == P10IVR::P10IV_2
+    }
+    #[doc = "Checks if the value of the field is `P10IV_4`"]
+    #[inline]
+    pub fn is_p10iv_4(&self) -> bool {
+        *self == P10IVR::P10IV_4
+    }
+    #[doc = "Checks if the value of the field is `P10IV_6`"]
+    #[inline]
+    pub fn is_p10iv_6(&self) -> bool {
+        *self == P10IVR::P10IV_6
+    }
+    #[doc = "Checks if the value of the field is `P10IV_8`"]
+    #[inline]
+    pub fn is_p10iv_8(&self) -> bool {
+        *self == P10IVR::P10IV_8
+    }
+    #[doc = "Checks if the value of the field is `P10IV_10`"]
+    #[inline]
+    pub fn is_p10iv_10(&self) -> bool {
+        *self == P10IVR::P10IV_10
+    }
+    #[doc = "Checks if the value of the field is `P10IV_12`"]
+    #[inline]
+    pub fn is_p10iv_12(&self) -> bool {
+        *self == P10IVR::P10IV_12
+    }
+    #[doc = "Checks if the value of the field is `P10IV_14`"]
+    #[inline]
+    pub fn is_p10iv_14(&self) -> bool {
+        *self == P10IVR::P10IV_14
+    }
+    #[doc = "Checks if the value of the field is `P10IV_16`"]
+    #[inline]
+    pub fn is_p10iv_16(&self) -> bool {
+        *self == P10IVR::P10IV_16
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:4 - Port 10 interrupt vector value"]
+    #[inline]
+    pub fn p10iv(&self) -> P10IVR {
+        P10IVR::_from({
+            const MASK: u8 = 31;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/p1iv.rs b/example-source/msp432p401r/src/dio/p1iv.rs
new file mode 100644
index 0000000..2cf8509
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/p1iv.rs
@@ -0,0 +1,133 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::P1IV {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `P1IV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum P1IVR {
+    #[doc = "No interrupt pending"]
+    P1IV_0,
+    #[doc = "Interrupt Source: Port 1.0 interrupt; Interrupt Flag: P1IFG0; Interrupt Priority: Highest"]
+    P1IV_2,
+    #[doc = "Interrupt Source: Port 1.1 interrupt; Interrupt Flag: P1IFG1"]
+    P1IV_4,
+    #[doc = "Interrupt Source: Port 1.2 interrupt; Interrupt Flag: P1IFG2"]
+    P1IV_6,
+    #[doc = "Interrupt Source: Port 1.3 interrupt; Interrupt Flag: P1IFG3"]
+    P1IV_8,
+    #[doc = "Interrupt Source: Port 1.4 interrupt; Interrupt Flag: P1IFG4"]
+    P1IV_10,
+    #[doc = "Interrupt Source: Port 1.5 interrupt; Interrupt Flag: P1IFG5"]
+    P1IV_12,
+    #[doc = "Interrupt Source: Port 1.6 interrupt; Interrupt Flag: P1IFG6"]
+    P1IV_14,
+    #[doc = "Interrupt Source: Port 1.7 interrupt; Interrupt Flag: P1IFG7; Interrupt Priority: Lowest"]
+    P1IV_16,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl P1IVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            P1IVR::P1IV_0 => 0,
+            P1IVR::P1IV_2 => 2,
+            P1IVR::P1IV_4 => 4,
+            P1IVR::P1IV_6 => 6,
+            P1IVR::P1IV_8 => 8,
+            P1IVR::P1IV_10 => 10,
+            P1IVR::P1IV_12 => 12,
+            P1IVR::P1IV_14 => 14,
+            P1IVR::P1IV_16 => 16,
+            P1IVR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> P1IVR {
+        match value {
+            0 => P1IVR::P1IV_0,
+            2 => P1IVR::P1IV_2,
+            4 => P1IVR::P1IV_4,
+            6 => P1IVR::P1IV_6,
+            8 => P1IVR::P1IV_8,
+            10 => P1IVR::P1IV_10,
+            12 => P1IVR::P1IV_12,
+            14 => P1IVR::P1IV_14,
+            16 => P1IVR::P1IV_16,
+            i => P1IVR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `P1IV_0`"]
+    #[inline]
+    pub fn is_p1iv_0(&self) -> bool {
+        *self == P1IVR::P1IV_0
+    }
+    #[doc = "Checks if the value of the field is `P1IV_2`"]
+    #[inline]
+    pub fn is_p1iv_2(&self) -> bool {
+        *self == P1IVR::P1IV_2
+    }
+    #[doc = "Checks if the value of the field is `P1IV_4`"]
+    #[inline]
+    pub fn is_p1iv_4(&self) -> bool {
+        *self == P1IVR::P1IV_4
+    }
+    #[doc = "Checks if the value of the field is `P1IV_6`"]
+    #[inline]
+    pub fn is_p1iv_6(&self) -> bool {
+        *self == P1IVR::P1IV_6
+    }
+    #[doc = "Checks if the value of the field is `P1IV_8`"]
+    #[inline]
+    pub fn is_p1iv_8(&self) -> bool {
+        *self == P1IVR::P1IV_8
+    }
+    #[doc = "Checks if the value of the field is `P1IV_10`"]
+    #[inline]
+    pub fn is_p1iv_10(&self) -> bool {
+        *self == P1IVR::P1IV_10
+    }
+    #[doc = "Checks if the value of the field is `P1IV_12`"]
+    #[inline]
+    pub fn is_p1iv_12(&self) -> bool {
+        *self == P1IVR::P1IV_12
+    }
+    #[doc = "Checks if the value of the field is `P1IV_14`"]
+    #[inline]
+    pub fn is_p1iv_14(&self) -> bool {
+        *self == P1IVR::P1IV_14
+    }
+    #[doc = "Checks if the value of the field is `P1IV_16`"]
+    #[inline]
+    pub fn is_p1iv_16(&self) -> bool {
+        *self == P1IVR::P1IV_16
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:4 - Port 1 interrupt vector value"]
+    #[inline]
+    pub fn p1iv(&self) -> P1IVR {
+        P1IVR::_from({
+            const MASK: u8 = 31;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/p2iv.rs b/example-source/msp432p401r/src/dio/p2iv.rs
new file mode 100644
index 0000000..bc1e8af
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/p2iv.rs
@@ -0,0 +1,133 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::P2IV {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `P2IV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum P2IVR {
+    #[doc = "No interrupt pending"]
+    P2IV_0,
+    #[doc = "Interrupt Source: Port 2.0 interrupt; Interrupt Flag: P2IFG0; Interrupt Priority: Highest"]
+    P2IV_2,
+    #[doc = "Interrupt Source: Port 2.1 interrupt; Interrupt Flag: P2IFG1"]
+    P2IV_4,
+    #[doc = "Interrupt Source: Port 2.2 interrupt; Interrupt Flag: P2IFG2"]
+    P2IV_6,
+    #[doc = "Interrupt Source: Port 2.3 interrupt; Interrupt Flag: P2IFG3"]
+    P2IV_8,
+    #[doc = "Interrupt Source: Port 2.4 interrupt; Interrupt Flag: P2IFG4"]
+    P2IV_10,
+    #[doc = "Interrupt Source: Port 2.5 interrupt; Interrupt Flag: P2IFG5"]
+    P2IV_12,
+    #[doc = "Interrupt Source: Port 2.6 interrupt; Interrupt Flag: P2IFG6"]
+    P2IV_14,
+    #[doc = "Interrupt Source: Port 2.7 interrupt; Interrupt Flag: P2IFG7; Interrupt Priority: Lowest"]
+    P2IV_16,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl P2IVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            P2IVR::P2IV_0 => 0,
+            P2IVR::P2IV_2 => 2,
+            P2IVR::P2IV_4 => 4,
+            P2IVR::P2IV_6 => 6,
+            P2IVR::P2IV_8 => 8,
+            P2IVR::P2IV_10 => 10,
+            P2IVR::P2IV_12 => 12,
+            P2IVR::P2IV_14 => 14,
+            P2IVR::P2IV_16 => 16,
+            P2IVR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> P2IVR {
+        match value {
+            0 => P2IVR::P2IV_0,
+            2 => P2IVR::P2IV_2,
+            4 => P2IVR::P2IV_4,
+            6 => P2IVR::P2IV_6,
+            8 => P2IVR::P2IV_8,
+            10 => P2IVR::P2IV_10,
+            12 => P2IVR::P2IV_12,
+            14 => P2IVR::P2IV_14,
+            16 => P2IVR::P2IV_16,
+            i => P2IVR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `P2IV_0`"]
+    #[inline]
+    pub fn is_p2iv_0(&self) -> bool {
+        *self == P2IVR::P2IV_0
+    }
+    #[doc = "Checks if the value of the field is `P2IV_2`"]
+    #[inline]
+    pub fn is_p2iv_2(&self) -> bool {
+        *self == P2IVR::P2IV_2
+    }
+    #[doc = "Checks if the value of the field is `P2IV_4`"]
+    #[inline]
+    pub fn is_p2iv_4(&self) -> bool {
+        *self == P2IVR::P2IV_4
+    }
+    #[doc = "Checks if the value of the field is `P2IV_6`"]
+    #[inline]
+    pub fn is_p2iv_6(&self) -> bool {
+        *self == P2IVR::P2IV_6
+    }
+    #[doc = "Checks if the value of the field is `P2IV_8`"]
+    #[inline]
+    pub fn is_p2iv_8(&self) -> bool {
+        *self == P2IVR::P2IV_8
+    }
+    #[doc = "Checks if the value of the field is `P2IV_10`"]
+    #[inline]
+    pub fn is_p2iv_10(&self) -> bool {
+        *self == P2IVR::P2IV_10
+    }
+    #[doc = "Checks if the value of the field is `P2IV_12`"]
+    #[inline]
+    pub fn is_p2iv_12(&self) -> bool {
+        *self == P2IVR::P2IV_12
+    }
+    #[doc = "Checks if the value of the field is `P2IV_14`"]
+    #[inline]
+    pub fn is_p2iv_14(&self) -> bool {
+        *self == P2IVR::P2IV_14
+    }
+    #[doc = "Checks if the value of the field is `P2IV_16`"]
+    #[inline]
+    pub fn is_p2iv_16(&self) -> bool {
+        *self == P2IVR::P2IV_16
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:4 - Port 2 interrupt vector value"]
+    #[inline]
+    pub fn p2iv(&self) -> P2IVR {
+        P2IVR::_from({
+            const MASK: u8 = 31;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/p3iv.rs b/example-source/msp432p401r/src/dio/p3iv.rs
new file mode 100644
index 0000000..34aef2a
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/p3iv.rs
@@ -0,0 +1,133 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::P3IV {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `P3IV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum P3IVR {
+    #[doc = "No interrupt pending"]
+    P3IV_0,
+    #[doc = "Interrupt Source: Port 3.0 interrupt; Interrupt Flag: P3IFG0; Interrupt Priority: Highest"]
+    P3IV_2,
+    #[doc = "Interrupt Source: Port 3.1 interrupt; Interrupt Flag: P3IFG1"]
+    P3IV_4,
+    #[doc = "Interrupt Source: Port 3.2 interrupt; Interrupt Flag: P3IFG2"]
+    P3IV_6,
+    #[doc = "Interrupt Source: Port 3.3 interrupt; Interrupt Flag: P3IFG3"]
+    P3IV_8,
+    #[doc = "Interrupt Source: Port 3.4 interrupt; Interrupt Flag: P3IFG4"]
+    P3IV_10,
+    #[doc = "Interrupt Source: Port 3.5 interrupt; Interrupt Flag: P3IFG5"]
+    P3IV_12,
+    #[doc = "Interrupt Source: Port 3.6 interrupt; Interrupt Flag: P3IFG6"]
+    P3IV_14,
+    #[doc = "Interrupt Source: Port 3.7 interrupt; Interrupt Flag: P3IFG7; Interrupt Priority: Lowest"]
+    P3IV_16,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl P3IVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            P3IVR::P3IV_0 => 0,
+            P3IVR::P3IV_2 => 2,
+            P3IVR::P3IV_4 => 4,
+            P3IVR::P3IV_6 => 6,
+            P3IVR::P3IV_8 => 8,
+            P3IVR::P3IV_10 => 10,
+            P3IVR::P3IV_12 => 12,
+            P3IVR::P3IV_14 => 14,
+            P3IVR::P3IV_16 => 16,
+            P3IVR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> P3IVR {
+        match value {
+            0 => P3IVR::P3IV_0,
+            2 => P3IVR::P3IV_2,
+            4 => P3IVR::P3IV_4,
+            6 => P3IVR::P3IV_6,
+            8 => P3IVR::P3IV_8,
+            10 => P3IVR::P3IV_10,
+            12 => P3IVR::P3IV_12,
+            14 => P3IVR::P3IV_14,
+            16 => P3IVR::P3IV_16,
+            i => P3IVR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `P3IV_0`"]
+    #[inline]
+    pub fn is_p3iv_0(&self) -> bool {
+        *self == P3IVR::P3IV_0
+    }
+    #[doc = "Checks if the value of the field is `P3IV_2`"]
+    #[inline]
+    pub fn is_p3iv_2(&self) -> bool {
+        *self == P3IVR::P3IV_2
+    }
+    #[doc = "Checks if the value of the field is `P3IV_4`"]
+    #[inline]
+    pub fn is_p3iv_4(&self) -> bool {
+        *self == P3IVR::P3IV_4
+    }
+    #[doc = "Checks if the value of the field is `P3IV_6`"]
+    #[inline]
+    pub fn is_p3iv_6(&self) -> bool {
+        *self == P3IVR::P3IV_6
+    }
+    #[doc = "Checks if the value of the field is `P3IV_8`"]
+    #[inline]
+    pub fn is_p3iv_8(&self) -> bool {
+        *self == P3IVR::P3IV_8
+    }
+    #[doc = "Checks if the value of the field is `P3IV_10`"]
+    #[inline]
+    pub fn is_p3iv_10(&self) -> bool {
+        *self == P3IVR::P3IV_10
+    }
+    #[doc = "Checks if the value of the field is `P3IV_12`"]
+    #[inline]
+    pub fn is_p3iv_12(&self) -> bool {
+        *self == P3IVR::P3IV_12
+    }
+    #[doc = "Checks if the value of the field is `P3IV_14`"]
+    #[inline]
+    pub fn is_p3iv_14(&self) -> bool {
+        *self == P3IVR::P3IV_14
+    }
+    #[doc = "Checks if the value of the field is `P3IV_16`"]
+    #[inline]
+    pub fn is_p3iv_16(&self) -> bool {
+        *self == P3IVR::P3IV_16
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:4 - Port 3 interrupt vector value"]
+    #[inline]
+    pub fn p3iv(&self) -> P3IVR {
+        P3IVR::_from({
+            const MASK: u8 = 31;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/p4iv.rs b/example-source/msp432p401r/src/dio/p4iv.rs
new file mode 100644
index 0000000..9adc518
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/p4iv.rs
@@ -0,0 +1,133 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::P4IV {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `P4IV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum P4IVR {
+    #[doc = "No interrupt pending"]
+    P4IV_0,
+    #[doc = "Interrupt Source: Port 4.0 interrupt; Interrupt Flag: P4IFG0; Interrupt Priority: Highest"]
+    P4IV_2,
+    #[doc = "Interrupt Source: Port 4.1 interrupt; Interrupt Flag: P4IFG1"]
+    P4IV_4,
+    #[doc = "Interrupt Source: Port 4.2 interrupt; Interrupt Flag: P4IFG2"]
+    P4IV_6,
+    #[doc = "Interrupt Source: Port 4.3 interrupt; Interrupt Flag: P4IFG3"]
+    P4IV_8,
+    #[doc = "Interrupt Source: Port 4.4 interrupt; Interrupt Flag: P4IFG4"]
+    P4IV_10,
+    #[doc = "Interrupt Source: Port 4.5 interrupt; Interrupt Flag: P4IFG5"]
+    P4IV_12,
+    #[doc = "Interrupt Source: Port 4.6 interrupt; Interrupt Flag: P4IFG6"]
+    P4IV_14,
+    #[doc = "Interrupt Source: Port 4.7 interrupt; Interrupt Flag: P4IFG7; Interrupt Priority: Lowest"]
+    P4IV_16,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl P4IVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            P4IVR::P4IV_0 => 0,
+            P4IVR::P4IV_2 => 2,
+            P4IVR::P4IV_4 => 4,
+            P4IVR::P4IV_6 => 6,
+            P4IVR::P4IV_8 => 8,
+            P4IVR::P4IV_10 => 10,
+            P4IVR::P4IV_12 => 12,
+            P4IVR::P4IV_14 => 14,
+            P4IVR::P4IV_16 => 16,
+            P4IVR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> P4IVR {
+        match value {
+            0 => P4IVR::P4IV_0,
+            2 => P4IVR::P4IV_2,
+            4 => P4IVR::P4IV_4,
+            6 => P4IVR::P4IV_6,
+            8 => P4IVR::P4IV_8,
+            10 => P4IVR::P4IV_10,
+            12 => P4IVR::P4IV_12,
+            14 => P4IVR::P4IV_14,
+            16 => P4IVR::P4IV_16,
+            i => P4IVR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `P4IV_0`"]
+    #[inline]
+    pub fn is_p4iv_0(&self) -> bool {
+        *self == P4IVR::P4IV_0
+    }
+    #[doc = "Checks if the value of the field is `P4IV_2`"]
+    #[inline]
+    pub fn is_p4iv_2(&self) -> bool {
+        *self == P4IVR::P4IV_2
+    }
+    #[doc = "Checks if the value of the field is `P4IV_4`"]
+    #[inline]
+    pub fn is_p4iv_4(&self) -> bool {
+        *self == P4IVR::P4IV_4
+    }
+    #[doc = "Checks if the value of the field is `P4IV_6`"]
+    #[inline]
+    pub fn is_p4iv_6(&self) -> bool {
+        *self == P4IVR::P4IV_6
+    }
+    #[doc = "Checks if the value of the field is `P4IV_8`"]
+    #[inline]
+    pub fn is_p4iv_8(&self) -> bool {
+        *self == P4IVR::P4IV_8
+    }
+    #[doc = "Checks if the value of the field is `P4IV_10`"]
+    #[inline]
+    pub fn is_p4iv_10(&self) -> bool {
+        *self == P4IVR::P4IV_10
+    }
+    #[doc = "Checks if the value of the field is `P4IV_12`"]
+    #[inline]
+    pub fn is_p4iv_12(&self) -> bool {
+        *self == P4IVR::P4IV_12
+    }
+    #[doc = "Checks if the value of the field is `P4IV_14`"]
+    #[inline]
+    pub fn is_p4iv_14(&self) -> bool {
+        *self == P4IVR::P4IV_14
+    }
+    #[doc = "Checks if the value of the field is `P4IV_16`"]
+    #[inline]
+    pub fn is_p4iv_16(&self) -> bool {
+        *self == P4IVR::P4IV_16
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:4 - Port 4 interrupt vector value"]
+    #[inline]
+    pub fn p4iv(&self) -> P4IVR {
+        P4IVR::_from({
+            const MASK: u8 = 31;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/p5iv.rs b/example-source/msp432p401r/src/dio/p5iv.rs
new file mode 100644
index 0000000..272bc4f
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/p5iv.rs
@@ -0,0 +1,133 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::P5IV {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `P5IV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum P5IVR {
+    #[doc = "No interrupt pending"]
+    P5IV_0,
+    #[doc = "Interrupt Source: Port 5.0 interrupt; Interrupt Flag: P5IFG0; Interrupt Priority: Highest"]
+    P5IV_2,
+    #[doc = "Interrupt Source: Port 5.1 interrupt; Interrupt Flag: P5IFG1"]
+    P5IV_4,
+    #[doc = "Interrupt Source: Port 5.2 interrupt; Interrupt Flag: P5IFG2"]
+    P5IV_6,
+    #[doc = "Interrupt Source: Port 5.3 interrupt; Interrupt Flag: P5IFG3"]
+    P5IV_8,
+    #[doc = "Interrupt Source: Port 5.4 interrupt; Interrupt Flag: P5IFG4"]
+    P5IV_10,
+    #[doc = "Interrupt Source: Port 5.5 interrupt; Interrupt Flag: P5IFG5"]
+    P5IV_12,
+    #[doc = "Interrupt Source: Port 5.6 interrupt; Interrupt Flag: P5IFG6"]
+    P5IV_14,
+    #[doc = "Interrupt Source: Port 5.7 interrupt; Interrupt Flag: P5IFG7; Interrupt Priority: Lowest"]
+    P5IV_16,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl P5IVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            P5IVR::P5IV_0 => 0,
+            P5IVR::P5IV_2 => 2,
+            P5IVR::P5IV_4 => 4,
+            P5IVR::P5IV_6 => 6,
+            P5IVR::P5IV_8 => 8,
+            P5IVR::P5IV_10 => 10,
+            P5IVR::P5IV_12 => 12,
+            P5IVR::P5IV_14 => 14,
+            P5IVR::P5IV_16 => 16,
+            P5IVR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> P5IVR {
+        match value {
+            0 => P5IVR::P5IV_0,
+            2 => P5IVR::P5IV_2,
+            4 => P5IVR::P5IV_4,
+            6 => P5IVR::P5IV_6,
+            8 => P5IVR::P5IV_8,
+            10 => P5IVR::P5IV_10,
+            12 => P5IVR::P5IV_12,
+            14 => P5IVR::P5IV_14,
+            16 => P5IVR::P5IV_16,
+            i => P5IVR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `P5IV_0`"]
+    #[inline]
+    pub fn is_p5iv_0(&self) -> bool {
+        *self == P5IVR::P5IV_0
+    }
+    #[doc = "Checks if the value of the field is `P5IV_2`"]
+    #[inline]
+    pub fn is_p5iv_2(&self) -> bool {
+        *self == P5IVR::P5IV_2
+    }
+    #[doc = "Checks if the value of the field is `P5IV_4`"]
+    #[inline]
+    pub fn is_p5iv_4(&self) -> bool {
+        *self == P5IVR::P5IV_4
+    }
+    #[doc = "Checks if the value of the field is `P5IV_6`"]
+    #[inline]
+    pub fn is_p5iv_6(&self) -> bool {
+        *self == P5IVR::P5IV_6
+    }
+    #[doc = "Checks if the value of the field is `P5IV_8`"]
+    #[inline]
+    pub fn is_p5iv_8(&self) -> bool {
+        *self == P5IVR::P5IV_8
+    }
+    #[doc = "Checks if the value of the field is `P5IV_10`"]
+    #[inline]
+    pub fn is_p5iv_10(&self) -> bool {
+        *self == P5IVR::P5IV_10
+    }
+    #[doc = "Checks if the value of the field is `P5IV_12`"]
+    #[inline]
+    pub fn is_p5iv_12(&self) -> bool {
+        *self == P5IVR::P5IV_12
+    }
+    #[doc = "Checks if the value of the field is `P5IV_14`"]
+    #[inline]
+    pub fn is_p5iv_14(&self) -> bool {
+        *self == P5IVR::P5IV_14
+    }
+    #[doc = "Checks if the value of the field is `P5IV_16`"]
+    #[inline]
+    pub fn is_p5iv_16(&self) -> bool {
+        *self == P5IVR::P5IV_16
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:4 - Port 5 interrupt vector value"]
+    #[inline]
+    pub fn p5iv(&self) -> P5IVR {
+        P5IVR::_from({
+            const MASK: u8 = 31;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/p6iv.rs b/example-source/msp432p401r/src/dio/p6iv.rs
new file mode 100644
index 0000000..eacd60e
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/p6iv.rs
@@ -0,0 +1,133 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::P6IV {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `P6IV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum P6IVR {
+    #[doc = "No interrupt pending"]
+    P6IV_0,
+    #[doc = "Interrupt Source: Port 6.0 interrupt; Interrupt Flag: P6IFG0; Interrupt Priority: Highest"]
+    P6IV_2,
+    #[doc = "Interrupt Source: Port 6.1 interrupt; Interrupt Flag: P6IFG1"]
+    P6IV_4,
+    #[doc = "Interrupt Source: Port 6.2 interrupt; Interrupt Flag: P6IFG2"]
+    P6IV_6,
+    #[doc = "Interrupt Source: Port 6.3 interrupt; Interrupt Flag: P6IFG3"]
+    P6IV_8,
+    #[doc = "Interrupt Source: Port 6.4 interrupt; Interrupt Flag: P6IFG4"]
+    P6IV_10,
+    #[doc = "Interrupt Source: Port 6.5 interrupt; Interrupt Flag: P6IFG5"]
+    P6IV_12,
+    #[doc = "Interrupt Source: Port 6.6 interrupt; Interrupt Flag: P6IFG6"]
+    P6IV_14,
+    #[doc = "Interrupt Source: Port 6.7 interrupt; Interrupt Flag: P6IFG7; Interrupt Priority: Lowest"]
+    P6IV_16,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl P6IVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            P6IVR::P6IV_0 => 0,
+            P6IVR::P6IV_2 => 2,
+            P6IVR::P6IV_4 => 4,
+            P6IVR::P6IV_6 => 6,
+            P6IVR::P6IV_8 => 8,
+            P6IVR::P6IV_10 => 10,
+            P6IVR::P6IV_12 => 12,
+            P6IVR::P6IV_14 => 14,
+            P6IVR::P6IV_16 => 16,
+            P6IVR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> P6IVR {
+        match value {
+            0 => P6IVR::P6IV_0,
+            2 => P6IVR::P6IV_2,
+            4 => P6IVR::P6IV_4,
+            6 => P6IVR::P6IV_6,
+            8 => P6IVR::P6IV_8,
+            10 => P6IVR::P6IV_10,
+            12 => P6IVR::P6IV_12,
+            14 => P6IVR::P6IV_14,
+            16 => P6IVR::P6IV_16,
+            i => P6IVR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `P6IV_0`"]
+    #[inline]
+    pub fn is_p6iv_0(&self) -> bool {
+        *self == P6IVR::P6IV_0
+    }
+    #[doc = "Checks if the value of the field is `P6IV_2`"]
+    #[inline]
+    pub fn is_p6iv_2(&self) -> bool {
+        *self == P6IVR::P6IV_2
+    }
+    #[doc = "Checks if the value of the field is `P6IV_4`"]
+    #[inline]
+    pub fn is_p6iv_4(&self) -> bool {
+        *self == P6IVR::P6IV_4
+    }
+    #[doc = "Checks if the value of the field is `P6IV_6`"]
+    #[inline]
+    pub fn is_p6iv_6(&self) -> bool {
+        *self == P6IVR::P6IV_6
+    }
+    #[doc = "Checks if the value of the field is `P6IV_8`"]
+    #[inline]
+    pub fn is_p6iv_8(&self) -> bool {
+        *self == P6IVR::P6IV_8
+    }
+    #[doc = "Checks if the value of the field is `P6IV_10`"]
+    #[inline]
+    pub fn is_p6iv_10(&self) -> bool {
+        *self == P6IVR::P6IV_10
+    }
+    #[doc = "Checks if the value of the field is `P6IV_12`"]
+    #[inline]
+    pub fn is_p6iv_12(&self) -> bool {
+        *self == P6IVR::P6IV_12
+    }
+    #[doc = "Checks if the value of the field is `P6IV_14`"]
+    #[inline]
+    pub fn is_p6iv_14(&self) -> bool {
+        *self == P6IVR::P6IV_14
+    }
+    #[doc = "Checks if the value of the field is `P6IV_16`"]
+    #[inline]
+    pub fn is_p6iv_16(&self) -> bool {
+        *self == P6IVR::P6IV_16
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:4 - Port 6 interrupt vector value"]
+    #[inline]
+    pub fn p6iv(&self) -> P6IVR {
+        P6IVR::_from({
+            const MASK: u8 = 31;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/p7iv.rs b/example-source/msp432p401r/src/dio/p7iv.rs
new file mode 100644
index 0000000..09043fe
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/p7iv.rs
@@ -0,0 +1,133 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::P7IV {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `P7IV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum P7IVR {
+    #[doc = "No interrupt pending"]
+    P7IV_0,
+    #[doc = "Interrupt Source: Port 7.0 interrupt; Interrupt Flag: P7IFG0; Interrupt Priority: Highest"]
+    P7IV_2,
+    #[doc = "Interrupt Source: Port 7.1 interrupt; Interrupt Flag: P7IFG1"]
+    P7IV_4,
+    #[doc = "Interrupt Source: Port 7.2 interrupt; Interrupt Flag: P7IFG2"]
+    P7IV_6,
+    #[doc = "Interrupt Source: Port 7.3 interrupt; Interrupt Flag: P7IFG3"]
+    P7IV_8,
+    #[doc = "Interrupt Source: Port 7.4 interrupt; Interrupt Flag: P7IFG4"]
+    P7IV_10,
+    #[doc = "Interrupt Source: Port 7.5 interrupt; Interrupt Flag: P7IFG5"]
+    P7IV_12,
+    #[doc = "Interrupt Source: Port 7.6 interrupt; Interrupt Flag: P7IFG6"]
+    P7IV_14,
+    #[doc = "Interrupt Source: Port 7.7 interrupt; Interrupt Flag: P7IFG7; Interrupt Priority: Lowest"]
+    P7IV_16,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl P7IVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            P7IVR::P7IV_0 => 0,
+            P7IVR::P7IV_2 => 2,
+            P7IVR::P7IV_4 => 4,
+            P7IVR::P7IV_6 => 6,
+            P7IVR::P7IV_8 => 8,
+            P7IVR::P7IV_10 => 10,
+            P7IVR::P7IV_12 => 12,
+            P7IVR::P7IV_14 => 14,
+            P7IVR::P7IV_16 => 16,
+            P7IVR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> P7IVR {
+        match value {
+            0 => P7IVR::P7IV_0,
+            2 => P7IVR::P7IV_2,
+            4 => P7IVR::P7IV_4,
+            6 => P7IVR::P7IV_6,
+            8 => P7IVR::P7IV_8,
+            10 => P7IVR::P7IV_10,
+            12 => P7IVR::P7IV_12,
+            14 => P7IVR::P7IV_14,
+            16 => P7IVR::P7IV_16,
+            i => P7IVR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `P7IV_0`"]
+    #[inline]
+    pub fn is_p7iv_0(&self) -> bool {
+        *self == P7IVR::P7IV_0
+    }
+    #[doc = "Checks if the value of the field is `P7IV_2`"]
+    #[inline]
+    pub fn is_p7iv_2(&self) -> bool {
+        *self == P7IVR::P7IV_2
+    }
+    #[doc = "Checks if the value of the field is `P7IV_4`"]
+    #[inline]
+    pub fn is_p7iv_4(&self) -> bool {
+        *self == P7IVR::P7IV_4
+    }
+    #[doc = "Checks if the value of the field is `P7IV_6`"]
+    #[inline]
+    pub fn is_p7iv_6(&self) -> bool {
+        *self == P7IVR::P7IV_6
+    }
+    #[doc = "Checks if the value of the field is `P7IV_8`"]
+    #[inline]
+    pub fn is_p7iv_8(&self) -> bool {
+        *self == P7IVR::P7IV_8
+    }
+    #[doc = "Checks if the value of the field is `P7IV_10`"]
+    #[inline]
+    pub fn is_p7iv_10(&self) -> bool {
+        *self == P7IVR::P7IV_10
+    }
+    #[doc = "Checks if the value of the field is `P7IV_12`"]
+    #[inline]
+    pub fn is_p7iv_12(&self) -> bool {
+        *self == P7IVR::P7IV_12
+    }
+    #[doc = "Checks if the value of the field is `P7IV_14`"]
+    #[inline]
+    pub fn is_p7iv_14(&self) -> bool {
+        *self == P7IVR::P7IV_14
+    }
+    #[doc = "Checks if the value of the field is `P7IV_16`"]
+    #[inline]
+    pub fn is_p7iv_16(&self) -> bool {
+        *self == P7IVR::P7IV_16
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:4 - Port 7 interrupt vector value"]
+    #[inline]
+    pub fn p7iv(&self) -> P7IVR {
+        P7IVR::_from({
+            const MASK: u8 = 31;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/p8iv.rs b/example-source/msp432p401r/src/dio/p8iv.rs
new file mode 100644
index 0000000..cfdd475
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/p8iv.rs
@@ -0,0 +1,133 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::P8IV {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `P8IV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum P8IVR {
+    #[doc = "No interrupt pending"]
+    P8IV_0,
+    #[doc = "Interrupt Source: Port 8.0 interrupt; Interrupt Flag: P8IFG0; Interrupt Priority: Highest"]
+    P8IV_2,
+    #[doc = "Interrupt Source: Port 8.1 interrupt; Interrupt Flag: P8IFG1"]
+    P8IV_4,
+    #[doc = "Interrupt Source: Port 8.2 interrupt; Interrupt Flag: P8IFG2"]
+    P8IV_6,
+    #[doc = "Interrupt Source: Port 8.3 interrupt; Interrupt Flag: P8IFG3"]
+    P8IV_8,
+    #[doc = "Interrupt Source: Port 8.4 interrupt; Interrupt Flag: P8IFG4"]
+    P8IV_10,
+    #[doc = "Interrupt Source: Port 8.5 interrupt; Interrupt Flag: P8IFG5"]
+    P8IV_12,
+    #[doc = "Interrupt Source: Port 8.6 interrupt; Interrupt Flag: P8IFG6"]
+    P8IV_14,
+    #[doc = "Interrupt Source: Port 8.7 interrupt; Interrupt Flag: P8IFG7; Interrupt Priority: Lowest"]
+    P8IV_16,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl P8IVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            P8IVR::P8IV_0 => 0,
+            P8IVR::P8IV_2 => 2,
+            P8IVR::P8IV_4 => 4,
+            P8IVR::P8IV_6 => 6,
+            P8IVR::P8IV_8 => 8,
+            P8IVR::P8IV_10 => 10,
+            P8IVR::P8IV_12 => 12,
+            P8IVR::P8IV_14 => 14,
+            P8IVR::P8IV_16 => 16,
+            P8IVR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> P8IVR {
+        match value {
+            0 => P8IVR::P8IV_0,
+            2 => P8IVR::P8IV_2,
+            4 => P8IVR::P8IV_4,
+            6 => P8IVR::P8IV_6,
+            8 => P8IVR::P8IV_8,
+            10 => P8IVR::P8IV_10,
+            12 => P8IVR::P8IV_12,
+            14 => P8IVR::P8IV_14,
+            16 => P8IVR::P8IV_16,
+            i => P8IVR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `P8IV_0`"]
+    #[inline]
+    pub fn is_p8iv_0(&self) -> bool {
+        *self == P8IVR::P8IV_0
+    }
+    #[doc = "Checks if the value of the field is `P8IV_2`"]
+    #[inline]
+    pub fn is_p8iv_2(&self) -> bool {
+        *self == P8IVR::P8IV_2
+    }
+    #[doc = "Checks if the value of the field is `P8IV_4`"]
+    #[inline]
+    pub fn is_p8iv_4(&self) -> bool {
+        *self == P8IVR::P8IV_4
+    }
+    #[doc = "Checks if the value of the field is `P8IV_6`"]
+    #[inline]
+    pub fn is_p8iv_6(&self) -> bool {
+        *self == P8IVR::P8IV_6
+    }
+    #[doc = "Checks if the value of the field is `P8IV_8`"]
+    #[inline]
+    pub fn is_p8iv_8(&self) -> bool {
+        *self == P8IVR::P8IV_8
+    }
+    #[doc = "Checks if the value of the field is `P8IV_10`"]
+    #[inline]
+    pub fn is_p8iv_10(&self) -> bool {
+        *self == P8IVR::P8IV_10
+    }
+    #[doc = "Checks if the value of the field is `P8IV_12`"]
+    #[inline]
+    pub fn is_p8iv_12(&self) -> bool {
+        *self == P8IVR::P8IV_12
+    }
+    #[doc = "Checks if the value of the field is `P8IV_14`"]
+    #[inline]
+    pub fn is_p8iv_14(&self) -> bool {
+        *self == P8IVR::P8IV_14
+    }
+    #[doc = "Checks if the value of the field is `P8IV_16`"]
+    #[inline]
+    pub fn is_p8iv_16(&self) -> bool {
+        *self == P8IVR::P8IV_16
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:4 - Port 8 interrupt vector value"]
+    #[inline]
+    pub fn p8iv(&self) -> P8IVR {
+        P8IVR::_from({
+            const MASK: u8 = 31;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/p9iv.rs b/example-source/msp432p401r/src/dio/p9iv.rs
new file mode 100644
index 0000000..d3a0173
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/p9iv.rs
@@ -0,0 +1,133 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::P9IV {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `P9IV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum P9IVR {
+    #[doc = "No interrupt pending"]
+    P9IV_0,
+    #[doc = "Interrupt Source: Port 9.0 interrupt; Interrupt Flag: P9IFG0; Interrupt Priority: Highest"]
+    P9IV_2,
+    #[doc = "Interrupt Source: Port 9.1 interrupt; Interrupt Flag: P9IFG1"]
+    P9IV_4,
+    #[doc = "Interrupt Source: Port 9.2 interrupt; Interrupt Flag: P9IFG2"]
+    P9IV_6,
+    #[doc = "Interrupt Source: Port 9.3 interrupt; Interrupt Flag: P9IFG3"]
+    P9IV_8,
+    #[doc = "Interrupt Source: Port 9.4 interrupt; Interrupt Flag: P9IFG4"]
+    P9IV_10,
+    #[doc = "Interrupt Source: Port 9.5 interrupt; Interrupt Flag: P9IFG5"]
+    P9IV_12,
+    #[doc = "Interrupt Source: Port 9.6 interrupt; Interrupt Flag: P9IFG6"]
+    P9IV_14,
+    #[doc = "Interrupt Source: Port 9.7 interrupt; Interrupt Flag: P9IFG7; Interrupt Priority: Lowest"]
+    P9IV_16,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl P9IVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            P9IVR::P9IV_0 => 0,
+            P9IVR::P9IV_2 => 2,
+            P9IVR::P9IV_4 => 4,
+            P9IVR::P9IV_6 => 6,
+            P9IVR::P9IV_8 => 8,
+            P9IVR::P9IV_10 => 10,
+            P9IVR::P9IV_12 => 12,
+            P9IVR::P9IV_14 => 14,
+            P9IVR::P9IV_16 => 16,
+            P9IVR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> P9IVR {
+        match value {
+            0 => P9IVR::P9IV_0,
+            2 => P9IVR::P9IV_2,
+            4 => P9IVR::P9IV_4,
+            6 => P9IVR::P9IV_6,
+            8 => P9IVR::P9IV_8,
+            10 => P9IVR::P9IV_10,
+            12 => P9IVR::P9IV_12,
+            14 => P9IVR::P9IV_14,
+            16 => P9IVR::P9IV_16,
+            i => P9IVR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `P9IV_0`"]
+    #[inline]
+    pub fn is_p9iv_0(&self) -> bool {
+        *self == P9IVR::P9IV_0
+    }
+    #[doc = "Checks if the value of the field is `P9IV_2`"]
+    #[inline]
+    pub fn is_p9iv_2(&self) -> bool {
+        *self == P9IVR::P9IV_2
+    }
+    #[doc = "Checks if the value of the field is `P9IV_4`"]
+    #[inline]
+    pub fn is_p9iv_4(&self) -> bool {
+        *self == P9IVR::P9IV_4
+    }
+    #[doc = "Checks if the value of the field is `P9IV_6`"]
+    #[inline]
+    pub fn is_p9iv_6(&self) -> bool {
+        *self == P9IVR::P9IV_6
+    }
+    #[doc = "Checks if the value of the field is `P9IV_8`"]
+    #[inline]
+    pub fn is_p9iv_8(&self) -> bool {
+        *self == P9IVR::P9IV_8
+    }
+    #[doc = "Checks if the value of the field is `P9IV_10`"]
+    #[inline]
+    pub fn is_p9iv_10(&self) -> bool {
+        *self == P9IVR::P9IV_10
+    }
+    #[doc = "Checks if the value of the field is `P9IV_12`"]
+    #[inline]
+    pub fn is_p9iv_12(&self) -> bool {
+        *self == P9IVR::P9IV_12
+    }
+    #[doc = "Checks if the value of the field is `P9IV_14`"]
+    #[inline]
+    pub fn is_p9iv_14(&self) -> bool {
+        *self == P9IVR::P9IV_14
+    }
+    #[doc = "Checks if the value of the field is `P9IV_16`"]
+    #[inline]
+    pub fn is_p9iv_16(&self) -> bool {
+        *self == P9IVR::P9IV_16
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:4 - Port 9 interrupt vector value"]
+    #[inline]
+    pub fn p9iv(&self) -> P9IVR {
+        P9IVR::_from({
+            const MASK: u8 = 31;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/padir.rs b/example-source/msp432p401r/src/dio/padir.rs
new file mode 100644
index 0000000..ee97d0c
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/padir.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PADIR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P1DIRR {
+    bits: u8,
+}
+impl P1DIRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P2DIRR {
+    bits: u8,
+}
+impl P2DIRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P1DIRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P1DIRW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P2DIRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P2DIRW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 1 Direction"]
+    #[inline]
+    pub fn p1dir(&self) -> P1DIRR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P1DIRR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 2 Direction"]
+    #[inline]
+    pub fn p2dir(&self) -> P2DIRR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P2DIRR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 1 Direction"]
+    #[inline]
+    pub fn p1dir(&mut self) -> _P1DIRW {
+        _P1DIRW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 2 Direction"]
+    #[inline]
+    pub fn p2dir(&mut self) -> _P2DIRW {
+        _P2DIRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pads.rs b/example-source/msp432p401r/src/dio/pads.rs
new file mode 100644
index 0000000..4fe4c78
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pads.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PADS {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P1DSR {
+    bits: u8,
+}
+impl P1DSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P2DSR {
+    bits: u8,
+}
+impl P2DSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P1DSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P1DSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P2DSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P2DSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 1 Drive Strength"]
+    #[inline]
+    pub fn p1ds(&self) -> P1DSR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P1DSR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 2 Drive Strength"]
+    #[inline]
+    pub fn p2ds(&self) -> P2DSR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P2DSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 1 Drive Strength"]
+    #[inline]
+    pub fn p1ds(&mut self) -> _P1DSW {
+        _P1DSW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 2 Drive Strength"]
+    #[inline]
+    pub fn p2ds(&mut self) -> _P2DSW {
+        _P2DSW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/paie.rs b/example-source/msp432p401r/src/dio/paie.rs
new file mode 100644
index 0000000..0d10611
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/paie.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PAIE {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P1IER {
+    bits: u8,
+}
+impl P1IER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P2IER {
+    bits: u8,
+}
+impl P2IER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P1IEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P1IEW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P2IEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P2IEW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 1 Interrupt Enable"]
+    #[inline]
+    pub fn p1ie(&self) -> P1IER {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P1IER { bits }
+    }
+    #[doc = "Bits 8:15 - Port 2 Interrupt Enable"]
+    #[inline]
+    pub fn p2ie(&self) -> P2IER {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P2IER { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 1 Interrupt Enable"]
+    #[inline]
+    pub fn p1ie(&mut self) -> _P1IEW {
+        _P1IEW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 2 Interrupt Enable"]
+    #[inline]
+    pub fn p2ie(&mut self) -> _P2IEW {
+        _P2IEW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/paies.rs b/example-source/msp432p401r/src/dio/paies.rs
new file mode 100644
index 0000000..4a7d671
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/paies.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PAIES {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P1IESR {
+    bits: u8,
+}
+impl P1IESR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P2IESR {
+    bits: u8,
+}
+impl P2IESR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P1IESW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P1IESW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P2IESW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P2IESW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 1 Interrupt Edge Select"]
+    #[inline]
+    pub fn p1ies(&self) -> P1IESR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P1IESR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 2 Interrupt Edge Select"]
+    #[inline]
+    pub fn p2ies(&self) -> P2IESR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P2IESR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 1 Interrupt Edge Select"]
+    #[inline]
+    pub fn p1ies(&mut self) -> _P1IESW {
+        _P1IESW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 2 Interrupt Edge Select"]
+    #[inline]
+    pub fn p2ies(&mut self) -> _P2IESW {
+        _P2IESW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/paifg.rs b/example-source/msp432p401r/src/dio/paifg.rs
new file mode 100644
index 0000000..a9f79f5
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/paifg.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PAIFG {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P1IFGR {
+    bits: u8,
+}
+impl P1IFGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P2IFGR {
+    bits: u8,
+}
+impl P2IFGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P1IFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P1IFGW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P2IFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P2IFGW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 1 Interrupt Flag"]
+    #[inline]
+    pub fn p1ifg(&self) -> P1IFGR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P1IFGR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 2 Interrupt Flag"]
+    #[inline]
+    pub fn p2ifg(&self) -> P2IFGR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P2IFGR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 1 Interrupt Flag"]
+    #[inline]
+    pub fn p1ifg(&mut self) -> _P1IFGW {
+        _P1IFGW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 2 Interrupt Flag"]
+    #[inline]
+    pub fn p2ifg(&mut self) -> _P2IFGW {
+        _P2IFGW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pain.rs b/example-source/msp432p401r/src/dio/pain.rs
new file mode 100644
index 0000000..fa0ad79
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pain.rs
@@ -0,0 +1,62 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::PAIN {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P1INR {
+    bits: u8,
+}
+impl P1INR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P2INR {
+    bits: u8,
+}
+impl P2INR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 1 Input"]
+    #[inline]
+    pub fn p1in(&self) -> P1INR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P1INR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 2 Input"]
+    #[inline]
+    pub fn p2in(&self) -> P2INR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P2INR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/paout.rs b/example-source/msp432p401r/src/dio/paout.rs
new file mode 100644
index 0000000..f273c55
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/paout.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PAOUT {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P2OUTR {
+    bits: u8,
+}
+impl P2OUTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P1OUTR {
+    bits: u8,
+}
+impl P1OUTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P2OUTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P2OUTW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P1OUTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P1OUTW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 8:15 - Port 2 Output"]
+    #[inline]
+    pub fn p2out(&self) -> P2OUTR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P2OUTR { bits }
+    }
+    #[doc = "Bits 0:7 - Port 1 Output"]
+    #[inline]
+    pub fn p1out(&self) -> P1OUTR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P1OUTR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 8:15 - Port 2 Output"]
+    #[inline]
+    pub fn p2out(&mut self) -> _P2OUTW {
+        _P2OUTW { w: self }
+    }
+    #[doc = "Bits 0:7 - Port 1 Output"]
+    #[inline]
+    pub fn p1out(&mut self) -> _P1OUTW {
+        _P1OUTW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/paren.rs b/example-source/msp432p401r/src/dio/paren.rs
new file mode 100644
index 0000000..ff8500f
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/paren.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PAREN {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P1RENR {
+    bits: u8,
+}
+impl P1RENR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P2RENR {
+    bits: u8,
+}
+impl P2RENR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P1RENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P1RENW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P2RENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P2RENW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 1 Resistor Enable"]
+    #[inline]
+    pub fn p1ren(&self) -> P1RENR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P1RENR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 2 Resistor Enable"]
+    #[inline]
+    pub fn p2ren(&self) -> P2RENR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P2RENR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 1 Resistor Enable"]
+    #[inline]
+    pub fn p1ren(&mut self) -> _P1RENW {
+        _P1RENW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 2 Resistor Enable"]
+    #[inline]
+    pub fn p2ren(&mut self) -> _P2RENW {
+        _P2RENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pasel0.rs b/example-source/msp432p401r/src/dio/pasel0.rs
new file mode 100644
index 0000000..c963279
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pasel0.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PASEL0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P1SEL0R {
+    bits: u8,
+}
+impl P1SEL0R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P2SEL0R {
+    bits: u8,
+}
+impl P2SEL0R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P1SEL0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P1SEL0W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P2SEL0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P2SEL0W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 1 Select 0"]
+    #[inline]
+    pub fn p1sel0(&self) -> P1SEL0R {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P1SEL0R { bits }
+    }
+    #[doc = "Bits 8:15 - Port 2 Select 0"]
+    #[inline]
+    pub fn p2sel0(&self) -> P2SEL0R {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P2SEL0R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 1 Select 0"]
+    #[inline]
+    pub fn p1sel0(&mut self) -> _P1SEL0W {
+        _P1SEL0W { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 2 Select 0"]
+    #[inline]
+    pub fn p2sel0(&mut self) -> _P2SEL0W {
+        _P2SEL0W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pasel1.rs b/example-source/msp432p401r/src/dio/pasel1.rs
new file mode 100644
index 0000000..c8e4003
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pasel1.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PASEL1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P1SEL1R {
+    bits: u8,
+}
+impl P1SEL1R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P2SEL1R {
+    bits: u8,
+}
+impl P2SEL1R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P1SEL1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P1SEL1W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P2SEL1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P2SEL1W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 1 Select 1"]
+    #[inline]
+    pub fn p1sel1(&self) -> P1SEL1R {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P1SEL1R { bits }
+    }
+    #[doc = "Bits 8:15 - Port 2 Select 1"]
+    #[inline]
+    pub fn p2sel1(&self) -> P2SEL1R {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P2SEL1R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 1 Select 1"]
+    #[inline]
+    pub fn p1sel1(&mut self) -> _P1SEL1W {
+        _P1SEL1W { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 2 Select 1"]
+    #[inline]
+    pub fn p2sel1(&mut self) -> _P2SEL1W {
+        _P2SEL1W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/paselc.rs b/example-source/msp432p401r/src/dio/paselc.rs
new file mode 100644
index 0000000..b9c5ebf
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/paselc.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PASELC {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P1SELCR {
+    bits: u8,
+}
+impl P1SELCR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P2SELCR {
+    bits: u8,
+}
+impl P2SELCR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P1SELCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P1SELCW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P2SELCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P2SELCW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 1 Complement Select"]
+    #[inline]
+    pub fn p1selc(&self) -> P1SELCR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P1SELCR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 2 Complement Select"]
+    #[inline]
+    pub fn p2selc(&self) -> P2SELCR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P2SELCR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 1 Complement Select"]
+    #[inline]
+    pub fn p1selc(&mut self) -> _P1SELCW {
+        _P1SELCW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 2 Complement Select"]
+    #[inline]
+    pub fn p2selc(&mut self) -> _P2SELCW {
+        _P2SELCW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pbdir.rs b/example-source/msp432p401r/src/dio/pbdir.rs
new file mode 100644
index 0000000..98caa9b
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pbdir.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PBDIR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P3DIRR {
+    bits: u8,
+}
+impl P3DIRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P4DIRR {
+    bits: u8,
+}
+impl P4DIRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P3DIRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P3DIRW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P4DIRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P4DIRW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 3 Direction"]
+    #[inline]
+    pub fn p3dir(&self) -> P3DIRR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P3DIRR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 4 Direction"]
+    #[inline]
+    pub fn p4dir(&self) -> P4DIRR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P4DIRR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 3 Direction"]
+    #[inline]
+    pub fn p3dir(&mut self) -> _P3DIRW {
+        _P3DIRW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 4 Direction"]
+    #[inline]
+    pub fn p4dir(&mut self) -> _P4DIRW {
+        _P4DIRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pbds.rs b/example-source/msp432p401r/src/dio/pbds.rs
new file mode 100644
index 0000000..1a42592
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pbds.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PBDS {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P3DSR {
+    bits: u8,
+}
+impl P3DSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P4DSR {
+    bits: u8,
+}
+impl P4DSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P3DSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P3DSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P4DSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P4DSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 3 Drive Strength"]
+    #[inline]
+    pub fn p3ds(&self) -> P3DSR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P3DSR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 4 Drive Strength"]
+    #[inline]
+    pub fn p4ds(&self) -> P4DSR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P4DSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 3 Drive Strength"]
+    #[inline]
+    pub fn p3ds(&mut self) -> _P3DSW {
+        _P3DSW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 4 Drive Strength"]
+    #[inline]
+    pub fn p4ds(&mut self) -> _P4DSW {
+        _P4DSW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pbie.rs b/example-source/msp432p401r/src/dio/pbie.rs
new file mode 100644
index 0000000..8cf0cee
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pbie.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PBIE {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P3IER {
+    bits: u8,
+}
+impl P3IER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P4IER {
+    bits: u8,
+}
+impl P4IER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P3IEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P3IEW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P4IEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P4IEW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 3 Interrupt Enable"]
+    #[inline]
+    pub fn p3ie(&self) -> P3IER {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P3IER { bits }
+    }
+    #[doc = "Bits 8:15 - Port 4 Interrupt Enable"]
+    #[inline]
+    pub fn p4ie(&self) -> P4IER {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P4IER { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 3 Interrupt Enable"]
+    #[inline]
+    pub fn p3ie(&mut self) -> _P3IEW {
+        _P3IEW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 4 Interrupt Enable"]
+    #[inline]
+    pub fn p4ie(&mut self) -> _P4IEW {
+        _P4IEW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pbies.rs b/example-source/msp432p401r/src/dio/pbies.rs
new file mode 100644
index 0000000..438dee1
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pbies.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PBIES {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P3IESR {
+    bits: u8,
+}
+impl P3IESR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P4IESR {
+    bits: u8,
+}
+impl P4IESR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P3IESW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P3IESW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P4IESW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P4IESW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 3 Interrupt Edge Select"]
+    #[inline]
+    pub fn p3ies(&self) -> P3IESR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P3IESR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 4 Interrupt Edge Select"]
+    #[inline]
+    pub fn p4ies(&self) -> P4IESR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P4IESR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 3 Interrupt Edge Select"]
+    #[inline]
+    pub fn p3ies(&mut self) -> _P3IESW {
+        _P3IESW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 4 Interrupt Edge Select"]
+    #[inline]
+    pub fn p4ies(&mut self) -> _P4IESW {
+        _P4IESW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pbifg.rs b/example-source/msp432p401r/src/dio/pbifg.rs
new file mode 100644
index 0000000..6ed205b
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pbifg.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PBIFG {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P3IFGR {
+    bits: u8,
+}
+impl P3IFGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P4IFGR {
+    bits: u8,
+}
+impl P4IFGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P3IFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P3IFGW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P4IFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P4IFGW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 3 Interrupt Flag"]
+    #[inline]
+    pub fn p3ifg(&self) -> P3IFGR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P3IFGR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 4 Interrupt Flag"]
+    #[inline]
+    pub fn p4ifg(&self) -> P4IFGR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P4IFGR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 3 Interrupt Flag"]
+    #[inline]
+    pub fn p3ifg(&mut self) -> _P3IFGW {
+        _P3IFGW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 4 Interrupt Flag"]
+    #[inline]
+    pub fn p4ifg(&mut self) -> _P4IFGW {
+        _P4IFGW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pbin.rs b/example-source/msp432p401r/src/dio/pbin.rs
new file mode 100644
index 0000000..b217142
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pbin.rs
@@ -0,0 +1,62 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::PBIN {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P3INR {
+    bits: u8,
+}
+impl P3INR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P4INR {
+    bits: u8,
+}
+impl P4INR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 3 Input"]
+    #[inline]
+    pub fn p3in(&self) -> P3INR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P3INR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 4 Input"]
+    #[inline]
+    pub fn p4in(&self) -> P4INR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P4INR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pbout.rs b/example-source/msp432p401r/src/dio/pbout.rs
new file mode 100644
index 0000000..15ef55d
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pbout.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PBOUT {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P3OUTR {
+    bits: u8,
+}
+impl P3OUTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P4OUTR {
+    bits: u8,
+}
+impl P4OUTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P3OUTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P3OUTW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P4OUTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P4OUTW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 3 Output"]
+    #[inline]
+    pub fn p3out(&self) -> P3OUTR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P3OUTR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 4 Output"]
+    #[inline]
+    pub fn p4out(&self) -> P4OUTR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P4OUTR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 3 Output"]
+    #[inline]
+    pub fn p3out(&mut self) -> _P3OUTW {
+        _P3OUTW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 4 Output"]
+    #[inline]
+    pub fn p4out(&mut self) -> _P4OUTW {
+        _P4OUTW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pbren.rs b/example-source/msp432p401r/src/dio/pbren.rs
new file mode 100644
index 0000000..98c7740
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pbren.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PBREN {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P3RENR {
+    bits: u8,
+}
+impl P3RENR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P4RENR {
+    bits: u8,
+}
+impl P4RENR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P3RENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P3RENW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P4RENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P4RENW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 3 Resistor Enable"]
+    #[inline]
+    pub fn p3ren(&self) -> P3RENR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P3RENR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 4 Resistor Enable"]
+    #[inline]
+    pub fn p4ren(&self) -> P4RENR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P4RENR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 3 Resistor Enable"]
+    #[inline]
+    pub fn p3ren(&mut self) -> _P3RENW {
+        _P3RENW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 4 Resistor Enable"]
+    #[inline]
+    pub fn p4ren(&mut self) -> _P4RENW {
+        _P4RENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pbsel0.rs b/example-source/msp432p401r/src/dio/pbsel0.rs
new file mode 100644
index 0000000..34e1bee
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pbsel0.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PBSEL0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P4SEL0R {
+    bits: u8,
+}
+impl P4SEL0R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P3SEL0R {
+    bits: u8,
+}
+impl P3SEL0R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P4SEL0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P4SEL0W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P3SEL0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P3SEL0W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 8:15 - Port 4 Select 0"]
+    #[inline]
+    pub fn p4sel0(&self) -> P4SEL0R {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P4SEL0R { bits }
+    }
+    #[doc = "Bits 0:7 - Port 3 Select 0"]
+    #[inline]
+    pub fn p3sel0(&self) -> P3SEL0R {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P3SEL0R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 8:15 - Port 4 Select 0"]
+    #[inline]
+    pub fn p4sel0(&mut self) -> _P4SEL0W {
+        _P4SEL0W { w: self }
+    }
+    #[doc = "Bits 0:7 - Port 3 Select 0"]
+    #[inline]
+    pub fn p3sel0(&mut self) -> _P3SEL0W {
+        _P3SEL0W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pbsel1.rs b/example-source/msp432p401r/src/dio/pbsel1.rs
new file mode 100644
index 0000000..d3da7ad
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pbsel1.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PBSEL1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P3SEL1R {
+    bits: u8,
+}
+impl P3SEL1R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P4SEL1R {
+    bits: u8,
+}
+impl P4SEL1R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P3SEL1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P3SEL1W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P4SEL1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P4SEL1W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 3 Select 1"]
+    #[inline]
+    pub fn p3sel1(&self) -> P3SEL1R {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P3SEL1R { bits }
+    }
+    #[doc = "Bits 8:15 - Port 4 Select 1"]
+    #[inline]
+    pub fn p4sel1(&self) -> P4SEL1R {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P4SEL1R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 3 Select 1"]
+    #[inline]
+    pub fn p3sel1(&mut self) -> _P3SEL1W {
+        _P3SEL1W { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 4 Select 1"]
+    #[inline]
+    pub fn p4sel1(&mut self) -> _P4SEL1W {
+        _P4SEL1W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pbselc.rs b/example-source/msp432p401r/src/dio/pbselc.rs
new file mode 100644
index 0000000..ee68977
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pbselc.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PBSELC {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P3SELCR {
+    bits: u8,
+}
+impl P3SELCR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P4SELCR {
+    bits: u8,
+}
+impl P4SELCR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P3SELCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P3SELCW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P4SELCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P4SELCW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 3 Complement Select"]
+    #[inline]
+    pub fn p3selc(&self) -> P3SELCR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P3SELCR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 4 Complement Select"]
+    #[inline]
+    pub fn p4selc(&self) -> P4SELCR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P4SELCR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 3 Complement Select"]
+    #[inline]
+    pub fn p3selc(&mut self) -> _P3SELCW {
+        _P3SELCW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 4 Complement Select"]
+    #[inline]
+    pub fn p4selc(&mut self) -> _P4SELCW {
+        _P4SELCW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pcdir.rs b/example-source/msp432p401r/src/dio/pcdir.rs
new file mode 100644
index 0000000..9ac7ba5
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pcdir.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PCDIR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P5DIRR {
+    bits: u8,
+}
+impl P5DIRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P6DIRR {
+    bits: u8,
+}
+impl P6DIRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P5DIRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P5DIRW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P6DIRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P6DIRW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 5 Direction"]
+    #[inline]
+    pub fn p5dir(&self) -> P5DIRR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P5DIRR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 6 Direction"]
+    #[inline]
+    pub fn p6dir(&self) -> P6DIRR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P6DIRR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 5 Direction"]
+    #[inline]
+    pub fn p5dir(&mut self) -> _P5DIRW {
+        _P5DIRW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 6 Direction"]
+    #[inline]
+    pub fn p6dir(&mut self) -> _P6DIRW {
+        _P6DIRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pcds.rs b/example-source/msp432p401r/src/dio/pcds.rs
new file mode 100644
index 0000000..48664fb
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pcds.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PCDS {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P5DSR {
+    bits: u8,
+}
+impl P5DSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P6DSR {
+    bits: u8,
+}
+impl P6DSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P5DSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P5DSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P6DSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P6DSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 5 Drive Strength"]
+    #[inline]
+    pub fn p5ds(&self) -> P5DSR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P5DSR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 6 Drive Strength"]
+    #[inline]
+    pub fn p6ds(&self) -> P6DSR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P6DSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 5 Drive Strength"]
+    #[inline]
+    pub fn p5ds(&mut self) -> _P5DSW {
+        _P5DSW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 6 Drive Strength"]
+    #[inline]
+    pub fn p6ds(&mut self) -> _P6DSW {
+        _P6DSW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pcie.rs b/example-source/msp432p401r/src/dio/pcie.rs
new file mode 100644
index 0000000..c583f44
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pcie.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PCIE {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P5IER {
+    bits: u8,
+}
+impl P5IER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P6IER {
+    bits: u8,
+}
+impl P6IER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P5IEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P5IEW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P6IEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P6IEW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 5 Interrupt Enable"]
+    #[inline]
+    pub fn p5ie(&self) -> P5IER {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P5IER { bits }
+    }
+    #[doc = "Bits 8:15 - Port 6 Interrupt Enable"]
+    #[inline]
+    pub fn p6ie(&self) -> P6IER {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P6IER { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 5 Interrupt Enable"]
+    #[inline]
+    pub fn p5ie(&mut self) -> _P5IEW {
+        _P5IEW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 6 Interrupt Enable"]
+    #[inline]
+    pub fn p6ie(&mut self) -> _P6IEW {
+        _P6IEW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pcies.rs b/example-source/msp432p401r/src/dio/pcies.rs
new file mode 100644
index 0000000..6ec1a5b
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pcies.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PCIES {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P5IESR {
+    bits: u8,
+}
+impl P5IESR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P6IESR {
+    bits: u8,
+}
+impl P6IESR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P5IESW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P5IESW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P6IESW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P6IESW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 5 Interrupt Edge Select"]
+    #[inline]
+    pub fn p5ies(&self) -> P5IESR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P5IESR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 6 Interrupt Edge Select"]
+    #[inline]
+    pub fn p6ies(&self) -> P6IESR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P6IESR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 5 Interrupt Edge Select"]
+    #[inline]
+    pub fn p5ies(&mut self) -> _P5IESW {
+        _P5IESW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 6 Interrupt Edge Select"]
+    #[inline]
+    pub fn p6ies(&mut self) -> _P6IESW {
+        _P6IESW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pcifg.rs b/example-source/msp432p401r/src/dio/pcifg.rs
new file mode 100644
index 0000000..4d65def
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pcifg.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PCIFG {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P5IFGR {
+    bits: u8,
+}
+impl P5IFGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P6IFGR {
+    bits: u8,
+}
+impl P6IFGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P5IFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P5IFGW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P6IFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P6IFGW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 5 Interrupt Flag"]
+    #[inline]
+    pub fn p5ifg(&self) -> P5IFGR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P5IFGR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 6 Interrupt Flag"]
+    #[inline]
+    pub fn p6ifg(&self) -> P6IFGR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P6IFGR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 5 Interrupt Flag"]
+    #[inline]
+    pub fn p5ifg(&mut self) -> _P5IFGW {
+        _P5IFGW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 6 Interrupt Flag"]
+    #[inline]
+    pub fn p6ifg(&mut self) -> _P6IFGW {
+        _P6IFGW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pcin.rs b/example-source/msp432p401r/src/dio/pcin.rs
new file mode 100644
index 0000000..d76b871
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pcin.rs
@@ -0,0 +1,62 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::PCIN {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P5INR {
+    bits: u8,
+}
+impl P5INR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P6INR {
+    bits: u8,
+}
+impl P6INR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 5 Input"]
+    #[inline]
+    pub fn p5in(&self) -> P5INR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P5INR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 6 Input"]
+    #[inline]
+    pub fn p6in(&self) -> P6INR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P6INR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pcout.rs b/example-source/msp432p401r/src/dio/pcout.rs
new file mode 100644
index 0000000..87d7d0f
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pcout.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PCOUT {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P5OUTR {
+    bits: u8,
+}
+impl P5OUTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P6OUTR {
+    bits: u8,
+}
+impl P6OUTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P5OUTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P5OUTW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P6OUTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P6OUTW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 5 Output"]
+    #[inline]
+    pub fn p5out(&self) -> P5OUTR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P5OUTR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 6 Output"]
+    #[inline]
+    pub fn p6out(&self) -> P6OUTR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P6OUTR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 5 Output"]
+    #[inline]
+    pub fn p5out(&mut self) -> _P5OUTW {
+        _P5OUTW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 6 Output"]
+    #[inline]
+    pub fn p6out(&mut self) -> _P6OUTW {
+        _P6OUTW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pcren.rs b/example-source/msp432p401r/src/dio/pcren.rs
new file mode 100644
index 0000000..1550cfe
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pcren.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PCREN {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P5RENR {
+    bits: u8,
+}
+impl P5RENR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P6RENR {
+    bits: u8,
+}
+impl P6RENR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P5RENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P5RENW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P6RENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P6RENW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 5 Resistor Enable"]
+    #[inline]
+    pub fn p5ren(&self) -> P5RENR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P5RENR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 6 Resistor Enable"]
+    #[inline]
+    pub fn p6ren(&self) -> P6RENR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P6RENR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 5 Resistor Enable"]
+    #[inline]
+    pub fn p5ren(&mut self) -> _P5RENW {
+        _P5RENW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 6 Resistor Enable"]
+    #[inline]
+    pub fn p6ren(&mut self) -> _P6RENW {
+        _P6RENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pcsel0.rs b/example-source/msp432p401r/src/dio/pcsel0.rs
new file mode 100644
index 0000000..2c132c8
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pcsel0.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PCSEL0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P5SEL0R {
+    bits: u8,
+}
+impl P5SEL0R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P6SEL0R {
+    bits: u8,
+}
+impl P6SEL0R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P5SEL0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P5SEL0W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P6SEL0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P6SEL0W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 5 Select 0"]
+    #[inline]
+    pub fn p5sel0(&self) -> P5SEL0R {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P5SEL0R { bits }
+    }
+    #[doc = "Bits 8:15 - Port 6 Select 0"]
+    #[inline]
+    pub fn p6sel0(&self) -> P6SEL0R {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P6SEL0R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 5 Select 0"]
+    #[inline]
+    pub fn p5sel0(&mut self) -> _P5SEL0W {
+        _P5SEL0W { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 6 Select 0"]
+    #[inline]
+    pub fn p6sel0(&mut self) -> _P6SEL0W {
+        _P6SEL0W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pcsel1.rs b/example-source/msp432p401r/src/dio/pcsel1.rs
new file mode 100644
index 0000000..b4b069c
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pcsel1.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PCSEL1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P5SEL1R {
+    bits: u8,
+}
+impl P5SEL1R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P6SEL1R {
+    bits: u8,
+}
+impl P6SEL1R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P5SEL1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P5SEL1W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P6SEL1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P6SEL1W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 5 Select 1"]
+    #[inline]
+    pub fn p5sel1(&self) -> P5SEL1R {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P5SEL1R { bits }
+    }
+    #[doc = "Bits 8:15 - Port 6 Select 1"]
+    #[inline]
+    pub fn p6sel1(&self) -> P6SEL1R {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P6SEL1R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 5 Select 1"]
+    #[inline]
+    pub fn p5sel1(&mut self) -> _P5SEL1W {
+        _P5SEL1W { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 6 Select 1"]
+    #[inline]
+    pub fn p6sel1(&mut self) -> _P6SEL1W {
+        _P6SEL1W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pcselc.rs b/example-source/msp432p401r/src/dio/pcselc.rs
new file mode 100644
index 0000000..304eab9
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pcselc.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PCSELC {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P5SELCR {
+    bits: u8,
+}
+impl P5SELCR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P6SELCR {
+    bits: u8,
+}
+impl P6SELCR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P5SELCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P5SELCW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P6SELCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P6SELCW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 5 Complement Select"]
+    #[inline]
+    pub fn p5selc(&self) -> P5SELCR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P5SELCR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 6 Complement Select"]
+    #[inline]
+    pub fn p6selc(&self) -> P6SELCR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P6SELCR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 5 Complement Select"]
+    #[inline]
+    pub fn p5selc(&mut self) -> _P5SELCW {
+        _P5SELCW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 6 Complement Select"]
+    #[inline]
+    pub fn p6selc(&mut self) -> _P6SELCW {
+        _P6SELCW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pddir.rs b/example-source/msp432p401r/src/dio/pddir.rs
new file mode 100644
index 0000000..c1601d9
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pddir.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PDDIR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P7DIRR {
+    bits: u8,
+}
+impl P7DIRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P8DIRR {
+    bits: u8,
+}
+impl P8DIRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P7DIRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P7DIRW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P8DIRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P8DIRW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 7 Direction"]
+    #[inline]
+    pub fn p7dir(&self) -> P7DIRR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P7DIRR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 8 Direction"]
+    #[inline]
+    pub fn p8dir(&self) -> P8DIRR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P8DIRR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 7 Direction"]
+    #[inline]
+    pub fn p7dir(&mut self) -> _P7DIRW {
+        _P7DIRW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 8 Direction"]
+    #[inline]
+    pub fn p8dir(&mut self) -> _P8DIRW {
+        _P8DIRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pdds.rs b/example-source/msp432p401r/src/dio/pdds.rs
new file mode 100644
index 0000000..c15da57
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pdds.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PDDS {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P7DSR {
+    bits: u8,
+}
+impl P7DSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P8DSR {
+    bits: u8,
+}
+impl P8DSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P7DSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P7DSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P8DSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P8DSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 7 Drive Strength"]
+    #[inline]
+    pub fn p7ds(&self) -> P7DSR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P7DSR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 8 Drive Strength"]
+    #[inline]
+    pub fn p8ds(&self) -> P8DSR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P8DSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 7 Drive Strength"]
+    #[inline]
+    pub fn p7ds(&mut self) -> _P7DSW {
+        _P7DSW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 8 Drive Strength"]
+    #[inline]
+    pub fn p8ds(&mut self) -> _P8DSW {
+        _P8DSW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pdie.rs b/example-source/msp432p401r/src/dio/pdie.rs
new file mode 100644
index 0000000..ee81dd3
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pdie.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PDIE {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P7IER {
+    bits: u8,
+}
+impl P7IER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P8IER {
+    bits: u8,
+}
+impl P8IER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P7IEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P7IEW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P8IEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P8IEW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 7 Interrupt Enable"]
+    #[inline]
+    pub fn p7ie(&self) -> P7IER {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P7IER { bits }
+    }
+    #[doc = "Bits 8:15 - Port 8 Interrupt Enable"]
+    #[inline]
+    pub fn p8ie(&self) -> P8IER {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P8IER { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 7 Interrupt Enable"]
+    #[inline]
+    pub fn p7ie(&mut self) -> _P7IEW {
+        _P7IEW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 8 Interrupt Enable"]
+    #[inline]
+    pub fn p8ie(&mut self) -> _P8IEW {
+        _P8IEW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pdies.rs b/example-source/msp432p401r/src/dio/pdies.rs
new file mode 100644
index 0000000..2adc10e
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pdies.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PDIES {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P7IESR {
+    bits: u8,
+}
+impl P7IESR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P8IESR {
+    bits: u8,
+}
+impl P8IESR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P7IESW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P7IESW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P8IESW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P8IESW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 7 Interrupt Edge Select"]
+    #[inline]
+    pub fn p7ies(&self) -> P7IESR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P7IESR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 8 Interrupt Edge Select"]
+    #[inline]
+    pub fn p8ies(&self) -> P8IESR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P8IESR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 7 Interrupt Edge Select"]
+    #[inline]
+    pub fn p7ies(&mut self) -> _P7IESW {
+        _P7IESW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 8 Interrupt Edge Select"]
+    #[inline]
+    pub fn p8ies(&mut self) -> _P8IESW {
+        _P8IESW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pdifg.rs b/example-source/msp432p401r/src/dio/pdifg.rs
new file mode 100644
index 0000000..784c676
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pdifg.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PDIFG {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P7IFGR {
+    bits: u8,
+}
+impl P7IFGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P8IFGR {
+    bits: u8,
+}
+impl P8IFGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P7IFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P7IFGW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P8IFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P8IFGW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 7 Interrupt Flag"]
+    #[inline]
+    pub fn p7ifg(&self) -> P7IFGR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P7IFGR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 8 Interrupt Flag"]
+    #[inline]
+    pub fn p8ifg(&self) -> P8IFGR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P8IFGR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 7 Interrupt Flag"]
+    #[inline]
+    pub fn p7ifg(&mut self) -> _P7IFGW {
+        _P7IFGW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 8 Interrupt Flag"]
+    #[inline]
+    pub fn p8ifg(&mut self) -> _P8IFGW {
+        _P8IFGW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pdin.rs b/example-source/msp432p401r/src/dio/pdin.rs
new file mode 100644
index 0000000..049a6f0
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pdin.rs
@@ -0,0 +1,62 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::PDIN {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P7INR {
+    bits: u8,
+}
+impl P7INR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P8INR {
+    bits: u8,
+}
+impl P8INR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 7 Input"]
+    #[inline]
+    pub fn p7in(&self) -> P7INR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P7INR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 8 Input"]
+    #[inline]
+    pub fn p8in(&self) -> P8INR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P8INR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pdout.rs b/example-source/msp432p401r/src/dio/pdout.rs
new file mode 100644
index 0000000..d64fa77
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pdout.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PDOUT {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P7OUTR {
+    bits: u8,
+}
+impl P7OUTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P8OUTR {
+    bits: u8,
+}
+impl P8OUTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P7OUTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P7OUTW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P8OUTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P8OUTW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 7 Output"]
+    #[inline]
+    pub fn p7out(&self) -> P7OUTR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P7OUTR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 8 Output"]
+    #[inline]
+    pub fn p8out(&self) -> P8OUTR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P8OUTR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 7 Output"]
+    #[inline]
+    pub fn p7out(&mut self) -> _P7OUTW {
+        _P7OUTW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 8 Output"]
+    #[inline]
+    pub fn p8out(&mut self) -> _P8OUTW {
+        _P8OUTW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pdren.rs b/example-source/msp432p401r/src/dio/pdren.rs
new file mode 100644
index 0000000..b7c8f4f
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pdren.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PDREN {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P7RENR {
+    bits: u8,
+}
+impl P7RENR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P8RENR {
+    bits: u8,
+}
+impl P8RENR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P7RENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P7RENW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P8RENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P8RENW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 7 Resistor Enable"]
+    #[inline]
+    pub fn p7ren(&self) -> P7RENR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P7RENR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 8 Resistor Enable"]
+    #[inline]
+    pub fn p8ren(&self) -> P8RENR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P8RENR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 7 Resistor Enable"]
+    #[inline]
+    pub fn p7ren(&mut self) -> _P7RENW {
+        _P7RENW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 8 Resistor Enable"]
+    #[inline]
+    pub fn p8ren(&mut self) -> _P8RENW {
+        _P8RENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pdsel0.rs b/example-source/msp432p401r/src/dio/pdsel0.rs
new file mode 100644
index 0000000..dbbccd1
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pdsel0.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PDSEL0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P7SEL0R {
+    bits: u8,
+}
+impl P7SEL0R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P8SEL0R {
+    bits: u8,
+}
+impl P8SEL0R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P7SEL0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P7SEL0W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P8SEL0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P8SEL0W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 7 Select 0"]
+    #[inline]
+    pub fn p7sel0(&self) -> P7SEL0R {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P7SEL0R { bits }
+    }
+    #[doc = "Bits 8:15 - Port 8 Select 0"]
+    #[inline]
+    pub fn p8sel0(&self) -> P8SEL0R {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P8SEL0R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 7 Select 0"]
+    #[inline]
+    pub fn p7sel0(&mut self) -> _P7SEL0W {
+        _P7SEL0W { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 8 Select 0"]
+    #[inline]
+    pub fn p8sel0(&mut self) -> _P8SEL0W {
+        _P8SEL0W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pdsel1.rs b/example-source/msp432p401r/src/dio/pdsel1.rs
new file mode 100644
index 0000000..e10587c
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pdsel1.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PDSEL1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P7SEL1R {
+    bits: u8,
+}
+impl P7SEL1R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P8SEL1R {
+    bits: u8,
+}
+impl P8SEL1R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P7SEL1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P7SEL1W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P8SEL1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P8SEL1W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 7 Select 1"]
+    #[inline]
+    pub fn p7sel1(&self) -> P7SEL1R {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P7SEL1R { bits }
+    }
+    #[doc = "Bits 8:15 - Port 8 Select 1"]
+    #[inline]
+    pub fn p8sel1(&self) -> P8SEL1R {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P8SEL1R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 7 Select 1"]
+    #[inline]
+    pub fn p7sel1(&mut self) -> _P7SEL1W {
+        _P7SEL1W { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 8 Select 1"]
+    #[inline]
+    pub fn p8sel1(&mut self) -> _P8SEL1W {
+        _P8SEL1W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pdselc.rs b/example-source/msp432p401r/src/dio/pdselc.rs
new file mode 100644
index 0000000..70ff637
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pdselc.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PDSELC {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P7SELCR {
+    bits: u8,
+}
+impl P7SELCR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P8SELCR {
+    bits: u8,
+}
+impl P8SELCR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P7SELCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P7SELCW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P8SELCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P8SELCW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 7 Complement Select"]
+    #[inline]
+    pub fn p7selc(&self) -> P7SELCR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P7SELCR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 8 Complement Select"]
+    #[inline]
+    pub fn p8selc(&self) -> P8SELCR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P8SELCR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 7 Complement Select"]
+    #[inline]
+    pub fn p7selc(&mut self) -> _P7SELCW {
+        _P7SELCW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 8 Complement Select"]
+    #[inline]
+    pub fn p8selc(&mut self) -> _P8SELCW {
+        _P8SELCW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pedir.rs b/example-source/msp432p401r/src/dio/pedir.rs
new file mode 100644
index 0000000..a777876
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pedir.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PEDIR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P9DIRR {
+    bits: u8,
+}
+impl P9DIRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P10DIRR {
+    bits: u8,
+}
+impl P10DIRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P9DIRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P9DIRW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P10DIRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P10DIRW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 9 Direction"]
+    #[inline]
+    pub fn p9dir(&self) -> P9DIRR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P9DIRR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 10 Direction"]
+    #[inline]
+    pub fn p10dir(&self) -> P10DIRR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P10DIRR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 9 Direction"]
+    #[inline]
+    pub fn p9dir(&mut self) -> _P9DIRW {
+        _P9DIRW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 10 Direction"]
+    #[inline]
+    pub fn p10dir(&mut self) -> _P10DIRW {
+        _P10DIRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/peds.rs b/example-source/msp432p401r/src/dio/peds.rs
new file mode 100644
index 0000000..80acd88
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/peds.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PEDS {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P9DSR {
+    bits: u8,
+}
+impl P9DSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P10DSR {
+    bits: u8,
+}
+impl P10DSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P9DSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P9DSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P10DSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P10DSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 9 Drive Strength"]
+    #[inline]
+    pub fn p9ds(&self) -> P9DSR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P9DSR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 10 Drive Strength"]
+    #[inline]
+    pub fn p10ds(&self) -> P10DSR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P10DSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 9 Drive Strength"]
+    #[inline]
+    pub fn p9ds(&mut self) -> _P9DSW {
+        _P9DSW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 10 Drive Strength"]
+    #[inline]
+    pub fn p10ds(&mut self) -> _P10DSW {
+        _P10DSW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/peie.rs b/example-source/msp432p401r/src/dio/peie.rs
new file mode 100644
index 0000000..b50dfd6
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/peie.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PEIE {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P9IER {
+    bits: u8,
+}
+impl P9IER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P10IER {
+    bits: u8,
+}
+impl P10IER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P9IEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P9IEW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P10IEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P10IEW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 9 Interrupt Enable"]
+    #[inline]
+    pub fn p9ie(&self) -> P9IER {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P9IER { bits }
+    }
+    #[doc = "Bits 8:15 - Port 10 Interrupt Enable"]
+    #[inline]
+    pub fn p10ie(&self) -> P10IER {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P10IER { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 9 Interrupt Enable"]
+    #[inline]
+    pub fn p9ie(&mut self) -> _P9IEW {
+        _P9IEW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 10 Interrupt Enable"]
+    #[inline]
+    pub fn p10ie(&mut self) -> _P10IEW {
+        _P10IEW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/peies.rs b/example-source/msp432p401r/src/dio/peies.rs
new file mode 100644
index 0000000..992dad3
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/peies.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PEIES {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P9IESR {
+    bits: u8,
+}
+impl P9IESR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P10IESR {
+    bits: u8,
+}
+impl P10IESR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P9IESW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P9IESW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P10IESW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P10IESW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 9 Interrupt Edge Select"]
+    #[inline]
+    pub fn p9ies(&self) -> P9IESR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P9IESR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 10 Interrupt Edge Select"]
+    #[inline]
+    pub fn p10ies(&self) -> P10IESR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P10IESR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 9 Interrupt Edge Select"]
+    #[inline]
+    pub fn p9ies(&mut self) -> _P9IESW {
+        _P9IESW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 10 Interrupt Edge Select"]
+    #[inline]
+    pub fn p10ies(&mut self) -> _P10IESW {
+        _P10IESW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/peifg.rs b/example-source/msp432p401r/src/dio/peifg.rs
new file mode 100644
index 0000000..b74ca72
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/peifg.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PEIFG {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P9IFGR {
+    bits: u8,
+}
+impl P9IFGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P10IFGR {
+    bits: u8,
+}
+impl P10IFGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P9IFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P9IFGW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P10IFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P10IFGW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 9 Interrupt Flag"]
+    #[inline]
+    pub fn p9ifg(&self) -> P9IFGR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P9IFGR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 10 Interrupt Flag"]
+    #[inline]
+    pub fn p10ifg(&self) -> P10IFGR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P10IFGR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 9 Interrupt Flag"]
+    #[inline]
+    pub fn p9ifg(&mut self) -> _P9IFGW {
+        _P9IFGW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 10 Interrupt Flag"]
+    #[inline]
+    pub fn p10ifg(&mut self) -> _P10IFGW {
+        _P10IFGW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pein.rs b/example-source/msp432p401r/src/dio/pein.rs
new file mode 100644
index 0000000..7b1530e
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pein.rs
@@ -0,0 +1,62 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::PEIN {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P9INR {
+    bits: u8,
+}
+impl P9INR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P10INR {
+    bits: u8,
+}
+impl P10INR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 9 Input"]
+    #[inline]
+    pub fn p9in(&self) -> P9INR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P9INR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 10 Input"]
+    #[inline]
+    pub fn p10in(&self) -> P10INR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P10INR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/peout.rs b/example-source/msp432p401r/src/dio/peout.rs
new file mode 100644
index 0000000..78febdb
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/peout.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PEOUT {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P9OUTR {
+    bits: u8,
+}
+impl P9OUTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P10OUTR {
+    bits: u8,
+}
+impl P10OUTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P9OUTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P9OUTW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P10OUTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P10OUTW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 9 Output"]
+    #[inline]
+    pub fn p9out(&self) -> P9OUTR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P9OUTR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 10 Output"]
+    #[inline]
+    pub fn p10out(&self) -> P10OUTR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P10OUTR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 9 Output"]
+    #[inline]
+    pub fn p9out(&mut self) -> _P9OUTW {
+        _P9OUTW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 10 Output"]
+    #[inline]
+    pub fn p10out(&mut self) -> _P10OUTW {
+        _P10OUTW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/peren.rs b/example-source/msp432p401r/src/dio/peren.rs
new file mode 100644
index 0000000..c6220c2
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/peren.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PEREN {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P9RENR {
+    bits: u8,
+}
+impl P9RENR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P10RENR {
+    bits: u8,
+}
+impl P10RENR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P9RENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P9RENW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P10RENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P10RENW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 9 Resistor Enable"]
+    #[inline]
+    pub fn p9ren(&self) -> P9RENR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P9RENR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 10 Resistor Enable"]
+    #[inline]
+    pub fn p10ren(&self) -> P10RENR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P10RENR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 9 Resistor Enable"]
+    #[inline]
+    pub fn p9ren(&mut self) -> _P9RENW {
+        _P9RENW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 10 Resistor Enable"]
+    #[inline]
+    pub fn p10ren(&mut self) -> _P10RENW {
+        _P10RENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pesel0.rs b/example-source/msp432p401r/src/dio/pesel0.rs
new file mode 100644
index 0000000..f02b307
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pesel0.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PESEL0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P9SEL0R {
+    bits: u8,
+}
+impl P9SEL0R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P10SEL0R {
+    bits: u8,
+}
+impl P10SEL0R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P9SEL0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P9SEL0W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P10SEL0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P10SEL0W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 9 Select 0"]
+    #[inline]
+    pub fn p9sel0(&self) -> P9SEL0R {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P9SEL0R { bits }
+    }
+    #[doc = "Bits 8:15 - Port 10 Select 0"]
+    #[inline]
+    pub fn p10sel0(&self) -> P10SEL0R {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P10SEL0R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 9 Select 0"]
+    #[inline]
+    pub fn p9sel0(&mut self) -> _P9SEL0W {
+        _P9SEL0W { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 10 Select 0"]
+    #[inline]
+    pub fn p10sel0(&mut self) -> _P10SEL0W {
+        _P10SEL0W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pesel1.rs b/example-source/msp432p401r/src/dio/pesel1.rs
new file mode 100644
index 0000000..2948654
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pesel1.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PESEL1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P9SEL1R {
+    bits: u8,
+}
+impl P9SEL1R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P10SEL1R {
+    bits: u8,
+}
+impl P10SEL1R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P9SEL1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P9SEL1W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P10SEL1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P10SEL1W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 9 Select 1"]
+    #[inline]
+    pub fn p9sel1(&self) -> P9SEL1R {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P9SEL1R { bits }
+    }
+    #[doc = "Bits 8:15 - Port 10 Select 1"]
+    #[inline]
+    pub fn p10sel1(&self) -> P10SEL1R {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P10SEL1R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 9 Select 1"]
+    #[inline]
+    pub fn p9sel1(&mut self) -> _P9SEL1W {
+        _P9SEL1W { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 10 Select 1"]
+    #[inline]
+    pub fn p10sel1(&mut self) -> _P10SEL1W {
+        _P10SEL1W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/peselc.rs b/example-source/msp432p401r/src/dio/peselc.rs
new file mode 100644
index 0000000..9b1adb0
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/peselc.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PESELC {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P9SELCR {
+    bits: u8,
+}
+impl P9SELCR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct P10SELCR {
+    bits: u8,
+}
+impl P10SELCR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P9SELCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P9SELCW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _P10SELCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _P10SELCW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Port 9 Complement Select"]
+    #[inline]
+    pub fn p9selc(&self) -> P9SELCR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P9SELCR { bits }
+    }
+    #[doc = "Bits 8:15 - Port 10 Complement Select"]
+    #[inline]
+    pub fn p10selc(&self) -> P10SELCR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        P10SELCR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Port 9 Complement Select"]
+    #[inline]
+    pub fn p9selc(&mut self) -> _P9SELCW {
+        _P9SELCW { w: self }
+    }
+    #[doc = "Bits 8:15 - Port 10 Complement Select"]
+    #[inline]
+    pub fn p10selc(&mut self) -> _P10SELCW {
+        _P10SELCW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pjdir.rs b/example-source/msp432p401r/src/dio/pjdir.rs
new file mode 100644
index 0000000..bdefad9
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pjdir.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PJDIR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PJDIRR {
+    bits: u16,
+}
+impl PJDIRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PJDIRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PJDIRW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Port J Direction"]
+    #[inline]
+    pub fn pjdir(&self) -> PJDIRR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PJDIRR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Port J Direction"]
+    #[inline]
+    pub fn pjdir(&mut self) -> _PJDIRW {
+        _PJDIRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pjds.rs b/example-source/msp432p401r/src/dio/pjds.rs
new file mode 100644
index 0000000..7f7a3fa
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pjds.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PJDS {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PJDSR {
+    bits: u16,
+}
+impl PJDSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PJDSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PJDSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Port J Drive Strength"]
+    #[inline]
+    pub fn pjds(&self) -> PJDSR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PJDSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Port J Drive Strength"]
+    #[inline]
+    pub fn pjds(&mut self) -> _PJDSW {
+        _PJDSW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pjin.rs b/example-source/msp432p401r/src/dio/pjin.rs
new file mode 100644
index 0000000..9c3d926
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pjin.rs
@@ -0,0 +1,41 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::PJIN {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PJINR {
+    bits: u16,
+}
+impl PJINR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Port J Input"]
+    #[inline]
+    pub fn pjin(&self) -> PJINR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PJINR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pjout.rs b/example-source/msp432p401r/src/dio/pjout.rs
new file mode 100644
index 0000000..ccc5c39
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pjout.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PJOUT {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PJOUTR {
+    bits: u16,
+}
+impl PJOUTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PJOUTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PJOUTW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Port J Output"]
+    #[inline]
+    pub fn pjout(&self) -> PJOUTR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PJOUTR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Port J Output"]
+    #[inline]
+    pub fn pjout(&mut self) -> _PJOUTW {
+        _PJOUTW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pjren.rs b/example-source/msp432p401r/src/dio/pjren.rs
new file mode 100644
index 0000000..83156a4
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pjren.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PJREN {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PJRENR {
+    bits: u16,
+}
+impl PJRENR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PJRENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PJRENW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Port J Resistor Enable"]
+    #[inline]
+    pub fn pjren(&self) -> PJRENR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PJRENR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Port J Resistor Enable"]
+    #[inline]
+    pub fn pjren(&mut self) -> _PJRENW {
+        _PJRENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pjsel0.rs b/example-source/msp432p401r/src/dio/pjsel0.rs
new file mode 100644
index 0000000..a0965ef
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pjsel0.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PJSEL0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PJSEL0R {
+    bits: u16,
+}
+impl PJSEL0R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PJSEL0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PJSEL0W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Port J Select 0"]
+    #[inline]
+    pub fn pjsel0(&self) -> PJSEL0R {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PJSEL0R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Port J Select 0"]
+    #[inline]
+    pub fn pjsel0(&mut self) -> _PJSEL0W {
+        _PJSEL0W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pjsel1.rs b/example-source/msp432p401r/src/dio/pjsel1.rs
new file mode 100644
index 0000000..36faee3
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pjsel1.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PJSEL1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PJSEL1R {
+    bits: u16,
+}
+impl PJSEL1R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PJSEL1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PJSEL1W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Port J Select 1"]
+    #[inline]
+    pub fn pjsel1(&self) -> PJSEL1R {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PJSEL1R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Port J Select 1"]
+    #[inline]
+    pub fn pjsel1(&mut self) -> _PJSEL1W {
+        _PJSEL1W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dio/pjselc.rs b/example-source/msp432p401r/src/dio/pjselc.rs
new file mode 100644
index 0000000..693f721
--- /dev/null
+++ b/example-source/msp432p401r/src/dio/pjselc.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PJSELC {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PJSELCR {
+    bits: u16,
+}
+impl PJSELCR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PJSELCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PJSELCW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Port J Complement Select"]
+    #[inline]
+    pub fn pjselc(&self) -> PJSELCR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PJSELCR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Port J Complement Select"]
+    #[inline]
+    pub fn pjselc(&mut self) -> _PJSELCW {
+        _PJSELCW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dma.rs b/example-source/msp432p401r/src/dma.rs
new file mode 100644
index 0000000..535b126
--- /dev/null
+++ b/example-source/msp432p401r/src/dma.rs
@@ -0,0 +1,209 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - Device Configuration Status"]
+    pub dma_device_cfg: DMA_DEVICE_CFG,
+    #[doc = "0x04 - Software Channel Trigger Register"]
+    pub dma_sw_chtrig: DMA_SW_CHTRIG,
+    _reserved0: [u8; 8usize],
+    #[doc = "0x10 - Channel n Source Configuration Register"]
+    pub dma_ch_srccfg: [DMA_CH_SRCCFG; 32],
+    _reserved1: [u8; 112usize],
+    #[doc = "0x100 - Interrupt 1 Source Channel Configuration"]
+    pub dma_int1_srccfg: DMA_INT1_SRCCFG,
+    #[doc = "0x104 - Interrupt 2 Source Channel Configuration Register"]
+    pub dma_int2_srccfg: DMA_INT2_SRCCFG,
+    #[doc = "0x108 - Interrupt 3 Source Channel Configuration Register"]
+    pub dma_int3_srccfg: DMA_INT3_SRCCFG,
+    _reserved2: [u8; 4usize],
+    #[doc = "0x110 - Interrupt 0 Source Channel Flag Register"]
+    pub dma_int0_srcflg: DMA_INT0_SRCFLG,
+    #[doc = "0x114 - Interrupt 0 Source Channel Clear Flag Register"]
+    pub dma_int0_clrflg: DMA_INT0_CLRFLG,
+    _reserved3: [u8; 3816usize],
+    #[doc = "0x1000 - Status Register"]
+    pub dma_stat: DMA_STAT,
+    #[doc = "0x1004 - Configuration Register"]
+    pub dma_cfg: DMA_CFG,
+    #[doc = "0x1008 - Channel Control Data Base Pointer Register"]
+    pub dma_ctlbase: DMA_CTLBASE,
+    #[doc = "0x100c - Channel Alternate Control Data Base Pointer Register"]
+    pub dma_altbase: DMA_ALTBASE,
+    #[doc = "0x1010 - Channel Wait on Request Status Register"]
+    pub dma_waitstat: DMA_WAITSTAT,
+    #[doc = "0x1014 - Channel Software Request Register"]
+    pub dma_swreq: DMA_SWREQ,
+    #[doc = "0x1018 - Channel Useburst Set Register"]
+    pub dma_useburstset: DMA_USEBURSTSET,
+    #[doc = "0x101c - Channel Useburst Clear Register"]
+    pub dma_useburstclr: DMA_USEBURSTCLR,
+    #[doc = "0x1020 - Channel Request Mask Set Register"]
+    pub dma_reqmaskset: DMA_REQMASKSET,
+    #[doc = "0x1024 - Channel Request Mask Clear Register"]
+    pub dma_reqmaskclr: DMA_REQMASKCLR,
+    #[doc = "0x1028 - Channel Enable Set Register"]
+    pub dma_enaset: DMA_ENASET,
+    #[doc = "0x102c - Channel Enable Clear Register"]
+    pub dma_enaclr: DMA_ENACLR,
+    #[doc = "0x1030 - Channel Primary-Alternate Set Register"]
+    pub dma_altset: DMA_ALTSET,
+    #[doc = "0x1034 - Channel Primary-Alternate Clear Register"]
+    pub dma_altclr: DMA_ALTCLR,
+    #[doc = "0x1038 - Channel Priority Set Register"]
+    pub dma_prioset: DMA_PRIOSET,
+    #[doc = "0x103c - Channel Priority Clear Register"]
+    pub dma_prioclr: DMA_PRIOCLR,
+    _reserved4: [u8; 12usize],
+    #[doc = "0x104c - Bus Error Clear Register"]
+    pub dma_errclr: DMA_ERRCLR,
+}
+#[doc = "Device Configuration Status"]
+pub struct DMA_DEVICE_CFG {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Device Configuration Status"]
+pub mod dma_device_cfg;
+#[doc = "Software Channel Trigger Register"]
+pub struct DMA_SW_CHTRIG {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Software Channel Trigger Register"]
+pub mod dma_sw_chtrig;
+#[doc = "Channel n Source Configuration Register"]
+pub struct DMA_CH_SRCCFG {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Channel n Source Configuration Register"]
+pub mod dma_ch_srccfg;
+#[doc = "Interrupt 1 Source Channel Configuration"]
+pub struct DMA_INT1_SRCCFG {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Interrupt 1 Source Channel Configuration"]
+pub mod dma_int1_srccfg;
+#[doc = "Interrupt 2 Source Channel Configuration Register"]
+pub struct DMA_INT2_SRCCFG {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Interrupt 2 Source Channel Configuration Register"]
+pub mod dma_int2_srccfg;
+#[doc = "Interrupt 3 Source Channel Configuration Register"]
+pub struct DMA_INT3_SRCCFG {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Interrupt 3 Source Channel Configuration Register"]
+pub mod dma_int3_srccfg;
+#[doc = "Interrupt 0 Source Channel Flag Register"]
+pub struct DMA_INT0_SRCFLG {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Interrupt 0 Source Channel Flag Register"]
+pub mod dma_int0_srcflg;
+#[doc = "Interrupt 0 Source Channel Clear Flag Register"]
+pub struct DMA_INT0_CLRFLG {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Interrupt 0 Source Channel Clear Flag Register"]
+pub mod dma_int0_clrflg;
+#[doc = "Status Register"]
+pub struct DMA_STAT {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Status Register"]
+pub mod dma_stat;
+#[doc = "Configuration Register"]
+pub struct DMA_CFG {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Configuration Register"]
+pub mod dma_cfg;
+#[doc = "Channel Control Data Base Pointer Register"]
+pub struct DMA_CTLBASE {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Channel Control Data Base Pointer Register"]
+pub mod dma_ctlbase;
+#[doc = "Channel Alternate Control Data Base Pointer Register"]
+pub struct DMA_ALTBASE {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Channel Alternate Control Data Base Pointer Register"]
+pub mod dma_altbase;
+#[doc = "Channel Wait on Request Status Register"]
+pub struct DMA_WAITSTAT {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Channel Wait on Request Status Register"]
+pub mod dma_waitstat;
+#[doc = "Channel Software Request Register"]
+pub struct DMA_SWREQ {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Channel Software Request Register"]
+pub mod dma_swreq;
+#[doc = "Channel Useburst Set Register"]
+pub struct DMA_USEBURSTSET {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Channel Useburst Set Register"]
+pub mod dma_useburstset;
+#[doc = "Channel Useburst Clear Register"]
+pub struct DMA_USEBURSTCLR {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Channel Useburst Clear Register"]
+pub mod dma_useburstclr;
+#[doc = "Channel Request Mask Set Register"]
+pub struct DMA_REQMASKSET {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Channel Request Mask Set Register"]
+pub mod dma_reqmaskset;
+#[doc = "Channel Request Mask Clear Register"]
+pub struct DMA_REQMASKCLR {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Channel Request Mask Clear Register"]
+pub mod dma_reqmaskclr;
+#[doc = "Channel Enable Set Register"]
+pub struct DMA_ENASET {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Channel Enable Set Register"]
+pub mod dma_enaset;
+#[doc = "Channel Enable Clear Register"]
+pub struct DMA_ENACLR {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Channel Enable Clear Register"]
+pub mod dma_enaclr;
+#[doc = "Channel Primary-Alternate Set Register"]
+pub struct DMA_ALTSET {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Channel Primary-Alternate Set Register"]
+pub mod dma_altset;
+#[doc = "Channel Primary-Alternate Clear Register"]
+pub struct DMA_ALTCLR {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Channel Primary-Alternate Clear Register"]
+pub mod dma_altclr;
+#[doc = "Channel Priority Set Register"]
+pub struct DMA_PRIOSET {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Channel Priority Set Register"]
+pub mod dma_prioset;
+#[doc = "Channel Priority Clear Register"]
+pub struct DMA_PRIOCLR {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Channel Priority Clear Register"]
+pub mod dma_prioclr;
+#[doc = "Bus Error Clear Register"]
+pub struct DMA_ERRCLR {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Bus Error Clear Register"]
+pub mod dma_errclr;
diff --git a/example-source/msp432p401r/src/dma/dma_altbase.rs b/example-source/msp432p401r/src/dma/dma_altbase.rs
new file mode 100644
index 0000000..78a21ee
--- /dev/null
+++ b/example-source/msp432p401r/src/dma/dma_altbase.rs
@@ -0,0 +1,41 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::DMA_ALTBASE {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ADDRR {
+    bits: u32,
+}
+impl ADDRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Base address of the alternate data structure"]
+    #[inline]
+    pub fn addr(&self) -> ADDRR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        ADDRR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/dma/dma_altclr.rs b/example-source/msp432p401r/src/dma/dma_altclr.rs
new file mode 100644
index 0000000..703a557
--- /dev/null
+++ b/example-source/msp432p401r/src/dma/dma_altclr.rs
@@ -0,0 +1,82 @@
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::DMA_ALTCLR {
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+}
+#[doc = "Values that can be written to the field `CLR`"]
+pub enum CLRW {
+    #[doc = "No effect.\r\r\nUse the DMA_ALTSET Register to select the alternate data structure."]
+    CLR_0,
+    #[doc = "Selects the primary data structure for channel C.\r\r\nWriting to a bit where a DMA channel is not implemented has no effect."]
+    CLR_1,
+}
+impl CLRW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u32 {
+        match *self {
+            CLRW::CLR_0 => 0,
+            CLRW::CLR_1 => 1,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "No effect. Use the DMA_ALTSET Register to select the alternate data structure."]
+    #[inline]
+    pub fn clr_0(self) -> &'a mut W {
+        self.variant(CLRW::CLR_0)
+    }
+    #[doc = "Selects the primary data structure for channel C. Writing to a bit where a DMA channel is not implemented has no effect."]
+    #[inline]
+    pub fn clr_1(self) -> &'a mut W {
+        self.variant(CLRW::CLR_1)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Channel Primary-Alternate Clear Register"]
+    #[inline]
+    pub fn clr(&mut self) -> _CLRW {
+        _CLRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dma/dma_altset.rs b/example-source/msp432p401r/src/dma/dma_altset.rs
new file mode 100644
index 0000000..5ad0bad
--- /dev/null
+++ b/example-source/msp432p401r/src/dma/dma_altset.rs
@@ -0,0 +1,167 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::DMA_ALTSET {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `SET`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SETR {
+    #[doc = "DMA channel C is using the primary data structure."]
+    SET_0_READ,
+    #[doc = "DMA channel C is using the alternate data structure."]
+    SET_1_READ,
+    #[doc = r" Reserved"]
+    _Reserved(u32),
+}
+impl SETR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        match *self {
+            SETR::SET_0_READ => 0,
+            SETR::SET_1_READ => 1,
+            SETR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u32) -> SETR {
+        match value {
+            0 => SETR::SET_0_READ,
+            1 => SETR::SET_1_READ,
+            i => SETR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `SET_0_READ`"]
+    #[inline]
+    pub fn is_set_0_read(&self) -> bool {
+        *self == SETR::SET_0_READ
+    }
+    #[doc = "Checks if the value of the field is `SET_1_READ`"]
+    #[inline]
+    pub fn is_set_1_read(&self) -> bool {
+        *self == SETR::SET_1_READ
+    }
+}
+#[doc = "Values that can be written to the field `SET`"]
+pub enum SETW {
+    #[doc = "No effect.\r\r\nUse the DMA_ALTCLR Register to set bit \\[C\\] to 0."]
+    SEL_0_WRITE,
+    #[doc = "Selects the alternate data structure for channel C.\r\r\nWriting to a bit where a DMA channel is not implemented has no effect."]
+    SEL_1_WRITE,
+}
+impl SETW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u32 {
+        match *self {
+            SETW::SEL_0_WRITE => 0,
+            SETW::SEL_1_WRITE => 1,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SETW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SETW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SETW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "No effect. Use the DMA_ALTCLR Register to set bit \\[C\\] to 0."]
+    #[inline]
+    pub fn sel_0_write(self) -> &'a mut W {
+        self.variant(SETW::SEL_0_WRITE)
+    }
+    #[doc = "Selects the alternate data structure for channel C. Writing to a bit where a DMA channel is not implemented has no effect."]
+    #[inline]
+    pub fn sel_1_write(self) -> &'a mut W {
+        self.variant(SETW::SEL_1_WRITE)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Channel Primary-Alternate Set Register"]
+    #[inline]
+    pub fn set(&self) -> SETR {
+        SETR::_from({
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Channel Primary-Alternate Set Register"]
+    #[inline]
+    pub fn set(&mut self) -> _SETW {
+        _SETW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dma/dma_cfg.rs b/example-source/msp432p401r/src/dma/dma_cfg.rs
new file mode 100644
index 0000000..e5fdd15
--- /dev/null
+++ b/example-source/msp432p401r/src/dma/dma_cfg.rs
@@ -0,0 +1,112 @@
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::DMA_CFG {
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+}
+#[doc = "Values that can be written to the field `MASTEN`"]
+pub enum MASTENW {
+    #[doc = "Controller disabled"]
+    MASTEN_0,
+    #[doc = "Controller enabled"]
+    MASTEN_1,
+}
+impl MASTENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            MASTENW::MASTEN_0 => false,
+            MASTENW::MASTEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MASTENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MASTENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: MASTENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Controller disabled"]
+    #[inline]
+    pub fn masten_0(self) -> &'a mut W {
+        self.variant(MASTENW::MASTEN_0)
+    }
+    #[doc = "Controller enabled"]
+    #[inline]
+    pub fn masten_1(self) -> &'a mut W {
+        self.variant(MASTENW::MASTEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CHPROTCTRLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CHPROTCTRLW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Enable status of the controller"]
+    #[inline]
+    pub fn masten(&mut self) -> _MASTENW {
+        _MASTENW { w: self }
+    }
+    #[doc = "Bits 5:7 - Sets the AHB-Lite protection by controlling the HPROT\\[3:1\\] signal levels as follows: Bit \\[7\\] Controls HPROT\\[3\\] to indicate if a cacheable access is occurring. Bit \\[6\\] Controls HPROT\\[2\\] to indicate if a bufferable access is occurring. Bit \\[5\\] Controls HPROT\\[1\\] to indicate if a privileged access is occurring. Note: When bit \\[n\\] = 1 then the corresponding HPROT is HIGH. When bit \\[n\\] = 0 then the corresponding HPROT is LOW."]
+    #[inline]
+    pub fn chprotctrl(&mut self) -> _CHPROTCTRLW {
+        _CHPROTCTRLW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dma/dma_ch_srccfg.rs b/example-source/msp432p401r/src/dma/dma_ch_srccfg.rs
new file mode 100644
index 0000000..d894d34
--- /dev/null
+++ b/example-source/msp432p401r/src/dma/dma_ch_srccfg.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::DMA_CH_SRCCFG {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DMA_SRCR {
+    bits: u8,
+}
+impl DMA_SRCR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DMA_SRCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DMA_SRCW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Device level DMA source mapping to channel input"]
+    #[inline]
+    pub fn dma_src(&self) -> DMA_SRCR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        DMA_SRCR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Device level DMA source mapping to channel input"]
+    #[inline]
+    pub fn dma_src(&mut self) -> _DMA_SRCW {
+        _DMA_SRCW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dma/dma_ctlbase.rs b/example-source/msp432p401r/src/dma/dma_ctlbase.rs
new file mode 100644
index 0000000..4303fdc
--- /dev/null
+++ b/example-source/msp432p401r/src/dma/dma_ctlbase.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::DMA_CTLBASE {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ADDRR {
+    bits: u32,
+}
+impl ADDRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADDRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADDRW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 134217727;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 5:31 - Pointer to the base address of the primary data structure."]
+    #[inline]
+    pub fn addr(&self) -> ADDRR {
+        let bits = {
+            const MASK: u32 = 134217727;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        ADDRR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 5:31 - Pointer to the base address of the primary data structure."]
+    #[inline]
+    pub fn addr(&mut self) -> _ADDRW {
+        _ADDRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dma/dma_device_cfg.rs b/example-source/msp432p401r/src/dma/dma_device_cfg.rs
new file mode 100644
index 0000000..469977f
--- /dev/null
+++ b/example-source/msp432p401r/src/dma/dma_device_cfg.rs
@@ -0,0 +1,62 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::DMA_DEVICE_CFG {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct NUM_DMA_CHANNELSR {
+    bits: u8,
+}
+impl NUM_DMA_CHANNELSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct NUM_SRC_PER_CHANNELR {
+    bits: u8,
+}
+impl NUM_SRC_PER_CHANNELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Number of DMA channels available"]
+    #[inline]
+    pub fn num_dma_channels(&self) -> NUM_DMA_CHANNELSR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        NUM_DMA_CHANNELSR { bits }
+    }
+    #[doc = "Bits 8:15 - Number of DMA sources per channel"]
+    #[inline]
+    pub fn num_src_per_channel(&self) -> NUM_SRC_PER_CHANNELR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        NUM_SRC_PER_CHANNELR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/dma/dma_enaclr.rs b/example-source/msp432p401r/src/dma/dma_enaclr.rs
new file mode 100644
index 0000000..8bdf3f6
--- /dev/null
+++ b/example-source/msp432p401r/src/dma/dma_enaclr.rs
@@ -0,0 +1,82 @@
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::DMA_ENACLR {
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+}
+#[doc = "Values that can be written to the field `CLR`"]
+pub enum CLRW {
+    #[doc = "No effect.\r\r\nUse the DMA_ENASET Register to enable DMA channels."]
+    CLR_0,
+    #[doc = "Disables channel C.\r\r\nWriting to a bit where a DMA channel is not implemented has no effect."]
+    CLR_1,
+}
+impl CLRW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u32 {
+        match *self {
+            CLRW::CLR_0 => 0,
+            CLRW::CLR_1 => 1,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "No effect. Use the DMA_ENASET Register to enable DMA channels."]
+    #[inline]
+    pub fn clr_0(self) -> &'a mut W {
+        self.variant(CLRW::CLR_0)
+    }
+    #[doc = "Disables channel C. Writing to a bit where a DMA channel is not implemented has no effect."]
+    #[inline]
+    pub fn clr_1(self) -> &'a mut W {
+        self.variant(CLRW::CLR_1)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Set the appropriate bit to disable the corresponding DMA channel. Note: The controller disables a channel, by setting the appropriate bit, when: a) it completes the DMA cycle b) it reads a channel_cfg memory location which has cycle_ctrl = b000 c) an ERROR occurs on the AHB-Lite bus."]
+    #[inline]
+    pub fn clr(&mut self) -> _CLRW {
+        _CLRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dma/dma_enaset.rs b/example-source/msp432p401r/src/dma/dma_enaset.rs
new file mode 100644
index 0000000..062c44c
--- /dev/null
+++ b/example-source/msp432p401r/src/dma/dma_enaset.rs
@@ -0,0 +1,167 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::DMA_ENASET {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `SET`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SETR {
+    #[doc = "Channel C is disabled."]
+    SET_0_READ,
+    #[doc = "Channel C is enabled."]
+    SET_1_READ,
+    #[doc = r" Reserved"]
+    _Reserved(u32),
+}
+impl SETR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        match *self {
+            SETR::SET_0_READ => 0,
+            SETR::SET_1_READ => 1,
+            SETR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u32) -> SETR {
+        match value {
+            0 => SETR::SET_0_READ,
+            1 => SETR::SET_1_READ,
+            i => SETR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `SET_0_READ`"]
+    #[inline]
+    pub fn is_set_0_read(&self) -> bool {
+        *self == SETR::SET_0_READ
+    }
+    #[doc = "Checks if the value of the field is `SET_1_READ`"]
+    #[inline]
+    pub fn is_set_1_read(&self) -> bool {
+        *self == SETR::SET_1_READ
+    }
+}
+#[doc = "Values that can be written to the field `SET`"]
+pub enum SETW {
+    #[doc = "No effect.\r\r\nUse the DMA_ENACLR Register to disable a channel."]
+    SET_0_WRITE,
+    #[doc = "Enables channel C.\r\r\nWriting to a bit where a DMA channel is not implemented has no effect."]
+    SET_1_WRITE,
+}
+impl SETW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u32 {
+        match *self {
+            SETW::SET_0_WRITE => 0,
+            SETW::SET_1_WRITE => 1,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SETW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SETW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SETW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "No effect. Use the DMA_ENACLR Register to disable a channel."]
+    #[inline]
+    pub fn set_0_write(self) -> &'a mut W {
+        self.variant(SETW::SET_0_WRITE)
+    }
+    #[doc = "Enables channel C. Writing to a bit where a DMA channel is not implemented has no effect."]
+    #[inline]
+    pub fn set_1_write(self) -> &'a mut W {
+        self.variant(SETW::SET_1_WRITE)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Returns the enable status of the channels, or enables the corresponding channels."]
+    #[inline]
+    pub fn set(&self) -> SETR {
+        SETR::_from({
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Returns the enable status of the channels, or enables the corresponding channels."]
+    #[inline]
+    pub fn set(&mut self) -> _SETW {
+        _SETW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dma/dma_errclr.rs b/example-source/msp432p401r/src/dma/dma_errclr.rs
new file mode 100644
index 0000000..db74ec2
--- /dev/null
+++ b/example-source/msp432p401r/src/dma/dma_errclr.rs
@@ -0,0 +1,183 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::DMA_ERRCLR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `ERRCLR`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ERRCLRR {
+    #[doc = "dma_err is LOW"]
+    ERRCLR_0_READ,
+    #[doc = "dma_err is HIGH."]
+    ERRCLR_1_READ,
+}
+impl ERRCLRR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ERRCLRR::ERRCLR_0_READ => false,
+            ERRCLRR::ERRCLR_1_READ => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ERRCLRR {
+        match value {
+            false => ERRCLRR::ERRCLR_0_READ,
+            true => ERRCLRR::ERRCLR_1_READ,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ERRCLR_0_READ`"]
+    #[inline]
+    pub fn is_errclr_0_read(&self) -> bool {
+        *self == ERRCLRR::ERRCLR_0_READ
+    }
+    #[doc = "Checks if the value of the field is `ERRCLR_1_READ`"]
+    #[inline]
+    pub fn is_errclr_1_read(&self) -> bool {
+        *self == ERRCLRR::ERRCLR_1_READ
+    }
+}
+#[doc = "Values that can be written to the field `ERRCLR`"]
+pub enum ERRCLRW {
+    #[doc = "No effect, status of dma_err is unchanged."]
+    ERRCLR_0_WRITE,
+    #[doc = "Sets dma_err LOW."]
+    ERRCLR_1_WRITE,
+}
+impl ERRCLRW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ERRCLRW::ERRCLR_0_WRITE => false,
+            ERRCLRW::ERRCLR_1_WRITE => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ERRCLRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ERRCLRW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ERRCLRW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No effect, status of dma_err is unchanged."]
+    #[inline]
+    pub fn errclr_0_write(self) -> &'a mut W {
+        self.variant(ERRCLRW::ERRCLR_0_WRITE)
+    }
+    #[doc = "Sets dma_err LOW."]
+    #[inline]
+    pub fn errclr_1_write(self) -> &'a mut W {
+        self.variant(ERRCLRW::ERRCLR_1_WRITE)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Returns the status of dma_err, or sets the signal LOW. For test purposes, use the ERRSET register to set dma_err HIGH. Note: If you deassert dma_err at the same time as an ERROR occurs on the AHB-Lite bus, then the ERROR condition takes precedence and dma_err remains asserted."]
+    #[inline]
+    pub fn errclr(&self) -> ERRCLRR {
+        ERRCLRR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Returns the status of dma_err, or sets the signal LOW. For test purposes, use the ERRSET register to set dma_err HIGH. Note: If you deassert dma_err at the same time as an ERROR occurs on the AHB-Lite bus, then the ERROR condition takes precedence and dma_err remains asserted."]
+    #[inline]
+    pub fn errclr(&mut self) -> _ERRCLRW {
+        _ERRCLRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dma/dma_int0_clrflg.rs b/example-source/msp432p401r/src/dma/dma_int0_clrflg.rs
new file mode 100644
index 0000000..082bfc8
--- /dev/null
+++ b/example-source/msp432p401r/src/dma/dma_int0_clrflg.rs
@@ -0,0 +1,925 @@
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::DMA_INT0_CLRFLG {
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH0W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH1W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH2W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH3W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH4W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH4W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH5W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH5W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH6W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH6W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH7W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH7W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH8W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH8W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH9W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH9W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH10W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH10W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH11W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH11W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH12W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH12W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH13W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH13W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH14W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH14W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH15W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH15W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH16W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH16W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 16;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH17W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH17W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 17;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH18W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH18W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 18;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH19W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH19W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 19;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH20W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH20W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 20;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH21W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH21W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 21;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH22W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH22W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 22;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH23W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH23W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 23;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH24W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH24W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 24;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH25W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH25W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 25;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH26W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH26W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 26;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH27W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH27W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 27;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH28W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH28W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 28;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH29W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH29W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 29;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH30W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH30W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 30;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH31W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH31W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 31;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch0(&mut self) -> _CH0W {
+        _CH0W { w: self }
+    }
+    #[doc = "Bit 1 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch1(&mut self) -> _CH1W {
+        _CH1W { w: self }
+    }
+    #[doc = "Bit 2 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch2(&mut self) -> _CH2W {
+        _CH2W { w: self }
+    }
+    #[doc = "Bit 3 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch3(&mut self) -> _CH3W {
+        _CH3W { w: self }
+    }
+    #[doc = "Bit 4 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch4(&mut self) -> _CH4W {
+        _CH4W { w: self }
+    }
+    #[doc = "Bit 5 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch5(&mut self) -> _CH5W {
+        _CH5W { w: self }
+    }
+    #[doc = "Bit 6 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch6(&mut self) -> _CH6W {
+        _CH6W { w: self }
+    }
+    #[doc = "Bit 7 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch7(&mut self) -> _CH7W {
+        _CH7W { w: self }
+    }
+    #[doc = "Bit 8 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch8(&mut self) -> _CH8W {
+        _CH8W { w: self }
+    }
+    #[doc = "Bit 9 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch9(&mut self) -> _CH9W {
+        _CH9W { w: self }
+    }
+    #[doc = "Bit 10 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch10(&mut self) -> _CH10W {
+        _CH10W { w: self }
+    }
+    #[doc = "Bit 11 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch11(&mut self) -> _CH11W {
+        _CH11W { w: self }
+    }
+    #[doc = "Bit 12 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch12(&mut self) -> _CH12W {
+        _CH12W { w: self }
+    }
+    #[doc = "Bit 13 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch13(&mut self) -> _CH13W {
+        _CH13W { w: self }
+    }
+    #[doc = "Bit 14 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch14(&mut self) -> _CH14W {
+        _CH14W { w: self }
+    }
+    #[doc = "Bit 15 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch15(&mut self) -> _CH15W {
+        _CH15W { w: self }
+    }
+    #[doc = "Bit 16 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch16(&mut self) -> _CH16W {
+        _CH16W { w: self }
+    }
+    #[doc = "Bit 17 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch17(&mut self) -> _CH17W {
+        _CH17W { w: self }
+    }
+    #[doc = "Bit 18 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch18(&mut self) -> _CH18W {
+        _CH18W { w: self }
+    }
+    #[doc = "Bit 19 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch19(&mut self) -> _CH19W {
+        _CH19W { w: self }
+    }
+    #[doc = "Bit 20 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch20(&mut self) -> _CH20W {
+        _CH20W { w: self }
+    }
+    #[doc = "Bit 21 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch21(&mut self) -> _CH21W {
+        _CH21W { w: self }
+    }
+    #[doc = "Bit 22 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch22(&mut self) -> _CH22W {
+        _CH22W { w: self }
+    }
+    #[doc = "Bit 23 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch23(&mut self) -> _CH23W {
+        _CH23W { w: self }
+    }
+    #[doc = "Bit 24 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch24(&mut self) -> _CH24W {
+        _CH24W { w: self }
+    }
+    #[doc = "Bit 25 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch25(&mut self) -> _CH25W {
+        _CH25W { w: self }
+    }
+    #[doc = "Bit 26 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch26(&mut self) -> _CH26W {
+        _CH26W { w: self }
+    }
+    #[doc = "Bit 27 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch27(&mut self) -> _CH27W {
+        _CH27W { w: self }
+    }
+    #[doc = "Bit 28 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch28(&mut self) -> _CH28W {
+        _CH28W { w: self }
+    }
+    #[doc = "Bit 29 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch29(&mut self) -> _CH29W {
+        _CH29W { w: self }
+    }
+    #[doc = "Bit 30 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch30(&mut self) -> _CH30W {
+        _CH30W { w: self }
+    }
+    #[doc = "Bit 31 - Clear corresponding DMA_INT0_SRCFLG_REG"]
+    #[inline]
+    pub fn ch31(&mut self) -> _CH31W {
+        _CH31W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dma/dma_int0_srcflg.rs b/example-source/msp432p401r/src/dma/dma_int0_srcflg.rs
new file mode 100644
index 0000000..570235b
--- /dev/null
+++ b/example-source/msp432p401r/src/dma/dma_int0_srcflg.rs
@@ -0,0 +1,1012 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::DMA_INT0_SRCFLG {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH0R {
+    bits: bool,
+}
+impl CH0R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH1R {
+    bits: bool,
+}
+impl CH1R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH2R {
+    bits: bool,
+}
+impl CH2R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH3R {
+    bits: bool,
+}
+impl CH3R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH4R {
+    bits: bool,
+}
+impl CH4R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH5R {
+    bits: bool,
+}
+impl CH5R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH6R {
+    bits: bool,
+}
+impl CH6R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH7R {
+    bits: bool,
+}
+impl CH7R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH8R {
+    bits: bool,
+}
+impl CH8R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH9R {
+    bits: bool,
+}
+impl CH9R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH10R {
+    bits: bool,
+}
+impl CH10R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH11R {
+    bits: bool,
+}
+impl CH11R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH12R {
+    bits: bool,
+}
+impl CH12R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH13R {
+    bits: bool,
+}
+impl CH13R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH14R {
+    bits: bool,
+}
+impl CH14R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH15R {
+    bits: bool,
+}
+impl CH15R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH16R {
+    bits: bool,
+}
+impl CH16R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH17R {
+    bits: bool,
+}
+impl CH17R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH18R {
+    bits: bool,
+}
+impl CH18R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH19R {
+    bits: bool,
+}
+impl CH19R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH20R {
+    bits: bool,
+}
+impl CH20R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH21R {
+    bits: bool,
+}
+impl CH21R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH22R {
+    bits: bool,
+}
+impl CH22R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH23R {
+    bits: bool,
+}
+impl CH23R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH24R {
+    bits: bool,
+}
+impl CH24R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH25R {
+    bits: bool,
+}
+impl CH25R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH26R {
+    bits: bool,
+}
+impl CH26R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH27R {
+    bits: bool,
+}
+impl CH27R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH28R {
+    bits: bool,
+}
+impl CH28R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH29R {
+    bits: bool,
+}
+impl CH29R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH30R {
+    bits: bool,
+}
+impl CH30R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH31R {
+    bits: bool,
+}
+impl CH31R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Channel 0 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch0(&self) -> CH0R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH0R { bits }
+    }
+    #[doc = "Bit 1 - Channel 1 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch1(&self) -> CH1R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH1R { bits }
+    }
+    #[doc = "Bit 2 - Channel 2 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch2(&self) -> CH2R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH2R { bits }
+    }
+    #[doc = "Bit 3 - Channel 3 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch3(&self) -> CH3R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH3R { bits }
+    }
+    #[doc = "Bit 4 - Channel 4 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch4(&self) -> CH4R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH4R { bits }
+    }
+    #[doc = "Bit 5 - Channel 5 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch5(&self) -> CH5R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH5R { bits }
+    }
+    #[doc = "Bit 6 - Channel 6 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch6(&self) -> CH6R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH6R { bits }
+    }
+    #[doc = "Bit 7 - Channel 7 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch7(&self) -> CH7R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH7R { bits }
+    }
+    #[doc = "Bit 8 - Channel 8 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch8(&self) -> CH8R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH8R { bits }
+    }
+    #[doc = "Bit 9 - Channel 9 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch9(&self) -> CH9R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH9R { bits }
+    }
+    #[doc = "Bit 10 - Channel 10 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch10(&self) -> CH10R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH10R { bits }
+    }
+    #[doc = "Bit 11 - Channel 11 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch11(&self) -> CH11R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH11R { bits }
+    }
+    #[doc = "Bit 12 - Channel 12 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch12(&self) -> CH12R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH12R { bits }
+    }
+    #[doc = "Bit 13 - Channel 13 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch13(&self) -> CH13R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH13R { bits }
+    }
+    #[doc = "Bit 14 - Channel 14 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch14(&self) -> CH14R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH14R { bits }
+    }
+    #[doc = "Bit 15 - Channel 15 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch15(&self) -> CH15R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH15R { bits }
+    }
+    #[doc = "Bit 16 - Channel 16 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch16(&self) -> CH16R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH16R { bits }
+    }
+    #[doc = "Bit 17 - Channel 17 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch17(&self) -> CH17R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 17;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH17R { bits }
+    }
+    #[doc = "Bit 18 - Channel 18 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch18(&self) -> CH18R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 18;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH18R { bits }
+    }
+    #[doc = "Bit 19 - Channel 19 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch19(&self) -> CH19R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 19;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH19R { bits }
+    }
+    #[doc = "Bit 20 - Channel 20 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch20(&self) -> CH20R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 20;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH20R { bits }
+    }
+    #[doc = "Bit 21 - Channel 21 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch21(&self) -> CH21R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 21;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH21R { bits }
+    }
+    #[doc = "Bit 22 - Channel 22 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch22(&self) -> CH22R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 22;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH22R { bits }
+    }
+    #[doc = "Bit 23 - Channel 23 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch23(&self) -> CH23R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 23;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH23R { bits }
+    }
+    #[doc = "Bit 24 - Channel 24 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch24(&self) -> CH24R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 24;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH24R { bits }
+    }
+    #[doc = "Bit 25 - Channel 25 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch25(&self) -> CH25R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 25;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH25R { bits }
+    }
+    #[doc = "Bit 26 - Channel 26 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch26(&self) -> CH26R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 26;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH26R { bits }
+    }
+    #[doc = "Bit 27 - Channel 27 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch27(&self) -> CH27R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 27;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH27R { bits }
+    }
+    #[doc = "Bit 28 - Channel 28 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch28(&self) -> CH28R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 28;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH28R { bits }
+    }
+    #[doc = "Bit 29 - Channel 29 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch29(&self) -> CH29R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 29;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH29R { bits }
+    }
+    #[doc = "Bit 30 - Channel 30 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch30(&self) -> CH30R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 30;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH30R { bits }
+    }
+    #[doc = "Bit 31 - Channel 31 was the source of DMA_INT0"]
+    #[inline]
+    pub fn ch31(&self) -> CH31R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 31;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH31R { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/dma/dma_int1_srccfg.rs b/example-source/msp432p401r/src/dma/dma_int1_srccfg.rs
new file mode 100644
index 0000000..04c58fe
--- /dev/null
+++ b/example-source/msp432p401r/src/dma/dma_int1_srccfg.rs
@@ -0,0 +1,164 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::DMA_INT1_SRCCFG {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct INT_SRCR {
+    bits: u8,
+}
+impl INT_SRCR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ENR {
+    bits: bool,
+}
+impl ENR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Proxy"]
+pub struct _INT_SRCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _INT_SRCW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 31;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ENW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:4 - Controls which channel's completion event is mapped as a source of this Interrupt"]
+    #[inline]
+    pub fn int_src(&self) -> INT_SRCR {
+        let bits = {
+            const MASK: u8 = 31;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        INT_SRCR { bits }
+    }
+    #[doc = "Bit 5 - Enables DMA_INT1 mapping"]
+    #[inline]
+    pub fn en(&self) -> ENR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        ENR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:4 - Controls which channel's completion event is mapped as a source of this Interrupt"]
+    #[inline]
+    pub fn int_src(&mut self) -> _INT_SRCW {
+        _INT_SRCW { w: self }
+    }
+    #[doc = "Bit 5 - Enables DMA_INT1 mapping"]
+    #[inline]
+    pub fn en(&mut self) -> _ENW {
+        _ENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dma/dma_int2_srccfg.rs b/example-source/msp432p401r/src/dma/dma_int2_srccfg.rs
new file mode 100644
index 0000000..92246ae
--- /dev/null
+++ b/example-source/msp432p401r/src/dma/dma_int2_srccfg.rs
@@ -0,0 +1,164 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::DMA_INT2_SRCCFG {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct INT_SRCR {
+    bits: u8,
+}
+impl INT_SRCR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ENR {
+    bits: bool,
+}
+impl ENR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Proxy"]
+pub struct _INT_SRCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _INT_SRCW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 31;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ENW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:4 - Controls which channel's completion event is mapped as a source of this Interrupt"]
+    #[inline]
+    pub fn int_src(&self) -> INT_SRCR {
+        let bits = {
+            const MASK: u8 = 31;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        INT_SRCR { bits }
+    }
+    #[doc = "Bit 5 - Enables DMA_INT2 mapping"]
+    #[inline]
+    pub fn en(&self) -> ENR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        ENR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:4 - Controls which channel's completion event is mapped as a source of this Interrupt"]
+    #[inline]
+    pub fn int_src(&mut self) -> _INT_SRCW {
+        _INT_SRCW { w: self }
+    }
+    #[doc = "Bit 5 - Enables DMA_INT2 mapping"]
+    #[inline]
+    pub fn en(&mut self) -> _ENW {
+        _ENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dma/dma_int3_srccfg.rs b/example-source/msp432p401r/src/dma/dma_int3_srccfg.rs
new file mode 100644
index 0000000..8e06464
--- /dev/null
+++ b/example-source/msp432p401r/src/dma/dma_int3_srccfg.rs
@@ -0,0 +1,164 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::DMA_INT3_SRCCFG {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct INT_SRCR {
+    bits: u8,
+}
+impl INT_SRCR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ENR {
+    bits: bool,
+}
+impl ENR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Proxy"]
+pub struct _INT_SRCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _INT_SRCW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 31;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ENW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:4 - Controls which channel's completion event is mapped as a source of this Interrupt"]
+    #[inline]
+    pub fn int_src(&self) -> INT_SRCR {
+        let bits = {
+            const MASK: u8 = 31;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        INT_SRCR { bits }
+    }
+    #[doc = "Bit 5 - Enables DMA_INT3 mapping"]
+    #[inline]
+    pub fn en(&self) -> ENR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        ENR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:4 - Controls which channel's completion event is mapped as a source of this Interrupt"]
+    #[inline]
+    pub fn int_src(&mut self) -> _INT_SRCW {
+        _INT_SRCW { w: self }
+    }
+    #[doc = "Bit 5 - Enables DMA_INT3 mapping"]
+    #[inline]
+    pub fn en(&mut self) -> _ENW {
+        _ENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dma/dma_prioclr.rs b/example-source/msp432p401r/src/dma/dma_prioclr.rs
new file mode 100644
index 0000000..f373337
--- /dev/null
+++ b/example-source/msp432p401r/src/dma/dma_prioclr.rs
@@ -0,0 +1,82 @@
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::DMA_PRIOCLR {
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+}
+#[doc = "Values that can be written to the field `CLR`"]
+pub enum CLRW {
+    #[doc = "No effect.\r\r\nUse the DMA_PRIOSET Register to set channel C to the high priority level."]
+    CLR_0,
+    #[doc = "Channel C uses the default priority level.\r\r\nWriting to a bit where a DMA channel is not implemented has no effect."]
+    CLR_1,
+}
+impl CLRW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u32 {
+        match *self {
+            CLRW::CLR_0 => 0,
+            CLRW::CLR_1 => 1,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "No effect. Use the DMA_PRIOSET Register to set channel C to the high priority level."]
+    #[inline]
+    pub fn clr_0(self) -> &'a mut W {
+        self.variant(CLRW::CLR_0)
+    }
+    #[doc = "Channel C uses the default priority level. Writing to a bit where a DMA channel is not implemented has no effect."]
+    #[inline]
+    pub fn clr_1(self) -> &'a mut W {
+        self.variant(CLRW::CLR_1)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Set the appropriate bit to select the default priority level for the specified DMA channel."]
+    #[inline]
+    pub fn clr(&mut self) -> _CLRW {
+        _CLRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dma/dma_prioset.rs b/example-source/msp432p401r/src/dma/dma_prioset.rs
new file mode 100644
index 0000000..2586a68
--- /dev/null
+++ b/example-source/msp432p401r/src/dma/dma_prioset.rs
@@ -0,0 +1,167 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::DMA_PRIOSET {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `SET`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SETR {
+    #[doc = "DMA channel C is using the default priority level."]
+    SET_0_READ,
+    #[doc = "DMA channel C is using a high priority level."]
+    SET_1_READ,
+    #[doc = r" Reserved"]
+    _Reserved(u32),
+}
+impl SETR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        match *self {
+            SETR::SET_0_READ => 0,
+            SETR::SET_1_READ => 1,
+            SETR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u32) -> SETR {
+        match value {
+            0 => SETR::SET_0_READ,
+            1 => SETR::SET_1_READ,
+            i => SETR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `SET_0_READ`"]
+    #[inline]
+    pub fn is_set_0_read(&self) -> bool {
+        *self == SETR::SET_0_READ
+    }
+    #[doc = "Checks if the value of the field is `SET_1_READ`"]
+    #[inline]
+    pub fn is_set_1_read(&self) -> bool {
+        *self == SETR::SET_1_READ
+    }
+}
+#[doc = "Values that can be written to the field `SET`"]
+pub enum SETW {
+    #[doc = "No effect.\r\r\nUse the DMA_PRIOCLR Register to set channel C to the default priority level."]
+    SET_0_WRITE,
+    #[doc = "Channel C uses the high priority level.\r\r\nWriting to a bit where a DMA channel is not implemented has no effect."]
+    SET_1_WRITE,
+}
+impl SETW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u32 {
+        match *self {
+            SETW::SET_0_WRITE => 0,
+            SETW::SET_1_WRITE => 1,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SETW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SETW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SETW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "No effect. Use the DMA_PRIOCLR Register to set channel C to the default priority level."]
+    #[inline]
+    pub fn set_0_write(self) -> &'a mut W {
+        self.variant(SETW::SET_0_WRITE)
+    }
+    #[doc = "Channel C uses the high priority level. Writing to a bit where a DMA channel is not implemented has no effect."]
+    #[inline]
+    pub fn set_1_write(self) -> &'a mut W {
+        self.variant(SETW::SET_1_WRITE)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Returns the channel priority mask status, or sets the channel priority to high."]
+    #[inline]
+    pub fn set(&self) -> SETR {
+        SETR::_from({
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Returns the channel priority mask status, or sets the channel priority to high."]
+    #[inline]
+    pub fn set(&mut self) -> _SETW {
+        _SETW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dma/dma_reqmaskclr.rs b/example-source/msp432p401r/src/dma/dma_reqmaskclr.rs
new file mode 100644
index 0000000..3c82903
--- /dev/null
+++ b/example-source/msp432p401r/src/dma/dma_reqmaskclr.rs
@@ -0,0 +1,82 @@
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::DMA_REQMASKCLR {
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+}
+#[doc = "Values that can be written to the field `CLR`"]
+pub enum CLRW {
+    #[doc = "No effect.\r\r\nUse the DMA_REQMASKSET Register to disable dma_req and\r\r\ndma_sreq from generating requests."]
+    CLR_0,
+    #[doc = "Enables dma_req\\[C\\] or dma_sreq\\[C\\] to generate DMA requests.\r\r\nWriting to a bit where a DMA channel is not implemented has no effect."]
+    CLR_1,
+}
+impl CLRW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u32 {
+        match *self {
+            CLRW::CLR_0 => 0,
+            CLRW::CLR_1 => 1,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "No effect. Use the DMA_REQMASKSET Register to disable dma_req and dma_sreq from generating requests."]
+    #[inline]
+    pub fn clr_0(self) -> &'a mut W {
+        self.variant(CLRW::CLR_0)
+    }
+    #[doc = "Enables dma_req\\[C\\] or dma_sreq\\[C\\] to generate DMA requests. Writing to a bit where a DMA channel is not implemented has no effect."]
+    #[inline]
+    pub fn clr_1(self) -> &'a mut W {
+        self.variant(CLRW::CLR_1)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Set the appropriate bit to enable DMA requests for the channel corresponding to dma_req and dma_sreq."]
+    #[inline]
+    pub fn clr(&mut self) -> _CLRW {
+        _CLRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dma/dma_reqmaskset.rs b/example-source/msp432p401r/src/dma/dma_reqmaskset.rs
new file mode 100644
index 0000000..b16d5fb
--- /dev/null
+++ b/example-source/msp432p401r/src/dma/dma_reqmaskset.rs
@@ -0,0 +1,167 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::DMA_REQMASKSET {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `SET`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SETR {
+    #[doc = "External requests are enabled for channel C."]
+    SET_0_READ,
+    #[doc = "External requests are disabled for channel C."]
+    SET_1_READ,
+    #[doc = r" Reserved"]
+    _Reserved(u32),
+}
+impl SETR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        match *self {
+            SETR::SET_0_READ => 0,
+            SETR::SET_1_READ => 1,
+            SETR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u32) -> SETR {
+        match value {
+            0 => SETR::SET_0_READ,
+            1 => SETR::SET_1_READ,
+            i => SETR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `SET_0_READ`"]
+    #[inline]
+    pub fn is_set_0_read(&self) -> bool {
+        *self == SETR::SET_0_READ
+    }
+    #[doc = "Checks if the value of the field is `SET_1_READ`"]
+    #[inline]
+    pub fn is_set_1_read(&self) -> bool {
+        *self == SETR::SET_1_READ
+    }
+}
+#[doc = "Values that can be written to the field `SET`"]
+pub enum SETW {
+    #[doc = "No effect.\r\r\nUse the DMA_REQMASKCLR Register to enable DMA requests."]
+    SET_0_WRITE,
+    #[doc = "Disables dma_req\\[C\\] and dma_sreq\\[C\\] from generating DMA requests.\r\r\nWriting to a bit where a DMA channel is not implemented has no effect."]
+    SET_1_WRITE,
+}
+impl SETW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u32 {
+        match *self {
+            SETW::SET_0_WRITE => 0,
+            SETW::SET_1_WRITE => 1,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SETW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SETW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SETW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "No effect. Use the DMA_REQMASKCLR Register to enable DMA requests."]
+    #[inline]
+    pub fn set_0_write(self) -> &'a mut W {
+        self.variant(SETW::SET_0_WRITE)
+    }
+    #[doc = "Disables dma_req\\[C\\] and dma_sreq\\[C\\] from generating DMA requests. Writing to a bit where a DMA channel is not implemented has no effect."]
+    #[inline]
+    pub fn set_1_write(self) -> &'a mut W {
+        self.variant(SETW::SET_1_WRITE)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Returns the request mask status of dma_req and dma_sreq, or disables the corresponding channel from generating DMA requests."]
+    #[inline]
+    pub fn set(&self) -> SETR {
+        SETR::_from({
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Returns the request mask status of dma_req and dma_sreq, or disables the corresponding channel from generating DMA requests."]
+    #[inline]
+    pub fn set(&mut self) -> _SETW {
+        _SETW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dma/dma_stat.rs b/example-source/msp432p401r/src/dma/dma_stat.rs
new file mode 100644
index 0000000..ec1b452
--- /dev/null
+++ b/example-source/msp432p401r/src/dma/dma_stat.rs
@@ -0,0 +1,325 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::DMA_STAT {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `MASTEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum MASTENR {
+    #[doc = "Controller disabled"]
+    MASTEN_0,
+    #[doc = "Controller enabled"]
+    MASTEN_1,
+}
+impl MASTENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            MASTENR::MASTEN_0 => false,
+            MASTENR::MASTEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> MASTENR {
+        match value {
+            false => MASTENR::MASTEN_0,
+            true => MASTENR::MASTEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `MASTEN_0`"]
+    #[inline]
+    pub fn is_masten_0(&self) -> bool {
+        *self == MASTENR::MASTEN_0
+    }
+    #[doc = "Checks if the value of the field is `MASTEN_1`"]
+    #[inline]
+    pub fn is_masten_1(&self) -> bool {
+        *self == MASTENR::MASTEN_1
+    }
+}
+#[doc = "Possible values of the field `STATE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum STATER {
+    #[doc = "idle"]
+    STATE_0,
+    #[doc = "reading channel controller data"]
+    STATE_1,
+    #[doc = "reading source data end pointer"]
+    STATE_2,
+    #[doc = "reading destination data end pointer"]
+    STATE_3,
+    #[doc = "reading source data"]
+    STATE_4,
+    #[doc = "writing destination data"]
+    STATE_5,
+    #[doc = "waiting for DMA request to clear"]
+    STATE_6,
+    #[doc = "writing channel controller data"]
+    STATE_7,
+    #[doc = "stalled"]
+    STATE_8,
+    #[doc = "done"]
+    STATE_9,
+    #[doc = "peripheral scatter-gather transition"]
+    STATE_10,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl STATER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            STATER::STATE_0 => 0,
+            STATER::STATE_1 => 1,
+            STATER::STATE_2 => 2,
+            STATER::STATE_3 => 3,
+            STATER::STATE_4 => 4,
+            STATER::STATE_5 => 5,
+            STATER::STATE_6 => 6,
+            STATER::STATE_7 => 7,
+            STATER::STATE_8 => 8,
+            STATER::STATE_9 => 9,
+            STATER::STATE_10 => 10,
+            STATER::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> STATER {
+        match value {
+            0 => STATER::STATE_0,
+            1 => STATER::STATE_1,
+            2 => STATER::STATE_2,
+            3 => STATER::STATE_3,
+            4 => STATER::STATE_4,
+            5 => STATER::STATE_5,
+            6 => STATER::STATE_6,
+            7 => STATER::STATE_7,
+            8 => STATER::STATE_8,
+            9 => STATER::STATE_9,
+            10 => STATER::STATE_10,
+            i => STATER::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `STATE_0`"]
+    #[inline]
+    pub fn is_state_0(&self) -> bool {
+        *self == STATER::STATE_0
+    }
+    #[doc = "Checks if the value of the field is `STATE_1`"]
+    #[inline]
+    pub fn is_state_1(&self) -> bool {
+        *self == STATER::STATE_1
+    }
+    #[doc = "Checks if the value of the field is `STATE_2`"]
+    #[inline]
+    pub fn is_state_2(&self) -> bool {
+        *self == STATER::STATE_2
+    }
+    #[doc = "Checks if the value of the field is `STATE_3`"]
+    #[inline]
+    pub fn is_state_3(&self) -> bool {
+        *self == STATER::STATE_3
+    }
+    #[doc = "Checks if the value of the field is `STATE_4`"]
+    #[inline]
+    pub fn is_state_4(&self) -> bool {
+        *self == STATER::STATE_4
+    }
+    #[doc = "Checks if the value of the field is `STATE_5`"]
+    #[inline]
+    pub fn is_state_5(&self) -> bool {
+        *self == STATER::STATE_5
+    }
+    #[doc = "Checks if the value of the field is `STATE_6`"]
+    #[inline]
+    pub fn is_state_6(&self) -> bool {
+        *self == STATER::STATE_6
+    }
+    #[doc = "Checks if the value of the field is `STATE_7`"]
+    #[inline]
+    pub fn is_state_7(&self) -> bool {
+        *self == STATER::STATE_7
+    }
+    #[doc = "Checks if the value of the field is `STATE_8`"]
+    #[inline]
+    pub fn is_state_8(&self) -> bool {
+        *self == STATER::STATE_8
+    }
+    #[doc = "Checks if the value of the field is `STATE_9`"]
+    #[inline]
+    pub fn is_state_9(&self) -> bool {
+        *self == STATER::STATE_9
+    }
+    #[doc = "Checks if the value of the field is `STATE_10`"]
+    #[inline]
+    pub fn is_state_10(&self) -> bool {
+        *self == STATER::STATE_10
+    }
+}
+#[doc = "Possible values of the field `DMACHANS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DMACHANSR {
+    #[doc = "Controller configured to use 1 DMA channel"]
+    DMACHANS_0,
+    #[doc = "Controller configured to use 2 DMA channels"]
+    DMACHANS_1,
+    #[doc = "Controller configured to use 31 DMA channels"]
+    DMACHANS_30,
+    #[doc = "Controller configured to use 32 DMA channels"]
+    DMACHANS_31,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl DMACHANSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            DMACHANSR::DMACHANS_0 => 0,
+            DMACHANSR::DMACHANS_1 => 1,
+            DMACHANSR::DMACHANS_30 => 30,
+            DMACHANSR::DMACHANS_31 => 31,
+            DMACHANSR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> DMACHANSR {
+        match value {
+            0 => DMACHANSR::DMACHANS_0,
+            1 => DMACHANSR::DMACHANS_1,
+            30 => DMACHANSR::DMACHANS_30,
+            31 => DMACHANSR::DMACHANS_31,
+            i => DMACHANSR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `DMACHANS_0`"]
+    #[inline]
+    pub fn is_dmachans_0(&self) -> bool {
+        *self == DMACHANSR::DMACHANS_0
+    }
+    #[doc = "Checks if the value of the field is `DMACHANS_1`"]
+    #[inline]
+    pub fn is_dmachans_1(&self) -> bool {
+        *self == DMACHANSR::DMACHANS_1
+    }
+    #[doc = "Checks if the value of the field is `DMACHANS_30`"]
+    #[inline]
+    pub fn is_dmachans_30(&self) -> bool {
+        *self == DMACHANSR::DMACHANS_30
+    }
+    #[doc = "Checks if the value of the field is `DMACHANS_31`"]
+    #[inline]
+    pub fn is_dmachans_31(&self) -> bool {
+        *self == DMACHANSR::DMACHANS_31
+    }
+}
+#[doc = "Possible values of the field `TESTSTAT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TESTSTATR {
+    #[doc = "Controller does not include the integration test logic"]
+    TESTSTAT_0,
+    #[doc = "Controller includes the integration test logic"]
+    TESTSTAT_1,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl TESTSTATR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            TESTSTATR::TESTSTAT_0 => 0,
+            TESTSTATR::TESTSTAT_1 => 1,
+            TESTSTATR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> TESTSTATR {
+        match value {
+            0 => TESTSTATR::TESTSTAT_0,
+            1 => TESTSTATR::TESTSTAT_1,
+            i => TESTSTATR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `TESTSTAT_0`"]
+    #[inline]
+    pub fn is_teststat_0(&self) -> bool {
+        *self == TESTSTATR::TESTSTAT_0
+    }
+    #[doc = "Checks if the value of the field is `TESTSTAT_1`"]
+    #[inline]
+    pub fn is_teststat_1(&self) -> bool {
+        *self == TESTSTATR::TESTSTAT_1
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Enable status of the controller"]
+    #[inline]
+    pub fn masten(&self) -> MASTENR {
+        MASTENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 4:7 - Current state of the control state machine. State can be one of the following:"]
+    #[inline]
+    pub fn state(&self) -> STATER {
+        STATER::_from({
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 16:20 - Number of available DMA channels minus one."]
+    #[inline]
+    pub fn dmachans(&self) -> DMACHANSR {
+        DMACHANSR::_from({
+            const MASK: u8 = 31;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 28:31 - To reduce the gate count the controller can be configured to exclude the integration test logic. The values 2h to Fh are Reserved."]
+    #[inline]
+    pub fn teststat(&self) -> TESTSTATR {
+        TESTSTATR::_from({
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 28;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/dma/dma_sw_chtrig.rs b/example-source/msp432p401r/src/dma/dma_sw_chtrig.rs
new file mode 100644
index 0000000..8a335aa
--- /dev/null
+++ b/example-source/msp432p401r/src/dma/dma_sw_chtrig.rs
@@ -0,0 +1,1952 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::DMA_SW_CHTRIG {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH0R {
+    bits: bool,
+}
+impl CH0R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH1R {
+    bits: bool,
+}
+impl CH1R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH2R {
+    bits: bool,
+}
+impl CH2R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH3R {
+    bits: bool,
+}
+impl CH3R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH4R {
+    bits: bool,
+}
+impl CH4R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH5R {
+    bits: bool,
+}
+impl CH5R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH6R {
+    bits: bool,
+}
+impl CH6R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH7R {
+    bits: bool,
+}
+impl CH7R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH8R {
+    bits: bool,
+}
+impl CH8R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH9R {
+    bits: bool,
+}
+impl CH9R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH10R {
+    bits: bool,
+}
+impl CH10R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH11R {
+    bits: bool,
+}
+impl CH11R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH12R {
+    bits: bool,
+}
+impl CH12R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH13R {
+    bits: bool,
+}
+impl CH13R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH14R {
+    bits: bool,
+}
+impl CH14R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH15R {
+    bits: bool,
+}
+impl CH15R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH16R {
+    bits: bool,
+}
+impl CH16R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH17R {
+    bits: bool,
+}
+impl CH17R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH18R {
+    bits: bool,
+}
+impl CH18R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH19R {
+    bits: bool,
+}
+impl CH19R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH20R {
+    bits: bool,
+}
+impl CH20R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH21R {
+    bits: bool,
+}
+impl CH21R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH22R {
+    bits: bool,
+}
+impl CH22R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH23R {
+    bits: bool,
+}
+impl CH23R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH24R {
+    bits: bool,
+}
+impl CH24R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH25R {
+    bits: bool,
+}
+impl CH25R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH26R {
+    bits: bool,
+}
+impl CH26R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH27R {
+    bits: bool,
+}
+impl CH27R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH28R {
+    bits: bool,
+}
+impl CH28R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH29R {
+    bits: bool,
+}
+impl CH29R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH30R {
+    bits: bool,
+}
+impl CH30R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH31R {
+    bits: bool,
+}
+impl CH31R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH0W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH1W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH2W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH3W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH4W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH4W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH5W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH5W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH6W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH6W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH7W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH7W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH8W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH8W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH9W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH9W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH10W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH10W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH11W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH11W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH12W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH12W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH13W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH13W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH14W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH14W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH15W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH15W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH16W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH16W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 16;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH17W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH17W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 17;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH18W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH18W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 18;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH19W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH19W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 19;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH20W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH20W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 20;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH21W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH21W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 21;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH22W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH22W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 22;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH23W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH23W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 23;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH24W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH24W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 24;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH25W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH25W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 25;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH26W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH26W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 26;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH27W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH27W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 27;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH28W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH28W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 28;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH29W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH29W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 29;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH30W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH30W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 30;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH31W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH31W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 31;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Write 1, triggers DMA_CHANNEL0"]
+    #[inline]
+    pub fn ch0(&self) -> CH0R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH0R { bits }
+    }
+    #[doc = "Bit 1 - Write 1, triggers DMA_CHANNEL1"]
+    #[inline]
+    pub fn ch1(&self) -> CH1R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH1R { bits }
+    }
+    #[doc = "Bit 2 - Write 1, triggers DMA_CHANNEL2"]
+    #[inline]
+    pub fn ch2(&self) -> CH2R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH2R { bits }
+    }
+    #[doc = "Bit 3 - Write 1, triggers DMA_CHANNEL3"]
+    #[inline]
+    pub fn ch3(&self) -> CH3R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH3R { bits }
+    }
+    #[doc = "Bit 4 - Write 1, triggers DMA_CHANNEL4"]
+    #[inline]
+    pub fn ch4(&self) -> CH4R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH4R { bits }
+    }
+    #[doc = "Bit 5 - Write 1, triggers DMA_CHANNEL5"]
+    #[inline]
+    pub fn ch5(&self) -> CH5R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH5R { bits }
+    }
+    #[doc = "Bit 6 - Write 1, triggers DMA_CHANNEL6"]
+    #[inline]
+    pub fn ch6(&self) -> CH6R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH6R { bits }
+    }
+    #[doc = "Bit 7 - Write 1, triggers DMA_CHANNEL7"]
+    #[inline]
+    pub fn ch7(&self) -> CH7R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH7R { bits }
+    }
+    #[doc = "Bit 8 - Write 1, triggers DMA_CHANNEL8"]
+    #[inline]
+    pub fn ch8(&self) -> CH8R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH8R { bits }
+    }
+    #[doc = "Bit 9 - Write 1, triggers DMA_CHANNEL9"]
+    #[inline]
+    pub fn ch9(&self) -> CH9R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH9R { bits }
+    }
+    #[doc = "Bit 10 - Write 1, triggers DMA_CHANNEL10"]
+    #[inline]
+    pub fn ch10(&self) -> CH10R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH10R { bits }
+    }
+    #[doc = "Bit 11 - Write 1, triggers DMA_CHANNEL11"]
+    #[inline]
+    pub fn ch11(&self) -> CH11R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH11R { bits }
+    }
+    #[doc = "Bit 12 - Write 1, triggers DMA_CHANNEL12"]
+    #[inline]
+    pub fn ch12(&self) -> CH12R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH12R { bits }
+    }
+    #[doc = "Bit 13 - Write 1, triggers DMA_CHANNEL13"]
+    #[inline]
+    pub fn ch13(&self) -> CH13R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH13R { bits }
+    }
+    #[doc = "Bit 14 - Write 1, triggers DMA_CHANNEL14"]
+    #[inline]
+    pub fn ch14(&self) -> CH14R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH14R { bits }
+    }
+    #[doc = "Bit 15 - Write 1, triggers DMA_CHANNEL15"]
+    #[inline]
+    pub fn ch15(&self) -> CH15R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH15R { bits }
+    }
+    #[doc = "Bit 16 - Write 1, triggers DMA_CHANNEL16"]
+    #[inline]
+    pub fn ch16(&self) -> CH16R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH16R { bits }
+    }
+    #[doc = "Bit 17 - Write 1, triggers DMA_CHANNEL17"]
+    #[inline]
+    pub fn ch17(&self) -> CH17R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 17;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH17R { bits }
+    }
+    #[doc = "Bit 18 - Write 1, triggers DMA_CHANNEL18"]
+    #[inline]
+    pub fn ch18(&self) -> CH18R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 18;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH18R { bits }
+    }
+    #[doc = "Bit 19 - Write 1, triggers DMA_CHANNEL19"]
+    #[inline]
+    pub fn ch19(&self) -> CH19R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 19;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH19R { bits }
+    }
+    #[doc = "Bit 20 - Write 1, triggers DMA_CHANNEL20"]
+    #[inline]
+    pub fn ch20(&self) -> CH20R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 20;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH20R { bits }
+    }
+    #[doc = "Bit 21 - Write 1, triggers DMA_CHANNEL21"]
+    #[inline]
+    pub fn ch21(&self) -> CH21R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 21;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH21R { bits }
+    }
+    #[doc = "Bit 22 - Write 1, triggers DMA_CHANNEL22"]
+    #[inline]
+    pub fn ch22(&self) -> CH22R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 22;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH22R { bits }
+    }
+    #[doc = "Bit 23 - Write 1, triggers DMA_CHANNEL23"]
+    #[inline]
+    pub fn ch23(&self) -> CH23R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 23;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH23R { bits }
+    }
+    #[doc = "Bit 24 - Write 1, triggers DMA_CHANNEL24"]
+    #[inline]
+    pub fn ch24(&self) -> CH24R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 24;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH24R { bits }
+    }
+    #[doc = "Bit 25 - Write 1, triggers DMA_CHANNEL25"]
+    #[inline]
+    pub fn ch25(&self) -> CH25R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 25;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH25R { bits }
+    }
+    #[doc = "Bit 26 - Write 1, triggers DMA_CHANNEL26"]
+    #[inline]
+    pub fn ch26(&self) -> CH26R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 26;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH26R { bits }
+    }
+    #[doc = "Bit 27 - Write 1, triggers DMA_CHANNEL27"]
+    #[inline]
+    pub fn ch27(&self) -> CH27R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 27;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH27R { bits }
+    }
+    #[doc = "Bit 28 - Write 1, triggers DMA_CHANNEL28"]
+    #[inline]
+    pub fn ch28(&self) -> CH28R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 28;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH28R { bits }
+    }
+    #[doc = "Bit 29 - Write 1, triggers DMA_CHANNEL29"]
+    #[inline]
+    pub fn ch29(&self) -> CH29R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 29;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH29R { bits }
+    }
+    #[doc = "Bit 30 - Write 1, triggers DMA_CHANNEL30"]
+    #[inline]
+    pub fn ch30(&self) -> CH30R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 30;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH30R { bits }
+    }
+    #[doc = "Bit 31 - Write 1, triggers DMA_CHANNEL31"]
+    #[inline]
+    pub fn ch31(&self) -> CH31R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 31;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CH31R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Write 1, triggers DMA_CHANNEL0"]
+    #[inline]
+    pub fn ch0(&mut self) -> _CH0W {
+        _CH0W { w: self }
+    }
+    #[doc = "Bit 1 - Write 1, triggers DMA_CHANNEL1"]
+    #[inline]
+    pub fn ch1(&mut self) -> _CH1W {
+        _CH1W { w: self }
+    }
+    #[doc = "Bit 2 - Write 1, triggers DMA_CHANNEL2"]
+    #[inline]
+    pub fn ch2(&mut self) -> _CH2W {
+        _CH2W { w: self }
+    }
+    #[doc = "Bit 3 - Write 1, triggers DMA_CHANNEL3"]
+    #[inline]
+    pub fn ch3(&mut self) -> _CH3W {
+        _CH3W { w: self }
+    }
+    #[doc = "Bit 4 - Write 1, triggers DMA_CHANNEL4"]
+    #[inline]
+    pub fn ch4(&mut self) -> _CH4W {
+        _CH4W { w: self }
+    }
+    #[doc = "Bit 5 - Write 1, triggers DMA_CHANNEL5"]
+    #[inline]
+    pub fn ch5(&mut self) -> _CH5W {
+        _CH5W { w: self }
+    }
+    #[doc = "Bit 6 - Write 1, triggers DMA_CHANNEL6"]
+    #[inline]
+    pub fn ch6(&mut self) -> _CH6W {
+        _CH6W { w: self }
+    }
+    #[doc = "Bit 7 - Write 1, triggers DMA_CHANNEL7"]
+    #[inline]
+    pub fn ch7(&mut self) -> _CH7W {
+        _CH7W { w: self }
+    }
+    #[doc = "Bit 8 - Write 1, triggers DMA_CHANNEL8"]
+    #[inline]
+    pub fn ch8(&mut self) -> _CH8W {
+        _CH8W { w: self }
+    }
+    #[doc = "Bit 9 - Write 1, triggers DMA_CHANNEL9"]
+    #[inline]
+    pub fn ch9(&mut self) -> _CH9W {
+        _CH9W { w: self }
+    }
+    #[doc = "Bit 10 - Write 1, triggers DMA_CHANNEL10"]
+    #[inline]
+    pub fn ch10(&mut self) -> _CH10W {
+        _CH10W { w: self }
+    }
+    #[doc = "Bit 11 - Write 1, triggers DMA_CHANNEL11"]
+    #[inline]
+    pub fn ch11(&mut self) -> _CH11W {
+        _CH11W { w: self }
+    }
+    #[doc = "Bit 12 - Write 1, triggers DMA_CHANNEL12"]
+    #[inline]
+    pub fn ch12(&mut self) -> _CH12W {
+        _CH12W { w: self }
+    }
+    #[doc = "Bit 13 - Write 1, triggers DMA_CHANNEL13"]
+    #[inline]
+    pub fn ch13(&mut self) -> _CH13W {
+        _CH13W { w: self }
+    }
+    #[doc = "Bit 14 - Write 1, triggers DMA_CHANNEL14"]
+    #[inline]
+    pub fn ch14(&mut self) -> _CH14W {
+        _CH14W { w: self }
+    }
+    #[doc = "Bit 15 - Write 1, triggers DMA_CHANNEL15"]
+    #[inline]
+    pub fn ch15(&mut self) -> _CH15W {
+        _CH15W { w: self }
+    }
+    #[doc = "Bit 16 - Write 1, triggers DMA_CHANNEL16"]
+    #[inline]
+    pub fn ch16(&mut self) -> _CH16W {
+        _CH16W { w: self }
+    }
+    #[doc = "Bit 17 - Write 1, triggers DMA_CHANNEL17"]
+    #[inline]
+    pub fn ch17(&mut self) -> _CH17W {
+        _CH17W { w: self }
+    }
+    #[doc = "Bit 18 - Write 1, triggers DMA_CHANNEL18"]
+    #[inline]
+    pub fn ch18(&mut self) -> _CH18W {
+        _CH18W { w: self }
+    }
+    #[doc = "Bit 19 - Write 1, triggers DMA_CHANNEL19"]
+    #[inline]
+    pub fn ch19(&mut self) -> _CH19W {
+        _CH19W { w: self }
+    }
+    #[doc = "Bit 20 - Write 1, triggers DMA_CHANNEL20"]
+    #[inline]
+    pub fn ch20(&mut self) -> _CH20W {
+        _CH20W { w: self }
+    }
+    #[doc = "Bit 21 - Write 1, triggers DMA_CHANNEL21"]
+    #[inline]
+    pub fn ch21(&mut self) -> _CH21W {
+        _CH21W { w: self }
+    }
+    #[doc = "Bit 22 - Write 1, triggers DMA_CHANNEL22"]
+    #[inline]
+    pub fn ch22(&mut self) -> _CH22W {
+        _CH22W { w: self }
+    }
+    #[doc = "Bit 23 - Write 1, triggers DMA_CHANNEL23"]
+    #[inline]
+    pub fn ch23(&mut self) -> _CH23W {
+        _CH23W { w: self }
+    }
+    #[doc = "Bit 24 - Write 1, triggers DMA_CHANNEL24"]
+    #[inline]
+    pub fn ch24(&mut self) -> _CH24W {
+        _CH24W { w: self }
+    }
+    #[doc = "Bit 25 - Write 1, triggers DMA_CHANNEL25"]
+    #[inline]
+    pub fn ch25(&mut self) -> _CH25W {
+        _CH25W { w: self }
+    }
+    #[doc = "Bit 26 - Write 1, triggers DMA_CHANNEL26"]
+    #[inline]
+    pub fn ch26(&mut self) -> _CH26W {
+        _CH26W { w: self }
+    }
+    #[doc = "Bit 27 - Write 1, triggers DMA_CHANNEL27"]
+    #[inline]
+    pub fn ch27(&mut self) -> _CH27W {
+        _CH27W { w: self }
+    }
+    #[doc = "Bit 28 - Write 1, triggers DMA_CHANNEL28"]
+    #[inline]
+    pub fn ch28(&mut self) -> _CH28W {
+        _CH28W { w: self }
+    }
+    #[doc = "Bit 29 - Write 1, triggers DMA_CHANNEL29"]
+    #[inline]
+    pub fn ch29(&mut self) -> _CH29W {
+        _CH29W { w: self }
+    }
+    #[doc = "Bit 30 - Write 1, triggers DMA_CHANNEL30"]
+    #[inline]
+    pub fn ch30(&mut self) -> _CH30W {
+        _CH30W { w: self }
+    }
+    #[doc = "Bit 31 - Write 1, triggers DMA_CHANNEL31"]
+    #[inline]
+    pub fn ch31(&mut self) -> _CH31W {
+        _CH31W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dma/dma_swreq.rs b/example-source/msp432p401r/src/dma/dma_swreq.rs
new file mode 100644
index 0000000..cf30ec7
--- /dev/null
+++ b/example-source/msp432p401r/src/dma/dma_swreq.rs
@@ -0,0 +1,82 @@
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::DMA_SWREQ {
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+}
+#[doc = "Values that can be written to the field `CHNL_SW_REQ`"]
+pub enum CHNL_SW_REQW {
+    #[doc = "Does not create a DMA request for the channel"]
+    CHNL_SW_REQ_0,
+    #[doc = "Creates a DMA request for the channel"]
+    CHNL_SW_REQ_1,
+}
+impl CHNL_SW_REQW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u32 {
+        match *self {
+            CHNL_SW_REQW::CHNL_SW_REQ_0 => 0,
+            CHNL_SW_REQW::CHNL_SW_REQ_1 => 1,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CHNL_SW_REQW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CHNL_SW_REQW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CHNL_SW_REQW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "Does not create a DMA request for the channel"]
+    #[inline]
+    pub fn chnl_sw_req_0(self) -> &'a mut W {
+        self.variant(CHNL_SW_REQW::CHNL_SW_REQ_0)
+    }
+    #[doc = "Creates a DMA request for the channel"]
+    #[inline]
+    pub fn chnl_sw_req_1(self) -> &'a mut W {
+        self.variant(CHNL_SW_REQW::CHNL_SW_REQ_1)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Set the appropriate bit to generate a software DMA request on the corresponding DMA channel. Writing to a bit where a DMA channel is not implemented does not create a DMA request for that channel."]
+    #[inline]
+    pub fn chnl_sw_req(&mut self) -> _CHNL_SW_REQW {
+        _CHNL_SW_REQW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dma/dma_useburstclr.rs b/example-source/msp432p401r/src/dma/dma_useburstclr.rs
new file mode 100644
index 0000000..c1936e5
--- /dev/null
+++ b/example-source/msp432p401r/src/dma/dma_useburstclr.rs
@@ -0,0 +1,82 @@
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::DMA_USEBURSTCLR {
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+}
+#[doc = "Values that can be written to the field `CLR`"]
+pub enum CLRW {
+    #[doc = "No effect.\r\r\nUse the DMA_USEBURST_SET Register to disable dma_sreq from generating requests."]
+    CLR_0,
+    #[doc = "Enables dma_sreq\\[C\\] to generate DMA requests.\r\r\nWriting to a bit where a DMA channel is not implemented has no effect."]
+    CLR_1,
+}
+impl CLRW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u32 {
+        match *self {
+            CLRW::CLR_0 => 0,
+            CLRW::CLR_1 => 1,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "No effect. Use the DMA_USEBURST_SET Register to disable dma_sreq from generating requests."]
+    #[inline]
+    pub fn clr_0(self) -> &'a mut W {
+        self.variant(CLRW::CLR_0)
+    }
+    #[doc = "Enables dma_sreq\\[C\\] to generate DMA requests. Writing to a bit where a DMA channel is not implemented has no effect."]
+    #[inline]
+    pub fn clr_1(self) -> &'a mut W {
+        self.variant(CLRW::CLR_1)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Set the appropriate bit to enable dma_sreq to generate requests."]
+    #[inline]
+    pub fn clr(&mut self) -> _CLRW {
+        _CLRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dma/dma_useburstset.rs b/example-source/msp432p401r/src/dma/dma_useburstset.rs
new file mode 100644
index 0000000..1369645
--- /dev/null
+++ b/example-source/msp432p401r/src/dma/dma_useburstset.rs
@@ -0,0 +1,167 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::DMA_USEBURSTSET {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `SET`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SETR {
+    #[doc = "DMA channel C responds to requests that it receives on dma_req\\[C\\] or dma_sreq\\[C\\].\r\r\nThe controller performs 2R, or single, bus transfers."]
+    SET_0_READ,
+    #[doc = "DMA channel C does not respond to requests that it receives on dma_sreq\\[C\\].\r\r\nThe controller only responds to dma_req\\[C\\] requests and performs 2R transfers."]
+    SET_1_READ,
+    #[doc = r" Reserved"]
+    _Reserved(u32),
+}
+impl SETR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        match *self {
+            SETR::SET_0_READ => 0,
+            SETR::SET_1_READ => 1,
+            SETR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u32) -> SETR {
+        match value {
+            0 => SETR::SET_0_READ,
+            1 => SETR::SET_1_READ,
+            i => SETR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `SET_0_READ`"]
+    #[inline]
+    pub fn is_set_0_read(&self) -> bool {
+        *self == SETR::SET_0_READ
+    }
+    #[doc = "Checks if the value of the field is `SET_1_READ`"]
+    #[inline]
+    pub fn is_set_1_read(&self) -> bool {
+        *self == SETR::SET_1_READ
+    }
+}
+#[doc = "Values that can be written to the field `SET`"]
+pub enum SETW {
+    #[doc = "No effect. Use the DMA_USEBURST_CLR Register to set bit \\[C\\] to 0."]
+    SET_0_WRITE,
+    #[doc = "Disables dma_sreq\\[C\\] from generating DMA requests.\r\r\nThe controller performs 2R transfers.\r\r\nWriting to a bit where a DMA channel is not implemented has no effect."]
+    SET_1_WRITE,
+}
+impl SETW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u32 {
+        match *self {
+            SETW::SET_0_WRITE => 0,
+            SETW::SET_1_WRITE => 1,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SETW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SETW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SETW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "No effect. Use the DMA_USEBURST_CLR Register to set bit \\[C\\] to 0."]
+    #[inline]
+    pub fn set_0_write(self) -> &'a mut W {
+        self.variant(SETW::SET_0_WRITE)
+    }
+    #[doc = "Disables dma_sreq\\[C\\] from generating DMA requests. The controller performs 2R transfers. Writing to a bit where a DMA channel is not implemented has no effect."]
+    #[inline]
+    pub fn set_1_write(self) -> &'a mut W {
+        self.variant(SETW::SET_1_WRITE)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Returns the useburst status, or disables dma_sreq from generating DMA requests."]
+    #[inline]
+    pub fn set(&self) -> SETR {
+        SETR::_from({
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Returns the useburst status, or disables dma_sreq from generating DMA requests."]
+    #[inline]
+    pub fn set(&mut self) -> _SETW {
+        _SETW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/dma/dma_waitstat.rs b/example-source/msp432p401r/src/dma/dma_waitstat.rs
new file mode 100644
index 0000000..6c26e6c
--- /dev/null
+++ b/example-source/msp432p401r/src/dma/dma_waitstat.rs
@@ -0,0 +1,70 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::DMA_WAITSTAT {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `WAITREQ`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WAITREQR {
+    #[doc = "dma_waitonreq\\[C\\] is LOW."]
+    WAITREQ_0,
+    #[doc = "dma_waitonreq\\[C\\] is HIGH."]
+    WAITREQ_1,
+    #[doc = r" Reserved"]
+    _Reserved(u32),
+}
+impl WAITREQR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        match *self {
+            WAITREQR::WAITREQ_0 => 0,
+            WAITREQR::WAITREQ_1 => 1,
+            WAITREQR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u32) -> WAITREQR {
+        match value {
+            0 => WAITREQR::WAITREQ_0,
+            1 => WAITREQR::WAITREQ_1,
+            i => WAITREQR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `WAITREQ_0`"]
+    #[inline]
+    pub fn is_waitreq_0(&self) -> bool {
+        *self == WAITREQR::WAITREQ_0
+    }
+    #[doc = "Checks if the value of the field is `WAITREQ_1`"]
+    #[inline]
+    pub fn is_waitreq_1(&self) -> bool {
+        *self == WAITREQR::WAITREQ_1
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Channel wait on request status."]
+    #[inline]
+    pub fn waitreq(&self) -> WAITREQR {
+        WAITREQR::_from({
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a0.rs b/example-source/msp432p401r/src/eusci_a0.rs
new file mode 100644
index 0000000..88b0e5e
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a0.rs
@@ -0,0 +1,102 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - eUSCI_Ax Control Word Register 0"]
+    pub ucax_ctlw0: UCAXCTLW0,
+    #[doc = "0x02 - eUSCI_Ax Control Word Register 1"]
+    pub ucax_ctlw1: UCAXCTLW1,
+    _reserved0: [u8; 2usize],
+    #[doc = "0x06 - eUSCI_Ax Baud Rate Control Word Register"]
+    pub ucax_brw: UCAXBRW,
+    #[doc = "0x08 - eUSCI_Ax Modulation Control Word Register"]
+    pub ucax_mctlw: UCAXMCTLW,
+    #[doc = "0x0a - eUSCI_Ax Status Register"]
+    pub ucax_statw: UCAXSTATW,
+    #[doc = "0x0c - eUSCI_Ax Receive Buffer Register"]
+    pub ucax_rxbuf: UCAXRXBUF,
+    #[doc = "0x0e - eUSCI_Ax Transmit Buffer Register"]
+    pub ucax_txbuf: UCAXTXBUF,
+    #[doc = "0x10 - eUSCI_Ax Auto Baud Rate Control Register"]
+    pub ucax_abctl: UCAXABCTL,
+    #[doc = "0x12 - eUSCI_Ax IrDA Control Word Register"]
+    pub ucax_irctl: UCAXIRCTL,
+    _reserved1: [u8; 6usize],
+    #[doc = "0x1a - eUSCI_Ax Interrupt Enable Register"]
+    pub ucax_ie: UCAXIE,
+    #[doc = "0x1c - eUSCI_Ax Interrupt Flag Register"]
+    pub ucax_ifg: UCAXIFG,
+    #[doc = "0x1e - eUSCI_Ax Interrupt Vector Register"]
+    pub ucax_iv: UCAXIV,
+}
+#[doc = "eUSCI_Ax Control Word Register 0"]
+pub struct UCAXCTLW0 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Control Word Register 0"]
+pub mod ucax_ctlw0;
+#[doc = "eUSCI_Ax Control Word Register 1"]
+pub struct UCAXCTLW1 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Control Word Register 1"]
+pub mod ucax_ctlw1;
+#[doc = "eUSCI_Ax Baud Rate Control Word Register"]
+pub struct UCAXBRW {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Baud Rate Control Word Register"]
+pub mod ucax_brw;
+#[doc = "eUSCI_Ax Modulation Control Word Register"]
+pub struct UCAXMCTLW {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Modulation Control Word Register"]
+pub mod ucax_mctlw;
+#[doc = "eUSCI_Ax Status Register"]
+pub struct UCAXSTATW {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Status Register"]
+pub mod ucax_statw;
+#[doc = "eUSCI_Ax Receive Buffer Register"]
+pub struct UCAXRXBUF {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Receive Buffer Register"]
+pub mod ucax_rxbuf;
+#[doc = "eUSCI_Ax Transmit Buffer Register"]
+pub struct UCAXTXBUF {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Transmit Buffer Register"]
+pub mod ucax_txbuf;
+#[doc = "eUSCI_Ax Auto Baud Rate Control Register"]
+pub struct UCAXABCTL {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Auto Baud Rate Control Register"]
+pub mod ucax_abctl;
+#[doc = "eUSCI_Ax IrDA Control Word Register"]
+pub struct UCAXIRCTL {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax IrDA Control Word Register"]
+pub mod ucax_irctl;
+#[doc = "eUSCI_Ax Interrupt Enable Register"]
+pub struct UCAXIE {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Interrupt Enable Register"]
+pub mod ucax_ie;
+#[doc = "eUSCI_Ax Interrupt Flag Register"]
+pub struct UCAXIFG {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Interrupt Flag Register"]
+pub mod ucax_ifg;
+#[doc = "eUSCI_Ax Interrupt Vector Register"]
+pub struct UCAXIV {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Interrupt Vector Register"]
+pub mod ucax_iv;
diff --git a/example-source/msp432p401r/src/eusci_a0/ucax_abctl.rs b/example-source/msp432p401r/src/eusci_a0/ucax_abctl.rs
new file mode 100644
index 0000000..ce574eb
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a0/ucax_abctl.rs
@@ -0,0 +1,557 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXABCTL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCABDEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCABDENR {
+    #[doc = "Baud-rate detection disabled. Length of break and synch field is not measured."]
+    UCABDEN_0,
+    #[doc = "Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly."]
+    UCABDEN_1,
+}
+impl UCABDENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCABDENR::UCABDEN_0 => false,
+            UCABDENR::UCABDEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCABDENR {
+        match value {
+            false => UCABDENR::UCABDEN_0,
+            true => UCABDENR::UCABDEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCABDEN_0`"]
+    #[inline]
+    pub fn is_ucabden_0(&self) -> bool {
+        *self == UCABDENR::UCABDEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCABDEN_1`"]
+    #[inline]
+    pub fn is_ucabden_1(&self) -> bool {
+        *self == UCABDENR::UCABDEN_1
+    }
+}
+#[doc = "Possible values of the field `UCBTOE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBTOER {
+    #[doc = "No error"]
+    UCBTOE_0,
+    #[doc = "Length of break field exceeded 22 bit times"]
+    UCBTOE_1,
+}
+impl UCBTOER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBTOER::UCBTOE_0 => false,
+            UCBTOER::UCBTOE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBTOER {
+        match value {
+            false => UCBTOER::UCBTOE_0,
+            true => UCBTOER::UCBTOE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBTOE_0`"]
+    #[inline]
+    pub fn is_ucbtoe_0(&self) -> bool {
+        *self == UCBTOER::UCBTOE_0
+    }
+    #[doc = "Checks if the value of the field is `UCBTOE_1`"]
+    #[inline]
+    pub fn is_ucbtoe_1(&self) -> bool {
+        *self == UCBTOER::UCBTOE_1
+    }
+}
+#[doc = "Possible values of the field `UCSTOE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTOER {
+    #[doc = "No error"]
+    UCSTOE_0,
+    #[doc = "Length of synch field exceeded measurable time"]
+    UCSTOE_1,
+}
+impl UCSTOER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTOER::UCSTOE_0 => false,
+            UCSTOER::UCSTOE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTOER {
+        match value {
+            false => UCSTOER::UCSTOE_0,
+            true => UCSTOER::UCSTOE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTOE_0`"]
+    #[inline]
+    pub fn is_ucstoe_0(&self) -> bool {
+        *self == UCSTOER::UCSTOE_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTOE_1`"]
+    #[inline]
+    pub fn is_ucstoe_1(&self) -> bool {
+        *self == UCSTOER::UCSTOE_1
+    }
+}
+#[doc = "Possible values of the field `UCDELIM`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCDELIMR {
+    #[doc = "1 bit time"]
+    UCDELIM_0,
+    #[doc = "2 bit times"]
+    UCDELIM_1,
+    #[doc = "3 bit times"]
+    UCDELIM_2,
+    #[doc = "4 bit times"]
+    UCDELIM_3,
+}
+impl UCDELIMR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCDELIMR::UCDELIM_0 => 0,
+            UCDELIMR::UCDELIM_1 => 1,
+            UCDELIMR::UCDELIM_2 => 2,
+            UCDELIMR::UCDELIM_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCDELIMR {
+        match value {
+            0 => UCDELIMR::UCDELIM_0,
+            1 => UCDELIMR::UCDELIM_1,
+            2 => UCDELIMR::UCDELIM_2,
+            3 => UCDELIMR::UCDELIM_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCDELIM_0`"]
+    #[inline]
+    pub fn is_ucdelim_0(&self) -> bool {
+        *self == UCDELIMR::UCDELIM_0
+    }
+    #[doc = "Checks if the value of the field is `UCDELIM_1`"]
+    #[inline]
+    pub fn is_ucdelim_1(&self) -> bool {
+        *self == UCDELIMR::UCDELIM_1
+    }
+    #[doc = "Checks if the value of the field is `UCDELIM_2`"]
+    #[inline]
+    pub fn is_ucdelim_2(&self) -> bool {
+        *self == UCDELIMR::UCDELIM_2
+    }
+    #[doc = "Checks if the value of the field is `UCDELIM_3`"]
+    #[inline]
+    pub fn is_ucdelim_3(&self) -> bool {
+        *self == UCDELIMR::UCDELIM_3
+    }
+}
+#[doc = "Values that can be written to the field `UCABDEN`"]
+pub enum UCABDENW {
+    #[doc = "Baud-rate detection disabled. Length of break and synch field is not measured."]
+    UCABDEN_0,
+    #[doc = "Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly."]
+    UCABDEN_1,
+}
+impl UCABDENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCABDENW::UCABDEN_0 => false,
+            UCABDENW::UCABDEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCABDENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCABDENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCABDENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Baud-rate detection disabled. Length of break and synch field is not measured."]
+    #[inline]
+    pub fn ucabden_0(self) -> &'a mut W {
+        self.variant(UCABDENW::UCABDEN_0)
+    }
+    #[doc = "Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly."]
+    #[inline]
+    pub fn ucabden_1(self) -> &'a mut W {
+        self.variant(UCABDENW::UCABDEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCBTOE`"]
+pub enum UCBTOEW {
+    #[doc = "No error"]
+    UCBTOE_0,
+    #[doc = "Length of break field exceeded 22 bit times"]
+    UCBTOE_1,
+}
+impl UCBTOEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCBTOEW::UCBTOE_0 => false,
+            UCBTOEW::UCBTOE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBTOEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBTOEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCBTOEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No error"]
+    #[inline]
+    pub fn ucbtoe_0(self) -> &'a mut W {
+        self.variant(UCBTOEW::UCBTOE_0)
+    }
+    #[doc = "Length of break field exceeded 22 bit times"]
+    #[inline]
+    pub fn ucbtoe_1(self) -> &'a mut W {
+        self.variant(UCBTOEW::UCBTOE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTOE`"]
+pub enum UCSTOEW {
+    #[doc = "No error"]
+    UCSTOE_0,
+    #[doc = "Length of synch field exceeded measurable time"]
+    UCSTOE_1,
+}
+impl UCSTOEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTOEW::UCSTOE_0 => false,
+            UCSTOEW::UCSTOE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTOEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTOEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTOEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No error"]
+    #[inline]
+    pub fn ucstoe_0(self) -> &'a mut W {
+        self.variant(UCSTOEW::UCSTOE_0)
+    }
+    #[doc = "Length of synch field exceeded measurable time"]
+    #[inline]
+    pub fn ucstoe_1(self) -> &'a mut W {
+        self.variant(UCSTOEW::UCSTOE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCDELIM`"]
+pub enum UCDELIMW {
+    #[doc = "1 bit time"]
+    UCDELIM_0,
+    #[doc = "2 bit times"]
+    UCDELIM_1,
+    #[doc = "3 bit times"]
+    UCDELIM_2,
+    #[doc = "4 bit times"]
+    UCDELIM_3,
+}
+impl UCDELIMW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCDELIMW::UCDELIM_0 => 0,
+            UCDELIMW::UCDELIM_1 => 1,
+            UCDELIMW::UCDELIM_2 => 2,
+            UCDELIMW::UCDELIM_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCDELIMW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCDELIMW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCDELIMW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "1 bit time"]
+    #[inline]
+    pub fn ucdelim_0(self) -> &'a mut W {
+        self.variant(UCDELIMW::UCDELIM_0)
+    }
+    #[doc = "2 bit times"]
+    #[inline]
+    pub fn ucdelim_1(self) -> &'a mut W {
+        self.variant(UCDELIMW::UCDELIM_1)
+    }
+    #[doc = "3 bit times"]
+    #[inline]
+    pub fn ucdelim_2(self) -> &'a mut W {
+        self.variant(UCDELIMW::UCDELIM_2)
+    }
+    #[doc = "4 bit times"]
+    #[inline]
+    pub fn ucdelim_3(self) -> &'a mut W {
+        self.variant(UCDELIMW::UCDELIM_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Automatic baud-rate detect enable"]
+    #[inline]
+    pub fn ucabden(&self) -> UCABDENR {
+        UCABDENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - Break time out error"]
+    #[inline]
+    pub fn ucbtoe(&self) -> UCBTOER {
+        UCBTOER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Synch field time out error"]
+    #[inline]
+    pub fn ucstoe(&self) -> UCSTOER {
+        UCSTOER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 4:5 - Break/synch delimiter length"]
+    #[inline]
+    pub fn ucdelim(&self) -> UCDELIMR {
+        UCDELIMR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Automatic baud-rate detect enable"]
+    #[inline]
+    pub fn ucabden(&mut self) -> _UCABDENW {
+        _UCABDENW { w: self }
+    }
+    #[doc = "Bit 2 - Break time out error"]
+    #[inline]
+    pub fn ucbtoe(&mut self) -> _UCBTOEW {
+        _UCBTOEW { w: self }
+    }
+    #[doc = "Bit 3 - Synch field time out error"]
+    #[inline]
+    pub fn ucstoe(&mut self) -> _UCSTOEW {
+        _UCSTOEW { w: self }
+    }
+    #[doc = "Bits 4:5 - Break/synch delimiter length"]
+    #[inline]
+    pub fn ucdelim(&mut self) -> _UCDELIMW {
+        _UCDELIMW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a0/ucax_brw.rs b/example-source/msp432p401r/src/eusci_a0/ucax_brw.rs
new file mode 100644
index 0000000..c9b1b2a
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a0/ucax_brw.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXBRW {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCBRR {
+    bits: u16,
+}
+impl UCBRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBRW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Clock prescaler setting of the Baud rate generator"]
+    #[inline]
+    pub fn ucbr(&self) -> UCBRR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        UCBRR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Clock prescaler setting of the Baud rate generator"]
+    #[inline]
+    pub fn ucbr(&mut self) -> _UCBRW {
+        _UCBRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a0/ucax_ctlw0.rs b/example-source/msp432p401r/src/eusci_a0/ucax_ctlw0.rs
new file mode 100644
index 0000000..aa44348
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a0/ucax_ctlw0.rs
@@ -0,0 +1,1748 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXCTLW0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCSWRST`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSWRSTR {
+    #[doc = "Disabled. eUSCI_A reset released for operation"]
+    UCSWRST_0,
+    #[doc = "Enabled. eUSCI_A logic held in reset state"]
+    UCSWRST_1,
+}
+impl UCSWRSTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSWRSTR::UCSWRST_0 => false,
+            UCSWRSTR::UCSWRST_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSWRSTR {
+        match value {
+            false => UCSWRSTR::UCSWRST_0,
+            true => UCSWRSTR::UCSWRST_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSWRST_0`"]
+    #[inline]
+    pub fn is_ucswrst_0(&self) -> bool {
+        *self == UCSWRSTR::UCSWRST_0
+    }
+    #[doc = "Checks if the value of the field is `UCSWRST_1`"]
+    #[inline]
+    pub fn is_ucswrst_1(&self) -> bool {
+        *self == UCSWRSTR::UCSWRST_1
+    }
+}
+#[doc = "Possible values of the field `UCTXBRK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXBRKR {
+    #[doc = "Next frame transmitted is not a break"]
+    UCTXBRK_0,
+    #[doc = "Next frame transmitted is a break or a break/synch"]
+    UCTXBRK_1,
+}
+impl UCTXBRKR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXBRKR::UCTXBRK_0 => false,
+            UCTXBRKR::UCTXBRK_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXBRKR {
+        match value {
+            false => UCTXBRKR::UCTXBRK_0,
+            true => UCTXBRKR::UCTXBRK_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXBRK_0`"]
+    #[inline]
+    pub fn is_uctxbrk_0(&self) -> bool {
+        *self == UCTXBRKR::UCTXBRK_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXBRK_1`"]
+    #[inline]
+    pub fn is_uctxbrk_1(&self) -> bool {
+        *self == UCTXBRKR::UCTXBRK_1
+    }
+}
+#[doc = "Possible values of the field `UCTXADDR`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXADDRR {
+    #[doc = "Next frame transmitted is data"]
+    UCTXADDR_0,
+    #[doc = "Next frame transmitted is an address"]
+    UCTXADDR_1,
+}
+impl UCTXADDRR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXADDRR::UCTXADDR_0 => false,
+            UCTXADDRR::UCTXADDR_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXADDRR {
+        match value {
+            false => UCTXADDRR::UCTXADDR_0,
+            true => UCTXADDRR::UCTXADDR_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXADDR_0`"]
+    #[inline]
+    pub fn is_uctxaddr_0(&self) -> bool {
+        *self == UCTXADDRR::UCTXADDR_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXADDR_1`"]
+    #[inline]
+    pub fn is_uctxaddr_1(&self) -> bool {
+        *self == UCTXADDRR::UCTXADDR_1
+    }
+}
+#[doc = "Possible values of the field `UCDORM`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCDORMR {
+    #[doc = "Not dormant. All received characters set UCRXIFG."]
+    UCDORM_0,
+    #[doc = "Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG."]
+    UCDORM_1,
+}
+impl UCDORMR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCDORMR::UCDORM_0 => false,
+            UCDORMR::UCDORM_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCDORMR {
+        match value {
+            false => UCDORMR::UCDORM_0,
+            true => UCDORMR::UCDORM_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCDORM_0`"]
+    #[inline]
+    pub fn is_ucdorm_0(&self) -> bool {
+        *self == UCDORMR::UCDORM_0
+    }
+    #[doc = "Checks if the value of the field is `UCDORM_1`"]
+    #[inline]
+    pub fn is_ucdorm_1(&self) -> bool {
+        *self == UCDORMR::UCDORM_1
+    }
+}
+#[doc = "Possible values of the field `UCBRKIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBRKIER {
+    #[doc = "Received break characters do not set UCRXIFG"]
+    UCBRKIE_0,
+    #[doc = "Received break characters set UCRXIFG"]
+    UCBRKIE_1,
+}
+impl UCBRKIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBRKIER::UCBRKIE_0 => false,
+            UCBRKIER::UCBRKIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBRKIER {
+        match value {
+            false => UCBRKIER::UCBRKIE_0,
+            true => UCBRKIER::UCBRKIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBRKIE_0`"]
+    #[inline]
+    pub fn is_ucbrkie_0(&self) -> bool {
+        *self == UCBRKIER::UCBRKIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCBRKIE_1`"]
+    #[inline]
+    pub fn is_ucbrkie_1(&self) -> bool {
+        *self == UCBRKIER::UCBRKIE_1
+    }
+}
+#[doc = "Possible values of the field `UCRXEIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXEIER {
+    #[doc = "Erroneous characters rejected and UCRXIFG is not set"]
+    UCRXEIE_0,
+    #[doc = "Erroneous characters received set UCRXIFG"]
+    UCRXEIE_1,
+}
+impl UCRXEIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXEIER::UCRXEIE_0 => false,
+            UCRXEIER::UCRXEIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXEIER {
+        match value {
+            false => UCRXEIER::UCRXEIE_0,
+            true => UCRXEIER::UCRXEIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXEIE_0`"]
+    #[inline]
+    pub fn is_ucrxeie_0(&self) -> bool {
+        *self == UCRXEIER::UCRXEIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXEIE_1`"]
+    #[inline]
+    pub fn is_ucrxeie_1(&self) -> bool {
+        *self == UCRXEIER::UCRXEIE_1
+    }
+}
+#[doc = "Possible values of the field `UCSSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSSELR {
+    #[doc = "UCLK"]
+    UCSSEL_0,
+    #[doc = "ACLK"]
+    UCSSEL_1,
+    #[doc = "SMCLK"]
+    UCSSEL_2,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl UCSSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCSSELR::UCSSEL_0 => 0,
+            UCSSELR::UCSSEL_1 => 1,
+            UCSSELR::UCSSEL_2 => 2,
+            UCSSELR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCSSELR {
+        match value {
+            0 => UCSSELR::UCSSEL_0,
+            1 => UCSSELR::UCSSEL_1,
+            2 => UCSSELR::UCSSEL_2,
+            i => UCSSELR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSSEL_0`"]
+    #[inline]
+    pub fn is_ucssel_0(&self) -> bool {
+        *self == UCSSELR::UCSSEL_0
+    }
+    #[doc = "Checks if the value of the field is `UCSSEL_1`"]
+    #[inline]
+    pub fn is_ucssel_1(&self) -> bool {
+        *self == UCSSELR::UCSSEL_1
+    }
+    #[doc = "Checks if the value of the field is `UCSSEL_2`"]
+    #[inline]
+    pub fn is_ucssel_2(&self) -> bool {
+        *self == UCSSELR::UCSSEL_2
+    }
+}
+#[doc = "Possible values of the field `UCSYNC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSYNCR {
+    #[doc = "Asynchronous mode"]
+    UCSYNC_0,
+    #[doc = "Synchronous mode"]
+    UCSYNC_1,
+}
+impl UCSYNCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSYNCR::UCSYNC_0 => false,
+            UCSYNCR::UCSYNC_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSYNCR {
+        match value {
+            false => UCSYNCR::UCSYNC_0,
+            true => UCSYNCR::UCSYNC_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSYNC_0`"]
+    #[inline]
+    pub fn is_ucsync_0(&self) -> bool {
+        *self == UCSYNCR::UCSYNC_0
+    }
+    #[doc = "Checks if the value of the field is `UCSYNC_1`"]
+    #[inline]
+    pub fn is_ucsync_1(&self) -> bool {
+        *self == UCSYNCR::UCSYNC_1
+    }
+}
+#[doc = "Possible values of the field `UCMODE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCMODER {
+    #[doc = "UART mode"]
+    UCMODE_0,
+    #[doc = "Idle-line multiprocessor mode"]
+    UCMODE_1,
+    #[doc = "Address-bit multiprocessor mode"]
+    UCMODE_2,
+    #[doc = "UART mode with automatic baud-rate detection"]
+    UCMODE_3,
+}
+impl UCMODER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCMODER::UCMODE_0 => 0,
+            UCMODER::UCMODE_1 => 1,
+            UCMODER::UCMODE_2 => 2,
+            UCMODER::UCMODE_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCMODER {
+        match value {
+            0 => UCMODER::UCMODE_0,
+            1 => UCMODER::UCMODE_1,
+            2 => UCMODER::UCMODE_2,
+            3 => UCMODER::UCMODE_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_0`"]
+    #[inline]
+    pub fn is_ucmode_0(&self) -> bool {
+        *self == UCMODER::UCMODE_0
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_1`"]
+    #[inline]
+    pub fn is_ucmode_1(&self) -> bool {
+        *self == UCMODER::UCMODE_1
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_2`"]
+    #[inline]
+    pub fn is_ucmode_2(&self) -> bool {
+        *self == UCMODER::UCMODE_2
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_3`"]
+    #[inline]
+    pub fn is_ucmode_3(&self) -> bool {
+        *self == UCMODER::UCMODE_3
+    }
+}
+#[doc = "Possible values of the field `UCSPB`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSPBR {
+    #[doc = "One stop bit"]
+    UCSPB_0,
+    #[doc = "Two stop bits"]
+    UCSPB_1,
+}
+impl UCSPBR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSPBR::UCSPB_0 => false,
+            UCSPBR::UCSPB_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSPBR {
+        match value {
+            false => UCSPBR::UCSPB_0,
+            true => UCSPBR::UCSPB_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSPB_0`"]
+    #[inline]
+    pub fn is_ucspb_0(&self) -> bool {
+        *self == UCSPBR::UCSPB_0
+    }
+    #[doc = "Checks if the value of the field is `UCSPB_1`"]
+    #[inline]
+    pub fn is_ucspb_1(&self) -> bool {
+        *self == UCSPBR::UCSPB_1
+    }
+}
+#[doc = "Possible values of the field `UC7BIT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UC7BITR {
+    #[doc = "8-bit data"]
+    UC7BIT_0,
+    #[doc = "7-bit data"]
+    UC7BIT_1,
+}
+impl UC7BITR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UC7BITR::UC7BIT_0 => false,
+            UC7BITR::UC7BIT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UC7BITR {
+        match value {
+            false => UC7BITR::UC7BIT_0,
+            true => UC7BITR::UC7BIT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UC7BIT_0`"]
+    #[inline]
+    pub fn is_uc7bit_0(&self) -> bool {
+        *self == UC7BITR::UC7BIT_0
+    }
+    #[doc = "Checks if the value of the field is `UC7BIT_1`"]
+    #[inline]
+    pub fn is_uc7bit_1(&self) -> bool {
+        *self == UC7BITR::UC7BIT_1
+    }
+}
+#[doc = "Possible values of the field `UCMSB`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCMSBR {
+    #[doc = "LSB first"]
+    UCMSB_0,
+    #[doc = "MSB first"]
+    UCMSB_1,
+}
+impl UCMSBR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCMSBR::UCMSB_0 => false,
+            UCMSBR::UCMSB_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCMSBR {
+        match value {
+            false => UCMSBR::UCMSB_0,
+            true => UCMSBR::UCMSB_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCMSB_0`"]
+    #[inline]
+    pub fn is_ucmsb_0(&self) -> bool {
+        *self == UCMSBR::UCMSB_0
+    }
+    #[doc = "Checks if the value of the field is `UCMSB_1`"]
+    #[inline]
+    pub fn is_ucmsb_1(&self) -> bool {
+        *self == UCMSBR::UCMSB_1
+    }
+}
+#[doc = "Possible values of the field `UCPAR`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCPARR {
+    #[doc = "Odd parity"]
+    UCPAR_0,
+    #[doc = "Even parity"]
+    UCPAR_1,
+}
+impl UCPARR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCPARR::UCPAR_0 => false,
+            UCPARR::UCPAR_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCPARR {
+        match value {
+            false => UCPARR::UCPAR_0,
+            true => UCPARR::UCPAR_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCPAR_0`"]
+    #[inline]
+    pub fn is_ucpar_0(&self) -> bool {
+        *self == UCPARR::UCPAR_0
+    }
+    #[doc = "Checks if the value of the field is `UCPAR_1`"]
+    #[inline]
+    pub fn is_ucpar_1(&self) -> bool {
+        *self == UCPARR::UCPAR_1
+    }
+}
+#[doc = "Possible values of the field `UCPEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCPENR {
+    #[doc = "Parity disabled"]
+    UCPEN_0,
+    #[doc = "Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation."]
+    UCPEN_1,
+}
+impl UCPENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCPENR::UCPEN_0 => false,
+            UCPENR::UCPEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCPENR {
+        match value {
+            false => UCPENR::UCPEN_0,
+            true => UCPENR::UCPEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCPEN_0`"]
+    #[inline]
+    pub fn is_ucpen_0(&self) -> bool {
+        *self == UCPENR::UCPEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCPEN_1`"]
+    #[inline]
+    pub fn is_ucpen_1(&self) -> bool {
+        *self == UCPENR::UCPEN_1
+    }
+}
+#[doc = "Values that can be written to the field `UCSWRST`"]
+pub enum UCSWRSTW {
+    #[doc = "Disabled. eUSCI_A reset released for operation"]
+    UCSWRST_0,
+    #[doc = "Enabled. eUSCI_A logic held in reset state"]
+    UCSWRST_1,
+}
+impl UCSWRSTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSWRSTW::UCSWRST_0 => false,
+            UCSWRSTW::UCSWRST_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSWRSTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSWRSTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSWRSTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disabled. eUSCI_A reset released for operation"]
+    #[inline]
+    pub fn ucswrst_0(self) -> &'a mut W {
+        self.variant(UCSWRSTW::UCSWRST_0)
+    }
+    #[doc = "Enabled. eUSCI_A logic held in reset state"]
+    #[inline]
+    pub fn ucswrst_1(self) -> &'a mut W {
+        self.variant(UCSWRSTW::UCSWRST_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXBRK`"]
+pub enum UCTXBRKW {
+    #[doc = "Next frame transmitted is not a break"]
+    UCTXBRK_0,
+    #[doc = "Next frame transmitted is a break or a break/synch"]
+    UCTXBRK_1,
+}
+impl UCTXBRKW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXBRKW::UCTXBRK_0 => false,
+            UCTXBRKW::UCTXBRK_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXBRKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXBRKW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXBRKW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Next frame transmitted is not a break"]
+    #[inline]
+    pub fn uctxbrk_0(self) -> &'a mut W {
+        self.variant(UCTXBRKW::UCTXBRK_0)
+    }
+    #[doc = "Next frame transmitted is a break or a break/synch"]
+    #[inline]
+    pub fn uctxbrk_1(self) -> &'a mut W {
+        self.variant(UCTXBRKW::UCTXBRK_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXADDR`"]
+pub enum UCTXADDRW {
+    #[doc = "Next frame transmitted is data"]
+    UCTXADDR_0,
+    #[doc = "Next frame transmitted is an address"]
+    UCTXADDR_1,
+}
+impl UCTXADDRW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXADDRW::UCTXADDR_0 => false,
+            UCTXADDRW::UCTXADDR_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXADDRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXADDRW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXADDRW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Next frame transmitted is data"]
+    #[inline]
+    pub fn uctxaddr_0(self) -> &'a mut W {
+        self.variant(UCTXADDRW::UCTXADDR_0)
+    }
+    #[doc = "Next frame transmitted is an address"]
+    #[inline]
+    pub fn uctxaddr_1(self) -> &'a mut W {
+        self.variant(UCTXADDRW::UCTXADDR_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCDORM`"]
+pub enum UCDORMW {
+    #[doc = "Not dormant. All received characters set UCRXIFG."]
+    UCDORM_0,
+    #[doc = "Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG."]
+    UCDORM_1,
+}
+impl UCDORMW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCDORMW::UCDORM_0 => false,
+            UCDORMW::UCDORM_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCDORMW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCDORMW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCDORMW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Not dormant. All received characters set UCRXIFG."]
+    #[inline]
+    pub fn ucdorm_0(self) -> &'a mut W {
+        self.variant(UCDORMW::UCDORM_0)
+    }
+    #[doc = "Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG."]
+    #[inline]
+    pub fn ucdorm_1(self) -> &'a mut W {
+        self.variant(UCDORMW::UCDORM_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCBRKIE`"]
+pub enum UCBRKIEW {
+    #[doc = "Received break characters do not set UCRXIFG"]
+    UCBRKIE_0,
+    #[doc = "Received break characters set UCRXIFG"]
+    UCBRKIE_1,
+}
+impl UCBRKIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCBRKIEW::UCBRKIE_0 => false,
+            UCBRKIEW::UCBRKIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBRKIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBRKIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCBRKIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Received break characters do not set UCRXIFG"]
+    #[inline]
+    pub fn ucbrkie_0(self) -> &'a mut W {
+        self.variant(UCBRKIEW::UCBRKIE_0)
+    }
+    #[doc = "Received break characters set UCRXIFG"]
+    #[inline]
+    pub fn ucbrkie_1(self) -> &'a mut W {
+        self.variant(UCBRKIEW::UCBRKIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXEIE`"]
+pub enum UCRXEIEW {
+    #[doc = "Erroneous characters rejected and UCRXIFG is not set"]
+    UCRXEIE_0,
+    #[doc = "Erroneous characters received set UCRXIFG"]
+    UCRXEIE_1,
+}
+impl UCRXEIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXEIEW::UCRXEIE_0 => false,
+            UCRXEIEW::UCRXEIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXEIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXEIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXEIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Erroneous characters rejected and UCRXIFG is not set"]
+    #[inline]
+    pub fn ucrxeie_0(self) -> &'a mut W {
+        self.variant(UCRXEIEW::UCRXEIE_0)
+    }
+    #[doc = "Erroneous characters received set UCRXIFG"]
+    #[inline]
+    pub fn ucrxeie_1(self) -> &'a mut W {
+        self.variant(UCRXEIEW::UCRXEIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSSEL`"]
+pub enum UCSSELW {
+    #[doc = "UCLK"]
+    UCSSEL_0,
+    #[doc = "ACLK"]
+    UCSSEL_1,
+    #[doc = "SMCLK"]
+    UCSSEL_2,
+}
+impl UCSSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCSSELW::UCSSEL_0 => 0,
+            UCSSELW::UCSSEL_1 => 1,
+            UCSSELW::UCSSEL_2 => 2,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSSELW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "UCLK"]
+    #[inline]
+    pub fn ucssel_0(self) -> &'a mut W {
+        self.variant(UCSSELW::UCSSEL_0)
+    }
+    #[doc = "ACLK"]
+    #[inline]
+    pub fn ucssel_1(self) -> &'a mut W {
+        self.variant(UCSSELW::UCSSEL_1)
+    }
+    #[doc = "SMCLK"]
+    #[inline]
+    pub fn ucssel_2(self) -> &'a mut W {
+        self.variant(UCSSELW::UCSSEL_2)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSYNC`"]
+pub enum UCSYNCW {
+    #[doc = "Asynchronous mode"]
+    UCSYNC_0,
+    #[doc = "Synchronous mode"]
+    UCSYNC_1,
+}
+impl UCSYNCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSYNCW::UCSYNC_0 => false,
+            UCSYNCW::UCSYNC_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSYNCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSYNCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSYNCW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Asynchronous mode"]
+    #[inline]
+    pub fn ucsync_0(self) -> &'a mut W {
+        self.variant(UCSYNCW::UCSYNC_0)
+    }
+    #[doc = "Synchronous mode"]
+    #[inline]
+    pub fn ucsync_1(self) -> &'a mut W {
+        self.variant(UCSYNCW::UCSYNC_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCMODE`"]
+pub enum UCMODEW {
+    #[doc = "UART mode"]
+    UCMODE_0,
+    #[doc = "Idle-line multiprocessor mode"]
+    UCMODE_1,
+    #[doc = "Address-bit multiprocessor mode"]
+    UCMODE_2,
+    #[doc = "UART mode with automatic baud-rate detection"]
+    UCMODE_3,
+}
+impl UCMODEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCMODEW::UCMODE_0 => 0,
+            UCMODEW::UCMODE_1 => 1,
+            UCMODEW::UCMODE_2 => 2,
+            UCMODEW::UCMODE_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCMODEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCMODEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCMODEW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "UART mode"]
+    #[inline]
+    pub fn ucmode_0(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_0)
+    }
+    #[doc = "Idle-line multiprocessor mode"]
+    #[inline]
+    pub fn ucmode_1(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_1)
+    }
+    #[doc = "Address-bit multiprocessor mode"]
+    #[inline]
+    pub fn ucmode_2(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_2)
+    }
+    #[doc = "UART mode with automatic baud-rate detection"]
+    #[inline]
+    pub fn ucmode_3(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSPB`"]
+pub enum UCSPBW {
+    #[doc = "One stop bit"]
+    UCSPB_0,
+    #[doc = "Two stop bits"]
+    UCSPB_1,
+}
+impl UCSPBW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSPBW::UCSPB_0 => false,
+            UCSPBW::UCSPB_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSPBW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSPBW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSPBW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "One stop bit"]
+    #[inline]
+    pub fn ucspb_0(self) -> &'a mut W {
+        self.variant(UCSPBW::UCSPB_0)
+    }
+    #[doc = "Two stop bits"]
+    #[inline]
+    pub fn ucspb_1(self) -> &'a mut W {
+        self.variant(UCSPBW::UCSPB_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UC7BIT`"]
+pub enum UC7BITW {
+    #[doc = "8-bit data"]
+    UC7BIT_0,
+    #[doc = "7-bit data"]
+    UC7BIT_1,
+}
+impl UC7BITW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UC7BITW::UC7BIT_0 => false,
+            UC7BITW::UC7BIT_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UC7BITW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UC7BITW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UC7BITW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "8-bit data"]
+    #[inline]
+    pub fn uc7bit_0(self) -> &'a mut W {
+        self.variant(UC7BITW::UC7BIT_0)
+    }
+    #[doc = "7-bit data"]
+    #[inline]
+    pub fn uc7bit_1(self) -> &'a mut W {
+        self.variant(UC7BITW::UC7BIT_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCMSB`"]
+pub enum UCMSBW {
+    #[doc = "LSB first"]
+    UCMSB_0,
+    #[doc = "MSB first"]
+    UCMSB_1,
+}
+impl UCMSBW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCMSBW::UCMSB_0 => false,
+            UCMSBW::UCMSB_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCMSBW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCMSBW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCMSBW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "LSB first"]
+    #[inline]
+    pub fn ucmsb_0(self) -> &'a mut W {
+        self.variant(UCMSBW::UCMSB_0)
+    }
+    #[doc = "MSB first"]
+    #[inline]
+    pub fn ucmsb_1(self) -> &'a mut W {
+        self.variant(UCMSBW::UCMSB_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCPAR`"]
+pub enum UCPARW {
+    #[doc = "Odd parity"]
+    UCPAR_0,
+    #[doc = "Even parity"]
+    UCPAR_1,
+}
+impl UCPARW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCPARW::UCPAR_0 => false,
+            UCPARW::UCPAR_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCPARW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCPARW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCPARW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Odd parity"]
+    #[inline]
+    pub fn ucpar_0(self) -> &'a mut W {
+        self.variant(UCPARW::UCPAR_0)
+    }
+    #[doc = "Even parity"]
+    #[inline]
+    pub fn ucpar_1(self) -> &'a mut W {
+        self.variant(UCPARW::UCPAR_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCPEN`"]
+pub enum UCPENW {
+    #[doc = "Parity disabled"]
+    UCPEN_0,
+    #[doc = "Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation."]
+    UCPEN_1,
+}
+impl UCPENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCPENW::UCPEN_0 => false,
+            UCPENW::UCPEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCPENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCPENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCPENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Parity disabled"]
+    #[inline]
+    pub fn ucpen_0(self) -> &'a mut W {
+        self.variant(UCPENW::UCPEN_0)
+    }
+    #[doc = "Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation."]
+    #[inline]
+    pub fn ucpen_1(self) -> &'a mut W {
+        self.variant(UCPENW::UCPEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Software reset enable"]
+    #[inline]
+    pub fn ucswrst(&self) -> UCSWRSTR {
+        UCSWRSTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Transmit break"]
+    #[inline]
+    pub fn uctxbrk(&self) -> UCTXBRKR {
+        UCTXBRKR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - Transmit address"]
+    #[inline]
+    pub fn uctxaddr(&self) -> UCTXADDRR {
+        UCTXADDRR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Dormant"]
+    #[inline]
+    pub fn ucdorm(&self) -> UCDORMR {
+        UCDORMR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 4 - Receive break character interrupt enable"]
+    #[inline]
+    pub fn ucbrkie(&self) -> UCBRKIER {
+        UCBRKIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - Receive erroneous-character interrupt enable"]
+    #[inline]
+    pub fn ucrxeie(&self) -> UCRXEIER {
+        UCRXEIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 6:7 - eUSCI_A clock source select"]
+    #[inline]
+    pub fn ucssel(&self) -> UCSSELR {
+        UCSSELR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 8 - Synchronous mode enable"]
+    #[inline]
+    pub fn ucsync(&self) -> UCSYNCR {
+        UCSYNCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 9:10 - eUSCI_A mode"]
+    #[inline]
+    pub fn ucmode(&self) -> UCMODER {
+        UCMODER::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 11 - Stop bit select"]
+    #[inline]
+    pub fn ucspb(&self) -> UCSPBR {
+        UCSPBR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 12 - Character length"]
+    #[inline]
+    pub fn uc7bit(&self) -> UC7BITR {
+        UC7BITR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 13 - MSB first select"]
+    #[inline]
+    pub fn ucmsb(&self) -> UCMSBR {
+        UCMSBR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 14 - Parity select"]
+    #[inline]
+    pub fn ucpar(&self) -> UCPARR {
+        UCPARR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 15 - Parity enable"]
+    #[inline]
+    pub fn ucpen(&self) -> UCPENR {
+        UCPENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 1 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Software reset enable"]
+    #[inline]
+    pub fn ucswrst(&mut self) -> _UCSWRSTW {
+        _UCSWRSTW { w: self }
+    }
+    #[doc = "Bit 1 - Transmit break"]
+    #[inline]
+    pub fn uctxbrk(&mut self) -> _UCTXBRKW {
+        _UCTXBRKW { w: self }
+    }
+    #[doc = "Bit 2 - Transmit address"]
+    #[inline]
+    pub fn uctxaddr(&mut self) -> _UCTXADDRW {
+        _UCTXADDRW { w: self }
+    }
+    #[doc = "Bit 3 - Dormant"]
+    #[inline]
+    pub fn ucdorm(&mut self) -> _UCDORMW {
+        _UCDORMW { w: self }
+    }
+    #[doc = "Bit 4 - Receive break character interrupt enable"]
+    #[inline]
+    pub fn ucbrkie(&mut self) -> _UCBRKIEW {
+        _UCBRKIEW { w: self }
+    }
+    #[doc = "Bit 5 - Receive erroneous-character interrupt enable"]
+    #[inline]
+    pub fn ucrxeie(&mut self) -> _UCRXEIEW {
+        _UCRXEIEW { w: self }
+    }
+    #[doc = "Bits 6:7 - eUSCI_A clock source select"]
+    #[inline]
+    pub fn ucssel(&mut self) -> _UCSSELW {
+        _UCSSELW { w: self }
+    }
+    #[doc = "Bit 8 - Synchronous mode enable"]
+    #[inline]
+    pub fn ucsync(&mut self) -> _UCSYNCW {
+        _UCSYNCW { w: self }
+    }
+    #[doc = "Bits 9:10 - eUSCI_A mode"]
+    #[inline]
+    pub fn ucmode(&mut self) -> _UCMODEW {
+        _UCMODEW { w: self }
+    }
+    #[doc = "Bit 11 - Stop bit select"]
+    #[inline]
+    pub fn ucspb(&mut self) -> _UCSPBW {
+        _UCSPBW { w: self }
+    }
+    #[doc = "Bit 12 - Character length"]
+    #[inline]
+    pub fn uc7bit(&mut self) -> _UC7BITW {
+        _UC7BITW { w: self }
+    }
+    #[doc = "Bit 13 - MSB first select"]
+    #[inline]
+    pub fn ucmsb(&mut self) -> _UCMSBW {
+        _UCMSBW { w: self }
+    }
+    #[doc = "Bit 14 - Parity select"]
+    #[inline]
+    pub fn ucpar(&mut self) -> _UCPARW {
+        _UCPARW { w: self }
+    }
+    #[doc = "Bit 15 - Parity enable"]
+    #[inline]
+    pub fn ucpen(&mut self) -> _UCPENW {
+        _UCPENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a0/ucax_ctlw1.rs b/example-source/msp432p401r/src/eusci_a0/ucax_ctlw1.rs
new file mode 100644
index 0000000..365cc0d
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a0/ucax_ctlw1.rs
@@ -0,0 +1,200 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXCTLW1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCGLIT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCGLITR {
+    #[doc = "Approximately 2 ns (equivalent of 1 delay element)"]
+    UCGLIT_0,
+    #[doc = "Approximately 50 ns"]
+    UCGLIT_1,
+    #[doc = "Approximately 100 ns"]
+    UCGLIT_2,
+    #[doc = "Approximately 200 ns"]
+    UCGLIT_3,
+}
+impl UCGLITR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCGLITR::UCGLIT_0 => 0,
+            UCGLITR::UCGLIT_1 => 1,
+            UCGLITR::UCGLIT_2 => 2,
+            UCGLITR::UCGLIT_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCGLITR {
+        match value {
+            0 => UCGLITR::UCGLIT_0,
+            1 => UCGLITR::UCGLIT_1,
+            2 => UCGLITR::UCGLIT_2,
+            3 => UCGLITR::UCGLIT_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_0`"]
+    #[inline]
+    pub fn is_ucglit_0(&self) -> bool {
+        *self == UCGLITR::UCGLIT_0
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_1`"]
+    #[inline]
+    pub fn is_ucglit_1(&self) -> bool {
+        *self == UCGLITR::UCGLIT_1
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_2`"]
+    #[inline]
+    pub fn is_ucglit_2(&self) -> bool {
+        *self == UCGLITR::UCGLIT_2
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_3`"]
+    #[inline]
+    pub fn is_ucglit_3(&self) -> bool {
+        *self == UCGLITR::UCGLIT_3
+    }
+}
+#[doc = "Values that can be written to the field `UCGLIT`"]
+pub enum UCGLITW {
+    #[doc = "Approximately 2 ns (equivalent of 1 delay element)"]
+    UCGLIT_0,
+    #[doc = "Approximately 50 ns"]
+    UCGLIT_1,
+    #[doc = "Approximately 100 ns"]
+    UCGLIT_2,
+    #[doc = "Approximately 200 ns"]
+    UCGLIT_3,
+}
+impl UCGLITW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCGLITW::UCGLIT_0 => 0,
+            UCGLITW::UCGLIT_1 => 1,
+            UCGLITW::UCGLIT_2 => 2,
+            UCGLITW::UCGLIT_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCGLITW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCGLITW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCGLITW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Approximately 2 ns (equivalent of 1 delay element)"]
+    #[inline]
+    pub fn ucglit_0(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_0)
+    }
+    #[doc = "Approximately 50 ns"]
+    #[inline]
+    pub fn ucglit_1(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_1)
+    }
+    #[doc = "Approximately 100 ns"]
+    #[inline]
+    pub fn ucglit_2(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_2)
+    }
+    #[doc = "Approximately 200 ns"]
+    #[inline]
+    pub fn ucglit_3(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:1 - Deglitch time"]
+    #[inline]
+    pub fn ucglit(&self) -> UCGLITR {
+        UCGLITR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 3 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:1 - Deglitch time"]
+    #[inline]
+    pub fn ucglit(&mut self) -> _UCGLITW {
+        _UCGLITW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a0/ucax_ie.rs b/example-source/msp432p401r/src/eusci_a0/ucax_ie.rs
new file mode 100644
index 0000000..f91baad
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a0/ucax_ie.rs
@@ -0,0 +1,540 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXIE {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCRXIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIER {
+    #[doc = "Interrupt disabled"]
+    UCRXIE_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE_1,
+}
+impl UCRXIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIER::UCRXIE_0 => false,
+            UCRXIER::UCRXIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIER {
+        match value {
+            false => UCRXIER::UCRXIE_0,
+            true => UCRXIER::UCRXIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE_0`"]
+    #[inline]
+    pub fn is_ucrxie_0(&self) -> bool {
+        *self == UCRXIER::UCRXIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE_1`"]
+    #[inline]
+    pub fn is_ucrxie_1(&self) -> bool {
+        *self == UCRXIER::UCRXIE_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIER {
+    #[doc = "Interrupt disabled"]
+    UCTXIE_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE_1,
+}
+impl UCTXIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIER::UCTXIE_0 => false,
+            UCTXIER::UCTXIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIER {
+        match value {
+            false => UCTXIER::UCTXIE_0,
+            true => UCTXIER::UCTXIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE_0`"]
+    #[inline]
+    pub fn is_uctxie_0(&self) -> bool {
+        *self == UCTXIER::UCTXIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE_1`"]
+    #[inline]
+    pub fn is_uctxie_1(&self) -> bool {
+        *self == UCTXIER::UCTXIE_1
+    }
+}
+#[doc = "Possible values of the field `UCSTTIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTTIER {
+    #[doc = "Interrupt disabled"]
+    UCSTTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCSTTIE_1,
+}
+impl UCSTTIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTTIER::UCSTTIE_0 => false,
+            UCSTTIER::UCSTTIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTTIER {
+        match value {
+            false => UCSTTIER::UCSTTIE_0,
+            true => UCSTTIER::UCSTTIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIE_0`"]
+    #[inline]
+    pub fn is_ucsttie_0(&self) -> bool {
+        *self == UCSTTIER::UCSTTIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIE_1`"]
+    #[inline]
+    pub fn is_ucsttie_1(&self) -> bool {
+        *self == UCSTTIER::UCSTTIE_1
+    }
+}
+#[doc = "Possible values of the field `UCTXCPTIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXCPTIER {
+    #[doc = "Interrupt disabled"]
+    UCTXCPTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCTXCPTIE_1,
+}
+impl UCTXCPTIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXCPTIER::UCTXCPTIE_0 => false,
+            UCTXCPTIER::UCTXCPTIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXCPTIER {
+        match value {
+            false => UCTXCPTIER::UCTXCPTIE_0,
+            true => UCTXCPTIER::UCTXCPTIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXCPTIE_0`"]
+    #[inline]
+    pub fn is_uctxcptie_0(&self) -> bool {
+        *self == UCTXCPTIER::UCTXCPTIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXCPTIE_1`"]
+    #[inline]
+    pub fn is_uctxcptie_1(&self) -> bool {
+        *self == UCTXCPTIER::UCTXCPTIE_1
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIE`"]
+pub enum UCRXIEW {
+    #[doc = "Interrupt disabled"]
+    UCRXIE_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE_1,
+}
+impl UCRXIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIEW::UCRXIE_0 => false,
+            UCRXIEW::UCRXIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucrxie_0(self) -> &'a mut W {
+        self.variant(UCRXIEW::UCRXIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucrxie_1(self) -> &'a mut W {
+        self.variant(UCRXIEW::UCRXIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIE`"]
+pub enum UCTXIEW {
+    #[doc = "Interrupt disabled"]
+    UCTXIE_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE_1,
+}
+impl UCTXIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIEW::UCTXIE_0 => false,
+            UCTXIEW::UCTXIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn uctxie_0(self) -> &'a mut W {
+        self.variant(UCTXIEW::UCTXIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn uctxie_1(self) -> &'a mut W {
+        self.variant(UCTXIEW::UCTXIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTTIE`"]
+pub enum UCSTTIEW {
+    #[doc = "Interrupt disabled"]
+    UCSTTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCSTTIE_1,
+}
+impl UCSTTIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTTIEW::UCSTTIE_0 => false,
+            UCSTTIEW::UCSTTIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTTIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTTIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTTIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucsttie_0(self) -> &'a mut W {
+        self.variant(UCSTTIEW::UCSTTIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucsttie_1(self) -> &'a mut W {
+        self.variant(UCSTTIEW::UCSTTIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXCPTIE`"]
+pub enum UCTXCPTIEW {
+    #[doc = "Interrupt disabled"]
+    UCTXCPTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCTXCPTIE_1,
+}
+impl UCTXCPTIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXCPTIEW::UCTXCPTIE_0 => false,
+            UCTXCPTIEW::UCTXCPTIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXCPTIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXCPTIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXCPTIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn uctxcptie_0(self) -> &'a mut W {
+        self.variant(UCTXCPTIEW::UCTXCPTIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn uctxcptie_1(self) -> &'a mut W {
+        self.variant(UCTXCPTIEW::UCTXCPTIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Receive interrupt enable"]
+    #[inline]
+    pub fn ucrxie(&self) -> UCRXIER {
+        UCRXIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Transmit interrupt enable"]
+    #[inline]
+    pub fn uctxie(&self) -> UCTXIER {
+        UCTXIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - Start bit interrupt enable"]
+    #[inline]
+    pub fn ucsttie(&self) -> UCSTTIER {
+        UCSTTIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Transmit complete interrupt enable"]
+    #[inline]
+    pub fn uctxcptie(&self) -> UCTXCPTIER {
+        UCTXCPTIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Receive interrupt enable"]
+    #[inline]
+    pub fn ucrxie(&mut self) -> _UCRXIEW {
+        _UCRXIEW { w: self }
+    }
+    #[doc = "Bit 1 - Transmit interrupt enable"]
+    #[inline]
+    pub fn uctxie(&mut self) -> _UCTXIEW {
+        _UCTXIEW { w: self }
+    }
+    #[doc = "Bit 2 - Start bit interrupt enable"]
+    #[inline]
+    pub fn ucsttie(&mut self) -> _UCSTTIEW {
+        _UCSTTIEW { w: self }
+    }
+    #[doc = "Bit 3 - Transmit complete interrupt enable"]
+    #[inline]
+    pub fn uctxcptie(&mut self) -> _UCTXCPTIEW {
+        _UCTXCPTIEW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a0/ucax_ifg.rs b/example-source/msp432p401r/src/eusci_a0/ucax_ifg.rs
new file mode 100644
index 0000000..88bb34d
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a0/ucax_ifg.rs
@@ -0,0 +1,540 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXIFG {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCRXIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIFGR {
+    #[doc = "No interrupt pending"]
+    UCRXIFG_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG_1,
+}
+impl UCRXIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIFGR::UCRXIFG_0 => false,
+            UCRXIFGR::UCRXIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIFGR {
+        match value {
+            false => UCRXIFGR::UCRXIFG_0,
+            true => UCRXIFGR::UCRXIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG_0`"]
+    #[inline]
+    pub fn is_ucrxifg_0(&self) -> bool {
+        *self == UCRXIFGR::UCRXIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG_1`"]
+    #[inline]
+    pub fn is_ucrxifg_1(&self) -> bool {
+        *self == UCRXIFGR::UCRXIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIFGR {
+    #[doc = "No interrupt pending"]
+    UCTXIFG_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG_1,
+}
+impl UCTXIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIFGR::UCTXIFG_0 => false,
+            UCTXIFGR::UCTXIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIFGR {
+        match value {
+            false => UCTXIFGR::UCTXIFG_0,
+            true => UCTXIFGR::UCTXIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG_0`"]
+    #[inline]
+    pub fn is_uctxifg_0(&self) -> bool {
+        *self == UCTXIFGR::UCTXIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG_1`"]
+    #[inline]
+    pub fn is_uctxifg_1(&self) -> bool {
+        *self == UCTXIFGR::UCTXIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCSTTIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTTIFGR {
+    #[doc = "No interrupt pending"]
+    UCSTTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCSTTIFG_1,
+}
+impl UCSTTIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTTIFGR::UCSTTIFG_0 => false,
+            UCSTTIFGR::UCSTTIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTTIFGR {
+        match value {
+            false => UCSTTIFGR::UCSTTIFG_0,
+            true => UCSTTIFGR::UCSTTIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIFG_0`"]
+    #[inline]
+    pub fn is_ucsttifg_0(&self) -> bool {
+        *self == UCSTTIFGR::UCSTTIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIFG_1`"]
+    #[inline]
+    pub fn is_ucsttifg_1(&self) -> bool {
+        *self == UCSTTIFGR::UCSTTIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCTXCPTIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXCPTIFGR {
+    #[doc = "No interrupt pending"]
+    UCTXCPTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCTXCPTIFG_1,
+}
+impl UCTXCPTIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXCPTIFGR::UCTXCPTIFG_0 => false,
+            UCTXCPTIFGR::UCTXCPTIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXCPTIFGR {
+        match value {
+            false => UCTXCPTIFGR::UCTXCPTIFG_0,
+            true => UCTXCPTIFGR::UCTXCPTIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXCPTIFG_0`"]
+    #[inline]
+    pub fn is_uctxcptifg_0(&self) -> bool {
+        *self == UCTXCPTIFGR::UCTXCPTIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXCPTIFG_1`"]
+    #[inline]
+    pub fn is_uctxcptifg_1(&self) -> bool {
+        *self == UCTXCPTIFGR::UCTXCPTIFG_1
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIFG`"]
+pub enum UCRXIFGW {
+    #[doc = "No interrupt pending"]
+    UCRXIFG_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG_1,
+}
+impl UCRXIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIFGW::UCRXIFG_0 => false,
+            UCRXIFGW::UCRXIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucrxifg_0(self) -> &'a mut W {
+        self.variant(UCRXIFGW::UCRXIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucrxifg_1(self) -> &'a mut W {
+        self.variant(UCRXIFGW::UCRXIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIFG`"]
+pub enum UCTXIFGW {
+    #[doc = "No interrupt pending"]
+    UCTXIFG_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG_1,
+}
+impl UCTXIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIFGW::UCTXIFG_0 => false,
+            UCTXIFGW::UCTXIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn uctxifg_0(self) -> &'a mut W {
+        self.variant(UCTXIFGW::UCTXIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn uctxifg_1(self) -> &'a mut W {
+        self.variant(UCTXIFGW::UCTXIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTTIFG`"]
+pub enum UCSTTIFGW {
+    #[doc = "No interrupt pending"]
+    UCSTTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCSTTIFG_1,
+}
+impl UCSTTIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTTIFGW::UCSTTIFG_0 => false,
+            UCSTTIFGW::UCSTTIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTTIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTTIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTTIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucsttifg_0(self) -> &'a mut W {
+        self.variant(UCSTTIFGW::UCSTTIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucsttifg_1(self) -> &'a mut W {
+        self.variant(UCSTTIFGW::UCSTTIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXCPTIFG`"]
+pub enum UCTXCPTIFGW {
+    #[doc = "No interrupt pending"]
+    UCTXCPTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCTXCPTIFG_1,
+}
+impl UCTXCPTIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXCPTIFGW::UCTXCPTIFG_0 => false,
+            UCTXCPTIFGW::UCTXCPTIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXCPTIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXCPTIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXCPTIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn uctxcptifg_0(self) -> &'a mut W {
+        self.variant(UCTXCPTIFGW::UCTXCPTIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn uctxcptifg_1(self) -> &'a mut W {
+        self.variant(UCTXCPTIFGW::UCTXCPTIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Receive interrupt flag"]
+    #[inline]
+    pub fn ucrxifg(&self) -> UCRXIFGR {
+        UCRXIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Transmit interrupt flag"]
+    #[inline]
+    pub fn uctxifg(&self) -> UCTXIFGR {
+        UCTXIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - Start bit interrupt flag"]
+    #[inline]
+    pub fn ucsttifg(&self) -> UCSTTIFGR {
+        UCSTTIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Transmit ready interrupt enable"]
+    #[inline]
+    pub fn uctxcptifg(&self) -> UCTXCPTIFGR {
+        UCTXCPTIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 2 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Receive interrupt flag"]
+    #[inline]
+    pub fn ucrxifg(&mut self) -> _UCRXIFGW {
+        _UCRXIFGW { w: self }
+    }
+    #[doc = "Bit 1 - Transmit interrupt flag"]
+    #[inline]
+    pub fn uctxifg(&mut self) -> _UCTXIFGW {
+        _UCTXIFGW { w: self }
+    }
+    #[doc = "Bit 2 - Start bit interrupt flag"]
+    #[inline]
+    pub fn ucsttifg(&mut self) -> _UCSTTIFGW {
+        _UCSTTIFGW { w: self }
+    }
+    #[doc = "Bit 3 - Transmit ready interrupt enable"]
+    #[inline]
+    pub fn uctxcptifg(&mut self) -> _UCTXCPTIFGW {
+        _UCTXCPTIFGW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a0/ucax_irctl.rs b/example-source/msp432p401r/src/eusci_a0/ucax_irctl.rs
new file mode 100644
index 0000000..38d0d14
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a0/ucax_irctl.rs
@@ -0,0 +1,622 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXIRCTL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCIREN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCIRENR {
+    #[doc = "IrDA encoder/decoder disabled"]
+    UCIREN_0,
+    #[doc = "IrDA encoder/decoder enabled"]
+    UCIREN_1,
+}
+impl UCIRENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCIRENR::UCIREN_0 => false,
+            UCIRENR::UCIREN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCIRENR {
+        match value {
+            false => UCIRENR::UCIREN_0,
+            true => UCIRENR::UCIREN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCIREN_0`"]
+    #[inline]
+    pub fn is_uciren_0(&self) -> bool {
+        *self == UCIRENR::UCIREN_0
+    }
+    #[doc = "Checks if the value of the field is `UCIREN_1`"]
+    #[inline]
+    pub fn is_uciren_1(&self) -> bool {
+        *self == UCIRENR::UCIREN_1
+    }
+}
+#[doc = "Possible values of the field `UCIRTXCLK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCIRTXCLKR {
+    #[doc = "BRCLK"]
+    UCIRTXCLK_0,
+    #[doc = "BITCLK16 when UCOS16 = 1. Otherwise, BRCLK."]
+    UCIRTXCLK_1,
+}
+impl UCIRTXCLKR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCIRTXCLKR::UCIRTXCLK_0 => false,
+            UCIRTXCLKR::UCIRTXCLK_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCIRTXCLKR {
+        match value {
+            false => UCIRTXCLKR::UCIRTXCLK_0,
+            true => UCIRTXCLKR::UCIRTXCLK_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCIRTXCLK_0`"]
+    #[inline]
+    pub fn is_ucirtxclk_0(&self) -> bool {
+        *self == UCIRTXCLKR::UCIRTXCLK_0
+    }
+    #[doc = "Checks if the value of the field is `UCIRTXCLK_1`"]
+    #[inline]
+    pub fn is_ucirtxclk_1(&self) -> bool {
+        *self == UCIRTXCLKR::UCIRTXCLK_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCIRTXPLR {
+    bits: u8,
+}
+impl UCIRTXPLR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `UCIRRXFE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCIRRXFER {
+    #[doc = "Receive filter disabled"]
+    UCIRRXFE_0,
+    #[doc = "Receive filter enabled"]
+    UCIRRXFE_1,
+}
+impl UCIRRXFER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCIRRXFER::UCIRRXFE_0 => false,
+            UCIRRXFER::UCIRRXFE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCIRRXFER {
+        match value {
+            false => UCIRRXFER::UCIRRXFE_0,
+            true => UCIRRXFER::UCIRRXFE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCIRRXFE_0`"]
+    #[inline]
+    pub fn is_ucirrxfe_0(&self) -> bool {
+        *self == UCIRRXFER::UCIRRXFE_0
+    }
+    #[doc = "Checks if the value of the field is `UCIRRXFE_1`"]
+    #[inline]
+    pub fn is_ucirrxfe_1(&self) -> bool {
+        *self == UCIRRXFER::UCIRRXFE_1
+    }
+}
+#[doc = "Possible values of the field `UCIRRXPL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCIRRXPLR {
+    #[doc = "IrDA transceiver delivers a high pulse when a light pulse is seen"]
+    UCIRRXPL_0,
+    #[doc = "IrDA transceiver delivers a low pulse when a light pulse is seen"]
+    UCIRRXPL_1,
+}
+impl UCIRRXPLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCIRRXPLR::UCIRRXPL_0 => false,
+            UCIRRXPLR::UCIRRXPL_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCIRRXPLR {
+        match value {
+            false => UCIRRXPLR::UCIRRXPL_0,
+            true => UCIRRXPLR::UCIRRXPL_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCIRRXPL_0`"]
+    #[inline]
+    pub fn is_ucirrxpl_0(&self) -> bool {
+        *self == UCIRRXPLR::UCIRRXPL_0
+    }
+    #[doc = "Checks if the value of the field is `UCIRRXPL_1`"]
+    #[inline]
+    pub fn is_ucirrxpl_1(&self) -> bool {
+        *self == UCIRRXPLR::UCIRRXPL_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCIRRXFLR {
+    bits: u8,
+}
+impl UCIRRXFLR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Values that can be written to the field `UCIREN`"]
+pub enum UCIRENW {
+    #[doc = "IrDA encoder/decoder disabled"]
+    UCIREN_0,
+    #[doc = "IrDA encoder/decoder enabled"]
+    UCIREN_1,
+}
+impl UCIRENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCIRENW::UCIREN_0 => false,
+            UCIRENW::UCIREN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCIRENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCIRENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCIRENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "IrDA encoder/decoder disabled"]
+    #[inline]
+    pub fn uciren_0(self) -> &'a mut W {
+        self.variant(UCIRENW::UCIREN_0)
+    }
+    #[doc = "IrDA encoder/decoder enabled"]
+    #[inline]
+    pub fn uciren_1(self) -> &'a mut W {
+        self.variant(UCIRENW::UCIREN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCIRTXCLK`"]
+pub enum UCIRTXCLKW {
+    #[doc = "BRCLK"]
+    UCIRTXCLK_0,
+    #[doc = "BITCLK16 when UCOS16 = 1. Otherwise, BRCLK."]
+    UCIRTXCLK_1,
+}
+impl UCIRTXCLKW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCIRTXCLKW::UCIRTXCLK_0 => false,
+            UCIRTXCLKW::UCIRTXCLK_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCIRTXCLKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCIRTXCLKW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCIRTXCLKW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "BRCLK"]
+    #[inline]
+    pub fn ucirtxclk_0(self) -> &'a mut W {
+        self.variant(UCIRTXCLKW::UCIRTXCLK_0)
+    }
+    #[doc = "BITCLK16 when UCOS16 = 1. Otherwise, BRCLK."]
+    #[inline]
+    pub fn ucirtxclk_1(self) -> &'a mut W {
+        self.variant(UCIRTXCLKW::UCIRTXCLK_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCIRTXPLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCIRTXPLW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 63;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCIRRXFE`"]
+pub enum UCIRRXFEW {
+    #[doc = "Receive filter disabled"]
+    UCIRRXFE_0,
+    #[doc = "Receive filter enabled"]
+    UCIRRXFE_1,
+}
+impl UCIRRXFEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCIRRXFEW::UCIRRXFE_0 => false,
+            UCIRRXFEW::UCIRRXFE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCIRRXFEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCIRRXFEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCIRRXFEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Receive filter disabled"]
+    #[inline]
+    pub fn ucirrxfe_0(self) -> &'a mut W {
+        self.variant(UCIRRXFEW::UCIRRXFE_0)
+    }
+    #[doc = "Receive filter enabled"]
+    #[inline]
+    pub fn ucirrxfe_1(self) -> &'a mut W {
+        self.variant(UCIRRXFEW::UCIRRXFE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCIRRXPL`"]
+pub enum UCIRRXPLW {
+    #[doc = "IrDA transceiver delivers a high pulse when a light pulse is seen"]
+    UCIRRXPL_0,
+    #[doc = "IrDA transceiver delivers a low pulse when a light pulse is seen"]
+    UCIRRXPL_1,
+}
+impl UCIRRXPLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCIRRXPLW::UCIRRXPL_0 => false,
+            UCIRRXPLW::UCIRRXPL_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCIRRXPLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCIRRXPLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCIRRXPLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "IrDA transceiver delivers a high pulse when a light pulse is seen"]
+    #[inline]
+    pub fn ucirrxpl_0(self) -> &'a mut W {
+        self.variant(UCIRRXPLW::UCIRRXPL_0)
+    }
+    #[doc = "IrDA transceiver delivers a low pulse when a light pulse is seen"]
+    #[inline]
+    pub fn ucirrxpl_1(self) -> &'a mut W {
+        self.variant(UCIRRXPLW::UCIRRXPL_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCIRRXFLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCIRRXFLW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - IrDA encoder/decoder enable"]
+    #[inline]
+    pub fn uciren(&self) -> UCIRENR {
+        UCIRENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - IrDA transmit pulse clock select"]
+    #[inline]
+    pub fn ucirtxclk(&self) -> UCIRTXCLKR {
+        UCIRTXCLKR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 2:7 - Transmit pulse length"]
+    #[inline]
+    pub fn ucirtxpl(&self) -> UCIRTXPLR {
+        let bits = {
+            const MASK: u8 = 63;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCIRTXPLR { bits }
+    }
+    #[doc = "Bit 8 - IrDA receive filter enabled"]
+    #[inline]
+    pub fn ucirrxfe(&self) -> UCIRRXFER {
+        UCIRRXFER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 9 - IrDA receive input UCAxRXD polarity"]
+    #[inline]
+    pub fn ucirrxpl(&self) -> UCIRRXPLR {
+        UCIRRXPLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 10:13 - Receive filter length"]
+    #[inline]
+    pub fn ucirrxfl(&self) -> UCIRRXFLR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCIRRXFLR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - IrDA encoder/decoder enable"]
+    #[inline]
+    pub fn uciren(&mut self) -> _UCIRENW {
+        _UCIRENW { w: self }
+    }
+    #[doc = "Bit 1 - IrDA transmit pulse clock select"]
+    #[inline]
+    pub fn ucirtxclk(&mut self) -> _UCIRTXCLKW {
+        _UCIRTXCLKW { w: self }
+    }
+    #[doc = "Bits 2:7 - Transmit pulse length"]
+    #[inline]
+    pub fn ucirtxpl(&mut self) -> _UCIRTXPLW {
+        _UCIRTXPLW { w: self }
+    }
+    #[doc = "Bit 8 - IrDA receive filter enabled"]
+    #[inline]
+    pub fn ucirrxfe(&mut self) -> _UCIRRXFEW {
+        _UCIRRXFEW { w: self }
+    }
+    #[doc = "Bit 9 - IrDA receive input UCAxRXD polarity"]
+    #[inline]
+    pub fn ucirrxpl(&mut self) -> _UCIRRXPLW {
+        _UCIRRXPLW { w: self }
+    }
+    #[doc = "Bits 10:13 - Receive filter length"]
+    #[inline]
+    pub fn ucirrxfl(&mut self) -> _UCIRRXFLW {
+        _UCIRRXFLW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a0/ucax_iv.rs b/example-source/msp432p401r/src/eusci_a0/ucax_iv.rs
new file mode 100644
index 0000000..9f6d12c
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a0/ucax_iv.rs
@@ -0,0 +1,97 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::UCAXIV {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `UCIV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCIVR {
+    #[doc = "No interrupt pending"]
+    UCIV_0,
+    #[doc = "Interrupt Source: Receive buffer full; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest"]
+    UCIV_2,
+    #[doc = "Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG"]
+    UCIV_4,
+    #[doc = "Interrupt Source: Start bit received; Interrupt Flag: UCSTTIFG"]
+    UCIV_6,
+    #[doc = "Interrupt Source: Transmit complete; Interrupt Flag: UCTXCPTIFG; Interrupt Priority: Lowest"]
+    UCIV_8,
+    #[doc = r" Reserved"]
+    _Reserved(u16),
+}
+impl UCIVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        match *self {
+            UCIVR::UCIV_0 => 0,
+            UCIVR::UCIV_2 => 2,
+            UCIVR::UCIV_4 => 4,
+            UCIVR::UCIV_6 => 6,
+            UCIVR::UCIV_8 => 8,
+            UCIVR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u16) -> UCIVR {
+        match value {
+            0 => UCIVR::UCIV_0,
+            2 => UCIVR::UCIV_2,
+            4 => UCIVR::UCIV_4,
+            6 => UCIVR::UCIV_6,
+            8 => UCIVR::UCIV_8,
+            i => UCIVR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCIV_0`"]
+    #[inline]
+    pub fn is_uciv_0(&self) -> bool {
+        *self == UCIVR::UCIV_0
+    }
+    #[doc = "Checks if the value of the field is `UCIV_2`"]
+    #[inline]
+    pub fn is_uciv_2(&self) -> bool {
+        *self == UCIVR::UCIV_2
+    }
+    #[doc = "Checks if the value of the field is `UCIV_4`"]
+    #[inline]
+    pub fn is_uciv_4(&self) -> bool {
+        *self == UCIVR::UCIV_4
+    }
+    #[doc = "Checks if the value of the field is `UCIV_6`"]
+    #[inline]
+    pub fn is_uciv_6(&self) -> bool {
+        *self == UCIVR::UCIV_6
+    }
+    #[doc = "Checks if the value of the field is `UCIV_8`"]
+    #[inline]
+    pub fn is_uciv_8(&self) -> bool {
+        *self == UCIVR::UCIV_8
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - eUSCI_A interrupt vector value"]
+    #[inline]
+    pub fn uciv(&self) -> UCIVR {
+        UCIVR::_from({
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a0/ucax_mctlw.rs b/example-source/msp432p401r/src/eusci_a0/ucax_mctlw.rs
new file mode 100644
index 0000000..aebce19
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a0/ucax_mctlw.rs
@@ -0,0 +1,265 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXMCTLW {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCOS16`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCOS16R {
+    #[doc = "Disabled"]
+    UCOS16_0,
+    #[doc = "Enabled"]
+    UCOS16_1,
+}
+impl UCOS16R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCOS16R::UCOS16_0 => false,
+            UCOS16R::UCOS16_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCOS16R {
+        match value {
+            false => UCOS16R::UCOS16_0,
+            true => UCOS16R::UCOS16_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCOS16_0`"]
+    #[inline]
+    pub fn is_ucos16_0(&self) -> bool {
+        *self == UCOS16R::UCOS16_0
+    }
+    #[doc = "Checks if the value of the field is `UCOS16_1`"]
+    #[inline]
+    pub fn is_ucos16_1(&self) -> bool {
+        *self == UCOS16R::UCOS16_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCBRFR {
+    bits: u8,
+}
+impl UCBRFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCBRSR {
+    bits: u8,
+}
+impl UCBRSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Values that can be written to the field `UCOS16`"]
+pub enum UCOS16W {
+    #[doc = "Disabled"]
+    UCOS16_0,
+    #[doc = "Enabled"]
+    UCOS16_1,
+}
+impl UCOS16W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCOS16W::UCOS16_0 => false,
+            UCOS16W::UCOS16_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCOS16W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCOS16W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCOS16W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disabled"]
+    #[inline]
+    pub fn ucos16_0(self) -> &'a mut W {
+        self.variant(UCOS16W::UCOS16_0)
+    }
+    #[doc = "Enabled"]
+    #[inline]
+    pub fn ucos16_1(self) -> &'a mut W {
+        self.variant(UCOS16W::UCOS16_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBRFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBRFW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBRSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBRSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Oversampling mode enabled"]
+    #[inline]
+    pub fn ucos16(&self) -> UCOS16R {
+        UCOS16R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 4:7 - First modulation stage select"]
+    #[inline]
+    pub fn ucbrf(&self) -> UCBRFR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCBRFR { bits }
+    }
+    #[doc = "Bits 8:15 - Second modulation stage select"]
+    #[inline]
+    pub fn ucbrs(&self) -> UCBRSR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCBRSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Oversampling mode enabled"]
+    #[inline]
+    pub fn ucos16(&mut self) -> _UCOS16W {
+        _UCOS16W { w: self }
+    }
+    #[doc = "Bits 4:7 - First modulation stage select"]
+    #[inline]
+    pub fn ucbrf(&mut self) -> _UCBRFW {
+        _UCBRFW { w: self }
+    }
+    #[doc = "Bits 8:15 - Second modulation stage select"]
+    #[inline]
+    pub fn ucbrs(&mut self) -> _UCBRSW {
+        _UCBRSW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a0/ucax_rxbuf.rs b/example-source/msp432p401r/src/eusci_a0/ucax_rxbuf.rs
new file mode 100644
index 0000000..d13ee75
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a0/ucax_rxbuf.rs
@@ -0,0 +1,41 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::UCAXRXBUF {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCRXBUFR {
+    bits: u8,
+}
+impl UCRXBUFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Receive data buffer"]
+    #[inline]
+    pub fn ucrxbuf(&self) -> UCRXBUFR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCRXBUFR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a0/ucax_statw.rs b/example-source/msp432p401r/src/eusci_a0/ucax_statw.rs
new file mode 100644
index 0000000..8992e75
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a0/ucax_statw.rs
@@ -0,0 +1,893 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXSTATW {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCBUSY`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBUSYR {
+    #[doc = "eUSCI_A inactive"]
+    UCBUSY_0,
+    #[doc = "eUSCI_A transmitting or receiving"]
+    UCBUSY_1,
+}
+impl UCBUSYR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBUSYR::UCBUSY_0 => false,
+            UCBUSYR::UCBUSY_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBUSYR {
+        match value {
+            false => UCBUSYR::UCBUSY_0,
+            true => UCBUSYR::UCBUSY_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBUSY_0`"]
+    #[inline]
+    pub fn is_ucbusy_0(&self) -> bool {
+        *self == UCBUSYR::UCBUSY_0
+    }
+    #[doc = "Checks if the value of the field is `UCBUSY_1`"]
+    #[inline]
+    pub fn is_ucbusy_1(&self) -> bool {
+        *self == UCBUSYR::UCBUSY_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCADDR_UCIDLER {
+    bits: bool,
+}
+impl UCADDR_UCIDLER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `UCRXERR`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXERRR {
+    #[doc = "No receive errors detected"]
+    UCRXERR_0,
+    #[doc = "Receive error detected"]
+    UCRXERR_1,
+}
+impl UCRXERRR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXERRR::UCRXERR_0 => false,
+            UCRXERRR::UCRXERR_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXERRR {
+        match value {
+            false => UCRXERRR::UCRXERR_0,
+            true => UCRXERRR::UCRXERR_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXERR_0`"]
+    #[inline]
+    pub fn is_ucrxerr_0(&self) -> bool {
+        *self == UCRXERRR::UCRXERR_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXERR_1`"]
+    #[inline]
+    pub fn is_ucrxerr_1(&self) -> bool {
+        *self == UCRXERRR::UCRXERR_1
+    }
+}
+#[doc = "Possible values of the field `UCBRK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBRKR {
+    #[doc = "No break condition"]
+    UCBRK_0,
+    #[doc = "Break condition occurred"]
+    UCBRK_1,
+}
+impl UCBRKR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBRKR::UCBRK_0 => false,
+            UCBRKR::UCBRK_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBRKR {
+        match value {
+            false => UCBRKR::UCBRK_0,
+            true => UCBRKR::UCBRK_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBRK_0`"]
+    #[inline]
+    pub fn is_ucbrk_0(&self) -> bool {
+        *self == UCBRKR::UCBRK_0
+    }
+    #[doc = "Checks if the value of the field is `UCBRK_1`"]
+    #[inline]
+    pub fn is_ucbrk_1(&self) -> bool {
+        *self == UCBRKR::UCBRK_1
+    }
+}
+#[doc = "Possible values of the field `UCPE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCPER {
+    #[doc = "No error"]
+    UCPE_0,
+    #[doc = "Character received with parity error"]
+    UCPE_1,
+}
+impl UCPER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCPER::UCPE_0 => false,
+            UCPER::UCPE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCPER {
+        match value {
+            false => UCPER::UCPE_0,
+            true => UCPER::UCPE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCPE_0`"]
+    #[inline]
+    pub fn is_ucpe_0(&self) -> bool {
+        *self == UCPER::UCPE_0
+    }
+    #[doc = "Checks if the value of the field is `UCPE_1`"]
+    #[inline]
+    pub fn is_ucpe_1(&self) -> bool {
+        *self == UCPER::UCPE_1
+    }
+}
+#[doc = "Possible values of the field `UCOE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCOER {
+    #[doc = "No error"]
+    UCOE_0,
+    #[doc = "Overrun error occurred"]
+    UCOE_1,
+}
+impl UCOER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCOER::UCOE_0 => false,
+            UCOER::UCOE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCOER {
+        match value {
+            false => UCOER::UCOE_0,
+            true => UCOER::UCOE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCOE_0`"]
+    #[inline]
+    pub fn is_ucoe_0(&self) -> bool {
+        *self == UCOER::UCOE_0
+    }
+    #[doc = "Checks if the value of the field is `UCOE_1`"]
+    #[inline]
+    pub fn is_ucoe_1(&self) -> bool {
+        *self == UCOER::UCOE_1
+    }
+}
+#[doc = "Possible values of the field `UCFE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCFER {
+    #[doc = "No error"]
+    UCFE_0,
+    #[doc = "Character received with low stop bit"]
+    UCFE_1,
+}
+impl UCFER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCFER::UCFE_0 => false,
+            UCFER::UCFE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCFER {
+        match value {
+            false => UCFER::UCFE_0,
+            true => UCFER::UCFE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCFE_0`"]
+    #[inline]
+    pub fn is_ucfe_0(&self) -> bool {
+        *self == UCFER::UCFE_0
+    }
+    #[doc = "Checks if the value of the field is `UCFE_1`"]
+    #[inline]
+    pub fn is_ucfe_1(&self) -> bool {
+        *self == UCFER::UCFE_1
+    }
+}
+#[doc = "Possible values of the field `UCLISTEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCLISTENR {
+    #[doc = "Disabled"]
+    UCLISTEN_0,
+    #[doc = "Enabled. UCAxTXD is internally fed back to the receiver"]
+    UCLISTEN_1,
+}
+impl UCLISTENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCLISTENR::UCLISTEN_0 => false,
+            UCLISTENR::UCLISTEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCLISTENR {
+        match value {
+            false => UCLISTENR::UCLISTEN_0,
+            true => UCLISTENR::UCLISTEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCLISTEN_0`"]
+    #[inline]
+    pub fn is_uclisten_0(&self) -> bool {
+        *self == UCLISTENR::UCLISTEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCLISTEN_1`"]
+    #[inline]
+    pub fn is_uclisten_1(&self) -> bool {
+        *self == UCLISTENR::UCLISTEN_1
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCADDR_UCIDLEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCADDR_UCIDLEW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXERR`"]
+pub enum UCRXERRW {
+    #[doc = "No receive errors detected"]
+    UCRXERR_0,
+    #[doc = "Receive error detected"]
+    UCRXERR_1,
+}
+impl UCRXERRW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXERRW::UCRXERR_0 => false,
+            UCRXERRW::UCRXERR_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXERRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXERRW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXERRW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No receive errors detected"]
+    #[inline]
+    pub fn ucrxerr_0(self) -> &'a mut W {
+        self.variant(UCRXERRW::UCRXERR_0)
+    }
+    #[doc = "Receive error detected"]
+    #[inline]
+    pub fn ucrxerr_1(self) -> &'a mut W {
+        self.variant(UCRXERRW::UCRXERR_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCBRK`"]
+pub enum UCBRKW {
+    #[doc = "No break condition"]
+    UCBRK_0,
+    #[doc = "Break condition occurred"]
+    UCBRK_1,
+}
+impl UCBRKW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCBRKW::UCBRK_0 => false,
+            UCBRKW::UCBRK_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBRKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBRKW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCBRKW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No break condition"]
+    #[inline]
+    pub fn ucbrk_0(self) -> &'a mut W {
+        self.variant(UCBRKW::UCBRK_0)
+    }
+    #[doc = "Break condition occurred"]
+    #[inline]
+    pub fn ucbrk_1(self) -> &'a mut W {
+        self.variant(UCBRKW::UCBRK_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCPE`"]
+pub enum UCPEW {
+    #[doc = "No error"]
+    UCPE_0,
+    #[doc = "Character received with parity error"]
+    UCPE_1,
+}
+impl UCPEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCPEW::UCPE_0 => false,
+            UCPEW::UCPE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCPEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCPEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCPEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No error"]
+    #[inline]
+    pub fn ucpe_0(self) -> &'a mut W {
+        self.variant(UCPEW::UCPE_0)
+    }
+    #[doc = "Character received with parity error"]
+    #[inline]
+    pub fn ucpe_1(self) -> &'a mut W {
+        self.variant(UCPEW::UCPE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCOE`"]
+pub enum UCOEW {
+    #[doc = "No error"]
+    UCOE_0,
+    #[doc = "Overrun error occurred"]
+    UCOE_1,
+}
+impl UCOEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCOEW::UCOE_0 => false,
+            UCOEW::UCOE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCOEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCOEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCOEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No error"]
+    #[inline]
+    pub fn ucoe_0(self) -> &'a mut W {
+        self.variant(UCOEW::UCOE_0)
+    }
+    #[doc = "Overrun error occurred"]
+    #[inline]
+    pub fn ucoe_1(self) -> &'a mut W {
+        self.variant(UCOEW::UCOE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCFE`"]
+pub enum UCFEW {
+    #[doc = "No error"]
+    UCFE_0,
+    #[doc = "Character received with low stop bit"]
+    UCFE_1,
+}
+impl UCFEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCFEW::UCFE_0 => false,
+            UCFEW::UCFE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCFEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCFEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCFEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No error"]
+    #[inline]
+    pub fn ucfe_0(self) -> &'a mut W {
+        self.variant(UCFEW::UCFE_0)
+    }
+    #[doc = "Character received with low stop bit"]
+    #[inline]
+    pub fn ucfe_1(self) -> &'a mut W {
+        self.variant(UCFEW::UCFE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCLISTEN`"]
+pub enum UCLISTENW {
+    #[doc = "Disabled"]
+    UCLISTEN_0,
+    #[doc = "Enabled. UCAxTXD is internally fed back to the receiver"]
+    UCLISTEN_1,
+}
+impl UCLISTENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCLISTENW::UCLISTEN_0 => false,
+            UCLISTENW::UCLISTEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCLISTENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCLISTENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCLISTENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disabled"]
+    #[inline]
+    pub fn uclisten_0(self) -> &'a mut W {
+        self.variant(UCLISTENW::UCLISTEN_0)
+    }
+    #[doc = "Enabled. UCAxTXD is internally fed back to the receiver"]
+    #[inline]
+    pub fn uclisten_1(self) -> &'a mut W {
+        self.variant(UCLISTENW::UCLISTEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - eUSCI_A busy"]
+    #[inline]
+    pub fn ucbusy(&self) -> UCBUSYR {
+        UCBUSYR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Address received / Idle line detected"]
+    #[inline]
+    pub fn ucaddr_ucidle(&self) -> UCADDR_UCIDLER {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        };
+        UCADDR_UCIDLER { bits }
+    }
+    #[doc = "Bit 2 - Receive error flag"]
+    #[inline]
+    pub fn ucrxerr(&self) -> UCRXERRR {
+        UCRXERRR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Break detect flag"]
+    #[inline]
+    pub fn ucbrk(&self) -> UCBRKR {
+        UCBRKR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 4 - Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read."]
+    #[inline]
+    pub fn ucpe(&self) -> UCPER {
+        UCPER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - Overrun error flag"]
+    #[inline]
+    pub fn ucoe(&self) -> UCOER {
+        UCOER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 6 - Framing error flag"]
+    #[inline]
+    pub fn ucfe(&self) -> UCFER {
+        UCFER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 7 - Listen enable"]
+    #[inline]
+    pub fn uclisten(&self) -> UCLISTENR {
+        UCLISTENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 1 - Address received / Idle line detected"]
+    #[inline]
+    pub fn ucaddr_ucidle(&mut self) -> _UCADDR_UCIDLEW {
+        _UCADDR_UCIDLEW { w: self }
+    }
+    #[doc = "Bit 2 - Receive error flag"]
+    #[inline]
+    pub fn ucrxerr(&mut self) -> _UCRXERRW {
+        _UCRXERRW { w: self }
+    }
+    #[doc = "Bit 3 - Break detect flag"]
+    #[inline]
+    pub fn ucbrk(&mut self) -> _UCBRKW {
+        _UCBRKW { w: self }
+    }
+    #[doc = "Bit 4 - Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read."]
+    #[inline]
+    pub fn ucpe(&mut self) -> _UCPEW {
+        _UCPEW { w: self }
+    }
+    #[doc = "Bit 5 - Overrun error flag"]
+    #[inline]
+    pub fn ucoe(&mut self) -> _UCOEW {
+        _UCOEW { w: self }
+    }
+    #[doc = "Bit 6 - Framing error flag"]
+    #[inline]
+    pub fn ucfe(&mut self) -> _UCFEW {
+        _UCFEW { w: self }
+    }
+    #[doc = "Bit 7 - Listen enable"]
+    #[inline]
+    pub fn uclisten(&mut self) -> _UCLISTENW {
+        _UCLISTENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a0/ucax_txbuf.rs b/example-source/msp432p401r/src/eusci_a0/ucax_txbuf.rs
new file mode 100644
index 0000000..47ca264
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a0/ucax_txbuf.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXTXBUF {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCTXBUFR {
+    bits: u8,
+}
+impl UCTXBUFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXBUFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXBUFW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Transmit data buffer"]
+    #[inline]
+    pub fn uctxbuf(&self) -> UCTXBUFR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCTXBUFR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Transmit data buffer"]
+    #[inline]
+    pub fn uctxbuf(&mut self) -> _UCTXBUFW {
+        _UCTXBUFW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a1.rs b/example-source/msp432p401r/src/eusci_a1.rs
new file mode 100644
index 0000000..88b0e5e
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a1.rs
@@ -0,0 +1,102 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - eUSCI_Ax Control Word Register 0"]
+    pub ucax_ctlw0: UCAXCTLW0,
+    #[doc = "0x02 - eUSCI_Ax Control Word Register 1"]
+    pub ucax_ctlw1: UCAXCTLW1,
+    _reserved0: [u8; 2usize],
+    #[doc = "0x06 - eUSCI_Ax Baud Rate Control Word Register"]
+    pub ucax_brw: UCAXBRW,
+    #[doc = "0x08 - eUSCI_Ax Modulation Control Word Register"]
+    pub ucax_mctlw: UCAXMCTLW,
+    #[doc = "0x0a - eUSCI_Ax Status Register"]
+    pub ucax_statw: UCAXSTATW,
+    #[doc = "0x0c - eUSCI_Ax Receive Buffer Register"]
+    pub ucax_rxbuf: UCAXRXBUF,
+    #[doc = "0x0e - eUSCI_Ax Transmit Buffer Register"]
+    pub ucax_txbuf: UCAXTXBUF,
+    #[doc = "0x10 - eUSCI_Ax Auto Baud Rate Control Register"]
+    pub ucax_abctl: UCAXABCTL,
+    #[doc = "0x12 - eUSCI_Ax IrDA Control Word Register"]
+    pub ucax_irctl: UCAXIRCTL,
+    _reserved1: [u8; 6usize],
+    #[doc = "0x1a - eUSCI_Ax Interrupt Enable Register"]
+    pub ucax_ie: UCAXIE,
+    #[doc = "0x1c - eUSCI_Ax Interrupt Flag Register"]
+    pub ucax_ifg: UCAXIFG,
+    #[doc = "0x1e - eUSCI_Ax Interrupt Vector Register"]
+    pub ucax_iv: UCAXIV,
+}
+#[doc = "eUSCI_Ax Control Word Register 0"]
+pub struct UCAXCTLW0 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Control Word Register 0"]
+pub mod ucax_ctlw0;
+#[doc = "eUSCI_Ax Control Word Register 1"]
+pub struct UCAXCTLW1 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Control Word Register 1"]
+pub mod ucax_ctlw1;
+#[doc = "eUSCI_Ax Baud Rate Control Word Register"]
+pub struct UCAXBRW {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Baud Rate Control Word Register"]
+pub mod ucax_brw;
+#[doc = "eUSCI_Ax Modulation Control Word Register"]
+pub struct UCAXMCTLW {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Modulation Control Word Register"]
+pub mod ucax_mctlw;
+#[doc = "eUSCI_Ax Status Register"]
+pub struct UCAXSTATW {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Status Register"]
+pub mod ucax_statw;
+#[doc = "eUSCI_Ax Receive Buffer Register"]
+pub struct UCAXRXBUF {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Receive Buffer Register"]
+pub mod ucax_rxbuf;
+#[doc = "eUSCI_Ax Transmit Buffer Register"]
+pub struct UCAXTXBUF {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Transmit Buffer Register"]
+pub mod ucax_txbuf;
+#[doc = "eUSCI_Ax Auto Baud Rate Control Register"]
+pub struct UCAXABCTL {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Auto Baud Rate Control Register"]
+pub mod ucax_abctl;
+#[doc = "eUSCI_Ax IrDA Control Word Register"]
+pub struct UCAXIRCTL {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax IrDA Control Word Register"]
+pub mod ucax_irctl;
+#[doc = "eUSCI_Ax Interrupt Enable Register"]
+pub struct UCAXIE {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Interrupt Enable Register"]
+pub mod ucax_ie;
+#[doc = "eUSCI_Ax Interrupt Flag Register"]
+pub struct UCAXIFG {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Interrupt Flag Register"]
+pub mod ucax_ifg;
+#[doc = "eUSCI_Ax Interrupt Vector Register"]
+pub struct UCAXIV {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Interrupt Vector Register"]
+pub mod ucax_iv;
diff --git a/example-source/msp432p401r/src/eusci_a1/ucax_abctl.rs b/example-source/msp432p401r/src/eusci_a1/ucax_abctl.rs
new file mode 100644
index 0000000..ce574eb
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a1/ucax_abctl.rs
@@ -0,0 +1,557 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXABCTL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCABDEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCABDENR {
+    #[doc = "Baud-rate detection disabled. Length of break and synch field is not measured."]
+    UCABDEN_0,
+    #[doc = "Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly."]
+    UCABDEN_1,
+}
+impl UCABDENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCABDENR::UCABDEN_0 => false,
+            UCABDENR::UCABDEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCABDENR {
+        match value {
+            false => UCABDENR::UCABDEN_0,
+            true => UCABDENR::UCABDEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCABDEN_0`"]
+    #[inline]
+    pub fn is_ucabden_0(&self) -> bool {
+        *self == UCABDENR::UCABDEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCABDEN_1`"]
+    #[inline]
+    pub fn is_ucabden_1(&self) -> bool {
+        *self == UCABDENR::UCABDEN_1
+    }
+}
+#[doc = "Possible values of the field `UCBTOE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBTOER {
+    #[doc = "No error"]
+    UCBTOE_0,
+    #[doc = "Length of break field exceeded 22 bit times"]
+    UCBTOE_1,
+}
+impl UCBTOER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBTOER::UCBTOE_0 => false,
+            UCBTOER::UCBTOE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBTOER {
+        match value {
+            false => UCBTOER::UCBTOE_0,
+            true => UCBTOER::UCBTOE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBTOE_0`"]
+    #[inline]
+    pub fn is_ucbtoe_0(&self) -> bool {
+        *self == UCBTOER::UCBTOE_0
+    }
+    #[doc = "Checks if the value of the field is `UCBTOE_1`"]
+    #[inline]
+    pub fn is_ucbtoe_1(&self) -> bool {
+        *self == UCBTOER::UCBTOE_1
+    }
+}
+#[doc = "Possible values of the field `UCSTOE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTOER {
+    #[doc = "No error"]
+    UCSTOE_0,
+    #[doc = "Length of synch field exceeded measurable time"]
+    UCSTOE_1,
+}
+impl UCSTOER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTOER::UCSTOE_0 => false,
+            UCSTOER::UCSTOE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTOER {
+        match value {
+            false => UCSTOER::UCSTOE_0,
+            true => UCSTOER::UCSTOE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTOE_0`"]
+    #[inline]
+    pub fn is_ucstoe_0(&self) -> bool {
+        *self == UCSTOER::UCSTOE_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTOE_1`"]
+    #[inline]
+    pub fn is_ucstoe_1(&self) -> bool {
+        *self == UCSTOER::UCSTOE_1
+    }
+}
+#[doc = "Possible values of the field `UCDELIM`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCDELIMR {
+    #[doc = "1 bit time"]
+    UCDELIM_0,
+    #[doc = "2 bit times"]
+    UCDELIM_1,
+    #[doc = "3 bit times"]
+    UCDELIM_2,
+    #[doc = "4 bit times"]
+    UCDELIM_3,
+}
+impl UCDELIMR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCDELIMR::UCDELIM_0 => 0,
+            UCDELIMR::UCDELIM_1 => 1,
+            UCDELIMR::UCDELIM_2 => 2,
+            UCDELIMR::UCDELIM_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCDELIMR {
+        match value {
+            0 => UCDELIMR::UCDELIM_0,
+            1 => UCDELIMR::UCDELIM_1,
+            2 => UCDELIMR::UCDELIM_2,
+            3 => UCDELIMR::UCDELIM_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCDELIM_0`"]
+    #[inline]
+    pub fn is_ucdelim_0(&self) -> bool {
+        *self == UCDELIMR::UCDELIM_0
+    }
+    #[doc = "Checks if the value of the field is `UCDELIM_1`"]
+    #[inline]
+    pub fn is_ucdelim_1(&self) -> bool {
+        *self == UCDELIMR::UCDELIM_1
+    }
+    #[doc = "Checks if the value of the field is `UCDELIM_2`"]
+    #[inline]
+    pub fn is_ucdelim_2(&self) -> bool {
+        *self == UCDELIMR::UCDELIM_2
+    }
+    #[doc = "Checks if the value of the field is `UCDELIM_3`"]
+    #[inline]
+    pub fn is_ucdelim_3(&self) -> bool {
+        *self == UCDELIMR::UCDELIM_3
+    }
+}
+#[doc = "Values that can be written to the field `UCABDEN`"]
+pub enum UCABDENW {
+    #[doc = "Baud-rate detection disabled. Length of break and synch field is not measured."]
+    UCABDEN_0,
+    #[doc = "Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly."]
+    UCABDEN_1,
+}
+impl UCABDENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCABDENW::UCABDEN_0 => false,
+            UCABDENW::UCABDEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCABDENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCABDENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCABDENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Baud-rate detection disabled. Length of break and synch field is not measured."]
+    #[inline]
+    pub fn ucabden_0(self) -> &'a mut W {
+        self.variant(UCABDENW::UCABDEN_0)
+    }
+    #[doc = "Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly."]
+    #[inline]
+    pub fn ucabden_1(self) -> &'a mut W {
+        self.variant(UCABDENW::UCABDEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCBTOE`"]
+pub enum UCBTOEW {
+    #[doc = "No error"]
+    UCBTOE_0,
+    #[doc = "Length of break field exceeded 22 bit times"]
+    UCBTOE_1,
+}
+impl UCBTOEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCBTOEW::UCBTOE_0 => false,
+            UCBTOEW::UCBTOE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBTOEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBTOEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCBTOEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No error"]
+    #[inline]
+    pub fn ucbtoe_0(self) -> &'a mut W {
+        self.variant(UCBTOEW::UCBTOE_0)
+    }
+    #[doc = "Length of break field exceeded 22 bit times"]
+    #[inline]
+    pub fn ucbtoe_1(self) -> &'a mut W {
+        self.variant(UCBTOEW::UCBTOE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTOE`"]
+pub enum UCSTOEW {
+    #[doc = "No error"]
+    UCSTOE_0,
+    #[doc = "Length of synch field exceeded measurable time"]
+    UCSTOE_1,
+}
+impl UCSTOEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTOEW::UCSTOE_0 => false,
+            UCSTOEW::UCSTOE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTOEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTOEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTOEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No error"]
+    #[inline]
+    pub fn ucstoe_0(self) -> &'a mut W {
+        self.variant(UCSTOEW::UCSTOE_0)
+    }
+    #[doc = "Length of synch field exceeded measurable time"]
+    #[inline]
+    pub fn ucstoe_1(self) -> &'a mut W {
+        self.variant(UCSTOEW::UCSTOE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCDELIM`"]
+pub enum UCDELIMW {
+    #[doc = "1 bit time"]
+    UCDELIM_0,
+    #[doc = "2 bit times"]
+    UCDELIM_1,
+    #[doc = "3 bit times"]
+    UCDELIM_2,
+    #[doc = "4 bit times"]
+    UCDELIM_3,
+}
+impl UCDELIMW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCDELIMW::UCDELIM_0 => 0,
+            UCDELIMW::UCDELIM_1 => 1,
+            UCDELIMW::UCDELIM_2 => 2,
+            UCDELIMW::UCDELIM_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCDELIMW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCDELIMW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCDELIMW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "1 bit time"]
+    #[inline]
+    pub fn ucdelim_0(self) -> &'a mut W {
+        self.variant(UCDELIMW::UCDELIM_0)
+    }
+    #[doc = "2 bit times"]
+    #[inline]
+    pub fn ucdelim_1(self) -> &'a mut W {
+        self.variant(UCDELIMW::UCDELIM_1)
+    }
+    #[doc = "3 bit times"]
+    #[inline]
+    pub fn ucdelim_2(self) -> &'a mut W {
+        self.variant(UCDELIMW::UCDELIM_2)
+    }
+    #[doc = "4 bit times"]
+    #[inline]
+    pub fn ucdelim_3(self) -> &'a mut W {
+        self.variant(UCDELIMW::UCDELIM_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Automatic baud-rate detect enable"]
+    #[inline]
+    pub fn ucabden(&self) -> UCABDENR {
+        UCABDENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - Break time out error"]
+    #[inline]
+    pub fn ucbtoe(&self) -> UCBTOER {
+        UCBTOER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Synch field time out error"]
+    #[inline]
+    pub fn ucstoe(&self) -> UCSTOER {
+        UCSTOER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 4:5 - Break/synch delimiter length"]
+    #[inline]
+    pub fn ucdelim(&self) -> UCDELIMR {
+        UCDELIMR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Automatic baud-rate detect enable"]
+    #[inline]
+    pub fn ucabden(&mut self) -> _UCABDENW {
+        _UCABDENW { w: self }
+    }
+    #[doc = "Bit 2 - Break time out error"]
+    #[inline]
+    pub fn ucbtoe(&mut self) -> _UCBTOEW {
+        _UCBTOEW { w: self }
+    }
+    #[doc = "Bit 3 - Synch field time out error"]
+    #[inline]
+    pub fn ucstoe(&mut self) -> _UCSTOEW {
+        _UCSTOEW { w: self }
+    }
+    #[doc = "Bits 4:5 - Break/synch delimiter length"]
+    #[inline]
+    pub fn ucdelim(&mut self) -> _UCDELIMW {
+        _UCDELIMW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a1/ucax_brw.rs b/example-source/msp432p401r/src/eusci_a1/ucax_brw.rs
new file mode 100644
index 0000000..c9b1b2a
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a1/ucax_brw.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXBRW {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCBRR {
+    bits: u16,
+}
+impl UCBRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBRW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Clock prescaler setting of the Baud rate generator"]
+    #[inline]
+    pub fn ucbr(&self) -> UCBRR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        UCBRR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Clock prescaler setting of the Baud rate generator"]
+    #[inline]
+    pub fn ucbr(&mut self) -> _UCBRW {
+        _UCBRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a1/ucax_ctlw0.rs b/example-source/msp432p401r/src/eusci_a1/ucax_ctlw0.rs
new file mode 100644
index 0000000..aa44348
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a1/ucax_ctlw0.rs
@@ -0,0 +1,1748 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXCTLW0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCSWRST`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSWRSTR {
+    #[doc = "Disabled. eUSCI_A reset released for operation"]
+    UCSWRST_0,
+    #[doc = "Enabled. eUSCI_A logic held in reset state"]
+    UCSWRST_1,
+}
+impl UCSWRSTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSWRSTR::UCSWRST_0 => false,
+            UCSWRSTR::UCSWRST_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSWRSTR {
+        match value {
+            false => UCSWRSTR::UCSWRST_0,
+            true => UCSWRSTR::UCSWRST_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSWRST_0`"]
+    #[inline]
+    pub fn is_ucswrst_0(&self) -> bool {
+        *self == UCSWRSTR::UCSWRST_0
+    }
+    #[doc = "Checks if the value of the field is `UCSWRST_1`"]
+    #[inline]
+    pub fn is_ucswrst_1(&self) -> bool {
+        *self == UCSWRSTR::UCSWRST_1
+    }
+}
+#[doc = "Possible values of the field `UCTXBRK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXBRKR {
+    #[doc = "Next frame transmitted is not a break"]
+    UCTXBRK_0,
+    #[doc = "Next frame transmitted is a break or a break/synch"]
+    UCTXBRK_1,
+}
+impl UCTXBRKR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXBRKR::UCTXBRK_0 => false,
+            UCTXBRKR::UCTXBRK_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXBRKR {
+        match value {
+            false => UCTXBRKR::UCTXBRK_0,
+            true => UCTXBRKR::UCTXBRK_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXBRK_0`"]
+    #[inline]
+    pub fn is_uctxbrk_0(&self) -> bool {
+        *self == UCTXBRKR::UCTXBRK_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXBRK_1`"]
+    #[inline]
+    pub fn is_uctxbrk_1(&self) -> bool {
+        *self == UCTXBRKR::UCTXBRK_1
+    }
+}
+#[doc = "Possible values of the field `UCTXADDR`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXADDRR {
+    #[doc = "Next frame transmitted is data"]
+    UCTXADDR_0,
+    #[doc = "Next frame transmitted is an address"]
+    UCTXADDR_1,
+}
+impl UCTXADDRR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXADDRR::UCTXADDR_0 => false,
+            UCTXADDRR::UCTXADDR_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXADDRR {
+        match value {
+            false => UCTXADDRR::UCTXADDR_0,
+            true => UCTXADDRR::UCTXADDR_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXADDR_0`"]
+    #[inline]
+    pub fn is_uctxaddr_0(&self) -> bool {
+        *self == UCTXADDRR::UCTXADDR_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXADDR_1`"]
+    #[inline]
+    pub fn is_uctxaddr_1(&self) -> bool {
+        *self == UCTXADDRR::UCTXADDR_1
+    }
+}
+#[doc = "Possible values of the field `UCDORM`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCDORMR {
+    #[doc = "Not dormant. All received characters set UCRXIFG."]
+    UCDORM_0,
+    #[doc = "Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG."]
+    UCDORM_1,
+}
+impl UCDORMR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCDORMR::UCDORM_0 => false,
+            UCDORMR::UCDORM_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCDORMR {
+        match value {
+            false => UCDORMR::UCDORM_0,
+            true => UCDORMR::UCDORM_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCDORM_0`"]
+    #[inline]
+    pub fn is_ucdorm_0(&self) -> bool {
+        *self == UCDORMR::UCDORM_0
+    }
+    #[doc = "Checks if the value of the field is `UCDORM_1`"]
+    #[inline]
+    pub fn is_ucdorm_1(&self) -> bool {
+        *self == UCDORMR::UCDORM_1
+    }
+}
+#[doc = "Possible values of the field `UCBRKIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBRKIER {
+    #[doc = "Received break characters do not set UCRXIFG"]
+    UCBRKIE_0,
+    #[doc = "Received break characters set UCRXIFG"]
+    UCBRKIE_1,
+}
+impl UCBRKIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBRKIER::UCBRKIE_0 => false,
+            UCBRKIER::UCBRKIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBRKIER {
+        match value {
+            false => UCBRKIER::UCBRKIE_0,
+            true => UCBRKIER::UCBRKIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBRKIE_0`"]
+    #[inline]
+    pub fn is_ucbrkie_0(&self) -> bool {
+        *self == UCBRKIER::UCBRKIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCBRKIE_1`"]
+    #[inline]
+    pub fn is_ucbrkie_1(&self) -> bool {
+        *self == UCBRKIER::UCBRKIE_1
+    }
+}
+#[doc = "Possible values of the field `UCRXEIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXEIER {
+    #[doc = "Erroneous characters rejected and UCRXIFG is not set"]
+    UCRXEIE_0,
+    #[doc = "Erroneous characters received set UCRXIFG"]
+    UCRXEIE_1,
+}
+impl UCRXEIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXEIER::UCRXEIE_0 => false,
+            UCRXEIER::UCRXEIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXEIER {
+        match value {
+            false => UCRXEIER::UCRXEIE_0,
+            true => UCRXEIER::UCRXEIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXEIE_0`"]
+    #[inline]
+    pub fn is_ucrxeie_0(&self) -> bool {
+        *self == UCRXEIER::UCRXEIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXEIE_1`"]
+    #[inline]
+    pub fn is_ucrxeie_1(&self) -> bool {
+        *self == UCRXEIER::UCRXEIE_1
+    }
+}
+#[doc = "Possible values of the field `UCSSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSSELR {
+    #[doc = "UCLK"]
+    UCSSEL_0,
+    #[doc = "ACLK"]
+    UCSSEL_1,
+    #[doc = "SMCLK"]
+    UCSSEL_2,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl UCSSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCSSELR::UCSSEL_0 => 0,
+            UCSSELR::UCSSEL_1 => 1,
+            UCSSELR::UCSSEL_2 => 2,
+            UCSSELR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCSSELR {
+        match value {
+            0 => UCSSELR::UCSSEL_0,
+            1 => UCSSELR::UCSSEL_1,
+            2 => UCSSELR::UCSSEL_2,
+            i => UCSSELR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSSEL_0`"]
+    #[inline]
+    pub fn is_ucssel_0(&self) -> bool {
+        *self == UCSSELR::UCSSEL_0
+    }
+    #[doc = "Checks if the value of the field is `UCSSEL_1`"]
+    #[inline]
+    pub fn is_ucssel_1(&self) -> bool {
+        *self == UCSSELR::UCSSEL_1
+    }
+    #[doc = "Checks if the value of the field is `UCSSEL_2`"]
+    #[inline]
+    pub fn is_ucssel_2(&self) -> bool {
+        *self == UCSSELR::UCSSEL_2
+    }
+}
+#[doc = "Possible values of the field `UCSYNC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSYNCR {
+    #[doc = "Asynchronous mode"]
+    UCSYNC_0,
+    #[doc = "Synchronous mode"]
+    UCSYNC_1,
+}
+impl UCSYNCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSYNCR::UCSYNC_0 => false,
+            UCSYNCR::UCSYNC_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSYNCR {
+        match value {
+            false => UCSYNCR::UCSYNC_0,
+            true => UCSYNCR::UCSYNC_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSYNC_0`"]
+    #[inline]
+    pub fn is_ucsync_0(&self) -> bool {
+        *self == UCSYNCR::UCSYNC_0
+    }
+    #[doc = "Checks if the value of the field is `UCSYNC_1`"]
+    #[inline]
+    pub fn is_ucsync_1(&self) -> bool {
+        *self == UCSYNCR::UCSYNC_1
+    }
+}
+#[doc = "Possible values of the field `UCMODE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCMODER {
+    #[doc = "UART mode"]
+    UCMODE_0,
+    #[doc = "Idle-line multiprocessor mode"]
+    UCMODE_1,
+    #[doc = "Address-bit multiprocessor mode"]
+    UCMODE_2,
+    #[doc = "UART mode with automatic baud-rate detection"]
+    UCMODE_3,
+}
+impl UCMODER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCMODER::UCMODE_0 => 0,
+            UCMODER::UCMODE_1 => 1,
+            UCMODER::UCMODE_2 => 2,
+            UCMODER::UCMODE_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCMODER {
+        match value {
+            0 => UCMODER::UCMODE_0,
+            1 => UCMODER::UCMODE_1,
+            2 => UCMODER::UCMODE_2,
+            3 => UCMODER::UCMODE_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_0`"]
+    #[inline]
+    pub fn is_ucmode_0(&self) -> bool {
+        *self == UCMODER::UCMODE_0
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_1`"]
+    #[inline]
+    pub fn is_ucmode_1(&self) -> bool {
+        *self == UCMODER::UCMODE_1
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_2`"]
+    #[inline]
+    pub fn is_ucmode_2(&self) -> bool {
+        *self == UCMODER::UCMODE_2
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_3`"]
+    #[inline]
+    pub fn is_ucmode_3(&self) -> bool {
+        *self == UCMODER::UCMODE_3
+    }
+}
+#[doc = "Possible values of the field `UCSPB`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSPBR {
+    #[doc = "One stop bit"]
+    UCSPB_0,
+    #[doc = "Two stop bits"]
+    UCSPB_1,
+}
+impl UCSPBR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSPBR::UCSPB_0 => false,
+            UCSPBR::UCSPB_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSPBR {
+        match value {
+            false => UCSPBR::UCSPB_0,
+            true => UCSPBR::UCSPB_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSPB_0`"]
+    #[inline]
+    pub fn is_ucspb_0(&self) -> bool {
+        *self == UCSPBR::UCSPB_0
+    }
+    #[doc = "Checks if the value of the field is `UCSPB_1`"]
+    #[inline]
+    pub fn is_ucspb_1(&self) -> bool {
+        *self == UCSPBR::UCSPB_1
+    }
+}
+#[doc = "Possible values of the field `UC7BIT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UC7BITR {
+    #[doc = "8-bit data"]
+    UC7BIT_0,
+    #[doc = "7-bit data"]
+    UC7BIT_1,
+}
+impl UC7BITR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UC7BITR::UC7BIT_0 => false,
+            UC7BITR::UC7BIT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UC7BITR {
+        match value {
+            false => UC7BITR::UC7BIT_0,
+            true => UC7BITR::UC7BIT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UC7BIT_0`"]
+    #[inline]
+    pub fn is_uc7bit_0(&self) -> bool {
+        *self == UC7BITR::UC7BIT_0
+    }
+    #[doc = "Checks if the value of the field is `UC7BIT_1`"]
+    #[inline]
+    pub fn is_uc7bit_1(&self) -> bool {
+        *self == UC7BITR::UC7BIT_1
+    }
+}
+#[doc = "Possible values of the field `UCMSB`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCMSBR {
+    #[doc = "LSB first"]
+    UCMSB_0,
+    #[doc = "MSB first"]
+    UCMSB_1,
+}
+impl UCMSBR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCMSBR::UCMSB_0 => false,
+            UCMSBR::UCMSB_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCMSBR {
+        match value {
+            false => UCMSBR::UCMSB_0,
+            true => UCMSBR::UCMSB_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCMSB_0`"]
+    #[inline]
+    pub fn is_ucmsb_0(&self) -> bool {
+        *self == UCMSBR::UCMSB_0
+    }
+    #[doc = "Checks if the value of the field is `UCMSB_1`"]
+    #[inline]
+    pub fn is_ucmsb_1(&self) -> bool {
+        *self == UCMSBR::UCMSB_1
+    }
+}
+#[doc = "Possible values of the field `UCPAR`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCPARR {
+    #[doc = "Odd parity"]
+    UCPAR_0,
+    #[doc = "Even parity"]
+    UCPAR_1,
+}
+impl UCPARR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCPARR::UCPAR_0 => false,
+            UCPARR::UCPAR_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCPARR {
+        match value {
+            false => UCPARR::UCPAR_0,
+            true => UCPARR::UCPAR_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCPAR_0`"]
+    #[inline]
+    pub fn is_ucpar_0(&self) -> bool {
+        *self == UCPARR::UCPAR_0
+    }
+    #[doc = "Checks if the value of the field is `UCPAR_1`"]
+    #[inline]
+    pub fn is_ucpar_1(&self) -> bool {
+        *self == UCPARR::UCPAR_1
+    }
+}
+#[doc = "Possible values of the field `UCPEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCPENR {
+    #[doc = "Parity disabled"]
+    UCPEN_0,
+    #[doc = "Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation."]
+    UCPEN_1,
+}
+impl UCPENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCPENR::UCPEN_0 => false,
+            UCPENR::UCPEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCPENR {
+        match value {
+            false => UCPENR::UCPEN_0,
+            true => UCPENR::UCPEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCPEN_0`"]
+    #[inline]
+    pub fn is_ucpen_0(&self) -> bool {
+        *self == UCPENR::UCPEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCPEN_1`"]
+    #[inline]
+    pub fn is_ucpen_1(&self) -> bool {
+        *self == UCPENR::UCPEN_1
+    }
+}
+#[doc = "Values that can be written to the field `UCSWRST`"]
+pub enum UCSWRSTW {
+    #[doc = "Disabled. eUSCI_A reset released for operation"]
+    UCSWRST_0,
+    #[doc = "Enabled. eUSCI_A logic held in reset state"]
+    UCSWRST_1,
+}
+impl UCSWRSTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSWRSTW::UCSWRST_0 => false,
+            UCSWRSTW::UCSWRST_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSWRSTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSWRSTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSWRSTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disabled. eUSCI_A reset released for operation"]
+    #[inline]
+    pub fn ucswrst_0(self) -> &'a mut W {
+        self.variant(UCSWRSTW::UCSWRST_0)
+    }
+    #[doc = "Enabled. eUSCI_A logic held in reset state"]
+    #[inline]
+    pub fn ucswrst_1(self) -> &'a mut W {
+        self.variant(UCSWRSTW::UCSWRST_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXBRK`"]
+pub enum UCTXBRKW {
+    #[doc = "Next frame transmitted is not a break"]
+    UCTXBRK_0,
+    #[doc = "Next frame transmitted is a break or a break/synch"]
+    UCTXBRK_1,
+}
+impl UCTXBRKW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXBRKW::UCTXBRK_0 => false,
+            UCTXBRKW::UCTXBRK_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXBRKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXBRKW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXBRKW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Next frame transmitted is not a break"]
+    #[inline]
+    pub fn uctxbrk_0(self) -> &'a mut W {
+        self.variant(UCTXBRKW::UCTXBRK_0)
+    }
+    #[doc = "Next frame transmitted is a break or a break/synch"]
+    #[inline]
+    pub fn uctxbrk_1(self) -> &'a mut W {
+        self.variant(UCTXBRKW::UCTXBRK_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXADDR`"]
+pub enum UCTXADDRW {
+    #[doc = "Next frame transmitted is data"]
+    UCTXADDR_0,
+    #[doc = "Next frame transmitted is an address"]
+    UCTXADDR_1,
+}
+impl UCTXADDRW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXADDRW::UCTXADDR_0 => false,
+            UCTXADDRW::UCTXADDR_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXADDRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXADDRW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXADDRW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Next frame transmitted is data"]
+    #[inline]
+    pub fn uctxaddr_0(self) -> &'a mut W {
+        self.variant(UCTXADDRW::UCTXADDR_0)
+    }
+    #[doc = "Next frame transmitted is an address"]
+    #[inline]
+    pub fn uctxaddr_1(self) -> &'a mut W {
+        self.variant(UCTXADDRW::UCTXADDR_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCDORM`"]
+pub enum UCDORMW {
+    #[doc = "Not dormant. All received characters set UCRXIFG."]
+    UCDORM_0,
+    #[doc = "Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG."]
+    UCDORM_1,
+}
+impl UCDORMW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCDORMW::UCDORM_0 => false,
+            UCDORMW::UCDORM_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCDORMW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCDORMW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCDORMW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Not dormant. All received characters set UCRXIFG."]
+    #[inline]
+    pub fn ucdorm_0(self) -> &'a mut W {
+        self.variant(UCDORMW::UCDORM_0)
+    }
+    #[doc = "Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG."]
+    #[inline]
+    pub fn ucdorm_1(self) -> &'a mut W {
+        self.variant(UCDORMW::UCDORM_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCBRKIE`"]
+pub enum UCBRKIEW {
+    #[doc = "Received break characters do not set UCRXIFG"]
+    UCBRKIE_0,
+    #[doc = "Received break characters set UCRXIFG"]
+    UCBRKIE_1,
+}
+impl UCBRKIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCBRKIEW::UCBRKIE_0 => false,
+            UCBRKIEW::UCBRKIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBRKIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBRKIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCBRKIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Received break characters do not set UCRXIFG"]
+    #[inline]
+    pub fn ucbrkie_0(self) -> &'a mut W {
+        self.variant(UCBRKIEW::UCBRKIE_0)
+    }
+    #[doc = "Received break characters set UCRXIFG"]
+    #[inline]
+    pub fn ucbrkie_1(self) -> &'a mut W {
+        self.variant(UCBRKIEW::UCBRKIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXEIE`"]
+pub enum UCRXEIEW {
+    #[doc = "Erroneous characters rejected and UCRXIFG is not set"]
+    UCRXEIE_0,
+    #[doc = "Erroneous characters received set UCRXIFG"]
+    UCRXEIE_1,
+}
+impl UCRXEIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXEIEW::UCRXEIE_0 => false,
+            UCRXEIEW::UCRXEIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXEIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXEIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXEIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Erroneous characters rejected and UCRXIFG is not set"]
+    #[inline]
+    pub fn ucrxeie_0(self) -> &'a mut W {
+        self.variant(UCRXEIEW::UCRXEIE_0)
+    }
+    #[doc = "Erroneous characters received set UCRXIFG"]
+    #[inline]
+    pub fn ucrxeie_1(self) -> &'a mut W {
+        self.variant(UCRXEIEW::UCRXEIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSSEL`"]
+pub enum UCSSELW {
+    #[doc = "UCLK"]
+    UCSSEL_0,
+    #[doc = "ACLK"]
+    UCSSEL_1,
+    #[doc = "SMCLK"]
+    UCSSEL_2,
+}
+impl UCSSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCSSELW::UCSSEL_0 => 0,
+            UCSSELW::UCSSEL_1 => 1,
+            UCSSELW::UCSSEL_2 => 2,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSSELW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "UCLK"]
+    #[inline]
+    pub fn ucssel_0(self) -> &'a mut W {
+        self.variant(UCSSELW::UCSSEL_0)
+    }
+    #[doc = "ACLK"]
+    #[inline]
+    pub fn ucssel_1(self) -> &'a mut W {
+        self.variant(UCSSELW::UCSSEL_1)
+    }
+    #[doc = "SMCLK"]
+    #[inline]
+    pub fn ucssel_2(self) -> &'a mut W {
+        self.variant(UCSSELW::UCSSEL_2)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSYNC`"]
+pub enum UCSYNCW {
+    #[doc = "Asynchronous mode"]
+    UCSYNC_0,
+    #[doc = "Synchronous mode"]
+    UCSYNC_1,
+}
+impl UCSYNCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSYNCW::UCSYNC_0 => false,
+            UCSYNCW::UCSYNC_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSYNCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSYNCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSYNCW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Asynchronous mode"]
+    #[inline]
+    pub fn ucsync_0(self) -> &'a mut W {
+        self.variant(UCSYNCW::UCSYNC_0)
+    }
+    #[doc = "Synchronous mode"]
+    #[inline]
+    pub fn ucsync_1(self) -> &'a mut W {
+        self.variant(UCSYNCW::UCSYNC_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCMODE`"]
+pub enum UCMODEW {
+    #[doc = "UART mode"]
+    UCMODE_0,
+    #[doc = "Idle-line multiprocessor mode"]
+    UCMODE_1,
+    #[doc = "Address-bit multiprocessor mode"]
+    UCMODE_2,
+    #[doc = "UART mode with automatic baud-rate detection"]
+    UCMODE_3,
+}
+impl UCMODEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCMODEW::UCMODE_0 => 0,
+            UCMODEW::UCMODE_1 => 1,
+            UCMODEW::UCMODE_2 => 2,
+            UCMODEW::UCMODE_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCMODEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCMODEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCMODEW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "UART mode"]
+    #[inline]
+    pub fn ucmode_0(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_0)
+    }
+    #[doc = "Idle-line multiprocessor mode"]
+    #[inline]
+    pub fn ucmode_1(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_1)
+    }
+    #[doc = "Address-bit multiprocessor mode"]
+    #[inline]
+    pub fn ucmode_2(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_2)
+    }
+    #[doc = "UART mode with automatic baud-rate detection"]
+    #[inline]
+    pub fn ucmode_3(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSPB`"]
+pub enum UCSPBW {
+    #[doc = "One stop bit"]
+    UCSPB_0,
+    #[doc = "Two stop bits"]
+    UCSPB_1,
+}
+impl UCSPBW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSPBW::UCSPB_0 => false,
+            UCSPBW::UCSPB_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSPBW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSPBW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSPBW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "One stop bit"]
+    #[inline]
+    pub fn ucspb_0(self) -> &'a mut W {
+        self.variant(UCSPBW::UCSPB_0)
+    }
+    #[doc = "Two stop bits"]
+    #[inline]
+    pub fn ucspb_1(self) -> &'a mut W {
+        self.variant(UCSPBW::UCSPB_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UC7BIT`"]
+pub enum UC7BITW {
+    #[doc = "8-bit data"]
+    UC7BIT_0,
+    #[doc = "7-bit data"]
+    UC7BIT_1,
+}
+impl UC7BITW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UC7BITW::UC7BIT_0 => false,
+            UC7BITW::UC7BIT_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UC7BITW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UC7BITW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UC7BITW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "8-bit data"]
+    #[inline]
+    pub fn uc7bit_0(self) -> &'a mut W {
+        self.variant(UC7BITW::UC7BIT_0)
+    }
+    #[doc = "7-bit data"]
+    #[inline]
+    pub fn uc7bit_1(self) -> &'a mut W {
+        self.variant(UC7BITW::UC7BIT_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCMSB`"]
+pub enum UCMSBW {
+    #[doc = "LSB first"]
+    UCMSB_0,
+    #[doc = "MSB first"]
+    UCMSB_1,
+}
+impl UCMSBW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCMSBW::UCMSB_0 => false,
+            UCMSBW::UCMSB_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCMSBW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCMSBW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCMSBW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "LSB first"]
+    #[inline]
+    pub fn ucmsb_0(self) -> &'a mut W {
+        self.variant(UCMSBW::UCMSB_0)
+    }
+    #[doc = "MSB first"]
+    #[inline]
+    pub fn ucmsb_1(self) -> &'a mut W {
+        self.variant(UCMSBW::UCMSB_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCPAR`"]
+pub enum UCPARW {
+    #[doc = "Odd parity"]
+    UCPAR_0,
+    #[doc = "Even parity"]
+    UCPAR_1,
+}
+impl UCPARW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCPARW::UCPAR_0 => false,
+            UCPARW::UCPAR_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCPARW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCPARW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCPARW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Odd parity"]
+    #[inline]
+    pub fn ucpar_0(self) -> &'a mut W {
+        self.variant(UCPARW::UCPAR_0)
+    }
+    #[doc = "Even parity"]
+    #[inline]
+    pub fn ucpar_1(self) -> &'a mut W {
+        self.variant(UCPARW::UCPAR_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCPEN`"]
+pub enum UCPENW {
+    #[doc = "Parity disabled"]
+    UCPEN_0,
+    #[doc = "Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation."]
+    UCPEN_1,
+}
+impl UCPENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCPENW::UCPEN_0 => false,
+            UCPENW::UCPEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCPENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCPENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCPENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Parity disabled"]
+    #[inline]
+    pub fn ucpen_0(self) -> &'a mut W {
+        self.variant(UCPENW::UCPEN_0)
+    }
+    #[doc = "Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation."]
+    #[inline]
+    pub fn ucpen_1(self) -> &'a mut W {
+        self.variant(UCPENW::UCPEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Software reset enable"]
+    #[inline]
+    pub fn ucswrst(&self) -> UCSWRSTR {
+        UCSWRSTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Transmit break"]
+    #[inline]
+    pub fn uctxbrk(&self) -> UCTXBRKR {
+        UCTXBRKR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - Transmit address"]
+    #[inline]
+    pub fn uctxaddr(&self) -> UCTXADDRR {
+        UCTXADDRR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Dormant"]
+    #[inline]
+    pub fn ucdorm(&self) -> UCDORMR {
+        UCDORMR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 4 - Receive break character interrupt enable"]
+    #[inline]
+    pub fn ucbrkie(&self) -> UCBRKIER {
+        UCBRKIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - Receive erroneous-character interrupt enable"]
+    #[inline]
+    pub fn ucrxeie(&self) -> UCRXEIER {
+        UCRXEIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 6:7 - eUSCI_A clock source select"]
+    #[inline]
+    pub fn ucssel(&self) -> UCSSELR {
+        UCSSELR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 8 - Synchronous mode enable"]
+    #[inline]
+    pub fn ucsync(&self) -> UCSYNCR {
+        UCSYNCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 9:10 - eUSCI_A mode"]
+    #[inline]
+    pub fn ucmode(&self) -> UCMODER {
+        UCMODER::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 11 - Stop bit select"]
+    #[inline]
+    pub fn ucspb(&self) -> UCSPBR {
+        UCSPBR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 12 - Character length"]
+    #[inline]
+    pub fn uc7bit(&self) -> UC7BITR {
+        UC7BITR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 13 - MSB first select"]
+    #[inline]
+    pub fn ucmsb(&self) -> UCMSBR {
+        UCMSBR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 14 - Parity select"]
+    #[inline]
+    pub fn ucpar(&self) -> UCPARR {
+        UCPARR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 15 - Parity enable"]
+    #[inline]
+    pub fn ucpen(&self) -> UCPENR {
+        UCPENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 1 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Software reset enable"]
+    #[inline]
+    pub fn ucswrst(&mut self) -> _UCSWRSTW {
+        _UCSWRSTW { w: self }
+    }
+    #[doc = "Bit 1 - Transmit break"]
+    #[inline]
+    pub fn uctxbrk(&mut self) -> _UCTXBRKW {
+        _UCTXBRKW { w: self }
+    }
+    #[doc = "Bit 2 - Transmit address"]
+    #[inline]
+    pub fn uctxaddr(&mut self) -> _UCTXADDRW {
+        _UCTXADDRW { w: self }
+    }
+    #[doc = "Bit 3 - Dormant"]
+    #[inline]
+    pub fn ucdorm(&mut self) -> _UCDORMW {
+        _UCDORMW { w: self }
+    }
+    #[doc = "Bit 4 - Receive break character interrupt enable"]
+    #[inline]
+    pub fn ucbrkie(&mut self) -> _UCBRKIEW {
+        _UCBRKIEW { w: self }
+    }
+    #[doc = "Bit 5 - Receive erroneous-character interrupt enable"]
+    #[inline]
+    pub fn ucrxeie(&mut self) -> _UCRXEIEW {
+        _UCRXEIEW { w: self }
+    }
+    #[doc = "Bits 6:7 - eUSCI_A clock source select"]
+    #[inline]
+    pub fn ucssel(&mut self) -> _UCSSELW {
+        _UCSSELW { w: self }
+    }
+    #[doc = "Bit 8 - Synchronous mode enable"]
+    #[inline]
+    pub fn ucsync(&mut self) -> _UCSYNCW {
+        _UCSYNCW { w: self }
+    }
+    #[doc = "Bits 9:10 - eUSCI_A mode"]
+    #[inline]
+    pub fn ucmode(&mut self) -> _UCMODEW {
+        _UCMODEW { w: self }
+    }
+    #[doc = "Bit 11 - Stop bit select"]
+    #[inline]
+    pub fn ucspb(&mut self) -> _UCSPBW {
+        _UCSPBW { w: self }
+    }
+    #[doc = "Bit 12 - Character length"]
+    #[inline]
+    pub fn uc7bit(&mut self) -> _UC7BITW {
+        _UC7BITW { w: self }
+    }
+    #[doc = "Bit 13 - MSB first select"]
+    #[inline]
+    pub fn ucmsb(&mut self) -> _UCMSBW {
+        _UCMSBW { w: self }
+    }
+    #[doc = "Bit 14 - Parity select"]
+    #[inline]
+    pub fn ucpar(&mut self) -> _UCPARW {
+        _UCPARW { w: self }
+    }
+    #[doc = "Bit 15 - Parity enable"]
+    #[inline]
+    pub fn ucpen(&mut self) -> _UCPENW {
+        _UCPENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a1/ucax_ctlw1.rs b/example-source/msp432p401r/src/eusci_a1/ucax_ctlw1.rs
new file mode 100644
index 0000000..365cc0d
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a1/ucax_ctlw1.rs
@@ -0,0 +1,200 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXCTLW1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCGLIT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCGLITR {
+    #[doc = "Approximately 2 ns (equivalent of 1 delay element)"]
+    UCGLIT_0,
+    #[doc = "Approximately 50 ns"]
+    UCGLIT_1,
+    #[doc = "Approximately 100 ns"]
+    UCGLIT_2,
+    #[doc = "Approximately 200 ns"]
+    UCGLIT_3,
+}
+impl UCGLITR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCGLITR::UCGLIT_0 => 0,
+            UCGLITR::UCGLIT_1 => 1,
+            UCGLITR::UCGLIT_2 => 2,
+            UCGLITR::UCGLIT_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCGLITR {
+        match value {
+            0 => UCGLITR::UCGLIT_0,
+            1 => UCGLITR::UCGLIT_1,
+            2 => UCGLITR::UCGLIT_2,
+            3 => UCGLITR::UCGLIT_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_0`"]
+    #[inline]
+    pub fn is_ucglit_0(&self) -> bool {
+        *self == UCGLITR::UCGLIT_0
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_1`"]
+    #[inline]
+    pub fn is_ucglit_1(&self) -> bool {
+        *self == UCGLITR::UCGLIT_1
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_2`"]
+    #[inline]
+    pub fn is_ucglit_2(&self) -> bool {
+        *self == UCGLITR::UCGLIT_2
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_3`"]
+    #[inline]
+    pub fn is_ucglit_3(&self) -> bool {
+        *self == UCGLITR::UCGLIT_3
+    }
+}
+#[doc = "Values that can be written to the field `UCGLIT`"]
+pub enum UCGLITW {
+    #[doc = "Approximately 2 ns (equivalent of 1 delay element)"]
+    UCGLIT_0,
+    #[doc = "Approximately 50 ns"]
+    UCGLIT_1,
+    #[doc = "Approximately 100 ns"]
+    UCGLIT_2,
+    #[doc = "Approximately 200 ns"]
+    UCGLIT_3,
+}
+impl UCGLITW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCGLITW::UCGLIT_0 => 0,
+            UCGLITW::UCGLIT_1 => 1,
+            UCGLITW::UCGLIT_2 => 2,
+            UCGLITW::UCGLIT_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCGLITW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCGLITW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCGLITW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Approximately 2 ns (equivalent of 1 delay element)"]
+    #[inline]
+    pub fn ucglit_0(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_0)
+    }
+    #[doc = "Approximately 50 ns"]
+    #[inline]
+    pub fn ucglit_1(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_1)
+    }
+    #[doc = "Approximately 100 ns"]
+    #[inline]
+    pub fn ucglit_2(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_2)
+    }
+    #[doc = "Approximately 200 ns"]
+    #[inline]
+    pub fn ucglit_3(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:1 - Deglitch time"]
+    #[inline]
+    pub fn ucglit(&self) -> UCGLITR {
+        UCGLITR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 3 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:1 - Deglitch time"]
+    #[inline]
+    pub fn ucglit(&mut self) -> _UCGLITW {
+        _UCGLITW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a1/ucax_ie.rs b/example-source/msp432p401r/src/eusci_a1/ucax_ie.rs
new file mode 100644
index 0000000..f91baad
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a1/ucax_ie.rs
@@ -0,0 +1,540 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXIE {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCRXIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIER {
+    #[doc = "Interrupt disabled"]
+    UCRXIE_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE_1,
+}
+impl UCRXIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIER::UCRXIE_0 => false,
+            UCRXIER::UCRXIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIER {
+        match value {
+            false => UCRXIER::UCRXIE_0,
+            true => UCRXIER::UCRXIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE_0`"]
+    #[inline]
+    pub fn is_ucrxie_0(&self) -> bool {
+        *self == UCRXIER::UCRXIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE_1`"]
+    #[inline]
+    pub fn is_ucrxie_1(&self) -> bool {
+        *self == UCRXIER::UCRXIE_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIER {
+    #[doc = "Interrupt disabled"]
+    UCTXIE_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE_1,
+}
+impl UCTXIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIER::UCTXIE_0 => false,
+            UCTXIER::UCTXIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIER {
+        match value {
+            false => UCTXIER::UCTXIE_0,
+            true => UCTXIER::UCTXIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE_0`"]
+    #[inline]
+    pub fn is_uctxie_0(&self) -> bool {
+        *self == UCTXIER::UCTXIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE_1`"]
+    #[inline]
+    pub fn is_uctxie_1(&self) -> bool {
+        *self == UCTXIER::UCTXIE_1
+    }
+}
+#[doc = "Possible values of the field `UCSTTIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTTIER {
+    #[doc = "Interrupt disabled"]
+    UCSTTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCSTTIE_1,
+}
+impl UCSTTIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTTIER::UCSTTIE_0 => false,
+            UCSTTIER::UCSTTIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTTIER {
+        match value {
+            false => UCSTTIER::UCSTTIE_0,
+            true => UCSTTIER::UCSTTIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIE_0`"]
+    #[inline]
+    pub fn is_ucsttie_0(&self) -> bool {
+        *self == UCSTTIER::UCSTTIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIE_1`"]
+    #[inline]
+    pub fn is_ucsttie_1(&self) -> bool {
+        *self == UCSTTIER::UCSTTIE_1
+    }
+}
+#[doc = "Possible values of the field `UCTXCPTIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXCPTIER {
+    #[doc = "Interrupt disabled"]
+    UCTXCPTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCTXCPTIE_1,
+}
+impl UCTXCPTIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXCPTIER::UCTXCPTIE_0 => false,
+            UCTXCPTIER::UCTXCPTIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXCPTIER {
+        match value {
+            false => UCTXCPTIER::UCTXCPTIE_0,
+            true => UCTXCPTIER::UCTXCPTIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXCPTIE_0`"]
+    #[inline]
+    pub fn is_uctxcptie_0(&self) -> bool {
+        *self == UCTXCPTIER::UCTXCPTIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXCPTIE_1`"]
+    #[inline]
+    pub fn is_uctxcptie_1(&self) -> bool {
+        *self == UCTXCPTIER::UCTXCPTIE_1
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIE`"]
+pub enum UCRXIEW {
+    #[doc = "Interrupt disabled"]
+    UCRXIE_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE_1,
+}
+impl UCRXIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIEW::UCRXIE_0 => false,
+            UCRXIEW::UCRXIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucrxie_0(self) -> &'a mut W {
+        self.variant(UCRXIEW::UCRXIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucrxie_1(self) -> &'a mut W {
+        self.variant(UCRXIEW::UCRXIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIE`"]
+pub enum UCTXIEW {
+    #[doc = "Interrupt disabled"]
+    UCTXIE_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE_1,
+}
+impl UCTXIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIEW::UCTXIE_0 => false,
+            UCTXIEW::UCTXIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn uctxie_0(self) -> &'a mut W {
+        self.variant(UCTXIEW::UCTXIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn uctxie_1(self) -> &'a mut W {
+        self.variant(UCTXIEW::UCTXIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTTIE`"]
+pub enum UCSTTIEW {
+    #[doc = "Interrupt disabled"]
+    UCSTTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCSTTIE_1,
+}
+impl UCSTTIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTTIEW::UCSTTIE_0 => false,
+            UCSTTIEW::UCSTTIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTTIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTTIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTTIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucsttie_0(self) -> &'a mut W {
+        self.variant(UCSTTIEW::UCSTTIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucsttie_1(self) -> &'a mut W {
+        self.variant(UCSTTIEW::UCSTTIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXCPTIE`"]
+pub enum UCTXCPTIEW {
+    #[doc = "Interrupt disabled"]
+    UCTXCPTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCTXCPTIE_1,
+}
+impl UCTXCPTIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXCPTIEW::UCTXCPTIE_0 => false,
+            UCTXCPTIEW::UCTXCPTIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXCPTIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXCPTIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXCPTIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn uctxcptie_0(self) -> &'a mut W {
+        self.variant(UCTXCPTIEW::UCTXCPTIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn uctxcptie_1(self) -> &'a mut W {
+        self.variant(UCTXCPTIEW::UCTXCPTIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Receive interrupt enable"]
+    #[inline]
+    pub fn ucrxie(&self) -> UCRXIER {
+        UCRXIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Transmit interrupt enable"]
+    #[inline]
+    pub fn uctxie(&self) -> UCTXIER {
+        UCTXIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - Start bit interrupt enable"]
+    #[inline]
+    pub fn ucsttie(&self) -> UCSTTIER {
+        UCSTTIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Transmit complete interrupt enable"]
+    #[inline]
+    pub fn uctxcptie(&self) -> UCTXCPTIER {
+        UCTXCPTIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Receive interrupt enable"]
+    #[inline]
+    pub fn ucrxie(&mut self) -> _UCRXIEW {
+        _UCRXIEW { w: self }
+    }
+    #[doc = "Bit 1 - Transmit interrupt enable"]
+    #[inline]
+    pub fn uctxie(&mut self) -> _UCTXIEW {
+        _UCTXIEW { w: self }
+    }
+    #[doc = "Bit 2 - Start bit interrupt enable"]
+    #[inline]
+    pub fn ucsttie(&mut self) -> _UCSTTIEW {
+        _UCSTTIEW { w: self }
+    }
+    #[doc = "Bit 3 - Transmit complete interrupt enable"]
+    #[inline]
+    pub fn uctxcptie(&mut self) -> _UCTXCPTIEW {
+        _UCTXCPTIEW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a1/ucax_ifg.rs b/example-source/msp432p401r/src/eusci_a1/ucax_ifg.rs
new file mode 100644
index 0000000..88bb34d
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a1/ucax_ifg.rs
@@ -0,0 +1,540 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXIFG {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCRXIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIFGR {
+    #[doc = "No interrupt pending"]
+    UCRXIFG_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG_1,
+}
+impl UCRXIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIFGR::UCRXIFG_0 => false,
+            UCRXIFGR::UCRXIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIFGR {
+        match value {
+            false => UCRXIFGR::UCRXIFG_0,
+            true => UCRXIFGR::UCRXIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG_0`"]
+    #[inline]
+    pub fn is_ucrxifg_0(&self) -> bool {
+        *self == UCRXIFGR::UCRXIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG_1`"]
+    #[inline]
+    pub fn is_ucrxifg_1(&self) -> bool {
+        *self == UCRXIFGR::UCRXIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIFGR {
+    #[doc = "No interrupt pending"]
+    UCTXIFG_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG_1,
+}
+impl UCTXIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIFGR::UCTXIFG_0 => false,
+            UCTXIFGR::UCTXIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIFGR {
+        match value {
+            false => UCTXIFGR::UCTXIFG_0,
+            true => UCTXIFGR::UCTXIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG_0`"]
+    #[inline]
+    pub fn is_uctxifg_0(&self) -> bool {
+        *self == UCTXIFGR::UCTXIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG_1`"]
+    #[inline]
+    pub fn is_uctxifg_1(&self) -> bool {
+        *self == UCTXIFGR::UCTXIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCSTTIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTTIFGR {
+    #[doc = "No interrupt pending"]
+    UCSTTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCSTTIFG_1,
+}
+impl UCSTTIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTTIFGR::UCSTTIFG_0 => false,
+            UCSTTIFGR::UCSTTIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTTIFGR {
+        match value {
+            false => UCSTTIFGR::UCSTTIFG_0,
+            true => UCSTTIFGR::UCSTTIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIFG_0`"]
+    #[inline]
+    pub fn is_ucsttifg_0(&self) -> bool {
+        *self == UCSTTIFGR::UCSTTIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIFG_1`"]
+    #[inline]
+    pub fn is_ucsttifg_1(&self) -> bool {
+        *self == UCSTTIFGR::UCSTTIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCTXCPTIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXCPTIFGR {
+    #[doc = "No interrupt pending"]
+    UCTXCPTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCTXCPTIFG_1,
+}
+impl UCTXCPTIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXCPTIFGR::UCTXCPTIFG_0 => false,
+            UCTXCPTIFGR::UCTXCPTIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXCPTIFGR {
+        match value {
+            false => UCTXCPTIFGR::UCTXCPTIFG_0,
+            true => UCTXCPTIFGR::UCTXCPTIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXCPTIFG_0`"]
+    #[inline]
+    pub fn is_uctxcptifg_0(&self) -> bool {
+        *self == UCTXCPTIFGR::UCTXCPTIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXCPTIFG_1`"]
+    #[inline]
+    pub fn is_uctxcptifg_1(&self) -> bool {
+        *self == UCTXCPTIFGR::UCTXCPTIFG_1
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIFG`"]
+pub enum UCRXIFGW {
+    #[doc = "No interrupt pending"]
+    UCRXIFG_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG_1,
+}
+impl UCRXIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIFGW::UCRXIFG_0 => false,
+            UCRXIFGW::UCRXIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucrxifg_0(self) -> &'a mut W {
+        self.variant(UCRXIFGW::UCRXIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucrxifg_1(self) -> &'a mut W {
+        self.variant(UCRXIFGW::UCRXIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIFG`"]
+pub enum UCTXIFGW {
+    #[doc = "No interrupt pending"]
+    UCTXIFG_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG_1,
+}
+impl UCTXIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIFGW::UCTXIFG_0 => false,
+            UCTXIFGW::UCTXIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn uctxifg_0(self) -> &'a mut W {
+        self.variant(UCTXIFGW::UCTXIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn uctxifg_1(self) -> &'a mut W {
+        self.variant(UCTXIFGW::UCTXIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTTIFG`"]
+pub enum UCSTTIFGW {
+    #[doc = "No interrupt pending"]
+    UCSTTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCSTTIFG_1,
+}
+impl UCSTTIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTTIFGW::UCSTTIFG_0 => false,
+            UCSTTIFGW::UCSTTIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTTIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTTIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTTIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucsttifg_0(self) -> &'a mut W {
+        self.variant(UCSTTIFGW::UCSTTIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucsttifg_1(self) -> &'a mut W {
+        self.variant(UCSTTIFGW::UCSTTIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXCPTIFG`"]
+pub enum UCTXCPTIFGW {
+    #[doc = "No interrupt pending"]
+    UCTXCPTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCTXCPTIFG_1,
+}
+impl UCTXCPTIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXCPTIFGW::UCTXCPTIFG_0 => false,
+            UCTXCPTIFGW::UCTXCPTIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXCPTIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXCPTIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXCPTIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn uctxcptifg_0(self) -> &'a mut W {
+        self.variant(UCTXCPTIFGW::UCTXCPTIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn uctxcptifg_1(self) -> &'a mut W {
+        self.variant(UCTXCPTIFGW::UCTXCPTIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Receive interrupt flag"]
+    #[inline]
+    pub fn ucrxifg(&self) -> UCRXIFGR {
+        UCRXIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Transmit interrupt flag"]
+    #[inline]
+    pub fn uctxifg(&self) -> UCTXIFGR {
+        UCTXIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - Start bit interrupt flag"]
+    #[inline]
+    pub fn ucsttifg(&self) -> UCSTTIFGR {
+        UCSTTIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Transmit ready interrupt enable"]
+    #[inline]
+    pub fn uctxcptifg(&self) -> UCTXCPTIFGR {
+        UCTXCPTIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 2 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Receive interrupt flag"]
+    #[inline]
+    pub fn ucrxifg(&mut self) -> _UCRXIFGW {
+        _UCRXIFGW { w: self }
+    }
+    #[doc = "Bit 1 - Transmit interrupt flag"]
+    #[inline]
+    pub fn uctxifg(&mut self) -> _UCTXIFGW {
+        _UCTXIFGW { w: self }
+    }
+    #[doc = "Bit 2 - Start bit interrupt flag"]
+    #[inline]
+    pub fn ucsttifg(&mut self) -> _UCSTTIFGW {
+        _UCSTTIFGW { w: self }
+    }
+    #[doc = "Bit 3 - Transmit ready interrupt enable"]
+    #[inline]
+    pub fn uctxcptifg(&mut self) -> _UCTXCPTIFGW {
+        _UCTXCPTIFGW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a1/ucax_irctl.rs b/example-source/msp432p401r/src/eusci_a1/ucax_irctl.rs
new file mode 100644
index 0000000..38d0d14
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a1/ucax_irctl.rs
@@ -0,0 +1,622 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXIRCTL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCIREN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCIRENR {
+    #[doc = "IrDA encoder/decoder disabled"]
+    UCIREN_0,
+    #[doc = "IrDA encoder/decoder enabled"]
+    UCIREN_1,
+}
+impl UCIRENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCIRENR::UCIREN_0 => false,
+            UCIRENR::UCIREN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCIRENR {
+        match value {
+            false => UCIRENR::UCIREN_0,
+            true => UCIRENR::UCIREN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCIREN_0`"]
+    #[inline]
+    pub fn is_uciren_0(&self) -> bool {
+        *self == UCIRENR::UCIREN_0
+    }
+    #[doc = "Checks if the value of the field is `UCIREN_1`"]
+    #[inline]
+    pub fn is_uciren_1(&self) -> bool {
+        *self == UCIRENR::UCIREN_1
+    }
+}
+#[doc = "Possible values of the field `UCIRTXCLK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCIRTXCLKR {
+    #[doc = "BRCLK"]
+    UCIRTXCLK_0,
+    #[doc = "BITCLK16 when UCOS16 = 1. Otherwise, BRCLK."]
+    UCIRTXCLK_1,
+}
+impl UCIRTXCLKR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCIRTXCLKR::UCIRTXCLK_0 => false,
+            UCIRTXCLKR::UCIRTXCLK_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCIRTXCLKR {
+        match value {
+            false => UCIRTXCLKR::UCIRTXCLK_0,
+            true => UCIRTXCLKR::UCIRTXCLK_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCIRTXCLK_0`"]
+    #[inline]
+    pub fn is_ucirtxclk_0(&self) -> bool {
+        *self == UCIRTXCLKR::UCIRTXCLK_0
+    }
+    #[doc = "Checks if the value of the field is `UCIRTXCLK_1`"]
+    #[inline]
+    pub fn is_ucirtxclk_1(&self) -> bool {
+        *self == UCIRTXCLKR::UCIRTXCLK_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCIRTXPLR {
+    bits: u8,
+}
+impl UCIRTXPLR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `UCIRRXFE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCIRRXFER {
+    #[doc = "Receive filter disabled"]
+    UCIRRXFE_0,
+    #[doc = "Receive filter enabled"]
+    UCIRRXFE_1,
+}
+impl UCIRRXFER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCIRRXFER::UCIRRXFE_0 => false,
+            UCIRRXFER::UCIRRXFE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCIRRXFER {
+        match value {
+            false => UCIRRXFER::UCIRRXFE_0,
+            true => UCIRRXFER::UCIRRXFE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCIRRXFE_0`"]
+    #[inline]
+    pub fn is_ucirrxfe_0(&self) -> bool {
+        *self == UCIRRXFER::UCIRRXFE_0
+    }
+    #[doc = "Checks if the value of the field is `UCIRRXFE_1`"]
+    #[inline]
+    pub fn is_ucirrxfe_1(&self) -> bool {
+        *self == UCIRRXFER::UCIRRXFE_1
+    }
+}
+#[doc = "Possible values of the field `UCIRRXPL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCIRRXPLR {
+    #[doc = "IrDA transceiver delivers a high pulse when a light pulse is seen"]
+    UCIRRXPL_0,
+    #[doc = "IrDA transceiver delivers a low pulse when a light pulse is seen"]
+    UCIRRXPL_1,
+}
+impl UCIRRXPLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCIRRXPLR::UCIRRXPL_0 => false,
+            UCIRRXPLR::UCIRRXPL_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCIRRXPLR {
+        match value {
+            false => UCIRRXPLR::UCIRRXPL_0,
+            true => UCIRRXPLR::UCIRRXPL_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCIRRXPL_0`"]
+    #[inline]
+    pub fn is_ucirrxpl_0(&self) -> bool {
+        *self == UCIRRXPLR::UCIRRXPL_0
+    }
+    #[doc = "Checks if the value of the field is `UCIRRXPL_1`"]
+    #[inline]
+    pub fn is_ucirrxpl_1(&self) -> bool {
+        *self == UCIRRXPLR::UCIRRXPL_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCIRRXFLR {
+    bits: u8,
+}
+impl UCIRRXFLR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Values that can be written to the field `UCIREN`"]
+pub enum UCIRENW {
+    #[doc = "IrDA encoder/decoder disabled"]
+    UCIREN_0,
+    #[doc = "IrDA encoder/decoder enabled"]
+    UCIREN_1,
+}
+impl UCIRENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCIRENW::UCIREN_0 => false,
+            UCIRENW::UCIREN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCIRENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCIRENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCIRENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "IrDA encoder/decoder disabled"]
+    #[inline]
+    pub fn uciren_0(self) -> &'a mut W {
+        self.variant(UCIRENW::UCIREN_0)
+    }
+    #[doc = "IrDA encoder/decoder enabled"]
+    #[inline]
+    pub fn uciren_1(self) -> &'a mut W {
+        self.variant(UCIRENW::UCIREN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCIRTXCLK`"]
+pub enum UCIRTXCLKW {
+    #[doc = "BRCLK"]
+    UCIRTXCLK_0,
+    #[doc = "BITCLK16 when UCOS16 = 1. Otherwise, BRCLK."]
+    UCIRTXCLK_1,
+}
+impl UCIRTXCLKW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCIRTXCLKW::UCIRTXCLK_0 => false,
+            UCIRTXCLKW::UCIRTXCLK_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCIRTXCLKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCIRTXCLKW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCIRTXCLKW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "BRCLK"]
+    #[inline]
+    pub fn ucirtxclk_0(self) -> &'a mut W {
+        self.variant(UCIRTXCLKW::UCIRTXCLK_0)
+    }
+    #[doc = "BITCLK16 when UCOS16 = 1. Otherwise, BRCLK."]
+    #[inline]
+    pub fn ucirtxclk_1(self) -> &'a mut W {
+        self.variant(UCIRTXCLKW::UCIRTXCLK_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCIRTXPLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCIRTXPLW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 63;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCIRRXFE`"]
+pub enum UCIRRXFEW {
+    #[doc = "Receive filter disabled"]
+    UCIRRXFE_0,
+    #[doc = "Receive filter enabled"]
+    UCIRRXFE_1,
+}
+impl UCIRRXFEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCIRRXFEW::UCIRRXFE_0 => false,
+            UCIRRXFEW::UCIRRXFE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCIRRXFEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCIRRXFEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCIRRXFEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Receive filter disabled"]
+    #[inline]
+    pub fn ucirrxfe_0(self) -> &'a mut W {
+        self.variant(UCIRRXFEW::UCIRRXFE_0)
+    }
+    #[doc = "Receive filter enabled"]
+    #[inline]
+    pub fn ucirrxfe_1(self) -> &'a mut W {
+        self.variant(UCIRRXFEW::UCIRRXFE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCIRRXPL`"]
+pub enum UCIRRXPLW {
+    #[doc = "IrDA transceiver delivers a high pulse when a light pulse is seen"]
+    UCIRRXPL_0,
+    #[doc = "IrDA transceiver delivers a low pulse when a light pulse is seen"]
+    UCIRRXPL_1,
+}
+impl UCIRRXPLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCIRRXPLW::UCIRRXPL_0 => false,
+            UCIRRXPLW::UCIRRXPL_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCIRRXPLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCIRRXPLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCIRRXPLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "IrDA transceiver delivers a high pulse when a light pulse is seen"]
+    #[inline]
+    pub fn ucirrxpl_0(self) -> &'a mut W {
+        self.variant(UCIRRXPLW::UCIRRXPL_0)
+    }
+    #[doc = "IrDA transceiver delivers a low pulse when a light pulse is seen"]
+    #[inline]
+    pub fn ucirrxpl_1(self) -> &'a mut W {
+        self.variant(UCIRRXPLW::UCIRRXPL_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCIRRXFLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCIRRXFLW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - IrDA encoder/decoder enable"]
+    #[inline]
+    pub fn uciren(&self) -> UCIRENR {
+        UCIRENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - IrDA transmit pulse clock select"]
+    #[inline]
+    pub fn ucirtxclk(&self) -> UCIRTXCLKR {
+        UCIRTXCLKR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 2:7 - Transmit pulse length"]
+    #[inline]
+    pub fn ucirtxpl(&self) -> UCIRTXPLR {
+        let bits = {
+            const MASK: u8 = 63;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCIRTXPLR { bits }
+    }
+    #[doc = "Bit 8 - IrDA receive filter enabled"]
+    #[inline]
+    pub fn ucirrxfe(&self) -> UCIRRXFER {
+        UCIRRXFER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 9 - IrDA receive input UCAxRXD polarity"]
+    #[inline]
+    pub fn ucirrxpl(&self) -> UCIRRXPLR {
+        UCIRRXPLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 10:13 - Receive filter length"]
+    #[inline]
+    pub fn ucirrxfl(&self) -> UCIRRXFLR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCIRRXFLR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - IrDA encoder/decoder enable"]
+    #[inline]
+    pub fn uciren(&mut self) -> _UCIRENW {
+        _UCIRENW { w: self }
+    }
+    #[doc = "Bit 1 - IrDA transmit pulse clock select"]
+    #[inline]
+    pub fn ucirtxclk(&mut self) -> _UCIRTXCLKW {
+        _UCIRTXCLKW { w: self }
+    }
+    #[doc = "Bits 2:7 - Transmit pulse length"]
+    #[inline]
+    pub fn ucirtxpl(&mut self) -> _UCIRTXPLW {
+        _UCIRTXPLW { w: self }
+    }
+    #[doc = "Bit 8 - IrDA receive filter enabled"]
+    #[inline]
+    pub fn ucirrxfe(&mut self) -> _UCIRRXFEW {
+        _UCIRRXFEW { w: self }
+    }
+    #[doc = "Bit 9 - IrDA receive input UCAxRXD polarity"]
+    #[inline]
+    pub fn ucirrxpl(&mut self) -> _UCIRRXPLW {
+        _UCIRRXPLW { w: self }
+    }
+    #[doc = "Bits 10:13 - Receive filter length"]
+    #[inline]
+    pub fn ucirrxfl(&mut self) -> _UCIRRXFLW {
+        _UCIRRXFLW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a1/ucax_iv.rs b/example-source/msp432p401r/src/eusci_a1/ucax_iv.rs
new file mode 100644
index 0000000..9f6d12c
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a1/ucax_iv.rs
@@ -0,0 +1,97 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::UCAXIV {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `UCIV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCIVR {
+    #[doc = "No interrupt pending"]
+    UCIV_0,
+    #[doc = "Interrupt Source: Receive buffer full; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest"]
+    UCIV_2,
+    #[doc = "Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG"]
+    UCIV_4,
+    #[doc = "Interrupt Source: Start bit received; Interrupt Flag: UCSTTIFG"]
+    UCIV_6,
+    #[doc = "Interrupt Source: Transmit complete; Interrupt Flag: UCTXCPTIFG; Interrupt Priority: Lowest"]
+    UCIV_8,
+    #[doc = r" Reserved"]
+    _Reserved(u16),
+}
+impl UCIVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        match *self {
+            UCIVR::UCIV_0 => 0,
+            UCIVR::UCIV_2 => 2,
+            UCIVR::UCIV_4 => 4,
+            UCIVR::UCIV_6 => 6,
+            UCIVR::UCIV_8 => 8,
+            UCIVR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u16) -> UCIVR {
+        match value {
+            0 => UCIVR::UCIV_0,
+            2 => UCIVR::UCIV_2,
+            4 => UCIVR::UCIV_4,
+            6 => UCIVR::UCIV_6,
+            8 => UCIVR::UCIV_8,
+            i => UCIVR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCIV_0`"]
+    #[inline]
+    pub fn is_uciv_0(&self) -> bool {
+        *self == UCIVR::UCIV_0
+    }
+    #[doc = "Checks if the value of the field is `UCIV_2`"]
+    #[inline]
+    pub fn is_uciv_2(&self) -> bool {
+        *self == UCIVR::UCIV_2
+    }
+    #[doc = "Checks if the value of the field is `UCIV_4`"]
+    #[inline]
+    pub fn is_uciv_4(&self) -> bool {
+        *self == UCIVR::UCIV_4
+    }
+    #[doc = "Checks if the value of the field is `UCIV_6`"]
+    #[inline]
+    pub fn is_uciv_6(&self) -> bool {
+        *self == UCIVR::UCIV_6
+    }
+    #[doc = "Checks if the value of the field is `UCIV_8`"]
+    #[inline]
+    pub fn is_uciv_8(&self) -> bool {
+        *self == UCIVR::UCIV_8
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - eUSCI_A interrupt vector value"]
+    #[inline]
+    pub fn uciv(&self) -> UCIVR {
+        UCIVR::_from({
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a1/ucax_mctlw.rs b/example-source/msp432p401r/src/eusci_a1/ucax_mctlw.rs
new file mode 100644
index 0000000..aebce19
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a1/ucax_mctlw.rs
@@ -0,0 +1,265 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXMCTLW {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCOS16`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCOS16R {
+    #[doc = "Disabled"]
+    UCOS16_0,
+    #[doc = "Enabled"]
+    UCOS16_1,
+}
+impl UCOS16R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCOS16R::UCOS16_0 => false,
+            UCOS16R::UCOS16_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCOS16R {
+        match value {
+            false => UCOS16R::UCOS16_0,
+            true => UCOS16R::UCOS16_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCOS16_0`"]
+    #[inline]
+    pub fn is_ucos16_0(&self) -> bool {
+        *self == UCOS16R::UCOS16_0
+    }
+    #[doc = "Checks if the value of the field is `UCOS16_1`"]
+    #[inline]
+    pub fn is_ucos16_1(&self) -> bool {
+        *self == UCOS16R::UCOS16_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCBRFR {
+    bits: u8,
+}
+impl UCBRFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCBRSR {
+    bits: u8,
+}
+impl UCBRSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Values that can be written to the field `UCOS16`"]
+pub enum UCOS16W {
+    #[doc = "Disabled"]
+    UCOS16_0,
+    #[doc = "Enabled"]
+    UCOS16_1,
+}
+impl UCOS16W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCOS16W::UCOS16_0 => false,
+            UCOS16W::UCOS16_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCOS16W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCOS16W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCOS16W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disabled"]
+    #[inline]
+    pub fn ucos16_0(self) -> &'a mut W {
+        self.variant(UCOS16W::UCOS16_0)
+    }
+    #[doc = "Enabled"]
+    #[inline]
+    pub fn ucos16_1(self) -> &'a mut W {
+        self.variant(UCOS16W::UCOS16_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBRFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBRFW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBRSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBRSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Oversampling mode enabled"]
+    #[inline]
+    pub fn ucos16(&self) -> UCOS16R {
+        UCOS16R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 4:7 - First modulation stage select"]
+    #[inline]
+    pub fn ucbrf(&self) -> UCBRFR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCBRFR { bits }
+    }
+    #[doc = "Bits 8:15 - Second modulation stage select"]
+    #[inline]
+    pub fn ucbrs(&self) -> UCBRSR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCBRSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Oversampling mode enabled"]
+    #[inline]
+    pub fn ucos16(&mut self) -> _UCOS16W {
+        _UCOS16W { w: self }
+    }
+    #[doc = "Bits 4:7 - First modulation stage select"]
+    #[inline]
+    pub fn ucbrf(&mut self) -> _UCBRFW {
+        _UCBRFW { w: self }
+    }
+    #[doc = "Bits 8:15 - Second modulation stage select"]
+    #[inline]
+    pub fn ucbrs(&mut self) -> _UCBRSW {
+        _UCBRSW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a1/ucax_rxbuf.rs b/example-source/msp432p401r/src/eusci_a1/ucax_rxbuf.rs
new file mode 100644
index 0000000..d13ee75
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a1/ucax_rxbuf.rs
@@ -0,0 +1,41 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::UCAXRXBUF {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCRXBUFR {
+    bits: u8,
+}
+impl UCRXBUFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Receive data buffer"]
+    #[inline]
+    pub fn ucrxbuf(&self) -> UCRXBUFR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCRXBUFR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a1/ucax_statw.rs b/example-source/msp432p401r/src/eusci_a1/ucax_statw.rs
new file mode 100644
index 0000000..8992e75
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a1/ucax_statw.rs
@@ -0,0 +1,893 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXSTATW {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCBUSY`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBUSYR {
+    #[doc = "eUSCI_A inactive"]
+    UCBUSY_0,
+    #[doc = "eUSCI_A transmitting or receiving"]
+    UCBUSY_1,
+}
+impl UCBUSYR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBUSYR::UCBUSY_0 => false,
+            UCBUSYR::UCBUSY_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBUSYR {
+        match value {
+            false => UCBUSYR::UCBUSY_0,
+            true => UCBUSYR::UCBUSY_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBUSY_0`"]
+    #[inline]
+    pub fn is_ucbusy_0(&self) -> bool {
+        *self == UCBUSYR::UCBUSY_0
+    }
+    #[doc = "Checks if the value of the field is `UCBUSY_1`"]
+    #[inline]
+    pub fn is_ucbusy_1(&self) -> bool {
+        *self == UCBUSYR::UCBUSY_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCADDR_UCIDLER {
+    bits: bool,
+}
+impl UCADDR_UCIDLER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `UCRXERR`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXERRR {
+    #[doc = "No receive errors detected"]
+    UCRXERR_0,
+    #[doc = "Receive error detected"]
+    UCRXERR_1,
+}
+impl UCRXERRR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXERRR::UCRXERR_0 => false,
+            UCRXERRR::UCRXERR_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXERRR {
+        match value {
+            false => UCRXERRR::UCRXERR_0,
+            true => UCRXERRR::UCRXERR_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXERR_0`"]
+    #[inline]
+    pub fn is_ucrxerr_0(&self) -> bool {
+        *self == UCRXERRR::UCRXERR_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXERR_1`"]
+    #[inline]
+    pub fn is_ucrxerr_1(&self) -> bool {
+        *self == UCRXERRR::UCRXERR_1
+    }
+}
+#[doc = "Possible values of the field `UCBRK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBRKR {
+    #[doc = "No break condition"]
+    UCBRK_0,
+    #[doc = "Break condition occurred"]
+    UCBRK_1,
+}
+impl UCBRKR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBRKR::UCBRK_0 => false,
+            UCBRKR::UCBRK_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBRKR {
+        match value {
+            false => UCBRKR::UCBRK_0,
+            true => UCBRKR::UCBRK_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBRK_0`"]
+    #[inline]
+    pub fn is_ucbrk_0(&self) -> bool {
+        *self == UCBRKR::UCBRK_0
+    }
+    #[doc = "Checks if the value of the field is `UCBRK_1`"]
+    #[inline]
+    pub fn is_ucbrk_1(&self) -> bool {
+        *self == UCBRKR::UCBRK_1
+    }
+}
+#[doc = "Possible values of the field `UCPE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCPER {
+    #[doc = "No error"]
+    UCPE_0,
+    #[doc = "Character received with parity error"]
+    UCPE_1,
+}
+impl UCPER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCPER::UCPE_0 => false,
+            UCPER::UCPE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCPER {
+        match value {
+            false => UCPER::UCPE_0,
+            true => UCPER::UCPE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCPE_0`"]
+    #[inline]
+    pub fn is_ucpe_0(&self) -> bool {
+        *self == UCPER::UCPE_0
+    }
+    #[doc = "Checks if the value of the field is `UCPE_1`"]
+    #[inline]
+    pub fn is_ucpe_1(&self) -> bool {
+        *self == UCPER::UCPE_1
+    }
+}
+#[doc = "Possible values of the field `UCOE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCOER {
+    #[doc = "No error"]
+    UCOE_0,
+    #[doc = "Overrun error occurred"]
+    UCOE_1,
+}
+impl UCOER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCOER::UCOE_0 => false,
+            UCOER::UCOE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCOER {
+        match value {
+            false => UCOER::UCOE_0,
+            true => UCOER::UCOE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCOE_0`"]
+    #[inline]
+    pub fn is_ucoe_0(&self) -> bool {
+        *self == UCOER::UCOE_0
+    }
+    #[doc = "Checks if the value of the field is `UCOE_1`"]
+    #[inline]
+    pub fn is_ucoe_1(&self) -> bool {
+        *self == UCOER::UCOE_1
+    }
+}
+#[doc = "Possible values of the field `UCFE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCFER {
+    #[doc = "No error"]
+    UCFE_0,
+    #[doc = "Character received with low stop bit"]
+    UCFE_1,
+}
+impl UCFER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCFER::UCFE_0 => false,
+            UCFER::UCFE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCFER {
+        match value {
+            false => UCFER::UCFE_0,
+            true => UCFER::UCFE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCFE_0`"]
+    #[inline]
+    pub fn is_ucfe_0(&self) -> bool {
+        *self == UCFER::UCFE_0
+    }
+    #[doc = "Checks if the value of the field is `UCFE_1`"]
+    #[inline]
+    pub fn is_ucfe_1(&self) -> bool {
+        *self == UCFER::UCFE_1
+    }
+}
+#[doc = "Possible values of the field `UCLISTEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCLISTENR {
+    #[doc = "Disabled"]
+    UCLISTEN_0,
+    #[doc = "Enabled. UCAxTXD is internally fed back to the receiver"]
+    UCLISTEN_1,
+}
+impl UCLISTENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCLISTENR::UCLISTEN_0 => false,
+            UCLISTENR::UCLISTEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCLISTENR {
+        match value {
+            false => UCLISTENR::UCLISTEN_0,
+            true => UCLISTENR::UCLISTEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCLISTEN_0`"]
+    #[inline]
+    pub fn is_uclisten_0(&self) -> bool {
+        *self == UCLISTENR::UCLISTEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCLISTEN_1`"]
+    #[inline]
+    pub fn is_uclisten_1(&self) -> bool {
+        *self == UCLISTENR::UCLISTEN_1
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCADDR_UCIDLEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCADDR_UCIDLEW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXERR`"]
+pub enum UCRXERRW {
+    #[doc = "No receive errors detected"]
+    UCRXERR_0,
+    #[doc = "Receive error detected"]
+    UCRXERR_1,
+}
+impl UCRXERRW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXERRW::UCRXERR_0 => false,
+            UCRXERRW::UCRXERR_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXERRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXERRW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXERRW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No receive errors detected"]
+    #[inline]
+    pub fn ucrxerr_0(self) -> &'a mut W {
+        self.variant(UCRXERRW::UCRXERR_0)
+    }
+    #[doc = "Receive error detected"]
+    #[inline]
+    pub fn ucrxerr_1(self) -> &'a mut W {
+        self.variant(UCRXERRW::UCRXERR_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCBRK`"]
+pub enum UCBRKW {
+    #[doc = "No break condition"]
+    UCBRK_0,
+    #[doc = "Break condition occurred"]
+    UCBRK_1,
+}
+impl UCBRKW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCBRKW::UCBRK_0 => false,
+            UCBRKW::UCBRK_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBRKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBRKW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCBRKW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No break condition"]
+    #[inline]
+    pub fn ucbrk_0(self) -> &'a mut W {
+        self.variant(UCBRKW::UCBRK_0)
+    }
+    #[doc = "Break condition occurred"]
+    #[inline]
+    pub fn ucbrk_1(self) -> &'a mut W {
+        self.variant(UCBRKW::UCBRK_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCPE`"]
+pub enum UCPEW {
+    #[doc = "No error"]
+    UCPE_0,
+    #[doc = "Character received with parity error"]
+    UCPE_1,
+}
+impl UCPEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCPEW::UCPE_0 => false,
+            UCPEW::UCPE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCPEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCPEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCPEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No error"]
+    #[inline]
+    pub fn ucpe_0(self) -> &'a mut W {
+        self.variant(UCPEW::UCPE_0)
+    }
+    #[doc = "Character received with parity error"]
+    #[inline]
+    pub fn ucpe_1(self) -> &'a mut W {
+        self.variant(UCPEW::UCPE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCOE`"]
+pub enum UCOEW {
+    #[doc = "No error"]
+    UCOE_0,
+    #[doc = "Overrun error occurred"]
+    UCOE_1,
+}
+impl UCOEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCOEW::UCOE_0 => false,
+            UCOEW::UCOE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCOEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCOEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCOEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No error"]
+    #[inline]
+    pub fn ucoe_0(self) -> &'a mut W {
+        self.variant(UCOEW::UCOE_0)
+    }
+    #[doc = "Overrun error occurred"]
+    #[inline]
+    pub fn ucoe_1(self) -> &'a mut W {
+        self.variant(UCOEW::UCOE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCFE`"]
+pub enum UCFEW {
+    #[doc = "No error"]
+    UCFE_0,
+    #[doc = "Character received with low stop bit"]
+    UCFE_1,
+}
+impl UCFEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCFEW::UCFE_0 => false,
+            UCFEW::UCFE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCFEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCFEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCFEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No error"]
+    #[inline]
+    pub fn ucfe_0(self) -> &'a mut W {
+        self.variant(UCFEW::UCFE_0)
+    }
+    #[doc = "Character received with low stop bit"]
+    #[inline]
+    pub fn ucfe_1(self) -> &'a mut W {
+        self.variant(UCFEW::UCFE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCLISTEN`"]
+pub enum UCLISTENW {
+    #[doc = "Disabled"]
+    UCLISTEN_0,
+    #[doc = "Enabled. UCAxTXD is internally fed back to the receiver"]
+    UCLISTEN_1,
+}
+impl UCLISTENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCLISTENW::UCLISTEN_0 => false,
+            UCLISTENW::UCLISTEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCLISTENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCLISTENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCLISTENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disabled"]
+    #[inline]
+    pub fn uclisten_0(self) -> &'a mut W {
+        self.variant(UCLISTENW::UCLISTEN_0)
+    }
+    #[doc = "Enabled. UCAxTXD is internally fed back to the receiver"]
+    #[inline]
+    pub fn uclisten_1(self) -> &'a mut W {
+        self.variant(UCLISTENW::UCLISTEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - eUSCI_A busy"]
+    #[inline]
+    pub fn ucbusy(&self) -> UCBUSYR {
+        UCBUSYR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Address received / Idle line detected"]
+    #[inline]
+    pub fn ucaddr_ucidle(&self) -> UCADDR_UCIDLER {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        };
+        UCADDR_UCIDLER { bits }
+    }
+    #[doc = "Bit 2 - Receive error flag"]
+    #[inline]
+    pub fn ucrxerr(&self) -> UCRXERRR {
+        UCRXERRR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Break detect flag"]
+    #[inline]
+    pub fn ucbrk(&self) -> UCBRKR {
+        UCBRKR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 4 - Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read."]
+    #[inline]
+    pub fn ucpe(&self) -> UCPER {
+        UCPER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - Overrun error flag"]
+    #[inline]
+    pub fn ucoe(&self) -> UCOER {
+        UCOER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 6 - Framing error flag"]
+    #[inline]
+    pub fn ucfe(&self) -> UCFER {
+        UCFER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 7 - Listen enable"]
+    #[inline]
+    pub fn uclisten(&self) -> UCLISTENR {
+        UCLISTENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 1 - Address received / Idle line detected"]
+    #[inline]
+    pub fn ucaddr_ucidle(&mut self) -> _UCADDR_UCIDLEW {
+        _UCADDR_UCIDLEW { w: self }
+    }
+    #[doc = "Bit 2 - Receive error flag"]
+    #[inline]
+    pub fn ucrxerr(&mut self) -> _UCRXERRW {
+        _UCRXERRW { w: self }
+    }
+    #[doc = "Bit 3 - Break detect flag"]
+    #[inline]
+    pub fn ucbrk(&mut self) -> _UCBRKW {
+        _UCBRKW { w: self }
+    }
+    #[doc = "Bit 4 - Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read."]
+    #[inline]
+    pub fn ucpe(&mut self) -> _UCPEW {
+        _UCPEW { w: self }
+    }
+    #[doc = "Bit 5 - Overrun error flag"]
+    #[inline]
+    pub fn ucoe(&mut self) -> _UCOEW {
+        _UCOEW { w: self }
+    }
+    #[doc = "Bit 6 - Framing error flag"]
+    #[inline]
+    pub fn ucfe(&mut self) -> _UCFEW {
+        _UCFEW { w: self }
+    }
+    #[doc = "Bit 7 - Listen enable"]
+    #[inline]
+    pub fn uclisten(&mut self) -> _UCLISTENW {
+        _UCLISTENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a1/ucax_txbuf.rs b/example-source/msp432p401r/src/eusci_a1/ucax_txbuf.rs
new file mode 100644
index 0000000..47ca264
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a1/ucax_txbuf.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXTXBUF {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCTXBUFR {
+    bits: u8,
+}
+impl UCTXBUFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXBUFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXBUFW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Transmit data buffer"]
+    #[inline]
+    pub fn uctxbuf(&self) -> UCTXBUFR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCTXBUFR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Transmit data buffer"]
+    #[inline]
+    pub fn uctxbuf(&mut self) -> _UCTXBUFW {
+        _UCTXBUFW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a2.rs b/example-source/msp432p401r/src/eusci_a2.rs
new file mode 100644
index 0000000..88b0e5e
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a2.rs
@@ -0,0 +1,102 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - eUSCI_Ax Control Word Register 0"]
+    pub ucax_ctlw0: UCAXCTLW0,
+    #[doc = "0x02 - eUSCI_Ax Control Word Register 1"]
+    pub ucax_ctlw1: UCAXCTLW1,
+    _reserved0: [u8; 2usize],
+    #[doc = "0x06 - eUSCI_Ax Baud Rate Control Word Register"]
+    pub ucax_brw: UCAXBRW,
+    #[doc = "0x08 - eUSCI_Ax Modulation Control Word Register"]
+    pub ucax_mctlw: UCAXMCTLW,
+    #[doc = "0x0a - eUSCI_Ax Status Register"]
+    pub ucax_statw: UCAXSTATW,
+    #[doc = "0x0c - eUSCI_Ax Receive Buffer Register"]
+    pub ucax_rxbuf: UCAXRXBUF,
+    #[doc = "0x0e - eUSCI_Ax Transmit Buffer Register"]
+    pub ucax_txbuf: UCAXTXBUF,
+    #[doc = "0x10 - eUSCI_Ax Auto Baud Rate Control Register"]
+    pub ucax_abctl: UCAXABCTL,
+    #[doc = "0x12 - eUSCI_Ax IrDA Control Word Register"]
+    pub ucax_irctl: UCAXIRCTL,
+    _reserved1: [u8; 6usize],
+    #[doc = "0x1a - eUSCI_Ax Interrupt Enable Register"]
+    pub ucax_ie: UCAXIE,
+    #[doc = "0x1c - eUSCI_Ax Interrupt Flag Register"]
+    pub ucax_ifg: UCAXIFG,
+    #[doc = "0x1e - eUSCI_Ax Interrupt Vector Register"]
+    pub ucax_iv: UCAXIV,
+}
+#[doc = "eUSCI_Ax Control Word Register 0"]
+pub struct UCAXCTLW0 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Control Word Register 0"]
+pub mod ucax_ctlw0;
+#[doc = "eUSCI_Ax Control Word Register 1"]
+pub struct UCAXCTLW1 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Control Word Register 1"]
+pub mod ucax_ctlw1;
+#[doc = "eUSCI_Ax Baud Rate Control Word Register"]
+pub struct UCAXBRW {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Baud Rate Control Word Register"]
+pub mod ucax_brw;
+#[doc = "eUSCI_Ax Modulation Control Word Register"]
+pub struct UCAXMCTLW {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Modulation Control Word Register"]
+pub mod ucax_mctlw;
+#[doc = "eUSCI_Ax Status Register"]
+pub struct UCAXSTATW {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Status Register"]
+pub mod ucax_statw;
+#[doc = "eUSCI_Ax Receive Buffer Register"]
+pub struct UCAXRXBUF {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Receive Buffer Register"]
+pub mod ucax_rxbuf;
+#[doc = "eUSCI_Ax Transmit Buffer Register"]
+pub struct UCAXTXBUF {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Transmit Buffer Register"]
+pub mod ucax_txbuf;
+#[doc = "eUSCI_Ax Auto Baud Rate Control Register"]
+pub struct UCAXABCTL {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Auto Baud Rate Control Register"]
+pub mod ucax_abctl;
+#[doc = "eUSCI_Ax IrDA Control Word Register"]
+pub struct UCAXIRCTL {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax IrDA Control Word Register"]
+pub mod ucax_irctl;
+#[doc = "eUSCI_Ax Interrupt Enable Register"]
+pub struct UCAXIE {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Interrupt Enable Register"]
+pub mod ucax_ie;
+#[doc = "eUSCI_Ax Interrupt Flag Register"]
+pub struct UCAXIFG {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Interrupt Flag Register"]
+pub mod ucax_ifg;
+#[doc = "eUSCI_Ax Interrupt Vector Register"]
+pub struct UCAXIV {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Interrupt Vector Register"]
+pub mod ucax_iv;
diff --git a/example-source/msp432p401r/src/eusci_a2/ucax_abctl.rs b/example-source/msp432p401r/src/eusci_a2/ucax_abctl.rs
new file mode 100644
index 0000000..ce574eb
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a2/ucax_abctl.rs
@@ -0,0 +1,557 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXABCTL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCABDEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCABDENR {
+    #[doc = "Baud-rate detection disabled. Length of break and synch field is not measured."]
+    UCABDEN_0,
+    #[doc = "Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly."]
+    UCABDEN_1,
+}
+impl UCABDENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCABDENR::UCABDEN_0 => false,
+            UCABDENR::UCABDEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCABDENR {
+        match value {
+            false => UCABDENR::UCABDEN_0,
+            true => UCABDENR::UCABDEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCABDEN_0`"]
+    #[inline]
+    pub fn is_ucabden_0(&self) -> bool {
+        *self == UCABDENR::UCABDEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCABDEN_1`"]
+    #[inline]
+    pub fn is_ucabden_1(&self) -> bool {
+        *self == UCABDENR::UCABDEN_1
+    }
+}
+#[doc = "Possible values of the field `UCBTOE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBTOER {
+    #[doc = "No error"]
+    UCBTOE_0,
+    #[doc = "Length of break field exceeded 22 bit times"]
+    UCBTOE_1,
+}
+impl UCBTOER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBTOER::UCBTOE_0 => false,
+            UCBTOER::UCBTOE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBTOER {
+        match value {
+            false => UCBTOER::UCBTOE_0,
+            true => UCBTOER::UCBTOE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBTOE_0`"]
+    #[inline]
+    pub fn is_ucbtoe_0(&self) -> bool {
+        *self == UCBTOER::UCBTOE_0
+    }
+    #[doc = "Checks if the value of the field is `UCBTOE_1`"]
+    #[inline]
+    pub fn is_ucbtoe_1(&self) -> bool {
+        *self == UCBTOER::UCBTOE_1
+    }
+}
+#[doc = "Possible values of the field `UCSTOE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTOER {
+    #[doc = "No error"]
+    UCSTOE_0,
+    #[doc = "Length of synch field exceeded measurable time"]
+    UCSTOE_1,
+}
+impl UCSTOER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTOER::UCSTOE_0 => false,
+            UCSTOER::UCSTOE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTOER {
+        match value {
+            false => UCSTOER::UCSTOE_0,
+            true => UCSTOER::UCSTOE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTOE_0`"]
+    #[inline]
+    pub fn is_ucstoe_0(&self) -> bool {
+        *self == UCSTOER::UCSTOE_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTOE_1`"]
+    #[inline]
+    pub fn is_ucstoe_1(&self) -> bool {
+        *self == UCSTOER::UCSTOE_1
+    }
+}
+#[doc = "Possible values of the field `UCDELIM`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCDELIMR {
+    #[doc = "1 bit time"]
+    UCDELIM_0,
+    #[doc = "2 bit times"]
+    UCDELIM_1,
+    #[doc = "3 bit times"]
+    UCDELIM_2,
+    #[doc = "4 bit times"]
+    UCDELIM_3,
+}
+impl UCDELIMR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCDELIMR::UCDELIM_0 => 0,
+            UCDELIMR::UCDELIM_1 => 1,
+            UCDELIMR::UCDELIM_2 => 2,
+            UCDELIMR::UCDELIM_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCDELIMR {
+        match value {
+            0 => UCDELIMR::UCDELIM_0,
+            1 => UCDELIMR::UCDELIM_1,
+            2 => UCDELIMR::UCDELIM_2,
+            3 => UCDELIMR::UCDELIM_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCDELIM_0`"]
+    #[inline]
+    pub fn is_ucdelim_0(&self) -> bool {
+        *self == UCDELIMR::UCDELIM_0
+    }
+    #[doc = "Checks if the value of the field is `UCDELIM_1`"]
+    #[inline]
+    pub fn is_ucdelim_1(&self) -> bool {
+        *self == UCDELIMR::UCDELIM_1
+    }
+    #[doc = "Checks if the value of the field is `UCDELIM_2`"]
+    #[inline]
+    pub fn is_ucdelim_2(&self) -> bool {
+        *self == UCDELIMR::UCDELIM_2
+    }
+    #[doc = "Checks if the value of the field is `UCDELIM_3`"]
+    #[inline]
+    pub fn is_ucdelim_3(&self) -> bool {
+        *self == UCDELIMR::UCDELIM_3
+    }
+}
+#[doc = "Values that can be written to the field `UCABDEN`"]
+pub enum UCABDENW {
+    #[doc = "Baud-rate detection disabled. Length of break and synch field is not measured."]
+    UCABDEN_0,
+    #[doc = "Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly."]
+    UCABDEN_1,
+}
+impl UCABDENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCABDENW::UCABDEN_0 => false,
+            UCABDENW::UCABDEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCABDENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCABDENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCABDENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Baud-rate detection disabled. Length of break and synch field is not measured."]
+    #[inline]
+    pub fn ucabden_0(self) -> &'a mut W {
+        self.variant(UCABDENW::UCABDEN_0)
+    }
+    #[doc = "Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly."]
+    #[inline]
+    pub fn ucabden_1(self) -> &'a mut W {
+        self.variant(UCABDENW::UCABDEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCBTOE`"]
+pub enum UCBTOEW {
+    #[doc = "No error"]
+    UCBTOE_0,
+    #[doc = "Length of break field exceeded 22 bit times"]
+    UCBTOE_1,
+}
+impl UCBTOEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCBTOEW::UCBTOE_0 => false,
+            UCBTOEW::UCBTOE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBTOEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBTOEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCBTOEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No error"]
+    #[inline]
+    pub fn ucbtoe_0(self) -> &'a mut W {
+        self.variant(UCBTOEW::UCBTOE_0)
+    }
+    #[doc = "Length of break field exceeded 22 bit times"]
+    #[inline]
+    pub fn ucbtoe_1(self) -> &'a mut W {
+        self.variant(UCBTOEW::UCBTOE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTOE`"]
+pub enum UCSTOEW {
+    #[doc = "No error"]
+    UCSTOE_0,
+    #[doc = "Length of synch field exceeded measurable time"]
+    UCSTOE_1,
+}
+impl UCSTOEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTOEW::UCSTOE_0 => false,
+            UCSTOEW::UCSTOE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTOEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTOEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTOEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No error"]
+    #[inline]
+    pub fn ucstoe_0(self) -> &'a mut W {
+        self.variant(UCSTOEW::UCSTOE_0)
+    }
+    #[doc = "Length of synch field exceeded measurable time"]
+    #[inline]
+    pub fn ucstoe_1(self) -> &'a mut W {
+        self.variant(UCSTOEW::UCSTOE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCDELIM`"]
+pub enum UCDELIMW {
+    #[doc = "1 bit time"]
+    UCDELIM_0,
+    #[doc = "2 bit times"]
+    UCDELIM_1,
+    #[doc = "3 bit times"]
+    UCDELIM_2,
+    #[doc = "4 bit times"]
+    UCDELIM_3,
+}
+impl UCDELIMW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCDELIMW::UCDELIM_0 => 0,
+            UCDELIMW::UCDELIM_1 => 1,
+            UCDELIMW::UCDELIM_2 => 2,
+            UCDELIMW::UCDELIM_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCDELIMW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCDELIMW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCDELIMW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "1 bit time"]
+    #[inline]
+    pub fn ucdelim_0(self) -> &'a mut W {
+        self.variant(UCDELIMW::UCDELIM_0)
+    }
+    #[doc = "2 bit times"]
+    #[inline]
+    pub fn ucdelim_1(self) -> &'a mut W {
+        self.variant(UCDELIMW::UCDELIM_1)
+    }
+    #[doc = "3 bit times"]
+    #[inline]
+    pub fn ucdelim_2(self) -> &'a mut W {
+        self.variant(UCDELIMW::UCDELIM_2)
+    }
+    #[doc = "4 bit times"]
+    #[inline]
+    pub fn ucdelim_3(self) -> &'a mut W {
+        self.variant(UCDELIMW::UCDELIM_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Automatic baud-rate detect enable"]
+    #[inline]
+    pub fn ucabden(&self) -> UCABDENR {
+        UCABDENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - Break time out error"]
+    #[inline]
+    pub fn ucbtoe(&self) -> UCBTOER {
+        UCBTOER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Synch field time out error"]
+    #[inline]
+    pub fn ucstoe(&self) -> UCSTOER {
+        UCSTOER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 4:5 - Break/synch delimiter length"]
+    #[inline]
+    pub fn ucdelim(&self) -> UCDELIMR {
+        UCDELIMR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Automatic baud-rate detect enable"]
+    #[inline]
+    pub fn ucabden(&mut self) -> _UCABDENW {
+        _UCABDENW { w: self }
+    }
+    #[doc = "Bit 2 - Break time out error"]
+    #[inline]
+    pub fn ucbtoe(&mut self) -> _UCBTOEW {
+        _UCBTOEW { w: self }
+    }
+    #[doc = "Bit 3 - Synch field time out error"]
+    #[inline]
+    pub fn ucstoe(&mut self) -> _UCSTOEW {
+        _UCSTOEW { w: self }
+    }
+    #[doc = "Bits 4:5 - Break/synch delimiter length"]
+    #[inline]
+    pub fn ucdelim(&mut self) -> _UCDELIMW {
+        _UCDELIMW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a2/ucax_brw.rs b/example-source/msp432p401r/src/eusci_a2/ucax_brw.rs
new file mode 100644
index 0000000..c9b1b2a
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a2/ucax_brw.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXBRW {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCBRR {
+    bits: u16,
+}
+impl UCBRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBRW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Clock prescaler setting of the Baud rate generator"]
+    #[inline]
+    pub fn ucbr(&self) -> UCBRR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        UCBRR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Clock prescaler setting of the Baud rate generator"]
+    #[inline]
+    pub fn ucbr(&mut self) -> _UCBRW {
+        _UCBRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a2/ucax_ctlw0.rs b/example-source/msp432p401r/src/eusci_a2/ucax_ctlw0.rs
new file mode 100644
index 0000000..aa44348
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a2/ucax_ctlw0.rs
@@ -0,0 +1,1748 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXCTLW0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCSWRST`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSWRSTR {
+    #[doc = "Disabled. eUSCI_A reset released for operation"]
+    UCSWRST_0,
+    #[doc = "Enabled. eUSCI_A logic held in reset state"]
+    UCSWRST_1,
+}
+impl UCSWRSTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSWRSTR::UCSWRST_0 => false,
+            UCSWRSTR::UCSWRST_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSWRSTR {
+        match value {
+            false => UCSWRSTR::UCSWRST_0,
+            true => UCSWRSTR::UCSWRST_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSWRST_0`"]
+    #[inline]
+    pub fn is_ucswrst_0(&self) -> bool {
+        *self == UCSWRSTR::UCSWRST_0
+    }
+    #[doc = "Checks if the value of the field is `UCSWRST_1`"]
+    #[inline]
+    pub fn is_ucswrst_1(&self) -> bool {
+        *self == UCSWRSTR::UCSWRST_1
+    }
+}
+#[doc = "Possible values of the field `UCTXBRK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXBRKR {
+    #[doc = "Next frame transmitted is not a break"]
+    UCTXBRK_0,
+    #[doc = "Next frame transmitted is a break or a break/synch"]
+    UCTXBRK_1,
+}
+impl UCTXBRKR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXBRKR::UCTXBRK_0 => false,
+            UCTXBRKR::UCTXBRK_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXBRKR {
+        match value {
+            false => UCTXBRKR::UCTXBRK_0,
+            true => UCTXBRKR::UCTXBRK_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXBRK_0`"]
+    #[inline]
+    pub fn is_uctxbrk_0(&self) -> bool {
+        *self == UCTXBRKR::UCTXBRK_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXBRK_1`"]
+    #[inline]
+    pub fn is_uctxbrk_1(&self) -> bool {
+        *self == UCTXBRKR::UCTXBRK_1
+    }
+}
+#[doc = "Possible values of the field `UCTXADDR`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXADDRR {
+    #[doc = "Next frame transmitted is data"]
+    UCTXADDR_0,
+    #[doc = "Next frame transmitted is an address"]
+    UCTXADDR_1,
+}
+impl UCTXADDRR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXADDRR::UCTXADDR_0 => false,
+            UCTXADDRR::UCTXADDR_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXADDRR {
+        match value {
+            false => UCTXADDRR::UCTXADDR_0,
+            true => UCTXADDRR::UCTXADDR_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXADDR_0`"]
+    #[inline]
+    pub fn is_uctxaddr_0(&self) -> bool {
+        *self == UCTXADDRR::UCTXADDR_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXADDR_1`"]
+    #[inline]
+    pub fn is_uctxaddr_1(&self) -> bool {
+        *self == UCTXADDRR::UCTXADDR_1
+    }
+}
+#[doc = "Possible values of the field `UCDORM`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCDORMR {
+    #[doc = "Not dormant. All received characters set UCRXIFG."]
+    UCDORM_0,
+    #[doc = "Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG."]
+    UCDORM_1,
+}
+impl UCDORMR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCDORMR::UCDORM_0 => false,
+            UCDORMR::UCDORM_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCDORMR {
+        match value {
+            false => UCDORMR::UCDORM_0,
+            true => UCDORMR::UCDORM_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCDORM_0`"]
+    #[inline]
+    pub fn is_ucdorm_0(&self) -> bool {
+        *self == UCDORMR::UCDORM_0
+    }
+    #[doc = "Checks if the value of the field is `UCDORM_1`"]
+    #[inline]
+    pub fn is_ucdorm_1(&self) -> bool {
+        *self == UCDORMR::UCDORM_1
+    }
+}
+#[doc = "Possible values of the field `UCBRKIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBRKIER {
+    #[doc = "Received break characters do not set UCRXIFG"]
+    UCBRKIE_0,
+    #[doc = "Received break characters set UCRXIFG"]
+    UCBRKIE_1,
+}
+impl UCBRKIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBRKIER::UCBRKIE_0 => false,
+            UCBRKIER::UCBRKIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBRKIER {
+        match value {
+            false => UCBRKIER::UCBRKIE_0,
+            true => UCBRKIER::UCBRKIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBRKIE_0`"]
+    #[inline]
+    pub fn is_ucbrkie_0(&self) -> bool {
+        *self == UCBRKIER::UCBRKIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCBRKIE_1`"]
+    #[inline]
+    pub fn is_ucbrkie_1(&self) -> bool {
+        *self == UCBRKIER::UCBRKIE_1
+    }
+}
+#[doc = "Possible values of the field `UCRXEIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXEIER {
+    #[doc = "Erroneous characters rejected and UCRXIFG is not set"]
+    UCRXEIE_0,
+    #[doc = "Erroneous characters received set UCRXIFG"]
+    UCRXEIE_1,
+}
+impl UCRXEIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXEIER::UCRXEIE_0 => false,
+            UCRXEIER::UCRXEIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXEIER {
+        match value {
+            false => UCRXEIER::UCRXEIE_0,
+            true => UCRXEIER::UCRXEIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXEIE_0`"]
+    #[inline]
+    pub fn is_ucrxeie_0(&self) -> bool {
+        *self == UCRXEIER::UCRXEIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXEIE_1`"]
+    #[inline]
+    pub fn is_ucrxeie_1(&self) -> bool {
+        *self == UCRXEIER::UCRXEIE_1
+    }
+}
+#[doc = "Possible values of the field `UCSSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSSELR {
+    #[doc = "UCLK"]
+    UCSSEL_0,
+    #[doc = "ACLK"]
+    UCSSEL_1,
+    #[doc = "SMCLK"]
+    UCSSEL_2,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl UCSSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCSSELR::UCSSEL_0 => 0,
+            UCSSELR::UCSSEL_1 => 1,
+            UCSSELR::UCSSEL_2 => 2,
+            UCSSELR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCSSELR {
+        match value {
+            0 => UCSSELR::UCSSEL_0,
+            1 => UCSSELR::UCSSEL_1,
+            2 => UCSSELR::UCSSEL_2,
+            i => UCSSELR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSSEL_0`"]
+    #[inline]
+    pub fn is_ucssel_0(&self) -> bool {
+        *self == UCSSELR::UCSSEL_0
+    }
+    #[doc = "Checks if the value of the field is `UCSSEL_1`"]
+    #[inline]
+    pub fn is_ucssel_1(&self) -> bool {
+        *self == UCSSELR::UCSSEL_1
+    }
+    #[doc = "Checks if the value of the field is `UCSSEL_2`"]
+    #[inline]
+    pub fn is_ucssel_2(&self) -> bool {
+        *self == UCSSELR::UCSSEL_2
+    }
+}
+#[doc = "Possible values of the field `UCSYNC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSYNCR {
+    #[doc = "Asynchronous mode"]
+    UCSYNC_0,
+    #[doc = "Synchronous mode"]
+    UCSYNC_1,
+}
+impl UCSYNCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSYNCR::UCSYNC_0 => false,
+            UCSYNCR::UCSYNC_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSYNCR {
+        match value {
+            false => UCSYNCR::UCSYNC_0,
+            true => UCSYNCR::UCSYNC_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSYNC_0`"]
+    #[inline]
+    pub fn is_ucsync_0(&self) -> bool {
+        *self == UCSYNCR::UCSYNC_0
+    }
+    #[doc = "Checks if the value of the field is `UCSYNC_1`"]
+    #[inline]
+    pub fn is_ucsync_1(&self) -> bool {
+        *self == UCSYNCR::UCSYNC_1
+    }
+}
+#[doc = "Possible values of the field `UCMODE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCMODER {
+    #[doc = "UART mode"]
+    UCMODE_0,
+    #[doc = "Idle-line multiprocessor mode"]
+    UCMODE_1,
+    #[doc = "Address-bit multiprocessor mode"]
+    UCMODE_2,
+    #[doc = "UART mode with automatic baud-rate detection"]
+    UCMODE_3,
+}
+impl UCMODER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCMODER::UCMODE_0 => 0,
+            UCMODER::UCMODE_1 => 1,
+            UCMODER::UCMODE_2 => 2,
+            UCMODER::UCMODE_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCMODER {
+        match value {
+            0 => UCMODER::UCMODE_0,
+            1 => UCMODER::UCMODE_1,
+            2 => UCMODER::UCMODE_2,
+            3 => UCMODER::UCMODE_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_0`"]
+    #[inline]
+    pub fn is_ucmode_0(&self) -> bool {
+        *self == UCMODER::UCMODE_0
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_1`"]
+    #[inline]
+    pub fn is_ucmode_1(&self) -> bool {
+        *self == UCMODER::UCMODE_1
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_2`"]
+    #[inline]
+    pub fn is_ucmode_2(&self) -> bool {
+        *self == UCMODER::UCMODE_2
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_3`"]
+    #[inline]
+    pub fn is_ucmode_3(&self) -> bool {
+        *self == UCMODER::UCMODE_3
+    }
+}
+#[doc = "Possible values of the field `UCSPB`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSPBR {
+    #[doc = "One stop bit"]
+    UCSPB_0,
+    #[doc = "Two stop bits"]
+    UCSPB_1,
+}
+impl UCSPBR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSPBR::UCSPB_0 => false,
+            UCSPBR::UCSPB_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSPBR {
+        match value {
+            false => UCSPBR::UCSPB_0,
+            true => UCSPBR::UCSPB_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSPB_0`"]
+    #[inline]
+    pub fn is_ucspb_0(&self) -> bool {
+        *self == UCSPBR::UCSPB_0
+    }
+    #[doc = "Checks if the value of the field is `UCSPB_1`"]
+    #[inline]
+    pub fn is_ucspb_1(&self) -> bool {
+        *self == UCSPBR::UCSPB_1
+    }
+}
+#[doc = "Possible values of the field `UC7BIT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UC7BITR {
+    #[doc = "8-bit data"]
+    UC7BIT_0,
+    #[doc = "7-bit data"]
+    UC7BIT_1,
+}
+impl UC7BITR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UC7BITR::UC7BIT_0 => false,
+            UC7BITR::UC7BIT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UC7BITR {
+        match value {
+            false => UC7BITR::UC7BIT_0,
+            true => UC7BITR::UC7BIT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UC7BIT_0`"]
+    #[inline]
+    pub fn is_uc7bit_0(&self) -> bool {
+        *self == UC7BITR::UC7BIT_0
+    }
+    #[doc = "Checks if the value of the field is `UC7BIT_1`"]
+    #[inline]
+    pub fn is_uc7bit_1(&self) -> bool {
+        *self == UC7BITR::UC7BIT_1
+    }
+}
+#[doc = "Possible values of the field `UCMSB`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCMSBR {
+    #[doc = "LSB first"]
+    UCMSB_0,
+    #[doc = "MSB first"]
+    UCMSB_1,
+}
+impl UCMSBR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCMSBR::UCMSB_0 => false,
+            UCMSBR::UCMSB_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCMSBR {
+        match value {
+            false => UCMSBR::UCMSB_0,
+            true => UCMSBR::UCMSB_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCMSB_0`"]
+    #[inline]
+    pub fn is_ucmsb_0(&self) -> bool {
+        *self == UCMSBR::UCMSB_0
+    }
+    #[doc = "Checks if the value of the field is `UCMSB_1`"]
+    #[inline]
+    pub fn is_ucmsb_1(&self) -> bool {
+        *self == UCMSBR::UCMSB_1
+    }
+}
+#[doc = "Possible values of the field `UCPAR`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCPARR {
+    #[doc = "Odd parity"]
+    UCPAR_0,
+    #[doc = "Even parity"]
+    UCPAR_1,
+}
+impl UCPARR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCPARR::UCPAR_0 => false,
+            UCPARR::UCPAR_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCPARR {
+        match value {
+            false => UCPARR::UCPAR_0,
+            true => UCPARR::UCPAR_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCPAR_0`"]
+    #[inline]
+    pub fn is_ucpar_0(&self) -> bool {
+        *self == UCPARR::UCPAR_0
+    }
+    #[doc = "Checks if the value of the field is `UCPAR_1`"]
+    #[inline]
+    pub fn is_ucpar_1(&self) -> bool {
+        *self == UCPARR::UCPAR_1
+    }
+}
+#[doc = "Possible values of the field `UCPEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCPENR {
+    #[doc = "Parity disabled"]
+    UCPEN_0,
+    #[doc = "Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation."]
+    UCPEN_1,
+}
+impl UCPENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCPENR::UCPEN_0 => false,
+            UCPENR::UCPEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCPENR {
+        match value {
+            false => UCPENR::UCPEN_0,
+            true => UCPENR::UCPEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCPEN_0`"]
+    #[inline]
+    pub fn is_ucpen_0(&self) -> bool {
+        *self == UCPENR::UCPEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCPEN_1`"]
+    #[inline]
+    pub fn is_ucpen_1(&self) -> bool {
+        *self == UCPENR::UCPEN_1
+    }
+}
+#[doc = "Values that can be written to the field `UCSWRST`"]
+pub enum UCSWRSTW {
+    #[doc = "Disabled. eUSCI_A reset released for operation"]
+    UCSWRST_0,
+    #[doc = "Enabled. eUSCI_A logic held in reset state"]
+    UCSWRST_1,
+}
+impl UCSWRSTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSWRSTW::UCSWRST_0 => false,
+            UCSWRSTW::UCSWRST_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSWRSTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSWRSTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSWRSTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disabled. eUSCI_A reset released for operation"]
+    #[inline]
+    pub fn ucswrst_0(self) -> &'a mut W {
+        self.variant(UCSWRSTW::UCSWRST_0)
+    }
+    #[doc = "Enabled. eUSCI_A logic held in reset state"]
+    #[inline]
+    pub fn ucswrst_1(self) -> &'a mut W {
+        self.variant(UCSWRSTW::UCSWRST_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXBRK`"]
+pub enum UCTXBRKW {
+    #[doc = "Next frame transmitted is not a break"]
+    UCTXBRK_0,
+    #[doc = "Next frame transmitted is a break or a break/synch"]
+    UCTXBRK_1,
+}
+impl UCTXBRKW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXBRKW::UCTXBRK_0 => false,
+            UCTXBRKW::UCTXBRK_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXBRKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXBRKW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXBRKW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Next frame transmitted is not a break"]
+    #[inline]
+    pub fn uctxbrk_0(self) -> &'a mut W {
+        self.variant(UCTXBRKW::UCTXBRK_0)
+    }
+    #[doc = "Next frame transmitted is a break or a break/synch"]
+    #[inline]
+    pub fn uctxbrk_1(self) -> &'a mut W {
+        self.variant(UCTXBRKW::UCTXBRK_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXADDR`"]
+pub enum UCTXADDRW {
+    #[doc = "Next frame transmitted is data"]
+    UCTXADDR_0,
+    #[doc = "Next frame transmitted is an address"]
+    UCTXADDR_1,
+}
+impl UCTXADDRW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXADDRW::UCTXADDR_0 => false,
+            UCTXADDRW::UCTXADDR_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXADDRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXADDRW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXADDRW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Next frame transmitted is data"]
+    #[inline]
+    pub fn uctxaddr_0(self) -> &'a mut W {
+        self.variant(UCTXADDRW::UCTXADDR_0)
+    }
+    #[doc = "Next frame transmitted is an address"]
+    #[inline]
+    pub fn uctxaddr_1(self) -> &'a mut W {
+        self.variant(UCTXADDRW::UCTXADDR_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCDORM`"]
+pub enum UCDORMW {
+    #[doc = "Not dormant. All received characters set UCRXIFG."]
+    UCDORM_0,
+    #[doc = "Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG."]
+    UCDORM_1,
+}
+impl UCDORMW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCDORMW::UCDORM_0 => false,
+            UCDORMW::UCDORM_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCDORMW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCDORMW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCDORMW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Not dormant. All received characters set UCRXIFG."]
+    #[inline]
+    pub fn ucdorm_0(self) -> &'a mut W {
+        self.variant(UCDORMW::UCDORM_0)
+    }
+    #[doc = "Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG."]
+    #[inline]
+    pub fn ucdorm_1(self) -> &'a mut W {
+        self.variant(UCDORMW::UCDORM_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCBRKIE`"]
+pub enum UCBRKIEW {
+    #[doc = "Received break characters do not set UCRXIFG"]
+    UCBRKIE_0,
+    #[doc = "Received break characters set UCRXIFG"]
+    UCBRKIE_1,
+}
+impl UCBRKIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCBRKIEW::UCBRKIE_0 => false,
+            UCBRKIEW::UCBRKIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBRKIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBRKIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCBRKIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Received break characters do not set UCRXIFG"]
+    #[inline]
+    pub fn ucbrkie_0(self) -> &'a mut W {
+        self.variant(UCBRKIEW::UCBRKIE_0)
+    }
+    #[doc = "Received break characters set UCRXIFG"]
+    #[inline]
+    pub fn ucbrkie_1(self) -> &'a mut W {
+        self.variant(UCBRKIEW::UCBRKIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXEIE`"]
+pub enum UCRXEIEW {
+    #[doc = "Erroneous characters rejected and UCRXIFG is not set"]
+    UCRXEIE_0,
+    #[doc = "Erroneous characters received set UCRXIFG"]
+    UCRXEIE_1,
+}
+impl UCRXEIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXEIEW::UCRXEIE_0 => false,
+            UCRXEIEW::UCRXEIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXEIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXEIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXEIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Erroneous characters rejected and UCRXIFG is not set"]
+    #[inline]
+    pub fn ucrxeie_0(self) -> &'a mut W {
+        self.variant(UCRXEIEW::UCRXEIE_0)
+    }
+    #[doc = "Erroneous characters received set UCRXIFG"]
+    #[inline]
+    pub fn ucrxeie_1(self) -> &'a mut W {
+        self.variant(UCRXEIEW::UCRXEIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSSEL`"]
+pub enum UCSSELW {
+    #[doc = "UCLK"]
+    UCSSEL_0,
+    #[doc = "ACLK"]
+    UCSSEL_1,
+    #[doc = "SMCLK"]
+    UCSSEL_2,
+}
+impl UCSSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCSSELW::UCSSEL_0 => 0,
+            UCSSELW::UCSSEL_1 => 1,
+            UCSSELW::UCSSEL_2 => 2,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSSELW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "UCLK"]
+    #[inline]
+    pub fn ucssel_0(self) -> &'a mut W {
+        self.variant(UCSSELW::UCSSEL_0)
+    }
+    #[doc = "ACLK"]
+    #[inline]
+    pub fn ucssel_1(self) -> &'a mut W {
+        self.variant(UCSSELW::UCSSEL_1)
+    }
+    #[doc = "SMCLK"]
+    #[inline]
+    pub fn ucssel_2(self) -> &'a mut W {
+        self.variant(UCSSELW::UCSSEL_2)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSYNC`"]
+pub enum UCSYNCW {
+    #[doc = "Asynchronous mode"]
+    UCSYNC_0,
+    #[doc = "Synchronous mode"]
+    UCSYNC_1,
+}
+impl UCSYNCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSYNCW::UCSYNC_0 => false,
+            UCSYNCW::UCSYNC_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSYNCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSYNCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSYNCW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Asynchronous mode"]
+    #[inline]
+    pub fn ucsync_0(self) -> &'a mut W {
+        self.variant(UCSYNCW::UCSYNC_0)
+    }
+    #[doc = "Synchronous mode"]
+    #[inline]
+    pub fn ucsync_1(self) -> &'a mut W {
+        self.variant(UCSYNCW::UCSYNC_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCMODE`"]
+pub enum UCMODEW {
+    #[doc = "UART mode"]
+    UCMODE_0,
+    #[doc = "Idle-line multiprocessor mode"]
+    UCMODE_1,
+    #[doc = "Address-bit multiprocessor mode"]
+    UCMODE_2,
+    #[doc = "UART mode with automatic baud-rate detection"]
+    UCMODE_3,
+}
+impl UCMODEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCMODEW::UCMODE_0 => 0,
+            UCMODEW::UCMODE_1 => 1,
+            UCMODEW::UCMODE_2 => 2,
+            UCMODEW::UCMODE_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCMODEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCMODEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCMODEW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "UART mode"]
+    #[inline]
+    pub fn ucmode_0(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_0)
+    }
+    #[doc = "Idle-line multiprocessor mode"]
+    #[inline]
+    pub fn ucmode_1(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_1)
+    }
+    #[doc = "Address-bit multiprocessor mode"]
+    #[inline]
+    pub fn ucmode_2(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_2)
+    }
+    #[doc = "UART mode with automatic baud-rate detection"]
+    #[inline]
+    pub fn ucmode_3(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSPB`"]
+pub enum UCSPBW {
+    #[doc = "One stop bit"]
+    UCSPB_0,
+    #[doc = "Two stop bits"]
+    UCSPB_1,
+}
+impl UCSPBW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSPBW::UCSPB_0 => false,
+            UCSPBW::UCSPB_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSPBW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSPBW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSPBW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "One stop bit"]
+    #[inline]
+    pub fn ucspb_0(self) -> &'a mut W {
+        self.variant(UCSPBW::UCSPB_0)
+    }
+    #[doc = "Two stop bits"]
+    #[inline]
+    pub fn ucspb_1(self) -> &'a mut W {
+        self.variant(UCSPBW::UCSPB_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UC7BIT`"]
+pub enum UC7BITW {
+    #[doc = "8-bit data"]
+    UC7BIT_0,
+    #[doc = "7-bit data"]
+    UC7BIT_1,
+}
+impl UC7BITW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UC7BITW::UC7BIT_0 => false,
+            UC7BITW::UC7BIT_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UC7BITW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UC7BITW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UC7BITW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "8-bit data"]
+    #[inline]
+    pub fn uc7bit_0(self) -> &'a mut W {
+        self.variant(UC7BITW::UC7BIT_0)
+    }
+    #[doc = "7-bit data"]
+    #[inline]
+    pub fn uc7bit_1(self) -> &'a mut W {
+        self.variant(UC7BITW::UC7BIT_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCMSB`"]
+pub enum UCMSBW {
+    #[doc = "LSB first"]
+    UCMSB_0,
+    #[doc = "MSB first"]
+    UCMSB_1,
+}
+impl UCMSBW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCMSBW::UCMSB_0 => false,
+            UCMSBW::UCMSB_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCMSBW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCMSBW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCMSBW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "LSB first"]
+    #[inline]
+    pub fn ucmsb_0(self) -> &'a mut W {
+        self.variant(UCMSBW::UCMSB_0)
+    }
+    #[doc = "MSB first"]
+    #[inline]
+    pub fn ucmsb_1(self) -> &'a mut W {
+        self.variant(UCMSBW::UCMSB_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCPAR`"]
+pub enum UCPARW {
+    #[doc = "Odd parity"]
+    UCPAR_0,
+    #[doc = "Even parity"]
+    UCPAR_1,
+}
+impl UCPARW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCPARW::UCPAR_0 => false,
+            UCPARW::UCPAR_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCPARW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCPARW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCPARW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Odd parity"]
+    #[inline]
+    pub fn ucpar_0(self) -> &'a mut W {
+        self.variant(UCPARW::UCPAR_0)
+    }
+    #[doc = "Even parity"]
+    #[inline]
+    pub fn ucpar_1(self) -> &'a mut W {
+        self.variant(UCPARW::UCPAR_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCPEN`"]
+pub enum UCPENW {
+    #[doc = "Parity disabled"]
+    UCPEN_0,
+    #[doc = "Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation."]
+    UCPEN_1,
+}
+impl UCPENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCPENW::UCPEN_0 => false,
+            UCPENW::UCPEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCPENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCPENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCPENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Parity disabled"]
+    #[inline]
+    pub fn ucpen_0(self) -> &'a mut W {
+        self.variant(UCPENW::UCPEN_0)
+    }
+    #[doc = "Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation."]
+    #[inline]
+    pub fn ucpen_1(self) -> &'a mut W {
+        self.variant(UCPENW::UCPEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Software reset enable"]
+    #[inline]
+    pub fn ucswrst(&self) -> UCSWRSTR {
+        UCSWRSTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Transmit break"]
+    #[inline]
+    pub fn uctxbrk(&self) -> UCTXBRKR {
+        UCTXBRKR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - Transmit address"]
+    #[inline]
+    pub fn uctxaddr(&self) -> UCTXADDRR {
+        UCTXADDRR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Dormant"]
+    #[inline]
+    pub fn ucdorm(&self) -> UCDORMR {
+        UCDORMR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 4 - Receive break character interrupt enable"]
+    #[inline]
+    pub fn ucbrkie(&self) -> UCBRKIER {
+        UCBRKIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - Receive erroneous-character interrupt enable"]
+    #[inline]
+    pub fn ucrxeie(&self) -> UCRXEIER {
+        UCRXEIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 6:7 - eUSCI_A clock source select"]
+    #[inline]
+    pub fn ucssel(&self) -> UCSSELR {
+        UCSSELR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 8 - Synchronous mode enable"]
+    #[inline]
+    pub fn ucsync(&self) -> UCSYNCR {
+        UCSYNCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 9:10 - eUSCI_A mode"]
+    #[inline]
+    pub fn ucmode(&self) -> UCMODER {
+        UCMODER::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 11 - Stop bit select"]
+    #[inline]
+    pub fn ucspb(&self) -> UCSPBR {
+        UCSPBR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 12 - Character length"]
+    #[inline]
+    pub fn uc7bit(&self) -> UC7BITR {
+        UC7BITR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 13 - MSB first select"]
+    #[inline]
+    pub fn ucmsb(&self) -> UCMSBR {
+        UCMSBR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 14 - Parity select"]
+    #[inline]
+    pub fn ucpar(&self) -> UCPARR {
+        UCPARR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 15 - Parity enable"]
+    #[inline]
+    pub fn ucpen(&self) -> UCPENR {
+        UCPENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 1 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Software reset enable"]
+    #[inline]
+    pub fn ucswrst(&mut self) -> _UCSWRSTW {
+        _UCSWRSTW { w: self }
+    }
+    #[doc = "Bit 1 - Transmit break"]
+    #[inline]
+    pub fn uctxbrk(&mut self) -> _UCTXBRKW {
+        _UCTXBRKW { w: self }
+    }
+    #[doc = "Bit 2 - Transmit address"]
+    #[inline]
+    pub fn uctxaddr(&mut self) -> _UCTXADDRW {
+        _UCTXADDRW { w: self }
+    }
+    #[doc = "Bit 3 - Dormant"]
+    #[inline]
+    pub fn ucdorm(&mut self) -> _UCDORMW {
+        _UCDORMW { w: self }
+    }
+    #[doc = "Bit 4 - Receive break character interrupt enable"]
+    #[inline]
+    pub fn ucbrkie(&mut self) -> _UCBRKIEW {
+        _UCBRKIEW { w: self }
+    }
+    #[doc = "Bit 5 - Receive erroneous-character interrupt enable"]
+    #[inline]
+    pub fn ucrxeie(&mut self) -> _UCRXEIEW {
+        _UCRXEIEW { w: self }
+    }
+    #[doc = "Bits 6:7 - eUSCI_A clock source select"]
+    #[inline]
+    pub fn ucssel(&mut self) -> _UCSSELW {
+        _UCSSELW { w: self }
+    }
+    #[doc = "Bit 8 - Synchronous mode enable"]
+    #[inline]
+    pub fn ucsync(&mut self) -> _UCSYNCW {
+        _UCSYNCW { w: self }
+    }
+    #[doc = "Bits 9:10 - eUSCI_A mode"]
+    #[inline]
+    pub fn ucmode(&mut self) -> _UCMODEW {
+        _UCMODEW { w: self }
+    }
+    #[doc = "Bit 11 - Stop bit select"]
+    #[inline]
+    pub fn ucspb(&mut self) -> _UCSPBW {
+        _UCSPBW { w: self }
+    }
+    #[doc = "Bit 12 - Character length"]
+    #[inline]
+    pub fn uc7bit(&mut self) -> _UC7BITW {
+        _UC7BITW { w: self }
+    }
+    #[doc = "Bit 13 - MSB first select"]
+    #[inline]
+    pub fn ucmsb(&mut self) -> _UCMSBW {
+        _UCMSBW { w: self }
+    }
+    #[doc = "Bit 14 - Parity select"]
+    #[inline]
+    pub fn ucpar(&mut self) -> _UCPARW {
+        _UCPARW { w: self }
+    }
+    #[doc = "Bit 15 - Parity enable"]
+    #[inline]
+    pub fn ucpen(&mut self) -> _UCPENW {
+        _UCPENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a2/ucax_ctlw1.rs b/example-source/msp432p401r/src/eusci_a2/ucax_ctlw1.rs
new file mode 100644
index 0000000..365cc0d
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a2/ucax_ctlw1.rs
@@ -0,0 +1,200 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXCTLW1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCGLIT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCGLITR {
+    #[doc = "Approximately 2 ns (equivalent of 1 delay element)"]
+    UCGLIT_0,
+    #[doc = "Approximately 50 ns"]
+    UCGLIT_1,
+    #[doc = "Approximately 100 ns"]
+    UCGLIT_2,
+    #[doc = "Approximately 200 ns"]
+    UCGLIT_3,
+}
+impl UCGLITR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCGLITR::UCGLIT_0 => 0,
+            UCGLITR::UCGLIT_1 => 1,
+            UCGLITR::UCGLIT_2 => 2,
+            UCGLITR::UCGLIT_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCGLITR {
+        match value {
+            0 => UCGLITR::UCGLIT_0,
+            1 => UCGLITR::UCGLIT_1,
+            2 => UCGLITR::UCGLIT_2,
+            3 => UCGLITR::UCGLIT_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_0`"]
+    #[inline]
+    pub fn is_ucglit_0(&self) -> bool {
+        *self == UCGLITR::UCGLIT_0
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_1`"]
+    #[inline]
+    pub fn is_ucglit_1(&self) -> bool {
+        *self == UCGLITR::UCGLIT_1
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_2`"]
+    #[inline]
+    pub fn is_ucglit_2(&self) -> bool {
+        *self == UCGLITR::UCGLIT_2
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_3`"]
+    #[inline]
+    pub fn is_ucglit_3(&self) -> bool {
+        *self == UCGLITR::UCGLIT_3
+    }
+}
+#[doc = "Values that can be written to the field `UCGLIT`"]
+pub enum UCGLITW {
+    #[doc = "Approximately 2 ns (equivalent of 1 delay element)"]
+    UCGLIT_0,
+    #[doc = "Approximately 50 ns"]
+    UCGLIT_1,
+    #[doc = "Approximately 100 ns"]
+    UCGLIT_2,
+    #[doc = "Approximately 200 ns"]
+    UCGLIT_3,
+}
+impl UCGLITW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCGLITW::UCGLIT_0 => 0,
+            UCGLITW::UCGLIT_1 => 1,
+            UCGLITW::UCGLIT_2 => 2,
+            UCGLITW::UCGLIT_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCGLITW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCGLITW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCGLITW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Approximately 2 ns (equivalent of 1 delay element)"]
+    #[inline]
+    pub fn ucglit_0(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_0)
+    }
+    #[doc = "Approximately 50 ns"]
+    #[inline]
+    pub fn ucglit_1(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_1)
+    }
+    #[doc = "Approximately 100 ns"]
+    #[inline]
+    pub fn ucglit_2(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_2)
+    }
+    #[doc = "Approximately 200 ns"]
+    #[inline]
+    pub fn ucglit_3(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:1 - Deglitch time"]
+    #[inline]
+    pub fn ucglit(&self) -> UCGLITR {
+        UCGLITR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 3 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:1 - Deglitch time"]
+    #[inline]
+    pub fn ucglit(&mut self) -> _UCGLITW {
+        _UCGLITW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a2/ucax_ie.rs b/example-source/msp432p401r/src/eusci_a2/ucax_ie.rs
new file mode 100644
index 0000000..f91baad
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a2/ucax_ie.rs
@@ -0,0 +1,540 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXIE {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCRXIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIER {
+    #[doc = "Interrupt disabled"]
+    UCRXIE_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE_1,
+}
+impl UCRXIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIER::UCRXIE_0 => false,
+            UCRXIER::UCRXIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIER {
+        match value {
+            false => UCRXIER::UCRXIE_0,
+            true => UCRXIER::UCRXIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE_0`"]
+    #[inline]
+    pub fn is_ucrxie_0(&self) -> bool {
+        *self == UCRXIER::UCRXIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE_1`"]
+    #[inline]
+    pub fn is_ucrxie_1(&self) -> bool {
+        *self == UCRXIER::UCRXIE_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIER {
+    #[doc = "Interrupt disabled"]
+    UCTXIE_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE_1,
+}
+impl UCTXIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIER::UCTXIE_0 => false,
+            UCTXIER::UCTXIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIER {
+        match value {
+            false => UCTXIER::UCTXIE_0,
+            true => UCTXIER::UCTXIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE_0`"]
+    #[inline]
+    pub fn is_uctxie_0(&self) -> bool {
+        *self == UCTXIER::UCTXIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE_1`"]
+    #[inline]
+    pub fn is_uctxie_1(&self) -> bool {
+        *self == UCTXIER::UCTXIE_1
+    }
+}
+#[doc = "Possible values of the field `UCSTTIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTTIER {
+    #[doc = "Interrupt disabled"]
+    UCSTTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCSTTIE_1,
+}
+impl UCSTTIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTTIER::UCSTTIE_0 => false,
+            UCSTTIER::UCSTTIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTTIER {
+        match value {
+            false => UCSTTIER::UCSTTIE_0,
+            true => UCSTTIER::UCSTTIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIE_0`"]
+    #[inline]
+    pub fn is_ucsttie_0(&self) -> bool {
+        *self == UCSTTIER::UCSTTIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIE_1`"]
+    #[inline]
+    pub fn is_ucsttie_1(&self) -> bool {
+        *self == UCSTTIER::UCSTTIE_1
+    }
+}
+#[doc = "Possible values of the field `UCTXCPTIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXCPTIER {
+    #[doc = "Interrupt disabled"]
+    UCTXCPTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCTXCPTIE_1,
+}
+impl UCTXCPTIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXCPTIER::UCTXCPTIE_0 => false,
+            UCTXCPTIER::UCTXCPTIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXCPTIER {
+        match value {
+            false => UCTXCPTIER::UCTXCPTIE_0,
+            true => UCTXCPTIER::UCTXCPTIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXCPTIE_0`"]
+    #[inline]
+    pub fn is_uctxcptie_0(&self) -> bool {
+        *self == UCTXCPTIER::UCTXCPTIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXCPTIE_1`"]
+    #[inline]
+    pub fn is_uctxcptie_1(&self) -> bool {
+        *self == UCTXCPTIER::UCTXCPTIE_1
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIE`"]
+pub enum UCRXIEW {
+    #[doc = "Interrupt disabled"]
+    UCRXIE_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE_1,
+}
+impl UCRXIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIEW::UCRXIE_0 => false,
+            UCRXIEW::UCRXIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucrxie_0(self) -> &'a mut W {
+        self.variant(UCRXIEW::UCRXIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucrxie_1(self) -> &'a mut W {
+        self.variant(UCRXIEW::UCRXIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIE`"]
+pub enum UCTXIEW {
+    #[doc = "Interrupt disabled"]
+    UCTXIE_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE_1,
+}
+impl UCTXIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIEW::UCTXIE_0 => false,
+            UCTXIEW::UCTXIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn uctxie_0(self) -> &'a mut W {
+        self.variant(UCTXIEW::UCTXIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn uctxie_1(self) -> &'a mut W {
+        self.variant(UCTXIEW::UCTXIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTTIE`"]
+pub enum UCSTTIEW {
+    #[doc = "Interrupt disabled"]
+    UCSTTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCSTTIE_1,
+}
+impl UCSTTIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTTIEW::UCSTTIE_0 => false,
+            UCSTTIEW::UCSTTIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTTIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTTIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTTIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucsttie_0(self) -> &'a mut W {
+        self.variant(UCSTTIEW::UCSTTIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucsttie_1(self) -> &'a mut W {
+        self.variant(UCSTTIEW::UCSTTIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXCPTIE`"]
+pub enum UCTXCPTIEW {
+    #[doc = "Interrupt disabled"]
+    UCTXCPTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCTXCPTIE_1,
+}
+impl UCTXCPTIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXCPTIEW::UCTXCPTIE_0 => false,
+            UCTXCPTIEW::UCTXCPTIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXCPTIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXCPTIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXCPTIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn uctxcptie_0(self) -> &'a mut W {
+        self.variant(UCTXCPTIEW::UCTXCPTIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn uctxcptie_1(self) -> &'a mut W {
+        self.variant(UCTXCPTIEW::UCTXCPTIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Receive interrupt enable"]
+    #[inline]
+    pub fn ucrxie(&self) -> UCRXIER {
+        UCRXIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Transmit interrupt enable"]
+    #[inline]
+    pub fn uctxie(&self) -> UCTXIER {
+        UCTXIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - Start bit interrupt enable"]
+    #[inline]
+    pub fn ucsttie(&self) -> UCSTTIER {
+        UCSTTIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Transmit complete interrupt enable"]
+    #[inline]
+    pub fn uctxcptie(&self) -> UCTXCPTIER {
+        UCTXCPTIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Receive interrupt enable"]
+    #[inline]
+    pub fn ucrxie(&mut self) -> _UCRXIEW {
+        _UCRXIEW { w: self }
+    }
+    #[doc = "Bit 1 - Transmit interrupt enable"]
+    #[inline]
+    pub fn uctxie(&mut self) -> _UCTXIEW {
+        _UCTXIEW { w: self }
+    }
+    #[doc = "Bit 2 - Start bit interrupt enable"]
+    #[inline]
+    pub fn ucsttie(&mut self) -> _UCSTTIEW {
+        _UCSTTIEW { w: self }
+    }
+    #[doc = "Bit 3 - Transmit complete interrupt enable"]
+    #[inline]
+    pub fn uctxcptie(&mut self) -> _UCTXCPTIEW {
+        _UCTXCPTIEW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a2/ucax_ifg.rs b/example-source/msp432p401r/src/eusci_a2/ucax_ifg.rs
new file mode 100644
index 0000000..88bb34d
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a2/ucax_ifg.rs
@@ -0,0 +1,540 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXIFG {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCRXIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIFGR {
+    #[doc = "No interrupt pending"]
+    UCRXIFG_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG_1,
+}
+impl UCRXIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIFGR::UCRXIFG_0 => false,
+            UCRXIFGR::UCRXIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIFGR {
+        match value {
+            false => UCRXIFGR::UCRXIFG_0,
+            true => UCRXIFGR::UCRXIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG_0`"]
+    #[inline]
+    pub fn is_ucrxifg_0(&self) -> bool {
+        *self == UCRXIFGR::UCRXIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG_1`"]
+    #[inline]
+    pub fn is_ucrxifg_1(&self) -> bool {
+        *self == UCRXIFGR::UCRXIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIFGR {
+    #[doc = "No interrupt pending"]
+    UCTXIFG_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG_1,
+}
+impl UCTXIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIFGR::UCTXIFG_0 => false,
+            UCTXIFGR::UCTXIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIFGR {
+        match value {
+            false => UCTXIFGR::UCTXIFG_0,
+            true => UCTXIFGR::UCTXIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG_0`"]
+    #[inline]
+    pub fn is_uctxifg_0(&self) -> bool {
+        *self == UCTXIFGR::UCTXIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG_1`"]
+    #[inline]
+    pub fn is_uctxifg_1(&self) -> bool {
+        *self == UCTXIFGR::UCTXIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCSTTIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTTIFGR {
+    #[doc = "No interrupt pending"]
+    UCSTTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCSTTIFG_1,
+}
+impl UCSTTIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTTIFGR::UCSTTIFG_0 => false,
+            UCSTTIFGR::UCSTTIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTTIFGR {
+        match value {
+            false => UCSTTIFGR::UCSTTIFG_0,
+            true => UCSTTIFGR::UCSTTIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIFG_0`"]
+    #[inline]
+    pub fn is_ucsttifg_0(&self) -> bool {
+        *self == UCSTTIFGR::UCSTTIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIFG_1`"]
+    #[inline]
+    pub fn is_ucsttifg_1(&self) -> bool {
+        *self == UCSTTIFGR::UCSTTIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCTXCPTIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXCPTIFGR {
+    #[doc = "No interrupt pending"]
+    UCTXCPTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCTXCPTIFG_1,
+}
+impl UCTXCPTIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXCPTIFGR::UCTXCPTIFG_0 => false,
+            UCTXCPTIFGR::UCTXCPTIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXCPTIFGR {
+        match value {
+            false => UCTXCPTIFGR::UCTXCPTIFG_0,
+            true => UCTXCPTIFGR::UCTXCPTIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXCPTIFG_0`"]
+    #[inline]
+    pub fn is_uctxcptifg_0(&self) -> bool {
+        *self == UCTXCPTIFGR::UCTXCPTIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXCPTIFG_1`"]
+    #[inline]
+    pub fn is_uctxcptifg_1(&self) -> bool {
+        *self == UCTXCPTIFGR::UCTXCPTIFG_1
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIFG`"]
+pub enum UCRXIFGW {
+    #[doc = "No interrupt pending"]
+    UCRXIFG_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG_1,
+}
+impl UCRXIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIFGW::UCRXIFG_0 => false,
+            UCRXIFGW::UCRXIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucrxifg_0(self) -> &'a mut W {
+        self.variant(UCRXIFGW::UCRXIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucrxifg_1(self) -> &'a mut W {
+        self.variant(UCRXIFGW::UCRXIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIFG`"]
+pub enum UCTXIFGW {
+    #[doc = "No interrupt pending"]
+    UCTXIFG_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG_1,
+}
+impl UCTXIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIFGW::UCTXIFG_0 => false,
+            UCTXIFGW::UCTXIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn uctxifg_0(self) -> &'a mut W {
+        self.variant(UCTXIFGW::UCTXIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn uctxifg_1(self) -> &'a mut W {
+        self.variant(UCTXIFGW::UCTXIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTTIFG`"]
+pub enum UCSTTIFGW {
+    #[doc = "No interrupt pending"]
+    UCSTTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCSTTIFG_1,
+}
+impl UCSTTIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTTIFGW::UCSTTIFG_0 => false,
+            UCSTTIFGW::UCSTTIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTTIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTTIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTTIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucsttifg_0(self) -> &'a mut W {
+        self.variant(UCSTTIFGW::UCSTTIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucsttifg_1(self) -> &'a mut W {
+        self.variant(UCSTTIFGW::UCSTTIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXCPTIFG`"]
+pub enum UCTXCPTIFGW {
+    #[doc = "No interrupt pending"]
+    UCTXCPTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCTXCPTIFG_1,
+}
+impl UCTXCPTIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXCPTIFGW::UCTXCPTIFG_0 => false,
+            UCTXCPTIFGW::UCTXCPTIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXCPTIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXCPTIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXCPTIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn uctxcptifg_0(self) -> &'a mut W {
+        self.variant(UCTXCPTIFGW::UCTXCPTIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn uctxcptifg_1(self) -> &'a mut W {
+        self.variant(UCTXCPTIFGW::UCTXCPTIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Receive interrupt flag"]
+    #[inline]
+    pub fn ucrxifg(&self) -> UCRXIFGR {
+        UCRXIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Transmit interrupt flag"]
+    #[inline]
+    pub fn uctxifg(&self) -> UCTXIFGR {
+        UCTXIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - Start bit interrupt flag"]
+    #[inline]
+    pub fn ucsttifg(&self) -> UCSTTIFGR {
+        UCSTTIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Transmit ready interrupt enable"]
+    #[inline]
+    pub fn uctxcptifg(&self) -> UCTXCPTIFGR {
+        UCTXCPTIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 2 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Receive interrupt flag"]
+    #[inline]
+    pub fn ucrxifg(&mut self) -> _UCRXIFGW {
+        _UCRXIFGW { w: self }
+    }
+    #[doc = "Bit 1 - Transmit interrupt flag"]
+    #[inline]
+    pub fn uctxifg(&mut self) -> _UCTXIFGW {
+        _UCTXIFGW { w: self }
+    }
+    #[doc = "Bit 2 - Start bit interrupt flag"]
+    #[inline]
+    pub fn ucsttifg(&mut self) -> _UCSTTIFGW {
+        _UCSTTIFGW { w: self }
+    }
+    #[doc = "Bit 3 - Transmit ready interrupt enable"]
+    #[inline]
+    pub fn uctxcptifg(&mut self) -> _UCTXCPTIFGW {
+        _UCTXCPTIFGW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a2/ucax_irctl.rs b/example-source/msp432p401r/src/eusci_a2/ucax_irctl.rs
new file mode 100644
index 0000000..38d0d14
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a2/ucax_irctl.rs
@@ -0,0 +1,622 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXIRCTL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCIREN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCIRENR {
+    #[doc = "IrDA encoder/decoder disabled"]
+    UCIREN_0,
+    #[doc = "IrDA encoder/decoder enabled"]
+    UCIREN_1,
+}
+impl UCIRENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCIRENR::UCIREN_0 => false,
+            UCIRENR::UCIREN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCIRENR {
+        match value {
+            false => UCIRENR::UCIREN_0,
+            true => UCIRENR::UCIREN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCIREN_0`"]
+    #[inline]
+    pub fn is_uciren_0(&self) -> bool {
+        *self == UCIRENR::UCIREN_0
+    }
+    #[doc = "Checks if the value of the field is `UCIREN_1`"]
+    #[inline]
+    pub fn is_uciren_1(&self) -> bool {
+        *self == UCIRENR::UCIREN_1
+    }
+}
+#[doc = "Possible values of the field `UCIRTXCLK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCIRTXCLKR {
+    #[doc = "BRCLK"]
+    UCIRTXCLK_0,
+    #[doc = "BITCLK16 when UCOS16 = 1. Otherwise, BRCLK."]
+    UCIRTXCLK_1,
+}
+impl UCIRTXCLKR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCIRTXCLKR::UCIRTXCLK_0 => false,
+            UCIRTXCLKR::UCIRTXCLK_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCIRTXCLKR {
+        match value {
+            false => UCIRTXCLKR::UCIRTXCLK_0,
+            true => UCIRTXCLKR::UCIRTXCLK_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCIRTXCLK_0`"]
+    #[inline]
+    pub fn is_ucirtxclk_0(&self) -> bool {
+        *self == UCIRTXCLKR::UCIRTXCLK_0
+    }
+    #[doc = "Checks if the value of the field is `UCIRTXCLK_1`"]
+    #[inline]
+    pub fn is_ucirtxclk_1(&self) -> bool {
+        *self == UCIRTXCLKR::UCIRTXCLK_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCIRTXPLR {
+    bits: u8,
+}
+impl UCIRTXPLR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `UCIRRXFE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCIRRXFER {
+    #[doc = "Receive filter disabled"]
+    UCIRRXFE_0,
+    #[doc = "Receive filter enabled"]
+    UCIRRXFE_1,
+}
+impl UCIRRXFER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCIRRXFER::UCIRRXFE_0 => false,
+            UCIRRXFER::UCIRRXFE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCIRRXFER {
+        match value {
+            false => UCIRRXFER::UCIRRXFE_0,
+            true => UCIRRXFER::UCIRRXFE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCIRRXFE_0`"]
+    #[inline]
+    pub fn is_ucirrxfe_0(&self) -> bool {
+        *self == UCIRRXFER::UCIRRXFE_0
+    }
+    #[doc = "Checks if the value of the field is `UCIRRXFE_1`"]
+    #[inline]
+    pub fn is_ucirrxfe_1(&self) -> bool {
+        *self == UCIRRXFER::UCIRRXFE_1
+    }
+}
+#[doc = "Possible values of the field `UCIRRXPL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCIRRXPLR {
+    #[doc = "IrDA transceiver delivers a high pulse when a light pulse is seen"]
+    UCIRRXPL_0,
+    #[doc = "IrDA transceiver delivers a low pulse when a light pulse is seen"]
+    UCIRRXPL_1,
+}
+impl UCIRRXPLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCIRRXPLR::UCIRRXPL_0 => false,
+            UCIRRXPLR::UCIRRXPL_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCIRRXPLR {
+        match value {
+            false => UCIRRXPLR::UCIRRXPL_0,
+            true => UCIRRXPLR::UCIRRXPL_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCIRRXPL_0`"]
+    #[inline]
+    pub fn is_ucirrxpl_0(&self) -> bool {
+        *self == UCIRRXPLR::UCIRRXPL_0
+    }
+    #[doc = "Checks if the value of the field is `UCIRRXPL_1`"]
+    #[inline]
+    pub fn is_ucirrxpl_1(&self) -> bool {
+        *self == UCIRRXPLR::UCIRRXPL_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCIRRXFLR {
+    bits: u8,
+}
+impl UCIRRXFLR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Values that can be written to the field `UCIREN`"]
+pub enum UCIRENW {
+    #[doc = "IrDA encoder/decoder disabled"]
+    UCIREN_0,
+    #[doc = "IrDA encoder/decoder enabled"]
+    UCIREN_1,
+}
+impl UCIRENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCIRENW::UCIREN_0 => false,
+            UCIRENW::UCIREN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCIRENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCIRENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCIRENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "IrDA encoder/decoder disabled"]
+    #[inline]
+    pub fn uciren_0(self) -> &'a mut W {
+        self.variant(UCIRENW::UCIREN_0)
+    }
+    #[doc = "IrDA encoder/decoder enabled"]
+    #[inline]
+    pub fn uciren_1(self) -> &'a mut W {
+        self.variant(UCIRENW::UCIREN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCIRTXCLK`"]
+pub enum UCIRTXCLKW {
+    #[doc = "BRCLK"]
+    UCIRTXCLK_0,
+    #[doc = "BITCLK16 when UCOS16 = 1. Otherwise, BRCLK."]
+    UCIRTXCLK_1,
+}
+impl UCIRTXCLKW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCIRTXCLKW::UCIRTXCLK_0 => false,
+            UCIRTXCLKW::UCIRTXCLK_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCIRTXCLKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCIRTXCLKW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCIRTXCLKW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "BRCLK"]
+    #[inline]
+    pub fn ucirtxclk_0(self) -> &'a mut W {
+        self.variant(UCIRTXCLKW::UCIRTXCLK_0)
+    }
+    #[doc = "BITCLK16 when UCOS16 = 1. Otherwise, BRCLK."]
+    #[inline]
+    pub fn ucirtxclk_1(self) -> &'a mut W {
+        self.variant(UCIRTXCLKW::UCIRTXCLK_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCIRTXPLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCIRTXPLW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 63;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCIRRXFE`"]
+pub enum UCIRRXFEW {
+    #[doc = "Receive filter disabled"]
+    UCIRRXFE_0,
+    #[doc = "Receive filter enabled"]
+    UCIRRXFE_1,
+}
+impl UCIRRXFEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCIRRXFEW::UCIRRXFE_0 => false,
+            UCIRRXFEW::UCIRRXFE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCIRRXFEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCIRRXFEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCIRRXFEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Receive filter disabled"]
+    #[inline]
+    pub fn ucirrxfe_0(self) -> &'a mut W {
+        self.variant(UCIRRXFEW::UCIRRXFE_0)
+    }
+    #[doc = "Receive filter enabled"]
+    #[inline]
+    pub fn ucirrxfe_1(self) -> &'a mut W {
+        self.variant(UCIRRXFEW::UCIRRXFE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCIRRXPL`"]
+pub enum UCIRRXPLW {
+    #[doc = "IrDA transceiver delivers a high pulse when a light pulse is seen"]
+    UCIRRXPL_0,
+    #[doc = "IrDA transceiver delivers a low pulse when a light pulse is seen"]
+    UCIRRXPL_1,
+}
+impl UCIRRXPLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCIRRXPLW::UCIRRXPL_0 => false,
+            UCIRRXPLW::UCIRRXPL_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCIRRXPLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCIRRXPLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCIRRXPLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "IrDA transceiver delivers a high pulse when a light pulse is seen"]
+    #[inline]
+    pub fn ucirrxpl_0(self) -> &'a mut W {
+        self.variant(UCIRRXPLW::UCIRRXPL_0)
+    }
+    #[doc = "IrDA transceiver delivers a low pulse when a light pulse is seen"]
+    #[inline]
+    pub fn ucirrxpl_1(self) -> &'a mut W {
+        self.variant(UCIRRXPLW::UCIRRXPL_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCIRRXFLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCIRRXFLW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - IrDA encoder/decoder enable"]
+    #[inline]
+    pub fn uciren(&self) -> UCIRENR {
+        UCIRENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - IrDA transmit pulse clock select"]
+    #[inline]
+    pub fn ucirtxclk(&self) -> UCIRTXCLKR {
+        UCIRTXCLKR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 2:7 - Transmit pulse length"]
+    #[inline]
+    pub fn ucirtxpl(&self) -> UCIRTXPLR {
+        let bits = {
+            const MASK: u8 = 63;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCIRTXPLR { bits }
+    }
+    #[doc = "Bit 8 - IrDA receive filter enabled"]
+    #[inline]
+    pub fn ucirrxfe(&self) -> UCIRRXFER {
+        UCIRRXFER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 9 - IrDA receive input UCAxRXD polarity"]
+    #[inline]
+    pub fn ucirrxpl(&self) -> UCIRRXPLR {
+        UCIRRXPLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 10:13 - Receive filter length"]
+    #[inline]
+    pub fn ucirrxfl(&self) -> UCIRRXFLR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCIRRXFLR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - IrDA encoder/decoder enable"]
+    #[inline]
+    pub fn uciren(&mut self) -> _UCIRENW {
+        _UCIRENW { w: self }
+    }
+    #[doc = "Bit 1 - IrDA transmit pulse clock select"]
+    #[inline]
+    pub fn ucirtxclk(&mut self) -> _UCIRTXCLKW {
+        _UCIRTXCLKW { w: self }
+    }
+    #[doc = "Bits 2:7 - Transmit pulse length"]
+    #[inline]
+    pub fn ucirtxpl(&mut self) -> _UCIRTXPLW {
+        _UCIRTXPLW { w: self }
+    }
+    #[doc = "Bit 8 - IrDA receive filter enabled"]
+    #[inline]
+    pub fn ucirrxfe(&mut self) -> _UCIRRXFEW {
+        _UCIRRXFEW { w: self }
+    }
+    #[doc = "Bit 9 - IrDA receive input UCAxRXD polarity"]
+    #[inline]
+    pub fn ucirrxpl(&mut self) -> _UCIRRXPLW {
+        _UCIRRXPLW { w: self }
+    }
+    #[doc = "Bits 10:13 - Receive filter length"]
+    #[inline]
+    pub fn ucirrxfl(&mut self) -> _UCIRRXFLW {
+        _UCIRRXFLW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a2/ucax_iv.rs b/example-source/msp432p401r/src/eusci_a2/ucax_iv.rs
new file mode 100644
index 0000000..9f6d12c
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a2/ucax_iv.rs
@@ -0,0 +1,97 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::UCAXIV {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `UCIV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCIVR {
+    #[doc = "No interrupt pending"]
+    UCIV_0,
+    #[doc = "Interrupt Source: Receive buffer full; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest"]
+    UCIV_2,
+    #[doc = "Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG"]
+    UCIV_4,
+    #[doc = "Interrupt Source: Start bit received; Interrupt Flag: UCSTTIFG"]
+    UCIV_6,
+    #[doc = "Interrupt Source: Transmit complete; Interrupt Flag: UCTXCPTIFG; Interrupt Priority: Lowest"]
+    UCIV_8,
+    #[doc = r" Reserved"]
+    _Reserved(u16),
+}
+impl UCIVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        match *self {
+            UCIVR::UCIV_0 => 0,
+            UCIVR::UCIV_2 => 2,
+            UCIVR::UCIV_4 => 4,
+            UCIVR::UCIV_6 => 6,
+            UCIVR::UCIV_8 => 8,
+            UCIVR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u16) -> UCIVR {
+        match value {
+            0 => UCIVR::UCIV_0,
+            2 => UCIVR::UCIV_2,
+            4 => UCIVR::UCIV_4,
+            6 => UCIVR::UCIV_6,
+            8 => UCIVR::UCIV_8,
+            i => UCIVR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCIV_0`"]
+    #[inline]
+    pub fn is_uciv_0(&self) -> bool {
+        *self == UCIVR::UCIV_0
+    }
+    #[doc = "Checks if the value of the field is `UCIV_2`"]
+    #[inline]
+    pub fn is_uciv_2(&self) -> bool {
+        *self == UCIVR::UCIV_2
+    }
+    #[doc = "Checks if the value of the field is `UCIV_4`"]
+    #[inline]
+    pub fn is_uciv_4(&self) -> bool {
+        *self == UCIVR::UCIV_4
+    }
+    #[doc = "Checks if the value of the field is `UCIV_6`"]
+    #[inline]
+    pub fn is_uciv_6(&self) -> bool {
+        *self == UCIVR::UCIV_6
+    }
+    #[doc = "Checks if the value of the field is `UCIV_8`"]
+    #[inline]
+    pub fn is_uciv_8(&self) -> bool {
+        *self == UCIVR::UCIV_8
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - eUSCI_A interrupt vector value"]
+    #[inline]
+    pub fn uciv(&self) -> UCIVR {
+        UCIVR::_from({
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a2/ucax_mctlw.rs b/example-source/msp432p401r/src/eusci_a2/ucax_mctlw.rs
new file mode 100644
index 0000000..aebce19
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a2/ucax_mctlw.rs
@@ -0,0 +1,265 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXMCTLW {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCOS16`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCOS16R {
+    #[doc = "Disabled"]
+    UCOS16_0,
+    #[doc = "Enabled"]
+    UCOS16_1,
+}
+impl UCOS16R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCOS16R::UCOS16_0 => false,
+            UCOS16R::UCOS16_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCOS16R {
+        match value {
+            false => UCOS16R::UCOS16_0,
+            true => UCOS16R::UCOS16_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCOS16_0`"]
+    #[inline]
+    pub fn is_ucos16_0(&self) -> bool {
+        *self == UCOS16R::UCOS16_0
+    }
+    #[doc = "Checks if the value of the field is `UCOS16_1`"]
+    #[inline]
+    pub fn is_ucos16_1(&self) -> bool {
+        *self == UCOS16R::UCOS16_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCBRFR {
+    bits: u8,
+}
+impl UCBRFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCBRSR {
+    bits: u8,
+}
+impl UCBRSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Values that can be written to the field `UCOS16`"]
+pub enum UCOS16W {
+    #[doc = "Disabled"]
+    UCOS16_0,
+    #[doc = "Enabled"]
+    UCOS16_1,
+}
+impl UCOS16W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCOS16W::UCOS16_0 => false,
+            UCOS16W::UCOS16_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCOS16W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCOS16W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCOS16W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disabled"]
+    #[inline]
+    pub fn ucos16_0(self) -> &'a mut W {
+        self.variant(UCOS16W::UCOS16_0)
+    }
+    #[doc = "Enabled"]
+    #[inline]
+    pub fn ucos16_1(self) -> &'a mut W {
+        self.variant(UCOS16W::UCOS16_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBRFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBRFW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBRSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBRSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Oversampling mode enabled"]
+    #[inline]
+    pub fn ucos16(&self) -> UCOS16R {
+        UCOS16R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 4:7 - First modulation stage select"]
+    #[inline]
+    pub fn ucbrf(&self) -> UCBRFR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCBRFR { bits }
+    }
+    #[doc = "Bits 8:15 - Second modulation stage select"]
+    #[inline]
+    pub fn ucbrs(&self) -> UCBRSR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCBRSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Oversampling mode enabled"]
+    #[inline]
+    pub fn ucos16(&mut self) -> _UCOS16W {
+        _UCOS16W { w: self }
+    }
+    #[doc = "Bits 4:7 - First modulation stage select"]
+    #[inline]
+    pub fn ucbrf(&mut self) -> _UCBRFW {
+        _UCBRFW { w: self }
+    }
+    #[doc = "Bits 8:15 - Second modulation stage select"]
+    #[inline]
+    pub fn ucbrs(&mut self) -> _UCBRSW {
+        _UCBRSW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a2/ucax_rxbuf.rs b/example-source/msp432p401r/src/eusci_a2/ucax_rxbuf.rs
new file mode 100644
index 0000000..d13ee75
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a2/ucax_rxbuf.rs
@@ -0,0 +1,41 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::UCAXRXBUF {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCRXBUFR {
+    bits: u8,
+}
+impl UCRXBUFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Receive data buffer"]
+    #[inline]
+    pub fn ucrxbuf(&self) -> UCRXBUFR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCRXBUFR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a2/ucax_statw.rs b/example-source/msp432p401r/src/eusci_a2/ucax_statw.rs
new file mode 100644
index 0000000..8992e75
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a2/ucax_statw.rs
@@ -0,0 +1,893 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXSTATW {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCBUSY`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBUSYR {
+    #[doc = "eUSCI_A inactive"]
+    UCBUSY_0,
+    #[doc = "eUSCI_A transmitting or receiving"]
+    UCBUSY_1,
+}
+impl UCBUSYR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBUSYR::UCBUSY_0 => false,
+            UCBUSYR::UCBUSY_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBUSYR {
+        match value {
+            false => UCBUSYR::UCBUSY_0,
+            true => UCBUSYR::UCBUSY_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBUSY_0`"]
+    #[inline]
+    pub fn is_ucbusy_0(&self) -> bool {
+        *self == UCBUSYR::UCBUSY_0
+    }
+    #[doc = "Checks if the value of the field is `UCBUSY_1`"]
+    #[inline]
+    pub fn is_ucbusy_1(&self) -> bool {
+        *self == UCBUSYR::UCBUSY_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCADDR_UCIDLER {
+    bits: bool,
+}
+impl UCADDR_UCIDLER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `UCRXERR`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXERRR {
+    #[doc = "No receive errors detected"]
+    UCRXERR_0,
+    #[doc = "Receive error detected"]
+    UCRXERR_1,
+}
+impl UCRXERRR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXERRR::UCRXERR_0 => false,
+            UCRXERRR::UCRXERR_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXERRR {
+        match value {
+            false => UCRXERRR::UCRXERR_0,
+            true => UCRXERRR::UCRXERR_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXERR_0`"]
+    #[inline]
+    pub fn is_ucrxerr_0(&self) -> bool {
+        *self == UCRXERRR::UCRXERR_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXERR_1`"]
+    #[inline]
+    pub fn is_ucrxerr_1(&self) -> bool {
+        *self == UCRXERRR::UCRXERR_1
+    }
+}
+#[doc = "Possible values of the field `UCBRK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBRKR {
+    #[doc = "No break condition"]
+    UCBRK_0,
+    #[doc = "Break condition occurred"]
+    UCBRK_1,
+}
+impl UCBRKR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBRKR::UCBRK_0 => false,
+            UCBRKR::UCBRK_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBRKR {
+        match value {
+            false => UCBRKR::UCBRK_0,
+            true => UCBRKR::UCBRK_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBRK_0`"]
+    #[inline]
+    pub fn is_ucbrk_0(&self) -> bool {
+        *self == UCBRKR::UCBRK_0
+    }
+    #[doc = "Checks if the value of the field is `UCBRK_1`"]
+    #[inline]
+    pub fn is_ucbrk_1(&self) -> bool {
+        *self == UCBRKR::UCBRK_1
+    }
+}
+#[doc = "Possible values of the field `UCPE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCPER {
+    #[doc = "No error"]
+    UCPE_0,
+    #[doc = "Character received with parity error"]
+    UCPE_1,
+}
+impl UCPER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCPER::UCPE_0 => false,
+            UCPER::UCPE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCPER {
+        match value {
+            false => UCPER::UCPE_0,
+            true => UCPER::UCPE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCPE_0`"]
+    #[inline]
+    pub fn is_ucpe_0(&self) -> bool {
+        *self == UCPER::UCPE_0
+    }
+    #[doc = "Checks if the value of the field is `UCPE_1`"]
+    #[inline]
+    pub fn is_ucpe_1(&self) -> bool {
+        *self == UCPER::UCPE_1
+    }
+}
+#[doc = "Possible values of the field `UCOE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCOER {
+    #[doc = "No error"]
+    UCOE_0,
+    #[doc = "Overrun error occurred"]
+    UCOE_1,
+}
+impl UCOER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCOER::UCOE_0 => false,
+            UCOER::UCOE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCOER {
+        match value {
+            false => UCOER::UCOE_0,
+            true => UCOER::UCOE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCOE_0`"]
+    #[inline]
+    pub fn is_ucoe_0(&self) -> bool {
+        *self == UCOER::UCOE_0
+    }
+    #[doc = "Checks if the value of the field is `UCOE_1`"]
+    #[inline]
+    pub fn is_ucoe_1(&self) -> bool {
+        *self == UCOER::UCOE_1
+    }
+}
+#[doc = "Possible values of the field `UCFE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCFER {
+    #[doc = "No error"]
+    UCFE_0,
+    #[doc = "Character received with low stop bit"]
+    UCFE_1,
+}
+impl UCFER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCFER::UCFE_0 => false,
+            UCFER::UCFE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCFER {
+        match value {
+            false => UCFER::UCFE_0,
+            true => UCFER::UCFE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCFE_0`"]
+    #[inline]
+    pub fn is_ucfe_0(&self) -> bool {
+        *self == UCFER::UCFE_0
+    }
+    #[doc = "Checks if the value of the field is `UCFE_1`"]
+    #[inline]
+    pub fn is_ucfe_1(&self) -> bool {
+        *self == UCFER::UCFE_1
+    }
+}
+#[doc = "Possible values of the field `UCLISTEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCLISTENR {
+    #[doc = "Disabled"]
+    UCLISTEN_0,
+    #[doc = "Enabled. UCAxTXD is internally fed back to the receiver"]
+    UCLISTEN_1,
+}
+impl UCLISTENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCLISTENR::UCLISTEN_0 => false,
+            UCLISTENR::UCLISTEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCLISTENR {
+        match value {
+            false => UCLISTENR::UCLISTEN_0,
+            true => UCLISTENR::UCLISTEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCLISTEN_0`"]
+    #[inline]
+    pub fn is_uclisten_0(&self) -> bool {
+        *self == UCLISTENR::UCLISTEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCLISTEN_1`"]
+    #[inline]
+    pub fn is_uclisten_1(&self) -> bool {
+        *self == UCLISTENR::UCLISTEN_1
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCADDR_UCIDLEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCADDR_UCIDLEW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXERR`"]
+pub enum UCRXERRW {
+    #[doc = "No receive errors detected"]
+    UCRXERR_0,
+    #[doc = "Receive error detected"]
+    UCRXERR_1,
+}
+impl UCRXERRW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXERRW::UCRXERR_0 => false,
+            UCRXERRW::UCRXERR_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXERRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXERRW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXERRW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No receive errors detected"]
+    #[inline]
+    pub fn ucrxerr_0(self) -> &'a mut W {
+        self.variant(UCRXERRW::UCRXERR_0)
+    }
+    #[doc = "Receive error detected"]
+    #[inline]
+    pub fn ucrxerr_1(self) -> &'a mut W {
+        self.variant(UCRXERRW::UCRXERR_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCBRK`"]
+pub enum UCBRKW {
+    #[doc = "No break condition"]
+    UCBRK_0,
+    #[doc = "Break condition occurred"]
+    UCBRK_1,
+}
+impl UCBRKW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCBRKW::UCBRK_0 => false,
+            UCBRKW::UCBRK_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBRKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBRKW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCBRKW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No break condition"]
+    #[inline]
+    pub fn ucbrk_0(self) -> &'a mut W {
+        self.variant(UCBRKW::UCBRK_0)
+    }
+    #[doc = "Break condition occurred"]
+    #[inline]
+    pub fn ucbrk_1(self) -> &'a mut W {
+        self.variant(UCBRKW::UCBRK_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCPE`"]
+pub enum UCPEW {
+    #[doc = "No error"]
+    UCPE_0,
+    #[doc = "Character received with parity error"]
+    UCPE_1,
+}
+impl UCPEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCPEW::UCPE_0 => false,
+            UCPEW::UCPE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCPEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCPEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCPEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No error"]
+    #[inline]
+    pub fn ucpe_0(self) -> &'a mut W {
+        self.variant(UCPEW::UCPE_0)
+    }
+    #[doc = "Character received with parity error"]
+    #[inline]
+    pub fn ucpe_1(self) -> &'a mut W {
+        self.variant(UCPEW::UCPE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCOE`"]
+pub enum UCOEW {
+    #[doc = "No error"]
+    UCOE_0,
+    #[doc = "Overrun error occurred"]
+    UCOE_1,
+}
+impl UCOEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCOEW::UCOE_0 => false,
+            UCOEW::UCOE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCOEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCOEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCOEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No error"]
+    #[inline]
+    pub fn ucoe_0(self) -> &'a mut W {
+        self.variant(UCOEW::UCOE_0)
+    }
+    #[doc = "Overrun error occurred"]
+    #[inline]
+    pub fn ucoe_1(self) -> &'a mut W {
+        self.variant(UCOEW::UCOE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCFE`"]
+pub enum UCFEW {
+    #[doc = "No error"]
+    UCFE_0,
+    #[doc = "Character received with low stop bit"]
+    UCFE_1,
+}
+impl UCFEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCFEW::UCFE_0 => false,
+            UCFEW::UCFE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCFEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCFEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCFEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No error"]
+    #[inline]
+    pub fn ucfe_0(self) -> &'a mut W {
+        self.variant(UCFEW::UCFE_0)
+    }
+    #[doc = "Character received with low stop bit"]
+    #[inline]
+    pub fn ucfe_1(self) -> &'a mut W {
+        self.variant(UCFEW::UCFE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCLISTEN`"]
+pub enum UCLISTENW {
+    #[doc = "Disabled"]
+    UCLISTEN_0,
+    #[doc = "Enabled. UCAxTXD is internally fed back to the receiver"]
+    UCLISTEN_1,
+}
+impl UCLISTENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCLISTENW::UCLISTEN_0 => false,
+            UCLISTENW::UCLISTEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCLISTENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCLISTENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCLISTENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disabled"]
+    #[inline]
+    pub fn uclisten_0(self) -> &'a mut W {
+        self.variant(UCLISTENW::UCLISTEN_0)
+    }
+    #[doc = "Enabled. UCAxTXD is internally fed back to the receiver"]
+    #[inline]
+    pub fn uclisten_1(self) -> &'a mut W {
+        self.variant(UCLISTENW::UCLISTEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - eUSCI_A busy"]
+    #[inline]
+    pub fn ucbusy(&self) -> UCBUSYR {
+        UCBUSYR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Address received / Idle line detected"]
+    #[inline]
+    pub fn ucaddr_ucidle(&self) -> UCADDR_UCIDLER {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        };
+        UCADDR_UCIDLER { bits }
+    }
+    #[doc = "Bit 2 - Receive error flag"]
+    #[inline]
+    pub fn ucrxerr(&self) -> UCRXERRR {
+        UCRXERRR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Break detect flag"]
+    #[inline]
+    pub fn ucbrk(&self) -> UCBRKR {
+        UCBRKR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 4 - Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read."]
+    #[inline]
+    pub fn ucpe(&self) -> UCPER {
+        UCPER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - Overrun error flag"]
+    #[inline]
+    pub fn ucoe(&self) -> UCOER {
+        UCOER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 6 - Framing error flag"]
+    #[inline]
+    pub fn ucfe(&self) -> UCFER {
+        UCFER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 7 - Listen enable"]
+    #[inline]
+    pub fn uclisten(&self) -> UCLISTENR {
+        UCLISTENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 1 - Address received / Idle line detected"]
+    #[inline]
+    pub fn ucaddr_ucidle(&mut self) -> _UCADDR_UCIDLEW {
+        _UCADDR_UCIDLEW { w: self }
+    }
+    #[doc = "Bit 2 - Receive error flag"]
+    #[inline]
+    pub fn ucrxerr(&mut self) -> _UCRXERRW {
+        _UCRXERRW { w: self }
+    }
+    #[doc = "Bit 3 - Break detect flag"]
+    #[inline]
+    pub fn ucbrk(&mut self) -> _UCBRKW {
+        _UCBRKW { w: self }
+    }
+    #[doc = "Bit 4 - Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read."]
+    #[inline]
+    pub fn ucpe(&mut self) -> _UCPEW {
+        _UCPEW { w: self }
+    }
+    #[doc = "Bit 5 - Overrun error flag"]
+    #[inline]
+    pub fn ucoe(&mut self) -> _UCOEW {
+        _UCOEW { w: self }
+    }
+    #[doc = "Bit 6 - Framing error flag"]
+    #[inline]
+    pub fn ucfe(&mut self) -> _UCFEW {
+        _UCFEW { w: self }
+    }
+    #[doc = "Bit 7 - Listen enable"]
+    #[inline]
+    pub fn uclisten(&mut self) -> _UCLISTENW {
+        _UCLISTENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a2/ucax_txbuf.rs b/example-source/msp432p401r/src/eusci_a2/ucax_txbuf.rs
new file mode 100644
index 0000000..47ca264
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a2/ucax_txbuf.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXTXBUF {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCTXBUFR {
+    bits: u8,
+}
+impl UCTXBUFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXBUFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXBUFW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Transmit data buffer"]
+    #[inline]
+    pub fn uctxbuf(&self) -> UCTXBUFR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCTXBUFR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Transmit data buffer"]
+    #[inline]
+    pub fn uctxbuf(&mut self) -> _UCTXBUFW {
+        _UCTXBUFW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a3.rs b/example-source/msp432p401r/src/eusci_a3.rs
new file mode 100644
index 0000000..88b0e5e
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a3.rs
@@ -0,0 +1,102 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - eUSCI_Ax Control Word Register 0"]
+    pub ucax_ctlw0: UCAXCTLW0,
+    #[doc = "0x02 - eUSCI_Ax Control Word Register 1"]
+    pub ucax_ctlw1: UCAXCTLW1,
+    _reserved0: [u8; 2usize],
+    #[doc = "0x06 - eUSCI_Ax Baud Rate Control Word Register"]
+    pub ucax_brw: UCAXBRW,
+    #[doc = "0x08 - eUSCI_Ax Modulation Control Word Register"]
+    pub ucax_mctlw: UCAXMCTLW,
+    #[doc = "0x0a - eUSCI_Ax Status Register"]
+    pub ucax_statw: UCAXSTATW,
+    #[doc = "0x0c - eUSCI_Ax Receive Buffer Register"]
+    pub ucax_rxbuf: UCAXRXBUF,
+    #[doc = "0x0e - eUSCI_Ax Transmit Buffer Register"]
+    pub ucax_txbuf: UCAXTXBUF,
+    #[doc = "0x10 - eUSCI_Ax Auto Baud Rate Control Register"]
+    pub ucax_abctl: UCAXABCTL,
+    #[doc = "0x12 - eUSCI_Ax IrDA Control Word Register"]
+    pub ucax_irctl: UCAXIRCTL,
+    _reserved1: [u8; 6usize],
+    #[doc = "0x1a - eUSCI_Ax Interrupt Enable Register"]
+    pub ucax_ie: UCAXIE,
+    #[doc = "0x1c - eUSCI_Ax Interrupt Flag Register"]
+    pub ucax_ifg: UCAXIFG,
+    #[doc = "0x1e - eUSCI_Ax Interrupt Vector Register"]
+    pub ucax_iv: UCAXIV,
+}
+#[doc = "eUSCI_Ax Control Word Register 0"]
+pub struct UCAXCTLW0 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Control Word Register 0"]
+pub mod ucax_ctlw0;
+#[doc = "eUSCI_Ax Control Word Register 1"]
+pub struct UCAXCTLW1 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Control Word Register 1"]
+pub mod ucax_ctlw1;
+#[doc = "eUSCI_Ax Baud Rate Control Word Register"]
+pub struct UCAXBRW {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Baud Rate Control Word Register"]
+pub mod ucax_brw;
+#[doc = "eUSCI_Ax Modulation Control Word Register"]
+pub struct UCAXMCTLW {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Modulation Control Word Register"]
+pub mod ucax_mctlw;
+#[doc = "eUSCI_Ax Status Register"]
+pub struct UCAXSTATW {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Status Register"]
+pub mod ucax_statw;
+#[doc = "eUSCI_Ax Receive Buffer Register"]
+pub struct UCAXRXBUF {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Receive Buffer Register"]
+pub mod ucax_rxbuf;
+#[doc = "eUSCI_Ax Transmit Buffer Register"]
+pub struct UCAXTXBUF {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Transmit Buffer Register"]
+pub mod ucax_txbuf;
+#[doc = "eUSCI_Ax Auto Baud Rate Control Register"]
+pub struct UCAXABCTL {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Auto Baud Rate Control Register"]
+pub mod ucax_abctl;
+#[doc = "eUSCI_Ax IrDA Control Word Register"]
+pub struct UCAXIRCTL {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax IrDA Control Word Register"]
+pub mod ucax_irctl;
+#[doc = "eUSCI_Ax Interrupt Enable Register"]
+pub struct UCAXIE {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Interrupt Enable Register"]
+pub mod ucax_ie;
+#[doc = "eUSCI_Ax Interrupt Flag Register"]
+pub struct UCAXIFG {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Interrupt Flag Register"]
+pub mod ucax_ifg;
+#[doc = "eUSCI_Ax Interrupt Vector Register"]
+pub struct UCAXIV {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Ax Interrupt Vector Register"]
+pub mod ucax_iv;
diff --git a/example-source/msp432p401r/src/eusci_a3/ucax_abctl.rs b/example-source/msp432p401r/src/eusci_a3/ucax_abctl.rs
new file mode 100644
index 0000000..ce574eb
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a3/ucax_abctl.rs
@@ -0,0 +1,557 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXABCTL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCABDEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCABDENR {
+    #[doc = "Baud-rate detection disabled. Length of break and synch field is not measured."]
+    UCABDEN_0,
+    #[doc = "Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly."]
+    UCABDEN_1,
+}
+impl UCABDENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCABDENR::UCABDEN_0 => false,
+            UCABDENR::UCABDEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCABDENR {
+        match value {
+            false => UCABDENR::UCABDEN_0,
+            true => UCABDENR::UCABDEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCABDEN_0`"]
+    #[inline]
+    pub fn is_ucabden_0(&self) -> bool {
+        *self == UCABDENR::UCABDEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCABDEN_1`"]
+    #[inline]
+    pub fn is_ucabden_1(&self) -> bool {
+        *self == UCABDENR::UCABDEN_1
+    }
+}
+#[doc = "Possible values of the field `UCBTOE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBTOER {
+    #[doc = "No error"]
+    UCBTOE_0,
+    #[doc = "Length of break field exceeded 22 bit times"]
+    UCBTOE_1,
+}
+impl UCBTOER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBTOER::UCBTOE_0 => false,
+            UCBTOER::UCBTOE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBTOER {
+        match value {
+            false => UCBTOER::UCBTOE_0,
+            true => UCBTOER::UCBTOE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBTOE_0`"]
+    #[inline]
+    pub fn is_ucbtoe_0(&self) -> bool {
+        *self == UCBTOER::UCBTOE_0
+    }
+    #[doc = "Checks if the value of the field is `UCBTOE_1`"]
+    #[inline]
+    pub fn is_ucbtoe_1(&self) -> bool {
+        *self == UCBTOER::UCBTOE_1
+    }
+}
+#[doc = "Possible values of the field `UCSTOE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTOER {
+    #[doc = "No error"]
+    UCSTOE_0,
+    #[doc = "Length of synch field exceeded measurable time"]
+    UCSTOE_1,
+}
+impl UCSTOER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTOER::UCSTOE_0 => false,
+            UCSTOER::UCSTOE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTOER {
+        match value {
+            false => UCSTOER::UCSTOE_0,
+            true => UCSTOER::UCSTOE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTOE_0`"]
+    #[inline]
+    pub fn is_ucstoe_0(&self) -> bool {
+        *self == UCSTOER::UCSTOE_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTOE_1`"]
+    #[inline]
+    pub fn is_ucstoe_1(&self) -> bool {
+        *self == UCSTOER::UCSTOE_1
+    }
+}
+#[doc = "Possible values of the field `UCDELIM`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCDELIMR {
+    #[doc = "1 bit time"]
+    UCDELIM_0,
+    #[doc = "2 bit times"]
+    UCDELIM_1,
+    #[doc = "3 bit times"]
+    UCDELIM_2,
+    #[doc = "4 bit times"]
+    UCDELIM_3,
+}
+impl UCDELIMR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCDELIMR::UCDELIM_0 => 0,
+            UCDELIMR::UCDELIM_1 => 1,
+            UCDELIMR::UCDELIM_2 => 2,
+            UCDELIMR::UCDELIM_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCDELIMR {
+        match value {
+            0 => UCDELIMR::UCDELIM_0,
+            1 => UCDELIMR::UCDELIM_1,
+            2 => UCDELIMR::UCDELIM_2,
+            3 => UCDELIMR::UCDELIM_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCDELIM_0`"]
+    #[inline]
+    pub fn is_ucdelim_0(&self) -> bool {
+        *self == UCDELIMR::UCDELIM_0
+    }
+    #[doc = "Checks if the value of the field is `UCDELIM_1`"]
+    #[inline]
+    pub fn is_ucdelim_1(&self) -> bool {
+        *self == UCDELIMR::UCDELIM_1
+    }
+    #[doc = "Checks if the value of the field is `UCDELIM_2`"]
+    #[inline]
+    pub fn is_ucdelim_2(&self) -> bool {
+        *self == UCDELIMR::UCDELIM_2
+    }
+    #[doc = "Checks if the value of the field is `UCDELIM_3`"]
+    #[inline]
+    pub fn is_ucdelim_3(&self) -> bool {
+        *self == UCDELIMR::UCDELIM_3
+    }
+}
+#[doc = "Values that can be written to the field `UCABDEN`"]
+pub enum UCABDENW {
+    #[doc = "Baud-rate detection disabled. Length of break and synch field is not measured."]
+    UCABDEN_0,
+    #[doc = "Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly."]
+    UCABDEN_1,
+}
+impl UCABDENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCABDENW::UCABDEN_0 => false,
+            UCABDENW::UCABDEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCABDENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCABDENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCABDENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Baud-rate detection disabled. Length of break and synch field is not measured."]
+    #[inline]
+    pub fn ucabden_0(self) -> &'a mut W {
+        self.variant(UCABDENW::UCABDEN_0)
+    }
+    #[doc = "Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly."]
+    #[inline]
+    pub fn ucabden_1(self) -> &'a mut W {
+        self.variant(UCABDENW::UCABDEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCBTOE`"]
+pub enum UCBTOEW {
+    #[doc = "No error"]
+    UCBTOE_0,
+    #[doc = "Length of break field exceeded 22 bit times"]
+    UCBTOE_1,
+}
+impl UCBTOEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCBTOEW::UCBTOE_0 => false,
+            UCBTOEW::UCBTOE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBTOEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBTOEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCBTOEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No error"]
+    #[inline]
+    pub fn ucbtoe_0(self) -> &'a mut W {
+        self.variant(UCBTOEW::UCBTOE_0)
+    }
+    #[doc = "Length of break field exceeded 22 bit times"]
+    #[inline]
+    pub fn ucbtoe_1(self) -> &'a mut W {
+        self.variant(UCBTOEW::UCBTOE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTOE`"]
+pub enum UCSTOEW {
+    #[doc = "No error"]
+    UCSTOE_0,
+    #[doc = "Length of synch field exceeded measurable time"]
+    UCSTOE_1,
+}
+impl UCSTOEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTOEW::UCSTOE_0 => false,
+            UCSTOEW::UCSTOE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTOEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTOEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTOEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No error"]
+    #[inline]
+    pub fn ucstoe_0(self) -> &'a mut W {
+        self.variant(UCSTOEW::UCSTOE_0)
+    }
+    #[doc = "Length of synch field exceeded measurable time"]
+    #[inline]
+    pub fn ucstoe_1(self) -> &'a mut W {
+        self.variant(UCSTOEW::UCSTOE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCDELIM`"]
+pub enum UCDELIMW {
+    #[doc = "1 bit time"]
+    UCDELIM_0,
+    #[doc = "2 bit times"]
+    UCDELIM_1,
+    #[doc = "3 bit times"]
+    UCDELIM_2,
+    #[doc = "4 bit times"]
+    UCDELIM_3,
+}
+impl UCDELIMW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCDELIMW::UCDELIM_0 => 0,
+            UCDELIMW::UCDELIM_1 => 1,
+            UCDELIMW::UCDELIM_2 => 2,
+            UCDELIMW::UCDELIM_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCDELIMW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCDELIMW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCDELIMW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "1 bit time"]
+    #[inline]
+    pub fn ucdelim_0(self) -> &'a mut W {
+        self.variant(UCDELIMW::UCDELIM_0)
+    }
+    #[doc = "2 bit times"]
+    #[inline]
+    pub fn ucdelim_1(self) -> &'a mut W {
+        self.variant(UCDELIMW::UCDELIM_1)
+    }
+    #[doc = "3 bit times"]
+    #[inline]
+    pub fn ucdelim_2(self) -> &'a mut W {
+        self.variant(UCDELIMW::UCDELIM_2)
+    }
+    #[doc = "4 bit times"]
+    #[inline]
+    pub fn ucdelim_3(self) -> &'a mut W {
+        self.variant(UCDELIMW::UCDELIM_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Automatic baud-rate detect enable"]
+    #[inline]
+    pub fn ucabden(&self) -> UCABDENR {
+        UCABDENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - Break time out error"]
+    #[inline]
+    pub fn ucbtoe(&self) -> UCBTOER {
+        UCBTOER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Synch field time out error"]
+    #[inline]
+    pub fn ucstoe(&self) -> UCSTOER {
+        UCSTOER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 4:5 - Break/synch delimiter length"]
+    #[inline]
+    pub fn ucdelim(&self) -> UCDELIMR {
+        UCDELIMR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Automatic baud-rate detect enable"]
+    #[inline]
+    pub fn ucabden(&mut self) -> _UCABDENW {
+        _UCABDENW { w: self }
+    }
+    #[doc = "Bit 2 - Break time out error"]
+    #[inline]
+    pub fn ucbtoe(&mut self) -> _UCBTOEW {
+        _UCBTOEW { w: self }
+    }
+    #[doc = "Bit 3 - Synch field time out error"]
+    #[inline]
+    pub fn ucstoe(&mut self) -> _UCSTOEW {
+        _UCSTOEW { w: self }
+    }
+    #[doc = "Bits 4:5 - Break/synch delimiter length"]
+    #[inline]
+    pub fn ucdelim(&mut self) -> _UCDELIMW {
+        _UCDELIMW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a3/ucax_brw.rs b/example-source/msp432p401r/src/eusci_a3/ucax_brw.rs
new file mode 100644
index 0000000..c9b1b2a
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a3/ucax_brw.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXBRW {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCBRR {
+    bits: u16,
+}
+impl UCBRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBRW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Clock prescaler setting of the Baud rate generator"]
+    #[inline]
+    pub fn ucbr(&self) -> UCBRR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        UCBRR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Clock prescaler setting of the Baud rate generator"]
+    #[inline]
+    pub fn ucbr(&mut self) -> _UCBRW {
+        _UCBRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a3/ucax_ctlw0.rs b/example-source/msp432p401r/src/eusci_a3/ucax_ctlw0.rs
new file mode 100644
index 0000000..aa44348
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a3/ucax_ctlw0.rs
@@ -0,0 +1,1748 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXCTLW0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCSWRST`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSWRSTR {
+    #[doc = "Disabled. eUSCI_A reset released for operation"]
+    UCSWRST_0,
+    #[doc = "Enabled. eUSCI_A logic held in reset state"]
+    UCSWRST_1,
+}
+impl UCSWRSTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSWRSTR::UCSWRST_0 => false,
+            UCSWRSTR::UCSWRST_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSWRSTR {
+        match value {
+            false => UCSWRSTR::UCSWRST_0,
+            true => UCSWRSTR::UCSWRST_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSWRST_0`"]
+    #[inline]
+    pub fn is_ucswrst_0(&self) -> bool {
+        *self == UCSWRSTR::UCSWRST_0
+    }
+    #[doc = "Checks if the value of the field is `UCSWRST_1`"]
+    #[inline]
+    pub fn is_ucswrst_1(&self) -> bool {
+        *self == UCSWRSTR::UCSWRST_1
+    }
+}
+#[doc = "Possible values of the field `UCTXBRK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXBRKR {
+    #[doc = "Next frame transmitted is not a break"]
+    UCTXBRK_0,
+    #[doc = "Next frame transmitted is a break or a break/synch"]
+    UCTXBRK_1,
+}
+impl UCTXBRKR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXBRKR::UCTXBRK_0 => false,
+            UCTXBRKR::UCTXBRK_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXBRKR {
+        match value {
+            false => UCTXBRKR::UCTXBRK_0,
+            true => UCTXBRKR::UCTXBRK_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXBRK_0`"]
+    #[inline]
+    pub fn is_uctxbrk_0(&self) -> bool {
+        *self == UCTXBRKR::UCTXBRK_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXBRK_1`"]
+    #[inline]
+    pub fn is_uctxbrk_1(&self) -> bool {
+        *self == UCTXBRKR::UCTXBRK_1
+    }
+}
+#[doc = "Possible values of the field `UCTXADDR`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXADDRR {
+    #[doc = "Next frame transmitted is data"]
+    UCTXADDR_0,
+    #[doc = "Next frame transmitted is an address"]
+    UCTXADDR_1,
+}
+impl UCTXADDRR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXADDRR::UCTXADDR_0 => false,
+            UCTXADDRR::UCTXADDR_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXADDRR {
+        match value {
+            false => UCTXADDRR::UCTXADDR_0,
+            true => UCTXADDRR::UCTXADDR_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXADDR_0`"]
+    #[inline]
+    pub fn is_uctxaddr_0(&self) -> bool {
+        *self == UCTXADDRR::UCTXADDR_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXADDR_1`"]
+    #[inline]
+    pub fn is_uctxaddr_1(&self) -> bool {
+        *self == UCTXADDRR::UCTXADDR_1
+    }
+}
+#[doc = "Possible values of the field `UCDORM`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCDORMR {
+    #[doc = "Not dormant. All received characters set UCRXIFG."]
+    UCDORM_0,
+    #[doc = "Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG."]
+    UCDORM_1,
+}
+impl UCDORMR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCDORMR::UCDORM_0 => false,
+            UCDORMR::UCDORM_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCDORMR {
+        match value {
+            false => UCDORMR::UCDORM_0,
+            true => UCDORMR::UCDORM_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCDORM_0`"]
+    #[inline]
+    pub fn is_ucdorm_0(&self) -> bool {
+        *self == UCDORMR::UCDORM_0
+    }
+    #[doc = "Checks if the value of the field is `UCDORM_1`"]
+    #[inline]
+    pub fn is_ucdorm_1(&self) -> bool {
+        *self == UCDORMR::UCDORM_1
+    }
+}
+#[doc = "Possible values of the field `UCBRKIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBRKIER {
+    #[doc = "Received break characters do not set UCRXIFG"]
+    UCBRKIE_0,
+    #[doc = "Received break characters set UCRXIFG"]
+    UCBRKIE_1,
+}
+impl UCBRKIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBRKIER::UCBRKIE_0 => false,
+            UCBRKIER::UCBRKIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBRKIER {
+        match value {
+            false => UCBRKIER::UCBRKIE_0,
+            true => UCBRKIER::UCBRKIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBRKIE_0`"]
+    #[inline]
+    pub fn is_ucbrkie_0(&self) -> bool {
+        *self == UCBRKIER::UCBRKIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCBRKIE_1`"]
+    #[inline]
+    pub fn is_ucbrkie_1(&self) -> bool {
+        *self == UCBRKIER::UCBRKIE_1
+    }
+}
+#[doc = "Possible values of the field `UCRXEIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXEIER {
+    #[doc = "Erroneous characters rejected and UCRXIFG is not set"]
+    UCRXEIE_0,
+    #[doc = "Erroneous characters received set UCRXIFG"]
+    UCRXEIE_1,
+}
+impl UCRXEIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXEIER::UCRXEIE_0 => false,
+            UCRXEIER::UCRXEIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXEIER {
+        match value {
+            false => UCRXEIER::UCRXEIE_0,
+            true => UCRXEIER::UCRXEIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXEIE_0`"]
+    #[inline]
+    pub fn is_ucrxeie_0(&self) -> bool {
+        *self == UCRXEIER::UCRXEIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXEIE_1`"]
+    #[inline]
+    pub fn is_ucrxeie_1(&self) -> bool {
+        *self == UCRXEIER::UCRXEIE_1
+    }
+}
+#[doc = "Possible values of the field `UCSSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSSELR {
+    #[doc = "UCLK"]
+    UCSSEL_0,
+    #[doc = "ACLK"]
+    UCSSEL_1,
+    #[doc = "SMCLK"]
+    UCSSEL_2,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl UCSSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCSSELR::UCSSEL_0 => 0,
+            UCSSELR::UCSSEL_1 => 1,
+            UCSSELR::UCSSEL_2 => 2,
+            UCSSELR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCSSELR {
+        match value {
+            0 => UCSSELR::UCSSEL_0,
+            1 => UCSSELR::UCSSEL_1,
+            2 => UCSSELR::UCSSEL_2,
+            i => UCSSELR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSSEL_0`"]
+    #[inline]
+    pub fn is_ucssel_0(&self) -> bool {
+        *self == UCSSELR::UCSSEL_0
+    }
+    #[doc = "Checks if the value of the field is `UCSSEL_1`"]
+    #[inline]
+    pub fn is_ucssel_1(&self) -> bool {
+        *self == UCSSELR::UCSSEL_1
+    }
+    #[doc = "Checks if the value of the field is `UCSSEL_2`"]
+    #[inline]
+    pub fn is_ucssel_2(&self) -> bool {
+        *self == UCSSELR::UCSSEL_2
+    }
+}
+#[doc = "Possible values of the field `UCSYNC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSYNCR {
+    #[doc = "Asynchronous mode"]
+    UCSYNC_0,
+    #[doc = "Synchronous mode"]
+    UCSYNC_1,
+}
+impl UCSYNCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSYNCR::UCSYNC_0 => false,
+            UCSYNCR::UCSYNC_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSYNCR {
+        match value {
+            false => UCSYNCR::UCSYNC_0,
+            true => UCSYNCR::UCSYNC_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSYNC_0`"]
+    #[inline]
+    pub fn is_ucsync_0(&self) -> bool {
+        *self == UCSYNCR::UCSYNC_0
+    }
+    #[doc = "Checks if the value of the field is `UCSYNC_1`"]
+    #[inline]
+    pub fn is_ucsync_1(&self) -> bool {
+        *self == UCSYNCR::UCSYNC_1
+    }
+}
+#[doc = "Possible values of the field `UCMODE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCMODER {
+    #[doc = "UART mode"]
+    UCMODE_0,
+    #[doc = "Idle-line multiprocessor mode"]
+    UCMODE_1,
+    #[doc = "Address-bit multiprocessor mode"]
+    UCMODE_2,
+    #[doc = "UART mode with automatic baud-rate detection"]
+    UCMODE_3,
+}
+impl UCMODER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCMODER::UCMODE_0 => 0,
+            UCMODER::UCMODE_1 => 1,
+            UCMODER::UCMODE_2 => 2,
+            UCMODER::UCMODE_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCMODER {
+        match value {
+            0 => UCMODER::UCMODE_0,
+            1 => UCMODER::UCMODE_1,
+            2 => UCMODER::UCMODE_2,
+            3 => UCMODER::UCMODE_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_0`"]
+    #[inline]
+    pub fn is_ucmode_0(&self) -> bool {
+        *self == UCMODER::UCMODE_0
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_1`"]
+    #[inline]
+    pub fn is_ucmode_1(&self) -> bool {
+        *self == UCMODER::UCMODE_1
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_2`"]
+    #[inline]
+    pub fn is_ucmode_2(&self) -> bool {
+        *self == UCMODER::UCMODE_2
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_3`"]
+    #[inline]
+    pub fn is_ucmode_3(&self) -> bool {
+        *self == UCMODER::UCMODE_3
+    }
+}
+#[doc = "Possible values of the field `UCSPB`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSPBR {
+    #[doc = "One stop bit"]
+    UCSPB_0,
+    #[doc = "Two stop bits"]
+    UCSPB_1,
+}
+impl UCSPBR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSPBR::UCSPB_0 => false,
+            UCSPBR::UCSPB_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSPBR {
+        match value {
+            false => UCSPBR::UCSPB_0,
+            true => UCSPBR::UCSPB_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSPB_0`"]
+    #[inline]
+    pub fn is_ucspb_0(&self) -> bool {
+        *self == UCSPBR::UCSPB_0
+    }
+    #[doc = "Checks if the value of the field is `UCSPB_1`"]
+    #[inline]
+    pub fn is_ucspb_1(&self) -> bool {
+        *self == UCSPBR::UCSPB_1
+    }
+}
+#[doc = "Possible values of the field `UC7BIT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UC7BITR {
+    #[doc = "8-bit data"]
+    UC7BIT_0,
+    #[doc = "7-bit data"]
+    UC7BIT_1,
+}
+impl UC7BITR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UC7BITR::UC7BIT_0 => false,
+            UC7BITR::UC7BIT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UC7BITR {
+        match value {
+            false => UC7BITR::UC7BIT_0,
+            true => UC7BITR::UC7BIT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UC7BIT_0`"]
+    #[inline]
+    pub fn is_uc7bit_0(&self) -> bool {
+        *self == UC7BITR::UC7BIT_0
+    }
+    #[doc = "Checks if the value of the field is `UC7BIT_1`"]
+    #[inline]
+    pub fn is_uc7bit_1(&self) -> bool {
+        *self == UC7BITR::UC7BIT_1
+    }
+}
+#[doc = "Possible values of the field `UCMSB`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCMSBR {
+    #[doc = "LSB first"]
+    UCMSB_0,
+    #[doc = "MSB first"]
+    UCMSB_1,
+}
+impl UCMSBR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCMSBR::UCMSB_0 => false,
+            UCMSBR::UCMSB_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCMSBR {
+        match value {
+            false => UCMSBR::UCMSB_0,
+            true => UCMSBR::UCMSB_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCMSB_0`"]
+    #[inline]
+    pub fn is_ucmsb_0(&self) -> bool {
+        *self == UCMSBR::UCMSB_0
+    }
+    #[doc = "Checks if the value of the field is `UCMSB_1`"]
+    #[inline]
+    pub fn is_ucmsb_1(&self) -> bool {
+        *self == UCMSBR::UCMSB_1
+    }
+}
+#[doc = "Possible values of the field `UCPAR`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCPARR {
+    #[doc = "Odd parity"]
+    UCPAR_0,
+    #[doc = "Even parity"]
+    UCPAR_1,
+}
+impl UCPARR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCPARR::UCPAR_0 => false,
+            UCPARR::UCPAR_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCPARR {
+        match value {
+            false => UCPARR::UCPAR_0,
+            true => UCPARR::UCPAR_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCPAR_0`"]
+    #[inline]
+    pub fn is_ucpar_0(&self) -> bool {
+        *self == UCPARR::UCPAR_0
+    }
+    #[doc = "Checks if the value of the field is `UCPAR_1`"]
+    #[inline]
+    pub fn is_ucpar_1(&self) -> bool {
+        *self == UCPARR::UCPAR_1
+    }
+}
+#[doc = "Possible values of the field `UCPEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCPENR {
+    #[doc = "Parity disabled"]
+    UCPEN_0,
+    #[doc = "Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation."]
+    UCPEN_1,
+}
+impl UCPENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCPENR::UCPEN_0 => false,
+            UCPENR::UCPEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCPENR {
+        match value {
+            false => UCPENR::UCPEN_0,
+            true => UCPENR::UCPEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCPEN_0`"]
+    #[inline]
+    pub fn is_ucpen_0(&self) -> bool {
+        *self == UCPENR::UCPEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCPEN_1`"]
+    #[inline]
+    pub fn is_ucpen_1(&self) -> bool {
+        *self == UCPENR::UCPEN_1
+    }
+}
+#[doc = "Values that can be written to the field `UCSWRST`"]
+pub enum UCSWRSTW {
+    #[doc = "Disabled. eUSCI_A reset released for operation"]
+    UCSWRST_0,
+    #[doc = "Enabled. eUSCI_A logic held in reset state"]
+    UCSWRST_1,
+}
+impl UCSWRSTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSWRSTW::UCSWRST_0 => false,
+            UCSWRSTW::UCSWRST_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSWRSTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSWRSTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSWRSTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disabled. eUSCI_A reset released for operation"]
+    #[inline]
+    pub fn ucswrst_0(self) -> &'a mut W {
+        self.variant(UCSWRSTW::UCSWRST_0)
+    }
+    #[doc = "Enabled. eUSCI_A logic held in reset state"]
+    #[inline]
+    pub fn ucswrst_1(self) -> &'a mut W {
+        self.variant(UCSWRSTW::UCSWRST_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXBRK`"]
+pub enum UCTXBRKW {
+    #[doc = "Next frame transmitted is not a break"]
+    UCTXBRK_0,
+    #[doc = "Next frame transmitted is a break or a break/synch"]
+    UCTXBRK_1,
+}
+impl UCTXBRKW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXBRKW::UCTXBRK_0 => false,
+            UCTXBRKW::UCTXBRK_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXBRKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXBRKW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXBRKW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Next frame transmitted is not a break"]
+    #[inline]
+    pub fn uctxbrk_0(self) -> &'a mut W {
+        self.variant(UCTXBRKW::UCTXBRK_0)
+    }
+    #[doc = "Next frame transmitted is a break or a break/synch"]
+    #[inline]
+    pub fn uctxbrk_1(self) -> &'a mut W {
+        self.variant(UCTXBRKW::UCTXBRK_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXADDR`"]
+pub enum UCTXADDRW {
+    #[doc = "Next frame transmitted is data"]
+    UCTXADDR_0,
+    #[doc = "Next frame transmitted is an address"]
+    UCTXADDR_1,
+}
+impl UCTXADDRW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXADDRW::UCTXADDR_0 => false,
+            UCTXADDRW::UCTXADDR_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXADDRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXADDRW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXADDRW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Next frame transmitted is data"]
+    #[inline]
+    pub fn uctxaddr_0(self) -> &'a mut W {
+        self.variant(UCTXADDRW::UCTXADDR_0)
+    }
+    #[doc = "Next frame transmitted is an address"]
+    #[inline]
+    pub fn uctxaddr_1(self) -> &'a mut W {
+        self.variant(UCTXADDRW::UCTXADDR_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCDORM`"]
+pub enum UCDORMW {
+    #[doc = "Not dormant. All received characters set UCRXIFG."]
+    UCDORM_0,
+    #[doc = "Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG."]
+    UCDORM_1,
+}
+impl UCDORMW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCDORMW::UCDORM_0 => false,
+            UCDORMW::UCDORM_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCDORMW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCDORMW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCDORMW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Not dormant. All received characters set UCRXIFG."]
+    #[inline]
+    pub fn ucdorm_0(self) -> &'a mut W {
+        self.variant(UCDORMW::UCDORM_0)
+    }
+    #[doc = "Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG."]
+    #[inline]
+    pub fn ucdorm_1(self) -> &'a mut W {
+        self.variant(UCDORMW::UCDORM_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCBRKIE`"]
+pub enum UCBRKIEW {
+    #[doc = "Received break characters do not set UCRXIFG"]
+    UCBRKIE_0,
+    #[doc = "Received break characters set UCRXIFG"]
+    UCBRKIE_1,
+}
+impl UCBRKIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCBRKIEW::UCBRKIE_0 => false,
+            UCBRKIEW::UCBRKIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBRKIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBRKIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCBRKIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Received break characters do not set UCRXIFG"]
+    #[inline]
+    pub fn ucbrkie_0(self) -> &'a mut W {
+        self.variant(UCBRKIEW::UCBRKIE_0)
+    }
+    #[doc = "Received break characters set UCRXIFG"]
+    #[inline]
+    pub fn ucbrkie_1(self) -> &'a mut W {
+        self.variant(UCBRKIEW::UCBRKIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXEIE`"]
+pub enum UCRXEIEW {
+    #[doc = "Erroneous characters rejected and UCRXIFG is not set"]
+    UCRXEIE_0,
+    #[doc = "Erroneous characters received set UCRXIFG"]
+    UCRXEIE_1,
+}
+impl UCRXEIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXEIEW::UCRXEIE_0 => false,
+            UCRXEIEW::UCRXEIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXEIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXEIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXEIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Erroneous characters rejected and UCRXIFG is not set"]
+    #[inline]
+    pub fn ucrxeie_0(self) -> &'a mut W {
+        self.variant(UCRXEIEW::UCRXEIE_0)
+    }
+    #[doc = "Erroneous characters received set UCRXIFG"]
+    #[inline]
+    pub fn ucrxeie_1(self) -> &'a mut W {
+        self.variant(UCRXEIEW::UCRXEIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSSEL`"]
+pub enum UCSSELW {
+    #[doc = "UCLK"]
+    UCSSEL_0,
+    #[doc = "ACLK"]
+    UCSSEL_1,
+    #[doc = "SMCLK"]
+    UCSSEL_2,
+}
+impl UCSSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCSSELW::UCSSEL_0 => 0,
+            UCSSELW::UCSSEL_1 => 1,
+            UCSSELW::UCSSEL_2 => 2,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSSELW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "UCLK"]
+    #[inline]
+    pub fn ucssel_0(self) -> &'a mut W {
+        self.variant(UCSSELW::UCSSEL_0)
+    }
+    #[doc = "ACLK"]
+    #[inline]
+    pub fn ucssel_1(self) -> &'a mut W {
+        self.variant(UCSSELW::UCSSEL_1)
+    }
+    #[doc = "SMCLK"]
+    #[inline]
+    pub fn ucssel_2(self) -> &'a mut W {
+        self.variant(UCSSELW::UCSSEL_2)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSYNC`"]
+pub enum UCSYNCW {
+    #[doc = "Asynchronous mode"]
+    UCSYNC_0,
+    #[doc = "Synchronous mode"]
+    UCSYNC_1,
+}
+impl UCSYNCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSYNCW::UCSYNC_0 => false,
+            UCSYNCW::UCSYNC_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSYNCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSYNCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSYNCW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Asynchronous mode"]
+    #[inline]
+    pub fn ucsync_0(self) -> &'a mut W {
+        self.variant(UCSYNCW::UCSYNC_0)
+    }
+    #[doc = "Synchronous mode"]
+    #[inline]
+    pub fn ucsync_1(self) -> &'a mut W {
+        self.variant(UCSYNCW::UCSYNC_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCMODE`"]
+pub enum UCMODEW {
+    #[doc = "UART mode"]
+    UCMODE_0,
+    #[doc = "Idle-line multiprocessor mode"]
+    UCMODE_1,
+    #[doc = "Address-bit multiprocessor mode"]
+    UCMODE_2,
+    #[doc = "UART mode with automatic baud-rate detection"]
+    UCMODE_3,
+}
+impl UCMODEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCMODEW::UCMODE_0 => 0,
+            UCMODEW::UCMODE_1 => 1,
+            UCMODEW::UCMODE_2 => 2,
+            UCMODEW::UCMODE_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCMODEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCMODEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCMODEW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "UART mode"]
+    #[inline]
+    pub fn ucmode_0(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_0)
+    }
+    #[doc = "Idle-line multiprocessor mode"]
+    #[inline]
+    pub fn ucmode_1(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_1)
+    }
+    #[doc = "Address-bit multiprocessor mode"]
+    #[inline]
+    pub fn ucmode_2(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_2)
+    }
+    #[doc = "UART mode with automatic baud-rate detection"]
+    #[inline]
+    pub fn ucmode_3(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSPB`"]
+pub enum UCSPBW {
+    #[doc = "One stop bit"]
+    UCSPB_0,
+    #[doc = "Two stop bits"]
+    UCSPB_1,
+}
+impl UCSPBW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSPBW::UCSPB_0 => false,
+            UCSPBW::UCSPB_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSPBW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSPBW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSPBW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "One stop bit"]
+    #[inline]
+    pub fn ucspb_0(self) -> &'a mut W {
+        self.variant(UCSPBW::UCSPB_0)
+    }
+    #[doc = "Two stop bits"]
+    #[inline]
+    pub fn ucspb_1(self) -> &'a mut W {
+        self.variant(UCSPBW::UCSPB_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UC7BIT`"]
+pub enum UC7BITW {
+    #[doc = "8-bit data"]
+    UC7BIT_0,
+    #[doc = "7-bit data"]
+    UC7BIT_1,
+}
+impl UC7BITW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UC7BITW::UC7BIT_0 => false,
+            UC7BITW::UC7BIT_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UC7BITW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UC7BITW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UC7BITW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "8-bit data"]
+    #[inline]
+    pub fn uc7bit_0(self) -> &'a mut W {
+        self.variant(UC7BITW::UC7BIT_0)
+    }
+    #[doc = "7-bit data"]
+    #[inline]
+    pub fn uc7bit_1(self) -> &'a mut W {
+        self.variant(UC7BITW::UC7BIT_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCMSB`"]
+pub enum UCMSBW {
+    #[doc = "LSB first"]
+    UCMSB_0,
+    #[doc = "MSB first"]
+    UCMSB_1,
+}
+impl UCMSBW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCMSBW::UCMSB_0 => false,
+            UCMSBW::UCMSB_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCMSBW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCMSBW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCMSBW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "LSB first"]
+    #[inline]
+    pub fn ucmsb_0(self) -> &'a mut W {
+        self.variant(UCMSBW::UCMSB_0)
+    }
+    #[doc = "MSB first"]
+    #[inline]
+    pub fn ucmsb_1(self) -> &'a mut W {
+        self.variant(UCMSBW::UCMSB_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCPAR`"]
+pub enum UCPARW {
+    #[doc = "Odd parity"]
+    UCPAR_0,
+    #[doc = "Even parity"]
+    UCPAR_1,
+}
+impl UCPARW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCPARW::UCPAR_0 => false,
+            UCPARW::UCPAR_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCPARW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCPARW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCPARW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Odd parity"]
+    #[inline]
+    pub fn ucpar_0(self) -> &'a mut W {
+        self.variant(UCPARW::UCPAR_0)
+    }
+    #[doc = "Even parity"]
+    #[inline]
+    pub fn ucpar_1(self) -> &'a mut W {
+        self.variant(UCPARW::UCPAR_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCPEN`"]
+pub enum UCPENW {
+    #[doc = "Parity disabled"]
+    UCPEN_0,
+    #[doc = "Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation."]
+    UCPEN_1,
+}
+impl UCPENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCPENW::UCPEN_0 => false,
+            UCPENW::UCPEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCPENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCPENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCPENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Parity disabled"]
+    #[inline]
+    pub fn ucpen_0(self) -> &'a mut W {
+        self.variant(UCPENW::UCPEN_0)
+    }
+    #[doc = "Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation."]
+    #[inline]
+    pub fn ucpen_1(self) -> &'a mut W {
+        self.variant(UCPENW::UCPEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Software reset enable"]
+    #[inline]
+    pub fn ucswrst(&self) -> UCSWRSTR {
+        UCSWRSTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Transmit break"]
+    #[inline]
+    pub fn uctxbrk(&self) -> UCTXBRKR {
+        UCTXBRKR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - Transmit address"]
+    #[inline]
+    pub fn uctxaddr(&self) -> UCTXADDRR {
+        UCTXADDRR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Dormant"]
+    #[inline]
+    pub fn ucdorm(&self) -> UCDORMR {
+        UCDORMR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 4 - Receive break character interrupt enable"]
+    #[inline]
+    pub fn ucbrkie(&self) -> UCBRKIER {
+        UCBRKIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - Receive erroneous-character interrupt enable"]
+    #[inline]
+    pub fn ucrxeie(&self) -> UCRXEIER {
+        UCRXEIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 6:7 - eUSCI_A clock source select"]
+    #[inline]
+    pub fn ucssel(&self) -> UCSSELR {
+        UCSSELR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 8 - Synchronous mode enable"]
+    #[inline]
+    pub fn ucsync(&self) -> UCSYNCR {
+        UCSYNCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 9:10 - eUSCI_A mode"]
+    #[inline]
+    pub fn ucmode(&self) -> UCMODER {
+        UCMODER::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 11 - Stop bit select"]
+    #[inline]
+    pub fn ucspb(&self) -> UCSPBR {
+        UCSPBR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 12 - Character length"]
+    #[inline]
+    pub fn uc7bit(&self) -> UC7BITR {
+        UC7BITR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 13 - MSB first select"]
+    #[inline]
+    pub fn ucmsb(&self) -> UCMSBR {
+        UCMSBR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 14 - Parity select"]
+    #[inline]
+    pub fn ucpar(&self) -> UCPARR {
+        UCPARR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 15 - Parity enable"]
+    #[inline]
+    pub fn ucpen(&self) -> UCPENR {
+        UCPENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 1 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Software reset enable"]
+    #[inline]
+    pub fn ucswrst(&mut self) -> _UCSWRSTW {
+        _UCSWRSTW { w: self }
+    }
+    #[doc = "Bit 1 - Transmit break"]
+    #[inline]
+    pub fn uctxbrk(&mut self) -> _UCTXBRKW {
+        _UCTXBRKW { w: self }
+    }
+    #[doc = "Bit 2 - Transmit address"]
+    #[inline]
+    pub fn uctxaddr(&mut self) -> _UCTXADDRW {
+        _UCTXADDRW { w: self }
+    }
+    #[doc = "Bit 3 - Dormant"]
+    #[inline]
+    pub fn ucdorm(&mut self) -> _UCDORMW {
+        _UCDORMW { w: self }
+    }
+    #[doc = "Bit 4 - Receive break character interrupt enable"]
+    #[inline]
+    pub fn ucbrkie(&mut self) -> _UCBRKIEW {
+        _UCBRKIEW { w: self }
+    }
+    #[doc = "Bit 5 - Receive erroneous-character interrupt enable"]
+    #[inline]
+    pub fn ucrxeie(&mut self) -> _UCRXEIEW {
+        _UCRXEIEW { w: self }
+    }
+    #[doc = "Bits 6:7 - eUSCI_A clock source select"]
+    #[inline]
+    pub fn ucssel(&mut self) -> _UCSSELW {
+        _UCSSELW { w: self }
+    }
+    #[doc = "Bit 8 - Synchronous mode enable"]
+    #[inline]
+    pub fn ucsync(&mut self) -> _UCSYNCW {
+        _UCSYNCW { w: self }
+    }
+    #[doc = "Bits 9:10 - eUSCI_A mode"]
+    #[inline]
+    pub fn ucmode(&mut self) -> _UCMODEW {
+        _UCMODEW { w: self }
+    }
+    #[doc = "Bit 11 - Stop bit select"]
+    #[inline]
+    pub fn ucspb(&mut self) -> _UCSPBW {
+        _UCSPBW { w: self }
+    }
+    #[doc = "Bit 12 - Character length"]
+    #[inline]
+    pub fn uc7bit(&mut self) -> _UC7BITW {
+        _UC7BITW { w: self }
+    }
+    #[doc = "Bit 13 - MSB first select"]
+    #[inline]
+    pub fn ucmsb(&mut self) -> _UCMSBW {
+        _UCMSBW { w: self }
+    }
+    #[doc = "Bit 14 - Parity select"]
+    #[inline]
+    pub fn ucpar(&mut self) -> _UCPARW {
+        _UCPARW { w: self }
+    }
+    #[doc = "Bit 15 - Parity enable"]
+    #[inline]
+    pub fn ucpen(&mut self) -> _UCPENW {
+        _UCPENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a3/ucax_ctlw1.rs b/example-source/msp432p401r/src/eusci_a3/ucax_ctlw1.rs
new file mode 100644
index 0000000..365cc0d
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a3/ucax_ctlw1.rs
@@ -0,0 +1,200 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXCTLW1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCGLIT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCGLITR {
+    #[doc = "Approximately 2 ns (equivalent of 1 delay element)"]
+    UCGLIT_0,
+    #[doc = "Approximately 50 ns"]
+    UCGLIT_1,
+    #[doc = "Approximately 100 ns"]
+    UCGLIT_2,
+    #[doc = "Approximately 200 ns"]
+    UCGLIT_3,
+}
+impl UCGLITR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCGLITR::UCGLIT_0 => 0,
+            UCGLITR::UCGLIT_1 => 1,
+            UCGLITR::UCGLIT_2 => 2,
+            UCGLITR::UCGLIT_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCGLITR {
+        match value {
+            0 => UCGLITR::UCGLIT_0,
+            1 => UCGLITR::UCGLIT_1,
+            2 => UCGLITR::UCGLIT_2,
+            3 => UCGLITR::UCGLIT_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_0`"]
+    #[inline]
+    pub fn is_ucglit_0(&self) -> bool {
+        *self == UCGLITR::UCGLIT_0
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_1`"]
+    #[inline]
+    pub fn is_ucglit_1(&self) -> bool {
+        *self == UCGLITR::UCGLIT_1
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_2`"]
+    #[inline]
+    pub fn is_ucglit_2(&self) -> bool {
+        *self == UCGLITR::UCGLIT_2
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_3`"]
+    #[inline]
+    pub fn is_ucglit_3(&self) -> bool {
+        *self == UCGLITR::UCGLIT_3
+    }
+}
+#[doc = "Values that can be written to the field `UCGLIT`"]
+pub enum UCGLITW {
+    #[doc = "Approximately 2 ns (equivalent of 1 delay element)"]
+    UCGLIT_0,
+    #[doc = "Approximately 50 ns"]
+    UCGLIT_1,
+    #[doc = "Approximately 100 ns"]
+    UCGLIT_2,
+    #[doc = "Approximately 200 ns"]
+    UCGLIT_3,
+}
+impl UCGLITW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCGLITW::UCGLIT_0 => 0,
+            UCGLITW::UCGLIT_1 => 1,
+            UCGLITW::UCGLIT_2 => 2,
+            UCGLITW::UCGLIT_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCGLITW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCGLITW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCGLITW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Approximately 2 ns (equivalent of 1 delay element)"]
+    #[inline]
+    pub fn ucglit_0(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_0)
+    }
+    #[doc = "Approximately 50 ns"]
+    #[inline]
+    pub fn ucglit_1(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_1)
+    }
+    #[doc = "Approximately 100 ns"]
+    #[inline]
+    pub fn ucglit_2(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_2)
+    }
+    #[doc = "Approximately 200 ns"]
+    #[inline]
+    pub fn ucglit_3(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:1 - Deglitch time"]
+    #[inline]
+    pub fn ucglit(&self) -> UCGLITR {
+        UCGLITR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 3 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:1 - Deglitch time"]
+    #[inline]
+    pub fn ucglit(&mut self) -> _UCGLITW {
+        _UCGLITW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a3/ucax_ie.rs b/example-source/msp432p401r/src/eusci_a3/ucax_ie.rs
new file mode 100644
index 0000000..f91baad
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a3/ucax_ie.rs
@@ -0,0 +1,540 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXIE {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCRXIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIER {
+    #[doc = "Interrupt disabled"]
+    UCRXIE_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE_1,
+}
+impl UCRXIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIER::UCRXIE_0 => false,
+            UCRXIER::UCRXIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIER {
+        match value {
+            false => UCRXIER::UCRXIE_0,
+            true => UCRXIER::UCRXIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE_0`"]
+    #[inline]
+    pub fn is_ucrxie_0(&self) -> bool {
+        *self == UCRXIER::UCRXIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE_1`"]
+    #[inline]
+    pub fn is_ucrxie_1(&self) -> bool {
+        *self == UCRXIER::UCRXIE_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIER {
+    #[doc = "Interrupt disabled"]
+    UCTXIE_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE_1,
+}
+impl UCTXIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIER::UCTXIE_0 => false,
+            UCTXIER::UCTXIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIER {
+        match value {
+            false => UCTXIER::UCTXIE_0,
+            true => UCTXIER::UCTXIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE_0`"]
+    #[inline]
+    pub fn is_uctxie_0(&self) -> bool {
+        *self == UCTXIER::UCTXIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE_1`"]
+    #[inline]
+    pub fn is_uctxie_1(&self) -> bool {
+        *self == UCTXIER::UCTXIE_1
+    }
+}
+#[doc = "Possible values of the field `UCSTTIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTTIER {
+    #[doc = "Interrupt disabled"]
+    UCSTTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCSTTIE_1,
+}
+impl UCSTTIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTTIER::UCSTTIE_0 => false,
+            UCSTTIER::UCSTTIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTTIER {
+        match value {
+            false => UCSTTIER::UCSTTIE_0,
+            true => UCSTTIER::UCSTTIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIE_0`"]
+    #[inline]
+    pub fn is_ucsttie_0(&self) -> bool {
+        *self == UCSTTIER::UCSTTIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIE_1`"]
+    #[inline]
+    pub fn is_ucsttie_1(&self) -> bool {
+        *self == UCSTTIER::UCSTTIE_1
+    }
+}
+#[doc = "Possible values of the field `UCTXCPTIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXCPTIER {
+    #[doc = "Interrupt disabled"]
+    UCTXCPTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCTXCPTIE_1,
+}
+impl UCTXCPTIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXCPTIER::UCTXCPTIE_0 => false,
+            UCTXCPTIER::UCTXCPTIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXCPTIER {
+        match value {
+            false => UCTXCPTIER::UCTXCPTIE_0,
+            true => UCTXCPTIER::UCTXCPTIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXCPTIE_0`"]
+    #[inline]
+    pub fn is_uctxcptie_0(&self) -> bool {
+        *self == UCTXCPTIER::UCTXCPTIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXCPTIE_1`"]
+    #[inline]
+    pub fn is_uctxcptie_1(&self) -> bool {
+        *self == UCTXCPTIER::UCTXCPTIE_1
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIE`"]
+pub enum UCRXIEW {
+    #[doc = "Interrupt disabled"]
+    UCRXIE_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE_1,
+}
+impl UCRXIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIEW::UCRXIE_0 => false,
+            UCRXIEW::UCRXIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucrxie_0(self) -> &'a mut W {
+        self.variant(UCRXIEW::UCRXIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucrxie_1(self) -> &'a mut W {
+        self.variant(UCRXIEW::UCRXIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIE`"]
+pub enum UCTXIEW {
+    #[doc = "Interrupt disabled"]
+    UCTXIE_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE_1,
+}
+impl UCTXIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIEW::UCTXIE_0 => false,
+            UCTXIEW::UCTXIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn uctxie_0(self) -> &'a mut W {
+        self.variant(UCTXIEW::UCTXIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn uctxie_1(self) -> &'a mut W {
+        self.variant(UCTXIEW::UCTXIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTTIE`"]
+pub enum UCSTTIEW {
+    #[doc = "Interrupt disabled"]
+    UCSTTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCSTTIE_1,
+}
+impl UCSTTIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTTIEW::UCSTTIE_0 => false,
+            UCSTTIEW::UCSTTIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTTIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTTIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTTIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucsttie_0(self) -> &'a mut W {
+        self.variant(UCSTTIEW::UCSTTIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucsttie_1(self) -> &'a mut W {
+        self.variant(UCSTTIEW::UCSTTIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXCPTIE`"]
+pub enum UCTXCPTIEW {
+    #[doc = "Interrupt disabled"]
+    UCTXCPTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCTXCPTIE_1,
+}
+impl UCTXCPTIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXCPTIEW::UCTXCPTIE_0 => false,
+            UCTXCPTIEW::UCTXCPTIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXCPTIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXCPTIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXCPTIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn uctxcptie_0(self) -> &'a mut W {
+        self.variant(UCTXCPTIEW::UCTXCPTIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn uctxcptie_1(self) -> &'a mut W {
+        self.variant(UCTXCPTIEW::UCTXCPTIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Receive interrupt enable"]
+    #[inline]
+    pub fn ucrxie(&self) -> UCRXIER {
+        UCRXIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Transmit interrupt enable"]
+    #[inline]
+    pub fn uctxie(&self) -> UCTXIER {
+        UCTXIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - Start bit interrupt enable"]
+    #[inline]
+    pub fn ucsttie(&self) -> UCSTTIER {
+        UCSTTIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Transmit complete interrupt enable"]
+    #[inline]
+    pub fn uctxcptie(&self) -> UCTXCPTIER {
+        UCTXCPTIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Receive interrupt enable"]
+    #[inline]
+    pub fn ucrxie(&mut self) -> _UCRXIEW {
+        _UCRXIEW { w: self }
+    }
+    #[doc = "Bit 1 - Transmit interrupt enable"]
+    #[inline]
+    pub fn uctxie(&mut self) -> _UCTXIEW {
+        _UCTXIEW { w: self }
+    }
+    #[doc = "Bit 2 - Start bit interrupt enable"]
+    #[inline]
+    pub fn ucsttie(&mut self) -> _UCSTTIEW {
+        _UCSTTIEW { w: self }
+    }
+    #[doc = "Bit 3 - Transmit complete interrupt enable"]
+    #[inline]
+    pub fn uctxcptie(&mut self) -> _UCTXCPTIEW {
+        _UCTXCPTIEW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a3/ucax_ifg.rs b/example-source/msp432p401r/src/eusci_a3/ucax_ifg.rs
new file mode 100644
index 0000000..88bb34d
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a3/ucax_ifg.rs
@@ -0,0 +1,540 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXIFG {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCRXIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIFGR {
+    #[doc = "No interrupt pending"]
+    UCRXIFG_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG_1,
+}
+impl UCRXIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIFGR::UCRXIFG_0 => false,
+            UCRXIFGR::UCRXIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIFGR {
+        match value {
+            false => UCRXIFGR::UCRXIFG_0,
+            true => UCRXIFGR::UCRXIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG_0`"]
+    #[inline]
+    pub fn is_ucrxifg_0(&self) -> bool {
+        *self == UCRXIFGR::UCRXIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG_1`"]
+    #[inline]
+    pub fn is_ucrxifg_1(&self) -> bool {
+        *self == UCRXIFGR::UCRXIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIFGR {
+    #[doc = "No interrupt pending"]
+    UCTXIFG_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG_1,
+}
+impl UCTXIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIFGR::UCTXIFG_0 => false,
+            UCTXIFGR::UCTXIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIFGR {
+        match value {
+            false => UCTXIFGR::UCTXIFG_0,
+            true => UCTXIFGR::UCTXIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG_0`"]
+    #[inline]
+    pub fn is_uctxifg_0(&self) -> bool {
+        *self == UCTXIFGR::UCTXIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG_1`"]
+    #[inline]
+    pub fn is_uctxifg_1(&self) -> bool {
+        *self == UCTXIFGR::UCTXIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCSTTIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTTIFGR {
+    #[doc = "No interrupt pending"]
+    UCSTTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCSTTIFG_1,
+}
+impl UCSTTIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTTIFGR::UCSTTIFG_0 => false,
+            UCSTTIFGR::UCSTTIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTTIFGR {
+        match value {
+            false => UCSTTIFGR::UCSTTIFG_0,
+            true => UCSTTIFGR::UCSTTIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIFG_0`"]
+    #[inline]
+    pub fn is_ucsttifg_0(&self) -> bool {
+        *self == UCSTTIFGR::UCSTTIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIFG_1`"]
+    #[inline]
+    pub fn is_ucsttifg_1(&self) -> bool {
+        *self == UCSTTIFGR::UCSTTIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCTXCPTIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXCPTIFGR {
+    #[doc = "No interrupt pending"]
+    UCTXCPTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCTXCPTIFG_1,
+}
+impl UCTXCPTIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXCPTIFGR::UCTXCPTIFG_0 => false,
+            UCTXCPTIFGR::UCTXCPTIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXCPTIFGR {
+        match value {
+            false => UCTXCPTIFGR::UCTXCPTIFG_0,
+            true => UCTXCPTIFGR::UCTXCPTIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXCPTIFG_0`"]
+    #[inline]
+    pub fn is_uctxcptifg_0(&self) -> bool {
+        *self == UCTXCPTIFGR::UCTXCPTIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXCPTIFG_1`"]
+    #[inline]
+    pub fn is_uctxcptifg_1(&self) -> bool {
+        *self == UCTXCPTIFGR::UCTXCPTIFG_1
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIFG`"]
+pub enum UCRXIFGW {
+    #[doc = "No interrupt pending"]
+    UCRXIFG_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG_1,
+}
+impl UCRXIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIFGW::UCRXIFG_0 => false,
+            UCRXIFGW::UCRXIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucrxifg_0(self) -> &'a mut W {
+        self.variant(UCRXIFGW::UCRXIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucrxifg_1(self) -> &'a mut W {
+        self.variant(UCRXIFGW::UCRXIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIFG`"]
+pub enum UCTXIFGW {
+    #[doc = "No interrupt pending"]
+    UCTXIFG_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG_1,
+}
+impl UCTXIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIFGW::UCTXIFG_0 => false,
+            UCTXIFGW::UCTXIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn uctxifg_0(self) -> &'a mut W {
+        self.variant(UCTXIFGW::UCTXIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn uctxifg_1(self) -> &'a mut W {
+        self.variant(UCTXIFGW::UCTXIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTTIFG`"]
+pub enum UCSTTIFGW {
+    #[doc = "No interrupt pending"]
+    UCSTTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCSTTIFG_1,
+}
+impl UCSTTIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTTIFGW::UCSTTIFG_0 => false,
+            UCSTTIFGW::UCSTTIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTTIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTTIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTTIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucsttifg_0(self) -> &'a mut W {
+        self.variant(UCSTTIFGW::UCSTTIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucsttifg_1(self) -> &'a mut W {
+        self.variant(UCSTTIFGW::UCSTTIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXCPTIFG`"]
+pub enum UCTXCPTIFGW {
+    #[doc = "No interrupt pending"]
+    UCTXCPTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCTXCPTIFG_1,
+}
+impl UCTXCPTIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXCPTIFGW::UCTXCPTIFG_0 => false,
+            UCTXCPTIFGW::UCTXCPTIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXCPTIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXCPTIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXCPTIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn uctxcptifg_0(self) -> &'a mut W {
+        self.variant(UCTXCPTIFGW::UCTXCPTIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn uctxcptifg_1(self) -> &'a mut W {
+        self.variant(UCTXCPTIFGW::UCTXCPTIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Receive interrupt flag"]
+    #[inline]
+    pub fn ucrxifg(&self) -> UCRXIFGR {
+        UCRXIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Transmit interrupt flag"]
+    #[inline]
+    pub fn uctxifg(&self) -> UCTXIFGR {
+        UCTXIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - Start bit interrupt flag"]
+    #[inline]
+    pub fn ucsttifg(&self) -> UCSTTIFGR {
+        UCSTTIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Transmit ready interrupt enable"]
+    #[inline]
+    pub fn uctxcptifg(&self) -> UCTXCPTIFGR {
+        UCTXCPTIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 2 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Receive interrupt flag"]
+    #[inline]
+    pub fn ucrxifg(&mut self) -> _UCRXIFGW {
+        _UCRXIFGW { w: self }
+    }
+    #[doc = "Bit 1 - Transmit interrupt flag"]
+    #[inline]
+    pub fn uctxifg(&mut self) -> _UCTXIFGW {
+        _UCTXIFGW { w: self }
+    }
+    #[doc = "Bit 2 - Start bit interrupt flag"]
+    #[inline]
+    pub fn ucsttifg(&mut self) -> _UCSTTIFGW {
+        _UCSTTIFGW { w: self }
+    }
+    #[doc = "Bit 3 - Transmit ready interrupt enable"]
+    #[inline]
+    pub fn uctxcptifg(&mut self) -> _UCTXCPTIFGW {
+        _UCTXCPTIFGW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a3/ucax_irctl.rs b/example-source/msp432p401r/src/eusci_a3/ucax_irctl.rs
new file mode 100644
index 0000000..38d0d14
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a3/ucax_irctl.rs
@@ -0,0 +1,622 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXIRCTL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCIREN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCIRENR {
+    #[doc = "IrDA encoder/decoder disabled"]
+    UCIREN_0,
+    #[doc = "IrDA encoder/decoder enabled"]
+    UCIREN_1,
+}
+impl UCIRENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCIRENR::UCIREN_0 => false,
+            UCIRENR::UCIREN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCIRENR {
+        match value {
+            false => UCIRENR::UCIREN_0,
+            true => UCIRENR::UCIREN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCIREN_0`"]
+    #[inline]
+    pub fn is_uciren_0(&self) -> bool {
+        *self == UCIRENR::UCIREN_0
+    }
+    #[doc = "Checks if the value of the field is `UCIREN_1`"]
+    #[inline]
+    pub fn is_uciren_1(&self) -> bool {
+        *self == UCIRENR::UCIREN_1
+    }
+}
+#[doc = "Possible values of the field `UCIRTXCLK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCIRTXCLKR {
+    #[doc = "BRCLK"]
+    UCIRTXCLK_0,
+    #[doc = "BITCLK16 when UCOS16 = 1. Otherwise, BRCLK."]
+    UCIRTXCLK_1,
+}
+impl UCIRTXCLKR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCIRTXCLKR::UCIRTXCLK_0 => false,
+            UCIRTXCLKR::UCIRTXCLK_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCIRTXCLKR {
+        match value {
+            false => UCIRTXCLKR::UCIRTXCLK_0,
+            true => UCIRTXCLKR::UCIRTXCLK_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCIRTXCLK_0`"]
+    #[inline]
+    pub fn is_ucirtxclk_0(&self) -> bool {
+        *self == UCIRTXCLKR::UCIRTXCLK_0
+    }
+    #[doc = "Checks if the value of the field is `UCIRTXCLK_1`"]
+    #[inline]
+    pub fn is_ucirtxclk_1(&self) -> bool {
+        *self == UCIRTXCLKR::UCIRTXCLK_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCIRTXPLR {
+    bits: u8,
+}
+impl UCIRTXPLR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `UCIRRXFE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCIRRXFER {
+    #[doc = "Receive filter disabled"]
+    UCIRRXFE_0,
+    #[doc = "Receive filter enabled"]
+    UCIRRXFE_1,
+}
+impl UCIRRXFER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCIRRXFER::UCIRRXFE_0 => false,
+            UCIRRXFER::UCIRRXFE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCIRRXFER {
+        match value {
+            false => UCIRRXFER::UCIRRXFE_0,
+            true => UCIRRXFER::UCIRRXFE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCIRRXFE_0`"]
+    #[inline]
+    pub fn is_ucirrxfe_0(&self) -> bool {
+        *self == UCIRRXFER::UCIRRXFE_0
+    }
+    #[doc = "Checks if the value of the field is `UCIRRXFE_1`"]
+    #[inline]
+    pub fn is_ucirrxfe_1(&self) -> bool {
+        *self == UCIRRXFER::UCIRRXFE_1
+    }
+}
+#[doc = "Possible values of the field `UCIRRXPL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCIRRXPLR {
+    #[doc = "IrDA transceiver delivers a high pulse when a light pulse is seen"]
+    UCIRRXPL_0,
+    #[doc = "IrDA transceiver delivers a low pulse when a light pulse is seen"]
+    UCIRRXPL_1,
+}
+impl UCIRRXPLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCIRRXPLR::UCIRRXPL_0 => false,
+            UCIRRXPLR::UCIRRXPL_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCIRRXPLR {
+        match value {
+            false => UCIRRXPLR::UCIRRXPL_0,
+            true => UCIRRXPLR::UCIRRXPL_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCIRRXPL_0`"]
+    #[inline]
+    pub fn is_ucirrxpl_0(&self) -> bool {
+        *self == UCIRRXPLR::UCIRRXPL_0
+    }
+    #[doc = "Checks if the value of the field is `UCIRRXPL_1`"]
+    #[inline]
+    pub fn is_ucirrxpl_1(&self) -> bool {
+        *self == UCIRRXPLR::UCIRRXPL_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCIRRXFLR {
+    bits: u8,
+}
+impl UCIRRXFLR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Values that can be written to the field `UCIREN`"]
+pub enum UCIRENW {
+    #[doc = "IrDA encoder/decoder disabled"]
+    UCIREN_0,
+    #[doc = "IrDA encoder/decoder enabled"]
+    UCIREN_1,
+}
+impl UCIRENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCIRENW::UCIREN_0 => false,
+            UCIRENW::UCIREN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCIRENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCIRENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCIRENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "IrDA encoder/decoder disabled"]
+    #[inline]
+    pub fn uciren_0(self) -> &'a mut W {
+        self.variant(UCIRENW::UCIREN_0)
+    }
+    #[doc = "IrDA encoder/decoder enabled"]
+    #[inline]
+    pub fn uciren_1(self) -> &'a mut W {
+        self.variant(UCIRENW::UCIREN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCIRTXCLK`"]
+pub enum UCIRTXCLKW {
+    #[doc = "BRCLK"]
+    UCIRTXCLK_0,
+    #[doc = "BITCLK16 when UCOS16 = 1. Otherwise, BRCLK."]
+    UCIRTXCLK_1,
+}
+impl UCIRTXCLKW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCIRTXCLKW::UCIRTXCLK_0 => false,
+            UCIRTXCLKW::UCIRTXCLK_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCIRTXCLKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCIRTXCLKW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCIRTXCLKW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "BRCLK"]
+    #[inline]
+    pub fn ucirtxclk_0(self) -> &'a mut W {
+        self.variant(UCIRTXCLKW::UCIRTXCLK_0)
+    }
+    #[doc = "BITCLK16 when UCOS16 = 1. Otherwise, BRCLK."]
+    #[inline]
+    pub fn ucirtxclk_1(self) -> &'a mut W {
+        self.variant(UCIRTXCLKW::UCIRTXCLK_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCIRTXPLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCIRTXPLW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 63;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCIRRXFE`"]
+pub enum UCIRRXFEW {
+    #[doc = "Receive filter disabled"]
+    UCIRRXFE_0,
+    #[doc = "Receive filter enabled"]
+    UCIRRXFE_1,
+}
+impl UCIRRXFEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCIRRXFEW::UCIRRXFE_0 => false,
+            UCIRRXFEW::UCIRRXFE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCIRRXFEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCIRRXFEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCIRRXFEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Receive filter disabled"]
+    #[inline]
+    pub fn ucirrxfe_0(self) -> &'a mut W {
+        self.variant(UCIRRXFEW::UCIRRXFE_0)
+    }
+    #[doc = "Receive filter enabled"]
+    #[inline]
+    pub fn ucirrxfe_1(self) -> &'a mut W {
+        self.variant(UCIRRXFEW::UCIRRXFE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCIRRXPL`"]
+pub enum UCIRRXPLW {
+    #[doc = "IrDA transceiver delivers a high pulse when a light pulse is seen"]
+    UCIRRXPL_0,
+    #[doc = "IrDA transceiver delivers a low pulse when a light pulse is seen"]
+    UCIRRXPL_1,
+}
+impl UCIRRXPLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCIRRXPLW::UCIRRXPL_0 => false,
+            UCIRRXPLW::UCIRRXPL_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCIRRXPLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCIRRXPLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCIRRXPLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "IrDA transceiver delivers a high pulse when a light pulse is seen"]
+    #[inline]
+    pub fn ucirrxpl_0(self) -> &'a mut W {
+        self.variant(UCIRRXPLW::UCIRRXPL_0)
+    }
+    #[doc = "IrDA transceiver delivers a low pulse when a light pulse is seen"]
+    #[inline]
+    pub fn ucirrxpl_1(self) -> &'a mut W {
+        self.variant(UCIRRXPLW::UCIRRXPL_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCIRRXFLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCIRRXFLW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - IrDA encoder/decoder enable"]
+    #[inline]
+    pub fn uciren(&self) -> UCIRENR {
+        UCIRENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - IrDA transmit pulse clock select"]
+    #[inline]
+    pub fn ucirtxclk(&self) -> UCIRTXCLKR {
+        UCIRTXCLKR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 2:7 - Transmit pulse length"]
+    #[inline]
+    pub fn ucirtxpl(&self) -> UCIRTXPLR {
+        let bits = {
+            const MASK: u8 = 63;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCIRTXPLR { bits }
+    }
+    #[doc = "Bit 8 - IrDA receive filter enabled"]
+    #[inline]
+    pub fn ucirrxfe(&self) -> UCIRRXFER {
+        UCIRRXFER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 9 - IrDA receive input UCAxRXD polarity"]
+    #[inline]
+    pub fn ucirrxpl(&self) -> UCIRRXPLR {
+        UCIRRXPLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 10:13 - Receive filter length"]
+    #[inline]
+    pub fn ucirrxfl(&self) -> UCIRRXFLR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCIRRXFLR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - IrDA encoder/decoder enable"]
+    #[inline]
+    pub fn uciren(&mut self) -> _UCIRENW {
+        _UCIRENW { w: self }
+    }
+    #[doc = "Bit 1 - IrDA transmit pulse clock select"]
+    #[inline]
+    pub fn ucirtxclk(&mut self) -> _UCIRTXCLKW {
+        _UCIRTXCLKW { w: self }
+    }
+    #[doc = "Bits 2:7 - Transmit pulse length"]
+    #[inline]
+    pub fn ucirtxpl(&mut self) -> _UCIRTXPLW {
+        _UCIRTXPLW { w: self }
+    }
+    #[doc = "Bit 8 - IrDA receive filter enabled"]
+    #[inline]
+    pub fn ucirrxfe(&mut self) -> _UCIRRXFEW {
+        _UCIRRXFEW { w: self }
+    }
+    #[doc = "Bit 9 - IrDA receive input UCAxRXD polarity"]
+    #[inline]
+    pub fn ucirrxpl(&mut self) -> _UCIRRXPLW {
+        _UCIRRXPLW { w: self }
+    }
+    #[doc = "Bits 10:13 - Receive filter length"]
+    #[inline]
+    pub fn ucirrxfl(&mut self) -> _UCIRRXFLW {
+        _UCIRRXFLW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a3/ucax_iv.rs b/example-source/msp432p401r/src/eusci_a3/ucax_iv.rs
new file mode 100644
index 0000000..9f6d12c
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a3/ucax_iv.rs
@@ -0,0 +1,97 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::UCAXIV {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `UCIV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCIVR {
+    #[doc = "No interrupt pending"]
+    UCIV_0,
+    #[doc = "Interrupt Source: Receive buffer full; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest"]
+    UCIV_2,
+    #[doc = "Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG"]
+    UCIV_4,
+    #[doc = "Interrupt Source: Start bit received; Interrupt Flag: UCSTTIFG"]
+    UCIV_6,
+    #[doc = "Interrupt Source: Transmit complete; Interrupt Flag: UCTXCPTIFG; Interrupt Priority: Lowest"]
+    UCIV_8,
+    #[doc = r" Reserved"]
+    _Reserved(u16),
+}
+impl UCIVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        match *self {
+            UCIVR::UCIV_0 => 0,
+            UCIVR::UCIV_2 => 2,
+            UCIVR::UCIV_4 => 4,
+            UCIVR::UCIV_6 => 6,
+            UCIVR::UCIV_8 => 8,
+            UCIVR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u16) -> UCIVR {
+        match value {
+            0 => UCIVR::UCIV_0,
+            2 => UCIVR::UCIV_2,
+            4 => UCIVR::UCIV_4,
+            6 => UCIVR::UCIV_6,
+            8 => UCIVR::UCIV_8,
+            i => UCIVR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCIV_0`"]
+    #[inline]
+    pub fn is_uciv_0(&self) -> bool {
+        *self == UCIVR::UCIV_0
+    }
+    #[doc = "Checks if the value of the field is `UCIV_2`"]
+    #[inline]
+    pub fn is_uciv_2(&self) -> bool {
+        *self == UCIVR::UCIV_2
+    }
+    #[doc = "Checks if the value of the field is `UCIV_4`"]
+    #[inline]
+    pub fn is_uciv_4(&self) -> bool {
+        *self == UCIVR::UCIV_4
+    }
+    #[doc = "Checks if the value of the field is `UCIV_6`"]
+    #[inline]
+    pub fn is_uciv_6(&self) -> bool {
+        *self == UCIVR::UCIV_6
+    }
+    #[doc = "Checks if the value of the field is `UCIV_8`"]
+    #[inline]
+    pub fn is_uciv_8(&self) -> bool {
+        *self == UCIVR::UCIV_8
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - eUSCI_A interrupt vector value"]
+    #[inline]
+    pub fn uciv(&self) -> UCIVR {
+        UCIVR::_from({
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a3/ucax_mctlw.rs b/example-source/msp432p401r/src/eusci_a3/ucax_mctlw.rs
new file mode 100644
index 0000000..aebce19
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a3/ucax_mctlw.rs
@@ -0,0 +1,265 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXMCTLW {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCOS16`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCOS16R {
+    #[doc = "Disabled"]
+    UCOS16_0,
+    #[doc = "Enabled"]
+    UCOS16_1,
+}
+impl UCOS16R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCOS16R::UCOS16_0 => false,
+            UCOS16R::UCOS16_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCOS16R {
+        match value {
+            false => UCOS16R::UCOS16_0,
+            true => UCOS16R::UCOS16_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCOS16_0`"]
+    #[inline]
+    pub fn is_ucos16_0(&self) -> bool {
+        *self == UCOS16R::UCOS16_0
+    }
+    #[doc = "Checks if the value of the field is `UCOS16_1`"]
+    #[inline]
+    pub fn is_ucos16_1(&self) -> bool {
+        *self == UCOS16R::UCOS16_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCBRFR {
+    bits: u8,
+}
+impl UCBRFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCBRSR {
+    bits: u8,
+}
+impl UCBRSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Values that can be written to the field `UCOS16`"]
+pub enum UCOS16W {
+    #[doc = "Disabled"]
+    UCOS16_0,
+    #[doc = "Enabled"]
+    UCOS16_1,
+}
+impl UCOS16W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCOS16W::UCOS16_0 => false,
+            UCOS16W::UCOS16_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCOS16W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCOS16W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCOS16W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disabled"]
+    #[inline]
+    pub fn ucos16_0(self) -> &'a mut W {
+        self.variant(UCOS16W::UCOS16_0)
+    }
+    #[doc = "Enabled"]
+    #[inline]
+    pub fn ucos16_1(self) -> &'a mut W {
+        self.variant(UCOS16W::UCOS16_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBRFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBRFW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBRSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBRSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Oversampling mode enabled"]
+    #[inline]
+    pub fn ucos16(&self) -> UCOS16R {
+        UCOS16R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 4:7 - First modulation stage select"]
+    #[inline]
+    pub fn ucbrf(&self) -> UCBRFR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCBRFR { bits }
+    }
+    #[doc = "Bits 8:15 - Second modulation stage select"]
+    #[inline]
+    pub fn ucbrs(&self) -> UCBRSR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCBRSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Oversampling mode enabled"]
+    #[inline]
+    pub fn ucos16(&mut self) -> _UCOS16W {
+        _UCOS16W { w: self }
+    }
+    #[doc = "Bits 4:7 - First modulation stage select"]
+    #[inline]
+    pub fn ucbrf(&mut self) -> _UCBRFW {
+        _UCBRFW { w: self }
+    }
+    #[doc = "Bits 8:15 - Second modulation stage select"]
+    #[inline]
+    pub fn ucbrs(&mut self) -> _UCBRSW {
+        _UCBRSW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a3/ucax_rxbuf.rs b/example-source/msp432p401r/src/eusci_a3/ucax_rxbuf.rs
new file mode 100644
index 0000000..d13ee75
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a3/ucax_rxbuf.rs
@@ -0,0 +1,41 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::UCAXRXBUF {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCRXBUFR {
+    bits: u8,
+}
+impl UCRXBUFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Receive data buffer"]
+    #[inline]
+    pub fn ucrxbuf(&self) -> UCRXBUFR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCRXBUFR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a3/ucax_statw.rs b/example-source/msp432p401r/src/eusci_a3/ucax_statw.rs
new file mode 100644
index 0000000..8992e75
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a3/ucax_statw.rs
@@ -0,0 +1,893 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXSTATW {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCBUSY`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBUSYR {
+    #[doc = "eUSCI_A inactive"]
+    UCBUSY_0,
+    #[doc = "eUSCI_A transmitting or receiving"]
+    UCBUSY_1,
+}
+impl UCBUSYR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBUSYR::UCBUSY_0 => false,
+            UCBUSYR::UCBUSY_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBUSYR {
+        match value {
+            false => UCBUSYR::UCBUSY_0,
+            true => UCBUSYR::UCBUSY_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBUSY_0`"]
+    #[inline]
+    pub fn is_ucbusy_0(&self) -> bool {
+        *self == UCBUSYR::UCBUSY_0
+    }
+    #[doc = "Checks if the value of the field is `UCBUSY_1`"]
+    #[inline]
+    pub fn is_ucbusy_1(&self) -> bool {
+        *self == UCBUSYR::UCBUSY_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCADDR_UCIDLER {
+    bits: bool,
+}
+impl UCADDR_UCIDLER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `UCRXERR`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXERRR {
+    #[doc = "No receive errors detected"]
+    UCRXERR_0,
+    #[doc = "Receive error detected"]
+    UCRXERR_1,
+}
+impl UCRXERRR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXERRR::UCRXERR_0 => false,
+            UCRXERRR::UCRXERR_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXERRR {
+        match value {
+            false => UCRXERRR::UCRXERR_0,
+            true => UCRXERRR::UCRXERR_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXERR_0`"]
+    #[inline]
+    pub fn is_ucrxerr_0(&self) -> bool {
+        *self == UCRXERRR::UCRXERR_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXERR_1`"]
+    #[inline]
+    pub fn is_ucrxerr_1(&self) -> bool {
+        *self == UCRXERRR::UCRXERR_1
+    }
+}
+#[doc = "Possible values of the field `UCBRK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBRKR {
+    #[doc = "No break condition"]
+    UCBRK_0,
+    #[doc = "Break condition occurred"]
+    UCBRK_1,
+}
+impl UCBRKR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBRKR::UCBRK_0 => false,
+            UCBRKR::UCBRK_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBRKR {
+        match value {
+            false => UCBRKR::UCBRK_0,
+            true => UCBRKR::UCBRK_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBRK_0`"]
+    #[inline]
+    pub fn is_ucbrk_0(&self) -> bool {
+        *self == UCBRKR::UCBRK_0
+    }
+    #[doc = "Checks if the value of the field is `UCBRK_1`"]
+    #[inline]
+    pub fn is_ucbrk_1(&self) -> bool {
+        *self == UCBRKR::UCBRK_1
+    }
+}
+#[doc = "Possible values of the field `UCPE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCPER {
+    #[doc = "No error"]
+    UCPE_0,
+    #[doc = "Character received with parity error"]
+    UCPE_1,
+}
+impl UCPER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCPER::UCPE_0 => false,
+            UCPER::UCPE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCPER {
+        match value {
+            false => UCPER::UCPE_0,
+            true => UCPER::UCPE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCPE_0`"]
+    #[inline]
+    pub fn is_ucpe_0(&self) -> bool {
+        *self == UCPER::UCPE_0
+    }
+    #[doc = "Checks if the value of the field is `UCPE_1`"]
+    #[inline]
+    pub fn is_ucpe_1(&self) -> bool {
+        *self == UCPER::UCPE_1
+    }
+}
+#[doc = "Possible values of the field `UCOE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCOER {
+    #[doc = "No error"]
+    UCOE_0,
+    #[doc = "Overrun error occurred"]
+    UCOE_1,
+}
+impl UCOER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCOER::UCOE_0 => false,
+            UCOER::UCOE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCOER {
+        match value {
+            false => UCOER::UCOE_0,
+            true => UCOER::UCOE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCOE_0`"]
+    #[inline]
+    pub fn is_ucoe_0(&self) -> bool {
+        *self == UCOER::UCOE_0
+    }
+    #[doc = "Checks if the value of the field is `UCOE_1`"]
+    #[inline]
+    pub fn is_ucoe_1(&self) -> bool {
+        *self == UCOER::UCOE_1
+    }
+}
+#[doc = "Possible values of the field `UCFE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCFER {
+    #[doc = "No error"]
+    UCFE_0,
+    #[doc = "Character received with low stop bit"]
+    UCFE_1,
+}
+impl UCFER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCFER::UCFE_0 => false,
+            UCFER::UCFE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCFER {
+        match value {
+            false => UCFER::UCFE_0,
+            true => UCFER::UCFE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCFE_0`"]
+    #[inline]
+    pub fn is_ucfe_0(&self) -> bool {
+        *self == UCFER::UCFE_0
+    }
+    #[doc = "Checks if the value of the field is `UCFE_1`"]
+    #[inline]
+    pub fn is_ucfe_1(&self) -> bool {
+        *self == UCFER::UCFE_1
+    }
+}
+#[doc = "Possible values of the field `UCLISTEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCLISTENR {
+    #[doc = "Disabled"]
+    UCLISTEN_0,
+    #[doc = "Enabled. UCAxTXD is internally fed back to the receiver"]
+    UCLISTEN_1,
+}
+impl UCLISTENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCLISTENR::UCLISTEN_0 => false,
+            UCLISTENR::UCLISTEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCLISTENR {
+        match value {
+            false => UCLISTENR::UCLISTEN_0,
+            true => UCLISTENR::UCLISTEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCLISTEN_0`"]
+    #[inline]
+    pub fn is_uclisten_0(&self) -> bool {
+        *self == UCLISTENR::UCLISTEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCLISTEN_1`"]
+    #[inline]
+    pub fn is_uclisten_1(&self) -> bool {
+        *self == UCLISTENR::UCLISTEN_1
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCADDR_UCIDLEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCADDR_UCIDLEW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXERR`"]
+pub enum UCRXERRW {
+    #[doc = "No receive errors detected"]
+    UCRXERR_0,
+    #[doc = "Receive error detected"]
+    UCRXERR_1,
+}
+impl UCRXERRW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXERRW::UCRXERR_0 => false,
+            UCRXERRW::UCRXERR_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXERRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXERRW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXERRW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No receive errors detected"]
+    #[inline]
+    pub fn ucrxerr_0(self) -> &'a mut W {
+        self.variant(UCRXERRW::UCRXERR_0)
+    }
+    #[doc = "Receive error detected"]
+    #[inline]
+    pub fn ucrxerr_1(self) -> &'a mut W {
+        self.variant(UCRXERRW::UCRXERR_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCBRK`"]
+pub enum UCBRKW {
+    #[doc = "No break condition"]
+    UCBRK_0,
+    #[doc = "Break condition occurred"]
+    UCBRK_1,
+}
+impl UCBRKW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCBRKW::UCBRK_0 => false,
+            UCBRKW::UCBRK_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBRKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBRKW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCBRKW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No break condition"]
+    #[inline]
+    pub fn ucbrk_0(self) -> &'a mut W {
+        self.variant(UCBRKW::UCBRK_0)
+    }
+    #[doc = "Break condition occurred"]
+    #[inline]
+    pub fn ucbrk_1(self) -> &'a mut W {
+        self.variant(UCBRKW::UCBRK_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCPE`"]
+pub enum UCPEW {
+    #[doc = "No error"]
+    UCPE_0,
+    #[doc = "Character received with parity error"]
+    UCPE_1,
+}
+impl UCPEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCPEW::UCPE_0 => false,
+            UCPEW::UCPE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCPEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCPEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCPEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No error"]
+    #[inline]
+    pub fn ucpe_0(self) -> &'a mut W {
+        self.variant(UCPEW::UCPE_0)
+    }
+    #[doc = "Character received with parity error"]
+    #[inline]
+    pub fn ucpe_1(self) -> &'a mut W {
+        self.variant(UCPEW::UCPE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCOE`"]
+pub enum UCOEW {
+    #[doc = "No error"]
+    UCOE_0,
+    #[doc = "Overrun error occurred"]
+    UCOE_1,
+}
+impl UCOEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCOEW::UCOE_0 => false,
+            UCOEW::UCOE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCOEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCOEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCOEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No error"]
+    #[inline]
+    pub fn ucoe_0(self) -> &'a mut W {
+        self.variant(UCOEW::UCOE_0)
+    }
+    #[doc = "Overrun error occurred"]
+    #[inline]
+    pub fn ucoe_1(self) -> &'a mut W {
+        self.variant(UCOEW::UCOE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCFE`"]
+pub enum UCFEW {
+    #[doc = "No error"]
+    UCFE_0,
+    #[doc = "Character received with low stop bit"]
+    UCFE_1,
+}
+impl UCFEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCFEW::UCFE_0 => false,
+            UCFEW::UCFE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCFEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCFEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCFEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No error"]
+    #[inline]
+    pub fn ucfe_0(self) -> &'a mut W {
+        self.variant(UCFEW::UCFE_0)
+    }
+    #[doc = "Character received with low stop bit"]
+    #[inline]
+    pub fn ucfe_1(self) -> &'a mut W {
+        self.variant(UCFEW::UCFE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCLISTEN`"]
+pub enum UCLISTENW {
+    #[doc = "Disabled"]
+    UCLISTEN_0,
+    #[doc = "Enabled. UCAxTXD is internally fed back to the receiver"]
+    UCLISTEN_1,
+}
+impl UCLISTENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCLISTENW::UCLISTEN_0 => false,
+            UCLISTENW::UCLISTEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCLISTENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCLISTENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCLISTENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disabled"]
+    #[inline]
+    pub fn uclisten_0(self) -> &'a mut W {
+        self.variant(UCLISTENW::UCLISTEN_0)
+    }
+    #[doc = "Enabled. UCAxTXD is internally fed back to the receiver"]
+    #[inline]
+    pub fn uclisten_1(self) -> &'a mut W {
+        self.variant(UCLISTENW::UCLISTEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - eUSCI_A busy"]
+    #[inline]
+    pub fn ucbusy(&self) -> UCBUSYR {
+        UCBUSYR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Address received / Idle line detected"]
+    #[inline]
+    pub fn ucaddr_ucidle(&self) -> UCADDR_UCIDLER {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        };
+        UCADDR_UCIDLER { bits }
+    }
+    #[doc = "Bit 2 - Receive error flag"]
+    #[inline]
+    pub fn ucrxerr(&self) -> UCRXERRR {
+        UCRXERRR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Break detect flag"]
+    #[inline]
+    pub fn ucbrk(&self) -> UCBRKR {
+        UCBRKR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 4 - Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read."]
+    #[inline]
+    pub fn ucpe(&self) -> UCPER {
+        UCPER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - Overrun error flag"]
+    #[inline]
+    pub fn ucoe(&self) -> UCOER {
+        UCOER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 6 - Framing error flag"]
+    #[inline]
+    pub fn ucfe(&self) -> UCFER {
+        UCFER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 7 - Listen enable"]
+    #[inline]
+    pub fn uclisten(&self) -> UCLISTENR {
+        UCLISTENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 1 - Address received / Idle line detected"]
+    #[inline]
+    pub fn ucaddr_ucidle(&mut self) -> _UCADDR_UCIDLEW {
+        _UCADDR_UCIDLEW { w: self }
+    }
+    #[doc = "Bit 2 - Receive error flag"]
+    #[inline]
+    pub fn ucrxerr(&mut self) -> _UCRXERRW {
+        _UCRXERRW { w: self }
+    }
+    #[doc = "Bit 3 - Break detect flag"]
+    #[inline]
+    pub fn ucbrk(&mut self) -> _UCBRKW {
+        _UCBRKW { w: self }
+    }
+    #[doc = "Bit 4 - Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read."]
+    #[inline]
+    pub fn ucpe(&mut self) -> _UCPEW {
+        _UCPEW { w: self }
+    }
+    #[doc = "Bit 5 - Overrun error flag"]
+    #[inline]
+    pub fn ucoe(&mut self) -> _UCOEW {
+        _UCOEW { w: self }
+    }
+    #[doc = "Bit 6 - Framing error flag"]
+    #[inline]
+    pub fn ucfe(&mut self) -> _UCFEW {
+        _UCFEW { w: self }
+    }
+    #[doc = "Bit 7 - Listen enable"]
+    #[inline]
+    pub fn uclisten(&mut self) -> _UCLISTENW {
+        _UCLISTENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_a3/ucax_txbuf.rs b/example-source/msp432p401r/src/eusci_a3/ucax_txbuf.rs
new file mode 100644
index 0000000..47ca264
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_a3/ucax_txbuf.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCAXTXBUF {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCTXBUFR {
+    bits: u8,
+}
+impl UCTXBUFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXBUFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXBUFW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Transmit data buffer"]
+    #[inline]
+    pub fn uctxbuf(&self) -> UCTXBUFR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCTXBUFR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Transmit data buffer"]
+    #[inline]
+    pub fn uctxbuf(&mut self) -> _UCTXBUFW {
+        _UCTXBUFW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b0.rs b/example-source/msp432p401r/src/eusci_b0.rs
new file mode 100644
index 0000000..e897801
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b0.rs
@@ -0,0 +1,143 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - eUSCI_Bx Control Word Register 0"]
+    pub ucbx_ctlw0: UCBXCTLW0,
+    #[doc = "0x02 - eUSCI_Bx Control Word Register 1"]
+    pub ucbx_ctlw1: UCBXCTLW1,
+    _reserved0: [u8; 2usize],
+    #[doc = "0x06 - eUSCI_Bx Baud Rate Control Word Register"]
+    pub ucbx_brw: UCBXBRW,
+    #[doc = "0x08 - eUSCI_Bx Status Register"]
+    pub ucbx_statw: UCBXSTATW,
+    #[doc = "0x0a - eUSCI_Bx Byte Counter Threshold Register"]
+    pub ucbx_tbcnt: UCBXTBCNT,
+    #[doc = "0x0c - eUSCI_Bx Receive Buffer Register"]
+    pub ucbx_rxbuf: UCBXRXBUF,
+    #[doc = "0x0e - eUSCI_Bx Transmit Buffer Register"]
+    pub ucbx_txbuf: UCBXTXBUF,
+    _reserved1: [u8; 4usize],
+    #[doc = "0x14 - eUSCI_Bx I2C Own Address 0 Register"]
+    pub ucbx_i2coa0: UCBXI2COA0,
+    #[doc = "0x16 - eUSCI_Bx I2C Own Address 1 Register"]
+    pub ucbx_i2coa1: UCBXI2COA1,
+    #[doc = "0x18 - eUSCI_Bx I2C Own Address 2 Register"]
+    pub ucbx_i2coa2: UCBXI2COA2,
+    #[doc = "0x1a - eUSCI_Bx I2C Own Address 3 Register"]
+    pub ucbx_i2coa3: UCBXI2COA3,
+    #[doc = "0x1c - eUSCI_Bx I2C Received Address Register"]
+    pub ucbx_addrx: UCBXADDRX,
+    #[doc = "0x1e - eUSCI_Bx I2C Address Mask Register"]
+    pub ucbx_addmask: UCBXADDMASK,
+    #[doc = "0x20 - eUSCI_Bx I2C Slave Address Register"]
+    pub ucbx_i2csa: UCBXI2CSA,
+    _reserved2: [u8; 8usize],
+    #[doc = "0x2a - eUSCI_Bx Interrupt Enable Register"]
+    pub ucbx_ie: UCBXIE,
+    #[doc = "0x2c - eUSCI_Bx Interrupt Flag Register"]
+    pub ucbx_ifg: UCBXIFG,
+    #[doc = "0x2e - eUSCI_Bx Interrupt Vector Register"]
+    pub ucbx_iv: UCBXIV,
+}
+#[doc = "eUSCI_Bx Control Word Register 0"]
+pub struct UCBXCTLW0 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Control Word Register 0"]
+pub mod ucbx_ctlw0;
+#[doc = "eUSCI_Bx Control Word Register 1"]
+pub struct UCBXCTLW1 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Control Word Register 1"]
+pub mod ucbx_ctlw1;
+#[doc = "eUSCI_Bx Baud Rate Control Word Register"]
+pub struct UCBXBRW {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Baud Rate Control Word Register"]
+pub mod ucbx_brw;
+#[doc = "eUSCI_Bx Status Register"]
+pub struct UCBXSTATW {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Status Register"]
+pub mod ucbx_statw;
+#[doc = "eUSCI_Bx Byte Counter Threshold Register"]
+pub struct UCBXTBCNT {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Byte Counter Threshold Register"]
+pub mod ucbx_tbcnt;
+#[doc = "eUSCI_Bx Receive Buffer Register"]
+pub struct UCBXRXBUF {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Receive Buffer Register"]
+pub mod ucbx_rxbuf;
+#[doc = "eUSCI_Bx Transmit Buffer Register"]
+pub struct UCBXTXBUF {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Transmit Buffer Register"]
+pub mod ucbx_txbuf;
+#[doc = "eUSCI_Bx I2C Own Address 0 Register"]
+pub struct UCBXI2COA0 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx I2C Own Address 0 Register"]
+pub mod ucbx_i2coa0;
+#[doc = "eUSCI_Bx I2C Own Address 1 Register"]
+pub struct UCBXI2COA1 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx I2C Own Address 1 Register"]
+pub mod ucbx_i2coa1;
+#[doc = "eUSCI_Bx I2C Own Address 2 Register"]
+pub struct UCBXI2COA2 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx I2C Own Address 2 Register"]
+pub mod ucbx_i2coa2;
+#[doc = "eUSCI_Bx I2C Own Address 3 Register"]
+pub struct UCBXI2COA3 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx I2C Own Address 3 Register"]
+pub mod ucbx_i2coa3;
+#[doc = "eUSCI_Bx I2C Received Address Register"]
+pub struct UCBXADDRX {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx I2C Received Address Register"]
+pub mod ucbx_addrx;
+#[doc = "eUSCI_Bx I2C Address Mask Register"]
+pub struct UCBXADDMASK {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx I2C Address Mask Register"]
+pub mod ucbx_addmask;
+#[doc = "eUSCI_Bx I2C Slave Address Register"]
+pub struct UCBXI2CSA {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx I2C Slave Address Register"]
+pub mod ucbx_i2csa;
+#[doc = "eUSCI_Bx Interrupt Enable Register"]
+pub struct UCBXIE {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Interrupt Enable Register"]
+pub mod ucbx_ie;
+#[doc = "eUSCI_Bx Interrupt Flag Register"]
+pub struct UCBXIFG {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Interrupt Flag Register"]
+pub mod ucbx_ifg;
+#[doc = "eUSCI_Bx Interrupt Vector Register"]
+pub struct UCBXIV {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Interrupt Vector Register"]
+pub mod ucbx_iv;
diff --git a/example-source/msp432p401r/src/eusci_b0/ucbx_addmask.rs b/example-source/msp432p401r/src/eusci_b0/ucbx_addmask.rs
new file mode 100644
index 0000000..856e7a6
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b0/ucbx_addmask.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXADDMASK {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ADDMASKR {
+    bits: u16,
+}
+impl ADDMASKR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADDMASKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADDMASKW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated. Modify only when UCSWRST = 1."]
+    #[inline]
+    pub fn addmask(&self) -> ADDMASKR {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        ADDMASKR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 1023 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:9 - Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated. Modify only when UCSWRST = 1."]
+    #[inline]
+    pub fn addmask(&mut self) -> _ADDMASKW {
+        _ADDMASKW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b0/ucbx_addrx.rs b/example-source/msp432p401r/src/eusci_b0/ucbx_addrx.rs
new file mode 100644
index 0000000..595f1cb
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b0/ucbx_addrx.rs
@@ -0,0 +1,41 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::UCBXADDRX {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ADDRXR {
+    bits: u16,
+}
+impl ADDRXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - Received Address Register"]
+    #[inline]
+    pub fn addrx(&self) -> ADDRXR {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        ADDRXR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b0/ucbx_brw.rs b/example-source/msp432p401r/src/eusci_b0/ucbx_brw.rs
new file mode 100644
index 0000000..1ed885e
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b0/ucbx_brw.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXBRW {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCBRR {
+    bits: u16,
+}
+impl UCBRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBRW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Bit clock prescaler"]
+    #[inline]
+    pub fn ucbr(&self) -> UCBRR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        UCBRR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Bit clock prescaler"]
+    #[inline]
+    pub fn ucbr(&mut self) -> _UCBRW {
+        _UCBRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b0/ucbx_ctlw0.rs b/example-source/msp432p401r/src/eusci_b0/ucbx_ctlw0.rs
new file mode 100644
index 0000000..4baf4f9
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b0/ucbx_ctlw0.rs
@@ -0,0 +1,1645 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXCTLW0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCSWRST`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSWRSTR {
+    #[doc = "Disabled. eUSCI_B reset released for operation"]
+    UCSWRST_0,
+    #[doc = "Enabled. eUSCI_B logic held in reset state"]
+    UCSWRST_1,
+}
+impl UCSWRSTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSWRSTR::UCSWRST_0 => false,
+            UCSWRSTR::UCSWRST_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSWRSTR {
+        match value {
+            false => UCSWRSTR::UCSWRST_0,
+            true => UCSWRSTR::UCSWRST_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSWRST_0`"]
+    #[inline]
+    pub fn is_ucswrst_0(&self) -> bool {
+        *self == UCSWRSTR::UCSWRST_0
+    }
+    #[doc = "Checks if the value of the field is `UCSWRST_1`"]
+    #[inline]
+    pub fn is_ucswrst_1(&self) -> bool {
+        *self == UCSWRSTR::UCSWRST_1
+    }
+}
+#[doc = "Possible values of the field `UCTXSTT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXSTTR {
+    #[doc = "Do not generate START condition"]
+    UCTXSTT_0,
+    #[doc = "Generate START condition"]
+    UCTXSTT_1,
+}
+impl UCTXSTTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXSTTR::UCTXSTT_0 => false,
+            UCTXSTTR::UCTXSTT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXSTTR {
+        match value {
+            false => UCTXSTTR::UCTXSTT_0,
+            true => UCTXSTTR::UCTXSTT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXSTT_0`"]
+    #[inline]
+    pub fn is_uctxstt_0(&self) -> bool {
+        *self == UCTXSTTR::UCTXSTT_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXSTT_1`"]
+    #[inline]
+    pub fn is_uctxstt_1(&self) -> bool {
+        *self == UCTXSTTR::UCTXSTT_1
+    }
+}
+#[doc = "Possible values of the field `UCTXSTP`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXSTPR {
+    #[doc = "No STOP generated"]
+    UCTXSTP_0,
+    #[doc = "Generate STOP"]
+    UCTXSTP_1,
+}
+impl UCTXSTPR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXSTPR::UCTXSTP_0 => false,
+            UCTXSTPR::UCTXSTP_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXSTPR {
+        match value {
+            false => UCTXSTPR::UCTXSTP_0,
+            true => UCTXSTPR::UCTXSTP_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXSTP_0`"]
+    #[inline]
+    pub fn is_uctxstp_0(&self) -> bool {
+        *self == UCTXSTPR::UCTXSTP_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXSTP_1`"]
+    #[inline]
+    pub fn is_uctxstp_1(&self) -> bool {
+        *self == UCTXSTPR::UCTXSTP_1
+    }
+}
+#[doc = "Possible values of the field `UCTXNACK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXNACKR {
+    #[doc = "Acknowledge normally"]
+    UCTXNACK_0,
+    #[doc = "Generate NACK"]
+    UCTXNACK_1,
+}
+impl UCTXNACKR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXNACKR::UCTXNACK_0 => false,
+            UCTXNACKR::UCTXNACK_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXNACKR {
+        match value {
+            false => UCTXNACKR::UCTXNACK_0,
+            true => UCTXNACKR::UCTXNACK_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXNACK_0`"]
+    #[inline]
+    pub fn is_uctxnack_0(&self) -> bool {
+        *self == UCTXNACKR::UCTXNACK_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXNACK_1`"]
+    #[inline]
+    pub fn is_uctxnack_1(&self) -> bool {
+        *self == UCTXNACKR::UCTXNACK_1
+    }
+}
+#[doc = "Possible values of the field `UCTR`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTRR {
+    #[doc = "Receiver"]
+    UCTR_0,
+    #[doc = "Transmitter"]
+    UCTR_1,
+}
+impl UCTRR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTRR::UCTR_0 => false,
+            UCTRR::UCTR_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTRR {
+        match value {
+            false => UCTRR::UCTR_0,
+            true => UCTRR::UCTR_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTR_0`"]
+    #[inline]
+    pub fn is_uctr_0(&self) -> bool {
+        *self == UCTRR::UCTR_0
+    }
+    #[doc = "Checks if the value of the field is `UCTR_1`"]
+    #[inline]
+    pub fn is_uctr_1(&self) -> bool {
+        *self == UCTRR::UCTR_1
+    }
+}
+#[doc = "Possible values of the field `UCTXACK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXACKR {
+    #[doc = "Do not acknowledge the slave address"]
+    UCTXACK_0,
+    #[doc = "Acknowledge the slave address"]
+    UCTXACK_1,
+}
+impl UCTXACKR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXACKR::UCTXACK_0 => false,
+            UCTXACKR::UCTXACK_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXACKR {
+        match value {
+            false => UCTXACKR::UCTXACK_0,
+            true => UCTXACKR::UCTXACK_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXACK_0`"]
+    #[inline]
+    pub fn is_uctxack_0(&self) -> bool {
+        *self == UCTXACKR::UCTXACK_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXACK_1`"]
+    #[inline]
+    pub fn is_uctxack_1(&self) -> bool {
+        *self == UCTXACKR::UCTXACK_1
+    }
+}
+#[doc = "Possible values of the field `UCSSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSSELR {
+    #[doc = "UCLKI"]
+    UCSSEL_0,
+    #[doc = "ACLK"]
+    UCSSEL_1,
+    #[doc = "SMCLK"]
+    UCSSEL_2,
+    #[doc = "SMCLK"]
+    UCSSEL_3,
+}
+impl UCSSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCSSELR::UCSSEL_0 => 0,
+            UCSSELR::UCSSEL_1 => 1,
+            UCSSELR::UCSSEL_2 => 2,
+            UCSSELR::UCSSEL_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCSSELR {
+        match value {
+            0 => UCSSELR::UCSSEL_0,
+            1 => UCSSELR::UCSSEL_1,
+            2 => UCSSELR::UCSSEL_2,
+            3 => UCSSELR::UCSSEL_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSSEL_0`"]
+    #[inline]
+    pub fn is_ucssel_0(&self) -> bool {
+        *self == UCSSELR::UCSSEL_0
+    }
+    #[doc = "Checks if the value of the field is `UCSSEL_1`"]
+    #[inline]
+    pub fn is_ucssel_1(&self) -> bool {
+        *self == UCSSELR::UCSSEL_1
+    }
+    #[doc = "Checks if the value of the field is `UCSSEL_2`"]
+    #[inline]
+    pub fn is_ucssel_2(&self) -> bool {
+        *self == UCSSELR::UCSSEL_2
+    }
+    #[doc = "Checks if the value of the field is `UCSSEL_3`"]
+    #[inline]
+    pub fn is_ucssel_3(&self) -> bool {
+        *self == UCSSELR::UCSSEL_3
+    }
+}
+#[doc = "Possible values of the field `UCSYNC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSYNCR {
+    #[doc = "Asynchronous mode"]
+    UCSYNC_0,
+    #[doc = "Synchronous mode"]
+    UCSYNC_1,
+}
+impl UCSYNCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSYNCR::UCSYNC_0 => false,
+            UCSYNCR::UCSYNC_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSYNCR {
+        match value {
+            false => UCSYNCR::UCSYNC_0,
+            true => UCSYNCR::UCSYNC_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSYNC_0`"]
+    #[inline]
+    pub fn is_ucsync_0(&self) -> bool {
+        *self == UCSYNCR::UCSYNC_0
+    }
+    #[doc = "Checks if the value of the field is `UCSYNC_1`"]
+    #[inline]
+    pub fn is_ucsync_1(&self) -> bool {
+        *self == UCSYNCR::UCSYNC_1
+    }
+}
+#[doc = "Possible values of the field `UCMODE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCMODER {
+    #[doc = "3-pin SPI"]
+    UCMODE_0,
+    #[doc = "4-pin SPI (master or slave enabled if STE = 1)"]
+    UCMODE_1,
+    #[doc = "4-pin SPI (master or slave enabled if STE = 0)"]
+    UCMODE_2,
+    #[doc = "I2C mode"]
+    UCMODE_3,
+}
+impl UCMODER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCMODER::UCMODE_0 => 0,
+            UCMODER::UCMODE_1 => 1,
+            UCMODER::UCMODE_2 => 2,
+            UCMODER::UCMODE_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCMODER {
+        match value {
+            0 => UCMODER::UCMODE_0,
+            1 => UCMODER::UCMODE_1,
+            2 => UCMODER::UCMODE_2,
+            3 => UCMODER::UCMODE_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_0`"]
+    #[inline]
+    pub fn is_ucmode_0(&self) -> bool {
+        *self == UCMODER::UCMODE_0
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_1`"]
+    #[inline]
+    pub fn is_ucmode_1(&self) -> bool {
+        *self == UCMODER::UCMODE_1
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_2`"]
+    #[inline]
+    pub fn is_ucmode_2(&self) -> bool {
+        *self == UCMODER::UCMODE_2
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_3`"]
+    #[inline]
+    pub fn is_ucmode_3(&self) -> bool {
+        *self == UCMODER::UCMODE_3
+    }
+}
+#[doc = "Possible values of the field `UCMST`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCMSTR {
+    #[doc = "Slave mode"]
+    UCMST_0,
+    #[doc = "Master mode"]
+    UCMST_1,
+}
+impl UCMSTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCMSTR::UCMST_0 => false,
+            UCMSTR::UCMST_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCMSTR {
+        match value {
+            false => UCMSTR::UCMST_0,
+            true => UCMSTR::UCMST_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCMST_0`"]
+    #[inline]
+    pub fn is_ucmst_0(&self) -> bool {
+        *self == UCMSTR::UCMST_0
+    }
+    #[doc = "Checks if the value of the field is `UCMST_1`"]
+    #[inline]
+    pub fn is_ucmst_1(&self) -> bool {
+        *self == UCMSTR::UCMST_1
+    }
+}
+#[doc = "Possible values of the field `UCMM`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCMMR {
+    #[doc = "Single master environment. There is no other master in the system. The address compare unit is disabled."]
+    UCMM_0,
+    #[doc = "Multi-master environment"]
+    UCMM_1,
+}
+impl UCMMR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCMMR::UCMM_0 => false,
+            UCMMR::UCMM_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCMMR {
+        match value {
+            false => UCMMR::UCMM_0,
+            true => UCMMR::UCMM_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCMM_0`"]
+    #[inline]
+    pub fn is_ucmm_0(&self) -> bool {
+        *self == UCMMR::UCMM_0
+    }
+    #[doc = "Checks if the value of the field is `UCMM_1`"]
+    #[inline]
+    pub fn is_ucmm_1(&self) -> bool {
+        *self == UCMMR::UCMM_1
+    }
+}
+#[doc = "Possible values of the field `UCSLA10`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSLA10R {
+    #[doc = "Address slave with 7-bit address"]
+    UCSLA10_0,
+    #[doc = "Address slave with 10-bit address"]
+    UCSLA10_1,
+}
+impl UCSLA10R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSLA10R::UCSLA10_0 => false,
+            UCSLA10R::UCSLA10_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSLA10R {
+        match value {
+            false => UCSLA10R::UCSLA10_0,
+            true => UCSLA10R::UCSLA10_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSLA10_0`"]
+    #[inline]
+    pub fn is_ucsla10_0(&self) -> bool {
+        *self == UCSLA10R::UCSLA10_0
+    }
+    #[doc = "Checks if the value of the field is `UCSLA10_1`"]
+    #[inline]
+    pub fn is_ucsla10_1(&self) -> bool {
+        *self == UCSLA10R::UCSLA10_1
+    }
+}
+#[doc = "Possible values of the field `UCA10`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCA10R {
+    #[doc = "Own address is a 7-bit address"]
+    UCA10_0,
+    #[doc = "Own address is a 10-bit address"]
+    UCA10_1,
+}
+impl UCA10R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCA10R::UCA10_0 => false,
+            UCA10R::UCA10_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCA10R {
+        match value {
+            false => UCA10R::UCA10_0,
+            true => UCA10R::UCA10_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCA10_0`"]
+    #[inline]
+    pub fn is_uca10_0(&self) -> bool {
+        *self == UCA10R::UCA10_0
+    }
+    #[doc = "Checks if the value of the field is `UCA10_1`"]
+    #[inline]
+    pub fn is_uca10_1(&self) -> bool {
+        *self == UCA10R::UCA10_1
+    }
+}
+#[doc = "Values that can be written to the field `UCSWRST`"]
+pub enum UCSWRSTW {
+    #[doc = "Disabled. eUSCI_B reset released for operation"]
+    UCSWRST_0,
+    #[doc = "Enabled. eUSCI_B logic held in reset state"]
+    UCSWRST_1,
+}
+impl UCSWRSTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSWRSTW::UCSWRST_0 => false,
+            UCSWRSTW::UCSWRST_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSWRSTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSWRSTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSWRSTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disabled. eUSCI_B reset released for operation"]
+    #[inline]
+    pub fn ucswrst_0(self) -> &'a mut W {
+        self.variant(UCSWRSTW::UCSWRST_0)
+    }
+    #[doc = "Enabled. eUSCI_B logic held in reset state"]
+    #[inline]
+    pub fn ucswrst_1(self) -> &'a mut W {
+        self.variant(UCSWRSTW::UCSWRST_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXSTT`"]
+pub enum UCTXSTTW {
+    #[doc = "Do not generate START condition"]
+    UCTXSTT_0,
+    #[doc = "Generate START condition"]
+    UCTXSTT_1,
+}
+impl UCTXSTTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXSTTW::UCTXSTT_0 => false,
+            UCTXSTTW::UCTXSTT_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXSTTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXSTTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXSTTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Do not generate START condition"]
+    #[inline]
+    pub fn uctxstt_0(self) -> &'a mut W {
+        self.variant(UCTXSTTW::UCTXSTT_0)
+    }
+    #[doc = "Generate START condition"]
+    #[inline]
+    pub fn uctxstt_1(self) -> &'a mut W {
+        self.variant(UCTXSTTW::UCTXSTT_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXSTP`"]
+pub enum UCTXSTPW {
+    #[doc = "No STOP generated"]
+    UCTXSTP_0,
+    #[doc = "Generate STOP"]
+    UCTXSTP_1,
+}
+impl UCTXSTPW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXSTPW::UCTXSTP_0 => false,
+            UCTXSTPW::UCTXSTP_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXSTPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXSTPW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXSTPW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No STOP generated"]
+    #[inline]
+    pub fn uctxstp_0(self) -> &'a mut W {
+        self.variant(UCTXSTPW::UCTXSTP_0)
+    }
+    #[doc = "Generate STOP"]
+    #[inline]
+    pub fn uctxstp_1(self) -> &'a mut W {
+        self.variant(UCTXSTPW::UCTXSTP_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXNACK`"]
+pub enum UCTXNACKW {
+    #[doc = "Acknowledge normally"]
+    UCTXNACK_0,
+    #[doc = "Generate NACK"]
+    UCTXNACK_1,
+}
+impl UCTXNACKW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXNACKW::UCTXNACK_0 => false,
+            UCTXNACKW::UCTXNACK_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXNACKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXNACKW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXNACKW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Acknowledge normally"]
+    #[inline]
+    pub fn uctxnack_0(self) -> &'a mut W {
+        self.variant(UCTXNACKW::UCTXNACK_0)
+    }
+    #[doc = "Generate NACK"]
+    #[inline]
+    pub fn uctxnack_1(self) -> &'a mut W {
+        self.variant(UCTXNACKW::UCTXNACK_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTR`"]
+pub enum UCTRW {
+    #[doc = "Receiver"]
+    UCTR_0,
+    #[doc = "Transmitter"]
+    UCTR_1,
+}
+impl UCTRW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTRW::UCTR_0 => false,
+            UCTRW::UCTR_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTRW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTRW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Receiver"]
+    #[inline]
+    pub fn uctr_0(self) -> &'a mut W {
+        self.variant(UCTRW::UCTR_0)
+    }
+    #[doc = "Transmitter"]
+    #[inline]
+    pub fn uctr_1(self) -> &'a mut W {
+        self.variant(UCTRW::UCTR_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXACK`"]
+pub enum UCTXACKW {
+    #[doc = "Do not acknowledge the slave address"]
+    UCTXACK_0,
+    #[doc = "Acknowledge the slave address"]
+    UCTXACK_1,
+}
+impl UCTXACKW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXACKW::UCTXACK_0 => false,
+            UCTXACKW::UCTXACK_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXACKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXACKW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXACKW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Do not acknowledge the slave address"]
+    #[inline]
+    pub fn uctxack_0(self) -> &'a mut W {
+        self.variant(UCTXACKW::UCTXACK_0)
+    }
+    #[doc = "Acknowledge the slave address"]
+    #[inline]
+    pub fn uctxack_1(self) -> &'a mut W {
+        self.variant(UCTXACKW::UCTXACK_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSSEL`"]
+pub enum UCSSELW {
+    #[doc = "UCLKI"]
+    UCSSEL_0,
+    #[doc = "ACLK"]
+    UCSSEL_1,
+    #[doc = "SMCLK"]
+    UCSSEL_2,
+    #[doc = "SMCLK"]
+    UCSSEL_3,
+}
+impl UCSSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCSSELW::UCSSEL_0 => 0,
+            UCSSELW::UCSSEL_1 => 1,
+            UCSSELW::UCSSEL_2 => 2,
+            UCSSELW::UCSSEL_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSSELW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "UCLKI"]
+    #[inline]
+    pub fn ucssel_0(self) -> &'a mut W {
+        self.variant(UCSSELW::UCSSEL_0)
+    }
+    #[doc = "ACLK"]
+    #[inline]
+    pub fn ucssel_1(self) -> &'a mut W {
+        self.variant(UCSSELW::UCSSEL_1)
+    }
+    #[doc = "SMCLK"]
+    #[inline]
+    pub fn ucssel_2(self) -> &'a mut W {
+        self.variant(UCSSELW::UCSSEL_2)
+    }
+    #[doc = "SMCLK"]
+    #[inline]
+    pub fn ucssel_3(self) -> &'a mut W {
+        self.variant(UCSSELW::UCSSEL_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSYNC`"]
+pub enum UCSYNCW {
+    #[doc = "Asynchronous mode"]
+    UCSYNC_0,
+    #[doc = "Synchronous mode"]
+    UCSYNC_1,
+}
+impl UCSYNCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSYNCW::UCSYNC_0 => false,
+            UCSYNCW::UCSYNC_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSYNCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSYNCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSYNCW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Asynchronous mode"]
+    #[inline]
+    pub fn ucsync_0(self) -> &'a mut W {
+        self.variant(UCSYNCW::UCSYNC_0)
+    }
+    #[doc = "Synchronous mode"]
+    #[inline]
+    pub fn ucsync_1(self) -> &'a mut W {
+        self.variant(UCSYNCW::UCSYNC_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCMODE`"]
+pub enum UCMODEW {
+    #[doc = "3-pin SPI"]
+    UCMODE_0,
+    #[doc = "4-pin SPI (master or slave enabled if STE = 1)"]
+    UCMODE_1,
+    #[doc = "4-pin SPI (master or slave enabled if STE = 0)"]
+    UCMODE_2,
+    #[doc = "I2C mode"]
+    UCMODE_3,
+}
+impl UCMODEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCMODEW::UCMODE_0 => 0,
+            UCMODEW::UCMODE_1 => 1,
+            UCMODEW::UCMODE_2 => 2,
+            UCMODEW::UCMODE_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCMODEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCMODEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCMODEW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "3-pin SPI"]
+    #[inline]
+    pub fn ucmode_0(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_0)
+    }
+    #[doc = "4-pin SPI (master or slave enabled if STE = 1)"]
+    #[inline]
+    pub fn ucmode_1(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_1)
+    }
+    #[doc = "4-pin SPI (master or slave enabled if STE = 0)"]
+    #[inline]
+    pub fn ucmode_2(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_2)
+    }
+    #[doc = "I2C mode"]
+    #[inline]
+    pub fn ucmode_3(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCMST`"]
+pub enum UCMSTW {
+    #[doc = "Slave mode"]
+    UCMST_0,
+    #[doc = "Master mode"]
+    UCMST_1,
+}
+impl UCMSTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCMSTW::UCMST_0 => false,
+            UCMSTW::UCMST_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCMSTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCMSTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCMSTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Slave mode"]
+    #[inline]
+    pub fn ucmst_0(self) -> &'a mut W {
+        self.variant(UCMSTW::UCMST_0)
+    }
+    #[doc = "Master mode"]
+    #[inline]
+    pub fn ucmst_1(self) -> &'a mut W {
+        self.variant(UCMSTW::UCMST_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCMM`"]
+pub enum UCMMW {
+    #[doc = "Single master environment. There is no other master in the system. The address compare unit is disabled."]
+    UCMM_0,
+    #[doc = "Multi-master environment"]
+    UCMM_1,
+}
+impl UCMMW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCMMW::UCMM_0 => false,
+            UCMMW::UCMM_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCMMW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCMMW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCMMW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Single master environment. There is no other master in the system. The address compare unit is disabled."]
+    #[inline]
+    pub fn ucmm_0(self) -> &'a mut W {
+        self.variant(UCMMW::UCMM_0)
+    }
+    #[doc = "Multi-master environment"]
+    #[inline]
+    pub fn ucmm_1(self) -> &'a mut W {
+        self.variant(UCMMW::UCMM_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSLA10`"]
+pub enum UCSLA10W {
+    #[doc = "Address slave with 7-bit address"]
+    UCSLA10_0,
+    #[doc = "Address slave with 10-bit address"]
+    UCSLA10_1,
+}
+impl UCSLA10W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSLA10W::UCSLA10_0 => false,
+            UCSLA10W::UCSLA10_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSLA10W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSLA10W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSLA10W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Address slave with 7-bit address"]
+    #[inline]
+    pub fn ucsla10_0(self) -> &'a mut W {
+        self.variant(UCSLA10W::UCSLA10_0)
+    }
+    #[doc = "Address slave with 10-bit address"]
+    #[inline]
+    pub fn ucsla10_1(self) -> &'a mut W {
+        self.variant(UCSLA10W::UCSLA10_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCA10`"]
+pub enum UCA10W {
+    #[doc = "Own address is a 7-bit address"]
+    UCA10_0,
+    #[doc = "Own address is a 10-bit address"]
+    UCA10_1,
+}
+impl UCA10W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCA10W::UCA10_0 => false,
+            UCA10W::UCA10_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCA10W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCA10W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCA10W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Own address is a 7-bit address"]
+    #[inline]
+    pub fn uca10_0(self) -> &'a mut W {
+        self.variant(UCA10W::UCA10_0)
+    }
+    #[doc = "Own address is a 10-bit address"]
+    #[inline]
+    pub fn uca10_1(self) -> &'a mut W {
+        self.variant(UCA10W::UCA10_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Software reset enable"]
+    #[inline]
+    pub fn ucswrst(&self) -> UCSWRSTR {
+        UCSWRSTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Transmit START condition in master mode"]
+    #[inline]
+    pub fn uctxstt(&self) -> UCTXSTTR {
+        UCTXSTTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - Transmit STOP condition in master mode"]
+    #[inline]
+    pub fn uctxstp(&self) -> UCTXSTPR {
+        UCTXSTPR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Transmit a NACK"]
+    #[inline]
+    pub fn uctxnack(&self) -> UCTXNACKR {
+        UCTXNACKR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 4 - Transmitter/receiver"]
+    #[inline]
+    pub fn uctr(&self) -> UCTRR {
+        UCTRR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - Transmit ACK condition in slave mode"]
+    #[inline]
+    pub fn uctxack(&self) -> UCTXACKR {
+        UCTXACKR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 6:7 - eUSCI_B clock source select"]
+    #[inline]
+    pub fn ucssel(&self) -> UCSSELR {
+        UCSSELR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 8 - Synchronous mode enable"]
+    #[inline]
+    pub fn ucsync(&self) -> UCSYNCR {
+        UCSYNCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 9:10 - eUSCI_B mode"]
+    #[inline]
+    pub fn ucmode(&self) -> UCMODER {
+        UCMODER::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 11 - Master mode select"]
+    #[inline]
+    pub fn ucmst(&self) -> UCMSTR {
+        UCMSTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 13 - Multi-master environment select"]
+    #[inline]
+    pub fn ucmm(&self) -> UCMMR {
+        UCMMR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 14 - Slave addressing mode select"]
+    #[inline]
+    pub fn ucsla10(&self) -> UCSLA10R {
+        UCSLA10R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 15 - Own addressing mode select"]
+    #[inline]
+    pub fn uca10(&self) -> UCA10R {
+        UCA10R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 449 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Software reset enable"]
+    #[inline]
+    pub fn ucswrst(&mut self) -> _UCSWRSTW {
+        _UCSWRSTW { w: self }
+    }
+    #[doc = "Bit 1 - Transmit START condition in master mode"]
+    #[inline]
+    pub fn uctxstt(&mut self) -> _UCTXSTTW {
+        _UCTXSTTW { w: self }
+    }
+    #[doc = "Bit 2 - Transmit STOP condition in master mode"]
+    #[inline]
+    pub fn uctxstp(&mut self) -> _UCTXSTPW {
+        _UCTXSTPW { w: self }
+    }
+    #[doc = "Bit 3 - Transmit a NACK"]
+    #[inline]
+    pub fn uctxnack(&mut self) -> _UCTXNACKW {
+        _UCTXNACKW { w: self }
+    }
+    #[doc = "Bit 4 - Transmitter/receiver"]
+    #[inline]
+    pub fn uctr(&mut self) -> _UCTRW {
+        _UCTRW { w: self }
+    }
+    #[doc = "Bit 5 - Transmit ACK condition in slave mode"]
+    #[inline]
+    pub fn uctxack(&mut self) -> _UCTXACKW {
+        _UCTXACKW { w: self }
+    }
+    #[doc = "Bits 6:7 - eUSCI_B clock source select"]
+    #[inline]
+    pub fn ucssel(&mut self) -> _UCSSELW {
+        _UCSSELW { w: self }
+    }
+    #[doc = "Bit 8 - Synchronous mode enable"]
+    #[inline]
+    pub fn ucsync(&mut self) -> _UCSYNCW {
+        _UCSYNCW { w: self }
+    }
+    #[doc = "Bits 9:10 - eUSCI_B mode"]
+    #[inline]
+    pub fn ucmode(&mut self) -> _UCMODEW {
+        _UCMODEW { w: self }
+    }
+    #[doc = "Bit 11 - Master mode select"]
+    #[inline]
+    pub fn ucmst(&mut self) -> _UCMSTW {
+        _UCMSTW { w: self }
+    }
+    #[doc = "Bit 13 - Multi-master environment select"]
+    #[inline]
+    pub fn ucmm(&mut self) -> _UCMMW {
+        _UCMMW { w: self }
+    }
+    #[doc = "Bit 14 - Slave addressing mode select"]
+    #[inline]
+    pub fn ucsla10(&mut self) -> _UCSLA10W {
+        _UCSLA10W { w: self }
+    }
+    #[doc = "Bit 15 - Own addressing mode select"]
+    #[inline]
+    pub fn uca10(&mut self) -> _UCA10W {
+        _UCA10W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b0/ucbx_ctlw1.rs b/example-source/msp432p401r/src/eusci_b0/ucbx_ctlw1.rs
new file mode 100644
index 0000000..64e2d04
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b0/ucbx_ctlw1.rs
@@ -0,0 +1,813 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXCTLW1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCGLIT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCGLITR {
+    #[doc = "50 ns"]
+    UCGLIT_0,
+    #[doc = "25 ns"]
+    UCGLIT_1,
+    #[doc = "12.5 ns"]
+    UCGLIT_2,
+    #[doc = "6.25 ns"]
+    UCGLIT_3,
+}
+impl UCGLITR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCGLITR::UCGLIT_0 => 0,
+            UCGLITR::UCGLIT_1 => 1,
+            UCGLITR::UCGLIT_2 => 2,
+            UCGLITR::UCGLIT_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCGLITR {
+        match value {
+            0 => UCGLITR::UCGLIT_0,
+            1 => UCGLITR::UCGLIT_1,
+            2 => UCGLITR::UCGLIT_2,
+            3 => UCGLITR::UCGLIT_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_0`"]
+    #[inline]
+    pub fn is_ucglit_0(&self) -> bool {
+        *self == UCGLITR::UCGLIT_0
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_1`"]
+    #[inline]
+    pub fn is_ucglit_1(&self) -> bool {
+        *self == UCGLITR::UCGLIT_1
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_2`"]
+    #[inline]
+    pub fn is_ucglit_2(&self) -> bool {
+        *self == UCGLITR::UCGLIT_2
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_3`"]
+    #[inline]
+    pub fn is_ucglit_3(&self) -> bool {
+        *self == UCGLITR::UCGLIT_3
+    }
+}
+#[doc = "Possible values of the field `UCASTP`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCASTPR {
+    #[doc = "No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care."]
+    UCASTP_0,
+    #[doc = "UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT"]
+    UCASTP_1,
+    #[doc = "A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold"]
+    UCASTP_2,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl UCASTPR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCASTPR::UCASTP_0 => 0,
+            UCASTPR::UCASTP_1 => 1,
+            UCASTPR::UCASTP_2 => 2,
+            UCASTPR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCASTPR {
+        match value {
+            0 => UCASTPR::UCASTP_0,
+            1 => UCASTPR::UCASTP_1,
+            2 => UCASTPR::UCASTP_2,
+            i => UCASTPR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCASTP_0`"]
+    #[inline]
+    pub fn is_ucastp_0(&self) -> bool {
+        *self == UCASTPR::UCASTP_0
+    }
+    #[doc = "Checks if the value of the field is `UCASTP_1`"]
+    #[inline]
+    pub fn is_ucastp_1(&self) -> bool {
+        *self == UCASTPR::UCASTP_1
+    }
+    #[doc = "Checks if the value of the field is `UCASTP_2`"]
+    #[inline]
+    pub fn is_ucastp_2(&self) -> bool {
+        *self == UCASTPR::UCASTP_2
+    }
+}
+#[doc = "Possible values of the field `UCSWACK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSWACKR {
+    #[doc = "The address acknowledge of the slave is controlled by the eUSCI_B module"]
+    UCSWACK_0,
+    #[doc = "The user needs to trigger the sending of the address ACK by issuing UCTXACK"]
+    UCSWACK_1,
+}
+impl UCSWACKR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSWACKR::UCSWACK_0 => false,
+            UCSWACKR::UCSWACK_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSWACKR {
+        match value {
+            false => UCSWACKR::UCSWACK_0,
+            true => UCSWACKR::UCSWACK_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSWACK_0`"]
+    #[inline]
+    pub fn is_ucswack_0(&self) -> bool {
+        *self == UCSWACKR::UCSWACK_0
+    }
+    #[doc = "Checks if the value of the field is `UCSWACK_1`"]
+    #[inline]
+    pub fn is_ucswack_1(&self) -> bool {
+        *self == UCSWACKR::UCSWACK_1
+    }
+}
+#[doc = "Possible values of the field `UCSTPNACK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTPNACKR {
+    #[doc = "Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard)"]
+    UCSTPNACK_0,
+    #[doc = "All bytes are acknowledged by the eUSCI_B when configured as master receiver"]
+    UCSTPNACK_1,
+}
+impl UCSTPNACKR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTPNACKR::UCSTPNACK_0 => false,
+            UCSTPNACKR::UCSTPNACK_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTPNACKR {
+        match value {
+            false => UCSTPNACKR::UCSTPNACK_0,
+            true => UCSTPNACKR::UCSTPNACK_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTPNACK_0`"]
+    #[inline]
+    pub fn is_ucstpnack_0(&self) -> bool {
+        *self == UCSTPNACKR::UCSTPNACK_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTPNACK_1`"]
+    #[inline]
+    pub fn is_ucstpnack_1(&self) -> bool {
+        *self == UCSTPNACKR::UCSTPNACK_1
+    }
+}
+#[doc = "Possible values of the field `UCCLTO`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCCLTOR {
+    #[doc = "Disable clock low timeout counter"]
+    UCCLTO_0,
+    #[doc = "135 000 SYSCLK cycles (approximately 28 ms)"]
+    UCCLTO_1,
+    #[doc = "150 000 SYSCLK cycles (approximately 31 ms)"]
+    UCCLTO_2,
+    #[doc = "165 000 SYSCLK cycles (approximately 34 ms)"]
+    UCCLTO_3,
+}
+impl UCCLTOR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCCLTOR::UCCLTO_0 => 0,
+            UCCLTOR::UCCLTO_1 => 1,
+            UCCLTOR::UCCLTO_2 => 2,
+            UCCLTOR::UCCLTO_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCCLTOR {
+        match value {
+            0 => UCCLTOR::UCCLTO_0,
+            1 => UCCLTOR::UCCLTO_1,
+            2 => UCCLTOR::UCCLTO_2,
+            3 => UCCLTOR::UCCLTO_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCCLTO_0`"]
+    #[inline]
+    pub fn is_ucclto_0(&self) -> bool {
+        *self == UCCLTOR::UCCLTO_0
+    }
+    #[doc = "Checks if the value of the field is `UCCLTO_1`"]
+    #[inline]
+    pub fn is_ucclto_1(&self) -> bool {
+        *self == UCCLTOR::UCCLTO_1
+    }
+    #[doc = "Checks if the value of the field is `UCCLTO_2`"]
+    #[inline]
+    pub fn is_ucclto_2(&self) -> bool {
+        *self == UCCLTOR::UCCLTO_2
+    }
+    #[doc = "Checks if the value of the field is `UCCLTO_3`"]
+    #[inline]
+    pub fn is_ucclto_3(&self) -> bool {
+        *self == UCCLTOR::UCCLTO_3
+    }
+}
+#[doc = "Possible values of the field `UCETXINT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCETXINTR {
+    #[doc = "UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit"]
+    UCETXINT_0,
+    #[doc = "UCTXIFG0 is set for each START condition"]
+    UCETXINT_1,
+}
+impl UCETXINTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCETXINTR::UCETXINT_0 => false,
+            UCETXINTR::UCETXINT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCETXINTR {
+        match value {
+            false => UCETXINTR::UCETXINT_0,
+            true => UCETXINTR::UCETXINT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCETXINT_0`"]
+    #[inline]
+    pub fn is_ucetxint_0(&self) -> bool {
+        *self == UCETXINTR::UCETXINT_0
+    }
+    #[doc = "Checks if the value of the field is `UCETXINT_1`"]
+    #[inline]
+    pub fn is_ucetxint_1(&self) -> bool {
+        *self == UCETXINTR::UCETXINT_1
+    }
+}
+#[doc = "Values that can be written to the field `UCGLIT`"]
+pub enum UCGLITW {
+    #[doc = "50 ns"]
+    UCGLIT_0,
+    #[doc = "25 ns"]
+    UCGLIT_1,
+    #[doc = "12.5 ns"]
+    UCGLIT_2,
+    #[doc = "6.25 ns"]
+    UCGLIT_3,
+}
+impl UCGLITW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCGLITW::UCGLIT_0 => 0,
+            UCGLITW::UCGLIT_1 => 1,
+            UCGLITW::UCGLIT_2 => 2,
+            UCGLITW::UCGLIT_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCGLITW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCGLITW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCGLITW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "50 ns"]
+    #[inline]
+    pub fn ucglit_0(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_0)
+    }
+    #[doc = "25 ns"]
+    #[inline]
+    pub fn ucglit_1(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_1)
+    }
+    #[doc = "12.5 ns"]
+    #[inline]
+    pub fn ucglit_2(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_2)
+    }
+    #[doc = "6.25 ns"]
+    #[inline]
+    pub fn ucglit_3(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCASTP`"]
+pub enum UCASTPW {
+    #[doc = "No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care."]
+    UCASTP_0,
+    #[doc = "UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT"]
+    UCASTP_1,
+    #[doc = "A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold"]
+    UCASTP_2,
+}
+impl UCASTPW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCASTPW::UCASTP_0 => 0,
+            UCASTPW::UCASTP_1 => 1,
+            UCASTPW::UCASTP_2 => 2,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCASTPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCASTPW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCASTPW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care."]
+    #[inline]
+    pub fn ucastp_0(self) -> &'a mut W {
+        self.variant(UCASTPW::UCASTP_0)
+    }
+    #[doc = "UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT"]
+    #[inline]
+    pub fn ucastp_1(self) -> &'a mut W {
+        self.variant(UCASTPW::UCASTP_1)
+    }
+    #[doc = "A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold"]
+    #[inline]
+    pub fn ucastp_2(self) -> &'a mut W {
+        self.variant(UCASTPW::UCASTP_2)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSWACK`"]
+pub enum UCSWACKW {
+    #[doc = "The address acknowledge of the slave is controlled by the eUSCI_B module"]
+    UCSWACK_0,
+    #[doc = "The user needs to trigger the sending of the address ACK by issuing UCTXACK"]
+    UCSWACK_1,
+}
+impl UCSWACKW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSWACKW::UCSWACK_0 => false,
+            UCSWACKW::UCSWACK_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSWACKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSWACKW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSWACKW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The address acknowledge of the slave is controlled by the eUSCI_B module"]
+    #[inline]
+    pub fn ucswack_0(self) -> &'a mut W {
+        self.variant(UCSWACKW::UCSWACK_0)
+    }
+    #[doc = "The user needs to trigger the sending of the address ACK by issuing UCTXACK"]
+    #[inline]
+    pub fn ucswack_1(self) -> &'a mut W {
+        self.variant(UCSWACKW::UCSWACK_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTPNACK`"]
+pub enum UCSTPNACKW {
+    #[doc = "Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard)"]
+    UCSTPNACK_0,
+    #[doc = "All bytes are acknowledged by the eUSCI_B when configured as master receiver"]
+    UCSTPNACK_1,
+}
+impl UCSTPNACKW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTPNACKW::UCSTPNACK_0 => false,
+            UCSTPNACKW::UCSTPNACK_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTPNACKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTPNACKW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTPNACKW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard)"]
+    #[inline]
+    pub fn ucstpnack_0(self) -> &'a mut W {
+        self.variant(UCSTPNACKW::UCSTPNACK_0)
+    }
+    #[doc = "All bytes are acknowledged by the eUSCI_B when configured as master receiver"]
+    #[inline]
+    pub fn ucstpnack_1(self) -> &'a mut W {
+        self.variant(UCSTPNACKW::UCSTPNACK_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCCLTO`"]
+pub enum UCCLTOW {
+    #[doc = "Disable clock low timeout counter"]
+    UCCLTO_0,
+    #[doc = "135 000 SYSCLK cycles (approximately 28 ms)"]
+    UCCLTO_1,
+    #[doc = "150 000 SYSCLK cycles (approximately 31 ms)"]
+    UCCLTO_2,
+    #[doc = "165 000 SYSCLK cycles (approximately 34 ms)"]
+    UCCLTO_3,
+}
+impl UCCLTOW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCCLTOW::UCCLTO_0 => 0,
+            UCCLTOW::UCCLTO_1 => 1,
+            UCCLTOW::UCCLTO_2 => 2,
+            UCCLTOW::UCCLTO_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCCLTOW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCCLTOW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCCLTOW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Disable clock low timeout counter"]
+    #[inline]
+    pub fn ucclto_0(self) -> &'a mut W {
+        self.variant(UCCLTOW::UCCLTO_0)
+    }
+    #[doc = "135 000 SYSCLK cycles (approximately 28 ms)"]
+    #[inline]
+    pub fn ucclto_1(self) -> &'a mut W {
+        self.variant(UCCLTOW::UCCLTO_1)
+    }
+    #[doc = "150 000 SYSCLK cycles (approximately 31 ms)"]
+    #[inline]
+    pub fn ucclto_2(self) -> &'a mut W {
+        self.variant(UCCLTOW::UCCLTO_2)
+    }
+    #[doc = "165 000 SYSCLK cycles (approximately 34 ms)"]
+    #[inline]
+    pub fn ucclto_3(self) -> &'a mut W {
+        self.variant(UCCLTOW::UCCLTO_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCETXINT`"]
+pub enum UCETXINTW {
+    #[doc = "UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit"]
+    UCETXINT_0,
+    #[doc = "UCTXIFG0 is set for each START condition"]
+    UCETXINT_1,
+}
+impl UCETXINTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCETXINTW::UCETXINT_0 => false,
+            UCETXINTW::UCETXINT_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCETXINTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCETXINTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCETXINTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit"]
+    #[inline]
+    pub fn ucetxint_0(self) -> &'a mut W {
+        self.variant(UCETXINTW::UCETXINT_0)
+    }
+    #[doc = "UCTXIFG0 is set for each START condition"]
+    #[inline]
+    pub fn ucetxint_1(self) -> &'a mut W {
+        self.variant(UCETXINTW::UCETXINT_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:1 - Deglitch time"]
+    #[inline]
+    pub fn ucglit(&self) -> UCGLITR {
+        UCGLITR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bits 2:3 - Automatic STOP condition generation"]
+    #[inline]
+    pub fn ucastp(&self) -> UCASTPR {
+        UCASTPR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 4 - SW or HW ACK control"]
+    #[inline]
+    pub fn ucswack(&self) -> UCSWACKR {
+        UCSWACKR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - ACK all master bytes"]
+    #[inline]
+    pub fn ucstpnack(&self) -> UCSTPNACKR {
+        UCSTPNACKR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 6:7 - Clock low timeout select"]
+    #[inline]
+    pub fn ucclto(&self) -> UCCLTOR {
+        UCCLTOR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 8 - Early UCTXIFG0"]
+    #[inline]
+    pub fn ucetxint(&self) -> UCETXINTR {
+        UCETXINTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 3 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:1 - Deglitch time"]
+    #[inline]
+    pub fn ucglit(&mut self) -> _UCGLITW {
+        _UCGLITW { w: self }
+    }
+    #[doc = "Bits 2:3 - Automatic STOP condition generation"]
+    #[inline]
+    pub fn ucastp(&mut self) -> _UCASTPW {
+        _UCASTPW { w: self }
+    }
+    #[doc = "Bit 4 - SW or HW ACK control"]
+    #[inline]
+    pub fn ucswack(&mut self) -> _UCSWACKW {
+        _UCSWACKW { w: self }
+    }
+    #[doc = "Bit 5 - ACK all master bytes"]
+    #[inline]
+    pub fn ucstpnack(&mut self) -> _UCSTPNACKW {
+        _UCSTPNACKW { w: self }
+    }
+    #[doc = "Bits 6:7 - Clock low timeout select"]
+    #[inline]
+    pub fn ucclto(&mut self) -> _UCCLTOW {
+        _UCCLTOW { w: self }
+    }
+    #[doc = "Bit 8 - Early UCTXIFG0"]
+    #[inline]
+    pub fn ucetxint(&mut self) -> _UCETXINTW {
+        _UCETXINTW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b0/ucbx_i2coa0.rs b/example-source/msp432p401r/src/eusci_b0/ucbx_i2coa0.rs
new file mode 100644
index 0000000..93003b5
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b0/ucbx_i2coa0.rs
@@ -0,0 +1,343 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXI2COA0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct I2COA0R {
+    bits: u16,
+}
+impl I2COA0R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `UCOAEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCOAENR {
+    #[doc = "The slave address defined in I2COA0 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA0 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCOAENR::UCOAEN_0 => false,
+            UCOAENR::UCOAEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCOAENR {
+        match value {
+            false => UCOAENR::UCOAEN_0,
+            true => UCOAENR::UCOAEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_0`"]
+    #[inline]
+    pub fn is_ucoaen_0(&self) -> bool {
+        *self == UCOAENR::UCOAEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_1`"]
+    #[inline]
+    pub fn is_ucoaen_1(&self) -> bool {
+        *self == UCOAENR::UCOAEN_1
+    }
+}
+#[doc = "Possible values of the field `UCGCEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCGCENR {
+    #[doc = "Do not respond to a general call"]
+    UCGCEN_0,
+    #[doc = "Respond to a general call"]
+    UCGCEN_1,
+}
+impl UCGCENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCGCENR::UCGCEN_0 => false,
+            UCGCENR::UCGCEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCGCENR {
+        match value {
+            false => UCGCENR::UCGCEN_0,
+            true => UCGCENR::UCGCEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCGCEN_0`"]
+    #[inline]
+    pub fn is_ucgcen_0(&self) -> bool {
+        *self == UCGCENR::UCGCEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCGCEN_1`"]
+    #[inline]
+    pub fn is_ucgcen_1(&self) -> bool {
+        *self == UCGCENR::UCGCEN_1
+    }
+}
+#[doc = r" Proxy"]
+pub struct _I2COA0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _I2COA0W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCOAEN`"]
+pub enum UCOAENW {
+    #[doc = "The slave address defined in I2COA0 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA0 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCOAENW::UCOAEN_0 => false,
+            UCOAENW::UCOAEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCOAENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCOAENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCOAENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The slave address defined in I2COA0 is disabled"]
+    #[inline]
+    pub fn ucoaen_0(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_0)
+    }
+    #[doc = "The slave address defined in I2COA0 is enabled"]
+    #[inline]
+    pub fn ucoaen_1(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCGCEN`"]
+pub enum UCGCENW {
+    #[doc = "Do not respond to a general call"]
+    UCGCEN_0,
+    #[doc = "Respond to a general call"]
+    UCGCEN_1,
+}
+impl UCGCENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCGCENW::UCGCEN_0 => false,
+            UCGCENW::UCGCEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCGCENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCGCENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCGCENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Do not respond to a general call"]
+    #[inline]
+    pub fn ucgcen_0(self) -> &'a mut W {
+        self.variant(UCGCENW::UCGCEN_0)
+    }
+    #[doc = "Respond to a general call"]
+    #[inline]
+    pub fn ucgcen_1(self) -> &'a mut W {
+        self.variant(UCGCENW::UCGCEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa0(&self) -> I2COA0R {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        I2COA0R { bits }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&self) -> UCOAENR {
+        UCOAENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 15 - General call response enable"]
+    #[inline]
+    pub fn ucgcen(&self) -> UCGCENR {
+        UCGCENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa0(&mut self) -> _I2COA0W {
+        _I2COA0W { w: self }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&mut self) -> _UCOAENW {
+        _UCOAENW { w: self }
+    }
+    #[doc = "Bit 15 - General call response enable"]
+    #[inline]
+    pub fn ucgcen(&mut self) -> _UCGCENW {
+        _UCGCENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b0/ucbx_i2coa1.rs b/example-source/msp432p401r/src/eusci_b0/ucbx_i2coa1.rs
new file mode 100644
index 0000000..660cba5
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b0/ucbx_i2coa1.rs
@@ -0,0 +1,224 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXI2COA1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct I2COA1R {
+    bits: u16,
+}
+impl I2COA1R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `UCOAEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCOAENR {
+    #[doc = "The slave address defined in I2COA1 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA1 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCOAENR::UCOAEN_0 => false,
+            UCOAENR::UCOAEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCOAENR {
+        match value {
+            false => UCOAENR::UCOAEN_0,
+            true => UCOAENR::UCOAEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_0`"]
+    #[inline]
+    pub fn is_ucoaen_0(&self) -> bool {
+        *self == UCOAENR::UCOAEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_1`"]
+    #[inline]
+    pub fn is_ucoaen_1(&self) -> bool {
+        *self == UCOAENR::UCOAEN_1
+    }
+}
+#[doc = r" Proxy"]
+pub struct _I2COA1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _I2COA1W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCOAEN`"]
+pub enum UCOAENW {
+    #[doc = "The slave address defined in I2COA1 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA1 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCOAENW::UCOAEN_0 => false,
+            UCOAENW::UCOAEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCOAENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCOAENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCOAENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The slave address defined in I2COA1 is disabled"]
+    #[inline]
+    pub fn ucoaen_0(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_0)
+    }
+    #[doc = "The slave address defined in I2COA1 is enabled"]
+    #[inline]
+    pub fn ucoaen_1(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa1(&self) -> I2COA1R {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        I2COA1R { bits }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&self) -> UCOAENR {
+        UCOAENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa1(&mut self) -> _I2COA1W {
+        _I2COA1W { w: self }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&mut self) -> _UCOAENW {
+        _UCOAENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b0/ucbx_i2coa2.rs b/example-source/msp432p401r/src/eusci_b0/ucbx_i2coa2.rs
new file mode 100644
index 0000000..4f3ceb5
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b0/ucbx_i2coa2.rs
@@ -0,0 +1,224 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXI2COA2 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct I2COA2R {
+    bits: u16,
+}
+impl I2COA2R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `UCOAEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCOAENR {
+    #[doc = "The slave address defined in I2COA2 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA2 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCOAENR::UCOAEN_0 => false,
+            UCOAENR::UCOAEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCOAENR {
+        match value {
+            false => UCOAENR::UCOAEN_0,
+            true => UCOAENR::UCOAEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_0`"]
+    #[inline]
+    pub fn is_ucoaen_0(&self) -> bool {
+        *self == UCOAENR::UCOAEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_1`"]
+    #[inline]
+    pub fn is_ucoaen_1(&self) -> bool {
+        *self == UCOAENR::UCOAEN_1
+    }
+}
+#[doc = r" Proxy"]
+pub struct _I2COA2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _I2COA2W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCOAEN`"]
+pub enum UCOAENW {
+    #[doc = "The slave address defined in I2COA2 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA2 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCOAENW::UCOAEN_0 => false,
+            UCOAENW::UCOAEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCOAENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCOAENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCOAENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The slave address defined in I2COA2 is disabled"]
+    #[inline]
+    pub fn ucoaen_0(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_0)
+    }
+    #[doc = "The slave address defined in I2COA2 is enabled"]
+    #[inline]
+    pub fn ucoaen_1(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa2(&self) -> I2COA2R {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        I2COA2R { bits }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&self) -> UCOAENR {
+        UCOAENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa2(&mut self) -> _I2COA2W {
+        _I2COA2W { w: self }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&mut self) -> _UCOAENW {
+        _UCOAENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b0/ucbx_i2coa3.rs b/example-source/msp432p401r/src/eusci_b0/ucbx_i2coa3.rs
new file mode 100644
index 0000000..8cab4f2
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b0/ucbx_i2coa3.rs
@@ -0,0 +1,224 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXI2COA3 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct I2COA3R {
+    bits: u16,
+}
+impl I2COA3R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `UCOAEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCOAENR {
+    #[doc = "The slave address defined in I2COA3 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA3 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCOAENR::UCOAEN_0 => false,
+            UCOAENR::UCOAEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCOAENR {
+        match value {
+            false => UCOAENR::UCOAEN_0,
+            true => UCOAENR::UCOAEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_0`"]
+    #[inline]
+    pub fn is_ucoaen_0(&self) -> bool {
+        *self == UCOAENR::UCOAEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_1`"]
+    #[inline]
+    pub fn is_ucoaen_1(&self) -> bool {
+        *self == UCOAENR::UCOAEN_1
+    }
+}
+#[doc = r" Proxy"]
+pub struct _I2COA3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _I2COA3W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCOAEN`"]
+pub enum UCOAENW {
+    #[doc = "The slave address defined in I2COA3 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA3 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCOAENW::UCOAEN_0 => false,
+            UCOAENW::UCOAEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCOAENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCOAENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCOAENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The slave address defined in I2COA3 is disabled"]
+    #[inline]
+    pub fn ucoaen_0(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_0)
+    }
+    #[doc = "The slave address defined in I2COA3 is enabled"]
+    #[inline]
+    pub fn ucoaen_1(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa3(&self) -> I2COA3R {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        I2COA3R { bits }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&self) -> UCOAENR {
+        UCOAENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa3(&mut self) -> _I2COA3W {
+        _I2COA3W { w: self }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&mut self) -> _UCOAENW {
+        _UCOAENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b0/ucbx_i2csa.rs b/example-source/msp432p401r/src/eusci_b0/ucbx_i2csa.rs
new file mode 100644
index 0000000..33de734
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b0/ucbx_i2csa.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXI2CSA {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct I2CSAR {
+    bits: u16,
+}
+impl I2CSAR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _I2CSAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _I2CSAW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - I2C slave address"]
+    #[inline]
+    pub fn i2csa(&self) -> I2CSAR {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        I2CSAR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:9 - I2C slave address"]
+    #[inline]
+    pub fn i2csa(&mut self) -> _I2CSAW {
+        _I2CSAW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b0/ucbx_ie.rs b/example-source/msp432p401r/src/eusci_b0/ucbx_ie.rs
new file mode 100644
index 0000000..7c9f18c
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b0/ucbx_ie.rs
@@ -0,0 +1,1849 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXIE {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCRXIE0`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIE0R {
+    #[doc = "Interrupt disabled"]
+    UCRXIE0_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE0_1,
+}
+impl UCRXIE0R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIE0R::UCRXIE0_0 => false,
+            UCRXIE0R::UCRXIE0_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIE0R {
+        match value {
+            false => UCRXIE0R::UCRXIE0_0,
+            true => UCRXIE0R::UCRXIE0_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE0_0`"]
+    #[inline]
+    pub fn is_ucrxie0_0(&self) -> bool {
+        *self == UCRXIE0R::UCRXIE0_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE0_1`"]
+    #[inline]
+    pub fn is_ucrxie0_1(&self) -> bool {
+        *self == UCRXIE0R::UCRXIE0_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIE0`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIE0R {
+    #[doc = "Interrupt disabled"]
+    UCTXIE0_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE0_1,
+}
+impl UCTXIE0R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIE0R::UCTXIE0_0 => false,
+            UCTXIE0R::UCTXIE0_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIE0R {
+        match value {
+            false => UCTXIE0R::UCTXIE0_0,
+            true => UCTXIE0R::UCTXIE0_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE0_0`"]
+    #[inline]
+    pub fn is_uctxie0_0(&self) -> bool {
+        *self == UCTXIE0R::UCTXIE0_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE0_1`"]
+    #[inline]
+    pub fn is_uctxie0_1(&self) -> bool {
+        *self == UCTXIE0R::UCTXIE0_1
+    }
+}
+#[doc = "Possible values of the field `UCSTTIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTTIER {
+    #[doc = "Interrupt disabled"]
+    UCSTTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCSTTIE_1,
+}
+impl UCSTTIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTTIER::UCSTTIE_0 => false,
+            UCSTTIER::UCSTTIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTTIER {
+        match value {
+            false => UCSTTIER::UCSTTIE_0,
+            true => UCSTTIER::UCSTTIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIE_0`"]
+    #[inline]
+    pub fn is_ucsttie_0(&self) -> bool {
+        *self == UCSTTIER::UCSTTIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIE_1`"]
+    #[inline]
+    pub fn is_ucsttie_1(&self) -> bool {
+        *self == UCSTTIER::UCSTTIE_1
+    }
+}
+#[doc = "Possible values of the field `UCSTPIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTPIER {
+    #[doc = "Interrupt disabled"]
+    UCSTPIE_0,
+    #[doc = "Interrupt enabled"]
+    UCSTPIE_1,
+}
+impl UCSTPIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTPIER::UCSTPIE_0 => false,
+            UCSTPIER::UCSTPIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTPIER {
+        match value {
+            false => UCSTPIER::UCSTPIE_0,
+            true => UCSTPIER::UCSTPIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTPIE_0`"]
+    #[inline]
+    pub fn is_ucstpie_0(&self) -> bool {
+        *self == UCSTPIER::UCSTPIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTPIE_1`"]
+    #[inline]
+    pub fn is_ucstpie_1(&self) -> bool {
+        *self == UCSTPIER::UCSTPIE_1
+    }
+}
+#[doc = "Possible values of the field `UCALIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCALIER {
+    #[doc = "Interrupt disabled"]
+    UCALIE_0,
+    #[doc = "Interrupt enabled"]
+    UCALIE_1,
+}
+impl UCALIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCALIER::UCALIE_0 => false,
+            UCALIER::UCALIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCALIER {
+        match value {
+            false => UCALIER::UCALIE_0,
+            true => UCALIER::UCALIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCALIE_0`"]
+    #[inline]
+    pub fn is_ucalie_0(&self) -> bool {
+        *self == UCALIER::UCALIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCALIE_1`"]
+    #[inline]
+    pub fn is_ucalie_1(&self) -> bool {
+        *self == UCALIER::UCALIE_1
+    }
+}
+#[doc = "Possible values of the field `UCNACKIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCNACKIER {
+    #[doc = "Interrupt disabled"]
+    UCNACKIE_0,
+    #[doc = "Interrupt enabled"]
+    UCNACKIE_1,
+}
+impl UCNACKIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCNACKIER::UCNACKIE_0 => false,
+            UCNACKIER::UCNACKIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCNACKIER {
+        match value {
+            false => UCNACKIER::UCNACKIE_0,
+            true => UCNACKIER::UCNACKIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCNACKIE_0`"]
+    #[inline]
+    pub fn is_ucnackie_0(&self) -> bool {
+        *self == UCNACKIER::UCNACKIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCNACKIE_1`"]
+    #[inline]
+    pub fn is_ucnackie_1(&self) -> bool {
+        *self == UCNACKIER::UCNACKIE_1
+    }
+}
+#[doc = "Possible values of the field `UCBCNTIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBCNTIER {
+    #[doc = "Interrupt disabled"]
+    UCBCNTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCBCNTIE_1,
+}
+impl UCBCNTIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBCNTIER::UCBCNTIE_0 => false,
+            UCBCNTIER::UCBCNTIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBCNTIER {
+        match value {
+            false => UCBCNTIER::UCBCNTIE_0,
+            true => UCBCNTIER::UCBCNTIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBCNTIE_0`"]
+    #[inline]
+    pub fn is_ucbcntie_0(&self) -> bool {
+        *self == UCBCNTIER::UCBCNTIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCBCNTIE_1`"]
+    #[inline]
+    pub fn is_ucbcntie_1(&self) -> bool {
+        *self == UCBCNTIER::UCBCNTIE_1
+    }
+}
+#[doc = "Possible values of the field `UCCLTOIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCCLTOIER {
+    #[doc = "Interrupt disabled"]
+    UCCLTOIE_0,
+    #[doc = "Interrupt enabled"]
+    UCCLTOIE_1,
+}
+impl UCCLTOIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCCLTOIER::UCCLTOIE_0 => false,
+            UCCLTOIER::UCCLTOIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCCLTOIER {
+        match value {
+            false => UCCLTOIER::UCCLTOIE_0,
+            true => UCCLTOIER::UCCLTOIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCCLTOIE_0`"]
+    #[inline]
+    pub fn is_uccltoie_0(&self) -> bool {
+        *self == UCCLTOIER::UCCLTOIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCCLTOIE_1`"]
+    #[inline]
+    pub fn is_uccltoie_1(&self) -> bool {
+        *self == UCCLTOIER::UCCLTOIE_1
+    }
+}
+#[doc = "Possible values of the field `UCRXIE1`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIE1R {
+    #[doc = "Interrupt disabled"]
+    UCRXIE1_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE1_1,
+}
+impl UCRXIE1R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIE1R::UCRXIE1_0 => false,
+            UCRXIE1R::UCRXIE1_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIE1R {
+        match value {
+            false => UCRXIE1R::UCRXIE1_0,
+            true => UCRXIE1R::UCRXIE1_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE1_0`"]
+    #[inline]
+    pub fn is_ucrxie1_0(&self) -> bool {
+        *self == UCRXIE1R::UCRXIE1_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE1_1`"]
+    #[inline]
+    pub fn is_ucrxie1_1(&self) -> bool {
+        *self == UCRXIE1R::UCRXIE1_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIE1`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIE1R {
+    #[doc = "Interrupt disabled"]
+    UCTXIE1_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE1_1,
+}
+impl UCTXIE1R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIE1R::UCTXIE1_0 => false,
+            UCTXIE1R::UCTXIE1_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIE1R {
+        match value {
+            false => UCTXIE1R::UCTXIE1_0,
+            true => UCTXIE1R::UCTXIE1_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE1_0`"]
+    #[inline]
+    pub fn is_uctxie1_0(&self) -> bool {
+        *self == UCTXIE1R::UCTXIE1_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE1_1`"]
+    #[inline]
+    pub fn is_uctxie1_1(&self) -> bool {
+        *self == UCTXIE1R::UCTXIE1_1
+    }
+}
+#[doc = "Possible values of the field `UCRXIE2`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIE2R {
+    #[doc = "Interrupt disabled"]
+    UCRXIE2_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE2_1,
+}
+impl UCRXIE2R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIE2R::UCRXIE2_0 => false,
+            UCRXIE2R::UCRXIE2_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIE2R {
+        match value {
+            false => UCRXIE2R::UCRXIE2_0,
+            true => UCRXIE2R::UCRXIE2_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE2_0`"]
+    #[inline]
+    pub fn is_ucrxie2_0(&self) -> bool {
+        *self == UCRXIE2R::UCRXIE2_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE2_1`"]
+    #[inline]
+    pub fn is_ucrxie2_1(&self) -> bool {
+        *self == UCRXIE2R::UCRXIE2_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIE2`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIE2R {
+    #[doc = "Interrupt disabled"]
+    UCTXIE2_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE2_1,
+}
+impl UCTXIE2R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIE2R::UCTXIE2_0 => false,
+            UCTXIE2R::UCTXIE2_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIE2R {
+        match value {
+            false => UCTXIE2R::UCTXIE2_0,
+            true => UCTXIE2R::UCTXIE2_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE2_0`"]
+    #[inline]
+    pub fn is_uctxie2_0(&self) -> bool {
+        *self == UCTXIE2R::UCTXIE2_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE2_1`"]
+    #[inline]
+    pub fn is_uctxie2_1(&self) -> bool {
+        *self == UCTXIE2R::UCTXIE2_1
+    }
+}
+#[doc = "Possible values of the field `UCRXIE3`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIE3R {
+    #[doc = "Interrupt disabled"]
+    UCRXIE3_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE3_1,
+}
+impl UCRXIE3R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIE3R::UCRXIE3_0 => false,
+            UCRXIE3R::UCRXIE3_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIE3R {
+        match value {
+            false => UCRXIE3R::UCRXIE3_0,
+            true => UCRXIE3R::UCRXIE3_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE3_0`"]
+    #[inline]
+    pub fn is_ucrxie3_0(&self) -> bool {
+        *self == UCRXIE3R::UCRXIE3_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE3_1`"]
+    #[inline]
+    pub fn is_ucrxie3_1(&self) -> bool {
+        *self == UCRXIE3R::UCRXIE3_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIE3`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIE3R {
+    #[doc = "Interrupt disabled"]
+    UCTXIE3_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE3_1,
+}
+impl UCTXIE3R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIE3R::UCTXIE3_0 => false,
+            UCTXIE3R::UCTXIE3_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIE3R {
+        match value {
+            false => UCTXIE3R::UCTXIE3_0,
+            true => UCTXIE3R::UCTXIE3_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE3_0`"]
+    #[inline]
+    pub fn is_uctxie3_0(&self) -> bool {
+        *self == UCTXIE3R::UCTXIE3_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE3_1`"]
+    #[inline]
+    pub fn is_uctxie3_1(&self) -> bool {
+        *self == UCTXIE3R::UCTXIE3_1
+    }
+}
+#[doc = "Possible values of the field `UCBIT9IE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBIT9IER {
+    #[doc = "Interrupt disabled"]
+    UCBIT9IE_0,
+    #[doc = "Interrupt enabled"]
+    UCBIT9IE_1,
+}
+impl UCBIT9IER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBIT9IER::UCBIT9IE_0 => false,
+            UCBIT9IER::UCBIT9IE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBIT9IER {
+        match value {
+            false => UCBIT9IER::UCBIT9IE_0,
+            true => UCBIT9IER::UCBIT9IE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBIT9IE_0`"]
+    #[inline]
+    pub fn is_ucbit9ie_0(&self) -> bool {
+        *self == UCBIT9IER::UCBIT9IE_0
+    }
+    #[doc = "Checks if the value of the field is `UCBIT9IE_1`"]
+    #[inline]
+    pub fn is_ucbit9ie_1(&self) -> bool {
+        *self == UCBIT9IER::UCBIT9IE_1
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIE0`"]
+pub enum UCRXIE0W {
+    #[doc = "Interrupt disabled"]
+    UCRXIE0_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE0_1,
+}
+impl UCRXIE0W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIE0W::UCRXIE0_0 => false,
+            UCRXIE0W::UCRXIE0_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIE0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIE0W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIE0W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucrxie0_0(self) -> &'a mut W {
+        self.variant(UCRXIE0W::UCRXIE0_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucrxie0_1(self) -> &'a mut W {
+        self.variant(UCRXIE0W::UCRXIE0_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIE0`"]
+pub enum UCTXIE0W {
+    #[doc = "Interrupt disabled"]
+    UCTXIE0_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE0_1,
+}
+impl UCTXIE0W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIE0W::UCTXIE0_0 => false,
+            UCTXIE0W::UCTXIE0_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIE0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIE0W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIE0W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn uctxie0_0(self) -> &'a mut W {
+        self.variant(UCTXIE0W::UCTXIE0_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn uctxie0_1(self) -> &'a mut W {
+        self.variant(UCTXIE0W::UCTXIE0_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTTIE`"]
+pub enum UCSTTIEW {
+    #[doc = "Interrupt disabled"]
+    UCSTTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCSTTIE_1,
+}
+impl UCSTTIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTTIEW::UCSTTIE_0 => false,
+            UCSTTIEW::UCSTTIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTTIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTTIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTTIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucsttie_0(self) -> &'a mut W {
+        self.variant(UCSTTIEW::UCSTTIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucsttie_1(self) -> &'a mut W {
+        self.variant(UCSTTIEW::UCSTTIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTPIE`"]
+pub enum UCSTPIEW {
+    #[doc = "Interrupt disabled"]
+    UCSTPIE_0,
+    #[doc = "Interrupt enabled"]
+    UCSTPIE_1,
+}
+impl UCSTPIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTPIEW::UCSTPIE_0 => false,
+            UCSTPIEW::UCSTPIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTPIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTPIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTPIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucstpie_0(self) -> &'a mut W {
+        self.variant(UCSTPIEW::UCSTPIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucstpie_1(self) -> &'a mut W {
+        self.variant(UCSTPIEW::UCSTPIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCALIE`"]
+pub enum UCALIEW {
+    #[doc = "Interrupt disabled"]
+    UCALIE_0,
+    #[doc = "Interrupt enabled"]
+    UCALIE_1,
+}
+impl UCALIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCALIEW::UCALIE_0 => false,
+            UCALIEW::UCALIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCALIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCALIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCALIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucalie_0(self) -> &'a mut W {
+        self.variant(UCALIEW::UCALIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucalie_1(self) -> &'a mut W {
+        self.variant(UCALIEW::UCALIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCNACKIE`"]
+pub enum UCNACKIEW {
+    #[doc = "Interrupt disabled"]
+    UCNACKIE_0,
+    #[doc = "Interrupt enabled"]
+    UCNACKIE_1,
+}
+impl UCNACKIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCNACKIEW::UCNACKIE_0 => false,
+            UCNACKIEW::UCNACKIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCNACKIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCNACKIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCNACKIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucnackie_0(self) -> &'a mut W {
+        self.variant(UCNACKIEW::UCNACKIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucnackie_1(self) -> &'a mut W {
+        self.variant(UCNACKIEW::UCNACKIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCBCNTIE`"]
+pub enum UCBCNTIEW {
+    #[doc = "Interrupt disabled"]
+    UCBCNTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCBCNTIE_1,
+}
+impl UCBCNTIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCBCNTIEW::UCBCNTIE_0 => false,
+            UCBCNTIEW::UCBCNTIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBCNTIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBCNTIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCBCNTIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucbcntie_0(self) -> &'a mut W {
+        self.variant(UCBCNTIEW::UCBCNTIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucbcntie_1(self) -> &'a mut W {
+        self.variant(UCBCNTIEW::UCBCNTIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCCLTOIE`"]
+pub enum UCCLTOIEW {
+    #[doc = "Interrupt disabled"]
+    UCCLTOIE_0,
+    #[doc = "Interrupt enabled"]
+    UCCLTOIE_1,
+}
+impl UCCLTOIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCCLTOIEW::UCCLTOIE_0 => false,
+            UCCLTOIEW::UCCLTOIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCCLTOIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCCLTOIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCCLTOIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn uccltoie_0(self) -> &'a mut W {
+        self.variant(UCCLTOIEW::UCCLTOIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn uccltoie_1(self) -> &'a mut W {
+        self.variant(UCCLTOIEW::UCCLTOIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIE1`"]
+pub enum UCRXIE1W {
+    #[doc = "Interrupt disabled"]
+    UCRXIE1_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE1_1,
+}
+impl UCRXIE1W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIE1W::UCRXIE1_0 => false,
+            UCRXIE1W::UCRXIE1_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIE1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIE1W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIE1W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucrxie1_0(self) -> &'a mut W {
+        self.variant(UCRXIE1W::UCRXIE1_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucrxie1_1(self) -> &'a mut W {
+        self.variant(UCRXIE1W::UCRXIE1_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIE1`"]
+pub enum UCTXIE1W {
+    #[doc = "Interrupt disabled"]
+    UCTXIE1_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE1_1,
+}
+impl UCTXIE1W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIE1W::UCTXIE1_0 => false,
+            UCTXIE1W::UCTXIE1_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIE1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIE1W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIE1W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn uctxie1_0(self) -> &'a mut W {
+        self.variant(UCTXIE1W::UCTXIE1_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn uctxie1_1(self) -> &'a mut W {
+        self.variant(UCTXIE1W::UCTXIE1_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIE2`"]
+pub enum UCRXIE2W {
+    #[doc = "Interrupt disabled"]
+    UCRXIE2_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE2_1,
+}
+impl UCRXIE2W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIE2W::UCRXIE2_0 => false,
+            UCRXIE2W::UCRXIE2_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIE2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIE2W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIE2W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucrxie2_0(self) -> &'a mut W {
+        self.variant(UCRXIE2W::UCRXIE2_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucrxie2_1(self) -> &'a mut W {
+        self.variant(UCRXIE2W::UCRXIE2_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIE2`"]
+pub enum UCTXIE2W {
+    #[doc = "Interrupt disabled"]
+    UCTXIE2_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE2_1,
+}
+impl UCTXIE2W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIE2W::UCTXIE2_0 => false,
+            UCTXIE2W::UCTXIE2_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIE2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIE2W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIE2W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn uctxie2_0(self) -> &'a mut W {
+        self.variant(UCTXIE2W::UCTXIE2_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn uctxie2_1(self) -> &'a mut W {
+        self.variant(UCTXIE2W::UCTXIE2_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIE3`"]
+pub enum UCRXIE3W {
+    #[doc = "Interrupt disabled"]
+    UCRXIE3_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE3_1,
+}
+impl UCRXIE3W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIE3W::UCRXIE3_0 => false,
+            UCRXIE3W::UCRXIE3_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIE3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIE3W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIE3W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucrxie3_0(self) -> &'a mut W {
+        self.variant(UCRXIE3W::UCRXIE3_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucrxie3_1(self) -> &'a mut W {
+        self.variant(UCRXIE3W::UCRXIE3_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIE3`"]
+pub enum UCTXIE3W {
+    #[doc = "Interrupt disabled"]
+    UCTXIE3_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE3_1,
+}
+impl UCTXIE3W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIE3W::UCTXIE3_0 => false,
+            UCTXIE3W::UCTXIE3_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIE3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIE3W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIE3W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn uctxie3_0(self) -> &'a mut W {
+        self.variant(UCTXIE3W::UCTXIE3_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn uctxie3_1(self) -> &'a mut W {
+        self.variant(UCTXIE3W::UCTXIE3_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCBIT9IE`"]
+pub enum UCBIT9IEW {
+    #[doc = "Interrupt disabled"]
+    UCBIT9IE_0,
+    #[doc = "Interrupt enabled"]
+    UCBIT9IE_1,
+}
+impl UCBIT9IEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCBIT9IEW::UCBIT9IE_0 => false,
+            UCBIT9IEW::UCBIT9IE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBIT9IEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBIT9IEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCBIT9IEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucbit9ie_0(self) -> &'a mut W {
+        self.variant(UCBIT9IEW::UCBIT9IE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucbit9ie_1(self) -> &'a mut W {
+        self.variant(UCBIT9IEW::UCBIT9IE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Receive interrupt enable 0"]
+    #[inline]
+    pub fn ucrxie0(&self) -> UCRXIE0R {
+        UCRXIE0R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Transmit interrupt enable 0"]
+    #[inline]
+    pub fn uctxie0(&self) -> UCTXIE0R {
+        UCTXIE0R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - START condition interrupt enable"]
+    #[inline]
+    pub fn ucsttie(&self) -> UCSTTIER {
+        UCSTTIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - STOP condition interrupt enable"]
+    #[inline]
+    pub fn ucstpie(&self) -> UCSTPIER {
+        UCSTPIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 4 - Arbitration lost interrupt enable"]
+    #[inline]
+    pub fn ucalie(&self) -> UCALIER {
+        UCALIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - Not-acknowledge interrupt enable"]
+    #[inline]
+    pub fn ucnackie(&self) -> UCNACKIER {
+        UCNACKIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 6 - Byte counter interrupt enable"]
+    #[inline]
+    pub fn ucbcntie(&self) -> UCBCNTIER {
+        UCBCNTIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 7 - Clock low timeout interrupt enable"]
+    #[inline]
+    pub fn uccltoie(&self) -> UCCLTOIER {
+        UCCLTOIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 8 - Receive interrupt enable 1"]
+    #[inline]
+    pub fn ucrxie1(&self) -> UCRXIE1R {
+        UCRXIE1R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 9 - Transmit interrupt enable 1"]
+    #[inline]
+    pub fn uctxie1(&self) -> UCTXIE1R {
+        UCTXIE1R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 10 - Receive interrupt enable 2"]
+    #[inline]
+    pub fn ucrxie2(&self) -> UCRXIE2R {
+        UCRXIE2R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 11 - Transmit interrupt enable 2"]
+    #[inline]
+    pub fn uctxie2(&self) -> UCTXIE2R {
+        UCTXIE2R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 12 - Receive interrupt enable 3"]
+    #[inline]
+    pub fn ucrxie3(&self) -> UCRXIE3R {
+        UCRXIE3R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 13 - Transmit interrupt enable 3"]
+    #[inline]
+    pub fn uctxie3(&self) -> UCTXIE3R {
+        UCTXIE3R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 14 - Bit position 9 interrupt enable"]
+    #[inline]
+    pub fn ucbit9ie(&self) -> UCBIT9IER {
+        UCBIT9IER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Receive interrupt enable 0"]
+    #[inline]
+    pub fn ucrxie0(&mut self) -> _UCRXIE0W {
+        _UCRXIE0W { w: self }
+    }
+    #[doc = "Bit 1 - Transmit interrupt enable 0"]
+    #[inline]
+    pub fn uctxie0(&mut self) -> _UCTXIE0W {
+        _UCTXIE0W { w: self }
+    }
+    #[doc = "Bit 2 - START condition interrupt enable"]
+    #[inline]
+    pub fn ucsttie(&mut self) -> _UCSTTIEW {
+        _UCSTTIEW { w: self }
+    }
+    #[doc = "Bit 3 - STOP condition interrupt enable"]
+    #[inline]
+    pub fn ucstpie(&mut self) -> _UCSTPIEW {
+        _UCSTPIEW { w: self }
+    }
+    #[doc = "Bit 4 - Arbitration lost interrupt enable"]
+    #[inline]
+    pub fn ucalie(&mut self) -> _UCALIEW {
+        _UCALIEW { w: self }
+    }
+    #[doc = "Bit 5 - Not-acknowledge interrupt enable"]
+    #[inline]
+    pub fn ucnackie(&mut self) -> _UCNACKIEW {
+        _UCNACKIEW { w: self }
+    }
+    #[doc = "Bit 6 - Byte counter interrupt enable"]
+    #[inline]
+    pub fn ucbcntie(&mut self) -> _UCBCNTIEW {
+        _UCBCNTIEW { w: self }
+    }
+    #[doc = "Bit 7 - Clock low timeout interrupt enable"]
+    #[inline]
+    pub fn uccltoie(&mut self) -> _UCCLTOIEW {
+        _UCCLTOIEW { w: self }
+    }
+    #[doc = "Bit 8 - Receive interrupt enable 1"]
+    #[inline]
+    pub fn ucrxie1(&mut self) -> _UCRXIE1W {
+        _UCRXIE1W { w: self }
+    }
+    #[doc = "Bit 9 - Transmit interrupt enable 1"]
+    #[inline]
+    pub fn uctxie1(&mut self) -> _UCTXIE1W {
+        _UCTXIE1W { w: self }
+    }
+    #[doc = "Bit 10 - Receive interrupt enable 2"]
+    #[inline]
+    pub fn ucrxie2(&mut self) -> _UCRXIE2W {
+        _UCRXIE2W { w: self }
+    }
+    #[doc = "Bit 11 - Transmit interrupt enable 2"]
+    #[inline]
+    pub fn uctxie2(&mut self) -> _UCTXIE2W {
+        _UCTXIE2W { w: self }
+    }
+    #[doc = "Bit 12 - Receive interrupt enable 3"]
+    #[inline]
+    pub fn ucrxie3(&mut self) -> _UCRXIE3W {
+        _UCRXIE3W { w: self }
+    }
+    #[doc = "Bit 13 - Transmit interrupt enable 3"]
+    #[inline]
+    pub fn uctxie3(&mut self) -> _UCTXIE3W {
+        _UCTXIE3W { w: self }
+    }
+    #[doc = "Bit 14 - Bit position 9 interrupt enable"]
+    #[inline]
+    pub fn ucbit9ie(&mut self) -> _UCBIT9IEW {
+        _UCBIT9IEW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b0/ucbx_ifg.rs b/example-source/msp432p401r/src/eusci_b0/ucbx_ifg.rs
new file mode 100644
index 0000000..28681c9
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b0/ucbx_ifg.rs
@@ -0,0 +1,1849 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXIFG {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCRXIFG0`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIFG0R {
+    #[doc = "No interrupt pending"]
+    UCRXIFG0_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG0_1,
+}
+impl UCRXIFG0R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIFG0R::UCRXIFG0_0 => false,
+            UCRXIFG0R::UCRXIFG0_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIFG0R {
+        match value {
+            false => UCRXIFG0R::UCRXIFG0_0,
+            true => UCRXIFG0R::UCRXIFG0_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG0_0`"]
+    #[inline]
+    pub fn is_ucrxifg0_0(&self) -> bool {
+        *self == UCRXIFG0R::UCRXIFG0_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG0_1`"]
+    #[inline]
+    pub fn is_ucrxifg0_1(&self) -> bool {
+        *self == UCRXIFG0R::UCRXIFG0_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIFG0`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIFG0R {
+    #[doc = "No interrupt pending"]
+    UCTXIFG0_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG0_1,
+}
+impl UCTXIFG0R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIFG0R::UCTXIFG0_0 => false,
+            UCTXIFG0R::UCTXIFG0_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIFG0R {
+        match value {
+            false => UCTXIFG0R::UCTXIFG0_0,
+            true => UCTXIFG0R::UCTXIFG0_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG0_0`"]
+    #[inline]
+    pub fn is_uctxifg0_0(&self) -> bool {
+        *self == UCTXIFG0R::UCTXIFG0_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG0_1`"]
+    #[inline]
+    pub fn is_uctxifg0_1(&self) -> bool {
+        *self == UCTXIFG0R::UCTXIFG0_1
+    }
+}
+#[doc = "Possible values of the field `UCSTTIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTTIFGR {
+    #[doc = "No interrupt pending"]
+    UCSTTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCSTTIFG_1,
+}
+impl UCSTTIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTTIFGR::UCSTTIFG_0 => false,
+            UCSTTIFGR::UCSTTIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTTIFGR {
+        match value {
+            false => UCSTTIFGR::UCSTTIFG_0,
+            true => UCSTTIFGR::UCSTTIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIFG_0`"]
+    #[inline]
+    pub fn is_ucsttifg_0(&self) -> bool {
+        *self == UCSTTIFGR::UCSTTIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIFG_1`"]
+    #[inline]
+    pub fn is_ucsttifg_1(&self) -> bool {
+        *self == UCSTTIFGR::UCSTTIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCSTPIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTPIFGR {
+    #[doc = "No interrupt pending"]
+    UCSTPIFG_0,
+    #[doc = "Interrupt pending"]
+    UCSTPIFG_1,
+}
+impl UCSTPIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTPIFGR::UCSTPIFG_0 => false,
+            UCSTPIFGR::UCSTPIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTPIFGR {
+        match value {
+            false => UCSTPIFGR::UCSTPIFG_0,
+            true => UCSTPIFGR::UCSTPIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTPIFG_0`"]
+    #[inline]
+    pub fn is_ucstpifg_0(&self) -> bool {
+        *self == UCSTPIFGR::UCSTPIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTPIFG_1`"]
+    #[inline]
+    pub fn is_ucstpifg_1(&self) -> bool {
+        *self == UCSTPIFGR::UCSTPIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCALIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCALIFGR {
+    #[doc = "No interrupt pending"]
+    UCALIFG_0,
+    #[doc = "Interrupt pending"]
+    UCALIFG_1,
+}
+impl UCALIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCALIFGR::UCALIFG_0 => false,
+            UCALIFGR::UCALIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCALIFGR {
+        match value {
+            false => UCALIFGR::UCALIFG_0,
+            true => UCALIFGR::UCALIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCALIFG_0`"]
+    #[inline]
+    pub fn is_ucalifg_0(&self) -> bool {
+        *self == UCALIFGR::UCALIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCALIFG_1`"]
+    #[inline]
+    pub fn is_ucalifg_1(&self) -> bool {
+        *self == UCALIFGR::UCALIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCNACKIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCNACKIFGR {
+    #[doc = "No interrupt pending"]
+    UCNACKIFG_0,
+    #[doc = "Interrupt pending"]
+    UCNACKIFG_1,
+}
+impl UCNACKIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCNACKIFGR::UCNACKIFG_0 => false,
+            UCNACKIFGR::UCNACKIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCNACKIFGR {
+        match value {
+            false => UCNACKIFGR::UCNACKIFG_0,
+            true => UCNACKIFGR::UCNACKIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCNACKIFG_0`"]
+    #[inline]
+    pub fn is_ucnackifg_0(&self) -> bool {
+        *self == UCNACKIFGR::UCNACKIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCNACKIFG_1`"]
+    #[inline]
+    pub fn is_ucnackifg_1(&self) -> bool {
+        *self == UCNACKIFGR::UCNACKIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCBCNTIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBCNTIFGR {
+    #[doc = "No interrupt pending"]
+    UCBCNTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCBCNTIFG_1,
+}
+impl UCBCNTIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBCNTIFGR::UCBCNTIFG_0 => false,
+            UCBCNTIFGR::UCBCNTIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBCNTIFGR {
+        match value {
+            false => UCBCNTIFGR::UCBCNTIFG_0,
+            true => UCBCNTIFGR::UCBCNTIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBCNTIFG_0`"]
+    #[inline]
+    pub fn is_ucbcntifg_0(&self) -> bool {
+        *self == UCBCNTIFGR::UCBCNTIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCBCNTIFG_1`"]
+    #[inline]
+    pub fn is_ucbcntifg_1(&self) -> bool {
+        *self == UCBCNTIFGR::UCBCNTIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCCLTOIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCCLTOIFGR {
+    #[doc = "No interrupt pending"]
+    UCCLTOIFG_0,
+    #[doc = "Interrupt pending"]
+    UCCLTOIFG_1,
+}
+impl UCCLTOIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCCLTOIFGR::UCCLTOIFG_0 => false,
+            UCCLTOIFGR::UCCLTOIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCCLTOIFGR {
+        match value {
+            false => UCCLTOIFGR::UCCLTOIFG_0,
+            true => UCCLTOIFGR::UCCLTOIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCCLTOIFG_0`"]
+    #[inline]
+    pub fn is_uccltoifg_0(&self) -> bool {
+        *self == UCCLTOIFGR::UCCLTOIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCCLTOIFG_1`"]
+    #[inline]
+    pub fn is_uccltoifg_1(&self) -> bool {
+        *self == UCCLTOIFGR::UCCLTOIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCRXIFG1`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIFG1R {
+    #[doc = "No interrupt pending"]
+    UCRXIFG1_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG1_1,
+}
+impl UCRXIFG1R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIFG1R::UCRXIFG1_0 => false,
+            UCRXIFG1R::UCRXIFG1_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIFG1R {
+        match value {
+            false => UCRXIFG1R::UCRXIFG1_0,
+            true => UCRXIFG1R::UCRXIFG1_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG1_0`"]
+    #[inline]
+    pub fn is_ucrxifg1_0(&self) -> bool {
+        *self == UCRXIFG1R::UCRXIFG1_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG1_1`"]
+    #[inline]
+    pub fn is_ucrxifg1_1(&self) -> bool {
+        *self == UCRXIFG1R::UCRXIFG1_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIFG1`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIFG1R {
+    #[doc = "No interrupt pending"]
+    UCTXIFG1_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG1_1,
+}
+impl UCTXIFG1R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIFG1R::UCTXIFG1_0 => false,
+            UCTXIFG1R::UCTXIFG1_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIFG1R {
+        match value {
+            false => UCTXIFG1R::UCTXIFG1_0,
+            true => UCTXIFG1R::UCTXIFG1_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG1_0`"]
+    #[inline]
+    pub fn is_uctxifg1_0(&self) -> bool {
+        *self == UCTXIFG1R::UCTXIFG1_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG1_1`"]
+    #[inline]
+    pub fn is_uctxifg1_1(&self) -> bool {
+        *self == UCTXIFG1R::UCTXIFG1_1
+    }
+}
+#[doc = "Possible values of the field `UCRXIFG2`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIFG2R {
+    #[doc = "No interrupt pending"]
+    UCRXIFG2_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG2_1,
+}
+impl UCRXIFG2R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIFG2R::UCRXIFG2_0 => false,
+            UCRXIFG2R::UCRXIFG2_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIFG2R {
+        match value {
+            false => UCRXIFG2R::UCRXIFG2_0,
+            true => UCRXIFG2R::UCRXIFG2_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG2_0`"]
+    #[inline]
+    pub fn is_ucrxifg2_0(&self) -> bool {
+        *self == UCRXIFG2R::UCRXIFG2_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG2_1`"]
+    #[inline]
+    pub fn is_ucrxifg2_1(&self) -> bool {
+        *self == UCRXIFG2R::UCRXIFG2_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIFG2`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIFG2R {
+    #[doc = "No interrupt pending"]
+    UCTXIFG2_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG2_1,
+}
+impl UCTXIFG2R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIFG2R::UCTXIFG2_0 => false,
+            UCTXIFG2R::UCTXIFG2_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIFG2R {
+        match value {
+            false => UCTXIFG2R::UCTXIFG2_0,
+            true => UCTXIFG2R::UCTXIFG2_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG2_0`"]
+    #[inline]
+    pub fn is_uctxifg2_0(&self) -> bool {
+        *self == UCTXIFG2R::UCTXIFG2_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG2_1`"]
+    #[inline]
+    pub fn is_uctxifg2_1(&self) -> bool {
+        *self == UCTXIFG2R::UCTXIFG2_1
+    }
+}
+#[doc = "Possible values of the field `UCRXIFG3`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIFG3R {
+    #[doc = "No interrupt pending"]
+    UCRXIFG3_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG3_1,
+}
+impl UCRXIFG3R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIFG3R::UCRXIFG3_0 => false,
+            UCRXIFG3R::UCRXIFG3_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIFG3R {
+        match value {
+            false => UCRXIFG3R::UCRXIFG3_0,
+            true => UCRXIFG3R::UCRXIFG3_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG3_0`"]
+    #[inline]
+    pub fn is_ucrxifg3_0(&self) -> bool {
+        *self == UCRXIFG3R::UCRXIFG3_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG3_1`"]
+    #[inline]
+    pub fn is_ucrxifg3_1(&self) -> bool {
+        *self == UCRXIFG3R::UCRXIFG3_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIFG3`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIFG3R {
+    #[doc = "No interrupt pending"]
+    UCTXIFG3_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG3_1,
+}
+impl UCTXIFG3R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIFG3R::UCTXIFG3_0 => false,
+            UCTXIFG3R::UCTXIFG3_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIFG3R {
+        match value {
+            false => UCTXIFG3R::UCTXIFG3_0,
+            true => UCTXIFG3R::UCTXIFG3_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG3_0`"]
+    #[inline]
+    pub fn is_uctxifg3_0(&self) -> bool {
+        *self == UCTXIFG3R::UCTXIFG3_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG3_1`"]
+    #[inline]
+    pub fn is_uctxifg3_1(&self) -> bool {
+        *self == UCTXIFG3R::UCTXIFG3_1
+    }
+}
+#[doc = "Possible values of the field `UCBIT9IFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBIT9IFGR {
+    #[doc = "No interrupt pending"]
+    UCBIT9IFG_0,
+    #[doc = "Interrupt pending"]
+    UCBIT9IFG_1,
+}
+impl UCBIT9IFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBIT9IFGR::UCBIT9IFG_0 => false,
+            UCBIT9IFGR::UCBIT9IFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBIT9IFGR {
+        match value {
+            false => UCBIT9IFGR::UCBIT9IFG_0,
+            true => UCBIT9IFGR::UCBIT9IFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBIT9IFG_0`"]
+    #[inline]
+    pub fn is_ucbit9ifg_0(&self) -> bool {
+        *self == UCBIT9IFGR::UCBIT9IFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCBIT9IFG_1`"]
+    #[inline]
+    pub fn is_ucbit9ifg_1(&self) -> bool {
+        *self == UCBIT9IFGR::UCBIT9IFG_1
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIFG0`"]
+pub enum UCRXIFG0W {
+    #[doc = "No interrupt pending"]
+    UCRXIFG0_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG0_1,
+}
+impl UCRXIFG0W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIFG0W::UCRXIFG0_0 => false,
+            UCRXIFG0W::UCRXIFG0_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIFG0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIFG0W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIFG0W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucrxifg0_0(self) -> &'a mut W {
+        self.variant(UCRXIFG0W::UCRXIFG0_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucrxifg0_1(self) -> &'a mut W {
+        self.variant(UCRXIFG0W::UCRXIFG0_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIFG0`"]
+pub enum UCTXIFG0W {
+    #[doc = "No interrupt pending"]
+    UCTXIFG0_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG0_1,
+}
+impl UCTXIFG0W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIFG0W::UCTXIFG0_0 => false,
+            UCTXIFG0W::UCTXIFG0_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIFG0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIFG0W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIFG0W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn uctxifg0_0(self) -> &'a mut W {
+        self.variant(UCTXIFG0W::UCTXIFG0_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn uctxifg0_1(self) -> &'a mut W {
+        self.variant(UCTXIFG0W::UCTXIFG0_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTTIFG`"]
+pub enum UCSTTIFGW {
+    #[doc = "No interrupt pending"]
+    UCSTTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCSTTIFG_1,
+}
+impl UCSTTIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTTIFGW::UCSTTIFG_0 => false,
+            UCSTTIFGW::UCSTTIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTTIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTTIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTTIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucsttifg_0(self) -> &'a mut W {
+        self.variant(UCSTTIFGW::UCSTTIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucsttifg_1(self) -> &'a mut W {
+        self.variant(UCSTTIFGW::UCSTTIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTPIFG`"]
+pub enum UCSTPIFGW {
+    #[doc = "No interrupt pending"]
+    UCSTPIFG_0,
+    #[doc = "Interrupt pending"]
+    UCSTPIFG_1,
+}
+impl UCSTPIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTPIFGW::UCSTPIFG_0 => false,
+            UCSTPIFGW::UCSTPIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTPIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTPIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTPIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucstpifg_0(self) -> &'a mut W {
+        self.variant(UCSTPIFGW::UCSTPIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucstpifg_1(self) -> &'a mut W {
+        self.variant(UCSTPIFGW::UCSTPIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCALIFG`"]
+pub enum UCALIFGW {
+    #[doc = "No interrupt pending"]
+    UCALIFG_0,
+    #[doc = "Interrupt pending"]
+    UCALIFG_1,
+}
+impl UCALIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCALIFGW::UCALIFG_0 => false,
+            UCALIFGW::UCALIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCALIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCALIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCALIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucalifg_0(self) -> &'a mut W {
+        self.variant(UCALIFGW::UCALIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucalifg_1(self) -> &'a mut W {
+        self.variant(UCALIFGW::UCALIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCNACKIFG`"]
+pub enum UCNACKIFGW {
+    #[doc = "No interrupt pending"]
+    UCNACKIFG_0,
+    #[doc = "Interrupt pending"]
+    UCNACKIFG_1,
+}
+impl UCNACKIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCNACKIFGW::UCNACKIFG_0 => false,
+            UCNACKIFGW::UCNACKIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCNACKIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCNACKIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCNACKIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucnackifg_0(self) -> &'a mut W {
+        self.variant(UCNACKIFGW::UCNACKIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucnackifg_1(self) -> &'a mut W {
+        self.variant(UCNACKIFGW::UCNACKIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCBCNTIFG`"]
+pub enum UCBCNTIFGW {
+    #[doc = "No interrupt pending"]
+    UCBCNTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCBCNTIFG_1,
+}
+impl UCBCNTIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCBCNTIFGW::UCBCNTIFG_0 => false,
+            UCBCNTIFGW::UCBCNTIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBCNTIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBCNTIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCBCNTIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucbcntifg_0(self) -> &'a mut W {
+        self.variant(UCBCNTIFGW::UCBCNTIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucbcntifg_1(self) -> &'a mut W {
+        self.variant(UCBCNTIFGW::UCBCNTIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCCLTOIFG`"]
+pub enum UCCLTOIFGW {
+    #[doc = "No interrupt pending"]
+    UCCLTOIFG_0,
+    #[doc = "Interrupt pending"]
+    UCCLTOIFG_1,
+}
+impl UCCLTOIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCCLTOIFGW::UCCLTOIFG_0 => false,
+            UCCLTOIFGW::UCCLTOIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCCLTOIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCCLTOIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCCLTOIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn uccltoifg_0(self) -> &'a mut W {
+        self.variant(UCCLTOIFGW::UCCLTOIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn uccltoifg_1(self) -> &'a mut W {
+        self.variant(UCCLTOIFGW::UCCLTOIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIFG1`"]
+pub enum UCRXIFG1W {
+    #[doc = "No interrupt pending"]
+    UCRXIFG1_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG1_1,
+}
+impl UCRXIFG1W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIFG1W::UCRXIFG1_0 => false,
+            UCRXIFG1W::UCRXIFG1_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIFG1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIFG1W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIFG1W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucrxifg1_0(self) -> &'a mut W {
+        self.variant(UCRXIFG1W::UCRXIFG1_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucrxifg1_1(self) -> &'a mut W {
+        self.variant(UCRXIFG1W::UCRXIFG1_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIFG1`"]
+pub enum UCTXIFG1W {
+    #[doc = "No interrupt pending"]
+    UCTXIFG1_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG1_1,
+}
+impl UCTXIFG1W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIFG1W::UCTXIFG1_0 => false,
+            UCTXIFG1W::UCTXIFG1_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIFG1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIFG1W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIFG1W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn uctxifg1_0(self) -> &'a mut W {
+        self.variant(UCTXIFG1W::UCTXIFG1_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn uctxifg1_1(self) -> &'a mut W {
+        self.variant(UCTXIFG1W::UCTXIFG1_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIFG2`"]
+pub enum UCRXIFG2W {
+    #[doc = "No interrupt pending"]
+    UCRXIFG2_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG2_1,
+}
+impl UCRXIFG2W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIFG2W::UCRXIFG2_0 => false,
+            UCRXIFG2W::UCRXIFG2_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIFG2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIFG2W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIFG2W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucrxifg2_0(self) -> &'a mut W {
+        self.variant(UCRXIFG2W::UCRXIFG2_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucrxifg2_1(self) -> &'a mut W {
+        self.variant(UCRXIFG2W::UCRXIFG2_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIFG2`"]
+pub enum UCTXIFG2W {
+    #[doc = "No interrupt pending"]
+    UCTXIFG2_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG2_1,
+}
+impl UCTXIFG2W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIFG2W::UCTXIFG2_0 => false,
+            UCTXIFG2W::UCTXIFG2_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIFG2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIFG2W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIFG2W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn uctxifg2_0(self) -> &'a mut W {
+        self.variant(UCTXIFG2W::UCTXIFG2_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn uctxifg2_1(self) -> &'a mut W {
+        self.variant(UCTXIFG2W::UCTXIFG2_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIFG3`"]
+pub enum UCRXIFG3W {
+    #[doc = "No interrupt pending"]
+    UCRXIFG3_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG3_1,
+}
+impl UCRXIFG3W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIFG3W::UCRXIFG3_0 => false,
+            UCRXIFG3W::UCRXIFG3_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIFG3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIFG3W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIFG3W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucrxifg3_0(self) -> &'a mut W {
+        self.variant(UCRXIFG3W::UCRXIFG3_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucrxifg3_1(self) -> &'a mut W {
+        self.variant(UCRXIFG3W::UCRXIFG3_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIFG3`"]
+pub enum UCTXIFG3W {
+    #[doc = "No interrupt pending"]
+    UCTXIFG3_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG3_1,
+}
+impl UCTXIFG3W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIFG3W::UCTXIFG3_0 => false,
+            UCTXIFG3W::UCTXIFG3_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIFG3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIFG3W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIFG3W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn uctxifg3_0(self) -> &'a mut W {
+        self.variant(UCTXIFG3W::UCTXIFG3_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn uctxifg3_1(self) -> &'a mut W {
+        self.variant(UCTXIFG3W::UCTXIFG3_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCBIT9IFG`"]
+pub enum UCBIT9IFGW {
+    #[doc = "No interrupt pending"]
+    UCBIT9IFG_0,
+    #[doc = "Interrupt pending"]
+    UCBIT9IFG_1,
+}
+impl UCBIT9IFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCBIT9IFGW::UCBIT9IFG_0 => false,
+            UCBIT9IFGW::UCBIT9IFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBIT9IFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBIT9IFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCBIT9IFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucbit9ifg_0(self) -> &'a mut W {
+        self.variant(UCBIT9IFGW::UCBIT9IFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucbit9ifg_1(self) -> &'a mut W {
+        self.variant(UCBIT9IFGW::UCBIT9IFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - eUSCI_B receive interrupt flag 0"]
+    #[inline]
+    pub fn ucrxifg0(&self) -> UCRXIFG0R {
+        UCRXIFG0R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - eUSCI_B transmit interrupt flag 0"]
+    #[inline]
+    pub fn uctxifg0(&self) -> UCTXIFG0R {
+        UCTXIFG0R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - START condition interrupt flag"]
+    #[inline]
+    pub fn ucsttifg(&self) -> UCSTTIFGR {
+        UCSTTIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - STOP condition interrupt flag"]
+    #[inline]
+    pub fn ucstpifg(&self) -> UCSTPIFGR {
+        UCSTPIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 4 - Arbitration lost interrupt flag"]
+    #[inline]
+    pub fn ucalifg(&self) -> UCALIFGR {
+        UCALIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - Not-acknowledge received interrupt flag"]
+    #[inline]
+    pub fn ucnackifg(&self) -> UCNACKIFGR {
+        UCNACKIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 6 - Byte counter interrupt flag"]
+    #[inline]
+    pub fn ucbcntifg(&self) -> UCBCNTIFGR {
+        UCBCNTIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 7 - Clock low timeout interrupt flag"]
+    #[inline]
+    pub fn uccltoifg(&self) -> UCCLTOIFGR {
+        UCCLTOIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 8 - eUSCI_B receive interrupt flag 1"]
+    #[inline]
+    pub fn ucrxifg1(&self) -> UCRXIFG1R {
+        UCRXIFG1R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 9 - eUSCI_B transmit interrupt flag 1"]
+    #[inline]
+    pub fn uctxifg1(&self) -> UCTXIFG1R {
+        UCTXIFG1R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 10 - eUSCI_B receive interrupt flag 2"]
+    #[inline]
+    pub fn ucrxifg2(&self) -> UCRXIFG2R {
+        UCRXIFG2R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 11 - eUSCI_B transmit interrupt flag 2"]
+    #[inline]
+    pub fn uctxifg2(&self) -> UCTXIFG2R {
+        UCTXIFG2R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 12 - eUSCI_B receive interrupt flag 3"]
+    #[inline]
+    pub fn ucrxifg3(&self) -> UCRXIFG3R {
+        UCRXIFG3R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 13 - eUSCI_B transmit interrupt flag 3"]
+    #[inline]
+    pub fn uctxifg3(&self) -> UCTXIFG3R {
+        UCTXIFG3R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 14 - Bit position 9 interrupt flag"]
+    #[inline]
+    pub fn ucbit9ifg(&self) -> UCBIT9IFGR {
+        UCBIT9IFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 2 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - eUSCI_B receive interrupt flag 0"]
+    #[inline]
+    pub fn ucrxifg0(&mut self) -> _UCRXIFG0W {
+        _UCRXIFG0W { w: self }
+    }
+    #[doc = "Bit 1 - eUSCI_B transmit interrupt flag 0"]
+    #[inline]
+    pub fn uctxifg0(&mut self) -> _UCTXIFG0W {
+        _UCTXIFG0W { w: self }
+    }
+    #[doc = "Bit 2 - START condition interrupt flag"]
+    #[inline]
+    pub fn ucsttifg(&mut self) -> _UCSTTIFGW {
+        _UCSTTIFGW { w: self }
+    }
+    #[doc = "Bit 3 - STOP condition interrupt flag"]
+    #[inline]
+    pub fn ucstpifg(&mut self) -> _UCSTPIFGW {
+        _UCSTPIFGW { w: self }
+    }
+    #[doc = "Bit 4 - Arbitration lost interrupt flag"]
+    #[inline]
+    pub fn ucalifg(&mut self) -> _UCALIFGW {
+        _UCALIFGW { w: self }
+    }
+    #[doc = "Bit 5 - Not-acknowledge received interrupt flag"]
+    #[inline]
+    pub fn ucnackifg(&mut self) -> _UCNACKIFGW {
+        _UCNACKIFGW { w: self }
+    }
+    #[doc = "Bit 6 - Byte counter interrupt flag"]
+    #[inline]
+    pub fn ucbcntifg(&mut self) -> _UCBCNTIFGW {
+        _UCBCNTIFGW { w: self }
+    }
+    #[doc = "Bit 7 - Clock low timeout interrupt flag"]
+    #[inline]
+    pub fn uccltoifg(&mut self) -> _UCCLTOIFGW {
+        _UCCLTOIFGW { w: self }
+    }
+    #[doc = "Bit 8 - eUSCI_B receive interrupt flag 1"]
+    #[inline]
+    pub fn ucrxifg1(&mut self) -> _UCRXIFG1W {
+        _UCRXIFG1W { w: self }
+    }
+    #[doc = "Bit 9 - eUSCI_B transmit interrupt flag 1"]
+    #[inline]
+    pub fn uctxifg1(&mut self) -> _UCTXIFG1W {
+        _UCTXIFG1W { w: self }
+    }
+    #[doc = "Bit 10 - eUSCI_B receive interrupt flag 2"]
+    #[inline]
+    pub fn ucrxifg2(&mut self) -> _UCRXIFG2W {
+        _UCRXIFG2W { w: self }
+    }
+    #[doc = "Bit 11 - eUSCI_B transmit interrupt flag 2"]
+    #[inline]
+    pub fn uctxifg2(&mut self) -> _UCTXIFG2W {
+        _UCTXIFG2W { w: self }
+    }
+    #[doc = "Bit 12 - eUSCI_B receive interrupt flag 3"]
+    #[inline]
+    pub fn ucrxifg3(&mut self) -> _UCRXIFG3W {
+        _UCRXIFG3W { w: self }
+    }
+    #[doc = "Bit 13 - eUSCI_B transmit interrupt flag 3"]
+    #[inline]
+    pub fn uctxifg3(&mut self) -> _UCTXIFG3W {
+        _UCTXIFG3W { w: self }
+    }
+    #[doc = "Bit 14 - Bit position 9 interrupt flag"]
+    #[inline]
+    pub fn ucbit9ifg(&mut self) -> _UCBIT9IFGW {
+        _UCBIT9IFGW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b0/ucbx_iv.rs b/example-source/msp432p401r/src/eusci_b0/ucbx_iv.rs
new file mode 100644
index 0000000..68af1a6
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b0/ucbx_iv.rs
@@ -0,0 +1,196 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::UCBXIV {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `UCIV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCIVR {
+    #[doc = "No interrupt pending"]
+    UCIV_0,
+    #[doc = "Interrupt Source: Arbitration lost; Interrupt Flag: UCALIFG; Interrupt Priority: Highest"]
+    UCIV_2,
+    #[doc = "Interrupt Source: Not acknowledgment; Interrupt Flag: UCNACKIFG"]
+    UCIV_4,
+    #[doc = "Interrupt Source: Start condition received; Interrupt Flag: UCSTTIFG"]
+    UCIV_6,
+    #[doc = "Interrupt Source: Stop condition received; Interrupt Flag: UCSTPIFG"]
+    UCIV_8,
+    #[doc = "Interrupt Source: Slave 3 Data received; Interrupt Flag: UCRXIFG3"]
+    UCIV_10,
+    #[doc = "Interrupt Source: Slave 3 Transmit buffer empty; Interrupt Flag: UCTXIFG3"]
+    UCIV_12,
+    #[doc = "Interrupt Source: Slave 2 Data received; Interrupt Flag: UCRXIFG2"]
+    UCIV_14,
+    #[doc = "Interrupt Source: Slave 2 Transmit buffer empty; Interrupt Flag: UCTXIFG2"]
+    UCIV_16,
+    #[doc = "Interrupt Source: Slave 1 Data received; Interrupt Flag: UCRXIFG1"]
+    UCIV_18,
+    #[doc = "Interrupt Source: Slave 1 Transmit buffer empty; Interrupt Flag: UCTXIFG1"]
+    UCIV_20,
+    #[doc = "Interrupt Source: Data received; Interrupt Flag: UCRXIFG0"]
+    UCIV_22,
+    #[doc = "Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG0"]
+    UCIV_24,
+    #[doc = "Interrupt Source: Byte counter zero; Interrupt Flag: UCBCNTIFG"]
+    UCIV_26,
+    #[doc = "Interrupt Source: Clock low timeout; Interrupt Flag: UCCLTOIFG"]
+    UCIV_28,
+    #[doc = "Interrupt Source: Nineth bit position; Interrupt Flag: UCBIT9IFG; Priority: Lowest"]
+    UCIV_30,
+    #[doc = r" Reserved"]
+    _Reserved(u16),
+}
+impl UCIVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        match *self {
+            UCIVR::UCIV_0 => 0,
+            UCIVR::UCIV_2 => 2,
+            UCIVR::UCIV_4 => 4,
+            UCIVR::UCIV_6 => 6,
+            UCIVR::UCIV_8 => 8,
+            UCIVR::UCIV_10 => 10,
+            UCIVR::UCIV_12 => 12,
+            UCIVR::UCIV_14 => 14,
+            UCIVR::UCIV_16 => 16,
+            UCIVR::UCIV_18 => 18,
+            UCIVR::UCIV_20 => 20,
+            UCIVR::UCIV_22 => 22,
+            UCIVR::UCIV_24 => 24,
+            UCIVR::UCIV_26 => 26,
+            UCIVR::UCIV_28 => 28,
+            UCIVR::UCIV_30 => 30,
+            UCIVR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u16) -> UCIVR {
+        match value {
+            0 => UCIVR::UCIV_0,
+            2 => UCIVR::UCIV_2,
+            4 => UCIVR::UCIV_4,
+            6 => UCIVR::UCIV_6,
+            8 => UCIVR::UCIV_8,
+            10 => UCIVR::UCIV_10,
+            12 => UCIVR::UCIV_12,
+            14 => UCIVR::UCIV_14,
+            16 => UCIVR::UCIV_16,
+            18 => UCIVR::UCIV_18,
+            20 => UCIVR::UCIV_20,
+            22 => UCIVR::UCIV_22,
+            24 => UCIVR::UCIV_24,
+            26 => UCIVR::UCIV_26,
+            28 => UCIVR::UCIV_28,
+            30 => UCIVR::UCIV_30,
+            i => UCIVR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCIV_0`"]
+    #[inline]
+    pub fn is_uciv_0(&self) -> bool {
+        *self == UCIVR::UCIV_0
+    }
+    #[doc = "Checks if the value of the field is `UCIV_2`"]
+    #[inline]
+    pub fn is_uciv_2(&self) -> bool {
+        *self == UCIVR::UCIV_2
+    }
+    #[doc = "Checks if the value of the field is `UCIV_4`"]
+    #[inline]
+    pub fn is_uciv_4(&self) -> bool {
+        *self == UCIVR::UCIV_4
+    }
+    #[doc = "Checks if the value of the field is `UCIV_6`"]
+    #[inline]
+    pub fn is_uciv_6(&self) -> bool {
+        *self == UCIVR::UCIV_6
+    }
+    #[doc = "Checks if the value of the field is `UCIV_8`"]
+    #[inline]
+    pub fn is_uciv_8(&self) -> bool {
+        *self == UCIVR::UCIV_8
+    }
+    #[doc = "Checks if the value of the field is `UCIV_10`"]
+    #[inline]
+    pub fn is_uciv_10(&self) -> bool {
+        *self == UCIVR::UCIV_10
+    }
+    #[doc = "Checks if the value of the field is `UCIV_12`"]
+    #[inline]
+    pub fn is_uciv_12(&self) -> bool {
+        *self == UCIVR::UCIV_12
+    }
+    #[doc = "Checks if the value of the field is `UCIV_14`"]
+    #[inline]
+    pub fn is_uciv_14(&self) -> bool {
+        *self == UCIVR::UCIV_14
+    }
+    #[doc = "Checks if the value of the field is `UCIV_16`"]
+    #[inline]
+    pub fn is_uciv_16(&self) -> bool {
+        *self == UCIVR::UCIV_16
+    }
+    #[doc = "Checks if the value of the field is `UCIV_18`"]
+    #[inline]
+    pub fn is_uciv_18(&self) -> bool {
+        *self == UCIVR::UCIV_18
+    }
+    #[doc = "Checks if the value of the field is `UCIV_20`"]
+    #[inline]
+    pub fn is_uciv_20(&self) -> bool {
+        *self == UCIVR::UCIV_20
+    }
+    #[doc = "Checks if the value of the field is `UCIV_22`"]
+    #[inline]
+    pub fn is_uciv_22(&self) -> bool {
+        *self == UCIVR::UCIV_22
+    }
+    #[doc = "Checks if the value of the field is `UCIV_24`"]
+    #[inline]
+    pub fn is_uciv_24(&self) -> bool {
+        *self == UCIVR::UCIV_24
+    }
+    #[doc = "Checks if the value of the field is `UCIV_26`"]
+    #[inline]
+    pub fn is_uciv_26(&self) -> bool {
+        *self == UCIVR::UCIV_26
+    }
+    #[doc = "Checks if the value of the field is `UCIV_28`"]
+    #[inline]
+    pub fn is_uciv_28(&self) -> bool {
+        *self == UCIVR::UCIV_28
+    }
+    #[doc = "Checks if the value of the field is `UCIV_30`"]
+    #[inline]
+    pub fn is_uciv_30(&self) -> bool {
+        *self == UCIVR::UCIV_30
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - eUSCI_B interrupt vector value"]
+    #[inline]
+    pub fn uciv(&self) -> UCIVR {
+        UCIVR::_from({
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b0/ucbx_rxbuf.rs b/example-source/msp432p401r/src/eusci_b0/ucbx_rxbuf.rs
new file mode 100644
index 0000000..74a7dd6
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b0/ucbx_rxbuf.rs
@@ -0,0 +1,41 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::UCBXRXBUF {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCRXBUFR {
+    bits: u8,
+}
+impl UCRXBUFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Receive data buffer"]
+    #[inline]
+    pub fn ucrxbuf(&self) -> UCRXBUFR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCRXBUFR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b0/ucbx_statw.rs b/example-source/msp432p401r/src/eusci_b0/ucbx_statw.rs
new file mode 100644
index 0000000..9f71700
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b0/ucbx_statw.rs
@@ -0,0 +1,253 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXSTATW {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCBBUSY`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBBUSYR {
+    #[doc = "Bus inactive"]
+    UCBBUSY_0,
+    #[doc = "Bus busy"]
+    UCBBUSY_1,
+}
+impl UCBBUSYR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBBUSYR::UCBBUSY_0 => false,
+            UCBBUSYR::UCBBUSY_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBBUSYR {
+        match value {
+            false => UCBBUSYR::UCBBUSY_0,
+            true => UCBBUSYR::UCBBUSY_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBBUSY_0`"]
+    #[inline]
+    pub fn is_ucbbusy_0(&self) -> bool {
+        *self == UCBBUSYR::UCBBUSY_0
+    }
+    #[doc = "Checks if the value of the field is `UCBBUSY_1`"]
+    #[inline]
+    pub fn is_ucbbusy_1(&self) -> bool {
+        *self == UCBBUSYR::UCBBUSY_1
+    }
+}
+#[doc = "Possible values of the field `UCGC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCGCR {
+    #[doc = "No general call address received"]
+    UCGC_0,
+    #[doc = "General call address received"]
+    UCGC_1,
+}
+impl UCGCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCGCR::UCGC_0 => false,
+            UCGCR::UCGC_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCGCR {
+        match value {
+            false => UCGCR::UCGC_0,
+            true => UCGCR::UCGC_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCGC_0`"]
+    #[inline]
+    pub fn is_ucgc_0(&self) -> bool {
+        *self == UCGCR::UCGC_0
+    }
+    #[doc = "Checks if the value of the field is `UCGC_1`"]
+    #[inline]
+    pub fn is_ucgc_1(&self) -> bool {
+        *self == UCGCR::UCGC_1
+    }
+}
+#[doc = "Possible values of the field `UCSCLLOW`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSCLLOWR {
+    #[doc = "SCL is not held low"]
+    UCSCLLOW_0,
+    #[doc = "SCL is held low"]
+    UCSCLLOW_1,
+}
+impl UCSCLLOWR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSCLLOWR::UCSCLLOW_0 => false,
+            UCSCLLOWR::UCSCLLOW_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSCLLOWR {
+        match value {
+            false => UCSCLLOWR::UCSCLLOW_0,
+            true => UCSCLLOWR::UCSCLLOW_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSCLLOW_0`"]
+    #[inline]
+    pub fn is_ucscllow_0(&self) -> bool {
+        *self == UCSCLLOWR::UCSCLLOW_0
+    }
+    #[doc = "Checks if the value of the field is `UCSCLLOW_1`"]
+    #[inline]
+    pub fn is_ucscllow_1(&self) -> bool {
+        *self == UCSCLLOWR::UCSCLLOW_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCBCNTR {
+    bits: u8,
+}
+impl UCBCNTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 4 - Bus busy"]
+    #[inline]
+    pub fn ucbbusy(&self) -> UCBBUSYR {
+        UCBBUSYR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - General call address received"]
+    #[inline]
+    pub fn ucgc(&self) -> UCGCR {
+        UCGCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 6 - SCL low"]
+    #[inline]
+    pub fn ucscllow(&self) -> UCSCLLOWR {
+        UCSCLLOWR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 8:15 - Hardware byte counter value"]
+    #[inline]
+    pub fn ucbcnt(&self) -> UCBCNTR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCBCNTR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b0/ucbx_tbcnt.rs b/example-source/msp432p401r/src/eusci_b0/ucbx_tbcnt.rs
new file mode 100644
index 0000000..52ef844
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b0/ucbx_tbcnt.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXTBCNT {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCTBCNTR {
+    bits: u8,
+}
+impl UCTBCNTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTBCNTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTBCNTW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Byte counter threshold value"]
+    #[inline]
+    pub fn uctbcnt(&self) -> UCTBCNTR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCTBCNTR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Byte counter threshold value"]
+    #[inline]
+    pub fn uctbcnt(&mut self) -> _UCTBCNTW {
+        _UCTBCNTW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b0/ucbx_txbuf.rs b/example-source/msp432p401r/src/eusci_b0/ucbx_txbuf.rs
new file mode 100644
index 0000000..2b787f2
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b0/ucbx_txbuf.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXTXBUF {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCTXBUFR {
+    bits: u8,
+}
+impl UCTXBUFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXBUFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXBUFW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Transmit data buffer"]
+    #[inline]
+    pub fn uctxbuf(&self) -> UCTXBUFR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCTXBUFR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Transmit data buffer"]
+    #[inline]
+    pub fn uctxbuf(&mut self) -> _UCTXBUFW {
+        _UCTXBUFW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b1.rs b/example-source/msp432p401r/src/eusci_b1.rs
new file mode 100644
index 0000000..e897801
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b1.rs
@@ -0,0 +1,143 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - eUSCI_Bx Control Word Register 0"]
+    pub ucbx_ctlw0: UCBXCTLW0,
+    #[doc = "0x02 - eUSCI_Bx Control Word Register 1"]
+    pub ucbx_ctlw1: UCBXCTLW1,
+    _reserved0: [u8; 2usize],
+    #[doc = "0x06 - eUSCI_Bx Baud Rate Control Word Register"]
+    pub ucbx_brw: UCBXBRW,
+    #[doc = "0x08 - eUSCI_Bx Status Register"]
+    pub ucbx_statw: UCBXSTATW,
+    #[doc = "0x0a - eUSCI_Bx Byte Counter Threshold Register"]
+    pub ucbx_tbcnt: UCBXTBCNT,
+    #[doc = "0x0c - eUSCI_Bx Receive Buffer Register"]
+    pub ucbx_rxbuf: UCBXRXBUF,
+    #[doc = "0x0e - eUSCI_Bx Transmit Buffer Register"]
+    pub ucbx_txbuf: UCBXTXBUF,
+    _reserved1: [u8; 4usize],
+    #[doc = "0x14 - eUSCI_Bx I2C Own Address 0 Register"]
+    pub ucbx_i2coa0: UCBXI2COA0,
+    #[doc = "0x16 - eUSCI_Bx I2C Own Address 1 Register"]
+    pub ucbx_i2coa1: UCBXI2COA1,
+    #[doc = "0x18 - eUSCI_Bx I2C Own Address 2 Register"]
+    pub ucbx_i2coa2: UCBXI2COA2,
+    #[doc = "0x1a - eUSCI_Bx I2C Own Address 3 Register"]
+    pub ucbx_i2coa3: UCBXI2COA3,
+    #[doc = "0x1c - eUSCI_Bx I2C Received Address Register"]
+    pub ucbx_addrx: UCBXADDRX,
+    #[doc = "0x1e - eUSCI_Bx I2C Address Mask Register"]
+    pub ucbx_addmask: UCBXADDMASK,
+    #[doc = "0x20 - eUSCI_Bx I2C Slave Address Register"]
+    pub ucbx_i2csa: UCBXI2CSA,
+    _reserved2: [u8; 8usize],
+    #[doc = "0x2a - eUSCI_Bx Interrupt Enable Register"]
+    pub ucbx_ie: UCBXIE,
+    #[doc = "0x2c - eUSCI_Bx Interrupt Flag Register"]
+    pub ucbx_ifg: UCBXIFG,
+    #[doc = "0x2e - eUSCI_Bx Interrupt Vector Register"]
+    pub ucbx_iv: UCBXIV,
+}
+#[doc = "eUSCI_Bx Control Word Register 0"]
+pub struct UCBXCTLW0 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Control Word Register 0"]
+pub mod ucbx_ctlw0;
+#[doc = "eUSCI_Bx Control Word Register 1"]
+pub struct UCBXCTLW1 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Control Word Register 1"]
+pub mod ucbx_ctlw1;
+#[doc = "eUSCI_Bx Baud Rate Control Word Register"]
+pub struct UCBXBRW {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Baud Rate Control Word Register"]
+pub mod ucbx_brw;
+#[doc = "eUSCI_Bx Status Register"]
+pub struct UCBXSTATW {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Status Register"]
+pub mod ucbx_statw;
+#[doc = "eUSCI_Bx Byte Counter Threshold Register"]
+pub struct UCBXTBCNT {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Byte Counter Threshold Register"]
+pub mod ucbx_tbcnt;
+#[doc = "eUSCI_Bx Receive Buffer Register"]
+pub struct UCBXRXBUF {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Receive Buffer Register"]
+pub mod ucbx_rxbuf;
+#[doc = "eUSCI_Bx Transmit Buffer Register"]
+pub struct UCBXTXBUF {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Transmit Buffer Register"]
+pub mod ucbx_txbuf;
+#[doc = "eUSCI_Bx I2C Own Address 0 Register"]
+pub struct UCBXI2COA0 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx I2C Own Address 0 Register"]
+pub mod ucbx_i2coa0;
+#[doc = "eUSCI_Bx I2C Own Address 1 Register"]
+pub struct UCBXI2COA1 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx I2C Own Address 1 Register"]
+pub mod ucbx_i2coa1;
+#[doc = "eUSCI_Bx I2C Own Address 2 Register"]
+pub struct UCBXI2COA2 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx I2C Own Address 2 Register"]
+pub mod ucbx_i2coa2;
+#[doc = "eUSCI_Bx I2C Own Address 3 Register"]
+pub struct UCBXI2COA3 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx I2C Own Address 3 Register"]
+pub mod ucbx_i2coa3;
+#[doc = "eUSCI_Bx I2C Received Address Register"]
+pub struct UCBXADDRX {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx I2C Received Address Register"]
+pub mod ucbx_addrx;
+#[doc = "eUSCI_Bx I2C Address Mask Register"]
+pub struct UCBXADDMASK {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx I2C Address Mask Register"]
+pub mod ucbx_addmask;
+#[doc = "eUSCI_Bx I2C Slave Address Register"]
+pub struct UCBXI2CSA {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx I2C Slave Address Register"]
+pub mod ucbx_i2csa;
+#[doc = "eUSCI_Bx Interrupt Enable Register"]
+pub struct UCBXIE {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Interrupt Enable Register"]
+pub mod ucbx_ie;
+#[doc = "eUSCI_Bx Interrupt Flag Register"]
+pub struct UCBXIFG {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Interrupt Flag Register"]
+pub mod ucbx_ifg;
+#[doc = "eUSCI_Bx Interrupt Vector Register"]
+pub struct UCBXIV {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Interrupt Vector Register"]
+pub mod ucbx_iv;
diff --git a/example-source/msp432p401r/src/eusci_b1/ucbx_addmask.rs b/example-source/msp432p401r/src/eusci_b1/ucbx_addmask.rs
new file mode 100644
index 0000000..856e7a6
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b1/ucbx_addmask.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXADDMASK {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ADDMASKR {
+    bits: u16,
+}
+impl ADDMASKR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADDMASKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADDMASKW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated. Modify only when UCSWRST = 1."]
+    #[inline]
+    pub fn addmask(&self) -> ADDMASKR {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        ADDMASKR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 1023 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:9 - Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated. Modify only when UCSWRST = 1."]
+    #[inline]
+    pub fn addmask(&mut self) -> _ADDMASKW {
+        _ADDMASKW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b1/ucbx_addrx.rs b/example-source/msp432p401r/src/eusci_b1/ucbx_addrx.rs
new file mode 100644
index 0000000..595f1cb
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b1/ucbx_addrx.rs
@@ -0,0 +1,41 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::UCBXADDRX {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ADDRXR {
+    bits: u16,
+}
+impl ADDRXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - Received Address Register"]
+    #[inline]
+    pub fn addrx(&self) -> ADDRXR {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        ADDRXR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b1/ucbx_brw.rs b/example-source/msp432p401r/src/eusci_b1/ucbx_brw.rs
new file mode 100644
index 0000000..1ed885e
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b1/ucbx_brw.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXBRW {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCBRR {
+    bits: u16,
+}
+impl UCBRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBRW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Bit clock prescaler"]
+    #[inline]
+    pub fn ucbr(&self) -> UCBRR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        UCBRR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Bit clock prescaler"]
+    #[inline]
+    pub fn ucbr(&mut self) -> _UCBRW {
+        _UCBRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b1/ucbx_ctlw0.rs b/example-source/msp432p401r/src/eusci_b1/ucbx_ctlw0.rs
new file mode 100644
index 0000000..4baf4f9
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b1/ucbx_ctlw0.rs
@@ -0,0 +1,1645 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXCTLW0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCSWRST`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSWRSTR {
+    #[doc = "Disabled. eUSCI_B reset released for operation"]
+    UCSWRST_0,
+    #[doc = "Enabled. eUSCI_B logic held in reset state"]
+    UCSWRST_1,
+}
+impl UCSWRSTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSWRSTR::UCSWRST_0 => false,
+            UCSWRSTR::UCSWRST_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSWRSTR {
+        match value {
+            false => UCSWRSTR::UCSWRST_0,
+            true => UCSWRSTR::UCSWRST_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSWRST_0`"]
+    #[inline]
+    pub fn is_ucswrst_0(&self) -> bool {
+        *self == UCSWRSTR::UCSWRST_0
+    }
+    #[doc = "Checks if the value of the field is `UCSWRST_1`"]
+    #[inline]
+    pub fn is_ucswrst_1(&self) -> bool {
+        *self == UCSWRSTR::UCSWRST_1
+    }
+}
+#[doc = "Possible values of the field `UCTXSTT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXSTTR {
+    #[doc = "Do not generate START condition"]
+    UCTXSTT_0,
+    #[doc = "Generate START condition"]
+    UCTXSTT_1,
+}
+impl UCTXSTTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXSTTR::UCTXSTT_0 => false,
+            UCTXSTTR::UCTXSTT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXSTTR {
+        match value {
+            false => UCTXSTTR::UCTXSTT_0,
+            true => UCTXSTTR::UCTXSTT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXSTT_0`"]
+    #[inline]
+    pub fn is_uctxstt_0(&self) -> bool {
+        *self == UCTXSTTR::UCTXSTT_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXSTT_1`"]
+    #[inline]
+    pub fn is_uctxstt_1(&self) -> bool {
+        *self == UCTXSTTR::UCTXSTT_1
+    }
+}
+#[doc = "Possible values of the field `UCTXSTP`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXSTPR {
+    #[doc = "No STOP generated"]
+    UCTXSTP_0,
+    #[doc = "Generate STOP"]
+    UCTXSTP_1,
+}
+impl UCTXSTPR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXSTPR::UCTXSTP_0 => false,
+            UCTXSTPR::UCTXSTP_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXSTPR {
+        match value {
+            false => UCTXSTPR::UCTXSTP_0,
+            true => UCTXSTPR::UCTXSTP_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXSTP_0`"]
+    #[inline]
+    pub fn is_uctxstp_0(&self) -> bool {
+        *self == UCTXSTPR::UCTXSTP_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXSTP_1`"]
+    #[inline]
+    pub fn is_uctxstp_1(&self) -> bool {
+        *self == UCTXSTPR::UCTXSTP_1
+    }
+}
+#[doc = "Possible values of the field `UCTXNACK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXNACKR {
+    #[doc = "Acknowledge normally"]
+    UCTXNACK_0,
+    #[doc = "Generate NACK"]
+    UCTXNACK_1,
+}
+impl UCTXNACKR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXNACKR::UCTXNACK_0 => false,
+            UCTXNACKR::UCTXNACK_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXNACKR {
+        match value {
+            false => UCTXNACKR::UCTXNACK_0,
+            true => UCTXNACKR::UCTXNACK_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXNACK_0`"]
+    #[inline]
+    pub fn is_uctxnack_0(&self) -> bool {
+        *self == UCTXNACKR::UCTXNACK_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXNACK_1`"]
+    #[inline]
+    pub fn is_uctxnack_1(&self) -> bool {
+        *self == UCTXNACKR::UCTXNACK_1
+    }
+}
+#[doc = "Possible values of the field `UCTR`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTRR {
+    #[doc = "Receiver"]
+    UCTR_0,
+    #[doc = "Transmitter"]
+    UCTR_1,
+}
+impl UCTRR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTRR::UCTR_0 => false,
+            UCTRR::UCTR_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTRR {
+        match value {
+            false => UCTRR::UCTR_0,
+            true => UCTRR::UCTR_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTR_0`"]
+    #[inline]
+    pub fn is_uctr_0(&self) -> bool {
+        *self == UCTRR::UCTR_0
+    }
+    #[doc = "Checks if the value of the field is `UCTR_1`"]
+    #[inline]
+    pub fn is_uctr_1(&self) -> bool {
+        *self == UCTRR::UCTR_1
+    }
+}
+#[doc = "Possible values of the field `UCTXACK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXACKR {
+    #[doc = "Do not acknowledge the slave address"]
+    UCTXACK_0,
+    #[doc = "Acknowledge the slave address"]
+    UCTXACK_1,
+}
+impl UCTXACKR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXACKR::UCTXACK_0 => false,
+            UCTXACKR::UCTXACK_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXACKR {
+        match value {
+            false => UCTXACKR::UCTXACK_0,
+            true => UCTXACKR::UCTXACK_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXACK_0`"]
+    #[inline]
+    pub fn is_uctxack_0(&self) -> bool {
+        *self == UCTXACKR::UCTXACK_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXACK_1`"]
+    #[inline]
+    pub fn is_uctxack_1(&self) -> bool {
+        *self == UCTXACKR::UCTXACK_1
+    }
+}
+#[doc = "Possible values of the field `UCSSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSSELR {
+    #[doc = "UCLKI"]
+    UCSSEL_0,
+    #[doc = "ACLK"]
+    UCSSEL_1,
+    #[doc = "SMCLK"]
+    UCSSEL_2,
+    #[doc = "SMCLK"]
+    UCSSEL_3,
+}
+impl UCSSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCSSELR::UCSSEL_0 => 0,
+            UCSSELR::UCSSEL_1 => 1,
+            UCSSELR::UCSSEL_2 => 2,
+            UCSSELR::UCSSEL_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCSSELR {
+        match value {
+            0 => UCSSELR::UCSSEL_0,
+            1 => UCSSELR::UCSSEL_1,
+            2 => UCSSELR::UCSSEL_2,
+            3 => UCSSELR::UCSSEL_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSSEL_0`"]
+    #[inline]
+    pub fn is_ucssel_0(&self) -> bool {
+        *self == UCSSELR::UCSSEL_0
+    }
+    #[doc = "Checks if the value of the field is `UCSSEL_1`"]
+    #[inline]
+    pub fn is_ucssel_1(&self) -> bool {
+        *self == UCSSELR::UCSSEL_1
+    }
+    #[doc = "Checks if the value of the field is `UCSSEL_2`"]
+    #[inline]
+    pub fn is_ucssel_2(&self) -> bool {
+        *self == UCSSELR::UCSSEL_2
+    }
+    #[doc = "Checks if the value of the field is `UCSSEL_3`"]
+    #[inline]
+    pub fn is_ucssel_3(&self) -> bool {
+        *self == UCSSELR::UCSSEL_3
+    }
+}
+#[doc = "Possible values of the field `UCSYNC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSYNCR {
+    #[doc = "Asynchronous mode"]
+    UCSYNC_0,
+    #[doc = "Synchronous mode"]
+    UCSYNC_1,
+}
+impl UCSYNCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSYNCR::UCSYNC_0 => false,
+            UCSYNCR::UCSYNC_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSYNCR {
+        match value {
+            false => UCSYNCR::UCSYNC_0,
+            true => UCSYNCR::UCSYNC_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSYNC_0`"]
+    #[inline]
+    pub fn is_ucsync_0(&self) -> bool {
+        *self == UCSYNCR::UCSYNC_0
+    }
+    #[doc = "Checks if the value of the field is `UCSYNC_1`"]
+    #[inline]
+    pub fn is_ucsync_1(&self) -> bool {
+        *self == UCSYNCR::UCSYNC_1
+    }
+}
+#[doc = "Possible values of the field `UCMODE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCMODER {
+    #[doc = "3-pin SPI"]
+    UCMODE_0,
+    #[doc = "4-pin SPI (master or slave enabled if STE = 1)"]
+    UCMODE_1,
+    #[doc = "4-pin SPI (master or slave enabled if STE = 0)"]
+    UCMODE_2,
+    #[doc = "I2C mode"]
+    UCMODE_3,
+}
+impl UCMODER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCMODER::UCMODE_0 => 0,
+            UCMODER::UCMODE_1 => 1,
+            UCMODER::UCMODE_2 => 2,
+            UCMODER::UCMODE_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCMODER {
+        match value {
+            0 => UCMODER::UCMODE_0,
+            1 => UCMODER::UCMODE_1,
+            2 => UCMODER::UCMODE_2,
+            3 => UCMODER::UCMODE_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_0`"]
+    #[inline]
+    pub fn is_ucmode_0(&self) -> bool {
+        *self == UCMODER::UCMODE_0
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_1`"]
+    #[inline]
+    pub fn is_ucmode_1(&self) -> bool {
+        *self == UCMODER::UCMODE_1
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_2`"]
+    #[inline]
+    pub fn is_ucmode_2(&self) -> bool {
+        *self == UCMODER::UCMODE_2
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_3`"]
+    #[inline]
+    pub fn is_ucmode_3(&self) -> bool {
+        *self == UCMODER::UCMODE_3
+    }
+}
+#[doc = "Possible values of the field `UCMST`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCMSTR {
+    #[doc = "Slave mode"]
+    UCMST_0,
+    #[doc = "Master mode"]
+    UCMST_1,
+}
+impl UCMSTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCMSTR::UCMST_0 => false,
+            UCMSTR::UCMST_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCMSTR {
+        match value {
+            false => UCMSTR::UCMST_0,
+            true => UCMSTR::UCMST_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCMST_0`"]
+    #[inline]
+    pub fn is_ucmst_0(&self) -> bool {
+        *self == UCMSTR::UCMST_0
+    }
+    #[doc = "Checks if the value of the field is `UCMST_1`"]
+    #[inline]
+    pub fn is_ucmst_1(&self) -> bool {
+        *self == UCMSTR::UCMST_1
+    }
+}
+#[doc = "Possible values of the field `UCMM`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCMMR {
+    #[doc = "Single master environment. There is no other master in the system. The address compare unit is disabled."]
+    UCMM_0,
+    #[doc = "Multi-master environment"]
+    UCMM_1,
+}
+impl UCMMR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCMMR::UCMM_0 => false,
+            UCMMR::UCMM_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCMMR {
+        match value {
+            false => UCMMR::UCMM_0,
+            true => UCMMR::UCMM_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCMM_0`"]
+    #[inline]
+    pub fn is_ucmm_0(&self) -> bool {
+        *self == UCMMR::UCMM_0
+    }
+    #[doc = "Checks if the value of the field is `UCMM_1`"]
+    #[inline]
+    pub fn is_ucmm_1(&self) -> bool {
+        *self == UCMMR::UCMM_1
+    }
+}
+#[doc = "Possible values of the field `UCSLA10`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSLA10R {
+    #[doc = "Address slave with 7-bit address"]
+    UCSLA10_0,
+    #[doc = "Address slave with 10-bit address"]
+    UCSLA10_1,
+}
+impl UCSLA10R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSLA10R::UCSLA10_0 => false,
+            UCSLA10R::UCSLA10_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSLA10R {
+        match value {
+            false => UCSLA10R::UCSLA10_0,
+            true => UCSLA10R::UCSLA10_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSLA10_0`"]
+    #[inline]
+    pub fn is_ucsla10_0(&self) -> bool {
+        *self == UCSLA10R::UCSLA10_0
+    }
+    #[doc = "Checks if the value of the field is `UCSLA10_1`"]
+    #[inline]
+    pub fn is_ucsla10_1(&self) -> bool {
+        *self == UCSLA10R::UCSLA10_1
+    }
+}
+#[doc = "Possible values of the field `UCA10`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCA10R {
+    #[doc = "Own address is a 7-bit address"]
+    UCA10_0,
+    #[doc = "Own address is a 10-bit address"]
+    UCA10_1,
+}
+impl UCA10R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCA10R::UCA10_0 => false,
+            UCA10R::UCA10_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCA10R {
+        match value {
+            false => UCA10R::UCA10_0,
+            true => UCA10R::UCA10_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCA10_0`"]
+    #[inline]
+    pub fn is_uca10_0(&self) -> bool {
+        *self == UCA10R::UCA10_0
+    }
+    #[doc = "Checks if the value of the field is `UCA10_1`"]
+    #[inline]
+    pub fn is_uca10_1(&self) -> bool {
+        *self == UCA10R::UCA10_1
+    }
+}
+#[doc = "Values that can be written to the field `UCSWRST`"]
+pub enum UCSWRSTW {
+    #[doc = "Disabled. eUSCI_B reset released for operation"]
+    UCSWRST_0,
+    #[doc = "Enabled. eUSCI_B logic held in reset state"]
+    UCSWRST_1,
+}
+impl UCSWRSTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSWRSTW::UCSWRST_0 => false,
+            UCSWRSTW::UCSWRST_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSWRSTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSWRSTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSWRSTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disabled. eUSCI_B reset released for operation"]
+    #[inline]
+    pub fn ucswrst_0(self) -> &'a mut W {
+        self.variant(UCSWRSTW::UCSWRST_0)
+    }
+    #[doc = "Enabled. eUSCI_B logic held in reset state"]
+    #[inline]
+    pub fn ucswrst_1(self) -> &'a mut W {
+        self.variant(UCSWRSTW::UCSWRST_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXSTT`"]
+pub enum UCTXSTTW {
+    #[doc = "Do not generate START condition"]
+    UCTXSTT_0,
+    #[doc = "Generate START condition"]
+    UCTXSTT_1,
+}
+impl UCTXSTTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXSTTW::UCTXSTT_0 => false,
+            UCTXSTTW::UCTXSTT_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXSTTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXSTTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXSTTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Do not generate START condition"]
+    #[inline]
+    pub fn uctxstt_0(self) -> &'a mut W {
+        self.variant(UCTXSTTW::UCTXSTT_0)
+    }
+    #[doc = "Generate START condition"]
+    #[inline]
+    pub fn uctxstt_1(self) -> &'a mut W {
+        self.variant(UCTXSTTW::UCTXSTT_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXSTP`"]
+pub enum UCTXSTPW {
+    #[doc = "No STOP generated"]
+    UCTXSTP_0,
+    #[doc = "Generate STOP"]
+    UCTXSTP_1,
+}
+impl UCTXSTPW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXSTPW::UCTXSTP_0 => false,
+            UCTXSTPW::UCTXSTP_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXSTPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXSTPW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXSTPW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No STOP generated"]
+    #[inline]
+    pub fn uctxstp_0(self) -> &'a mut W {
+        self.variant(UCTXSTPW::UCTXSTP_0)
+    }
+    #[doc = "Generate STOP"]
+    #[inline]
+    pub fn uctxstp_1(self) -> &'a mut W {
+        self.variant(UCTXSTPW::UCTXSTP_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXNACK`"]
+pub enum UCTXNACKW {
+    #[doc = "Acknowledge normally"]
+    UCTXNACK_0,
+    #[doc = "Generate NACK"]
+    UCTXNACK_1,
+}
+impl UCTXNACKW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXNACKW::UCTXNACK_0 => false,
+            UCTXNACKW::UCTXNACK_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXNACKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXNACKW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXNACKW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Acknowledge normally"]
+    #[inline]
+    pub fn uctxnack_0(self) -> &'a mut W {
+        self.variant(UCTXNACKW::UCTXNACK_0)
+    }
+    #[doc = "Generate NACK"]
+    #[inline]
+    pub fn uctxnack_1(self) -> &'a mut W {
+        self.variant(UCTXNACKW::UCTXNACK_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTR`"]
+pub enum UCTRW {
+    #[doc = "Receiver"]
+    UCTR_0,
+    #[doc = "Transmitter"]
+    UCTR_1,
+}
+impl UCTRW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTRW::UCTR_0 => false,
+            UCTRW::UCTR_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTRW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTRW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Receiver"]
+    #[inline]
+    pub fn uctr_0(self) -> &'a mut W {
+        self.variant(UCTRW::UCTR_0)
+    }
+    #[doc = "Transmitter"]
+    #[inline]
+    pub fn uctr_1(self) -> &'a mut W {
+        self.variant(UCTRW::UCTR_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXACK`"]
+pub enum UCTXACKW {
+    #[doc = "Do not acknowledge the slave address"]
+    UCTXACK_0,
+    #[doc = "Acknowledge the slave address"]
+    UCTXACK_1,
+}
+impl UCTXACKW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXACKW::UCTXACK_0 => false,
+            UCTXACKW::UCTXACK_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXACKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXACKW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXACKW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Do not acknowledge the slave address"]
+    #[inline]
+    pub fn uctxack_0(self) -> &'a mut W {
+        self.variant(UCTXACKW::UCTXACK_0)
+    }
+    #[doc = "Acknowledge the slave address"]
+    #[inline]
+    pub fn uctxack_1(self) -> &'a mut W {
+        self.variant(UCTXACKW::UCTXACK_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSSEL`"]
+pub enum UCSSELW {
+    #[doc = "UCLKI"]
+    UCSSEL_0,
+    #[doc = "ACLK"]
+    UCSSEL_1,
+    #[doc = "SMCLK"]
+    UCSSEL_2,
+    #[doc = "SMCLK"]
+    UCSSEL_3,
+}
+impl UCSSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCSSELW::UCSSEL_0 => 0,
+            UCSSELW::UCSSEL_1 => 1,
+            UCSSELW::UCSSEL_2 => 2,
+            UCSSELW::UCSSEL_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSSELW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "UCLKI"]
+    #[inline]
+    pub fn ucssel_0(self) -> &'a mut W {
+        self.variant(UCSSELW::UCSSEL_0)
+    }
+    #[doc = "ACLK"]
+    #[inline]
+    pub fn ucssel_1(self) -> &'a mut W {
+        self.variant(UCSSELW::UCSSEL_1)
+    }
+    #[doc = "SMCLK"]
+    #[inline]
+    pub fn ucssel_2(self) -> &'a mut W {
+        self.variant(UCSSELW::UCSSEL_2)
+    }
+    #[doc = "SMCLK"]
+    #[inline]
+    pub fn ucssel_3(self) -> &'a mut W {
+        self.variant(UCSSELW::UCSSEL_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSYNC`"]
+pub enum UCSYNCW {
+    #[doc = "Asynchronous mode"]
+    UCSYNC_0,
+    #[doc = "Synchronous mode"]
+    UCSYNC_1,
+}
+impl UCSYNCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSYNCW::UCSYNC_0 => false,
+            UCSYNCW::UCSYNC_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSYNCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSYNCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSYNCW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Asynchronous mode"]
+    #[inline]
+    pub fn ucsync_0(self) -> &'a mut W {
+        self.variant(UCSYNCW::UCSYNC_0)
+    }
+    #[doc = "Synchronous mode"]
+    #[inline]
+    pub fn ucsync_1(self) -> &'a mut W {
+        self.variant(UCSYNCW::UCSYNC_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCMODE`"]
+pub enum UCMODEW {
+    #[doc = "3-pin SPI"]
+    UCMODE_0,
+    #[doc = "4-pin SPI (master or slave enabled if STE = 1)"]
+    UCMODE_1,
+    #[doc = "4-pin SPI (master or slave enabled if STE = 0)"]
+    UCMODE_2,
+    #[doc = "I2C mode"]
+    UCMODE_3,
+}
+impl UCMODEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCMODEW::UCMODE_0 => 0,
+            UCMODEW::UCMODE_1 => 1,
+            UCMODEW::UCMODE_2 => 2,
+            UCMODEW::UCMODE_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCMODEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCMODEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCMODEW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "3-pin SPI"]
+    #[inline]
+    pub fn ucmode_0(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_0)
+    }
+    #[doc = "4-pin SPI (master or slave enabled if STE = 1)"]
+    #[inline]
+    pub fn ucmode_1(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_1)
+    }
+    #[doc = "4-pin SPI (master or slave enabled if STE = 0)"]
+    #[inline]
+    pub fn ucmode_2(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_2)
+    }
+    #[doc = "I2C mode"]
+    #[inline]
+    pub fn ucmode_3(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCMST`"]
+pub enum UCMSTW {
+    #[doc = "Slave mode"]
+    UCMST_0,
+    #[doc = "Master mode"]
+    UCMST_1,
+}
+impl UCMSTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCMSTW::UCMST_0 => false,
+            UCMSTW::UCMST_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCMSTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCMSTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCMSTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Slave mode"]
+    #[inline]
+    pub fn ucmst_0(self) -> &'a mut W {
+        self.variant(UCMSTW::UCMST_0)
+    }
+    #[doc = "Master mode"]
+    #[inline]
+    pub fn ucmst_1(self) -> &'a mut W {
+        self.variant(UCMSTW::UCMST_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCMM`"]
+pub enum UCMMW {
+    #[doc = "Single master environment. There is no other master in the system. The address compare unit is disabled."]
+    UCMM_0,
+    #[doc = "Multi-master environment"]
+    UCMM_1,
+}
+impl UCMMW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCMMW::UCMM_0 => false,
+            UCMMW::UCMM_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCMMW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCMMW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCMMW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Single master environment. There is no other master in the system. The address compare unit is disabled."]
+    #[inline]
+    pub fn ucmm_0(self) -> &'a mut W {
+        self.variant(UCMMW::UCMM_0)
+    }
+    #[doc = "Multi-master environment"]
+    #[inline]
+    pub fn ucmm_1(self) -> &'a mut W {
+        self.variant(UCMMW::UCMM_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSLA10`"]
+pub enum UCSLA10W {
+    #[doc = "Address slave with 7-bit address"]
+    UCSLA10_0,
+    #[doc = "Address slave with 10-bit address"]
+    UCSLA10_1,
+}
+impl UCSLA10W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSLA10W::UCSLA10_0 => false,
+            UCSLA10W::UCSLA10_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSLA10W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSLA10W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSLA10W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Address slave with 7-bit address"]
+    #[inline]
+    pub fn ucsla10_0(self) -> &'a mut W {
+        self.variant(UCSLA10W::UCSLA10_0)
+    }
+    #[doc = "Address slave with 10-bit address"]
+    #[inline]
+    pub fn ucsla10_1(self) -> &'a mut W {
+        self.variant(UCSLA10W::UCSLA10_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCA10`"]
+pub enum UCA10W {
+    #[doc = "Own address is a 7-bit address"]
+    UCA10_0,
+    #[doc = "Own address is a 10-bit address"]
+    UCA10_1,
+}
+impl UCA10W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCA10W::UCA10_0 => false,
+            UCA10W::UCA10_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCA10W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCA10W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCA10W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Own address is a 7-bit address"]
+    #[inline]
+    pub fn uca10_0(self) -> &'a mut W {
+        self.variant(UCA10W::UCA10_0)
+    }
+    #[doc = "Own address is a 10-bit address"]
+    #[inline]
+    pub fn uca10_1(self) -> &'a mut W {
+        self.variant(UCA10W::UCA10_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Software reset enable"]
+    #[inline]
+    pub fn ucswrst(&self) -> UCSWRSTR {
+        UCSWRSTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Transmit START condition in master mode"]
+    #[inline]
+    pub fn uctxstt(&self) -> UCTXSTTR {
+        UCTXSTTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - Transmit STOP condition in master mode"]
+    #[inline]
+    pub fn uctxstp(&self) -> UCTXSTPR {
+        UCTXSTPR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Transmit a NACK"]
+    #[inline]
+    pub fn uctxnack(&self) -> UCTXNACKR {
+        UCTXNACKR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 4 - Transmitter/receiver"]
+    #[inline]
+    pub fn uctr(&self) -> UCTRR {
+        UCTRR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - Transmit ACK condition in slave mode"]
+    #[inline]
+    pub fn uctxack(&self) -> UCTXACKR {
+        UCTXACKR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 6:7 - eUSCI_B clock source select"]
+    #[inline]
+    pub fn ucssel(&self) -> UCSSELR {
+        UCSSELR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 8 - Synchronous mode enable"]
+    #[inline]
+    pub fn ucsync(&self) -> UCSYNCR {
+        UCSYNCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 9:10 - eUSCI_B mode"]
+    #[inline]
+    pub fn ucmode(&self) -> UCMODER {
+        UCMODER::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 11 - Master mode select"]
+    #[inline]
+    pub fn ucmst(&self) -> UCMSTR {
+        UCMSTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 13 - Multi-master environment select"]
+    #[inline]
+    pub fn ucmm(&self) -> UCMMR {
+        UCMMR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 14 - Slave addressing mode select"]
+    #[inline]
+    pub fn ucsla10(&self) -> UCSLA10R {
+        UCSLA10R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 15 - Own addressing mode select"]
+    #[inline]
+    pub fn uca10(&self) -> UCA10R {
+        UCA10R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 449 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Software reset enable"]
+    #[inline]
+    pub fn ucswrst(&mut self) -> _UCSWRSTW {
+        _UCSWRSTW { w: self }
+    }
+    #[doc = "Bit 1 - Transmit START condition in master mode"]
+    #[inline]
+    pub fn uctxstt(&mut self) -> _UCTXSTTW {
+        _UCTXSTTW { w: self }
+    }
+    #[doc = "Bit 2 - Transmit STOP condition in master mode"]
+    #[inline]
+    pub fn uctxstp(&mut self) -> _UCTXSTPW {
+        _UCTXSTPW { w: self }
+    }
+    #[doc = "Bit 3 - Transmit a NACK"]
+    #[inline]
+    pub fn uctxnack(&mut self) -> _UCTXNACKW {
+        _UCTXNACKW { w: self }
+    }
+    #[doc = "Bit 4 - Transmitter/receiver"]
+    #[inline]
+    pub fn uctr(&mut self) -> _UCTRW {
+        _UCTRW { w: self }
+    }
+    #[doc = "Bit 5 - Transmit ACK condition in slave mode"]
+    #[inline]
+    pub fn uctxack(&mut self) -> _UCTXACKW {
+        _UCTXACKW { w: self }
+    }
+    #[doc = "Bits 6:7 - eUSCI_B clock source select"]
+    #[inline]
+    pub fn ucssel(&mut self) -> _UCSSELW {
+        _UCSSELW { w: self }
+    }
+    #[doc = "Bit 8 - Synchronous mode enable"]
+    #[inline]
+    pub fn ucsync(&mut self) -> _UCSYNCW {
+        _UCSYNCW { w: self }
+    }
+    #[doc = "Bits 9:10 - eUSCI_B mode"]
+    #[inline]
+    pub fn ucmode(&mut self) -> _UCMODEW {
+        _UCMODEW { w: self }
+    }
+    #[doc = "Bit 11 - Master mode select"]
+    #[inline]
+    pub fn ucmst(&mut self) -> _UCMSTW {
+        _UCMSTW { w: self }
+    }
+    #[doc = "Bit 13 - Multi-master environment select"]
+    #[inline]
+    pub fn ucmm(&mut self) -> _UCMMW {
+        _UCMMW { w: self }
+    }
+    #[doc = "Bit 14 - Slave addressing mode select"]
+    #[inline]
+    pub fn ucsla10(&mut self) -> _UCSLA10W {
+        _UCSLA10W { w: self }
+    }
+    #[doc = "Bit 15 - Own addressing mode select"]
+    #[inline]
+    pub fn uca10(&mut self) -> _UCA10W {
+        _UCA10W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b1/ucbx_ctlw1.rs b/example-source/msp432p401r/src/eusci_b1/ucbx_ctlw1.rs
new file mode 100644
index 0000000..64e2d04
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b1/ucbx_ctlw1.rs
@@ -0,0 +1,813 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXCTLW1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCGLIT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCGLITR {
+    #[doc = "50 ns"]
+    UCGLIT_0,
+    #[doc = "25 ns"]
+    UCGLIT_1,
+    #[doc = "12.5 ns"]
+    UCGLIT_2,
+    #[doc = "6.25 ns"]
+    UCGLIT_3,
+}
+impl UCGLITR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCGLITR::UCGLIT_0 => 0,
+            UCGLITR::UCGLIT_1 => 1,
+            UCGLITR::UCGLIT_2 => 2,
+            UCGLITR::UCGLIT_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCGLITR {
+        match value {
+            0 => UCGLITR::UCGLIT_0,
+            1 => UCGLITR::UCGLIT_1,
+            2 => UCGLITR::UCGLIT_2,
+            3 => UCGLITR::UCGLIT_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_0`"]
+    #[inline]
+    pub fn is_ucglit_0(&self) -> bool {
+        *self == UCGLITR::UCGLIT_0
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_1`"]
+    #[inline]
+    pub fn is_ucglit_1(&self) -> bool {
+        *self == UCGLITR::UCGLIT_1
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_2`"]
+    #[inline]
+    pub fn is_ucglit_2(&self) -> bool {
+        *self == UCGLITR::UCGLIT_2
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_3`"]
+    #[inline]
+    pub fn is_ucglit_3(&self) -> bool {
+        *self == UCGLITR::UCGLIT_3
+    }
+}
+#[doc = "Possible values of the field `UCASTP`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCASTPR {
+    #[doc = "No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care."]
+    UCASTP_0,
+    #[doc = "UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT"]
+    UCASTP_1,
+    #[doc = "A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold"]
+    UCASTP_2,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl UCASTPR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCASTPR::UCASTP_0 => 0,
+            UCASTPR::UCASTP_1 => 1,
+            UCASTPR::UCASTP_2 => 2,
+            UCASTPR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCASTPR {
+        match value {
+            0 => UCASTPR::UCASTP_0,
+            1 => UCASTPR::UCASTP_1,
+            2 => UCASTPR::UCASTP_2,
+            i => UCASTPR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCASTP_0`"]
+    #[inline]
+    pub fn is_ucastp_0(&self) -> bool {
+        *self == UCASTPR::UCASTP_0
+    }
+    #[doc = "Checks if the value of the field is `UCASTP_1`"]
+    #[inline]
+    pub fn is_ucastp_1(&self) -> bool {
+        *self == UCASTPR::UCASTP_1
+    }
+    #[doc = "Checks if the value of the field is `UCASTP_2`"]
+    #[inline]
+    pub fn is_ucastp_2(&self) -> bool {
+        *self == UCASTPR::UCASTP_2
+    }
+}
+#[doc = "Possible values of the field `UCSWACK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSWACKR {
+    #[doc = "The address acknowledge of the slave is controlled by the eUSCI_B module"]
+    UCSWACK_0,
+    #[doc = "The user needs to trigger the sending of the address ACK by issuing UCTXACK"]
+    UCSWACK_1,
+}
+impl UCSWACKR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSWACKR::UCSWACK_0 => false,
+            UCSWACKR::UCSWACK_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSWACKR {
+        match value {
+            false => UCSWACKR::UCSWACK_0,
+            true => UCSWACKR::UCSWACK_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSWACK_0`"]
+    #[inline]
+    pub fn is_ucswack_0(&self) -> bool {
+        *self == UCSWACKR::UCSWACK_0
+    }
+    #[doc = "Checks if the value of the field is `UCSWACK_1`"]
+    #[inline]
+    pub fn is_ucswack_1(&self) -> bool {
+        *self == UCSWACKR::UCSWACK_1
+    }
+}
+#[doc = "Possible values of the field `UCSTPNACK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTPNACKR {
+    #[doc = "Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard)"]
+    UCSTPNACK_0,
+    #[doc = "All bytes are acknowledged by the eUSCI_B when configured as master receiver"]
+    UCSTPNACK_1,
+}
+impl UCSTPNACKR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTPNACKR::UCSTPNACK_0 => false,
+            UCSTPNACKR::UCSTPNACK_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTPNACKR {
+        match value {
+            false => UCSTPNACKR::UCSTPNACK_0,
+            true => UCSTPNACKR::UCSTPNACK_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTPNACK_0`"]
+    #[inline]
+    pub fn is_ucstpnack_0(&self) -> bool {
+        *self == UCSTPNACKR::UCSTPNACK_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTPNACK_1`"]
+    #[inline]
+    pub fn is_ucstpnack_1(&self) -> bool {
+        *self == UCSTPNACKR::UCSTPNACK_1
+    }
+}
+#[doc = "Possible values of the field `UCCLTO`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCCLTOR {
+    #[doc = "Disable clock low timeout counter"]
+    UCCLTO_0,
+    #[doc = "135 000 SYSCLK cycles (approximately 28 ms)"]
+    UCCLTO_1,
+    #[doc = "150 000 SYSCLK cycles (approximately 31 ms)"]
+    UCCLTO_2,
+    #[doc = "165 000 SYSCLK cycles (approximately 34 ms)"]
+    UCCLTO_3,
+}
+impl UCCLTOR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCCLTOR::UCCLTO_0 => 0,
+            UCCLTOR::UCCLTO_1 => 1,
+            UCCLTOR::UCCLTO_2 => 2,
+            UCCLTOR::UCCLTO_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCCLTOR {
+        match value {
+            0 => UCCLTOR::UCCLTO_0,
+            1 => UCCLTOR::UCCLTO_1,
+            2 => UCCLTOR::UCCLTO_2,
+            3 => UCCLTOR::UCCLTO_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCCLTO_0`"]
+    #[inline]
+    pub fn is_ucclto_0(&self) -> bool {
+        *self == UCCLTOR::UCCLTO_0
+    }
+    #[doc = "Checks if the value of the field is `UCCLTO_1`"]
+    #[inline]
+    pub fn is_ucclto_1(&self) -> bool {
+        *self == UCCLTOR::UCCLTO_1
+    }
+    #[doc = "Checks if the value of the field is `UCCLTO_2`"]
+    #[inline]
+    pub fn is_ucclto_2(&self) -> bool {
+        *self == UCCLTOR::UCCLTO_2
+    }
+    #[doc = "Checks if the value of the field is `UCCLTO_3`"]
+    #[inline]
+    pub fn is_ucclto_3(&self) -> bool {
+        *self == UCCLTOR::UCCLTO_3
+    }
+}
+#[doc = "Possible values of the field `UCETXINT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCETXINTR {
+    #[doc = "UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit"]
+    UCETXINT_0,
+    #[doc = "UCTXIFG0 is set for each START condition"]
+    UCETXINT_1,
+}
+impl UCETXINTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCETXINTR::UCETXINT_0 => false,
+            UCETXINTR::UCETXINT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCETXINTR {
+        match value {
+            false => UCETXINTR::UCETXINT_0,
+            true => UCETXINTR::UCETXINT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCETXINT_0`"]
+    #[inline]
+    pub fn is_ucetxint_0(&self) -> bool {
+        *self == UCETXINTR::UCETXINT_0
+    }
+    #[doc = "Checks if the value of the field is `UCETXINT_1`"]
+    #[inline]
+    pub fn is_ucetxint_1(&self) -> bool {
+        *self == UCETXINTR::UCETXINT_1
+    }
+}
+#[doc = "Values that can be written to the field `UCGLIT`"]
+pub enum UCGLITW {
+    #[doc = "50 ns"]
+    UCGLIT_0,
+    #[doc = "25 ns"]
+    UCGLIT_1,
+    #[doc = "12.5 ns"]
+    UCGLIT_2,
+    #[doc = "6.25 ns"]
+    UCGLIT_3,
+}
+impl UCGLITW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCGLITW::UCGLIT_0 => 0,
+            UCGLITW::UCGLIT_1 => 1,
+            UCGLITW::UCGLIT_2 => 2,
+            UCGLITW::UCGLIT_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCGLITW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCGLITW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCGLITW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "50 ns"]
+    #[inline]
+    pub fn ucglit_0(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_0)
+    }
+    #[doc = "25 ns"]
+    #[inline]
+    pub fn ucglit_1(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_1)
+    }
+    #[doc = "12.5 ns"]
+    #[inline]
+    pub fn ucglit_2(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_2)
+    }
+    #[doc = "6.25 ns"]
+    #[inline]
+    pub fn ucglit_3(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCASTP`"]
+pub enum UCASTPW {
+    #[doc = "No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care."]
+    UCASTP_0,
+    #[doc = "UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT"]
+    UCASTP_1,
+    #[doc = "A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold"]
+    UCASTP_2,
+}
+impl UCASTPW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCASTPW::UCASTP_0 => 0,
+            UCASTPW::UCASTP_1 => 1,
+            UCASTPW::UCASTP_2 => 2,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCASTPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCASTPW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCASTPW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care."]
+    #[inline]
+    pub fn ucastp_0(self) -> &'a mut W {
+        self.variant(UCASTPW::UCASTP_0)
+    }
+    #[doc = "UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT"]
+    #[inline]
+    pub fn ucastp_1(self) -> &'a mut W {
+        self.variant(UCASTPW::UCASTP_1)
+    }
+    #[doc = "A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold"]
+    #[inline]
+    pub fn ucastp_2(self) -> &'a mut W {
+        self.variant(UCASTPW::UCASTP_2)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSWACK`"]
+pub enum UCSWACKW {
+    #[doc = "The address acknowledge of the slave is controlled by the eUSCI_B module"]
+    UCSWACK_0,
+    #[doc = "The user needs to trigger the sending of the address ACK by issuing UCTXACK"]
+    UCSWACK_1,
+}
+impl UCSWACKW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSWACKW::UCSWACK_0 => false,
+            UCSWACKW::UCSWACK_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSWACKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSWACKW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSWACKW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The address acknowledge of the slave is controlled by the eUSCI_B module"]
+    #[inline]
+    pub fn ucswack_0(self) -> &'a mut W {
+        self.variant(UCSWACKW::UCSWACK_0)
+    }
+    #[doc = "The user needs to trigger the sending of the address ACK by issuing UCTXACK"]
+    #[inline]
+    pub fn ucswack_1(self) -> &'a mut W {
+        self.variant(UCSWACKW::UCSWACK_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTPNACK`"]
+pub enum UCSTPNACKW {
+    #[doc = "Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard)"]
+    UCSTPNACK_0,
+    #[doc = "All bytes are acknowledged by the eUSCI_B when configured as master receiver"]
+    UCSTPNACK_1,
+}
+impl UCSTPNACKW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTPNACKW::UCSTPNACK_0 => false,
+            UCSTPNACKW::UCSTPNACK_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTPNACKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTPNACKW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTPNACKW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard)"]
+    #[inline]
+    pub fn ucstpnack_0(self) -> &'a mut W {
+        self.variant(UCSTPNACKW::UCSTPNACK_0)
+    }
+    #[doc = "All bytes are acknowledged by the eUSCI_B when configured as master receiver"]
+    #[inline]
+    pub fn ucstpnack_1(self) -> &'a mut W {
+        self.variant(UCSTPNACKW::UCSTPNACK_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCCLTO`"]
+pub enum UCCLTOW {
+    #[doc = "Disable clock low timeout counter"]
+    UCCLTO_0,
+    #[doc = "135 000 SYSCLK cycles (approximately 28 ms)"]
+    UCCLTO_1,
+    #[doc = "150 000 SYSCLK cycles (approximately 31 ms)"]
+    UCCLTO_2,
+    #[doc = "165 000 SYSCLK cycles (approximately 34 ms)"]
+    UCCLTO_3,
+}
+impl UCCLTOW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCCLTOW::UCCLTO_0 => 0,
+            UCCLTOW::UCCLTO_1 => 1,
+            UCCLTOW::UCCLTO_2 => 2,
+            UCCLTOW::UCCLTO_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCCLTOW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCCLTOW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCCLTOW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Disable clock low timeout counter"]
+    #[inline]
+    pub fn ucclto_0(self) -> &'a mut W {
+        self.variant(UCCLTOW::UCCLTO_0)
+    }
+    #[doc = "135 000 SYSCLK cycles (approximately 28 ms)"]
+    #[inline]
+    pub fn ucclto_1(self) -> &'a mut W {
+        self.variant(UCCLTOW::UCCLTO_1)
+    }
+    #[doc = "150 000 SYSCLK cycles (approximately 31 ms)"]
+    #[inline]
+    pub fn ucclto_2(self) -> &'a mut W {
+        self.variant(UCCLTOW::UCCLTO_2)
+    }
+    #[doc = "165 000 SYSCLK cycles (approximately 34 ms)"]
+    #[inline]
+    pub fn ucclto_3(self) -> &'a mut W {
+        self.variant(UCCLTOW::UCCLTO_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCETXINT`"]
+pub enum UCETXINTW {
+    #[doc = "UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit"]
+    UCETXINT_0,
+    #[doc = "UCTXIFG0 is set for each START condition"]
+    UCETXINT_1,
+}
+impl UCETXINTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCETXINTW::UCETXINT_0 => false,
+            UCETXINTW::UCETXINT_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCETXINTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCETXINTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCETXINTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit"]
+    #[inline]
+    pub fn ucetxint_0(self) -> &'a mut W {
+        self.variant(UCETXINTW::UCETXINT_0)
+    }
+    #[doc = "UCTXIFG0 is set for each START condition"]
+    #[inline]
+    pub fn ucetxint_1(self) -> &'a mut W {
+        self.variant(UCETXINTW::UCETXINT_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:1 - Deglitch time"]
+    #[inline]
+    pub fn ucglit(&self) -> UCGLITR {
+        UCGLITR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bits 2:3 - Automatic STOP condition generation"]
+    #[inline]
+    pub fn ucastp(&self) -> UCASTPR {
+        UCASTPR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 4 - SW or HW ACK control"]
+    #[inline]
+    pub fn ucswack(&self) -> UCSWACKR {
+        UCSWACKR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - ACK all master bytes"]
+    #[inline]
+    pub fn ucstpnack(&self) -> UCSTPNACKR {
+        UCSTPNACKR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 6:7 - Clock low timeout select"]
+    #[inline]
+    pub fn ucclto(&self) -> UCCLTOR {
+        UCCLTOR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 8 - Early UCTXIFG0"]
+    #[inline]
+    pub fn ucetxint(&self) -> UCETXINTR {
+        UCETXINTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 3 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:1 - Deglitch time"]
+    #[inline]
+    pub fn ucglit(&mut self) -> _UCGLITW {
+        _UCGLITW { w: self }
+    }
+    #[doc = "Bits 2:3 - Automatic STOP condition generation"]
+    #[inline]
+    pub fn ucastp(&mut self) -> _UCASTPW {
+        _UCASTPW { w: self }
+    }
+    #[doc = "Bit 4 - SW or HW ACK control"]
+    #[inline]
+    pub fn ucswack(&mut self) -> _UCSWACKW {
+        _UCSWACKW { w: self }
+    }
+    #[doc = "Bit 5 - ACK all master bytes"]
+    #[inline]
+    pub fn ucstpnack(&mut self) -> _UCSTPNACKW {
+        _UCSTPNACKW { w: self }
+    }
+    #[doc = "Bits 6:7 - Clock low timeout select"]
+    #[inline]
+    pub fn ucclto(&mut self) -> _UCCLTOW {
+        _UCCLTOW { w: self }
+    }
+    #[doc = "Bit 8 - Early UCTXIFG0"]
+    #[inline]
+    pub fn ucetxint(&mut self) -> _UCETXINTW {
+        _UCETXINTW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b1/ucbx_i2coa0.rs b/example-source/msp432p401r/src/eusci_b1/ucbx_i2coa0.rs
new file mode 100644
index 0000000..93003b5
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b1/ucbx_i2coa0.rs
@@ -0,0 +1,343 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXI2COA0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct I2COA0R {
+    bits: u16,
+}
+impl I2COA0R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `UCOAEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCOAENR {
+    #[doc = "The slave address defined in I2COA0 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA0 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCOAENR::UCOAEN_0 => false,
+            UCOAENR::UCOAEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCOAENR {
+        match value {
+            false => UCOAENR::UCOAEN_0,
+            true => UCOAENR::UCOAEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_0`"]
+    #[inline]
+    pub fn is_ucoaen_0(&self) -> bool {
+        *self == UCOAENR::UCOAEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_1`"]
+    #[inline]
+    pub fn is_ucoaen_1(&self) -> bool {
+        *self == UCOAENR::UCOAEN_1
+    }
+}
+#[doc = "Possible values of the field `UCGCEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCGCENR {
+    #[doc = "Do not respond to a general call"]
+    UCGCEN_0,
+    #[doc = "Respond to a general call"]
+    UCGCEN_1,
+}
+impl UCGCENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCGCENR::UCGCEN_0 => false,
+            UCGCENR::UCGCEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCGCENR {
+        match value {
+            false => UCGCENR::UCGCEN_0,
+            true => UCGCENR::UCGCEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCGCEN_0`"]
+    #[inline]
+    pub fn is_ucgcen_0(&self) -> bool {
+        *self == UCGCENR::UCGCEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCGCEN_1`"]
+    #[inline]
+    pub fn is_ucgcen_1(&self) -> bool {
+        *self == UCGCENR::UCGCEN_1
+    }
+}
+#[doc = r" Proxy"]
+pub struct _I2COA0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _I2COA0W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCOAEN`"]
+pub enum UCOAENW {
+    #[doc = "The slave address defined in I2COA0 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA0 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCOAENW::UCOAEN_0 => false,
+            UCOAENW::UCOAEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCOAENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCOAENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCOAENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The slave address defined in I2COA0 is disabled"]
+    #[inline]
+    pub fn ucoaen_0(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_0)
+    }
+    #[doc = "The slave address defined in I2COA0 is enabled"]
+    #[inline]
+    pub fn ucoaen_1(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCGCEN`"]
+pub enum UCGCENW {
+    #[doc = "Do not respond to a general call"]
+    UCGCEN_0,
+    #[doc = "Respond to a general call"]
+    UCGCEN_1,
+}
+impl UCGCENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCGCENW::UCGCEN_0 => false,
+            UCGCENW::UCGCEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCGCENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCGCENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCGCENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Do not respond to a general call"]
+    #[inline]
+    pub fn ucgcen_0(self) -> &'a mut W {
+        self.variant(UCGCENW::UCGCEN_0)
+    }
+    #[doc = "Respond to a general call"]
+    #[inline]
+    pub fn ucgcen_1(self) -> &'a mut W {
+        self.variant(UCGCENW::UCGCEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa0(&self) -> I2COA0R {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        I2COA0R { bits }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&self) -> UCOAENR {
+        UCOAENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 15 - General call response enable"]
+    #[inline]
+    pub fn ucgcen(&self) -> UCGCENR {
+        UCGCENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa0(&mut self) -> _I2COA0W {
+        _I2COA0W { w: self }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&mut self) -> _UCOAENW {
+        _UCOAENW { w: self }
+    }
+    #[doc = "Bit 15 - General call response enable"]
+    #[inline]
+    pub fn ucgcen(&mut self) -> _UCGCENW {
+        _UCGCENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b1/ucbx_i2coa1.rs b/example-source/msp432p401r/src/eusci_b1/ucbx_i2coa1.rs
new file mode 100644
index 0000000..660cba5
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b1/ucbx_i2coa1.rs
@@ -0,0 +1,224 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXI2COA1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct I2COA1R {
+    bits: u16,
+}
+impl I2COA1R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `UCOAEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCOAENR {
+    #[doc = "The slave address defined in I2COA1 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA1 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCOAENR::UCOAEN_0 => false,
+            UCOAENR::UCOAEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCOAENR {
+        match value {
+            false => UCOAENR::UCOAEN_0,
+            true => UCOAENR::UCOAEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_0`"]
+    #[inline]
+    pub fn is_ucoaen_0(&self) -> bool {
+        *self == UCOAENR::UCOAEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_1`"]
+    #[inline]
+    pub fn is_ucoaen_1(&self) -> bool {
+        *self == UCOAENR::UCOAEN_1
+    }
+}
+#[doc = r" Proxy"]
+pub struct _I2COA1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _I2COA1W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCOAEN`"]
+pub enum UCOAENW {
+    #[doc = "The slave address defined in I2COA1 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA1 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCOAENW::UCOAEN_0 => false,
+            UCOAENW::UCOAEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCOAENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCOAENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCOAENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The slave address defined in I2COA1 is disabled"]
+    #[inline]
+    pub fn ucoaen_0(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_0)
+    }
+    #[doc = "The slave address defined in I2COA1 is enabled"]
+    #[inline]
+    pub fn ucoaen_1(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa1(&self) -> I2COA1R {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        I2COA1R { bits }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&self) -> UCOAENR {
+        UCOAENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa1(&mut self) -> _I2COA1W {
+        _I2COA1W { w: self }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&mut self) -> _UCOAENW {
+        _UCOAENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b1/ucbx_i2coa2.rs b/example-source/msp432p401r/src/eusci_b1/ucbx_i2coa2.rs
new file mode 100644
index 0000000..4f3ceb5
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b1/ucbx_i2coa2.rs
@@ -0,0 +1,224 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXI2COA2 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct I2COA2R {
+    bits: u16,
+}
+impl I2COA2R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `UCOAEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCOAENR {
+    #[doc = "The slave address defined in I2COA2 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA2 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCOAENR::UCOAEN_0 => false,
+            UCOAENR::UCOAEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCOAENR {
+        match value {
+            false => UCOAENR::UCOAEN_0,
+            true => UCOAENR::UCOAEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_0`"]
+    #[inline]
+    pub fn is_ucoaen_0(&self) -> bool {
+        *self == UCOAENR::UCOAEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_1`"]
+    #[inline]
+    pub fn is_ucoaen_1(&self) -> bool {
+        *self == UCOAENR::UCOAEN_1
+    }
+}
+#[doc = r" Proxy"]
+pub struct _I2COA2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _I2COA2W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCOAEN`"]
+pub enum UCOAENW {
+    #[doc = "The slave address defined in I2COA2 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA2 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCOAENW::UCOAEN_0 => false,
+            UCOAENW::UCOAEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCOAENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCOAENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCOAENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The slave address defined in I2COA2 is disabled"]
+    #[inline]
+    pub fn ucoaen_0(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_0)
+    }
+    #[doc = "The slave address defined in I2COA2 is enabled"]
+    #[inline]
+    pub fn ucoaen_1(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa2(&self) -> I2COA2R {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        I2COA2R { bits }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&self) -> UCOAENR {
+        UCOAENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa2(&mut self) -> _I2COA2W {
+        _I2COA2W { w: self }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&mut self) -> _UCOAENW {
+        _UCOAENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b1/ucbx_i2coa3.rs b/example-source/msp432p401r/src/eusci_b1/ucbx_i2coa3.rs
new file mode 100644
index 0000000..8cab4f2
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b1/ucbx_i2coa3.rs
@@ -0,0 +1,224 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXI2COA3 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct I2COA3R {
+    bits: u16,
+}
+impl I2COA3R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `UCOAEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCOAENR {
+    #[doc = "The slave address defined in I2COA3 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA3 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCOAENR::UCOAEN_0 => false,
+            UCOAENR::UCOAEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCOAENR {
+        match value {
+            false => UCOAENR::UCOAEN_0,
+            true => UCOAENR::UCOAEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_0`"]
+    #[inline]
+    pub fn is_ucoaen_0(&self) -> bool {
+        *self == UCOAENR::UCOAEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_1`"]
+    #[inline]
+    pub fn is_ucoaen_1(&self) -> bool {
+        *self == UCOAENR::UCOAEN_1
+    }
+}
+#[doc = r" Proxy"]
+pub struct _I2COA3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _I2COA3W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCOAEN`"]
+pub enum UCOAENW {
+    #[doc = "The slave address defined in I2COA3 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA3 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCOAENW::UCOAEN_0 => false,
+            UCOAENW::UCOAEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCOAENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCOAENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCOAENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The slave address defined in I2COA3 is disabled"]
+    #[inline]
+    pub fn ucoaen_0(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_0)
+    }
+    #[doc = "The slave address defined in I2COA3 is enabled"]
+    #[inline]
+    pub fn ucoaen_1(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa3(&self) -> I2COA3R {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        I2COA3R { bits }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&self) -> UCOAENR {
+        UCOAENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa3(&mut self) -> _I2COA3W {
+        _I2COA3W { w: self }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&mut self) -> _UCOAENW {
+        _UCOAENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b1/ucbx_i2csa.rs b/example-source/msp432p401r/src/eusci_b1/ucbx_i2csa.rs
new file mode 100644
index 0000000..33de734
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b1/ucbx_i2csa.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXI2CSA {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct I2CSAR {
+    bits: u16,
+}
+impl I2CSAR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _I2CSAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _I2CSAW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - I2C slave address"]
+    #[inline]
+    pub fn i2csa(&self) -> I2CSAR {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        I2CSAR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:9 - I2C slave address"]
+    #[inline]
+    pub fn i2csa(&mut self) -> _I2CSAW {
+        _I2CSAW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b1/ucbx_ie.rs b/example-source/msp432p401r/src/eusci_b1/ucbx_ie.rs
new file mode 100644
index 0000000..7c9f18c
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b1/ucbx_ie.rs
@@ -0,0 +1,1849 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXIE {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCRXIE0`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIE0R {
+    #[doc = "Interrupt disabled"]
+    UCRXIE0_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE0_1,
+}
+impl UCRXIE0R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIE0R::UCRXIE0_0 => false,
+            UCRXIE0R::UCRXIE0_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIE0R {
+        match value {
+            false => UCRXIE0R::UCRXIE0_0,
+            true => UCRXIE0R::UCRXIE0_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE0_0`"]
+    #[inline]
+    pub fn is_ucrxie0_0(&self) -> bool {
+        *self == UCRXIE0R::UCRXIE0_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE0_1`"]
+    #[inline]
+    pub fn is_ucrxie0_1(&self) -> bool {
+        *self == UCRXIE0R::UCRXIE0_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIE0`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIE0R {
+    #[doc = "Interrupt disabled"]
+    UCTXIE0_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE0_1,
+}
+impl UCTXIE0R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIE0R::UCTXIE0_0 => false,
+            UCTXIE0R::UCTXIE0_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIE0R {
+        match value {
+            false => UCTXIE0R::UCTXIE0_0,
+            true => UCTXIE0R::UCTXIE0_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE0_0`"]
+    #[inline]
+    pub fn is_uctxie0_0(&self) -> bool {
+        *self == UCTXIE0R::UCTXIE0_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE0_1`"]
+    #[inline]
+    pub fn is_uctxie0_1(&self) -> bool {
+        *self == UCTXIE0R::UCTXIE0_1
+    }
+}
+#[doc = "Possible values of the field `UCSTTIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTTIER {
+    #[doc = "Interrupt disabled"]
+    UCSTTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCSTTIE_1,
+}
+impl UCSTTIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTTIER::UCSTTIE_0 => false,
+            UCSTTIER::UCSTTIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTTIER {
+        match value {
+            false => UCSTTIER::UCSTTIE_0,
+            true => UCSTTIER::UCSTTIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIE_0`"]
+    #[inline]
+    pub fn is_ucsttie_0(&self) -> bool {
+        *self == UCSTTIER::UCSTTIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIE_1`"]
+    #[inline]
+    pub fn is_ucsttie_1(&self) -> bool {
+        *self == UCSTTIER::UCSTTIE_1
+    }
+}
+#[doc = "Possible values of the field `UCSTPIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTPIER {
+    #[doc = "Interrupt disabled"]
+    UCSTPIE_0,
+    #[doc = "Interrupt enabled"]
+    UCSTPIE_1,
+}
+impl UCSTPIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTPIER::UCSTPIE_0 => false,
+            UCSTPIER::UCSTPIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTPIER {
+        match value {
+            false => UCSTPIER::UCSTPIE_0,
+            true => UCSTPIER::UCSTPIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTPIE_0`"]
+    #[inline]
+    pub fn is_ucstpie_0(&self) -> bool {
+        *self == UCSTPIER::UCSTPIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTPIE_1`"]
+    #[inline]
+    pub fn is_ucstpie_1(&self) -> bool {
+        *self == UCSTPIER::UCSTPIE_1
+    }
+}
+#[doc = "Possible values of the field `UCALIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCALIER {
+    #[doc = "Interrupt disabled"]
+    UCALIE_0,
+    #[doc = "Interrupt enabled"]
+    UCALIE_1,
+}
+impl UCALIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCALIER::UCALIE_0 => false,
+            UCALIER::UCALIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCALIER {
+        match value {
+            false => UCALIER::UCALIE_0,
+            true => UCALIER::UCALIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCALIE_0`"]
+    #[inline]
+    pub fn is_ucalie_0(&self) -> bool {
+        *self == UCALIER::UCALIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCALIE_1`"]
+    #[inline]
+    pub fn is_ucalie_1(&self) -> bool {
+        *self == UCALIER::UCALIE_1
+    }
+}
+#[doc = "Possible values of the field `UCNACKIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCNACKIER {
+    #[doc = "Interrupt disabled"]
+    UCNACKIE_0,
+    #[doc = "Interrupt enabled"]
+    UCNACKIE_1,
+}
+impl UCNACKIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCNACKIER::UCNACKIE_0 => false,
+            UCNACKIER::UCNACKIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCNACKIER {
+        match value {
+            false => UCNACKIER::UCNACKIE_0,
+            true => UCNACKIER::UCNACKIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCNACKIE_0`"]
+    #[inline]
+    pub fn is_ucnackie_0(&self) -> bool {
+        *self == UCNACKIER::UCNACKIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCNACKIE_1`"]
+    #[inline]
+    pub fn is_ucnackie_1(&self) -> bool {
+        *self == UCNACKIER::UCNACKIE_1
+    }
+}
+#[doc = "Possible values of the field `UCBCNTIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBCNTIER {
+    #[doc = "Interrupt disabled"]
+    UCBCNTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCBCNTIE_1,
+}
+impl UCBCNTIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBCNTIER::UCBCNTIE_0 => false,
+            UCBCNTIER::UCBCNTIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBCNTIER {
+        match value {
+            false => UCBCNTIER::UCBCNTIE_0,
+            true => UCBCNTIER::UCBCNTIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBCNTIE_0`"]
+    #[inline]
+    pub fn is_ucbcntie_0(&self) -> bool {
+        *self == UCBCNTIER::UCBCNTIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCBCNTIE_1`"]
+    #[inline]
+    pub fn is_ucbcntie_1(&self) -> bool {
+        *self == UCBCNTIER::UCBCNTIE_1
+    }
+}
+#[doc = "Possible values of the field `UCCLTOIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCCLTOIER {
+    #[doc = "Interrupt disabled"]
+    UCCLTOIE_0,
+    #[doc = "Interrupt enabled"]
+    UCCLTOIE_1,
+}
+impl UCCLTOIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCCLTOIER::UCCLTOIE_0 => false,
+            UCCLTOIER::UCCLTOIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCCLTOIER {
+        match value {
+            false => UCCLTOIER::UCCLTOIE_0,
+            true => UCCLTOIER::UCCLTOIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCCLTOIE_0`"]
+    #[inline]
+    pub fn is_uccltoie_0(&self) -> bool {
+        *self == UCCLTOIER::UCCLTOIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCCLTOIE_1`"]
+    #[inline]
+    pub fn is_uccltoie_1(&self) -> bool {
+        *self == UCCLTOIER::UCCLTOIE_1
+    }
+}
+#[doc = "Possible values of the field `UCRXIE1`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIE1R {
+    #[doc = "Interrupt disabled"]
+    UCRXIE1_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE1_1,
+}
+impl UCRXIE1R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIE1R::UCRXIE1_0 => false,
+            UCRXIE1R::UCRXIE1_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIE1R {
+        match value {
+            false => UCRXIE1R::UCRXIE1_0,
+            true => UCRXIE1R::UCRXIE1_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE1_0`"]
+    #[inline]
+    pub fn is_ucrxie1_0(&self) -> bool {
+        *self == UCRXIE1R::UCRXIE1_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE1_1`"]
+    #[inline]
+    pub fn is_ucrxie1_1(&self) -> bool {
+        *self == UCRXIE1R::UCRXIE1_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIE1`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIE1R {
+    #[doc = "Interrupt disabled"]
+    UCTXIE1_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE1_1,
+}
+impl UCTXIE1R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIE1R::UCTXIE1_0 => false,
+            UCTXIE1R::UCTXIE1_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIE1R {
+        match value {
+            false => UCTXIE1R::UCTXIE1_0,
+            true => UCTXIE1R::UCTXIE1_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE1_0`"]
+    #[inline]
+    pub fn is_uctxie1_0(&self) -> bool {
+        *self == UCTXIE1R::UCTXIE1_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE1_1`"]
+    #[inline]
+    pub fn is_uctxie1_1(&self) -> bool {
+        *self == UCTXIE1R::UCTXIE1_1
+    }
+}
+#[doc = "Possible values of the field `UCRXIE2`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIE2R {
+    #[doc = "Interrupt disabled"]
+    UCRXIE2_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE2_1,
+}
+impl UCRXIE2R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIE2R::UCRXIE2_0 => false,
+            UCRXIE2R::UCRXIE2_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIE2R {
+        match value {
+            false => UCRXIE2R::UCRXIE2_0,
+            true => UCRXIE2R::UCRXIE2_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE2_0`"]
+    #[inline]
+    pub fn is_ucrxie2_0(&self) -> bool {
+        *self == UCRXIE2R::UCRXIE2_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE2_1`"]
+    #[inline]
+    pub fn is_ucrxie2_1(&self) -> bool {
+        *self == UCRXIE2R::UCRXIE2_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIE2`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIE2R {
+    #[doc = "Interrupt disabled"]
+    UCTXIE2_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE2_1,
+}
+impl UCTXIE2R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIE2R::UCTXIE2_0 => false,
+            UCTXIE2R::UCTXIE2_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIE2R {
+        match value {
+            false => UCTXIE2R::UCTXIE2_0,
+            true => UCTXIE2R::UCTXIE2_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE2_0`"]
+    #[inline]
+    pub fn is_uctxie2_0(&self) -> bool {
+        *self == UCTXIE2R::UCTXIE2_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE2_1`"]
+    #[inline]
+    pub fn is_uctxie2_1(&self) -> bool {
+        *self == UCTXIE2R::UCTXIE2_1
+    }
+}
+#[doc = "Possible values of the field `UCRXIE3`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIE3R {
+    #[doc = "Interrupt disabled"]
+    UCRXIE3_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE3_1,
+}
+impl UCRXIE3R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIE3R::UCRXIE3_0 => false,
+            UCRXIE3R::UCRXIE3_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIE3R {
+        match value {
+            false => UCRXIE3R::UCRXIE3_0,
+            true => UCRXIE3R::UCRXIE3_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE3_0`"]
+    #[inline]
+    pub fn is_ucrxie3_0(&self) -> bool {
+        *self == UCRXIE3R::UCRXIE3_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE3_1`"]
+    #[inline]
+    pub fn is_ucrxie3_1(&self) -> bool {
+        *self == UCRXIE3R::UCRXIE3_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIE3`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIE3R {
+    #[doc = "Interrupt disabled"]
+    UCTXIE3_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE3_1,
+}
+impl UCTXIE3R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIE3R::UCTXIE3_0 => false,
+            UCTXIE3R::UCTXIE3_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIE3R {
+        match value {
+            false => UCTXIE3R::UCTXIE3_0,
+            true => UCTXIE3R::UCTXIE3_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE3_0`"]
+    #[inline]
+    pub fn is_uctxie3_0(&self) -> bool {
+        *self == UCTXIE3R::UCTXIE3_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE3_1`"]
+    #[inline]
+    pub fn is_uctxie3_1(&self) -> bool {
+        *self == UCTXIE3R::UCTXIE3_1
+    }
+}
+#[doc = "Possible values of the field `UCBIT9IE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBIT9IER {
+    #[doc = "Interrupt disabled"]
+    UCBIT9IE_0,
+    #[doc = "Interrupt enabled"]
+    UCBIT9IE_1,
+}
+impl UCBIT9IER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBIT9IER::UCBIT9IE_0 => false,
+            UCBIT9IER::UCBIT9IE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBIT9IER {
+        match value {
+            false => UCBIT9IER::UCBIT9IE_0,
+            true => UCBIT9IER::UCBIT9IE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBIT9IE_0`"]
+    #[inline]
+    pub fn is_ucbit9ie_0(&self) -> bool {
+        *self == UCBIT9IER::UCBIT9IE_0
+    }
+    #[doc = "Checks if the value of the field is `UCBIT9IE_1`"]
+    #[inline]
+    pub fn is_ucbit9ie_1(&self) -> bool {
+        *self == UCBIT9IER::UCBIT9IE_1
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIE0`"]
+pub enum UCRXIE0W {
+    #[doc = "Interrupt disabled"]
+    UCRXIE0_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE0_1,
+}
+impl UCRXIE0W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIE0W::UCRXIE0_0 => false,
+            UCRXIE0W::UCRXIE0_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIE0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIE0W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIE0W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucrxie0_0(self) -> &'a mut W {
+        self.variant(UCRXIE0W::UCRXIE0_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucrxie0_1(self) -> &'a mut W {
+        self.variant(UCRXIE0W::UCRXIE0_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIE0`"]
+pub enum UCTXIE0W {
+    #[doc = "Interrupt disabled"]
+    UCTXIE0_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE0_1,
+}
+impl UCTXIE0W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIE0W::UCTXIE0_0 => false,
+            UCTXIE0W::UCTXIE0_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIE0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIE0W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIE0W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn uctxie0_0(self) -> &'a mut W {
+        self.variant(UCTXIE0W::UCTXIE0_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn uctxie0_1(self) -> &'a mut W {
+        self.variant(UCTXIE0W::UCTXIE0_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTTIE`"]
+pub enum UCSTTIEW {
+    #[doc = "Interrupt disabled"]
+    UCSTTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCSTTIE_1,
+}
+impl UCSTTIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTTIEW::UCSTTIE_0 => false,
+            UCSTTIEW::UCSTTIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTTIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTTIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTTIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucsttie_0(self) -> &'a mut W {
+        self.variant(UCSTTIEW::UCSTTIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucsttie_1(self) -> &'a mut W {
+        self.variant(UCSTTIEW::UCSTTIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTPIE`"]
+pub enum UCSTPIEW {
+    #[doc = "Interrupt disabled"]
+    UCSTPIE_0,
+    #[doc = "Interrupt enabled"]
+    UCSTPIE_1,
+}
+impl UCSTPIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTPIEW::UCSTPIE_0 => false,
+            UCSTPIEW::UCSTPIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTPIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTPIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTPIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucstpie_0(self) -> &'a mut W {
+        self.variant(UCSTPIEW::UCSTPIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucstpie_1(self) -> &'a mut W {
+        self.variant(UCSTPIEW::UCSTPIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCALIE`"]
+pub enum UCALIEW {
+    #[doc = "Interrupt disabled"]
+    UCALIE_0,
+    #[doc = "Interrupt enabled"]
+    UCALIE_1,
+}
+impl UCALIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCALIEW::UCALIE_0 => false,
+            UCALIEW::UCALIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCALIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCALIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCALIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucalie_0(self) -> &'a mut W {
+        self.variant(UCALIEW::UCALIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucalie_1(self) -> &'a mut W {
+        self.variant(UCALIEW::UCALIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCNACKIE`"]
+pub enum UCNACKIEW {
+    #[doc = "Interrupt disabled"]
+    UCNACKIE_0,
+    #[doc = "Interrupt enabled"]
+    UCNACKIE_1,
+}
+impl UCNACKIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCNACKIEW::UCNACKIE_0 => false,
+            UCNACKIEW::UCNACKIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCNACKIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCNACKIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCNACKIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucnackie_0(self) -> &'a mut W {
+        self.variant(UCNACKIEW::UCNACKIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucnackie_1(self) -> &'a mut W {
+        self.variant(UCNACKIEW::UCNACKIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCBCNTIE`"]
+pub enum UCBCNTIEW {
+    #[doc = "Interrupt disabled"]
+    UCBCNTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCBCNTIE_1,
+}
+impl UCBCNTIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCBCNTIEW::UCBCNTIE_0 => false,
+            UCBCNTIEW::UCBCNTIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBCNTIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBCNTIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCBCNTIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucbcntie_0(self) -> &'a mut W {
+        self.variant(UCBCNTIEW::UCBCNTIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucbcntie_1(self) -> &'a mut W {
+        self.variant(UCBCNTIEW::UCBCNTIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCCLTOIE`"]
+pub enum UCCLTOIEW {
+    #[doc = "Interrupt disabled"]
+    UCCLTOIE_0,
+    #[doc = "Interrupt enabled"]
+    UCCLTOIE_1,
+}
+impl UCCLTOIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCCLTOIEW::UCCLTOIE_0 => false,
+            UCCLTOIEW::UCCLTOIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCCLTOIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCCLTOIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCCLTOIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn uccltoie_0(self) -> &'a mut W {
+        self.variant(UCCLTOIEW::UCCLTOIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn uccltoie_1(self) -> &'a mut W {
+        self.variant(UCCLTOIEW::UCCLTOIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIE1`"]
+pub enum UCRXIE1W {
+    #[doc = "Interrupt disabled"]
+    UCRXIE1_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE1_1,
+}
+impl UCRXIE1W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIE1W::UCRXIE1_0 => false,
+            UCRXIE1W::UCRXIE1_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIE1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIE1W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIE1W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucrxie1_0(self) -> &'a mut W {
+        self.variant(UCRXIE1W::UCRXIE1_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucrxie1_1(self) -> &'a mut W {
+        self.variant(UCRXIE1W::UCRXIE1_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIE1`"]
+pub enum UCTXIE1W {
+    #[doc = "Interrupt disabled"]
+    UCTXIE1_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE1_1,
+}
+impl UCTXIE1W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIE1W::UCTXIE1_0 => false,
+            UCTXIE1W::UCTXIE1_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIE1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIE1W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIE1W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn uctxie1_0(self) -> &'a mut W {
+        self.variant(UCTXIE1W::UCTXIE1_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn uctxie1_1(self) -> &'a mut W {
+        self.variant(UCTXIE1W::UCTXIE1_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIE2`"]
+pub enum UCRXIE2W {
+    #[doc = "Interrupt disabled"]
+    UCRXIE2_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE2_1,
+}
+impl UCRXIE2W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIE2W::UCRXIE2_0 => false,
+            UCRXIE2W::UCRXIE2_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIE2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIE2W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIE2W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucrxie2_0(self) -> &'a mut W {
+        self.variant(UCRXIE2W::UCRXIE2_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucrxie2_1(self) -> &'a mut W {
+        self.variant(UCRXIE2W::UCRXIE2_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIE2`"]
+pub enum UCTXIE2W {
+    #[doc = "Interrupt disabled"]
+    UCTXIE2_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE2_1,
+}
+impl UCTXIE2W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIE2W::UCTXIE2_0 => false,
+            UCTXIE2W::UCTXIE2_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIE2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIE2W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIE2W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn uctxie2_0(self) -> &'a mut W {
+        self.variant(UCTXIE2W::UCTXIE2_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn uctxie2_1(self) -> &'a mut W {
+        self.variant(UCTXIE2W::UCTXIE2_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIE3`"]
+pub enum UCRXIE3W {
+    #[doc = "Interrupt disabled"]
+    UCRXIE3_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE3_1,
+}
+impl UCRXIE3W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIE3W::UCRXIE3_0 => false,
+            UCRXIE3W::UCRXIE3_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIE3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIE3W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIE3W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucrxie3_0(self) -> &'a mut W {
+        self.variant(UCRXIE3W::UCRXIE3_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucrxie3_1(self) -> &'a mut W {
+        self.variant(UCRXIE3W::UCRXIE3_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIE3`"]
+pub enum UCTXIE3W {
+    #[doc = "Interrupt disabled"]
+    UCTXIE3_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE3_1,
+}
+impl UCTXIE3W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIE3W::UCTXIE3_0 => false,
+            UCTXIE3W::UCTXIE3_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIE3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIE3W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIE3W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn uctxie3_0(self) -> &'a mut W {
+        self.variant(UCTXIE3W::UCTXIE3_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn uctxie3_1(self) -> &'a mut W {
+        self.variant(UCTXIE3W::UCTXIE3_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCBIT9IE`"]
+pub enum UCBIT9IEW {
+    #[doc = "Interrupt disabled"]
+    UCBIT9IE_0,
+    #[doc = "Interrupt enabled"]
+    UCBIT9IE_1,
+}
+impl UCBIT9IEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCBIT9IEW::UCBIT9IE_0 => false,
+            UCBIT9IEW::UCBIT9IE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBIT9IEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBIT9IEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCBIT9IEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucbit9ie_0(self) -> &'a mut W {
+        self.variant(UCBIT9IEW::UCBIT9IE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucbit9ie_1(self) -> &'a mut W {
+        self.variant(UCBIT9IEW::UCBIT9IE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Receive interrupt enable 0"]
+    #[inline]
+    pub fn ucrxie0(&self) -> UCRXIE0R {
+        UCRXIE0R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Transmit interrupt enable 0"]
+    #[inline]
+    pub fn uctxie0(&self) -> UCTXIE0R {
+        UCTXIE0R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - START condition interrupt enable"]
+    #[inline]
+    pub fn ucsttie(&self) -> UCSTTIER {
+        UCSTTIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - STOP condition interrupt enable"]
+    #[inline]
+    pub fn ucstpie(&self) -> UCSTPIER {
+        UCSTPIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 4 - Arbitration lost interrupt enable"]
+    #[inline]
+    pub fn ucalie(&self) -> UCALIER {
+        UCALIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - Not-acknowledge interrupt enable"]
+    #[inline]
+    pub fn ucnackie(&self) -> UCNACKIER {
+        UCNACKIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 6 - Byte counter interrupt enable"]
+    #[inline]
+    pub fn ucbcntie(&self) -> UCBCNTIER {
+        UCBCNTIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 7 - Clock low timeout interrupt enable"]
+    #[inline]
+    pub fn uccltoie(&self) -> UCCLTOIER {
+        UCCLTOIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 8 - Receive interrupt enable 1"]
+    #[inline]
+    pub fn ucrxie1(&self) -> UCRXIE1R {
+        UCRXIE1R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 9 - Transmit interrupt enable 1"]
+    #[inline]
+    pub fn uctxie1(&self) -> UCTXIE1R {
+        UCTXIE1R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 10 - Receive interrupt enable 2"]
+    #[inline]
+    pub fn ucrxie2(&self) -> UCRXIE2R {
+        UCRXIE2R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 11 - Transmit interrupt enable 2"]
+    #[inline]
+    pub fn uctxie2(&self) -> UCTXIE2R {
+        UCTXIE2R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 12 - Receive interrupt enable 3"]
+    #[inline]
+    pub fn ucrxie3(&self) -> UCRXIE3R {
+        UCRXIE3R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 13 - Transmit interrupt enable 3"]
+    #[inline]
+    pub fn uctxie3(&self) -> UCTXIE3R {
+        UCTXIE3R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 14 - Bit position 9 interrupt enable"]
+    #[inline]
+    pub fn ucbit9ie(&self) -> UCBIT9IER {
+        UCBIT9IER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Receive interrupt enable 0"]
+    #[inline]
+    pub fn ucrxie0(&mut self) -> _UCRXIE0W {
+        _UCRXIE0W { w: self }
+    }
+    #[doc = "Bit 1 - Transmit interrupt enable 0"]
+    #[inline]
+    pub fn uctxie0(&mut self) -> _UCTXIE0W {
+        _UCTXIE0W { w: self }
+    }
+    #[doc = "Bit 2 - START condition interrupt enable"]
+    #[inline]
+    pub fn ucsttie(&mut self) -> _UCSTTIEW {
+        _UCSTTIEW { w: self }
+    }
+    #[doc = "Bit 3 - STOP condition interrupt enable"]
+    #[inline]
+    pub fn ucstpie(&mut self) -> _UCSTPIEW {
+        _UCSTPIEW { w: self }
+    }
+    #[doc = "Bit 4 - Arbitration lost interrupt enable"]
+    #[inline]
+    pub fn ucalie(&mut self) -> _UCALIEW {
+        _UCALIEW { w: self }
+    }
+    #[doc = "Bit 5 - Not-acknowledge interrupt enable"]
+    #[inline]
+    pub fn ucnackie(&mut self) -> _UCNACKIEW {
+        _UCNACKIEW { w: self }
+    }
+    #[doc = "Bit 6 - Byte counter interrupt enable"]
+    #[inline]
+    pub fn ucbcntie(&mut self) -> _UCBCNTIEW {
+        _UCBCNTIEW { w: self }
+    }
+    #[doc = "Bit 7 - Clock low timeout interrupt enable"]
+    #[inline]
+    pub fn uccltoie(&mut self) -> _UCCLTOIEW {
+        _UCCLTOIEW { w: self }
+    }
+    #[doc = "Bit 8 - Receive interrupt enable 1"]
+    #[inline]
+    pub fn ucrxie1(&mut self) -> _UCRXIE1W {
+        _UCRXIE1W { w: self }
+    }
+    #[doc = "Bit 9 - Transmit interrupt enable 1"]
+    #[inline]
+    pub fn uctxie1(&mut self) -> _UCTXIE1W {
+        _UCTXIE1W { w: self }
+    }
+    #[doc = "Bit 10 - Receive interrupt enable 2"]
+    #[inline]
+    pub fn ucrxie2(&mut self) -> _UCRXIE2W {
+        _UCRXIE2W { w: self }
+    }
+    #[doc = "Bit 11 - Transmit interrupt enable 2"]
+    #[inline]
+    pub fn uctxie2(&mut self) -> _UCTXIE2W {
+        _UCTXIE2W { w: self }
+    }
+    #[doc = "Bit 12 - Receive interrupt enable 3"]
+    #[inline]
+    pub fn ucrxie3(&mut self) -> _UCRXIE3W {
+        _UCRXIE3W { w: self }
+    }
+    #[doc = "Bit 13 - Transmit interrupt enable 3"]
+    #[inline]
+    pub fn uctxie3(&mut self) -> _UCTXIE3W {
+        _UCTXIE3W { w: self }
+    }
+    #[doc = "Bit 14 - Bit position 9 interrupt enable"]
+    #[inline]
+    pub fn ucbit9ie(&mut self) -> _UCBIT9IEW {
+        _UCBIT9IEW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b1/ucbx_ifg.rs b/example-source/msp432p401r/src/eusci_b1/ucbx_ifg.rs
new file mode 100644
index 0000000..28681c9
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b1/ucbx_ifg.rs
@@ -0,0 +1,1849 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXIFG {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCRXIFG0`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIFG0R {
+    #[doc = "No interrupt pending"]
+    UCRXIFG0_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG0_1,
+}
+impl UCRXIFG0R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIFG0R::UCRXIFG0_0 => false,
+            UCRXIFG0R::UCRXIFG0_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIFG0R {
+        match value {
+            false => UCRXIFG0R::UCRXIFG0_0,
+            true => UCRXIFG0R::UCRXIFG0_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG0_0`"]
+    #[inline]
+    pub fn is_ucrxifg0_0(&self) -> bool {
+        *self == UCRXIFG0R::UCRXIFG0_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG0_1`"]
+    #[inline]
+    pub fn is_ucrxifg0_1(&self) -> bool {
+        *self == UCRXIFG0R::UCRXIFG0_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIFG0`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIFG0R {
+    #[doc = "No interrupt pending"]
+    UCTXIFG0_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG0_1,
+}
+impl UCTXIFG0R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIFG0R::UCTXIFG0_0 => false,
+            UCTXIFG0R::UCTXIFG0_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIFG0R {
+        match value {
+            false => UCTXIFG0R::UCTXIFG0_0,
+            true => UCTXIFG0R::UCTXIFG0_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG0_0`"]
+    #[inline]
+    pub fn is_uctxifg0_0(&self) -> bool {
+        *self == UCTXIFG0R::UCTXIFG0_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG0_1`"]
+    #[inline]
+    pub fn is_uctxifg0_1(&self) -> bool {
+        *self == UCTXIFG0R::UCTXIFG0_1
+    }
+}
+#[doc = "Possible values of the field `UCSTTIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTTIFGR {
+    #[doc = "No interrupt pending"]
+    UCSTTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCSTTIFG_1,
+}
+impl UCSTTIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTTIFGR::UCSTTIFG_0 => false,
+            UCSTTIFGR::UCSTTIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTTIFGR {
+        match value {
+            false => UCSTTIFGR::UCSTTIFG_0,
+            true => UCSTTIFGR::UCSTTIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIFG_0`"]
+    #[inline]
+    pub fn is_ucsttifg_0(&self) -> bool {
+        *self == UCSTTIFGR::UCSTTIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIFG_1`"]
+    #[inline]
+    pub fn is_ucsttifg_1(&self) -> bool {
+        *self == UCSTTIFGR::UCSTTIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCSTPIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTPIFGR {
+    #[doc = "No interrupt pending"]
+    UCSTPIFG_0,
+    #[doc = "Interrupt pending"]
+    UCSTPIFG_1,
+}
+impl UCSTPIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTPIFGR::UCSTPIFG_0 => false,
+            UCSTPIFGR::UCSTPIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTPIFGR {
+        match value {
+            false => UCSTPIFGR::UCSTPIFG_0,
+            true => UCSTPIFGR::UCSTPIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTPIFG_0`"]
+    #[inline]
+    pub fn is_ucstpifg_0(&self) -> bool {
+        *self == UCSTPIFGR::UCSTPIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTPIFG_1`"]
+    #[inline]
+    pub fn is_ucstpifg_1(&self) -> bool {
+        *self == UCSTPIFGR::UCSTPIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCALIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCALIFGR {
+    #[doc = "No interrupt pending"]
+    UCALIFG_0,
+    #[doc = "Interrupt pending"]
+    UCALIFG_1,
+}
+impl UCALIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCALIFGR::UCALIFG_0 => false,
+            UCALIFGR::UCALIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCALIFGR {
+        match value {
+            false => UCALIFGR::UCALIFG_0,
+            true => UCALIFGR::UCALIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCALIFG_0`"]
+    #[inline]
+    pub fn is_ucalifg_0(&self) -> bool {
+        *self == UCALIFGR::UCALIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCALIFG_1`"]
+    #[inline]
+    pub fn is_ucalifg_1(&self) -> bool {
+        *self == UCALIFGR::UCALIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCNACKIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCNACKIFGR {
+    #[doc = "No interrupt pending"]
+    UCNACKIFG_0,
+    #[doc = "Interrupt pending"]
+    UCNACKIFG_1,
+}
+impl UCNACKIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCNACKIFGR::UCNACKIFG_0 => false,
+            UCNACKIFGR::UCNACKIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCNACKIFGR {
+        match value {
+            false => UCNACKIFGR::UCNACKIFG_0,
+            true => UCNACKIFGR::UCNACKIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCNACKIFG_0`"]
+    #[inline]
+    pub fn is_ucnackifg_0(&self) -> bool {
+        *self == UCNACKIFGR::UCNACKIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCNACKIFG_1`"]
+    #[inline]
+    pub fn is_ucnackifg_1(&self) -> bool {
+        *self == UCNACKIFGR::UCNACKIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCBCNTIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBCNTIFGR {
+    #[doc = "No interrupt pending"]
+    UCBCNTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCBCNTIFG_1,
+}
+impl UCBCNTIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBCNTIFGR::UCBCNTIFG_0 => false,
+            UCBCNTIFGR::UCBCNTIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBCNTIFGR {
+        match value {
+            false => UCBCNTIFGR::UCBCNTIFG_0,
+            true => UCBCNTIFGR::UCBCNTIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBCNTIFG_0`"]
+    #[inline]
+    pub fn is_ucbcntifg_0(&self) -> bool {
+        *self == UCBCNTIFGR::UCBCNTIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCBCNTIFG_1`"]
+    #[inline]
+    pub fn is_ucbcntifg_1(&self) -> bool {
+        *self == UCBCNTIFGR::UCBCNTIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCCLTOIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCCLTOIFGR {
+    #[doc = "No interrupt pending"]
+    UCCLTOIFG_0,
+    #[doc = "Interrupt pending"]
+    UCCLTOIFG_1,
+}
+impl UCCLTOIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCCLTOIFGR::UCCLTOIFG_0 => false,
+            UCCLTOIFGR::UCCLTOIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCCLTOIFGR {
+        match value {
+            false => UCCLTOIFGR::UCCLTOIFG_0,
+            true => UCCLTOIFGR::UCCLTOIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCCLTOIFG_0`"]
+    #[inline]
+    pub fn is_uccltoifg_0(&self) -> bool {
+        *self == UCCLTOIFGR::UCCLTOIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCCLTOIFG_1`"]
+    #[inline]
+    pub fn is_uccltoifg_1(&self) -> bool {
+        *self == UCCLTOIFGR::UCCLTOIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCRXIFG1`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIFG1R {
+    #[doc = "No interrupt pending"]
+    UCRXIFG1_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG1_1,
+}
+impl UCRXIFG1R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIFG1R::UCRXIFG1_0 => false,
+            UCRXIFG1R::UCRXIFG1_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIFG1R {
+        match value {
+            false => UCRXIFG1R::UCRXIFG1_0,
+            true => UCRXIFG1R::UCRXIFG1_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG1_0`"]
+    #[inline]
+    pub fn is_ucrxifg1_0(&self) -> bool {
+        *self == UCRXIFG1R::UCRXIFG1_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG1_1`"]
+    #[inline]
+    pub fn is_ucrxifg1_1(&self) -> bool {
+        *self == UCRXIFG1R::UCRXIFG1_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIFG1`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIFG1R {
+    #[doc = "No interrupt pending"]
+    UCTXIFG1_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG1_1,
+}
+impl UCTXIFG1R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIFG1R::UCTXIFG1_0 => false,
+            UCTXIFG1R::UCTXIFG1_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIFG1R {
+        match value {
+            false => UCTXIFG1R::UCTXIFG1_0,
+            true => UCTXIFG1R::UCTXIFG1_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG1_0`"]
+    #[inline]
+    pub fn is_uctxifg1_0(&self) -> bool {
+        *self == UCTXIFG1R::UCTXIFG1_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG1_1`"]
+    #[inline]
+    pub fn is_uctxifg1_1(&self) -> bool {
+        *self == UCTXIFG1R::UCTXIFG1_1
+    }
+}
+#[doc = "Possible values of the field `UCRXIFG2`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIFG2R {
+    #[doc = "No interrupt pending"]
+    UCRXIFG2_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG2_1,
+}
+impl UCRXIFG2R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIFG2R::UCRXIFG2_0 => false,
+            UCRXIFG2R::UCRXIFG2_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIFG2R {
+        match value {
+            false => UCRXIFG2R::UCRXIFG2_0,
+            true => UCRXIFG2R::UCRXIFG2_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG2_0`"]
+    #[inline]
+    pub fn is_ucrxifg2_0(&self) -> bool {
+        *self == UCRXIFG2R::UCRXIFG2_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG2_1`"]
+    #[inline]
+    pub fn is_ucrxifg2_1(&self) -> bool {
+        *self == UCRXIFG2R::UCRXIFG2_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIFG2`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIFG2R {
+    #[doc = "No interrupt pending"]
+    UCTXIFG2_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG2_1,
+}
+impl UCTXIFG2R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIFG2R::UCTXIFG2_0 => false,
+            UCTXIFG2R::UCTXIFG2_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIFG2R {
+        match value {
+            false => UCTXIFG2R::UCTXIFG2_0,
+            true => UCTXIFG2R::UCTXIFG2_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG2_0`"]
+    #[inline]
+    pub fn is_uctxifg2_0(&self) -> bool {
+        *self == UCTXIFG2R::UCTXIFG2_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG2_1`"]
+    #[inline]
+    pub fn is_uctxifg2_1(&self) -> bool {
+        *self == UCTXIFG2R::UCTXIFG2_1
+    }
+}
+#[doc = "Possible values of the field `UCRXIFG3`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIFG3R {
+    #[doc = "No interrupt pending"]
+    UCRXIFG3_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG3_1,
+}
+impl UCRXIFG3R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIFG3R::UCRXIFG3_0 => false,
+            UCRXIFG3R::UCRXIFG3_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIFG3R {
+        match value {
+            false => UCRXIFG3R::UCRXIFG3_0,
+            true => UCRXIFG3R::UCRXIFG3_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG3_0`"]
+    #[inline]
+    pub fn is_ucrxifg3_0(&self) -> bool {
+        *self == UCRXIFG3R::UCRXIFG3_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG3_1`"]
+    #[inline]
+    pub fn is_ucrxifg3_1(&self) -> bool {
+        *self == UCRXIFG3R::UCRXIFG3_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIFG3`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIFG3R {
+    #[doc = "No interrupt pending"]
+    UCTXIFG3_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG3_1,
+}
+impl UCTXIFG3R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIFG3R::UCTXIFG3_0 => false,
+            UCTXIFG3R::UCTXIFG3_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIFG3R {
+        match value {
+            false => UCTXIFG3R::UCTXIFG3_0,
+            true => UCTXIFG3R::UCTXIFG3_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG3_0`"]
+    #[inline]
+    pub fn is_uctxifg3_0(&self) -> bool {
+        *self == UCTXIFG3R::UCTXIFG3_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG3_1`"]
+    #[inline]
+    pub fn is_uctxifg3_1(&self) -> bool {
+        *self == UCTXIFG3R::UCTXIFG3_1
+    }
+}
+#[doc = "Possible values of the field `UCBIT9IFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBIT9IFGR {
+    #[doc = "No interrupt pending"]
+    UCBIT9IFG_0,
+    #[doc = "Interrupt pending"]
+    UCBIT9IFG_1,
+}
+impl UCBIT9IFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBIT9IFGR::UCBIT9IFG_0 => false,
+            UCBIT9IFGR::UCBIT9IFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBIT9IFGR {
+        match value {
+            false => UCBIT9IFGR::UCBIT9IFG_0,
+            true => UCBIT9IFGR::UCBIT9IFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBIT9IFG_0`"]
+    #[inline]
+    pub fn is_ucbit9ifg_0(&self) -> bool {
+        *self == UCBIT9IFGR::UCBIT9IFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCBIT9IFG_1`"]
+    #[inline]
+    pub fn is_ucbit9ifg_1(&self) -> bool {
+        *self == UCBIT9IFGR::UCBIT9IFG_1
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIFG0`"]
+pub enum UCRXIFG0W {
+    #[doc = "No interrupt pending"]
+    UCRXIFG0_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG0_1,
+}
+impl UCRXIFG0W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIFG0W::UCRXIFG0_0 => false,
+            UCRXIFG0W::UCRXIFG0_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIFG0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIFG0W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIFG0W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucrxifg0_0(self) -> &'a mut W {
+        self.variant(UCRXIFG0W::UCRXIFG0_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucrxifg0_1(self) -> &'a mut W {
+        self.variant(UCRXIFG0W::UCRXIFG0_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIFG0`"]
+pub enum UCTXIFG0W {
+    #[doc = "No interrupt pending"]
+    UCTXIFG0_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG0_1,
+}
+impl UCTXIFG0W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIFG0W::UCTXIFG0_0 => false,
+            UCTXIFG0W::UCTXIFG0_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIFG0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIFG0W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIFG0W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn uctxifg0_0(self) -> &'a mut W {
+        self.variant(UCTXIFG0W::UCTXIFG0_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn uctxifg0_1(self) -> &'a mut W {
+        self.variant(UCTXIFG0W::UCTXIFG0_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTTIFG`"]
+pub enum UCSTTIFGW {
+    #[doc = "No interrupt pending"]
+    UCSTTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCSTTIFG_1,
+}
+impl UCSTTIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTTIFGW::UCSTTIFG_0 => false,
+            UCSTTIFGW::UCSTTIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTTIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTTIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTTIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucsttifg_0(self) -> &'a mut W {
+        self.variant(UCSTTIFGW::UCSTTIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucsttifg_1(self) -> &'a mut W {
+        self.variant(UCSTTIFGW::UCSTTIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTPIFG`"]
+pub enum UCSTPIFGW {
+    #[doc = "No interrupt pending"]
+    UCSTPIFG_0,
+    #[doc = "Interrupt pending"]
+    UCSTPIFG_1,
+}
+impl UCSTPIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTPIFGW::UCSTPIFG_0 => false,
+            UCSTPIFGW::UCSTPIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTPIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTPIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTPIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucstpifg_0(self) -> &'a mut W {
+        self.variant(UCSTPIFGW::UCSTPIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucstpifg_1(self) -> &'a mut W {
+        self.variant(UCSTPIFGW::UCSTPIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCALIFG`"]
+pub enum UCALIFGW {
+    #[doc = "No interrupt pending"]
+    UCALIFG_0,
+    #[doc = "Interrupt pending"]
+    UCALIFG_1,
+}
+impl UCALIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCALIFGW::UCALIFG_0 => false,
+            UCALIFGW::UCALIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCALIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCALIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCALIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucalifg_0(self) -> &'a mut W {
+        self.variant(UCALIFGW::UCALIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucalifg_1(self) -> &'a mut W {
+        self.variant(UCALIFGW::UCALIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCNACKIFG`"]
+pub enum UCNACKIFGW {
+    #[doc = "No interrupt pending"]
+    UCNACKIFG_0,
+    #[doc = "Interrupt pending"]
+    UCNACKIFG_1,
+}
+impl UCNACKIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCNACKIFGW::UCNACKIFG_0 => false,
+            UCNACKIFGW::UCNACKIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCNACKIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCNACKIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCNACKIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucnackifg_0(self) -> &'a mut W {
+        self.variant(UCNACKIFGW::UCNACKIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucnackifg_1(self) -> &'a mut W {
+        self.variant(UCNACKIFGW::UCNACKIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCBCNTIFG`"]
+pub enum UCBCNTIFGW {
+    #[doc = "No interrupt pending"]
+    UCBCNTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCBCNTIFG_1,
+}
+impl UCBCNTIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCBCNTIFGW::UCBCNTIFG_0 => false,
+            UCBCNTIFGW::UCBCNTIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBCNTIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBCNTIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCBCNTIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucbcntifg_0(self) -> &'a mut W {
+        self.variant(UCBCNTIFGW::UCBCNTIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucbcntifg_1(self) -> &'a mut W {
+        self.variant(UCBCNTIFGW::UCBCNTIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCCLTOIFG`"]
+pub enum UCCLTOIFGW {
+    #[doc = "No interrupt pending"]
+    UCCLTOIFG_0,
+    #[doc = "Interrupt pending"]
+    UCCLTOIFG_1,
+}
+impl UCCLTOIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCCLTOIFGW::UCCLTOIFG_0 => false,
+            UCCLTOIFGW::UCCLTOIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCCLTOIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCCLTOIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCCLTOIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn uccltoifg_0(self) -> &'a mut W {
+        self.variant(UCCLTOIFGW::UCCLTOIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn uccltoifg_1(self) -> &'a mut W {
+        self.variant(UCCLTOIFGW::UCCLTOIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIFG1`"]
+pub enum UCRXIFG1W {
+    #[doc = "No interrupt pending"]
+    UCRXIFG1_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG1_1,
+}
+impl UCRXIFG1W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIFG1W::UCRXIFG1_0 => false,
+            UCRXIFG1W::UCRXIFG1_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIFG1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIFG1W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIFG1W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucrxifg1_0(self) -> &'a mut W {
+        self.variant(UCRXIFG1W::UCRXIFG1_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucrxifg1_1(self) -> &'a mut W {
+        self.variant(UCRXIFG1W::UCRXIFG1_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIFG1`"]
+pub enum UCTXIFG1W {
+    #[doc = "No interrupt pending"]
+    UCTXIFG1_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG1_1,
+}
+impl UCTXIFG1W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIFG1W::UCTXIFG1_0 => false,
+            UCTXIFG1W::UCTXIFG1_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIFG1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIFG1W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIFG1W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn uctxifg1_0(self) -> &'a mut W {
+        self.variant(UCTXIFG1W::UCTXIFG1_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn uctxifg1_1(self) -> &'a mut W {
+        self.variant(UCTXIFG1W::UCTXIFG1_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIFG2`"]
+pub enum UCRXIFG2W {
+    #[doc = "No interrupt pending"]
+    UCRXIFG2_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG2_1,
+}
+impl UCRXIFG2W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIFG2W::UCRXIFG2_0 => false,
+            UCRXIFG2W::UCRXIFG2_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIFG2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIFG2W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIFG2W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucrxifg2_0(self) -> &'a mut W {
+        self.variant(UCRXIFG2W::UCRXIFG2_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucrxifg2_1(self) -> &'a mut W {
+        self.variant(UCRXIFG2W::UCRXIFG2_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIFG2`"]
+pub enum UCTXIFG2W {
+    #[doc = "No interrupt pending"]
+    UCTXIFG2_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG2_1,
+}
+impl UCTXIFG2W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIFG2W::UCTXIFG2_0 => false,
+            UCTXIFG2W::UCTXIFG2_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIFG2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIFG2W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIFG2W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn uctxifg2_0(self) -> &'a mut W {
+        self.variant(UCTXIFG2W::UCTXIFG2_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn uctxifg2_1(self) -> &'a mut W {
+        self.variant(UCTXIFG2W::UCTXIFG2_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIFG3`"]
+pub enum UCRXIFG3W {
+    #[doc = "No interrupt pending"]
+    UCRXIFG3_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG3_1,
+}
+impl UCRXIFG3W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIFG3W::UCRXIFG3_0 => false,
+            UCRXIFG3W::UCRXIFG3_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIFG3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIFG3W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIFG3W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucrxifg3_0(self) -> &'a mut W {
+        self.variant(UCRXIFG3W::UCRXIFG3_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucrxifg3_1(self) -> &'a mut W {
+        self.variant(UCRXIFG3W::UCRXIFG3_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIFG3`"]
+pub enum UCTXIFG3W {
+    #[doc = "No interrupt pending"]
+    UCTXIFG3_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG3_1,
+}
+impl UCTXIFG3W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIFG3W::UCTXIFG3_0 => false,
+            UCTXIFG3W::UCTXIFG3_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIFG3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIFG3W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIFG3W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn uctxifg3_0(self) -> &'a mut W {
+        self.variant(UCTXIFG3W::UCTXIFG3_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn uctxifg3_1(self) -> &'a mut W {
+        self.variant(UCTXIFG3W::UCTXIFG3_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCBIT9IFG`"]
+pub enum UCBIT9IFGW {
+    #[doc = "No interrupt pending"]
+    UCBIT9IFG_0,
+    #[doc = "Interrupt pending"]
+    UCBIT9IFG_1,
+}
+impl UCBIT9IFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCBIT9IFGW::UCBIT9IFG_0 => false,
+            UCBIT9IFGW::UCBIT9IFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBIT9IFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBIT9IFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCBIT9IFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucbit9ifg_0(self) -> &'a mut W {
+        self.variant(UCBIT9IFGW::UCBIT9IFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucbit9ifg_1(self) -> &'a mut W {
+        self.variant(UCBIT9IFGW::UCBIT9IFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - eUSCI_B receive interrupt flag 0"]
+    #[inline]
+    pub fn ucrxifg0(&self) -> UCRXIFG0R {
+        UCRXIFG0R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - eUSCI_B transmit interrupt flag 0"]
+    #[inline]
+    pub fn uctxifg0(&self) -> UCTXIFG0R {
+        UCTXIFG0R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - START condition interrupt flag"]
+    #[inline]
+    pub fn ucsttifg(&self) -> UCSTTIFGR {
+        UCSTTIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - STOP condition interrupt flag"]
+    #[inline]
+    pub fn ucstpifg(&self) -> UCSTPIFGR {
+        UCSTPIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 4 - Arbitration lost interrupt flag"]
+    #[inline]
+    pub fn ucalifg(&self) -> UCALIFGR {
+        UCALIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - Not-acknowledge received interrupt flag"]
+    #[inline]
+    pub fn ucnackifg(&self) -> UCNACKIFGR {
+        UCNACKIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 6 - Byte counter interrupt flag"]
+    #[inline]
+    pub fn ucbcntifg(&self) -> UCBCNTIFGR {
+        UCBCNTIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 7 - Clock low timeout interrupt flag"]
+    #[inline]
+    pub fn uccltoifg(&self) -> UCCLTOIFGR {
+        UCCLTOIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 8 - eUSCI_B receive interrupt flag 1"]
+    #[inline]
+    pub fn ucrxifg1(&self) -> UCRXIFG1R {
+        UCRXIFG1R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 9 - eUSCI_B transmit interrupt flag 1"]
+    #[inline]
+    pub fn uctxifg1(&self) -> UCTXIFG1R {
+        UCTXIFG1R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 10 - eUSCI_B receive interrupt flag 2"]
+    #[inline]
+    pub fn ucrxifg2(&self) -> UCRXIFG2R {
+        UCRXIFG2R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 11 - eUSCI_B transmit interrupt flag 2"]
+    #[inline]
+    pub fn uctxifg2(&self) -> UCTXIFG2R {
+        UCTXIFG2R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 12 - eUSCI_B receive interrupt flag 3"]
+    #[inline]
+    pub fn ucrxifg3(&self) -> UCRXIFG3R {
+        UCRXIFG3R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 13 - eUSCI_B transmit interrupt flag 3"]
+    #[inline]
+    pub fn uctxifg3(&self) -> UCTXIFG3R {
+        UCTXIFG3R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 14 - Bit position 9 interrupt flag"]
+    #[inline]
+    pub fn ucbit9ifg(&self) -> UCBIT9IFGR {
+        UCBIT9IFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 2 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - eUSCI_B receive interrupt flag 0"]
+    #[inline]
+    pub fn ucrxifg0(&mut self) -> _UCRXIFG0W {
+        _UCRXIFG0W { w: self }
+    }
+    #[doc = "Bit 1 - eUSCI_B transmit interrupt flag 0"]
+    #[inline]
+    pub fn uctxifg0(&mut self) -> _UCTXIFG0W {
+        _UCTXIFG0W { w: self }
+    }
+    #[doc = "Bit 2 - START condition interrupt flag"]
+    #[inline]
+    pub fn ucsttifg(&mut self) -> _UCSTTIFGW {
+        _UCSTTIFGW { w: self }
+    }
+    #[doc = "Bit 3 - STOP condition interrupt flag"]
+    #[inline]
+    pub fn ucstpifg(&mut self) -> _UCSTPIFGW {
+        _UCSTPIFGW { w: self }
+    }
+    #[doc = "Bit 4 - Arbitration lost interrupt flag"]
+    #[inline]
+    pub fn ucalifg(&mut self) -> _UCALIFGW {
+        _UCALIFGW { w: self }
+    }
+    #[doc = "Bit 5 - Not-acknowledge received interrupt flag"]
+    #[inline]
+    pub fn ucnackifg(&mut self) -> _UCNACKIFGW {
+        _UCNACKIFGW { w: self }
+    }
+    #[doc = "Bit 6 - Byte counter interrupt flag"]
+    #[inline]
+    pub fn ucbcntifg(&mut self) -> _UCBCNTIFGW {
+        _UCBCNTIFGW { w: self }
+    }
+    #[doc = "Bit 7 - Clock low timeout interrupt flag"]
+    #[inline]
+    pub fn uccltoifg(&mut self) -> _UCCLTOIFGW {
+        _UCCLTOIFGW { w: self }
+    }
+    #[doc = "Bit 8 - eUSCI_B receive interrupt flag 1"]
+    #[inline]
+    pub fn ucrxifg1(&mut self) -> _UCRXIFG1W {
+        _UCRXIFG1W { w: self }
+    }
+    #[doc = "Bit 9 - eUSCI_B transmit interrupt flag 1"]
+    #[inline]
+    pub fn uctxifg1(&mut self) -> _UCTXIFG1W {
+        _UCTXIFG1W { w: self }
+    }
+    #[doc = "Bit 10 - eUSCI_B receive interrupt flag 2"]
+    #[inline]
+    pub fn ucrxifg2(&mut self) -> _UCRXIFG2W {
+        _UCRXIFG2W { w: self }
+    }
+    #[doc = "Bit 11 - eUSCI_B transmit interrupt flag 2"]
+    #[inline]
+    pub fn uctxifg2(&mut self) -> _UCTXIFG2W {
+        _UCTXIFG2W { w: self }
+    }
+    #[doc = "Bit 12 - eUSCI_B receive interrupt flag 3"]
+    #[inline]
+    pub fn ucrxifg3(&mut self) -> _UCRXIFG3W {
+        _UCRXIFG3W { w: self }
+    }
+    #[doc = "Bit 13 - eUSCI_B transmit interrupt flag 3"]
+    #[inline]
+    pub fn uctxifg3(&mut self) -> _UCTXIFG3W {
+        _UCTXIFG3W { w: self }
+    }
+    #[doc = "Bit 14 - Bit position 9 interrupt flag"]
+    #[inline]
+    pub fn ucbit9ifg(&mut self) -> _UCBIT9IFGW {
+        _UCBIT9IFGW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b1/ucbx_iv.rs b/example-source/msp432p401r/src/eusci_b1/ucbx_iv.rs
new file mode 100644
index 0000000..68af1a6
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b1/ucbx_iv.rs
@@ -0,0 +1,196 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::UCBXIV {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `UCIV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCIVR {
+    #[doc = "No interrupt pending"]
+    UCIV_0,
+    #[doc = "Interrupt Source: Arbitration lost; Interrupt Flag: UCALIFG; Interrupt Priority: Highest"]
+    UCIV_2,
+    #[doc = "Interrupt Source: Not acknowledgment; Interrupt Flag: UCNACKIFG"]
+    UCIV_4,
+    #[doc = "Interrupt Source: Start condition received; Interrupt Flag: UCSTTIFG"]
+    UCIV_6,
+    #[doc = "Interrupt Source: Stop condition received; Interrupt Flag: UCSTPIFG"]
+    UCIV_8,
+    #[doc = "Interrupt Source: Slave 3 Data received; Interrupt Flag: UCRXIFG3"]
+    UCIV_10,
+    #[doc = "Interrupt Source: Slave 3 Transmit buffer empty; Interrupt Flag: UCTXIFG3"]
+    UCIV_12,
+    #[doc = "Interrupt Source: Slave 2 Data received; Interrupt Flag: UCRXIFG2"]
+    UCIV_14,
+    #[doc = "Interrupt Source: Slave 2 Transmit buffer empty; Interrupt Flag: UCTXIFG2"]
+    UCIV_16,
+    #[doc = "Interrupt Source: Slave 1 Data received; Interrupt Flag: UCRXIFG1"]
+    UCIV_18,
+    #[doc = "Interrupt Source: Slave 1 Transmit buffer empty; Interrupt Flag: UCTXIFG1"]
+    UCIV_20,
+    #[doc = "Interrupt Source: Data received; Interrupt Flag: UCRXIFG0"]
+    UCIV_22,
+    #[doc = "Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG0"]
+    UCIV_24,
+    #[doc = "Interrupt Source: Byte counter zero; Interrupt Flag: UCBCNTIFG"]
+    UCIV_26,
+    #[doc = "Interrupt Source: Clock low timeout; Interrupt Flag: UCCLTOIFG"]
+    UCIV_28,
+    #[doc = "Interrupt Source: Nineth bit position; Interrupt Flag: UCBIT9IFG; Priority: Lowest"]
+    UCIV_30,
+    #[doc = r" Reserved"]
+    _Reserved(u16),
+}
+impl UCIVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        match *self {
+            UCIVR::UCIV_0 => 0,
+            UCIVR::UCIV_2 => 2,
+            UCIVR::UCIV_4 => 4,
+            UCIVR::UCIV_6 => 6,
+            UCIVR::UCIV_8 => 8,
+            UCIVR::UCIV_10 => 10,
+            UCIVR::UCIV_12 => 12,
+            UCIVR::UCIV_14 => 14,
+            UCIVR::UCIV_16 => 16,
+            UCIVR::UCIV_18 => 18,
+            UCIVR::UCIV_20 => 20,
+            UCIVR::UCIV_22 => 22,
+            UCIVR::UCIV_24 => 24,
+            UCIVR::UCIV_26 => 26,
+            UCIVR::UCIV_28 => 28,
+            UCIVR::UCIV_30 => 30,
+            UCIVR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u16) -> UCIVR {
+        match value {
+            0 => UCIVR::UCIV_0,
+            2 => UCIVR::UCIV_2,
+            4 => UCIVR::UCIV_4,
+            6 => UCIVR::UCIV_6,
+            8 => UCIVR::UCIV_8,
+            10 => UCIVR::UCIV_10,
+            12 => UCIVR::UCIV_12,
+            14 => UCIVR::UCIV_14,
+            16 => UCIVR::UCIV_16,
+            18 => UCIVR::UCIV_18,
+            20 => UCIVR::UCIV_20,
+            22 => UCIVR::UCIV_22,
+            24 => UCIVR::UCIV_24,
+            26 => UCIVR::UCIV_26,
+            28 => UCIVR::UCIV_28,
+            30 => UCIVR::UCIV_30,
+            i => UCIVR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCIV_0`"]
+    #[inline]
+    pub fn is_uciv_0(&self) -> bool {
+        *self == UCIVR::UCIV_0
+    }
+    #[doc = "Checks if the value of the field is `UCIV_2`"]
+    #[inline]
+    pub fn is_uciv_2(&self) -> bool {
+        *self == UCIVR::UCIV_2
+    }
+    #[doc = "Checks if the value of the field is `UCIV_4`"]
+    #[inline]
+    pub fn is_uciv_4(&self) -> bool {
+        *self == UCIVR::UCIV_4
+    }
+    #[doc = "Checks if the value of the field is `UCIV_6`"]
+    #[inline]
+    pub fn is_uciv_6(&self) -> bool {
+        *self == UCIVR::UCIV_6
+    }
+    #[doc = "Checks if the value of the field is `UCIV_8`"]
+    #[inline]
+    pub fn is_uciv_8(&self) -> bool {
+        *self == UCIVR::UCIV_8
+    }
+    #[doc = "Checks if the value of the field is `UCIV_10`"]
+    #[inline]
+    pub fn is_uciv_10(&self) -> bool {
+        *self == UCIVR::UCIV_10
+    }
+    #[doc = "Checks if the value of the field is `UCIV_12`"]
+    #[inline]
+    pub fn is_uciv_12(&self) -> bool {
+        *self == UCIVR::UCIV_12
+    }
+    #[doc = "Checks if the value of the field is `UCIV_14`"]
+    #[inline]
+    pub fn is_uciv_14(&self) -> bool {
+        *self == UCIVR::UCIV_14
+    }
+    #[doc = "Checks if the value of the field is `UCIV_16`"]
+    #[inline]
+    pub fn is_uciv_16(&self) -> bool {
+        *self == UCIVR::UCIV_16
+    }
+    #[doc = "Checks if the value of the field is `UCIV_18`"]
+    #[inline]
+    pub fn is_uciv_18(&self) -> bool {
+        *self == UCIVR::UCIV_18
+    }
+    #[doc = "Checks if the value of the field is `UCIV_20`"]
+    #[inline]
+    pub fn is_uciv_20(&self) -> bool {
+        *self == UCIVR::UCIV_20
+    }
+    #[doc = "Checks if the value of the field is `UCIV_22`"]
+    #[inline]
+    pub fn is_uciv_22(&self) -> bool {
+        *self == UCIVR::UCIV_22
+    }
+    #[doc = "Checks if the value of the field is `UCIV_24`"]
+    #[inline]
+    pub fn is_uciv_24(&self) -> bool {
+        *self == UCIVR::UCIV_24
+    }
+    #[doc = "Checks if the value of the field is `UCIV_26`"]
+    #[inline]
+    pub fn is_uciv_26(&self) -> bool {
+        *self == UCIVR::UCIV_26
+    }
+    #[doc = "Checks if the value of the field is `UCIV_28`"]
+    #[inline]
+    pub fn is_uciv_28(&self) -> bool {
+        *self == UCIVR::UCIV_28
+    }
+    #[doc = "Checks if the value of the field is `UCIV_30`"]
+    #[inline]
+    pub fn is_uciv_30(&self) -> bool {
+        *self == UCIVR::UCIV_30
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - eUSCI_B interrupt vector value"]
+    #[inline]
+    pub fn uciv(&self) -> UCIVR {
+        UCIVR::_from({
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b1/ucbx_rxbuf.rs b/example-source/msp432p401r/src/eusci_b1/ucbx_rxbuf.rs
new file mode 100644
index 0000000..74a7dd6
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b1/ucbx_rxbuf.rs
@@ -0,0 +1,41 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::UCBXRXBUF {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCRXBUFR {
+    bits: u8,
+}
+impl UCRXBUFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Receive data buffer"]
+    #[inline]
+    pub fn ucrxbuf(&self) -> UCRXBUFR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCRXBUFR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b1/ucbx_statw.rs b/example-source/msp432p401r/src/eusci_b1/ucbx_statw.rs
new file mode 100644
index 0000000..9f71700
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b1/ucbx_statw.rs
@@ -0,0 +1,253 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXSTATW {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCBBUSY`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBBUSYR {
+    #[doc = "Bus inactive"]
+    UCBBUSY_0,
+    #[doc = "Bus busy"]
+    UCBBUSY_1,
+}
+impl UCBBUSYR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBBUSYR::UCBBUSY_0 => false,
+            UCBBUSYR::UCBBUSY_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBBUSYR {
+        match value {
+            false => UCBBUSYR::UCBBUSY_0,
+            true => UCBBUSYR::UCBBUSY_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBBUSY_0`"]
+    #[inline]
+    pub fn is_ucbbusy_0(&self) -> bool {
+        *self == UCBBUSYR::UCBBUSY_0
+    }
+    #[doc = "Checks if the value of the field is `UCBBUSY_1`"]
+    #[inline]
+    pub fn is_ucbbusy_1(&self) -> bool {
+        *self == UCBBUSYR::UCBBUSY_1
+    }
+}
+#[doc = "Possible values of the field `UCGC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCGCR {
+    #[doc = "No general call address received"]
+    UCGC_0,
+    #[doc = "General call address received"]
+    UCGC_1,
+}
+impl UCGCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCGCR::UCGC_0 => false,
+            UCGCR::UCGC_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCGCR {
+        match value {
+            false => UCGCR::UCGC_0,
+            true => UCGCR::UCGC_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCGC_0`"]
+    #[inline]
+    pub fn is_ucgc_0(&self) -> bool {
+        *self == UCGCR::UCGC_0
+    }
+    #[doc = "Checks if the value of the field is `UCGC_1`"]
+    #[inline]
+    pub fn is_ucgc_1(&self) -> bool {
+        *self == UCGCR::UCGC_1
+    }
+}
+#[doc = "Possible values of the field `UCSCLLOW`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSCLLOWR {
+    #[doc = "SCL is not held low"]
+    UCSCLLOW_0,
+    #[doc = "SCL is held low"]
+    UCSCLLOW_1,
+}
+impl UCSCLLOWR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSCLLOWR::UCSCLLOW_0 => false,
+            UCSCLLOWR::UCSCLLOW_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSCLLOWR {
+        match value {
+            false => UCSCLLOWR::UCSCLLOW_0,
+            true => UCSCLLOWR::UCSCLLOW_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSCLLOW_0`"]
+    #[inline]
+    pub fn is_ucscllow_0(&self) -> bool {
+        *self == UCSCLLOWR::UCSCLLOW_0
+    }
+    #[doc = "Checks if the value of the field is `UCSCLLOW_1`"]
+    #[inline]
+    pub fn is_ucscllow_1(&self) -> bool {
+        *self == UCSCLLOWR::UCSCLLOW_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCBCNTR {
+    bits: u8,
+}
+impl UCBCNTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 4 - Bus busy"]
+    #[inline]
+    pub fn ucbbusy(&self) -> UCBBUSYR {
+        UCBBUSYR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - General call address received"]
+    #[inline]
+    pub fn ucgc(&self) -> UCGCR {
+        UCGCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 6 - SCL low"]
+    #[inline]
+    pub fn ucscllow(&self) -> UCSCLLOWR {
+        UCSCLLOWR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 8:15 - Hardware byte counter value"]
+    #[inline]
+    pub fn ucbcnt(&self) -> UCBCNTR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCBCNTR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b1/ucbx_tbcnt.rs b/example-source/msp432p401r/src/eusci_b1/ucbx_tbcnt.rs
new file mode 100644
index 0000000..52ef844
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b1/ucbx_tbcnt.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXTBCNT {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCTBCNTR {
+    bits: u8,
+}
+impl UCTBCNTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTBCNTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTBCNTW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Byte counter threshold value"]
+    #[inline]
+    pub fn uctbcnt(&self) -> UCTBCNTR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCTBCNTR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Byte counter threshold value"]
+    #[inline]
+    pub fn uctbcnt(&mut self) -> _UCTBCNTW {
+        _UCTBCNTW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b1/ucbx_txbuf.rs b/example-source/msp432p401r/src/eusci_b1/ucbx_txbuf.rs
new file mode 100644
index 0000000..2b787f2
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b1/ucbx_txbuf.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXTXBUF {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCTXBUFR {
+    bits: u8,
+}
+impl UCTXBUFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXBUFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXBUFW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Transmit data buffer"]
+    #[inline]
+    pub fn uctxbuf(&self) -> UCTXBUFR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCTXBUFR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Transmit data buffer"]
+    #[inline]
+    pub fn uctxbuf(&mut self) -> _UCTXBUFW {
+        _UCTXBUFW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b2.rs b/example-source/msp432p401r/src/eusci_b2.rs
new file mode 100644
index 0000000..e897801
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b2.rs
@@ -0,0 +1,143 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - eUSCI_Bx Control Word Register 0"]
+    pub ucbx_ctlw0: UCBXCTLW0,
+    #[doc = "0x02 - eUSCI_Bx Control Word Register 1"]
+    pub ucbx_ctlw1: UCBXCTLW1,
+    _reserved0: [u8; 2usize],
+    #[doc = "0x06 - eUSCI_Bx Baud Rate Control Word Register"]
+    pub ucbx_brw: UCBXBRW,
+    #[doc = "0x08 - eUSCI_Bx Status Register"]
+    pub ucbx_statw: UCBXSTATW,
+    #[doc = "0x0a - eUSCI_Bx Byte Counter Threshold Register"]
+    pub ucbx_tbcnt: UCBXTBCNT,
+    #[doc = "0x0c - eUSCI_Bx Receive Buffer Register"]
+    pub ucbx_rxbuf: UCBXRXBUF,
+    #[doc = "0x0e - eUSCI_Bx Transmit Buffer Register"]
+    pub ucbx_txbuf: UCBXTXBUF,
+    _reserved1: [u8; 4usize],
+    #[doc = "0x14 - eUSCI_Bx I2C Own Address 0 Register"]
+    pub ucbx_i2coa0: UCBXI2COA0,
+    #[doc = "0x16 - eUSCI_Bx I2C Own Address 1 Register"]
+    pub ucbx_i2coa1: UCBXI2COA1,
+    #[doc = "0x18 - eUSCI_Bx I2C Own Address 2 Register"]
+    pub ucbx_i2coa2: UCBXI2COA2,
+    #[doc = "0x1a - eUSCI_Bx I2C Own Address 3 Register"]
+    pub ucbx_i2coa3: UCBXI2COA3,
+    #[doc = "0x1c - eUSCI_Bx I2C Received Address Register"]
+    pub ucbx_addrx: UCBXADDRX,
+    #[doc = "0x1e - eUSCI_Bx I2C Address Mask Register"]
+    pub ucbx_addmask: UCBXADDMASK,
+    #[doc = "0x20 - eUSCI_Bx I2C Slave Address Register"]
+    pub ucbx_i2csa: UCBXI2CSA,
+    _reserved2: [u8; 8usize],
+    #[doc = "0x2a - eUSCI_Bx Interrupt Enable Register"]
+    pub ucbx_ie: UCBXIE,
+    #[doc = "0x2c - eUSCI_Bx Interrupt Flag Register"]
+    pub ucbx_ifg: UCBXIFG,
+    #[doc = "0x2e - eUSCI_Bx Interrupt Vector Register"]
+    pub ucbx_iv: UCBXIV,
+}
+#[doc = "eUSCI_Bx Control Word Register 0"]
+pub struct UCBXCTLW0 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Control Word Register 0"]
+pub mod ucbx_ctlw0;
+#[doc = "eUSCI_Bx Control Word Register 1"]
+pub struct UCBXCTLW1 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Control Word Register 1"]
+pub mod ucbx_ctlw1;
+#[doc = "eUSCI_Bx Baud Rate Control Word Register"]
+pub struct UCBXBRW {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Baud Rate Control Word Register"]
+pub mod ucbx_brw;
+#[doc = "eUSCI_Bx Status Register"]
+pub struct UCBXSTATW {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Status Register"]
+pub mod ucbx_statw;
+#[doc = "eUSCI_Bx Byte Counter Threshold Register"]
+pub struct UCBXTBCNT {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Byte Counter Threshold Register"]
+pub mod ucbx_tbcnt;
+#[doc = "eUSCI_Bx Receive Buffer Register"]
+pub struct UCBXRXBUF {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Receive Buffer Register"]
+pub mod ucbx_rxbuf;
+#[doc = "eUSCI_Bx Transmit Buffer Register"]
+pub struct UCBXTXBUF {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Transmit Buffer Register"]
+pub mod ucbx_txbuf;
+#[doc = "eUSCI_Bx I2C Own Address 0 Register"]
+pub struct UCBXI2COA0 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx I2C Own Address 0 Register"]
+pub mod ucbx_i2coa0;
+#[doc = "eUSCI_Bx I2C Own Address 1 Register"]
+pub struct UCBXI2COA1 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx I2C Own Address 1 Register"]
+pub mod ucbx_i2coa1;
+#[doc = "eUSCI_Bx I2C Own Address 2 Register"]
+pub struct UCBXI2COA2 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx I2C Own Address 2 Register"]
+pub mod ucbx_i2coa2;
+#[doc = "eUSCI_Bx I2C Own Address 3 Register"]
+pub struct UCBXI2COA3 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx I2C Own Address 3 Register"]
+pub mod ucbx_i2coa3;
+#[doc = "eUSCI_Bx I2C Received Address Register"]
+pub struct UCBXADDRX {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx I2C Received Address Register"]
+pub mod ucbx_addrx;
+#[doc = "eUSCI_Bx I2C Address Mask Register"]
+pub struct UCBXADDMASK {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx I2C Address Mask Register"]
+pub mod ucbx_addmask;
+#[doc = "eUSCI_Bx I2C Slave Address Register"]
+pub struct UCBXI2CSA {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx I2C Slave Address Register"]
+pub mod ucbx_i2csa;
+#[doc = "eUSCI_Bx Interrupt Enable Register"]
+pub struct UCBXIE {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Interrupt Enable Register"]
+pub mod ucbx_ie;
+#[doc = "eUSCI_Bx Interrupt Flag Register"]
+pub struct UCBXIFG {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Interrupt Flag Register"]
+pub mod ucbx_ifg;
+#[doc = "eUSCI_Bx Interrupt Vector Register"]
+pub struct UCBXIV {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Interrupt Vector Register"]
+pub mod ucbx_iv;
diff --git a/example-source/msp432p401r/src/eusci_b2/ucbx_addmask.rs b/example-source/msp432p401r/src/eusci_b2/ucbx_addmask.rs
new file mode 100644
index 0000000..856e7a6
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b2/ucbx_addmask.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXADDMASK {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ADDMASKR {
+    bits: u16,
+}
+impl ADDMASKR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADDMASKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADDMASKW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated. Modify only when UCSWRST = 1."]
+    #[inline]
+    pub fn addmask(&self) -> ADDMASKR {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        ADDMASKR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 1023 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:9 - Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated. Modify only when UCSWRST = 1."]
+    #[inline]
+    pub fn addmask(&mut self) -> _ADDMASKW {
+        _ADDMASKW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b2/ucbx_addrx.rs b/example-source/msp432p401r/src/eusci_b2/ucbx_addrx.rs
new file mode 100644
index 0000000..595f1cb
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b2/ucbx_addrx.rs
@@ -0,0 +1,41 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::UCBXADDRX {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ADDRXR {
+    bits: u16,
+}
+impl ADDRXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - Received Address Register"]
+    #[inline]
+    pub fn addrx(&self) -> ADDRXR {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        ADDRXR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b2/ucbx_brw.rs b/example-source/msp432p401r/src/eusci_b2/ucbx_brw.rs
new file mode 100644
index 0000000..1ed885e
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b2/ucbx_brw.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXBRW {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCBRR {
+    bits: u16,
+}
+impl UCBRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBRW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Bit clock prescaler"]
+    #[inline]
+    pub fn ucbr(&self) -> UCBRR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        UCBRR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Bit clock prescaler"]
+    #[inline]
+    pub fn ucbr(&mut self) -> _UCBRW {
+        _UCBRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b2/ucbx_ctlw0.rs b/example-source/msp432p401r/src/eusci_b2/ucbx_ctlw0.rs
new file mode 100644
index 0000000..4baf4f9
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b2/ucbx_ctlw0.rs
@@ -0,0 +1,1645 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXCTLW0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCSWRST`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSWRSTR {
+    #[doc = "Disabled. eUSCI_B reset released for operation"]
+    UCSWRST_0,
+    #[doc = "Enabled. eUSCI_B logic held in reset state"]
+    UCSWRST_1,
+}
+impl UCSWRSTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSWRSTR::UCSWRST_0 => false,
+            UCSWRSTR::UCSWRST_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSWRSTR {
+        match value {
+            false => UCSWRSTR::UCSWRST_0,
+            true => UCSWRSTR::UCSWRST_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSWRST_0`"]
+    #[inline]
+    pub fn is_ucswrst_0(&self) -> bool {
+        *self == UCSWRSTR::UCSWRST_0
+    }
+    #[doc = "Checks if the value of the field is `UCSWRST_1`"]
+    #[inline]
+    pub fn is_ucswrst_1(&self) -> bool {
+        *self == UCSWRSTR::UCSWRST_1
+    }
+}
+#[doc = "Possible values of the field `UCTXSTT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXSTTR {
+    #[doc = "Do not generate START condition"]
+    UCTXSTT_0,
+    #[doc = "Generate START condition"]
+    UCTXSTT_1,
+}
+impl UCTXSTTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXSTTR::UCTXSTT_0 => false,
+            UCTXSTTR::UCTXSTT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXSTTR {
+        match value {
+            false => UCTXSTTR::UCTXSTT_0,
+            true => UCTXSTTR::UCTXSTT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXSTT_0`"]
+    #[inline]
+    pub fn is_uctxstt_0(&self) -> bool {
+        *self == UCTXSTTR::UCTXSTT_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXSTT_1`"]
+    #[inline]
+    pub fn is_uctxstt_1(&self) -> bool {
+        *self == UCTXSTTR::UCTXSTT_1
+    }
+}
+#[doc = "Possible values of the field `UCTXSTP`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXSTPR {
+    #[doc = "No STOP generated"]
+    UCTXSTP_0,
+    #[doc = "Generate STOP"]
+    UCTXSTP_1,
+}
+impl UCTXSTPR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXSTPR::UCTXSTP_0 => false,
+            UCTXSTPR::UCTXSTP_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXSTPR {
+        match value {
+            false => UCTXSTPR::UCTXSTP_0,
+            true => UCTXSTPR::UCTXSTP_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXSTP_0`"]
+    #[inline]
+    pub fn is_uctxstp_0(&self) -> bool {
+        *self == UCTXSTPR::UCTXSTP_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXSTP_1`"]
+    #[inline]
+    pub fn is_uctxstp_1(&self) -> bool {
+        *self == UCTXSTPR::UCTXSTP_1
+    }
+}
+#[doc = "Possible values of the field `UCTXNACK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXNACKR {
+    #[doc = "Acknowledge normally"]
+    UCTXNACK_0,
+    #[doc = "Generate NACK"]
+    UCTXNACK_1,
+}
+impl UCTXNACKR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXNACKR::UCTXNACK_0 => false,
+            UCTXNACKR::UCTXNACK_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXNACKR {
+        match value {
+            false => UCTXNACKR::UCTXNACK_0,
+            true => UCTXNACKR::UCTXNACK_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXNACK_0`"]
+    #[inline]
+    pub fn is_uctxnack_0(&self) -> bool {
+        *self == UCTXNACKR::UCTXNACK_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXNACK_1`"]
+    #[inline]
+    pub fn is_uctxnack_1(&self) -> bool {
+        *self == UCTXNACKR::UCTXNACK_1
+    }
+}
+#[doc = "Possible values of the field `UCTR`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTRR {
+    #[doc = "Receiver"]
+    UCTR_0,
+    #[doc = "Transmitter"]
+    UCTR_1,
+}
+impl UCTRR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTRR::UCTR_0 => false,
+            UCTRR::UCTR_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTRR {
+        match value {
+            false => UCTRR::UCTR_0,
+            true => UCTRR::UCTR_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTR_0`"]
+    #[inline]
+    pub fn is_uctr_0(&self) -> bool {
+        *self == UCTRR::UCTR_0
+    }
+    #[doc = "Checks if the value of the field is `UCTR_1`"]
+    #[inline]
+    pub fn is_uctr_1(&self) -> bool {
+        *self == UCTRR::UCTR_1
+    }
+}
+#[doc = "Possible values of the field `UCTXACK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXACKR {
+    #[doc = "Do not acknowledge the slave address"]
+    UCTXACK_0,
+    #[doc = "Acknowledge the slave address"]
+    UCTXACK_1,
+}
+impl UCTXACKR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXACKR::UCTXACK_0 => false,
+            UCTXACKR::UCTXACK_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXACKR {
+        match value {
+            false => UCTXACKR::UCTXACK_0,
+            true => UCTXACKR::UCTXACK_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXACK_0`"]
+    #[inline]
+    pub fn is_uctxack_0(&self) -> bool {
+        *self == UCTXACKR::UCTXACK_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXACK_1`"]
+    #[inline]
+    pub fn is_uctxack_1(&self) -> bool {
+        *self == UCTXACKR::UCTXACK_1
+    }
+}
+#[doc = "Possible values of the field `UCSSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSSELR {
+    #[doc = "UCLKI"]
+    UCSSEL_0,
+    #[doc = "ACLK"]
+    UCSSEL_1,
+    #[doc = "SMCLK"]
+    UCSSEL_2,
+    #[doc = "SMCLK"]
+    UCSSEL_3,
+}
+impl UCSSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCSSELR::UCSSEL_0 => 0,
+            UCSSELR::UCSSEL_1 => 1,
+            UCSSELR::UCSSEL_2 => 2,
+            UCSSELR::UCSSEL_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCSSELR {
+        match value {
+            0 => UCSSELR::UCSSEL_0,
+            1 => UCSSELR::UCSSEL_1,
+            2 => UCSSELR::UCSSEL_2,
+            3 => UCSSELR::UCSSEL_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSSEL_0`"]
+    #[inline]
+    pub fn is_ucssel_0(&self) -> bool {
+        *self == UCSSELR::UCSSEL_0
+    }
+    #[doc = "Checks if the value of the field is `UCSSEL_1`"]
+    #[inline]
+    pub fn is_ucssel_1(&self) -> bool {
+        *self == UCSSELR::UCSSEL_1
+    }
+    #[doc = "Checks if the value of the field is `UCSSEL_2`"]
+    #[inline]
+    pub fn is_ucssel_2(&self) -> bool {
+        *self == UCSSELR::UCSSEL_2
+    }
+    #[doc = "Checks if the value of the field is `UCSSEL_3`"]
+    #[inline]
+    pub fn is_ucssel_3(&self) -> bool {
+        *self == UCSSELR::UCSSEL_3
+    }
+}
+#[doc = "Possible values of the field `UCSYNC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSYNCR {
+    #[doc = "Asynchronous mode"]
+    UCSYNC_0,
+    #[doc = "Synchronous mode"]
+    UCSYNC_1,
+}
+impl UCSYNCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSYNCR::UCSYNC_0 => false,
+            UCSYNCR::UCSYNC_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSYNCR {
+        match value {
+            false => UCSYNCR::UCSYNC_0,
+            true => UCSYNCR::UCSYNC_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSYNC_0`"]
+    #[inline]
+    pub fn is_ucsync_0(&self) -> bool {
+        *self == UCSYNCR::UCSYNC_0
+    }
+    #[doc = "Checks if the value of the field is `UCSYNC_1`"]
+    #[inline]
+    pub fn is_ucsync_1(&self) -> bool {
+        *self == UCSYNCR::UCSYNC_1
+    }
+}
+#[doc = "Possible values of the field `UCMODE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCMODER {
+    #[doc = "3-pin SPI"]
+    UCMODE_0,
+    #[doc = "4-pin SPI (master or slave enabled if STE = 1)"]
+    UCMODE_1,
+    #[doc = "4-pin SPI (master or slave enabled if STE = 0)"]
+    UCMODE_2,
+    #[doc = "I2C mode"]
+    UCMODE_3,
+}
+impl UCMODER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCMODER::UCMODE_0 => 0,
+            UCMODER::UCMODE_1 => 1,
+            UCMODER::UCMODE_2 => 2,
+            UCMODER::UCMODE_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCMODER {
+        match value {
+            0 => UCMODER::UCMODE_0,
+            1 => UCMODER::UCMODE_1,
+            2 => UCMODER::UCMODE_2,
+            3 => UCMODER::UCMODE_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_0`"]
+    #[inline]
+    pub fn is_ucmode_0(&self) -> bool {
+        *self == UCMODER::UCMODE_0
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_1`"]
+    #[inline]
+    pub fn is_ucmode_1(&self) -> bool {
+        *self == UCMODER::UCMODE_1
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_2`"]
+    #[inline]
+    pub fn is_ucmode_2(&self) -> bool {
+        *self == UCMODER::UCMODE_2
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_3`"]
+    #[inline]
+    pub fn is_ucmode_3(&self) -> bool {
+        *self == UCMODER::UCMODE_3
+    }
+}
+#[doc = "Possible values of the field `UCMST`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCMSTR {
+    #[doc = "Slave mode"]
+    UCMST_0,
+    #[doc = "Master mode"]
+    UCMST_1,
+}
+impl UCMSTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCMSTR::UCMST_0 => false,
+            UCMSTR::UCMST_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCMSTR {
+        match value {
+            false => UCMSTR::UCMST_0,
+            true => UCMSTR::UCMST_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCMST_0`"]
+    #[inline]
+    pub fn is_ucmst_0(&self) -> bool {
+        *self == UCMSTR::UCMST_0
+    }
+    #[doc = "Checks if the value of the field is `UCMST_1`"]
+    #[inline]
+    pub fn is_ucmst_1(&self) -> bool {
+        *self == UCMSTR::UCMST_1
+    }
+}
+#[doc = "Possible values of the field `UCMM`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCMMR {
+    #[doc = "Single master environment. There is no other master in the system. The address compare unit is disabled."]
+    UCMM_0,
+    #[doc = "Multi-master environment"]
+    UCMM_1,
+}
+impl UCMMR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCMMR::UCMM_0 => false,
+            UCMMR::UCMM_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCMMR {
+        match value {
+            false => UCMMR::UCMM_0,
+            true => UCMMR::UCMM_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCMM_0`"]
+    #[inline]
+    pub fn is_ucmm_0(&self) -> bool {
+        *self == UCMMR::UCMM_0
+    }
+    #[doc = "Checks if the value of the field is `UCMM_1`"]
+    #[inline]
+    pub fn is_ucmm_1(&self) -> bool {
+        *self == UCMMR::UCMM_1
+    }
+}
+#[doc = "Possible values of the field `UCSLA10`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSLA10R {
+    #[doc = "Address slave with 7-bit address"]
+    UCSLA10_0,
+    #[doc = "Address slave with 10-bit address"]
+    UCSLA10_1,
+}
+impl UCSLA10R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSLA10R::UCSLA10_0 => false,
+            UCSLA10R::UCSLA10_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSLA10R {
+        match value {
+            false => UCSLA10R::UCSLA10_0,
+            true => UCSLA10R::UCSLA10_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSLA10_0`"]
+    #[inline]
+    pub fn is_ucsla10_0(&self) -> bool {
+        *self == UCSLA10R::UCSLA10_0
+    }
+    #[doc = "Checks if the value of the field is `UCSLA10_1`"]
+    #[inline]
+    pub fn is_ucsla10_1(&self) -> bool {
+        *self == UCSLA10R::UCSLA10_1
+    }
+}
+#[doc = "Possible values of the field `UCA10`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCA10R {
+    #[doc = "Own address is a 7-bit address"]
+    UCA10_0,
+    #[doc = "Own address is a 10-bit address"]
+    UCA10_1,
+}
+impl UCA10R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCA10R::UCA10_0 => false,
+            UCA10R::UCA10_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCA10R {
+        match value {
+            false => UCA10R::UCA10_0,
+            true => UCA10R::UCA10_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCA10_0`"]
+    #[inline]
+    pub fn is_uca10_0(&self) -> bool {
+        *self == UCA10R::UCA10_0
+    }
+    #[doc = "Checks if the value of the field is `UCA10_1`"]
+    #[inline]
+    pub fn is_uca10_1(&self) -> bool {
+        *self == UCA10R::UCA10_1
+    }
+}
+#[doc = "Values that can be written to the field `UCSWRST`"]
+pub enum UCSWRSTW {
+    #[doc = "Disabled. eUSCI_B reset released for operation"]
+    UCSWRST_0,
+    #[doc = "Enabled. eUSCI_B logic held in reset state"]
+    UCSWRST_1,
+}
+impl UCSWRSTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSWRSTW::UCSWRST_0 => false,
+            UCSWRSTW::UCSWRST_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSWRSTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSWRSTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSWRSTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disabled. eUSCI_B reset released for operation"]
+    #[inline]
+    pub fn ucswrst_0(self) -> &'a mut W {
+        self.variant(UCSWRSTW::UCSWRST_0)
+    }
+    #[doc = "Enabled. eUSCI_B logic held in reset state"]
+    #[inline]
+    pub fn ucswrst_1(self) -> &'a mut W {
+        self.variant(UCSWRSTW::UCSWRST_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXSTT`"]
+pub enum UCTXSTTW {
+    #[doc = "Do not generate START condition"]
+    UCTXSTT_0,
+    #[doc = "Generate START condition"]
+    UCTXSTT_1,
+}
+impl UCTXSTTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXSTTW::UCTXSTT_0 => false,
+            UCTXSTTW::UCTXSTT_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXSTTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXSTTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXSTTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Do not generate START condition"]
+    #[inline]
+    pub fn uctxstt_0(self) -> &'a mut W {
+        self.variant(UCTXSTTW::UCTXSTT_0)
+    }
+    #[doc = "Generate START condition"]
+    #[inline]
+    pub fn uctxstt_1(self) -> &'a mut W {
+        self.variant(UCTXSTTW::UCTXSTT_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXSTP`"]
+pub enum UCTXSTPW {
+    #[doc = "No STOP generated"]
+    UCTXSTP_0,
+    #[doc = "Generate STOP"]
+    UCTXSTP_1,
+}
+impl UCTXSTPW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXSTPW::UCTXSTP_0 => false,
+            UCTXSTPW::UCTXSTP_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXSTPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXSTPW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXSTPW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No STOP generated"]
+    #[inline]
+    pub fn uctxstp_0(self) -> &'a mut W {
+        self.variant(UCTXSTPW::UCTXSTP_0)
+    }
+    #[doc = "Generate STOP"]
+    #[inline]
+    pub fn uctxstp_1(self) -> &'a mut W {
+        self.variant(UCTXSTPW::UCTXSTP_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXNACK`"]
+pub enum UCTXNACKW {
+    #[doc = "Acknowledge normally"]
+    UCTXNACK_0,
+    #[doc = "Generate NACK"]
+    UCTXNACK_1,
+}
+impl UCTXNACKW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXNACKW::UCTXNACK_0 => false,
+            UCTXNACKW::UCTXNACK_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXNACKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXNACKW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXNACKW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Acknowledge normally"]
+    #[inline]
+    pub fn uctxnack_0(self) -> &'a mut W {
+        self.variant(UCTXNACKW::UCTXNACK_0)
+    }
+    #[doc = "Generate NACK"]
+    #[inline]
+    pub fn uctxnack_1(self) -> &'a mut W {
+        self.variant(UCTXNACKW::UCTXNACK_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTR`"]
+pub enum UCTRW {
+    #[doc = "Receiver"]
+    UCTR_0,
+    #[doc = "Transmitter"]
+    UCTR_1,
+}
+impl UCTRW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTRW::UCTR_0 => false,
+            UCTRW::UCTR_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTRW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTRW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Receiver"]
+    #[inline]
+    pub fn uctr_0(self) -> &'a mut W {
+        self.variant(UCTRW::UCTR_0)
+    }
+    #[doc = "Transmitter"]
+    #[inline]
+    pub fn uctr_1(self) -> &'a mut W {
+        self.variant(UCTRW::UCTR_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXACK`"]
+pub enum UCTXACKW {
+    #[doc = "Do not acknowledge the slave address"]
+    UCTXACK_0,
+    #[doc = "Acknowledge the slave address"]
+    UCTXACK_1,
+}
+impl UCTXACKW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXACKW::UCTXACK_0 => false,
+            UCTXACKW::UCTXACK_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXACKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXACKW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXACKW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Do not acknowledge the slave address"]
+    #[inline]
+    pub fn uctxack_0(self) -> &'a mut W {
+        self.variant(UCTXACKW::UCTXACK_0)
+    }
+    #[doc = "Acknowledge the slave address"]
+    #[inline]
+    pub fn uctxack_1(self) -> &'a mut W {
+        self.variant(UCTXACKW::UCTXACK_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSSEL`"]
+pub enum UCSSELW {
+    #[doc = "UCLKI"]
+    UCSSEL_0,
+    #[doc = "ACLK"]
+    UCSSEL_1,
+    #[doc = "SMCLK"]
+    UCSSEL_2,
+    #[doc = "SMCLK"]
+    UCSSEL_3,
+}
+impl UCSSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCSSELW::UCSSEL_0 => 0,
+            UCSSELW::UCSSEL_1 => 1,
+            UCSSELW::UCSSEL_2 => 2,
+            UCSSELW::UCSSEL_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSSELW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "UCLKI"]
+    #[inline]
+    pub fn ucssel_0(self) -> &'a mut W {
+        self.variant(UCSSELW::UCSSEL_0)
+    }
+    #[doc = "ACLK"]
+    #[inline]
+    pub fn ucssel_1(self) -> &'a mut W {
+        self.variant(UCSSELW::UCSSEL_1)
+    }
+    #[doc = "SMCLK"]
+    #[inline]
+    pub fn ucssel_2(self) -> &'a mut W {
+        self.variant(UCSSELW::UCSSEL_2)
+    }
+    #[doc = "SMCLK"]
+    #[inline]
+    pub fn ucssel_3(self) -> &'a mut W {
+        self.variant(UCSSELW::UCSSEL_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSYNC`"]
+pub enum UCSYNCW {
+    #[doc = "Asynchronous mode"]
+    UCSYNC_0,
+    #[doc = "Synchronous mode"]
+    UCSYNC_1,
+}
+impl UCSYNCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSYNCW::UCSYNC_0 => false,
+            UCSYNCW::UCSYNC_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSYNCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSYNCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSYNCW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Asynchronous mode"]
+    #[inline]
+    pub fn ucsync_0(self) -> &'a mut W {
+        self.variant(UCSYNCW::UCSYNC_0)
+    }
+    #[doc = "Synchronous mode"]
+    #[inline]
+    pub fn ucsync_1(self) -> &'a mut W {
+        self.variant(UCSYNCW::UCSYNC_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCMODE`"]
+pub enum UCMODEW {
+    #[doc = "3-pin SPI"]
+    UCMODE_0,
+    #[doc = "4-pin SPI (master or slave enabled if STE = 1)"]
+    UCMODE_1,
+    #[doc = "4-pin SPI (master or slave enabled if STE = 0)"]
+    UCMODE_2,
+    #[doc = "I2C mode"]
+    UCMODE_3,
+}
+impl UCMODEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCMODEW::UCMODE_0 => 0,
+            UCMODEW::UCMODE_1 => 1,
+            UCMODEW::UCMODE_2 => 2,
+            UCMODEW::UCMODE_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCMODEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCMODEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCMODEW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "3-pin SPI"]
+    #[inline]
+    pub fn ucmode_0(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_0)
+    }
+    #[doc = "4-pin SPI (master or slave enabled if STE = 1)"]
+    #[inline]
+    pub fn ucmode_1(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_1)
+    }
+    #[doc = "4-pin SPI (master or slave enabled if STE = 0)"]
+    #[inline]
+    pub fn ucmode_2(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_2)
+    }
+    #[doc = "I2C mode"]
+    #[inline]
+    pub fn ucmode_3(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCMST`"]
+pub enum UCMSTW {
+    #[doc = "Slave mode"]
+    UCMST_0,
+    #[doc = "Master mode"]
+    UCMST_1,
+}
+impl UCMSTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCMSTW::UCMST_0 => false,
+            UCMSTW::UCMST_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCMSTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCMSTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCMSTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Slave mode"]
+    #[inline]
+    pub fn ucmst_0(self) -> &'a mut W {
+        self.variant(UCMSTW::UCMST_0)
+    }
+    #[doc = "Master mode"]
+    #[inline]
+    pub fn ucmst_1(self) -> &'a mut W {
+        self.variant(UCMSTW::UCMST_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCMM`"]
+pub enum UCMMW {
+    #[doc = "Single master environment. There is no other master in the system. The address compare unit is disabled."]
+    UCMM_0,
+    #[doc = "Multi-master environment"]
+    UCMM_1,
+}
+impl UCMMW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCMMW::UCMM_0 => false,
+            UCMMW::UCMM_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCMMW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCMMW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCMMW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Single master environment. There is no other master in the system. The address compare unit is disabled."]
+    #[inline]
+    pub fn ucmm_0(self) -> &'a mut W {
+        self.variant(UCMMW::UCMM_0)
+    }
+    #[doc = "Multi-master environment"]
+    #[inline]
+    pub fn ucmm_1(self) -> &'a mut W {
+        self.variant(UCMMW::UCMM_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSLA10`"]
+pub enum UCSLA10W {
+    #[doc = "Address slave with 7-bit address"]
+    UCSLA10_0,
+    #[doc = "Address slave with 10-bit address"]
+    UCSLA10_1,
+}
+impl UCSLA10W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSLA10W::UCSLA10_0 => false,
+            UCSLA10W::UCSLA10_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSLA10W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSLA10W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSLA10W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Address slave with 7-bit address"]
+    #[inline]
+    pub fn ucsla10_0(self) -> &'a mut W {
+        self.variant(UCSLA10W::UCSLA10_0)
+    }
+    #[doc = "Address slave with 10-bit address"]
+    #[inline]
+    pub fn ucsla10_1(self) -> &'a mut W {
+        self.variant(UCSLA10W::UCSLA10_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCA10`"]
+pub enum UCA10W {
+    #[doc = "Own address is a 7-bit address"]
+    UCA10_0,
+    #[doc = "Own address is a 10-bit address"]
+    UCA10_1,
+}
+impl UCA10W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCA10W::UCA10_0 => false,
+            UCA10W::UCA10_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCA10W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCA10W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCA10W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Own address is a 7-bit address"]
+    #[inline]
+    pub fn uca10_0(self) -> &'a mut W {
+        self.variant(UCA10W::UCA10_0)
+    }
+    #[doc = "Own address is a 10-bit address"]
+    #[inline]
+    pub fn uca10_1(self) -> &'a mut W {
+        self.variant(UCA10W::UCA10_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Software reset enable"]
+    #[inline]
+    pub fn ucswrst(&self) -> UCSWRSTR {
+        UCSWRSTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Transmit START condition in master mode"]
+    #[inline]
+    pub fn uctxstt(&self) -> UCTXSTTR {
+        UCTXSTTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - Transmit STOP condition in master mode"]
+    #[inline]
+    pub fn uctxstp(&self) -> UCTXSTPR {
+        UCTXSTPR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Transmit a NACK"]
+    #[inline]
+    pub fn uctxnack(&self) -> UCTXNACKR {
+        UCTXNACKR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 4 - Transmitter/receiver"]
+    #[inline]
+    pub fn uctr(&self) -> UCTRR {
+        UCTRR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - Transmit ACK condition in slave mode"]
+    #[inline]
+    pub fn uctxack(&self) -> UCTXACKR {
+        UCTXACKR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 6:7 - eUSCI_B clock source select"]
+    #[inline]
+    pub fn ucssel(&self) -> UCSSELR {
+        UCSSELR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 8 - Synchronous mode enable"]
+    #[inline]
+    pub fn ucsync(&self) -> UCSYNCR {
+        UCSYNCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 9:10 - eUSCI_B mode"]
+    #[inline]
+    pub fn ucmode(&self) -> UCMODER {
+        UCMODER::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 11 - Master mode select"]
+    #[inline]
+    pub fn ucmst(&self) -> UCMSTR {
+        UCMSTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 13 - Multi-master environment select"]
+    #[inline]
+    pub fn ucmm(&self) -> UCMMR {
+        UCMMR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 14 - Slave addressing mode select"]
+    #[inline]
+    pub fn ucsla10(&self) -> UCSLA10R {
+        UCSLA10R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 15 - Own addressing mode select"]
+    #[inline]
+    pub fn uca10(&self) -> UCA10R {
+        UCA10R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 449 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Software reset enable"]
+    #[inline]
+    pub fn ucswrst(&mut self) -> _UCSWRSTW {
+        _UCSWRSTW { w: self }
+    }
+    #[doc = "Bit 1 - Transmit START condition in master mode"]
+    #[inline]
+    pub fn uctxstt(&mut self) -> _UCTXSTTW {
+        _UCTXSTTW { w: self }
+    }
+    #[doc = "Bit 2 - Transmit STOP condition in master mode"]
+    #[inline]
+    pub fn uctxstp(&mut self) -> _UCTXSTPW {
+        _UCTXSTPW { w: self }
+    }
+    #[doc = "Bit 3 - Transmit a NACK"]
+    #[inline]
+    pub fn uctxnack(&mut self) -> _UCTXNACKW {
+        _UCTXNACKW { w: self }
+    }
+    #[doc = "Bit 4 - Transmitter/receiver"]
+    #[inline]
+    pub fn uctr(&mut self) -> _UCTRW {
+        _UCTRW { w: self }
+    }
+    #[doc = "Bit 5 - Transmit ACK condition in slave mode"]
+    #[inline]
+    pub fn uctxack(&mut self) -> _UCTXACKW {
+        _UCTXACKW { w: self }
+    }
+    #[doc = "Bits 6:7 - eUSCI_B clock source select"]
+    #[inline]
+    pub fn ucssel(&mut self) -> _UCSSELW {
+        _UCSSELW { w: self }
+    }
+    #[doc = "Bit 8 - Synchronous mode enable"]
+    #[inline]
+    pub fn ucsync(&mut self) -> _UCSYNCW {
+        _UCSYNCW { w: self }
+    }
+    #[doc = "Bits 9:10 - eUSCI_B mode"]
+    #[inline]
+    pub fn ucmode(&mut self) -> _UCMODEW {
+        _UCMODEW { w: self }
+    }
+    #[doc = "Bit 11 - Master mode select"]
+    #[inline]
+    pub fn ucmst(&mut self) -> _UCMSTW {
+        _UCMSTW { w: self }
+    }
+    #[doc = "Bit 13 - Multi-master environment select"]
+    #[inline]
+    pub fn ucmm(&mut self) -> _UCMMW {
+        _UCMMW { w: self }
+    }
+    #[doc = "Bit 14 - Slave addressing mode select"]
+    #[inline]
+    pub fn ucsla10(&mut self) -> _UCSLA10W {
+        _UCSLA10W { w: self }
+    }
+    #[doc = "Bit 15 - Own addressing mode select"]
+    #[inline]
+    pub fn uca10(&mut self) -> _UCA10W {
+        _UCA10W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b2/ucbx_ctlw1.rs b/example-source/msp432p401r/src/eusci_b2/ucbx_ctlw1.rs
new file mode 100644
index 0000000..64e2d04
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b2/ucbx_ctlw1.rs
@@ -0,0 +1,813 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXCTLW1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCGLIT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCGLITR {
+    #[doc = "50 ns"]
+    UCGLIT_0,
+    #[doc = "25 ns"]
+    UCGLIT_1,
+    #[doc = "12.5 ns"]
+    UCGLIT_2,
+    #[doc = "6.25 ns"]
+    UCGLIT_3,
+}
+impl UCGLITR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCGLITR::UCGLIT_0 => 0,
+            UCGLITR::UCGLIT_1 => 1,
+            UCGLITR::UCGLIT_2 => 2,
+            UCGLITR::UCGLIT_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCGLITR {
+        match value {
+            0 => UCGLITR::UCGLIT_0,
+            1 => UCGLITR::UCGLIT_1,
+            2 => UCGLITR::UCGLIT_2,
+            3 => UCGLITR::UCGLIT_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_0`"]
+    #[inline]
+    pub fn is_ucglit_0(&self) -> bool {
+        *self == UCGLITR::UCGLIT_0
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_1`"]
+    #[inline]
+    pub fn is_ucglit_1(&self) -> bool {
+        *self == UCGLITR::UCGLIT_1
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_2`"]
+    #[inline]
+    pub fn is_ucglit_2(&self) -> bool {
+        *self == UCGLITR::UCGLIT_2
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_3`"]
+    #[inline]
+    pub fn is_ucglit_3(&self) -> bool {
+        *self == UCGLITR::UCGLIT_3
+    }
+}
+#[doc = "Possible values of the field `UCASTP`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCASTPR {
+    #[doc = "No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care."]
+    UCASTP_0,
+    #[doc = "UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT"]
+    UCASTP_1,
+    #[doc = "A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold"]
+    UCASTP_2,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl UCASTPR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCASTPR::UCASTP_0 => 0,
+            UCASTPR::UCASTP_1 => 1,
+            UCASTPR::UCASTP_2 => 2,
+            UCASTPR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCASTPR {
+        match value {
+            0 => UCASTPR::UCASTP_0,
+            1 => UCASTPR::UCASTP_1,
+            2 => UCASTPR::UCASTP_2,
+            i => UCASTPR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCASTP_0`"]
+    #[inline]
+    pub fn is_ucastp_0(&self) -> bool {
+        *self == UCASTPR::UCASTP_0
+    }
+    #[doc = "Checks if the value of the field is `UCASTP_1`"]
+    #[inline]
+    pub fn is_ucastp_1(&self) -> bool {
+        *self == UCASTPR::UCASTP_1
+    }
+    #[doc = "Checks if the value of the field is `UCASTP_2`"]
+    #[inline]
+    pub fn is_ucastp_2(&self) -> bool {
+        *self == UCASTPR::UCASTP_2
+    }
+}
+#[doc = "Possible values of the field `UCSWACK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSWACKR {
+    #[doc = "The address acknowledge of the slave is controlled by the eUSCI_B module"]
+    UCSWACK_0,
+    #[doc = "The user needs to trigger the sending of the address ACK by issuing UCTXACK"]
+    UCSWACK_1,
+}
+impl UCSWACKR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSWACKR::UCSWACK_0 => false,
+            UCSWACKR::UCSWACK_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSWACKR {
+        match value {
+            false => UCSWACKR::UCSWACK_0,
+            true => UCSWACKR::UCSWACK_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSWACK_0`"]
+    #[inline]
+    pub fn is_ucswack_0(&self) -> bool {
+        *self == UCSWACKR::UCSWACK_0
+    }
+    #[doc = "Checks if the value of the field is `UCSWACK_1`"]
+    #[inline]
+    pub fn is_ucswack_1(&self) -> bool {
+        *self == UCSWACKR::UCSWACK_1
+    }
+}
+#[doc = "Possible values of the field `UCSTPNACK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTPNACKR {
+    #[doc = "Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard)"]
+    UCSTPNACK_0,
+    #[doc = "All bytes are acknowledged by the eUSCI_B when configured as master receiver"]
+    UCSTPNACK_1,
+}
+impl UCSTPNACKR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTPNACKR::UCSTPNACK_0 => false,
+            UCSTPNACKR::UCSTPNACK_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTPNACKR {
+        match value {
+            false => UCSTPNACKR::UCSTPNACK_0,
+            true => UCSTPNACKR::UCSTPNACK_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTPNACK_0`"]
+    #[inline]
+    pub fn is_ucstpnack_0(&self) -> bool {
+        *self == UCSTPNACKR::UCSTPNACK_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTPNACK_1`"]
+    #[inline]
+    pub fn is_ucstpnack_1(&self) -> bool {
+        *self == UCSTPNACKR::UCSTPNACK_1
+    }
+}
+#[doc = "Possible values of the field `UCCLTO`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCCLTOR {
+    #[doc = "Disable clock low timeout counter"]
+    UCCLTO_0,
+    #[doc = "135 000 SYSCLK cycles (approximately 28 ms)"]
+    UCCLTO_1,
+    #[doc = "150 000 SYSCLK cycles (approximately 31 ms)"]
+    UCCLTO_2,
+    #[doc = "165 000 SYSCLK cycles (approximately 34 ms)"]
+    UCCLTO_3,
+}
+impl UCCLTOR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCCLTOR::UCCLTO_0 => 0,
+            UCCLTOR::UCCLTO_1 => 1,
+            UCCLTOR::UCCLTO_2 => 2,
+            UCCLTOR::UCCLTO_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCCLTOR {
+        match value {
+            0 => UCCLTOR::UCCLTO_0,
+            1 => UCCLTOR::UCCLTO_1,
+            2 => UCCLTOR::UCCLTO_2,
+            3 => UCCLTOR::UCCLTO_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCCLTO_0`"]
+    #[inline]
+    pub fn is_ucclto_0(&self) -> bool {
+        *self == UCCLTOR::UCCLTO_0
+    }
+    #[doc = "Checks if the value of the field is `UCCLTO_1`"]
+    #[inline]
+    pub fn is_ucclto_1(&self) -> bool {
+        *self == UCCLTOR::UCCLTO_1
+    }
+    #[doc = "Checks if the value of the field is `UCCLTO_2`"]
+    #[inline]
+    pub fn is_ucclto_2(&self) -> bool {
+        *self == UCCLTOR::UCCLTO_2
+    }
+    #[doc = "Checks if the value of the field is `UCCLTO_3`"]
+    #[inline]
+    pub fn is_ucclto_3(&self) -> bool {
+        *self == UCCLTOR::UCCLTO_3
+    }
+}
+#[doc = "Possible values of the field `UCETXINT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCETXINTR {
+    #[doc = "UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit"]
+    UCETXINT_0,
+    #[doc = "UCTXIFG0 is set for each START condition"]
+    UCETXINT_1,
+}
+impl UCETXINTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCETXINTR::UCETXINT_0 => false,
+            UCETXINTR::UCETXINT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCETXINTR {
+        match value {
+            false => UCETXINTR::UCETXINT_0,
+            true => UCETXINTR::UCETXINT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCETXINT_0`"]
+    #[inline]
+    pub fn is_ucetxint_0(&self) -> bool {
+        *self == UCETXINTR::UCETXINT_0
+    }
+    #[doc = "Checks if the value of the field is `UCETXINT_1`"]
+    #[inline]
+    pub fn is_ucetxint_1(&self) -> bool {
+        *self == UCETXINTR::UCETXINT_1
+    }
+}
+#[doc = "Values that can be written to the field `UCGLIT`"]
+pub enum UCGLITW {
+    #[doc = "50 ns"]
+    UCGLIT_0,
+    #[doc = "25 ns"]
+    UCGLIT_1,
+    #[doc = "12.5 ns"]
+    UCGLIT_2,
+    #[doc = "6.25 ns"]
+    UCGLIT_3,
+}
+impl UCGLITW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCGLITW::UCGLIT_0 => 0,
+            UCGLITW::UCGLIT_1 => 1,
+            UCGLITW::UCGLIT_2 => 2,
+            UCGLITW::UCGLIT_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCGLITW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCGLITW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCGLITW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "50 ns"]
+    #[inline]
+    pub fn ucglit_0(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_0)
+    }
+    #[doc = "25 ns"]
+    #[inline]
+    pub fn ucglit_1(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_1)
+    }
+    #[doc = "12.5 ns"]
+    #[inline]
+    pub fn ucglit_2(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_2)
+    }
+    #[doc = "6.25 ns"]
+    #[inline]
+    pub fn ucglit_3(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCASTP`"]
+pub enum UCASTPW {
+    #[doc = "No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care."]
+    UCASTP_0,
+    #[doc = "UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT"]
+    UCASTP_1,
+    #[doc = "A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold"]
+    UCASTP_2,
+}
+impl UCASTPW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCASTPW::UCASTP_0 => 0,
+            UCASTPW::UCASTP_1 => 1,
+            UCASTPW::UCASTP_2 => 2,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCASTPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCASTPW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCASTPW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care."]
+    #[inline]
+    pub fn ucastp_0(self) -> &'a mut W {
+        self.variant(UCASTPW::UCASTP_0)
+    }
+    #[doc = "UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT"]
+    #[inline]
+    pub fn ucastp_1(self) -> &'a mut W {
+        self.variant(UCASTPW::UCASTP_1)
+    }
+    #[doc = "A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold"]
+    #[inline]
+    pub fn ucastp_2(self) -> &'a mut W {
+        self.variant(UCASTPW::UCASTP_2)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSWACK`"]
+pub enum UCSWACKW {
+    #[doc = "The address acknowledge of the slave is controlled by the eUSCI_B module"]
+    UCSWACK_0,
+    #[doc = "The user needs to trigger the sending of the address ACK by issuing UCTXACK"]
+    UCSWACK_1,
+}
+impl UCSWACKW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSWACKW::UCSWACK_0 => false,
+            UCSWACKW::UCSWACK_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSWACKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSWACKW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSWACKW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The address acknowledge of the slave is controlled by the eUSCI_B module"]
+    #[inline]
+    pub fn ucswack_0(self) -> &'a mut W {
+        self.variant(UCSWACKW::UCSWACK_0)
+    }
+    #[doc = "The user needs to trigger the sending of the address ACK by issuing UCTXACK"]
+    #[inline]
+    pub fn ucswack_1(self) -> &'a mut W {
+        self.variant(UCSWACKW::UCSWACK_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTPNACK`"]
+pub enum UCSTPNACKW {
+    #[doc = "Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard)"]
+    UCSTPNACK_0,
+    #[doc = "All bytes are acknowledged by the eUSCI_B when configured as master receiver"]
+    UCSTPNACK_1,
+}
+impl UCSTPNACKW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTPNACKW::UCSTPNACK_0 => false,
+            UCSTPNACKW::UCSTPNACK_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTPNACKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTPNACKW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTPNACKW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard)"]
+    #[inline]
+    pub fn ucstpnack_0(self) -> &'a mut W {
+        self.variant(UCSTPNACKW::UCSTPNACK_0)
+    }
+    #[doc = "All bytes are acknowledged by the eUSCI_B when configured as master receiver"]
+    #[inline]
+    pub fn ucstpnack_1(self) -> &'a mut W {
+        self.variant(UCSTPNACKW::UCSTPNACK_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCCLTO`"]
+pub enum UCCLTOW {
+    #[doc = "Disable clock low timeout counter"]
+    UCCLTO_0,
+    #[doc = "135 000 SYSCLK cycles (approximately 28 ms)"]
+    UCCLTO_1,
+    #[doc = "150 000 SYSCLK cycles (approximately 31 ms)"]
+    UCCLTO_2,
+    #[doc = "165 000 SYSCLK cycles (approximately 34 ms)"]
+    UCCLTO_3,
+}
+impl UCCLTOW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCCLTOW::UCCLTO_0 => 0,
+            UCCLTOW::UCCLTO_1 => 1,
+            UCCLTOW::UCCLTO_2 => 2,
+            UCCLTOW::UCCLTO_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCCLTOW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCCLTOW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCCLTOW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Disable clock low timeout counter"]
+    #[inline]
+    pub fn ucclto_0(self) -> &'a mut W {
+        self.variant(UCCLTOW::UCCLTO_0)
+    }
+    #[doc = "135 000 SYSCLK cycles (approximately 28 ms)"]
+    #[inline]
+    pub fn ucclto_1(self) -> &'a mut W {
+        self.variant(UCCLTOW::UCCLTO_1)
+    }
+    #[doc = "150 000 SYSCLK cycles (approximately 31 ms)"]
+    #[inline]
+    pub fn ucclto_2(self) -> &'a mut W {
+        self.variant(UCCLTOW::UCCLTO_2)
+    }
+    #[doc = "165 000 SYSCLK cycles (approximately 34 ms)"]
+    #[inline]
+    pub fn ucclto_3(self) -> &'a mut W {
+        self.variant(UCCLTOW::UCCLTO_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCETXINT`"]
+pub enum UCETXINTW {
+    #[doc = "UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit"]
+    UCETXINT_0,
+    #[doc = "UCTXIFG0 is set for each START condition"]
+    UCETXINT_1,
+}
+impl UCETXINTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCETXINTW::UCETXINT_0 => false,
+            UCETXINTW::UCETXINT_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCETXINTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCETXINTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCETXINTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit"]
+    #[inline]
+    pub fn ucetxint_0(self) -> &'a mut W {
+        self.variant(UCETXINTW::UCETXINT_0)
+    }
+    #[doc = "UCTXIFG0 is set for each START condition"]
+    #[inline]
+    pub fn ucetxint_1(self) -> &'a mut W {
+        self.variant(UCETXINTW::UCETXINT_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:1 - Deglitch time"]
+    #[inline]
+    pub fn ucglit(&self) -> UCGLITR {
+        UCGLITR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bits 2:3 - Automatic STOP condition generation"]
+    #[inline]
+    pub fn ucastp(&self) -> UCASTPR {
+        UCASTPR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 4 - SW or HW ACK control"]
+    #[inline]
+    pub fn ucswack(&self) -> UCSWACKR {
+        UCSWACKR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - ACK all master bytes"]
+    #[inline]
+    pub fn ucstpnack(&self) -> UCSTPNACKR {
+        UCSTPNACKR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 6:7 - Clock low timeout select"]
+    #[inline]
+    pub fn ucclto(&self) -> UCCLTOR {
+        UCCLTOR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 8 - Early UCTXIFG0"]
+    #[inline]
+    pub fn ucetxint(&self) -> UCETXINTR {
+        UCETXINTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 3 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:1 - Deglitch time"]
+    #[inline]
+    pub fn ucglit(&mut self) -> _UCGLITW {
+        _UCGLITW { w: self }
+    }
+    #[doc = "Bits 2:3 - Automatic STOP condition generation"]
+    #[inline]
+    pub fn ucastp(&mut self) -> _UCASTPW {
+        _UCASTPW { w: self }
+    }
+    #[doc = "Bit 4 - SW or HW ACK control"]
+    #[inline]
+    pub fn ucswack(&mut self) -> _UCSWACKW {
+        _UCSWACKW { w: self }
+    }
+    #[doc = "Bit 5 - ACK all master bytes"]
+    #[inline]
+    pub fn ucstpnack(&mut self) -> _UCSTPNACKW {
+        _UCSTPNACKW { w: self }
+    }
+    #[doc = "Bits 6:7 - Clock low timeout select"]
+    #[inline]
+    pub fn ucclto(&mut self) -> _UCCLTOW {
+        _UCCLTOW { w: self }
+    }
+    #[doc = "Bit 8 - Early UCTXIFG0"]
+    #[inline]
+    pub fn ucetxint(&mut self) -> _UCETXINTW {
+        _UCETXINTW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b2/ucbx_i2coa0.rs b/example-source/msp432p401r/src/eusci_b2/ucbx_i2coa0.rs
new file mode 100644
index 0000000..93003b5
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b2/ucbx_i2coa0.rs
@@ -0,0 +1,343 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXI2COA0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct I2COA0R {
+    bits: u16,
+}
+impl I2COA0R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `UCOAEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCOAENR {
+    #[doc = "The slave address defined in I2COA0 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA0 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCOAENR::UCOAEN_0 => false,
+            UCOAENR::UCOAEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCOAENR {
+        match value {
+            false => UCOAENR::UCOAEN_0,
+            true => UCOAENR::UCOAEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_0`"]
+    #[inline]
+    pub fn is_ucoaen_0(&self) -> bool {
+        *self == UCOAENR::UCOAEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_1`"]
+    #[inline]
+    pub fn is_ucoaen_1(&self) -> bool {
+        *self == UCOAENR::UCOAEN_1
+    }
+}
+#[doc = "Possible values of the field `UCGCEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCGCENR {
+    #[doc = "Do not respond to a general call"]
+    UCGCEN_0,
+    #[doc = "Respond to a general call"]
+    UCGCEN_1,
+}
+impl UCGCENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCGCENR::UCGCEN_0 => false,
+            UCGCENR::UCGCEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCGCENR {
+        match value {
+            false => UCGCENR::UCGCEN_0,
+            true => UCGCENR::UCGCEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCGCEN_0`"]
+    #[inline]
+    pub fn is_ucgcen_0(&self) -> bool {
+        *self == UCGCENR::UCGCEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCGCEN_1`"]
+    #[inline]
+    pub fn is_ucgcen_1(&self) -> bool {
+        *self == UCGCENR::UCGCEN_1
+    }
+}
+#[doc = r" Proxy"]
+pub struct _I2COA0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _I2COA0W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCOAEN`"]
+pub enum UCOAENW {
+    #[doc = "The slave address defined in I2COA0 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA0 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCOAENW::UCOAEN_0 => false,
+            UCOAENW::UCOAEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCOAENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCOAENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCOAENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The slave address defined in I2COA0 is disabled"]
+    #[inline]
+    pub fn ucoaen_0(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_0)
+    }
+    #[doc = "The slave address defined in I2COA0 is enabled"]
+    #[inline]
+    pub fn ucoaen_1(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCGCEN`"]
+pub enum UCGCENW {
+    #[doc = "Do not respond to a general call"]
+    UCGCEN_0,
+    #[doc = "Respond to a general call"]
+    UCGCEN_1,
+}
+impl UCGCENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCGCENW::UCGCEN_0 => false,
+            UCGCENW::UCGCEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCGCENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCGCENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCGCENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Do not respond to a general call"]
+    #[inline]
+    pub fn ucgcen_0(self) -> &'a mut W {
+        self.variant(UCGCENW::UCGCEN_0)
+    }
+    #[doc = "Respond to a general call"]
+    #[inline]
+    pub fn ucgcen_1(self) -> &'a mut W {
+        self.variant(UCGCENW::UCGCEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa0(&self) -> I2COA0R {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        I2COA0R { bits }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&self) -> UCOAENR {
+        UCOAENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 15 - General call response enable"]
+    #[inline]
+    pub fn ucgcen(&self) -> UCGCENR {
+        UCGCENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa0(&mut self) -> _I2COA0W {
+        _I2COA0W { w: self }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&mut self) -> _UCOAENW {
+        _UCOAENW { w: self }
+    }
+    #[doc = "Bit 15 - General call response enable"]
+    #[inline]
+    pub fn ucgcen(&mut self) -> _UCGCENW {
+        _UCGCENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b2/ucbx_i2coa1.rs b/example-source/msp432p401r/src/eusci_b2/ucbx_i2coa1.rs
new file mode 100644
index 0000000..660cba5
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b2/ucbx_i2coa1.rs
@@ -0,0 +1,224 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXI2COA1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct I2COA1R {
+    bits: u16,
+}
+impl I2COA1R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `UCOAEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCOAENR {
+    #[doc = "The slave address defined in I2COA1 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA1 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCOAENR::UCOAEN_0 => false,
+            UCOAENR::UCOAEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCOAENR {
+        match value {
+            false => UCOAENR::UCOAEN_0,
+            true => UCOAENR::UCOAEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_0`"]
+    #[inline]
+    pub fn is_ucoaen_0(&self) -> bool {
+        *self == UCOAENR::UCOAEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_1`"]
+    #[inline]
+    pub fn is_ucoaen_1(&self) -> bool {
+        *self == UCOAENR::UCOAEN_1
+    }
+}
+#[doc = r" Proxy"]
+pub struct _I2COA1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _I2COA1W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCOAEN`"]
+pub enum UCOAENW {
+    #[doc = "The slave address defined in I2COA1 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA1 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCOAENW::UCOAEN_0 => false,
+            UCOAENW::UCOAEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCOAENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCOAENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCOAENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The slave address defined in I2COA1 is disabled"]
+    #[inline]
+    pub fn ucoaen_0(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_0)
+    }
+    #[doc = "The slave address defined in I2COA1 is enabled"]
+    #[inline]
+    pub fn ucoaen_1(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa1(&self) -> I2COA1R {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        I2COA1R { bits }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&self) -> UCOAENR {
+        UCOAENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa1(&mut self) -> _I2COA1W {
+        _I2COA1W { w: self }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&mut self) -> _UCOAENW {
+        _UCOAENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b2/ucbx_i2coa2.rs b/example-source/msp432p401r/src/eusci_b2/ucbx_i2coa2.rs
new file mode 100644
index 0000000..4f3ceb5
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b2/ucbx_i2coa2.rs
@@ -0,0 +1,224 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXI2COA2 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct I2COA2R {
+    bits: u16,
+}
+impl I2COA2R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `UCOAEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCOAENR {
+    #[doc = "The slave address defined in I2COA2 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA2 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCOAENR::UCOAEN_0 => false,
+            UCOAENR::UCOAEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCOAENR {
+        match value {
+            false => UCOAENR::UCOAEN_0,
+            true => UCOAENR::UCOAEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_0`"]
+    #[inline]
+    pub fn is_ucoaen_0(&self) -> bool {
+        *self == UCOAENR::UCOAEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_1`"]
+    #[inline]
+    pub fn is_ucoaen_1(&self) -> bool {
+        *self == UCOAENR::UCOAEN_1
+    }
+}
+#[doc = r" Proxy"]
+pub struct _I2COA2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _I2COA2W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCOAEN`"]
+pub enum UCOAENW {
+    #[doc = "The slave address defined in I2COA2 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA2 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCOAENW::UCOAEN_0 => false,
+            UCOAENW::UCOAEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCOAENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCOAENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCOAENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The slave address defined in I2COA2 is disabled"]
+    #[inline]
+    pub fn ucoaen_0(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_0)
+    }
+    #[doc = "The slave address defined in I2COA2 is enabled"]
+    #[inline]
+    pub fn ucoaen_1(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa2(&self) -> I2COA2R {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        I2COA2R { bits }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&self) -> UCOAENR {
+        UCOAENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa2(&mut self) -> _I2COA2W {
+        _I2COA2W { w: self }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&mut self) -> _UCOAENW {
+        _UCOAENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b2/ucbx_i2coa3.rs b/example-source/msp432p401r/src/eusci_b2/ucbx_i2coa3.rs
new file mode 100644
index 0000000..8cab4f2
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b2/ucbx_i2coa3.rs
@@ -0,0 +1,224 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXI2COA3 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct I2COA3R {
+    bits: u16,
+}
+impl I2COA3R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `UCOAEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCOAENR {
+    #[doc = "The slave address defined in I2COA3 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA3 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCOAENR::UCOAEN_0 => false,
+            UCOAENR::UCOAEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCOAENR {
+        match value {
+            false => UCOAENR::UCOAEN_0,
+            true => UCOAENR::UCOAEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_0`"]
+    #[inline]
+    pub fn is_ucoaen_0(&self) -> bool {
+        *self == UCOAENR::UCOAEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_1`"]
+    #[inline]
+    pub fn is_ucoaen_1(&self) -> bool {
+        *self == UCOAENR::UCOAEN_1
+    }
+}
+#[doc = r" Proxy"]
+pub struct _I2COA3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _I2COA3W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCOAEN`"]
+pub enum UCOAENW {
+    #[doc = "The slave address defined in I2COA3 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA3 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCOAENW::UCOAEN_0 => false,
+            UCOAENW::UCOAEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCOAENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCOAENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCOAENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The slave address defined in I2COA3 is disabled"]
+    #[inline]
+    pub fn ucoaen_0(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_0)
+    }
+    #[doc = "The slave address defined in I2COA3 is enabled"]
+    #[inline]
+    pub fn ucoaen_1(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa3(&self) -> I2COA3R {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        I2COA3R { bits }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&self) -> UCOAENR {
+        UCOAENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa3(&mut self) -> _I2COA3W {
+        _I2COA3W { w: self }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&mut self) -> _UCOAENW {
+        _UCOAENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b2/ucbx_i2csa.rs b/example-source/msp432p401r/src/eusci_b2/ucbx_i2csa.rs
new file mode 100644
index 0000000..33de734
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b2/ucbx_i2csa.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXI2CSA {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct I2CSAR {
+    bits: u16,
+}
+impl I2CSAR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _I2CSAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _I2CSAW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - I2C slave address"]
+    #[inline]
+    pub fn i2csa(&self) -> I2CSAR {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        I2CSAR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:9 - I2C slave address"]
+    #[inline]
+    pub fn i2csa(&mut self) -> _I2CSAW {
+        _I2CSAW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b2/ucbx_ie.rs b/example-source/msp432p401r/src/eusci_b2/ucbx_ie.rs
new file mode 100644
index 0000000..7c9f18c
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b2/ucbx_ie.rs
@@ -0,0 +1,1849 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXIE {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCRXIE0`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIE0R {
+    #[doc = "Interrupt disabled"]
+    UCRXIE0_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE0_1,
+}
+impl UCRXIE0R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIE0R::UCRXIE0_0 => false,
+            UCRXIE0R::UCRXIE0_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIE0R {
+        match value {
+            false => UCRXIE0R::UCRXIE0_0,
+            true => UCRXIE0R::UCRXIE0_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE0_0`"]
+    #[inline]
+    pub fn is_ucrxie0_0(&self) -> bool {
+        *self == UCRXIE0R::UCRXIE0_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE0_1`"]
+    #[inline]
+    pub fn is_ucrxie0_1(&self) -> bool {
+        *self == UCRXIE0R::UCRXIE0_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIE0`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIE0R {
+    #[doc = "Interrupt disabled"]
+    UCTXIE0_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE0_1,
+}
+impl UCTXIE0R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIE0R::UCTXIE0_0 => false,
+            UCTXIE0R::UCTXIE0_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIE0R {
+        match value {
+            false => UCTXIE0R::UCTXIE0_0,
+            true => UCTXIE0R::UCTXIE0_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE0_0`"]
+    #[inline]
+    pub fn is_uctxie0_0(&self) -> bool {
+        *self == UCTXIE0R::UCTXIE0_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE0_1`"]
+    #[inline]
+    pub fn is_uctxie0_1(&self) -> bool {
+        *self == UCTXIE0R::UCTXIE0_1
+    }
+}
+#[doc = "Possible values of the field `UCSTTIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTTIER {
+    #[doc = "Interrupt disabled"]
+    UCSTTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCSTTIE_1,
+}
+impl UCSTTIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTTIER::UCSTTIE_0 => false,
+            UCSTTIER::UCSTTIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTTIER {
+        match value {
+            false => UCSTTIER::UCSTTIE_0,
+            true => UCSTTIER::UCSTTIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIE_0`"]
+    #[inline]
+    pub fn is_ucsttie_0(&self) -> bool {
+        *self == UCSTTIER::UCSTTIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIE_1`"]
+    #[inline]
+    pub fn is_ucsttie_1(&self) -> bool {
+        *self == UCSTTIER::UCSTTIE_1
+    }
+}
+#[doc = "Possible values of the field `UCSTPIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTPIER {
+    #[doc = "Interrupt disabled"]
+    UCSTPIE_0,
+    #[doc = "Interrupt enabled"]
+    UCSTPIE_1,
+}
+impl UCSTPIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTPIER::UCSTPIE_0 => false,
+            UCSTPIER::UCSTPIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTPIER {
+        match value {
+            false => UCSTPIER::UCSTPIE_0,
+            true => UCSTPIER::UCSTPIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTPIE_0`"]
+    #[inline]
+    pub fn is_ucstpie_0(&self) -> bool {
+        *self == UCSTPIER::UCSTPIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTPIE_1`"]
+    #[inline]
+    pub fn is_ucstpie_1(&self) -> bool {
+        *self == UCSTPIER::UCSTPIE_1
+    }
+}
+#[doc = "Possible values of the field `UCALIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCALIER {
+    #[doc = "Interrupt disabled"]
+    UCALIE_0,
+    #[doc = "Interrupt enabled"]
+    UCALIE_1,
+}
+impl UCALIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCALIER::UCALIE_0 => false,
+            UCALIER::UCALIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCALIER {
+        match value {
+            false => UCALIER::UCALIE_0,
+            true => UCALIER::UCALIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCALIE_0`"]
+    #[inline]
+    pub fn is_ucalie_0(&self) -> bool {
+        *self == UCALIER::UCALIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCALIE_1`"]
+    #[inline]
+    pub fn is_ucalie_1(&self) -> bool {
+        *self == UCALIER::UCALIE_1
+    }
+}
+#[doc = "Possible values of the field `UCNACKIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCNACKIER {
+    #[doc = "Interrupt disabled"]
+    UCNACKIE_0,
+    #[doc = "Interrupt enabled"]
+    UCNACKIE_1,
+}
+impl UCNACKIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCNACKIER::UCNACKIE_0 => false,
+            UCNACKIER::UCNACKIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCNACKIER {
+        match value {
+            false => UCNACKIER::UCNACKIE_0,
+            true => UCNACKIER::UCNACKIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCNACKIE_0`"]
+    #[inline]
+    pub fn is_ucnackie_0(&self) -> bool {
+        *self == UCNACKIER::UCNACKIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCNACKIE_1`"]
+    #[inline]
+    pub fn is_ucnackie_1(&self) -> bool {
+        *self == UCNACKIER::UCNACKIE_1
+    }
+}
+#[doc = "Possible values of the field `UCBCNTIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBCNTIER {
+    #[doc = "Interrupt disabled"]
+    UCBCNTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCBCNTIE_1,
+}
+impl UCBCNTIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBCNTIER::UCBCNTIE_0 => false,
+            UCBCNTIER::UCBCNTIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBCNTIER {
+        match value {
+            false => UCBCNTIER::UCBCNTIE_0,
+            true => UCBCNTIER::UCBCNTIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBCNTIE_0`"]
+    #[inline]
+    pub fn is_ucbcntie_0(&self) -> bool {
+        *self == UCBCNTIER::UCBCNTIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCBCNTIE_1`"]
+    #[inline]
+    pub fn is_ucbcntie_1(&self) -> bool {
+        *self == UCBCNTIER::UCBCNTIE_1
+    }
+}
+#[doc = "Possible values of the field `UCCLTOIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCCLTOIER {
+    #[doc = "Interrupt disabled"]
+    UCCLTOIE_0,
+    #[doc = "Interrupt enabled"]
+    UCCLTOIE_1,
+}
+impl UCCLTOIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCCLTOIER::UCCLTOIE_0 => false,
+            UCCLTOIER::UCCLTOIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCCLTOIER {
+        match value {
+            false => UCCLTOIER::UCCLTOIE_0,
+            true => UCCLTOIER::UCCLTOIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCCLTOIE_0`"]
+    #[inline]
+    pub fn is_uccltoie_0(&self) -> bool {
+        *self == UCCLTOIER::UCCLTOIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCCLTOIE_1`"]
+    #[inline]
+    pub fn is_uccltoie_1(&self) -> bool {
+        *self == UCCLTOIER::UCCLTOIE_1
+    }
+}
+#[doc = "Possible values of the field `UCRXIE1`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIE1R {
+    #[doc = "Interrupt disabled"]
+    UCRXIE1_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE1_1,
+}
+impl UCRXIE1R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIE1R::UCRXIE1_0 => false,
+            UCRXIE1R::UCRXIE1_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIE1R {
+        match value {
+            false => UCRXIE1R::UCRXIE1_0,
+            true => UCRXIE1R::UCRXIE1_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE1_0`"]
+    #[inline]
+    pub fn is_ucrxie1_0(&self) -> bool {
+        *self == UCRXIE1R::UCRXIE1_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE1_1`"]
+    #[inline]
+    pub fn is_ucrxie1_1(&self) -> bool {
+        *self == UCRXIE1R::UCRXIE1_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIE1`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIE1R {
+    #[doc = "Interrupt disabled"]
+    UCTXIE1_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE1_1,
+}
+impl UCTXIE1R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIE1R::UCTXIE1_0 => false,
+            UCTXIE1R::UCTXIE1_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIE1R {
+        match value {
+            false => UCTXIE1R::UCTXIE1_0,
+            true => UCTXIE1R::UCTXIE1_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE1_0`"]
+    #[inline]
+    pub fn is_uctxie1_0(&self) -> bool {
+        *self == UCTXIE1R::UCTXIE1_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE1_1`"]
+    #[inline]
+    pub fn is_uctxie1_1(&self) -> bool {
+        *self == UCTXIE1R::UCTXIE1_1
+    }
+}
+#[doc = "Possible values of the field `UCRXIE2`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIE2R {
+    #[doc = "Interrupt disabled"]
+    UCRXIE2_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE2_1,
+}
+impl UCRXIE2R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIE2R::UCRXIE2_0 => false,
+            UCRXIE2R::UCRXIE2_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIE2R {
+        match value {
+            false => UCRXIE2R::UCRXIE2_0,
+            true => UCRXIE2R::UCRXIE2_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE2_0`"]
+    #[inline]
+    pub fn is_ucrxie2_0(&self) -> bool {
+        *self == UCRXIE2R::UCRXIE2_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE2_1`"]
+    #[inline]
+    pub fn is_ucrxie2_1(&self) -> bool {
+        *self == UCRXIE2R::UCRXIE2_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIE2`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIE2R {
+    #[doc = "Interrupt disabled"]
+    UCTXIE2_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE2_1,
+}
+impl UCTXIE2R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIE2R::UCTXIE2_0 => false,
+            UCTXIE2R::UCTXIE2_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIE2R {
+        match value {
+            false => UCTXIE2R::UCTXIE2_0,
+            true => UCTXIE2R::UCTXIE2_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE2_0`"]
+    #[inline]
+    pub fn is_uctxie2_0(&self) -> bool {
+        *self == UCTXIE2R::UCTXIE2_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE2_1`"]
+    #[inline]
+    pub fn is_uctxie2_1(&self) -> bool {
+        *self == UCTXIE2R::UCTXIE2_1
+    }
+}
+#[doc = "Possible values of the field `UCRXIE3`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIE3R {
+    #[doc = "Interrupt disabled"]
+    UCRXIE3_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE3_1,
+}
+impl UCRXIE3R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIE3R::UCRXIE3_0 => false,
+            UCRXIE3R::UCRXIE3_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIE3R {
+        match value {
+            false => UCRXIE3R::UCRXIE3_0,
+            true => UCRXIE3R::UCRXIE3_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE3_0`"]
+    #[inline]
+    pub fn is_ucrxie3_0(&self) -> bool {
+        *self == UCRXIE3R::UCRXIE3_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE3_1`"]
+    #[inline]
+    pub fn is_ucrxie3_1(&self) -> bool {
+        *self == UCRXIE3R::UCRXIE3_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIE3`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIE3R {
+    #[doc = "Interrupt disabled"]
+    UCTXIE3_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE3_1,
+}
+impl UCTXIE3R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIE3R::UCTXIE3_0 => false,
+            UCTXIE3R::UCTXIE3_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIE3R {
+        match value {
+            false => UCTXIE3R::UCTXIE3_0,
+            true => UCTXIE3R::UCTXIE3_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE3_0`"]
+    #[inline]
+    pub fn is_uctxie3_0(&self) -> bool {
+        *self == UCTXIE3R::UCTXIE3_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE3_1`"]
+    #[inline]
+    pub fn is_uctxie3_1(&self) -> bool {
+        *self == UCTXIE3R::UCTXIE3_1
+    }
+}
+#[doc = "Possible values of the field `UCBIT9IE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBIT9IER {
+    #[doc = "Interrupt disabled"]
+    UCBIT9IE_0,
+    #[doc = "Interrupt enabled"]
+    UCBIT9IE_1,
+}
+impl UCBIT9IER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBIT9IER::UCBIT9IE_0 => false,
+            UCBIT9IER::UCBIT9IE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBIT9IER {
+        match value {
+            false => UCBIT9IER::UCBIT9IE_0,
+            true => UCBIT9IER::UCBIT9IE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBIT9IE_0`"]
+    #[inline]
+    pub fn is_ucbit9ie_0(&self) -> bool {
+        *self == UCBIT9IER::UCBIT9IE_0
+    }
+    #[doc = "Checks if the value of the field is `UCBIT9IE_1`"]
+    #[inline]
+    pub fn is_ucbit9ie_1(&self) -> bool {
+        *self == UCBIT9IER::UCBIT9IE_1
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIE0`"]
+pub enum UCRXIE0W {
+    #[doc = "Interrupt disabled"]
+    UCRXIE0_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE0_1,
+}
+impl UCRXIE0W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIE0W::UCRXIE0_0 => false,
+            UCRXIE0W::UCRXIE0_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIE0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIE0W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIE0W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucrxie0_0(self) -> &'a mut W {
+        self.variant(UCRXIE0W::UCRXIE0_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucrxie0_1(self) -> &'a mut W {
+        self.variant(UCRXIE0W::UCRXIE0_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIE0`"]
+pub enum UCTXIE0W {
+    #[doc = "Interrupt disabled"]
+    UCTXIE0_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE0_1,
+}
+impl UCTXIE0W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIE0W::UCTXIE0_0 => false,
+            UCTXIE0W::UCTXIE0_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIE0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIE0W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIE0W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn uctxie0_0(self) -> &'a mut W {
+        self.variant(UCTXIE0W::UCTXIE0_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn uctxie0_1(self) -> &'a mut W {
+        self.variant(UCTXIE0W::UCTXIE0_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTTIE`"]
+pub enum UCSTTIEW {
+    #[doc = "Interrupt disabled"]
+    UCSTTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCSTTIE_1,
+}
+impl UCSTTIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTTIEW::UCSTTIE_0 => false,
+            UCSTTIEW::UCSTTIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTTIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTTIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTTIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucsttie_0(self) -> &'a mut W {
+        self.variant(UCSTTIEW::UCSTTIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucsttie_1(self) -> &'a mut W {
+        self.variant(UCSTTIEW::UCSTTIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTPIE`"]
+pub enum UCSTPIEW {
+    #[doc = "Interrupt disabled"]
+    UCSTPIE_0,
+    #[doc = "Interrupt enabled"]
+    UCSTPIE_1,
+}
+impl UCSTPIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTPIEW::UCSTPIE_0 => false,
+            UCSTPIEW::UCSTPIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTPIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTPIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTPIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucstpie_0(self) -> &'a mut W {
+        self.variant(UCSTPIEW::UCSTPIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucstpie_1(self) -> &'a mut W {
+        self.variant(UCSTPIEW::UCSTPIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCALIE`"]
+pub enum UCALIEW {
+    #[doc = "Interrupt disabled"]
+    UCALIE_0,
+    #[doc = "Interrupt enabled"]
+    UCALIE_1,
+}
+impl UCALIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCALIEW::UCALIE_0 => false,
+            UCALIEW::UCALIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCALIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCALIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCALIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucalie_0(self) -> &'a mut W {
+        self.variant(UCALIEW::UCALIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucalie_1(self) -> &'a mut W {
+        self.variant(UCALIEW::UCALIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCNACKIE`"]
+pub enum UCNACKIEW {
+    #[doc = "Interrupt disabled"]
+    UCNACKIE_0,
+    #[doc = "Interrupt enabled"]
+    UCNACKIE_1,
+}
+impl UCNACKIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCNACKIEW::UCNACKIE_0 => false,
+            UCNACKIEW::UCNACKIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCNACKIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCNACKIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCNACKIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucnackie_0(self) -> &'a mut W {
+        self.variant(UCNACKIEW::UCNACKIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucnackie_1(self) -> &'a mut W {
+        self.variant(UCNACKIEW::UCNACKIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCBCNTIE`"]
+pub enum UCBCNTIEW {
+    #[doc = "Interrupt disabled"]
+    UCBCNTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCBCNTIE_1,
+}
+impl UCBCNTIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCBCNTIEW::UCBCNTIE_0 => false,
+            UCBCNTIEW::UCBCNTIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBCNTIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBCNTIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCBCNTIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucbcntie_0(self) -> &'a mut W {
+        self.variant(UCBCNTIEW::UCBCNTIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucbcntie_1(self) -> &'a mut W {
+        self.variant(UCBCNTIEW::UCBCNTIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCCLTOIE`"]
+pub enum UCCLTOIEW {
+    #[doc = "Interrupt disabled"]
+    UCCLTOIE_0,
+    #[doc = "Interrupt enabled"]
+    UCCLTOIE_1,
+}
+impl UCCLTOIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCCLTOIEW::UCCLTOIE_0 => false,
+            UCCLTOIEW::UCCLTOIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCCLTOIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCCLTOIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCCLTOIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn uccltoie_0(self) -> &'a mut W {
+        self.variant(UCCLTOIEW::UCCLTOIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn uccltoie_1(self) -> &'a mut W {
+        self.variant(UCCLTOIEW::UCCLTOIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIE1`"]
+pub enum UCRXIE1W {
+    #[doc = "Interrupt disabled"]
+    UCRXIE1_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE1_1,
+}
+impl UCRXIE1W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIE1W::UCRXIE1_0 => false,
+            UCRXIE1W::UCRXIE1_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIE1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIE1W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIE1W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucrxie1_0(self) -> &'a mut W {
+        self.variant(UCRXIE1W::UCRXIE1_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucrxie1_1(self) -> &'a mut W {
+        self.variant(UCRXIE1W::UCRXIE1_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIE1`"]
+pub enum UCTXIE1W {
+    #[doc = "Interrupt disabled"]
+    UCTXIE1_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE1_1,
+}
+impl UCTXIE1W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIE1W::UCTXIE1_0 => false,
+            UCTXIE1W::UCTXIE1_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIE1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIE1W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIE1W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn uctxie1_0(self) -> &'a mut W {
+        self.variant(UCTXIE1W::UCTXIE1_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn uctxie1_1(self) -> &'a mut W {
+        self.variant(UCTXIE1W::UCTXIE1_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIE2`"]
+pub enum UCRXIE2W {
+    #[doc = "Interrupt disabled"]
+    UCRXIE2_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE2_1,
+}
+impl UCRXIE2W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIE2W::UCRXIE2_0 => false,
+            UCRXIE2W::UCRXIE2_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIE2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIE2W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIE2W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucrxie2_0(self) -> &'a mut W {
+        self.variant(UCRXIE2W::UCRXIE2_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucrxie2_1(self) -> &'a mut W {
+        self.variant(UCRXIE2W::UCRXIE2_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIE2`"]
+pub enum UCTXIE2W {
+    #[doc = "Interrupt disabled"]
+    UCTXIE2_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE2_1,
+}
+impl UCTXIE2W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIE2W::UCTXIE2_0 => false,
+            UCTXIE2W::UCTXIE2_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIE2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIE2W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIE2W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn uctxie2_0(self) -> &'a mut W {
+        self.variant(UCTXIE2W::UCTXIE2_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn uctxie2_1(self) -> &'a mut W {
+        self.variant(UCTXIE2W::UCTXIE2_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIE3`"]
+pub enum UCRXIE3W {
+    #[doc = "Interrupt disabled"]
+    UCRXIE3_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE3_1,
+}
+impl UCRXIE3W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIE3W::UCRXIE3_0 => false,
+            UCRXIE3W::UCRXIE3_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIE3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIE3W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIE3W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucrxie3_0(self) -> &'a mut W {
+        self.variant(UCRXIE3W::UCRXIE3_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucrxie3_1(self) -> &'a mut W {
+        self.variant(UCRXIE3W::UCRXIE3_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIE3`"]
+pub enum UCTXIE3W {
+    #[doc = "Interrupt disabled"]
+    UCTXIE3_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE3_1,
+}
+impl UCTXIE3W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIE3W::UCTXIE3_0 => false,
+            UCTXIE3W::UCTXIE3_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIE3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIE3W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIE3W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn uctxie3_0(self) -> &'a mut W {
+        self.variant(UCTXIE3W::UCTXIE3_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn uctxie3_1(self) -> &'a mut W {
+        self.variant(UCTXIE3W::UCTXIE3_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCBIT9IE`"]
+pub enum UCBIT9IEW {
+    #[doc = "Interrupt disabled"]
+    UCBIT9IE_0,
+    #[doc = "Interrupt enabled"]
+    UCBIT9IE_1,
+}
+impl UCBIT9IEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCBIT9IEW::UCBIT9IE_0 => false,
+            UCBIT9IEW::UCBIT9IE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBIT9IEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBIT9IEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCBIT9IEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucbit9ie_0(self) -> &'a mut W {
+        self.variant(UCBIT9IEW::UCBIT9IE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucbit9ie_1(self) -> &'a mut W {
+        self.variant(UCBIT9IEW::UCBIT9IE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Receive interrupt enable 0"]
+    #[inline]
+    pub fn ucrxie0(&self) -> UCRXIE0R {
+        UCRXIE0R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Transmit interrupt enable 0"]
+    #[inline]
+    pub fn uctxie0(&self) -> UCTXIE0R {
+        UCTXIE0R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - START condition interrupt enable"]
+    #[inline]
+    pub fn ucsttie(&self) -> UCSTTIER {
+        UCSTTIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - STOP condition interrupt enable"]
+    #[inline]
+    pub fn ucstpie(&self) -> UCSTPIER {
+        UCSTPIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 4 - Arbitration lost interrupt enable"]
+    #[inline]
+    pub fn ucalie(&self) -> UCALIER {
+        UCALIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - Not-acknowledge interrupt enable"]
+    #[inline]
+    pub fn ucnackie(&self) -> UCNACKIER {
+        UCNACKIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 6 - Byte counter interrupt enable"]
+    #[inline]
+    pub fn ucbcntie(&self) -> UCBCNTIER {
+        UCBCNTIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 7 - Clock low timeout interrupt enable"]
+    #[inline]
+    pub fn uccltoie(&self) -> UCCLTOIER {
+        UCCLTOIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 8 - Receive interrupt enable 1"]
+    #[inline]
+    pub fn ucrxie1(&self) -> UCRXIE1R {
+        UCRXIE1R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 9 - Transmit interrupt enable 1"]
+    #[inline]
+    pub fn uctxie1(&self) -> UCTXIE1R {
+        UCTXIE1R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 10 - Receive interrupt enable 2"]
+    #[inline]
+    pub fn ucrxie2(&self) -> UCRXIE2R {
+        UCRXIE2R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 11 - Transmit interrupt enable 2"]
+    #[inline]
+    pub fn uctxie2(&self) -> UCTXIE2R {
+        UCTXIE2R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 12 - Receive interrupt enable 3"]
+    #[inline]
+    pub fn ucrxie3(&self) -> UCRXIE3R {
+        UCRXIE3R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 13 - Transmit interrupt enable 3"]
+    #[inline]
+    pub fn uctxie3(&self) -> UCTXIE3R {
+        UCTXIE3R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 14 - Bit position 9 interrupt enable"]
+    #[inline]
+    pub fn ucbit9ie(&self) -> UCBIT9IER {
+        UCBIT9IER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Receive interrupt enable 0"]
+    #[inline]
+    pub fn ucrxie0(&mut self) -> _UCRXIE0W {
+        _UCRXIE0W { w: self }
+    }
+    #[doc = "Bit 1 - Transmit interrupt enable 0"]
+    #[inline]
+    pub fn uctxie0(&mut self) -> _UCTXIE0W {
+        _UCTXIE0W { w: self }
+    }
+    #[doc = "Bit 2 - START condition interrupt enable"]
+    #[inline]
+    pub fn ucsttie(&mut self) -> _UCSTTIEW {
+        _UCSTTIEW { w: self }
+    }
+    #[doc = "Bit 3 - STOP condition interrupt enable"]
+    #[inline]
+    pub fn ucstpie(&mut self) -> _UCSTPIEW {
+        _UCSTPIEW { w: self }
+    }
+    #[doc = "Bit 4 - Arbitration lost interrupt enable"]
+    #[inline]
+    pub fn ucalie(&mut self) -> _UCALIEW {
+        _UCALIEW { w: self }
+    }
+    #[doc = "Bit 5 - Not-acknowledge interrupt enable"]
+    #[inline]
+    pub fn ucnackie(&mut self) -> _UCNACKIEW {
+        _UCNACKIEW { w: self }
+    }
+    #[doc = "Bit 6 - Byte counter interrupt enable"]
+    #[inline]
+    pub fn ucbcntie(&mut self) -> _UCBCNTIEW {
+        _UCBCNTIEW { w: self }
+    }
+    #[doc = "Bit 7 - Clock low timeout interrupt enable"]
+    #[inline]
+    pub fn uccltoie(&mut self) -> _UCCLTOIEW {
+        _UCCLTOIEW { w: self }
+    }
+    #[doc = "Bit 8 - Receive interrupt enable 1"]
+    #[inline]
+    pub fn ucrxie1(&mut self) -> _UCRXIE1W {
+        _UCRXIE1W { w: self }
+    }
+    #[doc = "Bit 9 - Transmit interrupt enable 1"]
+    #[inline]
+    pub fn uctxie1(&mut self) -> _UCTXIE1W {
+        _UCTXIE1W { w: self }
+    }
+    #[doc = "Bit 10 - Receive interrupt enable 2"]
+    #[inline]
+    pub fn ucrxie2(&mut self) -> _UCRXIE2W {
+        _UCRXIE2W { w: self }
+    }
+    #[doc = "Bit 11 - Transmit interrupt enable 2"]
+    #[inline]
+    pub fn uctxie2(&mut self) -> _UCTXIE2W {
+        _UCTXIE2W { w: self }
+    }
+    #[doc = "Bit 12 - Receive interrupt enable 3"]
+    #[inline]
+    pub fn ucrxie3(&mut self) -> _UCRXIE3W {
+        _UCRXIE3W { w: self }
+    }
+    #[doc = "Bit 13 - Transmit interrupt enable 3"]
+    #[inline]
+    pub fn uctxie3(&mut self) -> _UCTXIE3W {
+        _UCTXIE3W { w: self }
+    }
+    #[doc = "Bit 14 - Bit position 9 interrupt enable"]
+    #[inline]
+    pub fn ucbit9ie(&mut self) -> _UCBIT9IEW {
+        _UCBIT9IEW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b2/ucbx_ifg.rs b/example-source/msp432p401r/src/eusci_b2/ucbx_ifg.rs
new file mode 100644
index 0000000..28681c9
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b2/ucbx_ifg.rs
@@ -0,0 +1,1849 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXIFG {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCRXIFG0`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIFG0R {
+    #[doc = "No interrupt pending"]
+    UCRXIFG0_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG0_1,
+}
+impl UCRXIFG0R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIFG0R::UCRXIFG0_0 => false,
+            UCRXIFG0R::UCRXIFG0_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIFG0R {
+        match value {
+            false => UCRXIFG0R::UCRXIFG0_0,
+            true => UCRXIFG0R::UCRXIFG0_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG0_0`"]
+    #[inline]
+    pub fn is_ucrxifg0_0(&self) -> bool {
+        *self == UCRXIFG0R::UCRXIFG0_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG0_1`"]
+    #[inline]
+    pub fn is_ucrxifg0_1(&self) -> bool {
+        *self == UCRXIFG0R::UCRXIFG0_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIFG0`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIFG0R {
+    #[doc = "No interrupt pending"]
+    UCTXIFG0_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG0_1,
+}
+impl UCTXIFG0R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIFG0R::UCTXIFG0_0 => false,
+            UCTXIFG0R::UCTXIFG0_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIFG0R {
+        match value {
+            false => UCTXIFG0R::UCTXIFG0_0,
+            true => UCTXIFG0R::UCTXIFG0_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG0_0`"]
+    #[inline]
+    pub fn is_uctxifg0_0(&self) -> bool {
+        *self == UCTXIFG0R::UCTXIFG0_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG0_1`"]
+    #[inline]
+    pub fn is_uctxifg0_1(&self) -> bool {
+        *self == UCTXIFG0R::UCTXIFG0_1
+    }
+}
+#[doc = "Possible values of the field `UCSTTIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTTIFGR {
+    #[doc = "No interrupt pending"]
+    UCSTTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCSTTIFG_1,
+}
+impl UCSTTIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTTIFGR::UCSTTIFG_0 => false,
+            UCSTTIFGR::UCSTTIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTTIFGR {
+        match value {
+            false => UCSTTIFGR::UCSTTIFG_0,
+            true => UCSTTIFGR::UCSTTIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIFG_0`"]
+    #[inline]
+    pub fn is_ucsttifg_0(&self) -> bool {
+        *self == UCSTTIFGR::UCSTTIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIFG_1`"]
+    #[inline]
+    pub fn is_ucsttifg_1(&self) -> bool {
+        *self == UCSTTIFGR::UCSTTIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCSTPIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTPIFGR {
+    #[doc = "No interrupt pending"]
+    UCSTPIFG_0,
+    #[doc = "Interrupt pending"]
+    UCSTPIFG_1,
+}
+impl UCSTPIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTPIFGR::UCSTPIFG_0 => false,
+            UCSTPIFGR::UCSTPIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTPIFGR {
+        match value {
+            false => UCSTPIFGR::UCSTPIFG_0,
+            true => UCSTPIFGR::UCSTPIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTPIFG_0`"]
+    #[inline]
+    pub fn is_ucstpifg_0(&self) -> bool {
+        *self == UCSTPIFGR::UCSTPIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTPIFG_1`"]
+    #[inline]
+    pub fn is_ucstpifg_1(&self) -> bool {
+        *self == UCSTPIFGR::UCSTPIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCALIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCALIFGR {
+    #[doc = "No interrupt pending"]
+    UCALIFG_0,
+    #[doc = "Interrupt pending"]
+    UCALIFG_1,
+}
+impl UCALIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCALIFGR::UCALIFG_0 => false,
+            UCALIFGR::UCALIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCALIFGR {
+        match value {
+            false => UCALIFGR::UCALIFG_0,
+            true => UCALIFGR::UCALIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCALIFG_0`"]
+    #[inline]
+    pub fn is_ucalifg_0(&self) -> bool {
+        *self == UCALIFGR::UCALIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCALIFG_1`"]
+    #[inline]
+    pub fn is_ucalifg_1(&self) -> bool {
+        *self == UCALIFGR::UCALIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCNACKIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCNACKIFGR {
+    #[doc = "No interrupt pending"]
+    UCNACKIFG_0,
+    #[doc = "Interrupt pending"]
+    UCNACKIFG_1,
+}
+impl UCNACKIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCNACKIFGR::UCNACKIFG_0 => false,
+            UCNACKIFGR::UCNACKIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCNACKIFGR {
+        match value {
+            false => UCNACKIFGR::UCNACKIFG_0,
+            true => UCNACKIFGR::UCNACKIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCNACKIFG_0`"]
+    #[inline]
+    pub fn is_ucnackifg_0(&self) -> bool {
+        *self == UCNACKIFGR::UCNACKIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCNACKIFG_1`"]
+    #[inline]
+    pub fn is_ucnackifg_1(&self) -> bool {
+        *self == UCNACKIFGR::UCNACKIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCBCNTIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBCNTIFGR {
+    #[doc = "No interrupt pending"]
+    UCBCNTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCBCNTIFG_1,
+}
+impl UCBCNTIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBCNTIFGR::UCBCNTIFG_0 => false,
+            UCBCNTIFGR::UCBCNTIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBCNTIFGR {
+        match value {
+            false => UCBCNTIFGR::UCBCNTIFG_0,
+            true => UCBCNTIFGR::UCBCNTIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBCNTIFG_0`"]
+    #[inline]
+    pub fn is_ucbcntifg_0(&self) -> bool {
+        *self == UCBCNTIFGR::UCBCNTIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCBCNTIFG_1`"]
+    #[inline]
+    pub fn is_ucbcntifg_1(&self) -> bool {
+        *self == UCBCNTIFGR::UCBCNTIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCCLTOIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCCLTOIFGR {
+    #[doc = "No interrupt pending"]
+    UCCLTOIFG_0,
+    #[doc = "Interrupt pending"]
+    UCCLTOIFG_1,
+}
+impl UCCLTOIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCCLTOIFGR::UCCLTOIFG_0 => false,
+            UCCLTOIFGR::UCCLTOIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCCLTOIFGR {
+        match value {
+            false => UCCLTOIFGR::UCCLTOIFG_0,
+            true => UCCLTOIFGR::UCCLTOIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCCLTOIFG_0`"]
+    #[inline]
+    pub fn is_uccltoifg_0(&self) -> bool {
+        *self == UCCLTOIFGR::UCCLTOIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCCLTOIFG_1`"]
+    #[inline]
+    pub fn is_uccltoifg_1(&self) -> bool {
+        *self == UCCLTOIFGR::UCCLTOIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCRXIFG1`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIFG1R {
+    #[doc = "No interrupt pending"]
+    UCRXIFG1_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG1_1,
+}
+impl UCRXIFG1R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIFG1R::UCRXIFG1_0 => false,
+            UCRXIFG1R::UCRXIFG1_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIFG1R {
+        match value {
+            false => UCRXIFG1R::UCRXIFG1_0,
+            true => UCRXIFG1R::UCRXIFG1_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG1_0`"]
+    #[inline]
+    pub fn is_ucrxifg1_0(&self) -> bool {
+        *self == UCRXIFG1R::UCRXIFG1_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG1_1`"]
+    #[inline]
+    pub fn is_ucrxifg1_1(&self) -> bool {
+        *self == UCRXIFG1R::UCRXIFG1_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIFG1`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIFG1R {
+    #[doc = "No interrupt pending"]
+    UCTXIFG1_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG1_1,
+}
+impl UCTXIFG1R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIFG1R::UCTXIFG1_0 => false,
+            UCTXIFG1R::UCTXIFG1_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIFG1R {
+        match value {
+            false => UCTXIFG1R::UCTXIFG1_0,
+            true => UCTXIFG1R::UCTXIFG1_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG1_0`"]
+    #[inline]
+    pub fn is_uctxifg1_0(&self) -> bool {
+        *self == UCTXIFG1R::UCTXIFG1_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG1_1`"]
+    #[inline]
+    pub fn is_uctxifg1_1(&self) -> bool {
+        *self == UCTXIFG1R::UCTXIFG1_1
+    }
+}
+#[doc = "Possible values of the field `UCRXIFG2`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIFG2R {
+    #[doc = "No interrupt pending"]
+    UCRXIFG2_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG2_1,
+}
+impl UCRXIFG2R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIFG2R::UCRXIFG2_0 => false,
+            UCRXIFG2R::UCRXIFG2_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIFG2R {
+        match value {
+            false => UCRXIFG2R::UCRXIFG2_0,
+            true => UCRXIFG2R::UCRXIFG2_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG2_0`"]
+    #[inline]
+    pub fn is_ucrxifg2_0(&self) -> bool {
+        *self == UCRXIFG2R::UCRXIFG2_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG2_1`"]
+    #[inline]
+    pub fn is_ucrxifg2_1(&self) -> bool {
+        *self == UCRXIFG2R::UCRXIFG2_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIFG2`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIFG2R {
+    #[doc = "No interrupt pending"]
+    UCTXIFG2_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG2_1,
+}
+impl UCTXIFG2R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIFG2R::UCTXIFG2_0 => false,
+            UCTXIFG2R::UCTXIFG2_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIFG2R {
+        match value {
+            false => UCTXIFG2R::UCTXIFG2_0,
+            true => UCTXIFG2R::UCTXIFG2_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG2_0`"]
+    #[inline]
+    pub fn is_uctxifg2_0(&self) -> bool {
+        *self == UCTXIFG2R::UCTXIFG2_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG2_1`"]
+    #[inline]
+    pub fn is_uctxifg2_1(&self) -> bool {
+        *self == UCTXIFG2R::UCTXIFG2_1
+    }
+}
+#[doc = "Possible values of the field `UCRXIFG3`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIFG3R {
+    #[doc = "No interrupt pending"]
+    UCRXIFG3_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG3_1,
+}
+impl UCRXIFG3R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIFG3R::UCRXIFG3_0 => false,
+            UCRXIFG3R::UCRXIFG3_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIFG3R {
+        match value {
+            false => UCRXIFG3R::UCRXIFG3_0,
+            true => UCRXIFG3R::UCRXIFG3_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG3_0`"]
+    #[inline]
+    pub fn is_ucrxifg3_0(&self) -> bool {
+        *self == UCRXIFG3R::UCRXIFG3_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG3_1`"]
+    #[inline]
+    pub fn is_ucrxifg3_1(&self) -> bool {
+        *self == UCRXIFG3R::UCRXIFG3_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIFG3`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIFG3R {
+    #[doc = "No interrupt pending"]
+    UCTXIFG3_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG3_1,
+}
+impl UCTXIFG3R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIFG3R::UCTXIFG3_0 => false,
+            UCTXIFG3R::UCTXIFG3_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIFG3R {
+        match value {
+            false => UCTXIFG3R::UCTXIFG3_0,
+            true => UCTXIFG3R::UCTXIFG3_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG3_0`"]
+    #[inline]
+    pub fn is_uctxifg3_0(&self) -> bool {
+        *self == UCTXIFG3R::UCTXIFG3_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG3_1`"]
+    #[inline]
+    pub fn is_uctxifg3_1(&self) -> bool {
+        *self == UCTXIFG3R::UCTXIFG3_1
+    }
+}
+#[doc = "Possible values of the field `UCBIT9IFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBIT9IFGR {
+    #[doc = "No interrupt pending"]
+    UCBIT9IFG_0,
+    #[doc = "Interrupt pending"]
+    UCBIT9IFG_1,
+}
+impl UCBIT9IFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBIT9IFGR::UCBIT9IFG_0 => false,
+            UCBIT9IFGR::UCBIT9IFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBIT9IFGR {
+        match value {
+            false => UCBIT9IFGR::UCBIT9IFG_0,
+            true => UCBIT9IFGR::UCBIT9IFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBIT9IFG_0`"]
+    #[inline]
+    pub fn is_ucbit9ifg_0(&self) -> bool {
+        *self == UCBIT9IFGR::UCBIT9IFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCBIT9IFG_1`"]
+    #[inline]
+    pub fn is_ucbit9ifg_1(&self) -> bool {
+        *self == UCBIT9IFGR::UCBIT9IFG_1
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIFG0`"]
+pub enum UCRXIFG0W {
+    #[doc = "No interrupt pending"]
+    UCRXIFG0_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG0_1,
+}
+impl UCRXIFG0W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIFG0W::UCRXIFG0_0 => false,
+            UCRXIFG0W::UCRXIFG0_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIFG0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIFG0W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIFG0W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucrxifg0_0(self) -> &'a mut W {
+        self.variant(UCRXIFG0W::UCRXIFG0_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucrxifg0_1(self) -> &'a mut W {
+        self.variant(UCRXIFG0W::UCRXIFG0_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIFG0`"]
+pub enum UCTXIFG0W {
+    #[doc = "No interrupt pending"]
+    UCTXIFG0_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG0_1,
+}
+impl UCTXIFG0W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIFG0W::UCTXIFG0_0 => false,
+            UCTXIFG0W::UCTXIFG0_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIFG0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIFG0W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIFG0W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn uctxifg0_0(self) -> &'a mut W {
+        self.variant(UCTXIFG0W::UCTXIFG0_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn uctxifg0_1(self) -> &'a mut W {
+        self.variant(UCTXIFG0W::UCTXIFG0_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTTIFG`"]
+pub enum UCSTTIFGW {
+    #[doc = "No interrupt pending"]
+    UCSTTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCSTTIFG_1,
+}
+impl UCSTTIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTTIFGW::UCSTTIFG_0 => false,
+            UCSTTIFGW::UCSTTIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTTIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTTIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTTIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucsttifg_0(self) -> &'a mut W {
+        self.variant(UCSTTIFGW::UCSTTIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucsttifg_1(self) -> &'a mut W {
+        self.variant(UCSTTIFGW::UCSTTIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTPIFG`"]
+pub enum UCSTPIFGW {
+    #[doc = "No interrupt pending"]
+    UCSTPIFG_0,
+    #[doc = "Interrupt pending"]
+    UCSTPIFG_1,
+}
+impl UCSTPIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTPIFGW::UCSTPIFG_0 => false,
+            UCSTPIFGW::UCSTPIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTPIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTPIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTPIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucstpifg_0(self) -> &'a mut W {
+        self.variant(UCSTPIFGW::UCSTPIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucstpifg_1(self) -> &'a mut W {
+        self.variant(UCSTPIFGW::UCSTPIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCALIFG`"]
+pub enum UCALIFGW {
+    #[doc = "No interrupt pending"]
+    UCALIFG_0,
+    #[doc = "Interrupt pending"]
+    UCALIFG_1,
+}
+impl UCALIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCALIFGW::UCALIFG_0 => false,
+            UCALIFGW::UCALIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCALIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCALIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCALIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucalifg_0(self) -> &'a mut W {
+        self.variant(UCALIFGW::UCALIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucalifg_1(self) -> &'a mut W {
+        self.variant(UCALIFGW::UCALIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCNACKIFG`"]
+pub enum UCNACKIFGW {
+    #[doc = "No interrupt pending"]
+    UCNACKIFG_0,
+    #[doc = "Interrupt pending"]
+    UCNACKIFG_1,
+}
+impl UCNACKIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCNACKIFGW::UCNACKIFG_0 => false,
+            UCNACKIFGW::UCNACKIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCNACKIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCNACKIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCNACKIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucnackifg_0(self) -> &'a mut W {
+        self.variant(UCNACKIFGW::UCNACKIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucnackifg_1(self) -> &'a mut W {
+        self.variant(UCNACKIFGW::UCNACKIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCBCNTIFG`"]
+pub enum UCBCNTIFGW {
+    #[doc = "No interrupt pending"]
+    UCBCNTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCBCNTIFG_1,
+}
+impl UCBCNTIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCBCNTIFGW::UCBCNTIFG_0 => false,
+            UCBCNTIFGW::UCBCNTIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBCNTIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBCNTIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCBCNTIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucbcntifg_0(self) -> &'a mut W {
+        self.variant(UCBCNTIFGW::UCBCNTIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucbcntifg_1(self) -> &'a mut W {
+        self.variant(UCBCNTIFGW::UCBCNTIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCCLTOIFG`"]
+pub enum UCCLTOIFGW {
+    #[doc = "No interrupt pending"]
+    UCCLTOIFG_0,
+    #[doc = "Interrupt pending"]
+    UCCLTOIFG_1,
+}
+impl UCCLTOIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCCLTOIFGW::UCCLTOIFG_0 => false,
+            UCCLTOIFGW::UCCLTOIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCCLTOIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCCLTOIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCCLTOIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn uccltoifg_0(self) -> &'a mut W {
+        self.variant(UCCLTOIFGW::UCCLTOIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn uccltoifg_1(self) -> &'a mut W {
+        self.variant(UCCLTOIFGW::UCCLTOIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIFG1`"]
+pub enum UCRXIFG1W {
+    #[doc = "No interrupt pending"]
+    UCRXIFG1_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG1_1,
+}
+impl UCRXIFG1W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIFG1W::UCRXIFG1_0 => false,
+            UCRXIFG1W::UCRXIFG1_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIFG1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIFG1W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIFG1W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucrxifg1_0(self) -> &'a mut W {
+        self.variant(UCRXIFG1W::UCRXIFG1_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucrxifg1_1(self) -> &'a mut W {
+        self.variant(UCRXIFG1W::UCRXIFG1_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIFG1`"]
+pub enum UCTXIFG1W {
+    #[doc = "No interrupt pending"]
+    UCTXIFG1_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG1_1,
+}
+impl UCTXIFG1W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIFG1W::UCTXIFG1_0 => false,
+            UCTXIFG1W::UCTXIFG1_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIFG1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIFG1W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIFG1W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn uctxifg1_0(self) -> &'a mut W {
+        self.variant(UCTXIFG1W::UCTXIFG1_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn uctxifg1_1(self) -> &'a mut W {
+        self.variant(UCTXIFG1W::UCTXIFG1_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIFG2`"]
+pub enum UCRXIFG2W {
+    #[doc = "No interrupt pending"]
+    UCRXIFG2_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG2_1,
+}
+impl UCRXIFG2W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIFG2W::UCRXIFG2_0 => false,
+            UCRXIFG2W::UCRXIFG2_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIFG2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIFG2W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIFG2W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucrxifg2_0(self) -> &'a mut W {
+        self.variant(UCRXIFG2W::UCRXIFG2_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucrxifg2_1(self) -> &'a mut W {
+        self.variant(UCRXIFG2W::UCRXIFG2_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIFG2`"]
+pub enum UCTXIFG2W {
+    #[doc = "No interrupt pending"]
+    UCTXIFG2_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG2_1,
+}
+impl UCTXIFG2W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIFG2W::UCTXIFG2_0 => false,
+            UCTXIFG2W::UCTXIFG2_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIFG2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIFG2W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIFG2W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn uctxifg2_0(self) -> &'a mut W {
+        self.variant(UCTXIFG2W::UCTXIFG2_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn uctxifg2_1(self) -> &'a mut W {
+        self.variant(UCTXIFG2W::UCTXIFG2_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIFG3`"]
+pub enum UCRXIFG3W {
+    #[doc = "No interrupt pending"]
+    UCRXIFG3_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG3_1,
+}
+impl UCRXIFG3W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIFG3W::UCRXIFG3_0 => false,
+            UCRXIFG3W::UCRXIFG3_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIFG3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIFG3W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIFG3W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucrxifg3_0(self) -> &'a mut W {
+        self.variant(UCRXIFG3W::UCRXIFG3_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucrxifg3_1(self) -> &'a mut W {
+        self.variant(UCRXIFG3W::UCRXIFG3_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIFG3`"]
+pub enum UCTXIFG3W {
+    #[doc = "No interrupt pending"]
+    UCTXIFG3_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG3_1,
+}
+impl UCTXIFG3W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIFG3W::UCTXIFG3_0 => false,
+            UCTXIFG3W::UCTXIFG3_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIFG3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIFG3W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIFG3W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn uctxifg3_0(self) -> &'a mut W {
+        self.variant(UCTXIFG3W::UCTXIFG3_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn uctxifg3_1(self) -> &'a mut W {
+        self.variant(UCTXIFG3W::UCTXIFG3_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCBIT9IFG`"]
+pub enum UCBIT9IFGW {
+    #[doc = "No interrupt pending"]
+    UCBIT9IFG_0,
+    #[doc = "Interrupt pending"]
+    UCBIT9IFG_1,
+}
+impl UCBIT9IFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCBIT9IFGW::UCBIT9IFG_0 => false,
+            UCBIT9IFGW::UCBIT9IFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBIT9IFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBIT9IFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCBIT9IFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucbit9ifg_0(self) -> &'a mut W {
+        self.variant(UCBIT9IFGW::UCBIT9IFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucbit9ifg_1(self) -> &'a mut W {
+        self.variant(UCBIT9IFGW::UCBIT9IFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - eUSCI_B receive interrupt flag 0"]
+    #[inline]
+    pub fn ucrxifg0(&self) -> UCRXIFG0R {
+        UCRXIFG0R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - eUSCI_B transmit interrupt flag 0"]
+    #[inline]
+    pub fn uctxifg0(&self) -> UCTXIFG0R {
+        UCTXIFG0R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - START condition interrupt flag"]
+    #[inline]
+    pub fn ucsttifg(&self) -> UCSTTIFGR {
+        UCSTTIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - STOP condition interrupt flag"]
+    #[inline]
+    pub fn ucstpifg(&self) -> UCSTPIFGR {
+        UCSTPIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 4 - Arbitration lost interrupt flag"]
+    #[inline]
+    pub fn ucalifg(&self) -> UCALIFGR {
+        UCALIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - Not-acknowledge received interrupt flag"]
+    #[inline]
+    pub fn ucnackifg(&self) -> UCNACKIFGR {
+        UCNACKIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 6 - Byte counter interrupt flag"]
+    #[inline]
+    pub fn ucbcntifg(&self) -> UCBCNTIFGR {
+        UCBCNTIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 7 - Clock low timeout interrupt flag"]
+    #[inline]
+    pub fn uccltoifg(&self) -> UCCLTOIFGR {
+        UCCLTOIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 8 - eUSCI_B receive interrupt flag 1"]
+    #[inline]
+    pub fn ucrxifg1(&self) -> UCRXIFG1R {
+        UCRXIFG1R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 9 - eUSCI_B transmit interrupt flag 1"]
+    #[inline]
+    pub fn uctxifg1(&self) -> UCTXIFG1R {
+        UCTXIFG1R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 10 - eUSCI_B receive interrupt flag 2"]
+    #[inline]
+    pub fn ucrxifg2(&self) -> UCRXIFG2R {
+        UCRXIFG2R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 11 - eUSCI_B transmit interrupt flag 2"]
+    #[inline]
+    pub fn uctxifg2(&self) -> UCTXIFG2R {
+        UCTXIFG2R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 12 - eUSCI_B receive interrupt flag 3"]
+    #[inline]
+    pub fn ucrxifg3(&self) -> UCRXIFG3R {
+        UCRXIFG3R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 13 - eUSCI_B transmit interrupt flag 3"]
+    #[inline]
+    pub fn uctxifg3(&self) -> UCTXIFG3R {
+        UCTXIFG3R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 14 - Bit position 9 interrupt flag"]
+    #[inline]
+    pub fn ucbit9ifg(&self) -> UCBIT9IFGR {
+        UCBIT9IFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 2 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - eUSCI_B receive interrupt flag 0"]
+    #[inline]
+    pub fn ucrxifg0(&mut self) -> _UCRXIFG0W {
+        _UCRXIFG0W { w: self }
+    }
+    #[doc = "Bit 1 - eUSCI_B transmit interrupt flag 0"]
+    #[inline]
+    pub fn uctxifg0(&mut self) -> _UCTXIFG0W {
+        _UCTXIFG0W { w: self }
+    }
+    #[doc = "Bit 2 - START condition interrupt flag"]
+    #[inline]
+    pub fn ucsttifg(&mut self) -> _UCSTTIFGW {
+        _UCSTTIFGW { w: self }
+    }
+    #[doc = "Bit 3 - STOP condition interrupt flag"]
+    #[inline]
+    pub fn ucstpifg(&mut self) -> _UCSTPIFGW {
+        _UCSTPIFGW { w: self }
+    }
+    #[doc = "Bit 4 - Arbitration lost interrupt flag"]
+    #[inline]
+    pub fn ucalifg(&mut self) -> _UCALIFGW {
+        _UCALIFGW { w: self }
+    }
+    #[doc = "Bit 5 - Not-acknowledge received interrupt flag"]
+    #[inline]
+    pub fn ucnackifg(&mut self) -> _UCNACKIFGW {
+        _UCNACKIFGW { w: self }
+    }
+    #[doc = "Bit 6 - Byte counter interrupt flag"]
+    #[inline]
+    pub fn ucbcntifg(&mut self) -> _UCBCNTIFGW {
+        _UCBCNTIFGW { w: self }
+    }
+    #[doc = "Bit 7 - Clock low timeout interrupt flag"]
+    #[inline]
+    pub fn uccltoifg(&mut self) -> _UCCLTOIFGW {
+        _UCCLTOIFGW { w: self }
+    }
+    #[doc = "Bit 8 - eUSCI_B receive interrupt flag 1"]
+    #[inline]
+    pub fn ucrxifg1(&mut self) -> _UCRXIFG1W {
+        _UCRXIFG1W { w: self }
+    }
+    #[doc = "Bit 9 - eUSCI_B transmit interrupt flag 1"]
+    #[inline]
+    pub fn uctxifg1(&mut self) -> _UCTXIFG1W {
+        _UCTXIFG1W { w: self }
+    }
+    #[doc = "Bit 10 - eUSCI_B receive interrupt flag 2"]
+    #[inline]
+    pub fn ucrxifg2(&mut self) -> _UCRXIFG2W {
+        _UCRXIFG2W { w: self }
+    }
+    #[doc = "Bit 11 - eUSCI_B transmit interrupt flag 2"]
+    #[inline]
+    pub fn uctxifg2(&mut self) -> _UCTXIFG2W {
+        _UCTXIFG2W { w: self }
+    }
+    #[doc = "Bit 12 - eUSCI_B receive interrupt flag 3"]
+    #[inline]
+    pub fn ucrxifg3(&mut self) -> _UCRXIFG3W {
+        _UCRXIFG3W { w: self }
+    }
+    #[doc = "Bit 13 - eUSCI_B transmit interrupt flag 3"]
+    #[inline]
+    pub fn uctxifg3(&mut self) -> _UCTXIFG3W {
+        _UCTXIFG3W { w: self }
+    }
+    #[doc = "Bit 14 - Bit position 9 interrupt flag"]
+    #[inline]
+    pub fn ucbit9ifg(&mut self) -> _UCBIT9IFGW {
+        _UCBIT9IFGW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b2/ucbx_iv.rs b/example-source/msp432p401r/src/eusci_b2/ucbx_iv.rs
new file mode 100644
index 0000000..68af1a6
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b2/ucbx_iv.rs
@@ -0,0 +1,196 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::UCBXIV {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `UCIV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCIVR {
+    #[doc = "No interrupt pending"]
+    UCIV_0,
+    #[doc = "Interrupt Source: Arbitration lost; Interrupt Flag: UCALIFG; Interrupt Priority: Highest"]
+    UCIV_2,
+    #[doc = "Interrupt Source: Not acknowledgment; Interrupt Flag: UCNACKIFG"]
+    UCIV_4,
+    #[doc = "Interrupt Source: Start condition received; Interrupt Flag: UCSTTIFG"]
+    UCIV_6,
+    #[doc = "Interrupt Source: Stop condition received; Interrupt Flag: UCSTPIFG"]
+    UCIV_8,
+    #[doc = "Interrupt Source: Slave 3 Data received; Interrupt Flag: UCRXIFG3"]
+    UCIV_10,
+    #[doc = "Interrupt Source: Slave 3 Transmit buffer empty; Interrupt Flag: UCTXIFG3"]
+    UCIV_12,
+    #[doc = "Interrupt Source: Slave 2 Data received; Interrupt Flag: UCRXIFG2"]
+    UCIV_14,
+    #[doc = "Interrupt Source: Slave 2 Transmit buffer empty; Interrupt Flag: UCTXIFG2"]
+    UCIV_16,
+    #[doc = "Interrupt Source: Slave 1 Data received; Interrupt Flag: UCRXIFG1"]
+    UCIV_18,
+    #[doc = "Interrupt Source: Slave 1 Transmit buffer empty; Interrupt Flag: UCTXIFG1"]
+    UCIV_20,
+    #[doc = "Interrupt Source: Data received; Interrupt Flag: UCRXIFG0"]
+    UCIV_22,
+    #[doc = "Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG0"]
+    UCIV_24,
+    #[doc = "Interrupt Source: Byte counter zero; Interrupt Flag: UCBCNTIFG"]
+    UCIV_26,
+    #[doc = "Interrupt Source: Clock low timeout; Interrupt Flag: UCCLTOIFG"]
+    UCIV_28,
+    #[doc = "Interrupt Source: Nineth bit position; Interrupt Flag: UCBIT9IFG; Priority: Lowest"]
+    UCIV_30,
+    #[doc = r" Reserved"]
+    _Reserved(u16),
+}
+impl UCIVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        match *self {
+            UCIVR::UCIV_0 => 0,
+            UCIVR::UCIV_2 => 2,
+            UCIVR::UCIV_4 => 4,
+            UCIVR::UCIV_6 => 6,
+            UCIVR::UCIV_8 => 8,
+            UCIVR::UCIV_10 => 10,
+            UCIVR::UCIV_12 => 12,
+            UCIVR::UCIV_14 => 14,
+            UCIVR::UCIV_16 => 16,
+            UCIVR::UCIV_18 => 18,
+            UCIVR::UCIV_20 => 20,
+            UCIVR::UCIV_22 => 22,
+            UCIVR::UCIV_24 => 24,
+            UCIVR::UCIV_26 => 26,
+            UCIVR::UCIV_28 => 28,
+            UCIVR::UCIV_30 => 30,
+            UCIVR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u16) -> UCIVR {
+        match value {
+            0 => UCIVR::UCIV_0,
+            2 => UCIVR::UCIV_2,
+            4 => UCIVR::UCIV_4,
+            6 => UCIVR::UCIV_6,
+            8 => UCIVR::UCIV_8,
+            10 => UCIVR::UCIV_10,
+            12 => UCIVR::UCIV_12,
+            14 => UCIVR::UCIV_14,
+            16 => UCIVR::UCIV_16,
+            18 => UCIVR::UCIV_18,
+            20 => UCIVR::UCIV_20,
+            22 => UCIVR::UCIV_22,
+            24 => UCIVR::UCIV_24,
+            26 => UCIVR::UCIV_26,
+            28 => UCIVR::UCIV_28,
+            30 => UCIVR::UCIV_30,
+            i => UCIVR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCIV_0`"]
+    #[inline]
+    pub fn is_uciv_0(&self) -> bool {
+        *self == UCIVR::UCIV_0
+    }
+    #[doc = "Checks if the value of the field is `UCIV_2`"]
+    #[inline]
+    pub fn is_uciv_2(&self) -> bool {
+        *self == UCIVR::UCIV_2
+    }
+    #[doc = "Checks if the value of the field is `UCIV_4`"]
+    #[inline]
+    pub fn is_uciv_4(&self) -> bool {
+        *self == UCIVR::UCIV_4
+    }
+    #[doc = "Checks if the value of the field is `UCIV_6`"]
+    #[inline]
+    pub fn is_uciv_6(&self) -> bool {
+        *self == UCIVR::UCIV_6
+    }
+    #[doc = "Checks if the value of the field is `UCIV_8`"]
+    #[inline]
+    pub fn is_uciv_8(&self) -> bool {
+        *self == UCIVR::UCIV_8
+    }
+    #[doc = "Checks if the value of the field is `UCIV_10`"]
+    #[inline]
+    pub fn is_uciv_10(&self) -> bool {
+        *self == UCIVR::UCIV_10
+    }
+    #[doc = "Checks if the value of the field is `UCIV_12`"]
+    #[inline]
+    pub fn is_uciv_12(&self) -> bool {
+        *self == UCIVR::UCIV_12
+    }
+    #[doc = "Checks if the value of the field is `UCIV_14`"]
+    #[inline]
+    pub fn is_uciv_14(&self) -> bool {
+        *self == UCIVR::UCIV_14
+    }
+    #[doc = "Checks if the value of the field is `UCIV_16`"]
+    #[inline]
+    pub fn is_uciv_16(&self) -> bool {
+        *self == UCIVR::UCIV_16
+    }
+    #[doc = "Checks if the value of the field is `UCIV_18`"]
+    #[inline]
+    pub fn is_uciv_18(&self) -> bool {
+        *self == UCIVR::UCIV_18
+    }
+    #[doc = "Checks if the value of the field is `UCIV_20`"]
+    #[inline]
+    pub fn is_uciv_20(&self) -> bool {
+        *self == UCIVR::UCIV_20
+    }
+    #[doc = "Checks if the value of the field is `UCIV_22`"]
+    #[inline]
+    pub fn is_uciv_22(&self) -> bool {
+        *self == UCIVR::UCIV_22
+    }
+    #[doc = "Checks if the value of the field is `UCIV_24`"]
+    #[inline]
+    pub fn is_uciv_24(&self) -> bool {
+        *self == UCIVR::UCIV_24
+    }
+    #[doc = "Checks if the value of the field is `UCIV_26`"]
+    #[inline]
+    pub fn is_uciv_26(&self) -> bool {
+        *self == UCIVR::UCIV_26
+    }
+    #[doc = "Checks if the value of the field is `UCIV_28`"]
+    #[inline]
+    pub fn is_uciv_28(&self) -> bool {
+        *self == UCIVR::UCIV_28
+    }
+    #[doc = "Checks if the value of the field is `UCIV_30`"]
+    #[inline]
+    pub fn is_uciv_30(&self) -> bool {
+        *self == UCIVR::UCIV_30
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - eUSCI_B interrupt vector value"]
+    #[inline]
+    pub fn uciv(&self) -> UCIVR {
+        UCIVR::_from({
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b2/ucbx_rxbuf.rs b/example-source/msp432p401r/src/eusci_b2/ucbx_rxbuf.rs
new file mode 100644
index 0000000..74a7dd6
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b2/ucbx_rxbuf.rs
@@ -0,0 +1,41 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::UCBXRXBUF {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCRXBUFR {
+    bits: u8,
+}
+impl UCRXBUFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Receive data buffer"]
+    #[inline]
+    pub fn ucrxbuf(&self) -> UCRXBUFR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCRXBUFR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b2/ucbx_statw.rs b/example-source/msp432p401r/src/eusci_b2/ucbx_statw.rs
new file mode 100644
index 0000000..9f71700
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b2/ucbx_statw.rs
@@ -0,0 +1,253 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXSTATW {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCBBUSY`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBBUSYR {
+    #[doc = "Bus inactive"]
+    UCBBUSY_0,
+    #[doc = "Bus busy"]
+    UCBBUSY_1,
+}
+impl UCBBUSYR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBBUSYR::UCBBUSY_0 => false,
+            UCBBUSYR::UCBBUSY_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBBUSYR {
+        match value {
+            false => UCBBUSYR::UCBBUSY_0,
+            true => UCBBUSYR::UCBBUSY_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBBUSY_0`"]
+    #[inline]
+    pub fn is_ucbbusy_0(&self) -> bool {
+        *self == UCBBUSYR::UCBBUSY_0
+    }
+    #[doc = "Checks if the value of the field is `UCBBUSY_1`"]
+    #[inline]
+    pub fn is_ucbbusy_1(&self) -> bool {
+        *self == UCBBUSYR::UCBBUSY_1
+    }
+}
+#[doc = "Possible values of the field `UCGC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCGCR {
+    #[doc = "No general call address received"]
+    UCGC_0,
+    #[doc = "General call address received"]
+    UCGC_1,
+}
+impl UCGCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCGCR::UCGC_0 => false,
+            UCGCR::UCGC_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCGCR {
+        match value {
+            false => UCGCR::UCGC_0,
+            true => UCGCR::UCGC_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCGC_0`"]
+    #[inline]
+    pub fn is_ucgc_0(&self) -> bool {
+        *self == UCGCR::UCGC_0
+    }
+    #[doc = "Checks if the value of the field is `UCGC_1`"]
+    #[inline]
+    pub fn is_ucgc_1(&self) -> bool {
+        *self == UCGCR::UCGC_1
+    }
+}
+#[doc = "Possible values of the field `UCSCLLOW`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSCLLOWR {
+    #[doc = "SCL is not held low"]
+    UCSCLLOW_0,
+    #[doc = "SCL is held low"]
+    UCSCLLOW_1,
+}
+impl UCSCLLOWR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSCLLOWR::UCSCLLOW_0 => false,
+            UCSCLLOWR::UCSCLLOW_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSCLLOWR {
+        match value {
+            false => UCSCLLOWR::UCSCLLOW_0,
+            true => UCSCLLOWR::UCSCLLOW_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSCLLOW_0`"]
+    #[inline]
+    pub fn is_ucscllow_0(&self) -> bool {
+        *self == UCSCLLOWR::UCSCLLOW_0
+    }
+    #[doc = "Checks if the value of the field is `UCSCLLOW_1`"]
+    #[inline]
+    pub fn is_ucscllow_1(&self) -> bool {
+        *self == UCSCLLOWR::UCSCLLOW_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCBCNTR {
+    bits: u8,
+}
+impl UCBCNTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 4 - Bus busy"]
+    #[inline]
+    pub fn ucbbusy(&self) -> UCBBUSYR {
+        UCBBUSYR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - General call address received"]
+    #[inline]
+    pub fn ucgc(&self) -> UCGCR {
+        UCGCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 6 - SCL low"]
+    #[inline]
+    pub fn ucscllow(&self) -> UCSCLLOWR {
+        UCSCLLOWR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 8:15 - Hardware byte counter value"]
+    #[inline]
+    pub fn ucbcnt(&self) -> UCBCNTR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCBCNTR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b2/ucbx_tbcnt.rs b/example-source/msp432p401r/src/eusci_b2/ucbx_tbcnt.rs
new file mode 100644
index 0000000..52ef844
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b2/ucbx_tbcnt.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXTBCNT {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCTBCNTR {
+    bits: u8,
+}
+impl UCTBCNTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTBCNTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTBCNTW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Byte counter threshold value"]
+    #[inline]
+    pub fn uctbcnt(&self) -> UCTBCNTR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCTBCNTR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Byte counter threshold value"]
+    #[inline]
+    pub fn uctbcnt(&mut self) -> _UCTBCNTW {
+        _UCTBCNTW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b2/ucbx_txbuf.rs b/example-source/msp432p401r/src/eusci_b2/ucbx_txbuf.rs
new file mode 100644
index 0000000..2b787f2
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b2/ucbx_txbuf.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXTXBUF {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCTXBUFR {
+    bits: u8,
+}
+impl UCTXBUFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXBUFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXBUFW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Transmit data buffer"]
+    #[inline]
+    pub fn uctxbuf(&self) -> UCTXBUFR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCTXBUFR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Transmit data buffer"]
+    #[inline]
+    pub fn uctxbuf(&mut self) -> _UCTXBUFW {
+        _UCTXBUFW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b3.rs b/example-source/msp432p401r/src/eusci_b3.rs
new file mode 100644
index 0000000..e897801
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b3.rs
@@ -0,0 +1,143 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - eUSCI_Bx Control Word Register 0"]
+    pub ucbx_ctlw0: UCBXCTLW0,
+    #[doc = "0x02 - eUSCI_Bx Control Word Register 1"]
+    pub ucbx_ctlw1: UCBXCTLW1,
+    _reserved0: [u8; 2usize],
+    #[doc = "0x06 - eUSCI_Bx Baud Rate Control Word Register"]
+    pub ucbx_brw: UCBXBRW,
+    #[doc = "0x08 - eUSCI_Bx Status Register"]
+    pub ucbx_statw: UCBXSTATW,
+    #[doc = "0x0a - eUSCI_Bx Byte Counter Threshold Register"]
+    pub ucbx_tbcnt: UCBXTBCNT,
+    #[doc = "0x0c - eUSCI_Bx Receive Buffer Register"]
+    pub ucbx_rxbuf: UCBXRXBUF,
+    #[doc = "0x0e - eUSCI_Bx Transmit Buffer Register"]
+    pub ucbx_txbuf: UCBXTXBUF,
+    _reserved1: [u8; 4usize],
+    #[doc = "0x14 - eUSCI_Bx I2C Own Address 0 Register"]
+    pub ucbx_i2coa0: UCBXI2COA0,
+    #[doc = "0x16 - eUSCI_Bx I2C Own Address 1 Register"]
+    pub ucbx_i2coa1: UCBXI2COA1,
+    #[doc = "0x18 - eUSCI_Bx I2C Own Address 2 Register"]
+    pub ucbx_i2coa2: UCBXI2COA2,
+    #[doc = "0x1a - eUSCI_Bx I2C Own Address 3 Register"]
+    pub ucbx_i2coa3: UCBXI2COA3,
+    #[doc = "0x1c - eUSCI_Bx I2C Received Address Register"]
+    pub ucbx_addrx: UCBXADDRX,
+    #[doc = "0x1e - eUSCI_Bx I2C Address Mask Register"]
+    pub ucbx_addmask: UCBXADDMASK,
+    #[doc = "0x20 - eUSCI_Bx I2C Slave Address Register"]
+    pub ucbx_i2csa: UCBXI2CSA,
+    _reserved2: [u8; 8usize],
+    #[doc = "0x2a - eUSCI_Bx Interrupt Enable Register"]
+    pub ucbx_ie: UCBXIE,
+    #[doc = "0x2c - eUSCI_Bx Interrupt Flag Register"]
+    pub ucbx_ifg: UCBXIFG,
+    #[doc = "0x2e - eUSCI_Bx Interrupt Vector Register"]
+    pub ucbx_iv: UCBXIV,
+}
+#[doc = "eUSCI_Bx Control Word Register 0"]
+pub struct UCBXCTLW0 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Control Word Register 0"]
+pub mod ucbx_ctlw0;
+#[doc = "eUSCI_Bx Control Word Register 1"]
+pub struct UCBXCTLW1 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Control Word Register 1"]
+pub mod ucbx_ctlw1;
+#[doc = "eUSCI_Bx Baud Rate Control Word Register"]
+pub struct UCBXBRW {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Baud Rate Control Word Register"]
+pub mod ucbx_brw;
+#[doc = "eUSCI_Bx Status Register"]
+pub struct UCBXSTATW {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Status Register"]
+pub mod ucbx_statw;
+#[doc = "eUSCI_Bx Byte Counter Threshold Register"]
+pub struct UCBXTBCNT {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Byte Counter Threshold Register"]
+pub mod ucbx_tbcnt;
+#[doc = "eUSCI_Bx Receive Buffer Register"]
+pub struct UCBXRXBUF {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Receive Buffer Register"]
+pub mod ucbx_rxbuf;
+#[doc = "eUSCI_Bx Transmit Buffer Register"]
+pub struct UCBXTXBUF {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Transmit Buffer Register"]
+pub mod ucbx_txbuf;
+#[doc = "eUSCI_Bx I2C Own Address 0 Register"]
+pub struct UCBXI2COA0 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx I2C Own Address 0 Register"]
+pub mod ucbx_i2coa0;
+#[doc = "eUSCI_Bx I2C Own Address 1 Register"]
+pub struct UCBXI2COA1 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx I2C Own Address 1 Register"]
+pub mod ucbx_i2coa1;
+#[doc = "eUSCI_Bx I2C Own Address 2 Register"]
+pub struct UCBXI2COA2 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx I2C Own Address 2 Register"]
+pub mod ucbx_i2coa2;
+#[doc = "eUSCI_Bx I2C Own Address 3 Register"]
+pub struct UCBXI2COA3 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx I2C Own Address 3 Register"]
+pub mod ucbx_i2coa3;
+#[doc = "eUSCI_Bx I2C Received Address Register"]
+pub struct UCBXADDRX {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx I2C Received Address Register"]
+pub mod ucbx_addrx;
+#[doc = "eUSCI_Bx I2C Address Mask Register"]
+pub struct UCBXADDMASK {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx I2C Address Mask Register"]
+pub mod ucbx_addmask;
+#[doc = "eUSCI_Bx I2C Slave Address Register"]
+pub struct UCBXI2CSA {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx I2C Slave Address Register"]
+pub mod ucbx_i2csa;
+#[doc = "eUSCI_Bx Interrupt Enable Register"]
+pub struct UCBXIE {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Interrupt Enable Register"]
+pub mod ucbx_ie;
+#[doc = "eUSCI_Bx Interrupt Flag Register"]
+pub struct UCBXIFG {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Interrupt Flag Register"]
+pub mod ucbx_ifg;
+#[doc = "eUSCI_Bx Interrupt Vector Register"]
+pub struct UCBXIV {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "eUSCI_Bx Interrupt Vector Register"]
+pub mod ucbx_iv;
diff --git a/example-source/msp432p401r/src/eusci_b3/ucbx_addmask.rs b/example-source/msp432p401r/src/eusci_b3/ucbx_addmask.rs
new file mode 100644
index 0000000..856e7a6
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b3/ucbx_addmask.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXADDMASK {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ADDMASKR {
+    bits: u16,
+}
+impl ADDMASKR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADDMASKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADDMASKW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated. Modify only when UCSWRST = 1."]
+    #[inline]
+    pub fn addmask(&self) -> ADDMASKR {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        ADDMASKR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 1023 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:9 - Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated. Modify only when UCSWRST = 1."]
+    #[inline]
+    pub fn addmask(&mut self) -> _ADDMASKW {
+        _ADDMASKW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b3/ucbx_addrx.rs b/example-source/msp432p401r/src/eusci_b3/ucbx_addrx.rs
new file mode 100644
index 0000000..595f1cb
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b3/ucbx_addrx.rs
@@ -0,0 +1,41 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::UCBXADDRX {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ADDRXR {
+    bits: u16,
+}
+impl ADDRXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - Received Address Register"]
+    #[inline]
+    pub fn addrx(&self) -> ADDRXR {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        ADDRXR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b3/ucbx_brw.rs b/example-source/msp432p401r/src/eusci_b3/ucbx_brw.rs
new file mode 100644
index 0000000..1ed885e
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b3/ucbx_brw.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXBRW {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCBRR {
+    bits: u16,
+}
+impl UCBRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBRW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Bit clock prescaler"]
+    #[inline]
+    pub fn ucbr(&self) -> UCBRR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        UCBRR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Bit clock prescaler"]
+    #[inline]
+    pub fn ucbr(&mut self) -> _UCBRW {
+        _UCBRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b3/ucbx_ctlw0.rs b/example-source/msp432p401r/src/eusci_b3/ucbx_ctlw0.rs
new file mode 100644
index 0000000..4baf4f9
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b3/ucbx_ctlw0.rs
@@ -0,0 +1,1645 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXCTLW0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCSWRST`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSWRSTR {
+    #[doc = "Disabled. eUSCI_B reset released for operation"]
+    UCSWRST_0,
+    #[doc = "Enabled. eUSCI_B logic held in reset state"]
+    UCSWRST_1,
+}
+impl UCSWRSTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSWRSTR::UCSWRST_0 => false,
+            UCSWRSTR::UCSWRST_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSWRSTR {
+        match value {
+            false => UCSWRSTR::UCSWRST_0,
+            true => UCSWRSTR::UCSWRST_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSWRST_0`"]
+    #[inline]
+    pub fn is_ucswrst_0(&self) -> bool {
+        *self == UCSWRSTR::UCSWRST_0
+    }
+    #[doc = "Checks if the value of the field is `UCSWRST_1`"]
+    #[inline]
+    pub fn is_ucswrst_1(&self) -> bool {
+        *self == UCSWRSTR::UCSWRST_1
+    }
+}
+#[doc = "Possible values of the field `UCTXSTT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXSTTR {
+    #[doc = "Do not generate START condition"]
+    UCTXSTT_0,
+    #[doc = "Generate START condition"]
+    UCTXSTT_1,
+}
+impl UCTXSTTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXSTTR::UCTXSTT_0 => false,
+            UCTXSTTR::UCTXSTT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXSTTR {
+        match value {
+            false => UCTXSTTR::UCTXSTT_0,
+            true => UCTXSTTR::UCTXSTT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXSTT_0`"]
+    #[inline]
+    pub fn is_uctxstt_0(&self) -> bool {
+        *self == UCTXSTTR::UCTXSTT_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXSTT_1`"]
+    #[inline]
+    pub fn is_uctxstt_1(&self) -> bool {
+        *self == UCTXSTTR::UCTXSTT_1
+    }
+}
+#[doc = "Possible values of the field `UCTXSTP`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXSTPR {
+    #[doc = "No STOP generated"]
+    UCTXSTP_0,
+    #[doc = "Generate STOP"]
+    UCTXSTP_1,
+}
+impl UCTXSTPR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXSTPR::UCTXSTP_0 => false,
+            UCTXSTPR::UCTXSTP_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXSTPR {
+        match value {
+            false => UCTXSTPR::UCTXSTP_0,
+            true => UCTXSTPR::UCTXSTP_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXSTP_0`"]
+    #[inline]
+    pub fn is_uctxstp_0(&self) -> bool {
+        *self == UCTXSTPR::UCTXSTP_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXSTP_1`"]
+    #[inline]
+    pub fn is_uctxstp_1(&self) -> bool {
+        *self == UCTXSTPR::UCTXSTP_1
+    }
+}
+#[doc = "Possible values of the field `UCTXNACK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXNACKR {
+    #[doc = "Acknowledge normally"]
+    UCTXNACK_0,
+    #[doc = "Generate NACK"]
+    UCTXNACK_1,
+}
+impl UCTXNACKR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXNACKR::UCTXNACK_0 => false,
+            UCTXNACKR::UCTXNACK_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXNACKR {
+        match value {
+            false => UCTXNACKR::UCTXNACK_0,
+            true => UCTXNACKR::UCTXNACK_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXNACK_0`"]
+    #[inline]
+    pub fn is_uctxnack_0(&self) -> bool {
+        *self == UCTXNACKR::UCTXNACK_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXNACK_1`"]
+    #[inline]
+    pub fn is_uctxnack_1(&self) -> bool {
+        *self == UCTXNACKR::UCTXNACK_1
+    }
+}
+#[doc = "Possible values of the field `UCTR`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTRR {
+    #[doc = "Receiver"]
+    UCTR_0,
+    #[doc = "Transmitter"]
+    UCTR_1,
+}
+impl UCTRR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTRR::UCTR_0 => false,
+            UCTRR::UCTR_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTRR {
+        match value {
+            false => UCTRR::UCTR_0,
+            true => UCTRR::UCTR_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTR_0`"]
+    #[inline]
+    pub fn is_uctr_0(&self) -> bool {
+        *self == UCTRR::UCTR_0
+    }
+    #[doc = "Checks if the value of the field is `UCTR_1`"]
+    #[inline]
+    pub fn is_uctr_1(&self) -> bool {
+        *self == UCTRR::UCTR_1
+    }
+}
+#[doc = "Possible values of the field `UCTXACK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXACKR {
+    #[doc = "Do not acknowledge the slave address"]
+    UCTXACK_0,
+    #[doc = "Acknowledge the slave address"]
+    UCTXACK_1,
+}
+impl UCTXACKR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXACKR::UCTXACK_0 => false,
+            UCTXACKR::UCTXACK_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXACKR {
+        match value {
+            false => UCTXACKR::UCTXACK_0,
+            true => UCTXACKR::UCTXACK_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXACK_0`"]
+    #[inline]
+    pub fn is_uctxack_0(&self) -> bool {
+        *self == UCTXACKR::UCTXACK_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXACK_1`"]
+    #[inline]
+    pub fn is_uctxack_1(&self) -> bool {
+        *self == UCTXACKR::UCTXACK_1
+    }
+}
+#[doc = "Possible values of the field `UCSSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSSELR {
+    #[doc = "UCLKI"]
+    UCSSEL_0,
+    #[doc = "ACLK"]
+    UCSSEL_1,
+    #[doc = "SMCLK"]
+    UCSSEL_2,
+    #[doc = "SMCLK"]
+    UCSSEL_3,
+}
+impl UCSSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCSSELR::UCSSEL_0 => 0,
+            UCSSELR::UCSSEL_1 => 1,
+            UCSSELR::UCSSEL_2 => 2,
+            UCSSELR::UCSSEL_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCSSELR {
+        match value {
+            0 => UCSSELR::UCSSEL_0,
+            1 => UCSSELR::UCSSEL_1,
+            2 => UCSSELR::UCSSEL_2,
+            3 => UCSSELR::UCSSEL_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSSEL_0`"]
+    #[inline]
+    pub fn is_ucssel_0(&self) -> bool {
+        *self == UCSSELR::UCSSEL_0
+    }
+    #[doc = "Checks if the value of the field is `UCSSEL_1`"]
+    #[inline]
+    pub fn is_ucssel_1(&self) -> bool {
+        *self == UCSSELR::UCSSEL_1
+    }
+    #[doc = "Checks if the value of the field is `UCSSEL_2`"]
+    #[inline]
+    pub fn is_ucssel_2(&self) -> bool {
+        *self == UCSSELR::UCSSEL_2
+    }
+    #[doc = "Checks if the value of the field is `UCSSEL_3`"]
+    #[inline]
+    pub fn is_ucssel_3(&self) -> bool {
+        *self == UCSSELR::UCSSEL_3
+    }
+}
+#[doc = "Possible values of the field `UCSYNC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSYNCR {
+    #[doc = "Asynchronous mode"]
+    UCSYNC_0,
+    #[doc = "Synchronous mode"]
+    UCSYNC_1,
+}
+impl UCSYNCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSYNCR::UCSYNC_0 => false,
+            UCSYNCR::UCSYNC_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSYNCR {
+        match value {
+            false => UCSYNCR::UCSYNC_0,
+            true => UCSYNCR::UCSYNC_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSYNC_0`"]
+    #[inline]
+    pub fn is_ucsync_0(&self) -> bool {
+        *self == UCSYNCR::UCSYNC_0
+    }
+    #[doc = "Checks if the value of the field is `UCSYNC_1`"]
+    #[inline]
+    pub fn is_ucsync_1(&self) -> bool {
+        *self == UCSYNCR::UCSYNC_1
+    }
+}
+#[doc = "Possible values of the field `UCMODE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCMODER {
+    #[doc = "3-pin SPI"]
+    UCMODE_0,
+    #[doc = "4-pin SPI (master or slave enabled if STE = 1)"]
+    UCMODE_1,
+    #[doc = "4-pin SPI (master or slave enabled if STE = 0)"]
+    UCMODE_2,
+    #[doc = "I2C mode"]
+    UCMODE_3,
+}
+impl UCMODER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCMODER::UCMODE_0 => 0,
+            UCMODER::UCMODE_1 => 1,
+            UCMODER::UCMODE_2 => 2,
+            UCMODER::UCMODE_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCMODER {
+        match value {
+            0 => UCMODER::UCMODE_0,
+            1 => UCMODER::UCMODE_1,
+            2 => UCMODER::UCMODE_2,
+            3 => UCMODER::UCMODE_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_0`"]
+    #[inline]
+    pub fn is_ucmode_0(&self) -> bool {
+        *self == UCMODER::UCMODE_0
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_1`"]
+    #[inline]
+    pub fn is_ucmode_1(&self) -> bool {
+        *self == UCMODER::UCMODE_1
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_2`"]
+    #[inline]
+    pub fn is_ucmode_2(&self) -> bool {
+        *self == UCMODER::UCMODE_2
+    }
+    #[doc = "Checks if the value of the field is `UCMODE_3`"]
+    #[inline]
+    pub fn is_ucmode_3(&self) -> bool {
+        *self == UCMODER::UCMODE_3
+    }
+}
+#[doc = "Possible values of the field `UCMST`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCMSTR {
+    #[doc = "Slave mode"]
+    UCMST_0,
+    #[doc = "Master mode"]
+    UCMST_1,
+}
+impl UCMSTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCMSTR::UCMST_0 => false,
+            UCMSTR::UCMST_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCMSTR {
+        match value {
+            false => UCMSTR::UCMST_0,
+            true => UCMSTR::UCMST_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCMST_0`"]
+    #[inline]
+    pub fn is_ucmst_0(&self) -> bool {
+        *self == UCMSTR::UCMST_0
+    }
+    #[doc = "Checks if the value of the field is `UCMST_1`"]
+    #[inline]
+    pub fn is_ucmst_1(&self) -> bool {
+        *self == UCMSTR::UCMST_1
+    }
+}
+#[doc = "Possible values of the field `UCMM`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCMMR {
+    #[doc = "Single master environment. There is no other master in the system. The address compare unit is disabled."]
+    UCMM_0,
+    #[doc = "Multi-master environment"]
+    UCMM_1,
+}
+impl UCMMR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCMMR::UCMM_0 => false,
+            UCMMR::UCMM_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCMMR {
+        match value {
+            false => UCMMR::UCMM_0,
+            true => UCMMR::UCMM_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCMM_0`"]
+    #[inline]
+    pub fn is_ucmm_0(&self) -> bool {
+        *self == UCMMR::UCMM_0
+    }
+    #[doc = "Checks if the value of the field is `UCMM_1`"]
+    #[inline]
+    pub fn is_ucmm_1(&self) -> bool {
+        *self == UCMMR::UCMM_1
+    }
+}
+#[doc = "Possible values of the field `UCSLA10`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSLA10R {
+    #[doc = "Address slave with 7-bit address"]
+    UCSLA10_0,
+    #[doc = "Address slave with 10-bit address"]
+    UCSLA10_1,
+}
+impl UCSLA10R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSLA10R::UCSLA10_0 => false,
+            UCSLA10R::UCSLA10_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSLA10R {
+        match value {
+            false => UCSLA10R::UCSLA10_0,
+            true => UCSLA10R::UCSLA10_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSLA10_0`"]
+    #[inline]
+    pub fn is_ucsla10_0(&self) -> bool {
+        *self == UCSLA10R::UCSLA10_0
+    }
+    #[doc = "Checks if the value of the field is `UCSLA10_1`"]
+    #[inline]
+    pub fn is_ucsla10_1(&self) -> bool {
+        *self == UCSLA10R::UCSLA10_1
+    }
+}
+#[doc = "Possible values of the field `UCA10`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCA10R {
+    #[doc = "Own address is a 7-bit address"]
+    UCA10_0,
+    #[doc = "Own address is a 10-bit address"]
+    UCA10_1,
+}
+impl UCA10R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCA10R::UCA10_0 => false,
+            UCA10R::UCA10_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCA10R {
+        match value {
+            false => UCA10R::UCA10_0,
+            true => UCA10R::UCA10_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCA10_0`"]
+    #[inline]
+    pub fn is_uca10_0(&self) -> bool {
+        *self == UCA10R::UCA10_0
+    }
+    #[doc = "Checks if the value of the field is `UCA10_1`"]
+    #[inline]
+    pub fn is_uca10_1(&self) -> bool {
+        *self == UCA10R::UCA10_1
+    }
+}
+#[doc = "Values that can be written to the field `UCSWRST`"]
+pub enum UCSWRSTW {
+    #[doc = "Disabled. eUSCI_B reset released for operation"]
+    UCSWRST_0,
+    #[doc = "Enabled. eUSCI_B logic held in reset state"]
+    UCSWRST_1,
+}
+impl UCSWRSTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSWRSTW::UCSWRST_0 => false,
+            UCSWRSTW::UCSWRST_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSWRSTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSWRSTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSWRSTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disabled. eUSCI_B reset released for operation"]
+    #[inline]
+    pub fn ucswrst_0(self) -> &'a mut W {
+        self.variant(UCSWRSTW::UCSWRST_0)
+    }
+    #[doc = "Enabled. eUSCI_B logic held in reset state"]
+    #[inline]
+    pub fn ucswrst_1(self) -> &'a mut W {
+        self.variant(UCSWRSTW::UCSWRST_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXSTT`"]
+pub enum UCTXSTTW {
+    #[doc = "Do not generate START condition"]
+    UCTXSTT_0,
+    #[doc = "Generate START condition"]
+    UCTXSTT_1,
+}
+impl UCTXSTTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXSTTW::UCTXSTT_0 => false,
+            UCTXSTTW::UCTXSTT_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXSTTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXSTTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXSTTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Do not generate START condition"]
+    #[inline]
+    pub fn uctxstt_0(self) -> &'a mut W {
+        self.variant(UCTXSTTW::UCTXSTT_0)
+    }
+    #[doc = "Generate START condition"]
+    #[inline]
+    pub fn uctxstt_1(self) -> &'a mut W {
+        self.variant(UCTXSTTW::UCTXSTT_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXSTP`"]
+pub enum UCTXSTPW {
+    #[doc = "No STOP generated"]
+    UCTXSTP_0,
+    #[doc = "Generate STOP"]
+    UCTXSTP_1,
+}
+impl UCTXSTPW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXSTPW::UCTXSTP_0 => false,
+            UCTXSTPW::UCTXSTP_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXSTPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXSTPW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXSTPW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No STOP generated"]
+    #[inline]
+    pub fn uctxstp_0(self) -> &'a mut W {
+        self.variant(UCTXSTPW::UCTXSTP_0)
+    }
+    #[doc = "Generate STOP"]
+    #[inline]
+    pub fn uctxstp_1(self) -> &'a mut W {
+        self.variant(UCTXSTPW::UCTXSTP_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXNACK`"]
+pub enum UCTXNACKW {
+    #[doc = "Acknowledge normally"]
+    UCTXNACK_0,
+    #[doc = "Generate NACK"]
+    UCTXNACK_1,
+}
+impl UCTXNACKW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXNACKW::UCTXNACK_0 => false,
+            UCTXNACKW::UCTXNACK_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXNACKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXNACKW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXNACKW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Acknowledge normally"]
+    #[inline]
+    pub fn uctxnack_0(self) -> &'a mut W {
+        self.variant(UCTXNACKW::UCTXNACK_0)
+    }
+    #[doc = "Generate NACK"]
+    #[inline]
+    pub fn uctxnack_1(self) -> &'a mut W {
+        self.variant(UCTXNACKW::UCTXNACK_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTR`"]
+pub enum UCTRW {
+    #[doc = "Receiver"]
+    UCTR_0,
+    #[doc = "Transmitter"]
+    UCTR_1,
+}
+impl UCTRW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTRW::UCTR_0 => false,
+            UCTRW::UCTR_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTRW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTRW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Receiver"]
+    #[inline]
+    pub fn uctr_0(self) -> &'a mut W {
+        self.variant(UCTRW::UCTR_0)
+    }
+    #[doc = "Transmitter"]
+    #[inline]
+    pub fn uctr_1(self) -> &'a mut W {
+        self.variant(UCTRW::UCTR_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXACK`"]
+pub enum UCTXACKW {
+    #[doc = "Do not acknowledge the slave address"]
+    UCTXACK_0,
+    #[doc = "Acknowledge the slave address"]
+    UCTXACK_1,
+}
+impl UCTXACKW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXACKW::UCTXACK_0 => false,
+            UCTXACKW::UCTXACK_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXACKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXACKW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXACKW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Do not acknowledge the slave address"]
+    #[inline]
+    pub fn uctxack_0(self) -> &'a mut W {
+        self.variant(UCTXACKW::UCTXACK_0)
+    }
+    #[doc = "Acknowledge the slave address"]
+    #[inline]
+    pub fn uctxack_1(self) -> &'a mut W {
+        self.variant(UCTXACKW::UCTXACK_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSSEL`"]
+pub enum UCSSELW {
+    #[doc = "UCLKI"]
+    UCSSEL_0,
+    #[doc = "ACLK"]
+    UCSSEL_1,
+    #[doc = "SMCLK"]
+    UCSSEL_2,
+    #[doc = "SMCLK"]
+    UCSSEL_3,
+}
+impl UCSSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCSSELW::UCSSEL_0 => 0,
+            UCSSELW::UCSSEL_1 => 1,
+            UCSSELW::UCSSEL_2 => 2,
+            UCSSELW::UCSSEL_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSSELW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "UCLKI"]
+    #[inline]
+    pub fn ucssel_0(self) -> &'a mut W {
+        self.variant(UCSSELW::UCSSEL_0)
+    }
+    #[doc = "ACLK"]
+    #[inline]
+    pub fn ucssel_1(self) -> &'a mut W {
+        self.variant(UCSSELW::UCSSEL_1)
+    }
+    #[doc = "SMCLK"]
+    #[inline]
+    pub fn ucssel_2(self) -> &'a mut W {
+        self.variant(UCSSELW::UCSSEL_2)
+    }
+    #[doc = "SMCLK"]
+    #[inline]
+    pub fn ucssel_3(self) -> &'a mut W {
+        self.variant(UCSSELW::UCSSEL_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSYNC`"]
+pub enum UCSYNCW {
+    #[doc = "Asynchronous mode"]
+    UCSYNC_0,
+    #[doc = "Synchronous mode"]
+    UCSYNC_1,
+}
+impl UCSYNCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSYNCW::UCSYNC_0 => false,
+            UCSYNCW::UCSYNC_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSYNCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSYNCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSYNCW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Asynchronous mode"]
+    #[inline]
+    pub fn ucsync_0(self) -> &'a mut W {
+        self.variant(UCSYNCW::UCSYNC_0)
+    }
+    #[doc = "Synchronous mode"]
+    #[inline]
+    pub fn ucsync_1(self) -> &'a mut W {
+        self.variant(UCSYNCW::UCSYNC_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCMODE`"]
+pub enum UCMODEW {
+    #[doc = "3-pin SPI"]
+    UCMODE_0,
+    #[doc = "4-pin SPI (master or slave enabled if STE = 1)"]
+    UCMODE_1,
+    #[doc = "4-pin SPI (master or slave enabled if STE = 0)"]
+    UCMODE_2,
+    #[doc = "I2C mode"]
+    UCMODE_3,
+}
+impl UCMODEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCMODEW::UCMODE_0 => 0,
+            UCMODEW::UCMODE_1 => 1,
+            UCMODEW::UCMODE_2 => 2,
+            UCMODEW::UCMODE_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCMODEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCMODEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCMODEW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "3-pin SPI"]
+    #[inline]
+    pub fn ucmode_0(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_0)
+    }
+    #[doc = "4-pin SPI (master or slave enabled if STE = 1)"]
+    #[inline]
+    pub fn ucmode_1(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_1)
+    }
+    #[doc = "4-pin SPI (master or slave enabled if STE = 0)"]
+    #[inline]
+    pub fn ucmode_2(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_2)
+    }
+    #[doc = "I2C mode"]
+    #[inline]
+    pub fn ucmode_3(self) -> &'a mut W {
+        self.variant(UCMODEW::UCMODE_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCMST`"]
+pub enum UCMSTW {
+    #[doc = "Slave mode"]
+    UCMST_0,
+    #[doc = "Master mode"]
+    UCMST_1,
+}
+impl UCMSTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCMSTW::UCMST_0 => false,
+            UCMSTW::UCMST_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCMSTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCMSTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCMSTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Slave mode"]
+    #[inline]
+    pub fn ucmst_0(self) -> &'a mut W {
+        self.variant(UCMSTW::UCMST_0)
+    }
+    #[doc = "Master mode"]
+    #[inline]
+    pub fn ucmst_1(self) -> &'a mut W {
+        self.variant(UCMSTW::UCMST_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCMM`"]
+pub enum UCMMW {
+    #[doc = "Single master environment. There is no other master in the system. The address compare unit is disabled."]
+    UCMM_0,
+    #[doc = "Multi-master environment"]
+    UCMM_1,
+}
+impl UCMMW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCMMW::UCMM_0 => false,
+            UCMMW::UCMM_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCMMW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCMMW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCMMW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Single master environment. There is no other master in the system. The address compare unit is disabled."]
+    #[inline]
+    pub fn ucmm_0(self) -> &'a mut W {
+        self.variant(UCMMW::UCMM_0)
+    }
+    #[doc = "Multi-master environment"]
+    #[inline]
+    pub fn ucmm_1(self) -> &'a mut W {
+        self.variant(UCMMW::UCMM_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSLA10`"]
+pub enum UCSLA10W {
+    #[doc = "Address slave with 7-bit address"]
+    UCSLA10_0,
+    #[doc = "Address slave with 10-bit address"]
+    UCSLA10_1,
+}
+impl UCSLA10W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSLA10W::UCSLA10_0 => false,
+            UCSLA10W::UCSLA10_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSLA10W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSLA10W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSLA10W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Address slave with 7-bit address"]
+    #[inline]
+    pub fn ucsla10_0(self) -> &'a mut W {
+        self.variant(UCSLA10W::UCSLA10_0)
+    }
+    #[doc = "Address slave with 10-bit address"]
+    #[inline]
+    pub fn ucsla10_1(self) -> &'a mut W {
+        self.variant(UCSLA10W::UCSLA10_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCA10`"]
+pub enum UCA10W {
+    #[doc = "Own address is a 7-bit address"]
+    UCA10_0,
+    #[doc = "Own address is a 10-bit address"]
+    UCA10_1,
+}
+impl UCA10W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCA10W::UCA10_0 => false,
+            UCA10W::UCA10_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCA10W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCA10W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCA10W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Own address is a 7-bit address"]
+    #[inline]
+    pub fn uca10_0(self) -> &'a mut W {
+        self.variant(UCA10W::UCA10_0)
+    }
+    #[doc = "Own address is a 10-bit address"]
+    #[inline]
+    pub fn uca10_1(self) -> &'a mut W {
+        self.variant(UCA10W::UCA10_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Software reset enable"]
+    #[inline]
+    pub fn ucswrst(&self) -> UCSWRSTR {
+        UCSWRSTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Transmit START condition in master mode"]
+    #[inline]
+    pub fn uctxstt(&self) -> UCTXSTTR {
+        UCTXSTTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - Transmit STOP condition in master mode"]
+    #[inline]
+    pub fn uctxstp(&self) -> UCTXSTPR {
+        UCTXSTPR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Transmit a NACK"]
+    #[inline]
+    pub fn uctxnack(&self) -> UCTXNACKR {
+        UCTXNACKR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 4 - Transmitter/receiver"]
+    #[inline]
+    pub fn uctr(&self) -> UCTRR {
+        UCTRR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - Transmit ACK condition in slave mode"]
+    #[inline]
+    pub fn uctxack(&self) -> UCTXACKR {
+        UCTXACKR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 6:7 - eUSCI_B clock source select"]
+    #[inline]
+    pub fn ucssel(&self) -> UCSSELR {
+        UCSSELR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 8 - Synchronous mode enable"]
+    #[inline]
+    pub fn ucsync(&self) -> UCSYNCR {
+        UCSYNCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 9:10 - eUSCI_B mode"]
+    #[inline]
+    pub fn ucmode(&self) -> UCMODER {
+        UCMODER::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 11 - Master mode select"]
+    #[inline]
+    pub fn ucmst(&self) -> UCMSTR {
+        UCMSTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 13 - Multi-master environment select"]
+    #[inline]
+    pub fn ucmm(&self) -> UCMMR {
+        UCMMR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 14 - Slave addressing mode select"]
+    #[inline]
+    pub fn ucsla10(&self) -> UCSLA10R {
+        UCSLA10R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 15 - Own addressing mode select"]
+    #[inline]
+    pub fn uca10(&self) -> UCA10R {
+        UCA10R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 449 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Software reset enable"]
+    #[inline]
+    pub fn ucswrst(&mut self) -> _UCSWRSTW {
+        _UCSWRSTW { w: self }
+    }
+    #[doc = "Bit 1 - Transmit START condition in master mode"]
+    #[inline]
+    pub fn uctxstt(&mut self) -> _UCTXSTTW {
+        _UCTXSTTW { w: self }
+    }
+    #[doc = "Bit 2 - Transmit STOP condition in master mode"]
+    #[inline]
+    pub fn uctxstp(&mut self) -> _UCTXSTPW {
+        _UCTXSTPW { w: self }
+    }
+    #[doc = "Bit 3 - Transmit a NACK"]
+    #[inline]
+    pub fn uctxnack(&mut self) -> _UCTXNACKW {
+        _UCTXNACKW { w: self }
+    }
+    #[doc = "Bit 4 - Transmitter/receiver"]
+    #[inline]
+    pub fn uctr(&mut self) -> _UCTRW {
+        _UCTRW { w: self }
+    }
+    #[doc = "Bit 5 - Transmit ACK condition in slave mode"]
+    #[inline]
+    pub fn uctxack(&mut self) -> _UCTXACKW {
+        _UCTXACKW { w: self }
+    }
+    #[doc = "Bits 6:7 - eUSCI_B clock source select"]
+    #[inline]
+    pub fn ucssel(&mut self) -> _UCSSELW {
+        _UCSSELW { w: self }
+    }
+    #[doc = "Bit 8 - Synchronous mode enable"]
+    #[inline]
+    pub fn ucsync(&mut self) -> _UCSYNCW {
+        _UCSYNCW { w: self }
+    }
+    #[doc = "Bits 9:10 - eUSCI_B mode"]
+    #[inline]
+    pub fn ucmode(&mut self) -> _UCMODEW {
+        _UCMODEW { w: self }
+    }
+    #[doc = "Bit 11 - Master mode select"]
+    #[inline]
+    pub fn ucmst(&mut self) -> _UCMSTW {
+        _UCMSTW { w: self }
+    }
+    #[doc = "Bit 13 - Multi-master environment select"]
+    #[inline]
+    pub fn ucmm(&mut self) -> _UCMMW {
+        _UCMMW { w: self }
+    }
+    #[doc = "Bit 14 - Slave addressing mode select"]
+    #[inline]
+    pub fn ucsla10(&mut self) -> _UCSLA10W {
+        _UCSLA10W { w: self }
+    }
+    #[doc = "Bit 15 - Own addressing mode select"]
+    #[inline]
+    pub fn uca10(&mut self) -> _UCA10W {
+        _UCA10W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b3/ucbx_ctlw1.rs b/example-source/msp432p401r/src/eusci_b3/ucbx_ctlw1.rs
new file mode 100644
index 0000000..64e2d04
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b3/ucbx_ctlw1.rs
@@ -0,0 +1,813 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXCTLW1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCGLIT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCGLITR {
+    #[doc = "50 ns"]
+    UCGLIT_0,
+    #[doc = "25 ns"]
+    UCGLIT_1,
+    #[doc = "12.5 ns"]
+    UCGLIT_2,
+    #[doc = "6.25 ns"]
+    UCGLIT_3,
+}
+impl UCGLITR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCGLITR::UCGLIT_0 => 0,
+            UCGLITR::UCGLIT_1 => 1,
+            UCGLITR::UCGLIT_2 => 2,
+            UCGLITR::UCGLIT_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCGLITR {
+        match value {
+            0 => UCGLITR::UCGLIT_0,
+            1 => UCGLITR::UCGLIT_1,
+            2 => UCGLITR::UCGLIT_2,
+            3 => UCGLITR::UCGLIT_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_0`"]
+    #[inline]
+    pub fn is_ucglit_0(&self) -> bool {
+        *self == UCGLITR::UCGLIT_0
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_1`"]
+    #[inline]
+    pub fn is_ucglit_1(&self) -> bool {
+        *self == UCGLITR::UCGLIT_1
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_2`"]
+    #[inline]
+    pub fn is_ucglit_2(&self) -> bool {
+        *self == UCGLITR::UCGLIT_2
+    }
+    #[doc = "Checks if the value of the field is `UCGLIT_3`"]
+    #[inline]
+    pub fn is_ucglit_3(&self) -> bool {
+        *self == UCGLITR::UCGLIT_3
+    }
+}
+#[doc = "Possible values of the field `UCASTP`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCASTPR {
+    #[doc = "No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care."]
+    UCASTP_0,
+    #[doc = "UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT"]
+    UCASTP_1,
+    #[doc = "A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold"]
+    UCASTP_2,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl UCASTPR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCASTPR::UCASTP_0 => 0,
+            UCASTPR::UCASTP_1 => 1,
+            UCASTPR::UCASTP_2 => 2,
+            UCASTPR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCASTPR {
+        match value {
+            0 => UCASTPR::UCASTP_0,
+            1 => UCASTPR::UCASTP_1,
+            2 => UCASTPR::UCASTP_2,
+            i => UCASTPR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCASTP_0`"]
+    #[inline]
+    pub fn is_ucastp_0(&self) -> bool {
+        *self == UCASTPR::UCASTP_0
+    }
+    #[doc = "Checks if the value of the field is `UCASTP_1`"]
+    #[inline]
+    pub fn is_ucastp_1(&self) -> bool {
+        *self == UCASTPR::UCASTP_1
+    }
+    #[doc = "Checks if the value of the field is `UCASTP_2`"]
+    #[inline]
+    pub fn is_ucastp_2(&self) -> bool {
+        *self == UCASTPR::UCASTP_2
+    }
+}
+#[doc = "Possible values of the field `UCSWACK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSWACKR {
+    #[doc = "The address acknowledge of the slave is controlled by the eUSCI_B module"]
+    UCSWACK_0,
+    #[doc = "The user needs to trigger the sending of the address ACK by issuing UCTXACK"]
+    UCSWACK_1,
+}
+impl UCSWACKR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSWACKR::UCSWACK_0 => false,
+            UCSWACKR::UCSWACK_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSWACKR {
+        match value {
+            false => UCSWACKR::UCSWACK_0,
+            true => UCSWACKR::UCSWACK_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSWACK_0`"]
+    #[inline]
+    pub fn is_ucswack_0(&self) -> bool {
+        *self == UCSWACKR::UCSWACK_0
+    }
+    #[doc = "Checks if the value of the field is `UCSWACK_1`"]
+    #[inline]
+    pub fn is_ucswack_1(&self) -> bool {
+        *self == UCSWACKR::UCSWACK_1
+    }
+}
+#[doc = "Possible values of the field `UCSTPNACK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTPNACKR {
+    #[doc = "Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard)"]
+    UCSTPNACK_0,
+    #[doc = "All bytes are acknowledged by the eUSCI_B when configured as master receiver"]
+    UCSTPNACK_1,
+}
+impl UCSTPNACKR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTPNACKR::UCSTPNACK_0 => false,
+            UCSTPNACKR::UCSTPNACK_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTPNACKR {
+        match value {
+            false => UCSTPNACKR::UCSTPNACK_0,
+            true => UCSTPNACKR::UCSTPNACK_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTPNACK_0`"]
+    #[inline]
+    pub fn is_ucstpnack_0(&self) -> bool {
+        *self == UCSTPNACKR::UCSTPNACK_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTPNACK_1`"]
+    #[inline]
+    pub fn is_ucstpnack_1(&self) -> bool {
+        *self == UCSTPNACKR::UCSTPNACK_1
+    }
+}
+#[doc = "Possible values of the field `UCCLTO`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCCLTOR {
+    #[doc = "Disable clock low timeout counter"]
+    UCCLTO_0,
+    #[doc = "135 000 SYSCLK cycles (approximately 28 ms)"]
+    UCCLTO_1,
+    #[doc = "150 000 SYSCLK cycles (approximately 31 ms)"]
+    UCCLTO_2,
+    #[doc = "165 000 SYSCLK cycles (approximately 34 ms)"]
+    UCCLTO_3,
+}
+impl UCCLTOR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            UCCLTOR::UCCLTO_0 => 0,
+            UCCLTOR::UCCLTO_1 => 1,
+            UCCLTOR::UCCLTO_2 => 2,
+            UCCLTOR::UCCLTO_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> UCCLTOR {
+        match value {
+            0 => UCCLTOR::UCCLTO_0,
+            1 => UCCLTOR::UCCLTO_1,
+            2 => UCCLTOR::UCCLTO_2,
+            3 => UCCLTOR::UCCLTO_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCCLTO_0`"]
+    #[inline]
+    pub fn is_ucclto_0(&self) -> bool {
+        *self == UCCLTOR::UCCLTO_0
+    }
+    #[doc = "Checks if the value of the field is `UCCLTO_1`"]
+    #[inline]
+    pub fn is_ucclto_1(&self) -> bool {
+        *self == UCCLTOR::UCCLTO_1
+    }
+    #[doc = "Checks if the value of the field is `UCCLTO_2`"]
+    #[inline]
+    pub fn is_ucclto_2(&self) -> bool {
+        *self == UCCLTOR::UCCLTO_2
+    }
+    #[doc = "Checks if the value of the field is `UCCLTO_3`"]
+    #[inline]
+    pub fn is_ucclto_3(&self) -> bool {
+        *self == UCCLTOR::UCCLTO_3
+    }
+}
+#[doc = "Possible values of the field `UCETXINT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCETXINTR {
+    #[doc = "UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit"]
+    UCETXINT_0,
+    #[doc = "UCTXIFG0 is set for each START condition"]
+    UCETXINT_1,
+}
+impl UCETXINTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCETXINTR::UCETXINT_0 => false,
+            UCETXINTR::UCETXINT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCETXINTR {
+        match value {
+            false => UCETXINTR::UCETXINT_0,
+            true => UCETXINTR::UCETXINT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCETXINT_0`"]
+    #[inline]
+    pub fn is_ucetxint_0(&self) -> bool {
+        *self == UCETXINTR::UCETXINT_0
+    }
+    #[doc = "Checks if the value of the field is `UCETXINT_1`"]
+    #[inline]
+    pub fn is_ucetxint_1(&self) -> bool {
+        *self == UCETXINTR::UCETXINT_1
+    }
+}
+#[doc = "Values that can be written to the field `UCGLIT`"]
+pub enum UCGLITW {
+    #[doc = "50 ns"]
+    UCGLIT_0,
+    #[doc = "25 ns"]
+    UCGLIT_1,
+    #[doc = "12.5 ns"]
+    UCGLIT_2,
+    #[doc = "6.25 ns"]
+    UCGLIT_3,
+}
+impl UCGLITW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCGLITW::UCGLIT_0 => 0,
+            UCGLITW::UCGLIT_1 => 1,
+            UCGLITW::UCGLIT_2 => 2,
+            UCGLITW::UCGLIT_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCGLITW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCGLITW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCGLITW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "50 ns"]
+    #[inline]
+    pub fn ucglit_0(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_0)
+    }
+    #[doc = "25 ns"]
+    #[inline]
+    pub fn ucglit_1(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_1)
+    }
+    #[doc = "12.5 ns"]
+    #[inline]
+    pub fn ucglit_2(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_2)
+    }
+    #[doc = "6.25 ns"]
+    #[inline]
+    pub fn ucglit_3(self) -> &'a mut W {
+        self.variant(UCGLITW::UCGLIT_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCASTP`"]
+pub enum UCASTPW {
+    #[doc = "No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care."]
+    UCASTP_0,
+    #[doc = "UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT"]
+    UCASTP_1,
+    #[doc = "A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold"]
+    UCASTP_2,
+}
+impl UCASTPW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCASTPW::UCASTP_0 => 0,
+            UCASTPW::UCASTP_1 => 1,
+            UCASTPW::UCASTP_2 => 2,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCASTPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCASTPW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCASTPW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care."]
+    #[inline]
+    pub fn ucastp_0(self) -> &'a mut W {
+        self.variant(UCASTPW::UCASTP_0)
+    }
+    #[doc = "UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT"]
+    #[inline]
+    pub fn ucastp_1(self) -> &'a mut W {
+        self.variant(UCASTPW::UCASTP_1)
+    }
+    #[doc = "A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold"]
+    #[inline]
+    pub fn ucastp_2(self) -> &'a mut W {
+        self.variant(UCASTPW::UCASTP_2)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSWACK`"]
+pub enum UCSWACKW {
+    #[doc = "The address acknowledge of the slave is controlled by the eUSCI_B module"]
+    UCSWACK_0,
+    #[doc = "The user needs to trigger the sending of the address ACK by issuing UCTXACK"]
+    UCSWACK_1,
+}
+impl UCSWACKW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSWACKW::UCSWACK_0 => false,
+            UCSWACKW::UCSWACK_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSWACKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSWACKW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSWACKW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The address acknowledge of the slave is controlled by the eUSCI_B module"]
+    #[inline]
+    pub fn ucswack_0(self) -> &'a mut W {
+        self.variant(UCSWACKW::UCSWACK_0)
+    }
+    #[doc = "The user needs to trigger the sending of the address ACK by issuing UCTXACK"]
+    #[inline]
+    pub fn ucswack_1(self) -> &'a mut W {
+        self.variant(UCSWACKW::UCSWACK_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTPNACK`"]
+pub enum UCSTPNACKW {
+    #[doc = "Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard)"]
+    UCSTPNACK_0,
+    #[doc = "All bytes are acknowledged by the eUSCI_B when configured as master receiver"]
+    UCSTPNACK_1,
+}
+impl UCSTPNACKW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTPNACKW::UCSTPNACK_0 => false,
+            UCSTPNACKW::UCSTPNACK_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTPNACKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTPNACKW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTPNACKW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard)"]
+    #[inline]
+    pub fn ucstpnack_0(self) -> &'a mut W {
+        self.variant(UCSTPNACKW::UCSTPNACK_0)
+    }
+    #[doc = "All bytes are acknowledged by the eUSCI_B when configured as master receiver"]
+    #[inline]
+    pub fn ucstpnack_1(self) -> &'a mut W {
+        self.variant(UCSTPNACKW::UCSTPNACK_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCCLTO`"]
+pub enum UCCLTOW {
+    #[doc = "Disable clock low timeout counter"]
+    UCCLTO_0,
+    #[doc = "135 000 SYSCLK cycles (approximately 28 ms)"]
+    UCCLTO_1,
+    #[doc = "150 000 SYSCLK cycles (approximately 31 ms)"]
+    UCCLTO_2,
+    #[doc = "165 000 SYSCLK cycles (approximately 34 ms)"]
+    UCCLTO_3,
+}
+impl UCCLTOW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            UCCLTOW::UCCLTO_0 => 0,
+            UCCLTOW::UCCLTO_1 => 1,
+            UCCLTOW::UCCLTO_2 => 2,
+            UCCLTOW::UCCLTO_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCCLTOW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCCLTOW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCCLTOW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Disable clock low timeout counter"]
+    #[inline]
+    pub fn ucclto_0(self) -> &'a mut W {
+        self.variant(UCCLTOW::UCCLTO_0)
+    }
+    #[doc = "135 000 SYSCLK cycles (approximately 28 ms)"]
+    #[inline]
+    pub fn ucclto_1(self) -> &'a mut W {
+        self.variant(UCCLTOW::UCCLTO_1)
+    }
+    #[doc = "150 000 SYSCLK cycles (approximately 31 ms)"]
+    #[inline]
+    pub fn ucclto_2(self) -> &'a mut W {
+        self.variant(UCCLTOW::UCCLTO_2)
+    }
+    #[doc = "165 000 SYSCLK cycles (approximately 34 ms)"]
+    #[inline]
+    pub fn ucclto_3(self) -> &'a mut W {
+        self.variant(UCCLTOW::UCCLTO_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCETXINT`"]
+pub enum UCETXINTW {
+    #[doc = "UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit"]
+    UCETXINT_0,
+    #[doc = "UCTXIFG0 is set for each START condition"]
+    UCETXINT_1,
+}
+impl UCETXINTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCETXINTW::UCETXINT_0 => false,
+            UCETXINTW::UCETXINT_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCETXINTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCETXINTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCETXINTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit"]
+    #[inline]
+    pub fn ucetxint_0(self) -> &'a mut W {
+        self.variant(UCETXINTW::UCETXINT_0)
+    }
+    #[doc = "UCTXIFG0 is set for each START condition"]
+    #[inline]
+    pub fn ucetxint_1(self) -> &'a mut W {
+        self.variant(UCETXINTW::UCETXINT_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:1 - Deglitch time"]
+    #[inline]
+    pub fn ucglit(&self) -> UCGLITR {
+        UCGLITR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bits 2:3 - Automatic STOP condition generation"]
+    #[inline]
+    pub fn ucastp(&self) -> UCASTPR {
+        UCASTPR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 4 - SW or HW ACK control"]
+    #[inline]
+    pub fn ucswack(&self) -> UCSWACKR {
+        UCSWACKR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - ACK all master bytes"]
+    #[inline]
+    pub fn ucstpnack(&self) -> UCSTPNACKR {
+        UCSTPNACKR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 6:7 - Clock low timeout select"]
+    #[inline]
+    pub fn ucclto(&self) -> UCCLTOR {
+        UCCLTOR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 8 - Early UCTXIFG0"]
+    #[inline]
+    pub fn ucetxint(&self) -> UCETXINTR {
+        UCETXINTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 3 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:1 - Deglitch time"]
+    #[inline]
+    pub fn ucglit(&mut self) -> _UCGLITW {
+        _UCGLITW { w: self }
+    }
+    #[doc = "Bits 2:3 - Automatic STOP condition generation"]
+    #[inline]
+    pub fn ucastp(&mut self) -> _UCASTPW {
+        _UCASTPW { w: self }
+    }
+    #[doc = "Bit 4 - SW or HW ACK control"]
+    #[inline]
+    pub fn ucswack(&mut self) -> _UCSWACKW {
+        _UCSWACKW { w: self }
+    }
+    #[doc = "Bit 5 - ACK all master bytes"]
+    #[inline]
+    pub fn ucstpnack(&mut self) -> _UCSTPNACKW {
+        _UCSTPNACKW { w: self }
+    }
+    #[doc = "Bits 6:7 - Clock low timeout select"]
+    #[inline]
+    pub fn ucclto(&mut self) -> _UCCLTOW {
+        _UCCLTOW { w: self }
+    }
+    #[doc = "Bit 8 - Early UCTXIFG0"]
+    #[inline]
+    pub fn ucetxint(&mut self) -> _UCETXINTW {
+        _UCETXINTW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b3/ucbx_i2coa0.rs b/example-source/msp432p401r/src/eusci_b3/ucbx_i2coa0.rs
new file mode 100644
index 0000000..93003b5
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b3/ucbx_i2coa0.rs
@@ -0,0 +1,343 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXI2COA0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct I2COA0R {
+    bits: u16,
+}
+impl I2COA0R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `UCOAEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCOAENR {
+    #[doc = "The slave address defined in I2COA0 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA0 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCOAENR::UCOAEN_0 => false,
+            UCOAENR::UCOAEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCOAENR {
+        match value {
+            false => UCOAENR::UCOAEN_0,
+            true => UCOAENR::UCOAEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_0`"]
+    #[inline]
+    pub fn is_ucoaen_0(&self) -> bool {
+        *self == UCOAENR::UCOAEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_1`"]
+    #[inline]
+    pub fn is_ucoaen_1(&self) -> bool {
+        *self == UCOAENR::UCOAEN_1
+    }
+}
+#[doc = "Possible values of the field `UCGCEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCGCENR {
+    #[doc = "Do not respond to a general call"]
+    UCGCEN_0,
+    #[doc = "Respond to a general call"]
+    UCGCEN_1,
+}
+impl UCGCENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCGCENR::UCGCEN_0 => false,
+            UCGCENR::UCGCEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCGCENR {
+        match value {
+            false => UCGCENR::UCGCEN_0,
+            true => UCGCENR::UCGCEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCGCEN_0`"]
+    #[inline]
+    pub fn is_ucgcen_0(&self) -> bool {
+        *self == UCGCENR::UCGCEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCGCEN_1`"]
+    #[inline]
+    pub fn is_ucgcen_1(&self) -> bool {
+        *self == UCGCENR::UCGCEN_1
+    }
+}
+#[doc = r" Proxy"]
+pub struct _I2COA0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _I2COA0W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCOAEN`"]
+pub enum UCOAENW {
+    #[doc = "The slave address defined in I2COA0 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA0 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCOAENW::UCOAEN_0 => false,
+            UCOAENW::UCOAEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCOAENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCOAENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCOAENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The slave address defined in I2COA0 is disabled"]
+    #[inline]
+    pub fn ucoaen_0(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_0)
+    }
+    #[doc = "The slave address defined in I2COA0 is enabled"]
+    #[inline]
+    pub fn ucoaen_1(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCGCEN`"]
+pub enum UCGCENW {
+    #[doc = "Do not respond to a general call"]
+    UCGCEN_0,
+    #[doc = "Respond to a general call"]
+    UCGCEN_1,
+}
+impl UCGCENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCGCENW::UCGCEN_0 => false,
+            UCGCENW::UCGCEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCGCENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCGCENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCGCENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Do not respond to a general call"]
+    #[inline]
+    pub fn ucgcen_0(self) -> &'a mut W {
+        self.variant(UCGCENW::UCGCEN_0)
+    }
+    #[doc = "Respond to a general call"]
+    #[inline]
+    pub fn ucgcen_1(self) -> &'a mut W {
+        self.variant(UCGCENW::UCGCEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa0(&self) -> I2COA0R {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        I2COA0R { bits }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&self) -> UCOAENR {
+        UCOAENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 15 - General call response enable"]
+    #[inline]
+    pub fn ucgcen(&self) -> UCGCENR {
+        UCGCENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa0(&mut self) -> _I2COA0W {
+        _I2COA0W { w: self }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&mut self) -> _UCOAENW {
+        _UCOAENW { w: self }
+    }
+    #[doc = "Bit 15 - General call response enable"]
+    #[inline]
+    pub fn ucgcen(&mut self) -> _UCGCENW {
+        _UCGCENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b3/ucbx_i2coa1.rs b/example-source/msp432p401r/src/eusci_b3/ucbx_i2coa1.rs
new file mode 100644
index 0000000..660cba5
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b3/ucbx_i2coa1.rs
@@ -0,0 +1,224 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXI2COA1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct I2COA1R {
+    bits: u16,
+}
+impl I2COA1R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `UCOAEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCOAENR {
+    #[doc = "The slave address defined in I2COA1 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA1 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCOAENR::UCOAEN_0 => false,
+            UCOAENR::UCOAEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCOAENR {
+        match value {
+            false => UCOAENR::UCOAEN_0,
+            true => UCOAENR::UCOAEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_0`"]
+    #[inline]
+    pub fn is_ucoaen_0(&self) -> bool {
+        *self == UCOAENR::UCOAEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_1`"]
+    #[inline]
+    pub fn is_ucoaen_1(&self) -> bool {
+        *self == UCOAENR::UCOAEN_1
+    }
+}
+#[doc = r" Proxy"]
+pub struct _I2COA1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _I2COA1W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCOAEN`"]
+pub enum UCOAENW {
+    #[doc = "The slave address defined in I2COA1 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA1 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCOAENW::UCOAEN_0 => false,
+            UCOAENW::UCOAEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCOAENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCOAENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCOAENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The slave address defined in I2COA1 is disabled"]
+    #[inline]
+    pub fn ucoaen_0(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_0)
+    }
+    #[doc = "The slave address defined in I2COA1 is enabled"]
+    #[inline]
+    pub fn ucoaen_1(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa1(&self) -> I2COA1R {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        I2COA1R { bits }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&self) -> UCOAENR {
+        UCOAENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa1(&mut self) -> _I2COA1W {
+        _I2COA1W { w: self }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&mut self) -> _UCOAENW {
+        _UCOAENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b3/ucbx_i2coa2.rs b/example-source/msp432p401r/src/eusci_b3/ucbx_i2coa2.rs
new file mode 100644
index 0000000..4f3ceb5
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b3/ucbx_i2coa2.rs
@@ -0,0 +1,224 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXI2COA2 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct I2COA2R {
+    bits: u16,
+}
+impl I2COA2R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `UCOAEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCOAENR {
+    #[doc = "The slave address defined in I2COA2 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA2 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCOAENR::UCOAEN_0 => false,
+            UCOAENR::UCOAEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCOAENR {
+        match value {
+            false => UCOAENR::UCOAEN_0,
+            true => UCOAENR::UCOAEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_0`"]
+    #[inline]
+    pub fn is_ucoaen_0(&self) -> bool {
+        *self == UCOAENR::UCOAEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_1`"]
+    #[inline]
+    pub fn is_ucoaen_1(&self) -> bool {
+        *self == UCOAENR::UCOAEN_1
+    }
+}
+#[doc = r" Proxy"]
+pub struct _I2COA2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _I2COA2W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCOAEN`"]
+pub enum UCOAENW {
+    #[doc = "The slave address defined in I2COA2 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA2 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCOAENW::UCOAEN_0 => false,
+            UCOAENW::UCOAEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCOAENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCOAENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCOAENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The slave address defined in I2COA2 is disabled"]
+    #[inline]
+    pub fn ucoaen_0(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_0)
+    }
+    #[doc = "The slave address defined in I2COA2 is enabled"]
+    #[inline]
+    pub fn ucoaen_1(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa2(&self) -> I2COA2R {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        I2COA2R { bits }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&self) -> UCOAENR {
+        UCOAENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa2(&mut self) -> _I2COA2W {
+        _I2COA2W { w: self }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&mut self) -> _UCOAENW {
+        _UCOAENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b3/ucbx_i2coa3.rs b/example-source/msp432p401r/src/eusci_b3/ucbx_i2coa3.rs
new file mode 100644
index 0000000..8cab4f2
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b3/ucbx_i2coa3.rs
@@ -0,0 +1,224 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXI2COA3 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct I2COA3R {
+    bits: u16,
+}
+impl I2COA3R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `UCOAEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCOAENR {
+    #[doc = "The slave address defined in I2COA3 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA3 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCOAENR::UCOAEN_0 => false,
+            UCOAENR::UCOAEN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCOAENR {
+        match value {
+            false => UCOAENR::UCOAEN_0,
+            true => UCOAENR::UCOAEN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_0`"]
+    #[inline]
+    pub fn is_ucoaen_0(&self) -> bool {
+        *self == UCOAENR::UCOAEN_0
+    }
+    #[doc = "Checks if the value of the field is `UCOAEN_1`"]
+    #[inline]
+    pub fn is_ucoaen_1(&self) -> bool {
+        *self == UCOAENR::UCOAEN_1
+    }
+}
+#[doc = r" Proxy"]
+pub struct _I2COA3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _I2COA3W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCOAEN`"]
+pub enum UCOAENW {
+    #[doc = "The slave address defined in I2COA3 is disabled"]
+    UCOAEN_0,
+    #[doc = "The slave address defined in I2COA3 is enabled"]
+    UCOAEN_1,
+}
+impl UCOAENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCOAENW::UCOAEN_0 => false,
+            UCOAENW::UCOAEN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCOAENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCOAENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCOAENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The slave address defined in I2COA3 is disabled"]
+    #[inline]
+    pub fn ucoaen_0(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_0)
+    }
+    #[doc = "The slave address defined in I2COA3 is enabled"]
+    #[inline]
+    pub fn ucoaen_1(self) -> &'a mut W {
+        self.variant(UCOAENW::UCOAEN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa3(&self) -> I2COA3R {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        I2COA3R { bits }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&self) -> UCOAENR {
+        UCOAENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:9 - I2C own address"]
+    #[inline]
+    pub fn i2coa3(&mut self) -> _I2COA3W {
+        _I2COA3W { w: self }
+    }
+    #[doc = "Bit 10 - Own Address enable register"]
+    #[inline]
+    pub fn ucoaen(&mut self) -> _UCOAENW {
+        _UCOAENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b3/ucbx_i2csa.rs b/example-source/msp432p401r/src/eusci_b3/ucbx_i2csa.rs
new file mode 100644
index 0000000..33de734
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b3/ucbx_i2csa.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXI2CSA {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct I2CSAR {
+    bits: u16,
+}
+impl I2CSAR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _I2CSAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _I2CSAW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - I2C slave address"]
+    #[inline]
+    pub fn i2csa(&self) -> I2CSAR {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        I2CSAR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:9 - I2C slave address"]
+    #[inline]
+    pub fn i2csa(&mut self) -> _I2CSAW {
+        _I2CSAW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b3/ucbx_ie.rs b/example-source/msp432p401r/src/eusci_b3/ucbx_ie.rs
new file mode 100644
index 0000000..7c9f18c
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b3/ucbx_ie.rs
@@ -0,0 +1,1849 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXIE {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCRXIE0`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIE0R {
+    #[doc = "Interrupt disabled"]
+    UCRXIE0_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE0_1,
+}
+impl UCRXIE0R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIE0R::UCRXIE0_0 => false,
+            UCRXIE0R::UCRXIE0_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIE0R {
+        match value {
+            false => UCRXIE0R::UCRXIE0_0,
+            true => UCRXIE0R::UCRXIE0_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE0_0`"]
+    #[inline]
+    pub fn is_ucrxie0_0(&self) -> bool {
+        *self == UCRXIE0R::UCRXIE0_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE0_1`"]
+    #[inline]
+    pub fn is_ucrxie0_1(&self) -> bool {
+        *self == UCRXIE0R::UCRXIE0_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIE0`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIE0R {
+    #[doc = "Interrupt disabled"]
+    UCTXIE0_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE0_1,
+}
+impl UCTXIE0R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIE0R::UCTXIE0_0 => false,
+            UCTXIE0R::UCTXIE0_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIE0R {
+        match value {
+            false => UCTXIE0R::UCTXIE0_0,
+            true => UCTXIE0R::UCTXIE0_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE0_0`"]
+    #[inline]
+    pub fn is_uctxie0_0(&self) -> bool {
+        *self == UCTXIE0R::UCTXIE0_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE0_1`"]
+    #[inline]
+    pub fn is_uctxie0_1(&self) -> bool {
+        *self == UCTXIE0R::UCTXIE0_1
+    }
+}
+#[doc = "Possible values of the field `UCSTTIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTTIER {
+    #[doc = "Interrupt disabled"]
+    UCSTTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCSTTIE_1,
+}
+impl UCSTTIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTTIER::UCSTTIE_0 => false,
+            UCSTTIER::UCSTTIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTTIER {
+        match value {
+            false => UCSTTIER::UCSTTIE_0,
+            true => UCSTTIER::UCSTTIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIE_0`"]
+    #[inline]
+    pub fn is_ucsttie_0(&self) -> bool {
+        *self == UCSTTIER::UCSTTIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIE_1`"]
+    #[inline]
+    pub fn is_ucsttie_1(&self) -> bool {
+        *self == UCSTTIER::UCSTTIE_1
+    }
+}
+#[doc = "Possible values of the field `UCSTPIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTPIER {
+    #[doc = "Interrupt disabled"]
+    UCSTPIE_0,
+    #[doc = "Interrupt enabled"]
+    UCSTPIE_1,
+}
+impl UCSTPIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTPIER::UCSTPIE_0 => false,
+            UCSTPIER::UCSTPIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTPIER {
+        match value {
+            false => UCSTPIER::UCSTPIE_0,
+            true => UCSTPIER::UCSTPIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTPIE_0`"]
+    #[inline]
+    pub fn is_ucstpie_0(&self) -> bool {
+        *self == UCSTPIER::UCSTPIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTPIE_1`"]
+    #[inline]
+    pub fn is_ucstpie_1(&self) -> bool {
+        *self == UCSTPIER::UCSTPIE_1
+    }
+}
+#[doc = "Possible values of the field `UCALIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCALIER {
+    #[doc = "Interrupt disabled"]
+    UCALIE_0,
+    #[doc = "Interrupt enabled"]
+    UCALIE_1,
+}
+impl UCALIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCALIER::UCALIE_0 => false,
+            UCALIER::UCALIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCALIER {
+        match value {
+            false => UCALIER::UCALIE_0,
+            true => UCALIER::UCALIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCALIE_0`"]
+    #[inline]
+    pub fn is_ucalie_0(&self) -> bool {
+        *self == UCALIER::UCALIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCALIE_1`"]
+    #[inline]
+    pub fn is_ucalie_1(&self) -> bool {
+        *self == UCALIER::UCALIE_1
+    }
+}
+#[doc = "Possible values of the field `UCNACKIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCNACKIER {
+    #[doc = "Interrupt disabled"]
+    UCNACKIE_0,
+    #[doc = "Interrupt enabled"]
+    UCNACKIE_1,
+}
+impl UCNACKIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCNACKIER::UCNACKIE_0 => false,
+            UCNACKIER::UCNACKIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCNACKIER {
+        match value {
+            false => UCNACKIER::UCNACKIE_0,
+            true => UCNACKIER::UCNACKIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCNACKIE_0`"]
+    #[inline]
+    pub fn is_ucnackie_0(&self) -> bool {
+        *self == UCNACKIER::UCNACKIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCNACKIE_1`"]
+    #[inline]
+    pub fn is_ucnackie_1(&self) -> bool {
+        *self == UCNACKIER::UCNACKIE_1
+    }
+}
+#[doc = "Possible values of the field `UCBCNTIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBCNTIER {
+    #[doc = "Interrupt disabled"]
+    UCBCNTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCBCNTIE_1,
+}
+impl UCBCNTIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBCNTIER::UCBCNTIE_0 => false,
+            UCBCNTIER::UCBCNTIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBCNTIER {
+        match value {
+            false => UCBCNTIER::UCBCNTIE_0,
+            true => UCBCNTIER::UCBCNTIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBCNTIE_0`"]
+    #[inline]
+    pub fn is_ucbcntie_0(&self) -> bool {
+        *self == UCBCNTIER::UCBCNTIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCBCNTIE_1`"]
+    #[inline]
+    pub fn is_ucbcntie_1(&self) -> bool {
+        *self == UCBCNTIER::UCBCNTIE_1
+    }
+}
+#[doc = "Possible values of the field `UCCLTOIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCCLTOIER {
+    #[doc = "Interrupt disabled"]
+    UCCLTOIE_0,
+    #[doc = "Interrupt enabled"]
+    UCCLTOIE_1,
+}
+impl UCCLTOIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCCLTOIER::UCCLTOIE_0 => false,
+            UCCLTOIER::UCCLTOIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCCLTOIER {
+        match value {
+            false => UCCLTOIER::UCCLTOIE_0,
+            true => UCCLTOIER::UCCLTOIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCCLTOIE_0`"]
+    #[inline]
+    pub fn is_uccltoie_0(&self) -> bool {
+        *self == UCCLTOIER::UCCLTOIE_0
+    }
+    #[doc = "Checks if the value of the field is `UCCLTOIE_1`"]
+    #[inline]
+    pub fn is_uccltoie_1(&self) -> bool {
+        *self == UCCLTOIER::UCCLTOIE_1
+    }
+}
+#[doc = "Possible values of the field `UCRXIE1`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIE1R {
+    #[doc = "Interrupt disabled"]
+    UCRXIE1_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE1_1,
+}
+impl UCRXIE1R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIE1R::UCRXIE1_0 => false,
+            UCRXIE1R::UCRXIE1_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIE1R {
+        match value {
+            false => UCRXIE1R::UCRXIE1_0,
+            true => UCRXIE1R::UCRXIE1_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE1_0`"]
+    #[inline]
+    pub fn is_ucrxie1_0(&self) -> bool {
+        *self == UCRXIE1R::UCRXIE1_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE1_1`"]
+    #[inline]
+    pub fn is_ucrxie1_1(&self) -> bool {
+        *self == UCRXIE1R::UCRXIE1_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIE1`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIE1R {
+    #[doc = "Interrupt disabled"]
+    UCTXIE1_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE1_1,
+}
+impl UCTXIE1R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIE1R::UCTXIE1_0 => false,
+            UCTXIE1R::UCTXIE1_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIE1R {
+        match value {
+            false => UCTXIE1R::UCTXIE1_0,
+            true => UCTXIE1R::UCTXIE1_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE1_0`"]
+    #[inline]
+    pub fn is_uctxie1_0(&self) -> bool {
+        *self == UCTXIE1R::UCTXIE1_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE1_1`"]
+    #[inline]
+    pub fn is_uctxie1_1(&self) -> bool {
+        *self == UCTXIE1R::UCTXIE1_1
+    }
+}
+#[doc = "Possible values of the field `UCRXIE2`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIE2R {
+    #[doc = "Interrupt disabled"]
+    UCRXIE2_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE2_1,
+}
+impl UCRXIE2R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIE2R::UCRXIE2_0 => false,
+            UCRXIE2R::UCRXIE2_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIE2R {
+        match value {
+            false => UCRXIE2R::UCRXIE2_0,
+            true => UCRXIE2R::UCRXIE2_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE2_0`"]
+    #[inline]
+    pub fn is_ucrxie2_0(&self) -> bool {
+        *self == UCRXIE2R::UCRXIE2_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE2_1`"]
+    #[inline]
+    pub fn is_ucrxie2_1(&self) -> bool {
+        *self == UCRXIE2R::UCRXIE2_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIE2`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIE2R {
+    #[doc = "Interrupt disabled"]
+    UCTXIE2_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE2_1,
+}
+impl UCTXIE2R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIE2R::UCTXIE2_0 => false,
+            UCTXIE2R::UCTXIE2_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIE2R {
+        match value {
+            false => UCTXIE2R::UCTXIE2_0,
+            true => UCTXIE2R::UCTXIE2_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE2_0`"]
+    #[inline]
+    pub fn is_uctxie2_0(&self) -> bool {
+        *self == UCTXIE2R::UCTXIE2_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE2_1`"]
+    #[inline]
+    pub fn is_uctxie2_1(&self) -> bool {
+        *self == UCTXIE2R::UCTXIE2_1
+    }
+}
+#[doc = "Possible values of the field `UCRXIE3`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIE3R {
+    #[doc = "Interrupt disabled"]
+    UCRXIE3_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE3_1,
+}
+impl UCRXIE3R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIE3R::UCRXIE3_0 => false,
+            UCRXIE3R::UCRXIE3_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIE3R {
+        match value {
+            false => UCRXIE3R::UCRXIE3_0,
+            true => UCRXIE3R::UCRXIE3_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE3_0`"]
+    #[inline]
+    pub fn is_ucrxie3_0(&self) -> bool {
+        *self == UCRXIE3R::UCRXIE3_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIE3_1`"]
+    #[inline]
+    pub fn is_ucrxie3_1(&self) -> bool {
+        *self == UCRXIE3R::UCRXIE3_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIE3`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIE3R {
+    #[doc = "Interrupt disabled"]
+    UCTXIE3_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE3_1,
+}
+impl UCTXIE3R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIE3R::UCTXIE3_0 => false,
+            UCTXIE3R::UCTXIE3_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIE3R {
+        match value {
+            false => UCTXIE3R::UCTXIE3_0,
+            true => UCTXIE3R::UCTXIE3_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE3_0`"]
+    #[inline]
+    pub fn is_uctxie3_0(&self) -> bool {
+        *self == UCTXIE3R::UCTXIE3_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIE3_1`"]
+    #[inline]
+    pub fn is_uctxie3_1(&self) -> bool {
+        *self == UCTXIE3R::UCTXIE3_1
+    }
+}
+#[doc = "Possible values of the field `UCBIT9IE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBIT9IER {
+    #[doc = "Interrupt disabled"]
+    UCBIT9IE_0,
+    #[doc = "Interrupt enabled"]
+    UCBIT9IE_1,
+}
+impl UCBIT9IER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBIT9IER::UCBIT9IE_0 => false,
+            UCBIT9IER::UCBIT9IE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBIT9IER {
+        match value {
+            false => UCBIT9IER::UCBIT9IE_0,
+            true => UCBIT9IER::UCBIT9IE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBIT9IE_0`"]
+    #[inline]
+    pub fn is_ucbit9ie_0(&self) -> bool {
+        *self == UCBIT9IER::UCBIT9IE_0
+    }
+    #[doc = "Checks if the value of the field is `UCBIT9IE_1`"]
+    #[inline]
+    pub fn is_ucbit9ie_1(&self) -> bool {
+        *self == UCBIT9IER::UCBIT9IE_1
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIE0`"]
+pub enum UCRXIE0W {
+    #[doc = "Interrupt disabled"]
+    UCRXIE0_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE0_1,
+}
+impl UCRXIE0W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIE0W::UCRXIE0_0 => false,
+            UCRXIE0W::UCRXIE0_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIE0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIE0W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIE0W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucrxie0_0(self) -> &'a mut W {
+        self.variant(UCRXIE0W::UCRXIE0_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucrxie0_1(self) -> &'a mut W {
+        self.variant(UCRXIE0W::UCRXIE0_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIE0`"]
+pub enum UCTXIE0W {
+    #[doc = "Interrupt disabled"]
+    UCTXIE0_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE0_1,
+}
+impl UCTXIE0W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIE0W::UCTXIE0_0 => false,
+            UCTXIE0W::UCTXIE0_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIE0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIE0W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIE0W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn uctxie0_0(self) -> &'a mut W {
+        self.variant(UCTXIE0W::UCTXIE0_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn uctxie0_1(self) -> &'a mut W {
+        self.variant(UCTXIE0W::UCTXIE0_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTTIE`"]
+pub enum UCSTTIEW {
+    #[doc = "Interrupt disabled"]
+    UCSTTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCSTTIE_1,
+}
+impl UCSTTIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTTIEW::UCSTTIE_0 => false,
+            UCSTTIEW::UCSTTIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTTIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTTIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTTIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucsttie_0(self) -> &'a mut W {
+        self.variant(UCSTTIEW::UCSTTIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucsttie_1(self) -> &'a mut W {
+        self.variant(UCSTTIEW::UCSTTIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTPIE`"]
+pub enum UCSTPIEW {
+    #[doc = "Interrupt disabled"]
+    UCSTPIE_0,
+    #[doc = "Interrupt enabled"]
+    UCSTPIE_1,
+}
+impl UCSTPIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTPIEW::UCSTPIE_0 => false,
+            UCSTPIEW::UCSTPIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTPIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTPIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTPIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucstpie_0(self) -> &'a mut W {
+        self.variant(UCSTPIEW::UCSTPIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucstpie_1(self) -> &'a mut W {
+        self.variant(UCSTPIEW::UCSTPIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCALIE`"]
+pub enum UCALIEW {
+    #[doc = "Interrupt disabled"]
+    UCALIE_0,
+    #[doc = "Interrupt enabled"]
+    UCALIE_1,
+}
+impl UCALIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCALIEW::UCALIE_0 => false,
+            UCALIEW::UCALIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCALIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCALIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCALIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucalie_0(self) -> &'a mut W {
+        self.variant(UCALIEW::UCALIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucalie_1(self) -> &'a mut W {
+        self.variant(UCALIEW::UCALIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCNACKIE`"]
+pub enum UCNACKIEW {
+    #[doc = "Interrupt disabled"]
+    UCNACKIE_0,
+    #[doc = "Interrupt enabled"]
+    UCNACKIE_1,
+}
+impl UCNACKIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCNACKIEW::UCNACKIE_0 => false,
+            UCNACKIEW::UCNACKIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCNACKIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCNACKIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCNACKIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucnackie_0(self) -> &'a mut W {
+        self.variant(UCNACKIEW::UCNACKIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucnackie_1(self) -> &'a mut W {
+        self.variant(UCNACKIEW::UCNACKIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCBCNTIE`"]
+pub enum UCBCNTIEW {
+    #[doc = "Interrupt disabled"]
+    UCBCNTIE_0,
+    #[doc = "Interrupt enabled"]
+    UCBCNTIE_1,
+}
+impl UCBCNTIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCBCNTIEW::UCBCNTIE_0 => false,
+            UCBCNTIEW::UCBCNTIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBCNTIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBCNTIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCBCNTIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucbcntie_0(self) -> &'a mut W {
+        self.variant(UCBCNTIEW::UCBCNTIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucbcntie_1(self) -> &'a mut W {
+        self.variant(UCBCNTIEW::UCBCNTIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCCLTOIE`"]
+pub enum UCCLTOIEW {
+    #[doc = "Interrupt disabled"]
+    UCCLTOIE_0,
+    #[doc = "Interrupt enabled"]
+    UCCLTOIE_1,
+}
+impl UCCLTOIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCCLTOIEW::UCCLTOIE_0 => false,
+            UCCLTOIEW::UCCLTOIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCCLTOIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCCLTOIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCCLTOIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn uccltoie_0(self) -> &'a mut W {
+        self.variant(UCCLTOIEW::UCCLTOIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn uccltoie_1(self) -> &'a mut W {
+        self.variant(UCCLTOIEW::UCCLTOIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIE1`"]
+pub enum UCRXIE1W {
+    #[doc = "Interrupt disabled"]
+    UCRXIE1_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE1_1,
+}
+impl UCRXIE1W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIE1W::UCRXIE1_0 => false,
+            UCRXIE1W::UCRXIE1_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIE1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIE1W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIE1W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucrxie1_0(self) -> &'a mut W {
+        self.variant(UCRXIE1W::UCRXIE1_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucrxie1_1(self) -> &'a mut W {
+        self.variant(UCRXIE1W::UCRXIE1_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIE1`"]
+pub enum UCTXIE1W {
+    #[doc = "Interrupt disabled"]
+    UCTXIE1_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE1_1,
+}
+impl UCTXIE1W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIE1W::UCTXIE1_0 => false,
+            UCTXIE1W::UCTXIE1_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIE1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIE1W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIE1W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn uctxie1_0(self) -> &'a mut W {
+        self.variant(UCTXIE1W::UCTXIE1_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn uctxie1_1(self) -> &'a mut W {
+        self.variant(UCTXIE1W::UCTXIE1_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIE2`"]
+pub enum UCRXIE2W {
+    #[doc = "Interrupt disabled"]
+    UCRXIE2_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE2_1,
+}
+impl UCRXIE2W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIE2W::UCRXIE2_0 => false,
+            UCRXIE2W::UCRXIE2_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIE2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIE2W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIE2W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucrxie2_0(self) -> &'a mut W {
+        self.variant(UCRXIE2W::UCRXIE2_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucrxie2_1(self) -> &'a mut W {
+        self.variant(UCRXIE2W::UCRXIE2_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIE2`"]
+pub enum UCTXIE2W {
+    #[doc = "Interrupt disabled"]
+    UCTXIE2_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE2_1,
+}
+impl UCTXIE2W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIE2W::UCTXIE2_0 => false,
+            UCTXIE2W::UCTXIE2_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIE2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIE2W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIE2W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn uctxie2_0(self) -> &'a mut W {
+        self.variant(UCTXIE2W::UCTXIE2_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn uctxie2_1(self) -> &'a mut W {
+        self.variant(UCTXIE2W::UCTXIE2_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIE3`"]
+pub enum UCRXIE3W {
+    #[doc = "Interrupt disabled"]
+    UCRXIE3_0,
+    #[doc = "Interrupt enabled"]
+    UCRXIE3_1,
+}
+impl UCRXIE3W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIE3W::UCRXIE3_0 => false,
+            UCRXIE3W::UCRXIE3_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIE3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIE3W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIE3W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucrxie3_0(self) -> &'a mut W {
+        self.variant(UCRXIE3W::UCRXIE3_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucrxie3_1(self) -> &'a mut W {
+        self.variant(UCRXIE3W::UCRXIE3_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIE3`"]
+pub enum UCTXIE3W {
+    #[doc = "Interrupt disabled"]
+    UCTXIE3_0,
+    #[doc = "Interrupt enabled"]
+    UCTXIE3_1,
+}
+impl UCTXIE3W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIE3W::UCTXIE3_0 => false,
+            UCTXIE3W::UCTXIE3_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIE3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIE3W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIE3W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn uctxie3_0(self) -> &'a mut W {
+        self.variant(UCTXIE3W::UCTXIE3_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn uctxie3_1(self) -> &'a mut W {
+        self.variant(UCTXIE3W::UCTXIE3_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCBIT9IE`"]
+pub enum UCBIT9IEW {
+    #[doc = "Interrupt disabled"]
+    UCBIT9IE_0,
+    #[doc = "Interrupt enabled"]
+    UCBIT9IE_1,
+}
+impl UCBIT9IEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCBIT9IEW::UCBIT9IE_0 => false,
+            UCBIT9IEW::UCBIT9IE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBIT9IEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBIT9IEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCBIT9IEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ucbit9ie_0(self) -> &'a mut W {
+        self.variant(UCBIT9IEW::UCBIT9IE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ucbit9ie_1(self) -> &'a mut W {
+        self.variant(UCBIT9IEW::UCBIT9IE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Receive interrupt enable 0"]
+    #[inline]
+    pub fn ucrxie0(&self) -> UCRXIE0R {
+        UCRXIE0R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Transmit interrupt enable 0"]
+    #[inline]
+    pub fn uctxie0(&self) -> UCTXIE0R {
+        UCTXIE0R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - START condition interrupt enable"]
+    #[inline]
+    pub fn ucsttie(&self) -> UCSTTIER {
+        UCSTTIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - STOP condition interrupt enable"]
+    #[inline]
+    pub fn ucstpie(&self) -> UCSTPIER {
+        UCSTPIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 4 - Arbitration lost interrupt enable"]
+    #[inline]
+    pub fn ucalie(&self) -> UCALIER {
+        UCALIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - Not-acknowledge interrupt enable"]
+    #[inline]
+    pub fn ucnackie(&self) -> UCNACKIER {
+        UCNACKIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 6 - Byte counter interrupt enable"]
+    #[inline]
+    pub fn ucbcntie(&self) -> UCBCNTIER {
+        UCBCNTIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 7 - Clock low timeout interrupt enable"]
+    #[inline]
+    pub fn uccltoie(&self) -> UCCLTOIER {
+        UCCLTOIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 8 - Receive interrupt enable 1"]
+    #[inline]
+    pub fn ucrxie1(&self) -> UCRXIE1R {
+        UCRXIE1R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 9 - Transmit interrupt enable 1"]
+    #[inline]
+    pub fn uctxie1(&self) -> UCTXIE1R {
+        UCTXIE1R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 10 - Receive interrupt enable 2"]
+    #[inline]
+    pub fn ucrxie2(&self) -> UCRXIE2R {
+        UCRXIE2R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 11 - Transmit interrupt enable 2"]
+    #[inline]
+    pub fn uctxie2(&self) -> UCTXIE2R {
+        UCTXIE2R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 12 - Receive interrupt enable 3"]
+    #[inline]
+    pub fn ucrxie3(&self) -> UCRXIE3R {
+        UCRXIE3R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 13 - Transmit interrupt enable 3"]
+    #[inline]
+    pub fn uctxie3(&self) -> UCTXIE3R {
+        UCTXIE3R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 14 - Bit position 9 interrupt enable"]
+    #[inline]
+    pub fn ucbit9ie(&self) -> UCBIT9IER {
+        UCBIT9IER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Receive interrupt enable 0"]
+    #[inline]
+    pub fn ucrxie0(&mut self) -> _UCRXIE0W {
+        _UCRXIE0W { w: self }
+    }
+    #[doc = "Bit 1 - Transmit interrupt enable 0"]
+    #[inline]
+    pub fn uctxie0(&mut self) -> _UCTXIE0W {
+        _UCTXIE0W { w: self }
+    }
+    #[doc = "Bit 2 - START condition interrupt enable"]
+    #[inline]
+    pub fn ucsttie(&mut self) -> _UCSTTIEW {
+        _UCSTTIEW { w: self }
+    }
+    #[doc = "Bit 3 - STOP condition interrupt enable"]
+    #[inline]
+    pub fn ucstpie(&mut self) -> _UCSTPIEW {
+        _UCSTPIEW { w: self }
+    }
+    #[doc = "Bit 4 - Arbitration lost interrupt enable"]
+    #[inline]
+    pub fn ucalie(&mut self) -> _UCALIEW {
+        _UCALIEW { w: self }
+    }
+    #[doc = "Bit 5 - Not-acknowledge interrupt enable"]
+    #[inline]
+    pub fn ucnackie(&mut self) -> _UCNACKIEW {
+        _UCNACKIEW { w: self }
+    }
+    #[doc = "Bit 6 - Byte counter interrupt enable"]
+    #[inline]
+    pub fn ucbcntie(&mut self) -> _UCBCNTIEW {
+        _UCBCNTIEW { w: self }
+    }
+    #[doc = "Bit 7 - Clock low timeout interrupt enable"]
+    #[inline]
+    pub fn uccltoie(&mut self) -> _UCCLTOIEW {
+        _UCCLTOIEW { w: self }
+    }
+    #[doc = "Bit 8 - Receive interrupt enable 1"]
+    #[inline]
+    pub fn ucrxie1(&mut self) -> _UCRXIE1W {
+        _UCRXIE1W { w: self }
+    }
+    #[doc = "Bit 9 - Transmit interrupt enable 1"]
+    #[inline]
+    pub fn uctxie1(&mut self) -> _UCTXIE1W {
+        _UCTXIE1W { w: self }
+    }
+    #[doc = "Bit 10 - Receive interrupt enable 2"]
+    #[inline]
+    pub fn ucrxie2(&mut self) -> _UCRXIE2W {
+        _UCRXIE2W { w: self }
+    }
+    #[doc = "Bit 11 - Transmit interrupt enable 2"]
+    #[inline]
+    pub fn uctxie2(&mut self) -> _UCTXIE2W {
+        _UCTXIE2W { w: self }
+    }
+    #[doc = "Bit 12 - Receive interrupt enable 3"]
+    #[inline]
+    pub fn ucrxie3(&mut self) -> _UCRXIE3W {
+        _UCRXIE3W { w: self }
+    }
+    #[doc = "Bit 13 - Transmit interrupt enable 3"]
+    #[inline]
+    pub fn uctxie3(&mut self) -> _UCTXIE3W {
+        _UCTXIE3W { w: self }
+    }
+    #[doc = "Bit 14 - Bit position 9 interrupt enable"]
+    #[inline]
+    pub fn ucbit9ie(&mut self) -> _UCBIT9IEW {
+        _UCBIT9IEW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b3/ucbx_ifg.rs b/example-source/msp432p401r/src/eusci_b3/ucbx_ifg.rs
new file mode 100644
index 0000000..28681c9
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b3/ucbx_ifg.rs
@@ -0,0 +1,1849 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXIFG {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCRXIFG0`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIFG0R {
+    #[doc = "No interrupt pending"]
+    UCRXIFG0_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG0_1,
+}
+impl UCRXIFG0R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIFG0R::UCRXIFG0_0 => false,
+            UCRXIFG0R::UCRXIFG0_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIFG0R {
+        match value {
+            false => UCRXIFG0R::UCRXIFG0_0,
+            true => UCRXIFG0R::UCRXIFG0_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG0_0`"]
+    #[inline]
+    pub fn is_ucrxifg0_0(&self) -> bool {
+        *self == UCRXIFG0R::UCRXIFG0_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG0_1`"]
+    #[inline]
+    pub fn is_ucrxifg0_1(&self) -> bool {
+        *self == UCRXIFG0R::UCRXIFG0_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIFG0`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIFG0R {
+    #[doc = "No interrupt pending"]
+    UCTXIFG0_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG0_1,
+}
+impl UCTXIFG0R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIFG0R::UCTXIFG0_0 => false,
+            UCTXIFG0R::UCTXIFG0_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIFG0R {
+        match value {
+            false => UCTXIFG0R::UCTXIFG0_0,
+            true => UCTXIFG0R::UCTXIFG0_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG0_0`"]
+    #[inline]
+    pub fn is_uctxifg0_0(&self) -> bool {
+        *self == UCTXIFG0R::UCTXIFG0_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG0_1`"]
+    #[inline]
+    pub fn is_uctxifg0_1(&self) -> bool {
+        *self == UCTXIFG0R::UCTXIFG0_1
+    }
+}
+#[doc = "Possible values of the field `UCSTTIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTTIFGR {
+    #[doc = "No interrupt pending"]
+    UCSTTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCSTTIFG_1,
+}
+impl UCSTTIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTTIFGR::UCSTTIFG_0 => false,
+            UCSTTIFGR::UCSTTIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTTIFGR {
+        match value {
+            false => UCSTTIFGR::UCSTTIFG_0,
+            true => UCSTTIFGR::UCSTTIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIFG_0`"]
+    #[inline]
+    pub fn is_ucsttifg_0(&self) -> bool {
+        *self == UCSTTIFGR::UCSTTIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTTIFG_1`"]
+    #[inline]
+    pub fn is_ucsttifg_1(&self) -> bool {
+        *self == UCSTTIFGR::UCSTTIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCSTPIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSTPIFGR {
+    #[doc = "No interrupt pending"]
+    UCSTPIFG_0,
+    #[doc = "Interrupt pending"]
+    UCSTPIFG_1,
+}
+impl UCSTPIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSTPIFGR::UCSTPIFG_0 => false,
+            UCSTPIFGR::UCSTPIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSTPIFGR {
+        match value {
+            false => UCSTPIFGR::UCSTPIFG_0,
+            true => UCSTPIFGR::UCSTPIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSTPIFG_0`"]
+    #[inline]
+    pub fn is_ucstpifg_0(&self) -> bool {
+        *self == UCSTPIFGR::UCSTPIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCSTPIFG_1`"]
+    #[inline]
+    pub fn is_ucstpifg_1(&self) -> bool {
+        *self == UCSTPIFGR::UCSTPIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCALIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCALIFGR {
+    #[doc = "No interrupt pending"]
+    UCALIFG_0,
+    #[doc = "Interrupt pending"]
+    UCALIFG_1,
+}
+impl UCALIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCALIFGR::UCALIFG_0 => false,
+            UCALIFGR::UCALIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCALIFGR {
+        match value {
+            false => UCALIFGR::UCALIFG_0,
+            true => UCALIFGR::UCALIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCALIFG_0`"]
+    #[inline]
+    pub fn is_ucalifg_0(&self) -> bool {
+        *self == UCALIFGR::UCALIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCALIFG_1`"]
+    #[inline]
+    pub fn is_ucalifg_1(&self) -> bool {
+        *self == UCALIFGR::UCALIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCNACKIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCNACKIFGR {
+    #[doc = "No interrupt pending"]
+    UCNACKIFG_0,
+    #[doc = "Interrupt pending"]
+    UCNACKIFG_1,
+}
+impl UCNACKIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCNACKIFGR::UCNACKIFG_0 => false,
+            UCNACKIFGR::UCNACKIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCNACKIFGR {
+        match value {
+            false => UCNACKIFGR::UCNACKIFG_0,
+            true => UCNACKIFGR::UCNACKIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCNACKIFG_0`"]
+    #[inline]
+    pub fn is_ucnackifg_0(&self) -> bool {
+        *self == UCNACKIFGR::UCNACKIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCNACKIFG_1`"]
+    #[inline]
+    pub fn is_ucnackifg_1(&self) -> bool {
+        *self == UCNACKIFGR::UCNACKIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCBCNTIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBCNTIFGR {
+    #[doc = "No interrupt pending"]
+    UCBCNTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCBCNTIFG_1,
+}
+impl UCBCNTIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBCNTIFGR::UCBCNTIFG_0 => false,
+            UCBCNTIFGR::UCBCNTIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBCNTIFGR {
+        match value {
+            false => UCBCNTIFGR::UCBCNTIFG_0,
+            true => UCBCNTIFGR::UCBCNTIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBCNTIFG_0`"]
+    #[inline]
+    pub fn is_ucbcntifg_0(&self) -> bool {
+        *self == UCBCNTIFGR::UCBCNTIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCBCNTIFG_1`"]
+    #[inline]
+    pub fn is_ucbcntifg_1(&self) -> bool {
+        *self == UCBCNTIFGR::UCBCNTIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCCLTOIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCCLTOIFGR {
+    #[doc = "No interrupt pending"]
+    UCCLTOIFG_0,
+    #[doc = "Interrupt pending"]
+    UCCLTOIFG_1,
+}
+impl UCCLTOIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCCLTOIFGR::UCCLTOIFG_0 => false,
+            UCCLTOIFGR::UCCLTOIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCCLTOIFGR {
+        match value {
+            false => UCCLTOIFGR::UCCLTOIFG_0,
+            true => UCCLTOIFGR::UCCLTOIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCCLTOIFG_0`"]
+    #[inline]
+    pub fn is_uccltoifg_0(&self) -> bool {
+        *self == UCCLTOIFGR::UCCLTOIFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCCLTOIFG_1`"]
+    #[inline]
+    pub fn is_uccltoifg_1(&self) -> bool {
+        *self == UCCLTOIFGR::UCCLTOIFG_1
+    }
+}
+#[doc = "Possible values of the field `UCRXIFG1`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIFG1R {
+    #[doc = "No interrupt pending"]
+    UCRXIFG1_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG1_1,
+}
+impl UCRXIFG1R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIFG1R::UCRXIFG1_0 => false,
+            UCRXIFG1R::UCRXIFG1_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIFG1R {
+        match value {
+            false => UCRXIFG1R::UCRXIFG1_0,
+            true => UCRXIFG1R::UCRXIFG1_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG1_0`"]
+    #[inline]
+    pub fn is_ucrxifg1_0(&self) -> bool {
+        *self == UCRXIFG1R::UCRXIFG1_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG1_1`"]
+    #[inline]
+    pub fn is_ucrxifg1_1(&self) -> bool {
+        *self == UCRXIFG1R::UCRXIFG1_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIFG1`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIFG1R {
+    #[doc = "No interrupt pending"]
+    UCTXIFG1_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG1_1,
+}
+impl UCTXIFG1R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIFG1R::UCTXIFG1_0 => false,
+            UCTXIFG1R::UCTXIFG1_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIFG1R {
+        match value {
+            false => UCTXIFG1R::UCTXIFG1_0,
+            true => UCTXIFG1R::UCTXIFG1_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG1_0`"]
+    #[inline]
+    pub fn is_uctxifg1_0(&self) -> bool {
+        *self == UCTXIFG1R::UCTXIFG1_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG1_1`"]
+    #[inline]
+    pub fn is_uctxifg1_1(&self) -> bool {
+        *self == UCTXIFG1R::UCTXIFG1_1
+    }
+}
+#[doc = "Possible values of the field `UCRXIFG2`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIFG2R {
+    #[doc = "No interrupt pending"]
+    UCRXIFG2_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG2_1,
+}
+impl UCRXIFG2R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIFG2R::UCRXIFG2_0 => false,
+            UCRXIFG2R::UCRXIFG2_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIFG2R {
+        match value {
+            false => UCRXIFG2R::UCRXIFG2_0,
+            true => UCRXIFG2R::UCRXIFG2_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG2_0`"]
+    #[inline]
+    pub fn is_ucrxifg2_0(&self) -> bool {
+        *self == UCRXIFG2R::UCRXIFG2_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG2_1`"]
+    #[inline]
+    pub fn is_ucrxifg2_1(&self) -> bool {
+        *self == UCRXIFG2R::UCRXIFG2_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIFG2`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIFG2R {
+    #[doc = "No interrupt pending"]
+    UCTXIFG2_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG2_1,
+}
+impl UCTXIFG2R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIFG2R::UCTXIFG2_0 => false,
+            UCTXIFG2R::UCTXIFG2_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIFG2R {
+        match value {
+            false => UCTXIFG2R::UCTXIFG2_0,
+            true => UCTXIFG2R::UCTXIFG2_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG2_0`"]
+    #[inline]
+    pub fn is_uctxifg2_0(&self) -> bool {
+        *self == UCTXIFG2R::UCTXIFG2_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG2_1`"]
+    #[inline]
+    pub fn is_uctxifg2_1(&self) -> bool {
+        *self == UCTXIFG2R::UCTXIFG2_1
+    }
+}
+#[doc = "Possible values of the field `UCRXIFG3`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCRXIFG3R {
+    #[doc = "No interrupt pending"]
+    UCRXIFG3_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG3_1,
+}
+impl UCRXIFG3R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCRXIFG3R::UCRXIFG3_0 => false,
+            UCRXIFG3R::UCRXIFG3_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCRXIFG3R {
+        match value {
+            false => UCRXIFG3R::UCRXIFG3_0,
+            true => UCRXIFG3R::UCRXIFG3_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG3_0`"]
+    #[inline]
+    pub fn is_ucrxifg3_0(&self) -> bool {
+        *self == UCRXIFG3R::UCRXIFG3_0
+    }
+    #[doc = "Checks if the value of the field is `UCRXIFG3_1`"]
+    #[inline]
+    pub fn is_ucrxifg3_1(&self) -> bool {
+        *self == UCRXIFG3R::UCRXIFG3_1
+    }
+}
+#[doc = "Possible values of the field `UCTXIFG3`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCTXIFG3R {
+    #[doc = "No interrupt pending"]
+    UCTXIFG3_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG3_1,
+}
+impl UCTXIFG3R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCTXIFG3R::UCTXIFG3_0 => false,
+            UCTXIFG3R::UCTXIFG3_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCTXIFG3R {
+        match value {
+            false => UCTXIFG3R::UCTXIFG3_0,
+            true => UCTXIFG3R::UCTXIFG3_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG3_0`"]
+    #[inline]
+    pub fn is_uctxifg3_0(&self) -> bool {
+        *self == UCTXIFG3R::UCTXIFG3_0
+    }
+    #[doc = "Checks if the value of the field is `UCTXIFG3_1`"]
+    #[inline]
+    pub fn is_uctxifg3_1(&self) -> bool {
+        *self == UCTXIFG3R::UCTXIFG3_1
+    }
+}
+#[doc = "Possible values of the field `UCBIT9IFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBIT9IFGR {
+    #[doc = "No interrupt pending"]
+    UCBIT9IFG_0,
+    #[doc = "Interrupt pending"]
+    UCBIT9IFG_1,
+}
+impl UCBIT9IFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBIT9IFGR::UCBIT9IFG_0 => false,
+            UCBIT9IFGR::UCBIT9IFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBIT9IFGR {
+        match value {
+            false => UCBIT9IFGR::UCBIT9IFG_0,
+            true => UCBIT9IFGR::UCBIT9IFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBIT9IFG_0`"]
+    #[inline]
+    pub fn is_ucbit9ifg_0(&self) -> bool {
+        *self == UCBIT9IFGR::UCBIT9IFG_0
+    }
+    #[doc = "Checks if the value of the field is `UCBIT9IFG_1`"]
+    #[inline]
+    pub fn is_ucbit9ifg_1(&self) -> bool {
+        *self == UCBIT9IFGR::UCBIT9IFG_1
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIFG0`"]
+pub enum UCRXIFG0W {
+    #[doc = "No interrupt pending"]
+    UCRXIFG0_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG0_1,
+}
+impl UCRXIFG0W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIFG0W::UCRXIFG0_0 => false,
+            UCRXIFG0W::UCRXIFG0_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIFG0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIFG0W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIFG0W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucrxifg0_0(self) -> &'a mut W {
+        self.variant(UCRXIFG0W::UCRXIFG0_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucrxifg0_1(self) -> &'a mut W {
+        self.variant(UCRXIFG0W::UCRXIFG0_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIFG0`"]
+pub enum UCTXIFG0W {
+    #[doc = "No interrupt pending"]
+    UCTXIFG0_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG0_1,
+}
+impl UCTXIFG0W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIFG0W::UCTXIFG0_0 => false,
+            UCTXIFG0W::UCTXIFG0_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIFG0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIFG0W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIFG0W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn uctxifg0_0(self) -> &'a mut W {
+        self.variant(UCTXIFG0W::UCTXIFG0_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn uctxifg0_1(self) -> &'a mut W {
+        self.variant(UCTXIFG0W::UCTXIFG0_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTTIFG`"]
+pub enum UCSTTIFGW {
+    #[doc = "No interrupt pending"]
+    UCSTTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCSTTIFG_1,
+}
+impl UCSTTIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTTIFGW::UCSTTIFG_0 => false,
+            UCSTTIFGW::UCSTTIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTTIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTTIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTTIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucsttifg_0(self) -> &'a mut W {
+        self.variant(UCSTTIFGW::UCSTTIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucsttifg_1(self) -> &'a mut W {
+        self.variant(UCSTTIFGW::UCSTTIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCSTPIFG`"]
+pub enum UCSTPIFGW {
+    #[doc = "No interrupt pending"]
+    UCSTPIFG_0,
+    #[doc = "Interrupt pending"]
+    UCSTPIFG_1,
+}
+impl UCSTPIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCSTPIFGW::UCSTPIFG_0 => false,
+            UCSTPIFGW::UCSTPIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCSTPIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCSTPIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCSTPIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucstpifg_0(self) -> &'a mut W {
+        self.variant(UCSTPIFGW::UCSTPIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucstpifg_1(self) -> &'a mut W {
+        self.variant(UCSTPIFGW::UCSTPIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCALIFG`"]
+pub enum UCALIFGW {
+    #[doc = "No interrupt pending"]
+    UCALIFG_0,
+    #[doc = "Interrupt pending"]
+    UCALIFG_1,
+}
+impl UCALIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCALIFGW::UCALIFG_0 => false,
+            UCALIFGW::UCALIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCALIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCALIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCALIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucalifg_0(self) -> &'a mut W {
+        self.variant(UCALIFGW::UCALIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucalifg_1(self) -> &'a mut W {
+        self.variant(UCALIFGW::UCALIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCNACKIFG`"]
+pub enum UCNACKIFGW {
+    #[doc = "No interrupt pending"]
+    UCNACKIFG_0,
+    #[doc = "Interrupt pending"]
+    UCNACKIFG_1,
+}
+impl UCNACKIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCNACKIFGW::UCNACKIFG_0 => false,
+            UCNACKIFGW::UCNACKIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCNACKIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCNACKIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCNACKIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucnackifg_0(self) -> &'a mut W {
+        self.variant(UCNACKIFGW::UCNACKIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucnackifg_1(self) -> &'a mut W {
+        self.variant(UCNACKIFGW::UCNACKIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCBCNTIFG`"]
+pub enum UCBCNTIFGW {
+    #[doc = "No interrupt pending"]
+    UCBCNTIFG_0,
+    #[doc = "Interrupt pending"]
+    UCBCNTIFG_1,
+}
+impl UCBCNTIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCBCNTIFGW::UCBCNTIFG_0 => false,
+            UCBCNTIFGW::UCBCNTIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBCNTIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBCNTIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCBCNTIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucbcntifg_0(self) -> &'a mut W {
+        self.variant(UCBCNTIFGW::UCBCNTIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucbcntifg_1(self) -> &'a mut W {
+        self.variant(UCBCNTIFGW::UCBCNTIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCCLTOIFG`"]
+pub enum UCCLTOIFGW {
+    #[doc = "No interrupt pending"]
+    UCCLTOIFG_0,
+    #[doc = "Interrupt pending"]
+    UCCLTOIFG_1,
+}
+impl UCCLTOIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCCLTOIFGW::UCCLTOIFG_0 => false,
+            UCCLTOIFGW::UCCLTOIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCCLTOIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCCLTOIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCCLTOIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn uccltoifg_0(self) -> &'a mut W {
+        self.variant(UCCLTOIFGW::UCCLTOIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn uccltoifg_1(self) -> &'a mut W {
+        self.variant(UCCLTOIFGW::UCCLTOIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIFG1`"]
+pub enum UCRXIFG1W {
+    #[doc = "No interrupt pending"]
+    UCRXIFG1_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG1_1,
+}
+impl UCRXIFG1W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIFG1W::UCRXIFG1_0 => false,
+            UCRXIFG1W::UCRXIFG1_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIFG1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIFG1W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIFG1W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucrxifg1_0(self) -> &'a mut W {
+        self.variant(UCRXIFG1W::UCRXIFG1_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucrxifg1_1(self) -> &'a mut W {
+        self.variant(UCRXIFG1W::UCRXIFG1_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIFG1`"]
+pub enum UCTXIFG1W {
+    #[doc = "No interrupt pending"]
+    UCTXIFG1_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG1_1,
+}
+impl UCTXIFG1W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIFG1W::UCTXIFG1_0 => false,
+            UCTXIFG1W::UCTXIFG1_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIFG1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIFG1W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIFG1W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn uctxifg1_0(self) -> &'a mut W {
+        self.variant(UCTXIFG1W::UCTXIFG1_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn uctxifg1_1(self) -> &'a mut W {
+        self.variant(UCTXIFG1W::UCTXIFG1_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIFG2`"]
+pub enum UCRXIFG2W {
+    #[doc = "No interrupt pending"]
+    UCRXIFG2_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG2_1,
+}
+impl UCRXIFG2W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIFG2W::UCRXIFG2_0 => false,
+            UCRXIFG2W::UCRXIFG2_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIFG2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIFG2W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIFG2W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucrxifg2_0(self) -> &'a mut W {
+        self.variant(UCRXIFG2W::UCRXIFG2_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucrxifg2_1(self) -> &'a mut W {
+        self.variant(UCRXIFG2W::UCRXIFG2_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIFG2`"]
+pub enum UCTXIFG2W {
+    #[doc = "No interrupt pending"]
+    UCTXIFG2_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG2_1,
+}
+impl UCTXIFG2W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIFG2W::UCTXIFG2_0 => false,
+            UCTXIFG2W::UCTXIFG2_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIFG2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIFG2W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIFG2W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn uctxifg2_0(self) -> &'a mut W {
+        self.variant(UCTXIFG2W::UCTXIFG2_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn uctxifg2_1(self) -> &'a mut W {
+        self.variant(UCTXIFG2W::UCTXIFG2_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCRXIFG3`"]
+pub enum UCRXIFG3W {
+    #[doc = "No interrupt pending"]
+    UCRXIFG3_0,
+    #[doc = "Interrupt pending"]
+    UCRXIFG3_1,
+}
+impl UCRXIFG3W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCRXIFG3W::UCRXIFG3_0 => false,
+            UCRXIFG3W::UCRXIFG3_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCRXIFG3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCRXIFG3W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCRXIFG3W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucrxifg3_0(self) -> &'a mut W {
+        self.variant(UCRXIFG3W::UCRXIFG3_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucrxifg3_1(self) -> &'a mut W {
+        self.variant(UCRXIFG3W::UCRXIFG3_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCTXIFG3`"]
+pub enum UCTXIFG3W {
+    #[doc = "No interrupt pending"]
+    UCTXIFG3_0,
+    #[doc = "Interrupt pending"]
+    UCTXIFG3_1,
+}
+impl UCTXIFG3W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCTXIFG3W::UCTXIFG3_0 => false,
+            UCTXIFG3W::UCTXIFG3_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXIFG3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXIFG3W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCTXIFG3W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn uctxifg3_0(self) -> &'a mut W {
+        self.variant(UCTXIFG3W::UCTXIFG3_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn uctxifg3_1(self) -> &'a mut W {
+        self.variant(UCTXIFG3W::UCTXIFG3_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UCBIT9IFG`"]
+pub enum UCBIT9IFGW {
+    #[doc = "No interrupt pending"]
+    UCBIT9IFG_0,
+    #[doc = "Interrupt pending"]
+    UCBIT9IFG_1,
+}
+impl UCBIT9IFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UCBIT9IFGW::UCBIT9IFG_0 => false,
+            UCBIT9IFGW::UCBIT9IFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCBIT9IFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCBIT9IFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UCBIT9IFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ucbit9ifg_0(self) -> &'a mut W {
+        self.variant(UCBIT9IFGW::UCBIT9IFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ucbit9ifg_1(self) -> &'a mut W {
+        self.variant(UCBIT9IFGW::UCBIT9IFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - eUSCI_B receive interrupt flag 0"]
+    #[inline]
+    pub fn ucrxifg0(&self) -> UCRXIFG0R {
+        UCRXIFG0R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - eUSCI_B transmit interrupt flag 0"]
+    #[inline]
+    pub fn uctxifg0(&self) -> UCTXIFG0R {
+        UCTXIFG0R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - START condition interrupt flag"]
+    #[inline]
+    pub fn ucsttifg(&self) -> UCSTTIFGR {
+        UCSTTIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - STOP condition interrupt flag"]
+    #[inline]
+    pub fn ucstpifg(&self) -> UCSTPIFGR {
+        UCSTPIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 4 - Arbitration lost interrupt flag"]
+    #[inline]
+    pub fn ucalifg(&self) -> UCALIFGR {
+        UCALIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - Not-acknowledge received interrupt flag"]
+    #[inline]
+    pub fn ucnackifg(&self) -> UCNACKIFGR {
+        UCNACKIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 6 - Byte counter interrupt flag"]
+    #[inline]
+    pub fn ucbcntifg(&self) -> UCBCNTIFGR {
+        UCBCNTIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 7 - Clock low timeout interrupt flag"]
+    #[inline]
+    pub fn uccltoifg(&self) -> UCCLTOIFGR {
+        UCCLTOIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 8 - eUSCI_B receive interrupt flag 1"]
+    #[inline]
+    pub fn ucrxifg1(&self) -> UCRXIFG1R {
+        UCRXIFG1R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 9 - eUSCI_B transmit interrupt flag 1"]
+    #[inline]
+    pub fn uctxifg1(&self) -> UCTXIFG1R {
+        UCTXIFG1R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 10 - eUSCI_B receive interrupt flag 2"]
+    #[inline]
+    pub fn ucrxifg2(&self) -> UCRXIFG2R {
+        UCRXIFG2R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 11 - eUSCI_B transmit interrupt flag 2"]
+    #[inline]
+    pub fn uctxifg2(&self) -> UCTXIFG2R {
+        UCTXIFG2R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 12 - eUSCI_B receive interrupt flag 3"]
+    #[inline]
+    pub fn ucrxifg3(&self) -> UCRXIFG3R {
+        UCRXIFG3R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 13 - eUSCI_B transmit interrupt flag 3"]
+    #[inline]
+    pub fn uctxifg3(&self) -> UCTXIFG3R {
+        UCTXIFG3R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 14 - Bit position 9 interrupt flag"]
+    #[inline]
+    pub fn ucbit9ifg(&self) -> UCBIT9IFGR {
+        UCBIT9IFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 2 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - eUSCI_B receive interrupt flag 0"]
+    #[inline]
+    pub fn ucrxifg0(&mut self) -> _UCRXIFG0W {
+        _UCRXIFG0W { w: self }
+    }
+    #[doc = "Bit 1 - eUSCI_B transmit interrupt flag 0"]
+    #[inline]
+    pub fn uctxifg0(&mut self) -> _UCTXIFG0W {
+        _UCTXIFG0W { w: self }
+    }
+    #[doc = "Bit 2 - START condition interrupt flag"]
+    #[inline]
+    pub fn ucsttifg(&mut self) -> _UCSTTIFGW {
+        _UCSTTIFGW { w: self }
+    }
+    #[doc = "Bit 3 - STOP condition interrupt flag"]
+    #[inline]
+    pub fn ucstpifg(&mut self) -> _UCSTPIFGW {
+        _UCSTPIFGW { w: self }
+    }
+    #[doc = "Bit 4 - Arbitration lost interrupt flag"]
+    #[inline]
+    pub fn ucalifg(&mut self) -> _UCALIFGW {
+        _UCALIFGW { w: self }
+    }
+    #[doc = "Bit 5 - Not-acknowledge received interrupt flag"]
+    #[inline]
+    pub fn ucnackifg(&mut self) -> _UCNACKIFGW {
+        _UCNACKIFGW { w: self }
+    }
+    #[doc = "Bit 6 - Byte counter interrupt flag"]
+    #[inline]
+    pub fn ucbcntifg(&mut self) -> _UCBCNTIFGW {
+        _UCBCNTIFGW { w: self }
+    }
+    #[doc = "Bit 7 - Clock low timeout interrupt flag"]
+    #[inline]
+    pub fn uccltoifg(&mut self) -> _UCCLTOIFGW {
+        _UCCLTOIFGW { w: self }
+    }
+    #[doc = "Bit 8 - eUSCI_B receive interrupt flag 1"]
+    #[inline]
+    pub fn ucrxifg1(&mut self) -> _UCRXIFG1W {
+        _UCRXIFG1W { w: self }
+    }
+    #[doc = "Bit 9 - eUSCI_B transmit interrupt flag 1"]
+    #[inline]
+    pub fn uctxifg1(&mut self) -> _UCTXIFG1W {
+        _UCTXIFG1W { w: self }
+    }
+    #[doc = "Bit 10 - eUSCI_B receive interrupt flag 2"]
+    #[inline]
+    pub fn ucrxifg2(&mut self) -> _UCRXIFG2W {
+        _UCRXIFG2W { w: self }
+    }
+    #[doc = "Bit 11 - eUSCI_B transmit interrupt flag 2"]
+    #[inline]
+    pub fn uctxifg2(&mut self) -> _UCTXIFG2W {
+        _UCTXIFG2W { w: self }
+    }
+    #[doc = "Bit 12 - eUSCI_B receive interrupt flag 3"]
+    #[inline]
+    pub fn ucrxifg3(&mut self) -> _UCRXIFG3W {
+        _UCRXIFG3W { w: self }
+    }
+    #[doc = "Bit 13 - eUSCI_B transmit interrupt flag 3"]
+    #[inline]
+    pub fn uctxifg3(&mut self) -> _UCTXIFG3W {
+        _UCTXIFG3W { w: self }
+    }
+    #[doc = "Bit 14 - Bit position 9 interrupt flag"]
+    #[inline]
+    pub fn ucbit9ifg(&mut self) -> _UCBIT9IFGW {
+        _UCBIT9IFGW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b3/ucbx_iv.rs b/example-source/msp432p401r/src/eusci_b3/ucbx_iv.rs
new file mode 100644
index 0000000..68af1a6
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b3/ucbx_iv.rs
@@ -0,0 +1,196 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::UCBXIV {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `UCIV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCIVR {
+    #[doc = "No interrupt pending"]
+    UCIV_0,
+    #[doc = "Interrupt Source: Arbitration lost; Interrupt Flag: UCALIFG; Interrupt Priority: Highest"]
+    UCIV_2,
+    #[doc = "Interrupt Source: Not acknowledgment; Interrupt Flag: UCNACKIFG"]
+    UCIV_4,
+    #[doc = "Interrupt Source: Start condition received; Interrupt Flag: UCSTTIFG"]
+    UCIV_6,
+    #[doc = "Interrupt Source: Stop condition received; Interrupt Flag: UCSTPIFG"]
+    UCIV_8,
+    #[doc = "Interrupt Source: Slave 3 Data received; Interrupt Flag: UCRXIFG3"]
+    UCIV_10,
+    #[doc = "Interrupt Source: Slave 3 Transmit buffer empty; Interrupt Flag: UCTXIFG3"]
+    UCIV_12,
+    #[doc = "Interrupt Source: Slave 2 Data received; Interrupt Flag: UCRXIFG2"]
+    UCIV_14,
+    #[doc = "Interrupt Source: Slave 2 Transmit buffer empty; Interrupt Flag: UCTXIFG2"]
+    UCIV_16,
+    #[doc = "Interrupt Source: Slave 1 Data received; Interrupt Flag: UCRXIFG1"]
+    UCIV_18,
+    #[doc = "Interrupt Source: Slave 1 Transmit buffer empty; Interrupt Flag: UCTXIFG1"]
+    UCIV_20,
+    #[doc = "Interrupt Source: Data received; Interrupt Flag: UCRXIFG0"]
+    UCIV_22,
+    #[doc = "Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG0"]
+    UCIV_24,
+    #[doc = "Interrupt Source: Byte counter zero; Interrupt Flag: UCBCNTIFG"]
+    UCIV_26,
+    #[doc = "Interrupt Source: Clock low timeout; Interrupt Flag: UCCLTOIFG"]
+    UCIV_28,
+    #[doc = "Interrupt Source: Nineth bit position; Interrupt Flag: UCBIT9IFG; Priority: Lowest"]
+    UCIV_30,
+    #[doc = r" Reserved"]
+    _Reserved(u16),
+}
+impl UCIVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        match *self {
+            UCIVR::UCIV_0 => 0,
+            UCIVR::UCIV_2 => 2,
+            UCIVR::UCIV_4 => 4,
+            UCIVR::UCIV_6 => 6,
+            UCIVR::UCIV_8 => 8,
+            UCIVR::UCIV_10 => 10,
+            UCIVR::UCIV_12 => 12,
+            UCIVR::UCIV_14 => 14,
+            UCIVR::UCIV_16 => 16,
+            UCIVR::UCIV_18 => 18,
+            UCIVR::UCIV_20 => 20,
+            UCIVR::UCIV_22 => 22,
+            UCIVR::UCIV_24 => 24,
+            UCIVR::UCIV_26 => 26,
+            UCIVR::UCIV_28 => 28,
+            UCIVR::UCIV_30 => 30,
+            UCIVR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u16) -> UCIVR {
+        match value {
+            0 => UCIVR::UCIV_0,
+            2 => UCIVR::UCIV_2,
+            4 => UCIVR::UCIV_4,
+            6 => UCIVR::UCIV_6,
+            8 => UCIVR::UCIV_8,
+            10 => UCIVR::UCIV_10,
+            12 => UCIVR::UCIV_12,
+            14 => UCIVR::UCIV_14,
+            16 => UCIVR::UCIV_16,
+            18 => UCIVR::UCIV_18,
+            20 => UCIVR::UCIV_20,
+            22 => UCIVR::UCIV_22,
+            24 => UCIVR::UCIV_24,
+            26 => UCIVR::UCIV_26,
+            28 => UCIVR::UCIV_28,
+            30 => UCIVR::UCIV_30,
+            i => UCIVR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCIV_0`"]
+    #[inline]
+    pub fn is_uciv_0(&self) -> bool {
+        *self == UCIVR::UCIV_0
+    }
+    #[doc = "Checks if the value of the field is `UCIV_2`"]
+    #[inline]
+    pub fn is_uciv_2(&self) -> bool {
+        *self == UCIVR::UCIV_2
+    }
+    #[doc = "Checks if the value of the field is `UCIV_4`"]
+    #[inline]
+    pub fn is_uciv_4(&self) -> bool {
+        *self == UCIVR::UCIV_4
+    }
+    #[doc = "Checks if the value of the field is `UCIV_6`"]
+    #[inline]
+    pub fn is_uciv_6(&self) -> bool {
+        *self == UCIVR::UCIV_6
+    }
+    #[doc = "Checks if the value of the field is `UCIV_8`"]
+    #[inline]
+    pub fn is_uciv_8(&self) -> bool {
+        *self == UCIVR::UCIV_8
+    }
+    #[doc = "Checks if the value of the field is `UCIV_10`"]
+    #[inline]
+    pub fn is_uciv_10(&self) -> bool {
+        *self == UCIVR::UCIV_10
+    }
+    #[doc = "Checks if the value of the field is `UCIV_12`"]
+    #[inline]
+    pub fn is_uciv_12(&self) -> bool {
+        *self == UCIVR::UCIV_12
+    }
+    #[doc = "Checks if the value of the field is `UCIV_14`"]
+    #[inline]
+    pub fn is_uciv_14(&self) -> bool {
+        *self == UCIVR::UCIV_14
+    }
+    #[doc = "Checks if the value of the field is `UCIV_16`"]
+    #[inline]
+    pub fn is_uciv_16(&self) -> bool {
+        *self == UCIVR::UCIV_16
+    }
+    #[doc = "Checks if the value of the field is `UCIV_18`"]
+    #[inline]
+    pub fn is_uciv_18(&self) -> bool {
+        *self == UCIVR::UCIV_18
+    }
+    #[doc = "Checks if the value of the field is `UCIV_20`"]
+    #[inline]
+    pub fn is_uciv_20(&self) -> bool {
+        *self == UCIVR::UCIV_20
+    }
+    #[doc = "Checks if the value of the field is `UCIV_22`"]
+    #[inline]
+    pub fn is_uciv_22(&self) -> bool {
+        *self == UCIVR::UCIV_22
+    }
+    #[doc = "Checks if the value of the field is `UCIV_24`"]
+    #[inline]
+    pub fn is_uciv_24(&self) -> bool {
+        *self == UCIVR::UCIV_24
+    }
+    #[doc = "Checks if the value of the field is `UCIV_26`"]
+    #[inline]
+    pub fn is_uciv_26(&self) -> bool {
+        *self == UCIVR::UCIV_26
+    }
+    #[doc = "Checks if the value of the field is `UCIV_28`"]
+    #[inline]
+    pub fn is_uciv_28(&self) -> bool {
+        *self == UCIVR::UCIV_28
+    }
+    #[doc = "Checks if the value of the field is `UCIV_30`"]
+    #[inline]
+    pub fn is_uciv_30(&self) -> bool {
+        *self == UCIVR::UCIV_30
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - eUSCI_B interrupt vector value"]
+    #[inline]
+    pub fn uciv(&self) -> UCIVR {
+        UCIVR::_from({
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b3/ucbx_rxbuf.rs b/example-source/msp432p401r/src/eusci_b3/ucbx_rxbuf.rs
new file mode 100644
index 0000000..74a7dd6
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b3/ucbx_rxbuf.rs
@@ -0,0 +1,41 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::UCBXRXBUF {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCRXBUFR {
+    bits: u8,
+}
+impl UCRXBUFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Receive data buffer"]
+    #[inline]
+    pub fn ucrxbuf(&self) -> UCRXBUFR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCRXBUFR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b3/ucbx_statw.rs b/example-source/msp432p401r/src/eusci_b3/ucbx_statw.rs
new file mode 100644
index 0000000..9f71700
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b3/ucbx_statw.rs
@@ -0,0 +1,253 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXSTATW {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `UCBBUSY`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCBBUSYR {
+    #[doc = "Bus inactive"]
+    UCBBUSY_0,
+    #[doc = "Bus busy"]
+    UCBBUSY_1,
+}
+impl UCBBUSYR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCBBUSYR::UCBBUSY_0 => false,
+            UCBBUSYR::UCBBUSY_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCBBUSYR {
+        match value {
+            false => UCBBUSYR::UCBBUSY_0,
+            true => UCBBUSYR::UCBBUSY_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCBBUSY_0`"]
+    #[inline]
+    pub fn is_ucbbusy_0(&self) -> bool {
+        *self == UCBBUSYR::UCBBUSY_0
+    }
+    #[doc = "Checks if the value of the field is `UCBBUSY_1`"]
+    #[inline]
+    pub fn is_ucbbusy_1(&self) -> bool {
+        *self == UCBBUSYR::UCBBUSY_1
+    }
+}
+#[doc = "Possible values of the field `UCGC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCGCR {
+    #[doc = "No general call address received"]
+    UCGC_0,
+    #[doc = "General call address received"]
+    UCGC_1,
+}
+impl UCGCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCGCR::UCGC_0 => false,
+            UCGCR::UCGC_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCGCR {
+        match value {
+            false => UCGCR::UCGC_0,
+            true => UCGCR::UCGC_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCGC_0`"]
+    #[inline]
+    pub fn is_ucgc_0(&self) -> bool {
+        *self == UCGCR::UCGC_0
+    }
+    #[doc = "Checks if the value of the field is `UCGC_1`"]
+    #[inline]
+    pub fn is_ucgc_1(&self) -> bool {
+        *self == UCGCR::UCGC_1
+    }
+}
+#[doc = "Possible values of the field `UCSCLLOW`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UCSCLLOWR {
+    #[doc = "SCL is not held low"]
+    UCSCLLOW_0,
+    #[doc = "SCL is held low"]
+    UCSCLLOW_1,
+}
+impl UCSCLLOWR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UCSCLLOWR::UCSCLLOW_0 => false,
+            UCSCLLOWR::UCSCLLOW_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UCSCLLOWR {
+        match value {
+            false => UCSCLLOWR::UCSCLLOW_0,
+            true => UCSCLLOWR::UCSCLLOW_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UCSCLLOW_0`"]
+    #[inline]
+    pub fn is_ucscllow_0(&self) -> bool {
+        *self == UCSCLLOWR::UCSCLLOW_0
+    }
+    #[doc = "Checks if the value of the field is `UCSCLLOW_1`"]
+    #[inline]
+    pub fn is_ucscllow_1(&self) -> bool {
+        *self == UCSCLLOWR::UCSCLLOW_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCBCNTR {
+    bits: u8,
+}
+impl UCBCNTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 4 - Bus busy"]
+    #[inline]
+    pub fn ucbbusy(&self) -> UCBBUSYR {
+        UCBBUSYR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - General call address received"]
+    #[inline]
+    pub fn ucgc(&self) -> UCGCR {
+        UCGCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 6 - SCL low"]
+    #[inline]
+    pub fn ucscllow(&self) -> UCSCLLOWR {
+        UCSCLLOWR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 8:15 - Hardware byte counter value"]
+    #[inline]
+    pub fn ucbcnt(&self) -> UCBCNTR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCBCNTR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b3/ucbx_tbcnt.rs b/example-source/msp432p401r/src/eusci_b3/ucbx_tbcnt.rs
new file mode 100644
index 0000000..52ef844
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b3/ucbx_tbcnt.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXTBCNT {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCTBCNTR {
+    bits: u8,
+}
+impl UCTBCNTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTBCNTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTBCNTW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Byte counter threshold value"]
+    #[inline]
+    pub fn uctbcnt(&self) -> UCTBCNTR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCTBCNTR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Byte counter threshold value"]
+    #[inline]
+    pub fn uctbcnt(&mut self) -> _UCTBCNTW {
+        _UCTBCNTW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/eusci_b3/ucbx_txbuf.rs b/example-source/msp432p401r/src/eusci_b3/ucbx_txbuf.rs
new file mode 100644
index 0000000..2b787f2
--- /dev/null
+++ b/example-source/msp432p401r/src/eusci_b3/ucbx_txbuf.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::UCBXTXBUF {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UCTXBUFR {
+    bits: u8,
+}
+impl UCTXBUFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UCTXBUFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UCTXBUFW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Transmit data buffer"]
+    #[inline]
+    pub fn uctxbuf(&self) -> UCTXBUFR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        UCTXBUFR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Transmit data buffer"]
+    #[inline]
+    pub fn uctxbuf(&mut self) -> _UCTXBUFW {
+        _UCTXBUFW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl.rs b/example-source/msp432p401r/src/flctl.rs
new file mode 100644
index 0000000..5913573
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl.rs
@@ -0,0 +1,413 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - Power Status Register"]
+    pub flctl_power_stat: FLCTL_POWER_STAT,
+    _reserved0: [u8; 12usize],
+    #[doc = "0x10 - Bank0 Read Control Register"]
+    pub flctl_bank0_rdctl: FLCTL_BANK0_RDCTL,
+    #[doc = "0x14 - Bank1 Read Control Register"]
+    pub flctl_bank1_rdctl: FLCTL_BANK1_RDCTL,
+    _reserved1: [u8; 8usize],
+    #[doc = "0x20 - Read Burst/Compare Control and Status Register"]
+    pub flctl_rdbrst_ctlstat: FLCTL_RDBRST_CTLSTAT,
+    #[doc = "0x24 - Read Burst/Compare Start Address Register"]
+    pub flctl_rdbrst_startaddr: FLCTL_RDBRST_STARTADDR,
+    #[doc = "0x28 - Read Burst/Compare Length Register"]
+    pub flctl_rdbrst_len: FLCTL_RDBRST_LEN,
+    _reserved2: [u8; 16usize],
+    #[doc = "0x3c - Read Burst/Compare Fail Address Register"]
+    pub flctl_rdbrst_failaddr: FLCTL_RDBRST_FAILADDR,
+    #[doc = "0x40 - Read Burst/Compare Fail Count Register"]
+    pub flctl_rdbrst_failcnt: FLCTL_RDBRST_FAILCNT,
+    _reserved3: [u8; 12usize],
+    #[doc = "0x50 - Program Control and Status Register"]
+    pub flctl_prg_ctlstat: FLCTL_PRG_CTLSTAT,
+    #[doc = "0x54 - Program Burst Control and Status Register"]
+    pub flctl_prgbrst_ctlstat: FLCTL_PRGBRST_CTLSTAT,
+    #[doc = "0x58 - Program Burst Start Address Register"]
+    pub flctl_prgbrst_startaddr: FLCTL_PRGBRST_STARTADDR,
+    _reserved4: [u8; 4usize],
+    #[doc = "0x60 - Program Burst Data0 Register0"]
+    pub flctl_prgbrst_data0_0: FLCTL_PRGBRST_DATA0_0,
+    #[doc = "0x64 - Program Burst Data0 Register1"]
+    pub flctl_prgbrst_data0_1: FLCTL_PRGBRST_DATA0_1,
+    #[doc = "0x68 - Program Burst Data0 Register2"]
+    pub flctl_prgbrst_data0_2: FLCTL_PRGBRST_DATA0_2,
+    #[doc = "0x6c - Program Burst Data0 Register3"]
+    pub flctl_prgbrst_data0_3: FLCTL_PRGBRST_DATA0_3,
+    #[doc = "0x70 - Program Burst Data1 Register0"]
+    pub flctl_prgbrst_data1_0: FLCTL_PRGBRST_DATA1_0,
+    #[doc = "0x74 - Program Burst Data1 Register1"]
+    pub flctl_prgbrst_data1_1: FLCTL_PRGBRST_DATA1_1,
+    #[doc = "0x78 - Program Burst Data1 Register2"]
+    pub flctl_prgbrst_data1_2: FLCTL_PRGBRST_DATA1_2,
+    #[doc = "0x7c - Program Burst Data1 Register3"]
+    pub flctl_prgbrst_data1_3: FLCTL_PRGBRST_DATA1_3,
+    #[doc = "0x80 - Program Burst Data2 Register0"]
+    pub flctl_prgbrst_data2_0: FLCTL_PRGBRST_DATA2_0,
+    #[doc = "0x84 - Program Burst Data2 Register1"]
+    pub flctl_prgbrst_data2_1: FLCTL_PRGBRST_DATA2_1,
+    #[doc = "0x88 - Program Burst Data2 Register2"]
+    pub flctl_prgbrst_data2_2: FLCTL_PRGBRST_DATA2_2,
+    #[doc = "0x8c - Program Burst Data2 Register3"]
+    pub flctl_prgbrst_data2_3: FLCTL_PRGBRST_DATA2_3,
+    #[doc = "0x90 - Program Burst Data3 Register0"]
+    pub flctl_prgbrst_data3_0: FLCTL_PRGBRST_DATA3_0,
+    #[doc = "0x94 - Program Burst Data3 Register1"]
+    pub flctl_prgbrst_data3_1: FLCTL_PRGBRST_DATA3_1,
+    #[doc = "0x98 - Program Burst Data3 Register2"]
+    pub flctl_prgbrst_data3_2: FLCTL_PRGBRST_DATA3_2,
+    #[doc = "0x9c - Program Burst Data3 Register3"]
+    pub flctl_prgbrst_data3_3: FLCTL_PRGBRST_DATA3_3,
+    #[doc = "0xa0 - Erase Control and Status Register"]
+    pub flctl_erase_ctlstat: FLCTL_ERASE_CTLSTAT,
+    #[doc = "0xa4 - Erase Sector Address Register"]
+    pub flctl_erase_sectaddr: FLCTL_ERASE_SECTADDR,
+    _reserved5: [u8; 8usize],
+    #[doc = "0xb0 - Information Memory Bank0 Write/Erase Protection Register"]
+    pub flctl_bank0_info_weprot: FLCTL_BANK0_INFO_WEPROT,
+    #[doc = "0xb4 - Main Memory Bank0 Write/Erase Protection Register"]
+    pub flctl_bank0_main_weprot: FLCTL_BANK0_MAIN_WEPROT,
+    _reserved6: [u8; 8usize],
+    #[doc = "0xc0 - Information Memory Bank1 Write/Erase Protection Register"]
+    pub flctl_bank1_info_weprot: FLCTL_BANK1_INFO_WEPROT,
+    #[doc = "0xc4 - Main Memory Bank1 Write/Erase Protection Register"]
+    pub flctl_bank1_main_weprot: FLCTL_BANK1_MAIN_WEPROT,
+    _reserved7: [u8; 8usize],
+    #[doc = "0xd0 - Benchmark Control and Status Register"]
+    pub flctl_bmrk_ctlstat: FLCTL_BMRK_CTLSTAT,
+    #[doc = "0xd4 - Benchmark Instruction Fetch Count Register"]
+    pub flctl_bmrk_ifetch: FLCTL_BMRK_IFETCH,
+    #[doc = "0xd8 - Benchmark Data Read Count Register"]
+    pub flctl_bmrk_dread: FLCTL_BMRK_DREAD,
+    #[doc = "0xdc - Benchmark Count Compare Register"]
+    pub flctl_bmrk_cmp: FLCTL_BMRK_CMP,
+    _reserved8: [u8; 16usize],
+    #[doc = "0xf0 - Interrupt Flag Register"]
+    pub flctl_ifg: FLCTL_IFG,
+    #[doc = "0xf4 - Interrupt Enable Register"]
+    pub flctl_ie: FLCTL_IE,
+    #[doc = "0xf8 - Clear Interrupt Flag Register"]
+    pub flctl_clrifg: FLCTL_CLRIFG,
+    #[doc = "0xfc - Set Interrupt Flag Register"]
+    pub flctl_setifg: FLCTL_SETIFG,
+    #[doc = "0x100 - Read Timing Control Register"]
+    pub flctl_read_timctl: FLCTL_READ_TIMCTL,
+    #[doc = "0x104 - Read Margin Timing Control Register"]
+    pub flctl_readmargin_timctl: FLCTL_READMARGIN_TIMCTL,
+    #[doc = "0x108 - Program Verify Timing Control Register"]
+    pub flctl_prgver_timctl: FLCTL_PRGVER_TIMCTL,
+    #[doc = "0x10c - Erase Verify Timing Control Register"]
+    pub flctl_ersver_timctl: FLCTL_ERSVER_TIMCTL,
+    #[doc = "0x110 - Leakage Verify Timing Control Register"]
+    pub flctl_lkgver_timctl: FLCTL_LKGVER_TIMCTL,
+    #[doc = "0x114 - Program Timing Control Register"]
+    pub flctl_program_timctl: FLCTL_PROGRAM_TIMCTL,
+    #[doc = "0x118 - Erase Timing Control Register"]
+    pub flctl_erase_timctl: FLCTL_ERASE_TIMCTL,
+    #[doc = "0x11c - Mass Erase Timing Control Register"]
+    pub flctl_masserase_timctl: FLCTL_MASSERASE_TIMCTL,
+    #[doc = "0x120 - Burst Program Timing Control Register"]
+    pub flctl_burstprg_timctl: FLCTL_BURSTPRG_TIMCTL,
+}
+#[doc = "Power Status Register"]
+pub struct FLCTL_POWER_STAT {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Power Status Register"]
+pub mod flctl_power_stat;
+#[doc = "Bank0 Read Control Register"]
+pub struct FLCTL_BANK0_RDCTL {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Bank0 Read Control Register"]
+pub mod flctl_bank0_rdctl;
+#[doc = "Bank1 Read Control Register"]
+pub struct FLCTL_BANK1_RDCTL {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Bank1 Read Control Register"]
+pub mod flctl_bank1_rdctl;
+#[doc = "Read Burst/Compare Control and Status Register"]
+pub struct FLCTL_RDBRST_CTLSTAT {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Read Burst/Compare Control and Status Register"]
+pub mod flctl_rdbrst_ctlstat;
+#[doc = "Read Burst/Compare Start Address Register"]
+pub struct FLCTL_RDBRST_STARTADDR {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Read Burst/Compare Start Address Register"]
+pub mod flctl_rdbrst_startaddr;
+#[doc = "Read Burst/Compare Length Register"]
+pub struct FLCTL_RDBRST_LEN {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Read Burst/Compare Length Register"]
+pub mod flctl_rdbrst_len;
+#[doc = "Read Burst/Compare Fail Address Register"]
+pub struct FLCTL_RDBRST_FAILADDR {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Read Burst/Compare Fail Address Register"]
+pub mod flctl_rdbrst_failaddr;
+#[doc = "Read Burst/Compare Fail Count Register"]
+pub struct FLCTL_RDBRST_FAILCNT {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Read Burst/Compare Fail Count Register"]
+pub mod flctl_rdbrst_failcnt;
+#[doc = "Program Control and Status Register"]
+pub struct FLCTL_PRG_CTLSTAT {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Program Control and Status Register"]
+pub mod flctl_prg_ctlstat;
+#[doc = "Program Burst Control and Status Register"]
+pub struct FLCTL_PRGBRST_CTLSTAT {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Program Burst Control and Status Register"]
+pub mod flctl_prgbrst_ctlstat;
+#[doc = "Program Burst Start Address Register"]
+pub struct FLCTL_PRGBRST_STARTADDR {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Program Burst Start Address Register"]
+pub mod flctl_prgbrst_startaddr;
+#[doc = "Program Burst Data0 Register0"]
+pub struct FLCTL_PRGBRST_DATA0_0 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Program Burst Data0 Register0"]
+pub mod flctl_prgbrst_data0_0;
+#[doc = "Program Burst Data0 Register1"]
+pub struct FLCTL_PRGBRST_DATA0_1 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Program Burst Data0 Register1"]
+pub mod flctl_prgbrst_data0_1;
+#[doc = "Program Burst Data0 Register2"]
+pub struct FLCTL_PRGBRST_DATA0_2 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Program Burst Data0 Register2"]
+pub mod flctl_prgbrst_data0_2;
+#[doc = "Program Burst Data0 Register3"]
+pub struct FLCTL_PRGBRST_DATA0_3 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Program Burst Data0 Register3"]
+pub mod flctl_prgbrst_data0_3;
+#[doc = "Program Burst Data1 Register0"]
+pub struct FLCTL_PRGBRST_DATA1_0 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Program Burst Data1 Register0"]
+pub mod flctl_prgbrst_data1_0;
+#[doc = "Program Burst Data1 Register1"]
+pub struct FLCTL_PRGBRST_DATA1_1 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Program Burst Data1 Register1"]
+pub mod flctl_prgbrst_data1_1;
+#[doc = "Program Burst Data1 Register2"]
+pub struct FLCTL_PRGBRST_DATA1_2 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Program Burst Data1 Register2"]
+pub mod flctl_prgbrst_data1_2;
+#[doc = "Program Burst Data1 Register3"]
+pub struct FLCTL_PRGBRST_DATA1_3 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Program Burst Data1 Register3"]
+pub mod flctl_prgbrst_data1_3;
+#[doc = "Program Burst Data2 Register0"]
+pub struct FLCTL_PRGBRST_DATA2_0 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Program Burst Data2 Register0"]
+pub mod flctl_prgbrst_data2_0;
+#[doc = "Program Burst Data2 Register1"]
+pub struct FLCTL_PRGBRST_DATA2_1 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Program Burst Data2 Register1"]
+pub mod flctl_prgbrst_data2_1;
+#[doc = "Program Burst Data2 Register2"]
+pub struct FLCTL_PRGBRST_DATA2_2 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Program Burst Data2 Register2"]
+pub mod flctl_prgbrst_data2_2;
+#[doc = "Program Burst Data2 Register3"]
+pub struct FLCTL_PRGBRST_DATA2_3 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Program Burst Data2 Register3"]
+pub mod flctl_prgbrst_data2_3;
+#[doc = "Program Burst Data3 Register0"]
+pub struct FLCTL_PRGBRST_DATA3_0 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Program Burst Data3 Register0"]
+pub mod flctl_prgbrst_data3_0;
+#[doc = "Program Burst Data3 Register1"]
+pub struct FLCTL_PRGBRST_DATA3_1 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Program Burst Data3 Register1"]
+pub mod flctl_prgbrst_data3_1;
+#[doc = "Program Burst Data3 Register2"]
+pub struct FLCTL_PRGBRST_DATA3_2 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Program Burst Data3 Register2"]
+pub mod flctl_prgbrst_data3_2;
+#[doc = "Program Burst Data3 Register3"]
+pub struct FLCTL_PRGBRST_DATA3_3 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Program Burst Data3 Register3"]
+pub mod flctl_prgbrst_data3_3;
+#[doc = "Erase Control and Status Register"]
+pub struct FLCTL_ERASE_CTLSTAT {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Erase Control and Status Register"]
+pub mod flctl_erase_ctlstat;
+#[doc = "Erase Sector Address Register"]
+pub struct FLCTL_ERASE_SECTADDR {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Erase Sector Address Register"]
+pub mod flctl_erase_sectaddr;
+#[doc = "Information Memory Bank0 Write/Erase Protection Register"]
+pub struct FLCTL_BANK0_INFO_WEPROT {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Information Memory Bank0 Write/Erase Protection Register"]
+pub mod flctl_bank0_info_weprot;
+#[doc = "Main Memory Bank0 Write/Erase Protection Register"]
+pub struct FLCTL_BANK0_MAIN_WEPROT {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Main Memory Bank0 Write/Erase Protection Register"]
+pub mod flctl_bank0_main_weprot;
+#[doc = "Information Memory Bank1 Write/Erase Protection Register"]
+pub struct FLCTL_BANK1_INFO_WEPROT {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Information Memory Bank1 Write/Erase Protection Register"]
+pub mod flctl_bank1_info_weprot;
+#[doc = "Main Memory Bank1 Write/Erase Protection Register"]
+pub struct FLCTL_BANK1_MAIN_WEPROT {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Main Memory Bank1 Write/Erase Protection Register"]
+pub mod flctl_bank1_main_weprot;
+#[doc = "Benchmark Control and Status Register"]
+pub struct FLCTL_BMRK_CTLSTAT {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Benchmark Control and Status Register"]
+pub mod flctl_bmrk_ctlstat;
+#[doc = "Benchmark Instruction Fetch Count Register"]
+pub struct FLCTL_BMRK_IFETCH {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Benchmark Instruction Fetch Count Register"]
+pub mod flctl_bmrk_ifetch;
+#[doc = "Benchmark Data Read Count Register"]
+pub struct FLCTL_BMRK_DREAD {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Benchmark Data Read Count Register"]
+pub mod flctl_bmrk_dread;
+#[doc = "Benchmark Count Compare Register"]
+pub struct FLCTL_BMRK_CMP {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Benchmark Count Compare Register"]
+pub mod flctl_bmrk_cmp;
+#[doc = "Interrupt Flag Register"]
+pub struct FLCTL_IFG {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Interrupt Flag Register"]
+pub mod flctl_ifg;
+#[doc = "Interrupt Enable Register"]
+pub struct FLCTL_IE {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Interrupt Enable Register"]
+pub mod flctl_ie;
+#[doc = "Clear Interrupt Flag Register"]
+pub struct FLCTL_CLRIFG {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Clear Interrupt Flag Register"]
+pub mod flctl_clrifg;
+#[doc = "Set Interrupt Flag Register"]
+pub struct FLCTL_SETIFG {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Set Interrupt Flag Register"]
+pub mod flctl_setifg;
+#[doc = "Read Timing Control Register"]
+pub struct FLCTL_READ_TIMCTL {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Read Timing Control Register"]
+pub mod flctl_read_timctl;
+#[doc = "Read Margin Timing Control Register"]
+pub struct FLCTL_READMARGIN_TIMCTL {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Read Margin Timing Control Register"]
+pub mod flctl_readmargin_timctl;
+#[doc = "Program Verify Timing Control Register"]
+pub struct FLCTL_PRGVER_TIMCTL {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Program Verify Timing Control Register"]
+pub mod flctl_prgver_timctl;
+#[doc = "Erase Verify Timing Control Register"]
+pub struct FLCTL_ERSVER_TIMCTL {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Erase Verify Timing Control Register"]
+pub mod flctl_ersver_timctl;
+#[doc = "Leakage Verify Timing Control Register"]
+pub struct FLCTL_LKGVER_TIMCTL {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Leakage Verify Timing Control Register"]
+pub mod flctl_lkgver_timctl;
+#[doc = "Program Timing Control Register"]
+pub struct FLCTL_PROGRAM_TIMCTL {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Program Timing Control Register"]
+pub mod flctl_program_timctl;
+#[doc = "Erase Timing Control Register"]
+pub struct FLCTL_ERASE_TIMCTL {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Erase Timing Control Register"]
+pub mod flctl_erase_timctl;
+#[doc = "Mass Erase Timing Control Register"]
+pub struct FLCTL_MASSERASE_TIMCTL {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Mass Erase Timing Control Register"]
+pub mod flctl_masserase_timctl;
+#[doc = "Burst Program Timing Control Register"]
+pub struct FLCTL_BURSTPRG_TIMCTL {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Burst Program Timing Control Register"]
+pub mod flctl_burstprg_timctl;
diff --git a/example-source/msp432p401r/src/flctl/flctl_bank0_info_weprot.rs b/example-source/msp432p401r/src/flctl/flctl_bank0_info_weprot.rs
new file mode 100644
index 0000000..ba86c3f
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_bank0_info_weprot.rs
@@ -0,0 +1,182 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_BANK0_INFO_WEPROT {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT0R {
+    bits: bool,
+}
+impl PROT0R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT1R {
+    bits: bool,
+}
+impl PROT1R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT0W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT1W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Protects Sector 0 from program or erase"]
+    #[inline]
+    pub fn prot0(&self) -> PROT0R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT0R { bits }
+    }
+    #[doc = "Bit 1 - Protects Sector 1 from program or erase"]
+    #[inline]
+    pub fn prot1(&self) -> PROT1R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT1R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 3 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Protects Sector 0 from program or erase"]
+    #[inline]
+    pub fn prot0(&mut self) -> _PROT0W {
+        _PROT0W { w: self }
+    }
+    #[doc = "Bit 1 - Protects Sector 1 from program or erase"]
+    #[inline]
+    pub fn prot1(&mut self) -> _PROT1W {
+        _PROT1W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_bank0_main_weprot.rs b/example-source/msp432p401r/src/flctl/flctl_bank0_main_weprot.rs
new file mode 100644
index 0000000..fc752e2
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_bank0_main_weprot.rs
@@ -0,0 +1,1952 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_BANK0_MAIN_WEPROT {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT0R {
+    bits: bool,
+}
+impl PROT0R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT1R {
+    bits: bool,
+}
+impl PROT1R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT2R {
+    bits: bool,
+}
+impl PROT2R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT3R {
+    bits: bool,
+}
+impl PROT3R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT4R {
+    bits: bool,
+}
+impl PROT4R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT5R {
+    bits: bool,
+}
+impl PROT5R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT6R {
+    bits: bool,
+}
+impl PROT6R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT7R {
+    bits: bool,
+}
+impl PROT7R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT8R {
+    bits: bool,
+}
+impl PROT8R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT9R {
+    bits: bool,
+}
+impl PROT9R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT10R {
+    bits: bool,
+}
+impl PROT10R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT11R {
+    bits: bool,
+}
+impl PROT11R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT12R {
+    bits: bool,
+}
+impl PROT12R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT13R {
+    bits: bool,
+}
+impl PROT13R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT14R {
+    bits: bool,
+}
+impl PROT14R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT15R {
+    bits: bool,
+}
+impl PROT15R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT16R {
+    bits: bool,
+}
+impl PROT16R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT17R {
+    bits: bool,
+}
+impl PROT17R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT18R {
+    bits: bool,
+}
+impl PROT18R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT19R {
+    bits: bool,
+}
+impl PROT19R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT20R {
+    bits: bool,
+}
+impl PROT20R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT21R {
+    bits: bool,
+}
+impl PROT21R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT22R {
+    bits: bool,
+}
+impl PROT22R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT23R {
+    bits: bool,
+}
+impl PROT23R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT24R {
+    bits: bool,
+}
+impl PROT24R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT25R {
+    bits: bool,
+}
+impl PROT25R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT26R {
+    bits: bool,
+}
+impl PROT26R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT27R {
+    bits: bool,
+}
+impl PROT27R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT28R {
+    bits: bool,
+}
+impl PROT28R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT29R {
+    bits: bool,
+}
+impl PROT29R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT30R {
+    bits: bool,
+}
+impl PROT30R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT31R {
+    bits: bool,
+}
+impl PROT31R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT0W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT1W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT2W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT3W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT4W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT4W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT5W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT5W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT6W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT6W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT7W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT7W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT8W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT8W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT9W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT9W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT10W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT10W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT11W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT11W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT12W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT12W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT13W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT13W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT14W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT14W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT15W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT15W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT16W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT16W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 16;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT17W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT17W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 17;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT18W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT18W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 18;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT19W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT19W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 19;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT20W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT20W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 20;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT21W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT21W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 21;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT22W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT22W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 22;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT23W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT23W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 23;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT24W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT24W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 24;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT25W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT25W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 25;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT26W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT26W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 26;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT27W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT27W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 27;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT28W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT28W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 28;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT29W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT29W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 29;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT30W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT30W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 30;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT31W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT31W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 31;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Protects Sector 0 from program or erase"]
+    #[inline]
+    pub fn prot0(&self) -> PROT0R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT0R { bits }
+    }
+    #[doc = "Bit 1 - Protects Sector 1 from program or erase"]
+    #[inline]
+    pub fn prot1(&self) -> PROT1R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT1R { bits }
+    }
+    #[doc = "Bit 2 - Protects Sector 2 from program or erase"]
+    #[inline]
+    pub fn prot2(&self) -> PROT2R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT2R { bits }
+    }
+    #[doc = "Bit 3 - Protects Sector 3 from program or erase"]
+    #[inline]
+    pub fn prot3(&self) -> PROT3R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT3R { bits }
+    }
+    #[doc = "Bit 4 - Protects Sector 4 from program or erase"]
+    #[inline]
+    pub fn prot4(&self) -> PROT4R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT4R { bits }
+    }
+    #[doc = "Bit 5 - Protects Sector 5 from program or erase"]
+    #[inline]
+    pub fn prot5(&self) -> PROT5R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT5R { bits }
+    }
+    #[doc = "Bit 6 - Protects Sector 6 from program or erase"]
+    #[inline]
+    pub fn prot6(&self) -> PROT6R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT6R { bits }
+    }
+    #[doc = "Bit 7 - Protects Sector 7 from program or erase"]
+    #[inline]
+    pub fn prot7(&self) -> PROT7R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT7R { bits }
+    }
+    #[doc = "Bit 8 - Protects Sector 8 from program or erase"]
+    #[inline]
+    pub fn prot8(&self) -> PROT8R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT8R { bits }
+    }
+    #[doc = "Bit 9 - Protects Sector 9 from program or erase"]
+    #[inline]
+    pub fn prot9(&self) -> PROT9R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT9R { bits }
+    }
+    #[doc = "Bit 10 - Protects Sector 10 from program or erase"]
+    #[inline]
+    pub fn prot10(&self) -> PROT10R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT10R { bits }
+    }
+    #[doc = "Bit 11 - Protects Sector 11 from program or erase"]
+    #[inline]
+    pub fn prot11(&self) -> PROT11R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT11R { bits }
+    }
+    #[doc = "Bit 12 - Protects Sector 12 from program or erase"]
+    #[inline]
+    pub fn prot12(&self) -> PROT12R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT12R { bits }
+    }
+    #[doc = "Bit 13 - Protects Sector 13 from program or erase"]
+    #[inline]
+    pub fn prot13(&self) -> PROT13R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT13R { bits }
+    }
+    #[doc = "Bit 14 - Protects Sector 14 from program or erase"]
+    #[inline]
+    pub fn prot14(&self) -> PROT14R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT14R { bits }
+    }
+    #[doc = "Bit 15 - Protects Sector 15 from program or erase"]
+    #[inline]
+    pub fn prot15(&self) -> PROT15R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT15R { bits }
+    }
+    #[doc = "Bit 16 - Protects Sector 16 from program or erase"]
+    #[inline]
+    pub fn prot16(&self) -> PROT16R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT16R { bits }
+    }
+    #[doc = "Bit 17 - Protects Sector 17 from program or erase"]
+    #[inline]
+    pub fn prot17(&self) -> PROT17R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 17;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT17R { bits }
+    }
+    #[doc = "Bit 18 - Protects Sector 18 from program or erase"]
+    #[inline]
+    pub fn prot18(&self) -> PROT18R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 18;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT18R { bits }
+    }
+    #[doc = "Bit 19 - Protects Sector 19 from program or erase"]
+    #[inline]
+    pub fn prot19(&self) -> PROT19R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 19;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT19R { bits }
+    }
+    #[doc = "Bit 20 - Protects Sector 20 from program or erase"]
+    #[inline]
+    pub fn prot20(&self) -> PROT20R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 20;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT20R { bits }
+    }
+    #[doc = "Bit 21 - Protects Sector 21 from program or erase"]
+    #[inline]
+    pub fn prot21(&self) -> PROT21R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 21;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT21R { bits }
+    }
+    #[doc = "Bit 22 - Protects Sector 22 from program or erase"]
+    #[inline]
+    pub fn prot22(&self) -> PROT22R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 22;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT22R { bits }
+    }
+    #[doc = "Bit 23 - Protects Sector 23 from program or erase"]
+    #[inline]
+    pub fn prot23(&self) -> PROT23R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 23;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT23R { bits }
+    }
+    #[doc = "Bit 24 - Protects Sector 24 from program or erase"]
+    #[inline]
+    pub fn prot24(&self) -> PROT24R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 24;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT24R { bits }
+    }
+    #[doc = "Bit 25 - Protects Sector 25 from program or erase"]
+    #[inline]
+    pub fn prot25(&self) -> PROT25R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 25;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT25R { bits }
+    }
+    #[doc = "Bit 26 - Protects Sector 26 from program or erase"]
+    #[inline]
+    pub fn prot26(&self) -> PROT26R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 26;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT26R { bits }
+    }
+    #[doc = "Bit 27 - Protects Sector 27 from program or erase"]
+    #[inline]
+    pub fn prot27(&self) -> PROT27R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 27;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT27R { bits }
+    }
+    #[doc = "Bit 28 - Protects Sector 28 from program or erase"]
+    #[inline]
+    pub fn prot28(&self) -> PROT28R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 28;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT28R { bits }
+    }
+    #[doc = "Bit 29 - Protects Sector 29 from program or erase"]
+    #[inline]
+    pub fn prot29(&self) -> PROT29R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 29;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT29R { bits }
+    }
+    #[doc = "Bit 30 - Protects Sector 30 from program or erase"]
+    #[inline]
+    pub fn prot30(&self) -> PROT30R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 30;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT30R { bits }
+    }
+    #[doc = "Bit 31 - Protects Sector 31 from program or erase"]
+    #[inline]
+    pub fn prot31(&self) -> PROT31R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 31;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT31R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 4294967295 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Protects Sector 0 from program or erase"]
+    #[inline]
+    pub fn prot0(&mut self) -> _PROT0W {
+        _PROT0W { w: self }
+    }
+    #[doc = "Bit 1 - Protects Sector 1 from program or erase"]
+    #[inline]
+    pub fn prot1(&mut self) -> _PROT1W {
+        _PROT1W { w: self }
+    }
+    #[doc = "Bit 2 - Protects Sector 2 from program or erase"]
+    #[inline]
+    pub fn prot2(&mut self) -> _PROT2W {
+        _PROT2W { w: self }
+    }
+    #[doc = "Bit 3 - Protects Sector 3 from program or erase"]
+    #[inline]
+    pub fn prot3(&mut self) -> _PROT3W {
+        _PROT3W { w: self }
+    }
+    #[doc = "Bit 4 - Protects Sector 4 from program or erase"]
+    #[inline]
+    pub fn prot4(&mut self) -> _PROT4W {
+        _PROT4W { w: self }
+    }
+    #[doc = "Bit 5 - Protects Sector 5 from program or erase"]
+    #[inline]
+    pub fn prot5(&mut self) -> _PROT5W {
+        _PROT5W { w: self }
+    }
+    #[doc = "Bit 6 - Protects Sector 6 from program or erase"]
+    #[inline]
+    pub fn prot6(&mut self) -> _PROT6W {
+        _PROT6W { w: self }
+    }
+    #[doc = "Bit 7 - Protects Sector 7 from program or erase"]
+    #[inline]
+    pub fn prot7(&mut self) -> _PROT7W {
+        _PROT7W { w: self }
+    }
+    #[doc = "Bit 8 - Protects Sector 8 from program or erase"]
+    #[inline]
+    pub fn prot8(&mut self) -> _PROT8W {
+        _PROT8W { w: self }
+    }
+    #[doc = "Bit 9 - Protects Sector 9 from program or erase"]
+    #[inline]
+    pub fn prot9(&mut self) -> _PROT9W {
+        _PROT9W { w: self }
+    }
+    #[doc = "Bit 10 - Protects Sector 10 from program or erase"]
+    #[inline]
+    pub fn prot10(&mut self) -> _PROT10W {
+        _PROT10W { w: self }
+    }
+    #[doc = "Bit 11 - Protects Sector 11 from program or erase"]
+    #[inline]
+    pub fn prot11(&mut self) -> _PROT11W {
+        _PROT11W { w: self }
+    }
+    #[doc = "Bit 12 - Protects Sector 12 from program or erase"]
+    #[inline]
+    pub fn prot12(&mut self) -> _PROT12W {
+        _PROT12W { w: self }
+    }
+    #[doc = "Bit 13 - Protects Sector 13 from program or erase"]
+    #[inline]
+    pub fn prot13(&mut self) -> _PROT13W {
+        _PROT13W { w: self }
+    }
+    #[doc = "Bit 14 - Protects Sector 14 from program or erase"]
+    #[inline]
+    pub fn prot14(&mut self) -> _PROT14W {
+        _PROT14W { w: self }
+    }
+    #[doc = "Bit 15 - Protects Sector 15 from program or erase"]
+    #[inline]
+    pub fn prot15(&mut self) -> _PROT15W {
+        _PROT15W { w: self }
+    }
+    #[doc = "Bit 16 - Protects Sector 16 from program or erase"]
+    #[inline]
+    pub fn prot16(&mut self) -> _PROT16W {
+        _PROT16W { w: self }
+    }
+    #[doc = "Bit 17 - Protects Sector 17 from program or erase"]
+    #[inline]
+    pub fn prot17(&mut self) -> _PROT17W {
+        _PROT17W { w: self }
+    }
+    #[doc = "Bit 18 - Protects Sector 18 from program or erase"]
+    #[inline]
+    pub fn prot18(&mut self) -> _PROT18W {
+        _PROT18W { w: self }
+    }
+    #[doc = "Bit 19 - Protects Sector 19 from program or erase"]
+    #[inline]
+    pub fn prot19(&mut self) -> _PROT19W {
+        _PROT19W { w: self }
+    }
+    #[doc = "Bit 20 - Protects Sector 20 from program or erase"]
+    #[inline]
+    pub fn prot20(&mut self) -> _PROT20W {
+        _PROT20W { w: self }
+    }
+    #[doc = "Bit 21 - Protects Sector 21 from program or erase"]
+    #[inline]
+    pub fn prot21(&mut self) -> _PROT21W {
+        _PROT21W { w: self }
+    }
+    #[doc = "Bit 22 - Protects Sector 22 from program or erase"]
+    #[inline]
+    pub fn prot22(&mut self) -> _PROT22W {
+        _PROT22W { w: self }
+    }
+    #[doc = "Bit 23 - Protects Sector 23 from program or erase"]
+    #[inline]
+    pub fn prot23(&mut self) -> _PROT23W {
+        _PROT23W { w: self }
+    }
+    #[doc = "Bit 24 - Protects Sector 24 from program or erase"]
+    #[inline]
+    pub fn prot24(&mut self) -> _PROT24W {
+        _PROT24W { w: self }
+    }
+    #[doc = "Bit 25 - Protects Sector 25 from program or erase"]
+    #[inline]
+    pub fn prot25(&mut self) -> _PROT25W {
+        _PROT25W { w: self }
+    }
+    #[doc = "Bit 26 - Protects Sector 26 from program or erase"]
+    #[inline]
+    pub fn prot26(&mut self) -> _PROT26W {
+        _PROT26W { w: self }
+    }
+    #[doc = "Bit 27 - Protects Sector 27 from program or erase"]
+    #[inline]
+    pub fn prot27(&mut self) -> _PROT27W {
+        _PROT27W { w: self }
+    }
+    #[doc = "Bit 28 - Protects Sector 28 from program or erase"]
+    #[inline]
+    pub fn prot28(&mut self) -> _PROT28W {
+        _PROT28W { w: self }
+    }
+    #[doc = "Bit 29 - Protects Sector 29 from program or erase"]
+    #[inline]
+    pub fn prot29(&mut self) -> _PROT29W {
+        _PROT29W { w: self }
+    }
+    #[doc = "Bit 30 - Protects Sector 30 from program or erase"]
+    #[inline]
+    pub fn prot30(&mut self) -> _PROT30W {
+        _PROT30W { w: self }
+    }
+    #[doc = "Bit 31 - Protects Sector 31 from program or erase"]
+    #[inline]
+    pub fn prot31(&mut self) -> _PROT31W {
+        _PROT31W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_bank0_rdctl.rs b/example-source/msp432p401r/src/flctl/flctl_bank0_rdctl.rs
new file mode 100644
index 0000000..33344fd
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_bank0_rdctl.rs
@@ -0,0 +1,831 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_BANK0_RDCTL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `RD_MODE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RD_MODER {
+    #[doc = "Normal read mode"]
+    RD_MODE_0,
+    #[doc = "Read Margin 0"]
+    RD_MODE_1,
+    #[doc = "Read Margin 1"]
+    RD_MODE_2,
+    #[doc = "Program Verify"]
+    RD_MODE_3,
+    #[doc = "Erase Verify"]
+    RD_MODE_4,
+    #[doc = "Leakage Verify"]
+    RD_MODE_5,
+    #[doc = "Read Margin 0B"]
+    RD_MODE_9,
+    #[doc = "Read Margin 1B"]
+    RD_MODE_10,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl RD_MODER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            RD_MODER::RD_MODE_0 => 0,
+            RD_MODER::RD_MODE_1 => 1,
+            RD_MODER::RD_MODE_2 => 2,
+            RD_MODER::RD_MODE_3 => 3,
+            RD_MODER::RD_MODE_4 => 4,
+            RD_MODER::RD_MODE_5 => 5,
+            RD_MODER::RD_MODE_9 => 9,
+            RD_MODER::RD_MODE_10 => 10,
+            RD_MODER::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> RD_MODER {
+        match value {
+            0 => RD_MODER::RD_MODE_0,
+            1 => RD_MODER::RD_MODE_1,
+            2 => RD_MODER::RD_MODE_2,
+            3 => RD_MODER::RD_MODE_3,
+            4 => RD_MODER::RD_MODE_4,
+            5 => RD_MODER::RD_MODE_5,
+            9 => RD_MODER::RD_MODE_9,
+            10 => RD_MODER::RD_MODE_10,
+            i => RD_MODER::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_0`"]
+    #[inline]
+    pub fn is_rd_mode_0(&self) -> bool {
+        *self == RD_MODER::RD_MODE_0
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_1`"]
+    #[inline]
+    pub fn is_rd_mode_1(&self) -> bool {
+        *self == RD_MODER::RD_MODE_1
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_2`"]
+    #[inline]
+    pub fn is_rd_mode_2(&self) -> bool {
+        *self == RD_MODER::RD_MODE_2
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_3`"]
+    #[inline]
+    pub fn is_rd_mode_3(&self) -> bool {
+        *self == RD_MODER::RD_MODE_3
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_4`"]
+    #[inline]
+    pub fn is_rd_mode_4(&self) -> bool {
+        *self == RD_MODER::RD_MODE_4
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_5`"]
+    #[inline]
+    pub fn is_rd_mode_5(&self) -> bool {
+        *self == RD_MODER::RD_MODE_5
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_9`"]
+    #[inline]
+    pub fn is_rd_mode_9(&self) -> bool {
+        *self == RD_MODER::RD_MODE_9
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_10`"]
+    #[inline]
+    pub fn is_rd_mode_10(&self) -> bool {
+        *self == RD_MODER::RD_MODE_10
+    }
+}
+#[doc = r" Value of the field"]
+pub struct BUFIR {
+    bits: bool,
+}
+impl BUFIR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct BUFDR {
+    bits: bool,
+}
+impl BUFDR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `WAIT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WAITR {
+    #[doc = "0 wait states"]
+    WAIT_0,
+    #[doc = "1 wait states"]
+    WAIT_1,
+    #[doc = "2 wait states"]
+    WAIT_2,
+    #[doc = "3 wait states"]
+    WAIT_3,
+    #[doc = "4 wait states"]
+    WAIT_4,
+    #[doc = "5 wait states"]
+    WAIT_5,
+    #[doc = "6 wait states"]
+    WAIT_6,
+    #[doc = "7 wait states"]
+    WAIT_7,
+    #[doc = "8 wait states"]
+    WAIT_8,
+    #[doc = "9 wait states"]
+    WAIT_9,
+    #[doc = "10 wait states"]
+    WAIT_10,
+    #[doc = "11 wait states"]
+    WAIT_11,
+    #[doc = "12 wait states"]
+    WAIT_12,
+    #[doc = "13 wait states"]
+    WAIT_13,
+    #[doc = "14 wait states"]
+    WAIT_14,
+    #[doc = "15 wait states"]
+    WAIT_15,
+}
+impl WAITR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            WAITR::WAIT_0 => 0,
+            WAITR::WAIT_1 => 1,
+            WAITR::WAIT_2 => 2,
+            WAITR::WAIT_3 => 3,
+            WAITR::WAIT_4 => 4,
+            WAITR::WAIT_5 => 5,
+            WAITR::WAIT_6 => 6,
+            WAITR::WAIT_7 => 7,
+            WAITR::WAIT_8 => 8,
+            WAITR::WAIT_9 => 9,
+            WAITR::WAIT_10 => 10,
+            WAITR::WAIT_11 => 11,
+            WAITR::WAIT_12 => 12,
+            WAITR::WAIT_13 => 13,
+            WAITR::WAIT_14 => 14,
+            WAITR::WAIT_15 => 15,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> WAITR {
+        match value {
+            0 => WAITR::WAIT_0,
+            1 => WAITR::WAIT_1,
+            2 => WAITR::WAIT_2,
+            3 => WAITR::WAIT_3,
+            4 => WAITR::WAIT_4,
+            5 => WAITR::WAIT_5,
+            6 => WAITR::WAIT_6,
+            7 => WAITR::WAIT_7,
+            8 => WAITR::WAIT_8,
+            9 => WAITR::WAIT_9,
+            10 => WAITR::WAIT_10,
+            11 => WAITR::WAIT_11,
+            12 => WAITR::WAIT_12,
+            13 => WAITR::WAIT_13,
+            14 => WAITR::WAIT_14,
+            15 => WAITR::WAIT_15,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `WAIT_0`"]
+    #[inline]
+    pub fn is_wait_0(&self) -> bool {
+        *self == WAITR::WAIT_0
+    }
+    #[doc = "Checks if the value of the field is `WAIT_1`"]
+    #[inline]
+    pub fn is_wait_1(&self) -> bool {
+        *self == WAITR::WAIT_1
+    }
+    #[doc = "Checks if the value of the field is `WAIT_2`"]
+    #[inline]
+    pub fn is_wait_2(&self) -> bool {
+        *self == WAITR::WAIT_2
+    }
+    #[doc = "Checks if the value of the field is `WAIT_3`"]
+    #[inline]
+    pub fn is_wait_3(&self) -> bool {
+        *self == WAITR::WAIT_3
+    }
+    #[doc = "Checks if the value of the field is `WAIT_4`"]
+    #[inline]
+    pub fn is_wait_4(&self) -> bool {
+        *self == WAITR::WAIT_4
+    }
+    #[doc = "Checks if the value of the field is `WAIT_5`"]
+    #[inline]
+    pub fn is_wait_5(&self) -> bool {
+        *self == WAITR::WAIT_5
+    }
+    #[doc = "Checks if the value of the field is `WAIT_6`"]
+    #[inline]
+    pub fn is_wait_6(&self) -> bool {
+        *self == WAITR::WAIT_6
+    }
+    #[doc = "Checks if the value of the field is `WAIT_7`"]
+    #[inline]
+    pub fn is_wait_7(&self) -> bool {
+        *self == WAITR::WAIT_7
+    }
+    #[doc = "Checks if the value of the field is `WAIT_8`"]
+    #[inline]
+    pub fn is_wait_8(&self) -> bool {
+        *self == WAITR::WAIT_8
+    }
+    #[doc = "Checks if the value of the field is `WAIT_9`"]
+    #[inline]
+    pub fn is_wait_9(&self) -> bool {
+        *self == WAITR::WAIT_9
+    }
+    #[doc = "Checks if the value of the field is `WAIT_10`"]
+    #[inline]
+    pub fn is_wait_10(&self) -> bool {
+        *self == WAITR::WAIT_10
+    }
+    #[doc = "Checks if the value of the field is `WAIT_11`"]
+    #[inline]
+    pub fn is_wait_11(&self) -> bool {
+        *self == WAITR::WAIT_11
+    }
+    #[doc = "Checks if the value of the field is `WAIT_12`"]
+    #[inline]
+    pub fn is_wait_12(&self) -> bool {
+        *self == WAITR::WAIT_12
+    }
+    #[doc = "Checks if the value of the field is `WAIT_13`"]
+    #[inline]
+    pub fn is_wait_13(&self) -> bool {
+        *self == WAITR::WAIT_13
+    }
+    #[doc = "Checks if the value of the field is `WAIT_14`"]
+    #[inline]
+    pub fn is_wait_14(&self) -> bool {
+        *self == WAITR::WAIT_14
+    }
+    #[doc = "Checks if the value of the field is `WAIT_15`"]
+    #[inline]
+    pub fn is_wait_15(&self) -> bool {
+        *self == WAITR::WAIT_15
+    }
+}
+#[doc = "Possible values of the field `RD_MODE_STATUS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RD_MODE_STATUSR {
+    #[doc = "Normal read mode"]
+    RD_MODE_STATUS_0,
+    #[doc = "Read Margin 0"]
+    RD_MODE_STATUS_1,
+    #[doc = "Read Margin 1"]
+    RD_MODE_STATUS_2,
+    #[doc = "Program Verify"]
+    RD_MODE_STATUS_3,
+    #[doc = "Erase Verify"]
+    RD_MODE_STATUS_4,
+    #[doc = "Leakage Verify"]
+    RD_MODE_STATUS_5,
+    #[doc = "Read Margin 0B"]
+    RD_MODE_STATUS_9,
+    #[doc = "Read Margin 1B"]
+    RD_MODE_STATUS_10,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl RD_MODE_STATUSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            RD_MODE_STATUSR::RD_MODE_STATUS_0 => 0,
+            RD_MODE_STATUSR::RD_MODE_STATUS_1 => 1,
+            RD_MODE_STATUSR::RD_MODE_STATUS_2 => 2,
+            RD_MODE_STATUSR::RD_MODE_STATUS_3 => 3,
+            RD_MODE_STATUSR::RD_MODE_STATUS_4 => 4,
+            RD_MODE_STATUSR::RD_MODE_STATUS_5 => 5,
+            RD_MODE_STATUSR::RD_MODE_STATUS_9 => 9,
+            RD_MODE_STATUSR::RD_MODE_STATUS_10 => 10,
+            RD_MODE_STATUSR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> RD_MODE_STATUSR {
+        match value {
+            0 => RD_MODE_STATUSR::RD_MODE_STATUS_0,
+            1 => RD_MODE_STATUSR::RD_MODE_STATUS_1,
+            2 => RD_MODE_STATUSR::RD_MODE_STATUS_2,
+            3 => RD_MODE_STATUSR::RD_MODE_STATUS_3,
+            4 => RD_MODE_STATUSR::RD_MODE_STATUS_4,
+            5 => RD_MODE_STATUSR::RD_MODE_STATUS_5,
+            9 => RD_MODE_STATUSR::RD_MODE_STATUS_9,
+            10 => RD_MODE_STATUSR::RD_MODE_STATUS_10,
+            i => RD_MODE_STATUSR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_STATUS_0`"]
+    #[inline]
+    pub fn is_rd_mode_status_0(&self) -> bool {
+        *self == RD_MODE_STATUSR::RD_MODE_STATUS_0
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_STATUS_1`"]
+    #[inline]
+    pub fn is_rd_mode_status_1(&self) -> bool {
+        *self == RD_MODE_STATUSR::RD_MODE_STATUS_1
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_STATUS_2`"]
+    #[inline]
+    pub fn is_rd_mode_status_2(&self) -> bool {
+        *self == RD_MODE_STATUSR::RD_MODE_STATUS_2
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_STATUS_3`"]
+    #[inline]
+    pub fn is_rd_mode_status_3(&self) -> bool {
+        *self == RD_MODE_STATUSR::RD_MODE_STATUS_3
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_STATUS_4`"]
+    #[inline]
+    pub fn is_rd_mode_status_4(&self) -> bool {
+        *self == RD_MODE_STATUSR::RD_MODE_STATUS_4
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_STATUS_5`"]
+    #[inline]
+    pub fn is_rd_mode_status_5(&self) -> bool {
+        *self == RD_MODE_STATUSR::RD_MODE_STATUS_5
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_STATUS_9`"]
+    #[inline]
+    pub fn is_rd_mode_status_9(&self) -> bool {
+        *self == RD_MODE_STATUSR::RD_MODE_STATUS_9
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_STATUS_10`"]
+    #[inline]
+    pub fn is_rd_mode_status_10(&self) -> bool {
+        *self == RD_MODE_STATUSR::RD_MODE_STATUS_10
+    }
+}
+#[doc = "Values that can be written to the field `RD_MODE`"]
+pub enum RD_MODEW {
+    #[doc = "Normal read mode"]
+    RD_MODE_0,
+    #[doc = "Read Margin 0"]
+    RD_MODE_1,
+    #[doc = "Read Margin 1"]
+    RD_MODE_2,
+    #[doc = "Program Verify"]
+    RD_MODE_3,
+    #[doc = "Erase Verify"]
+    RD_MODE_4,
+    #[doc = "Leakage Verify"]
+    RD_MODE_5,
+    #[doc = "Read Margin 0B"]
+    RD_MODE_9,
+    #[doc = "Read Margin 1B"]
+    RD_MODE_10,
+}
+impl RD_MODEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            RD_MODEW::RD_MODE_0 => 0,
+            RD_MODEW::RD_MODE_1 => 1,
+            RD_MODEW::RD_MODE_2 => 2,
+            RD_MODEW::RD_MODE_3 => 3,
+            RD_MODEW::RD_MODE_4 => 4,
+            RD_MODEW::RD_MODE_5 => 5,
+            RD_MODEW::RD_MODE_9 => 9,
+            RD_MODEW::RD_MODE_10 => 10,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RD_MODEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RD_MODEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: RD_MODEW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "Normal read mode"]
+    #[inline]
+    pub fn rd_mode_0(self) -> &'a mut W {
+        self.variant(RD_MODEW::RD_MODE_0)
+    }
+    #[doc = "Read Margin 0"]
+    #[inline]
+    pub fn rd_mode_1(self) -> &'a mut W {
+        self.variant(RD_MODEW::RD_MODE_1)
+    }
+    #[doc = "Read Margin 1"]
+    #[inline]
+    pub fn rd_mode_2(self) -> &'a mut W {
+        self.variant(RD_MODEW::RD_MODE_2)
+    }
+    #[doc = "Program Verify"]
+    #[inline]
+    pub fn rd_mode_3(self) -> &'a mut W {
+        self.variant(RD_MODEW::RD_MODE_3)
+    }
+    #[doc = "Erase Verify"]
+    #[inline]
+    pub fn rd_mode_4(self) -> &'a mut W {
+        self.variant(RD_MODEW::RD_MODE_4)
+    }
+    #[doc = "Leakage Verify"]
+    #[inline]
+    pub fn rd_mode_5(self) -> &'a mut W {
+        self.variant(RD_MODEW::RD_MODE_5)
+    }
+    #[doc = "Read Margin 0B"]
+    #[inline]
+    pub fn rd_mode_9(self) -> &'a mut W {
+        self.variant(RD_MODEW::RD_MODE_9)
+    }
+    #[doc = "Read Margin 1B"]
+    #[inline]
+    pub fn rd_mode_10(self) -> &'a mut W {
+        self.variant(RD_MODEW::RD_MODE_10)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _BUFIW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _BUFIW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _BUFDW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _BUFDW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `WAIT`"]
+pub enum WAITW {
+    #[doc = "0 wait states"]
+    WAIT_0,
+    #[doc = "1 wait states"]
+    WAIT_1,
+    #[doc = "2 wait states"]
+    WAIT_2,
+    #[doc = "3 wait states"]
+    WAIT_3,
+    #[doc = "4 wait states"]
+    WAIT_4,
+    #[doc = "5 wait states"]
+    WAIT_5,
+    #[doc = "6 wait states"]
+    WAIT_6,
+    #[doc = "7 wait states"]
+    WAIT_7,
+    #[doc = "8 wait states"]
+    WAIT_8,
+    #[doc = "9 wait states"]
+    WAIT_9,
+    #[doc = "10 wait states"]
+    WAIT_10,
+    #[doc = "11 wait states"]
+    WAIT_11,
+    #[doc = "12 wait states"]
+    WAIT_12,
+    #[doc = "13 wait states"]
+    WAIT_13,
+    #[doc = "14 wait states"]
+    WAIT_14,
+    #[doc = "15 wait states"]
+    WAIT_15,
+}
+impl WAITW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            WAITW::WAIT_0 => 0,
+            WAITW::WAIT_1 => 1,
+            WAITW::WAIT_2 => 2,
+            WAITW::WAIT_3 => 3,
+            WAITW::WAIT_4 => 4,
+            WAITW::WAIT_5 => 5,
+            WAITW::WAIT_6 => 6,
+            WAITW::WAIT_7 => 7,
+            WAITW::WAIT_8 => 8,
+            WAITW::WAIT_9 => 9,
+            WAITW::WAIT_10 => 10,
+            WAITW::WAIT_11 => 11,
+            WAITW::WAIT_12 => 12,
+            WAITW::WAIT_13 => 13,
+            WAITW::WAIT_14 => 14,
+            WAITW::WAIT_15 => 15,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _WAITW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _WAITW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: WAITW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "0 wait states"]
+    #[inline]
+    pub fn wait_0(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_0)
+    }
+    #[doc = "1 wait states"]
+    #[inline]
+    pub fn wait_1(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_1)
+    }
+    #[doc = "2 wait states"]
+    #[inline]
+    pub fn wait_2(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_2)
+    }
+    #[doc = "3 wait states"]
+    #[inline]
+    pub fn wait_3(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_3)
+    }
+    #[doc = "4 wait states"]
+    #[inline]
+    pub fn wait_4(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_4)
+    }
+    #[doc = "5 wait states"]
+    #[inline]
+    pub fn wait_5(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_5)
+    }
+    #[doc = "6 wait states"]
+    #[inline]
+    pub fn wait_6(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_6)
+    }
+    #[doc = "7 wait states"]
+    #[inline]
+    pub fn wait_7(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_7)
+    }
+    #[doc = "8 wait states"]
+    #[inline]
+    pub fn wait_8(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_8)
+    }
+    #[doc = "9 wait states"]
+    #[inline]
+    pub fn wait_9(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_9)
+    }
+    #[doc = "10 wait states"]
+    #[inline]
+    pub fn wait_10(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_10)
+    }
+    #[doc = "11 wait states"]
+    #[inline]
+    pub fn wait_11(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_11)
+    }
+    #[doc = "12 wait states"]
+    #[inline]
+    pub fn wait_12(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_12)
+    }
+    #[doc = "13 wait states"]
+    #[inline]
+    pub fn wait_13(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_13)
+    }
+    #[doc = "14 wait states"]
+    #[inline]
+    pub fn wait_14(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_14)
+    }
+    #[doc = "15 wait states"]
+    #[inline]
+    pub fn wait_15(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_15)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:3 - Flash read mode control setting for Bank 0"]
+    #[inline]
+    pub fn rd_mode(&self) -> RD_MODER {
+        RD_MODER::_from({
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 4 - Enables read buffering feature for instruction fetches to this Bank"]
+    #[inline]
+    pub fn bufi(&self) -> BUFIR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        BUFIR { bits }
+    }
+    #[doc = "Bit 5 - Enables read buffering feature for data reads to this Bank"]
+    #[inline]
+    pub fn bufd(&self) -> BUFDR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        BUFDR { bits }
+    }
+    #[doc = "Bits 12:15 - Number of wait states for read"]
+    #[inline]
+    pub fn wait(&self) -> WAITR {
+        WAITR::_from({
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 16:19 - Read mode"]
+    #[inline]
+    pub fn rd_mode_status(&self) -> RD_MODE_STATUSR {
+        RD_MODE_STATUSR::_from({
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:3 - Flash read mode control setting for Bank 0"]
+    #[inline]
+    pub fn rd_mode(&mut self) -> _RD_MODEW {
+        _RD_MODEW { w: self }
+    }
+    #[doc = "Bit 4 - Enables read buffering feature for instruction fetches to this Bank"]
+    #[inline]
+    pub fn bufi(&mut self) -> _BUFIW {
+        _BUFIW { w: self }
+    }
+    #[doc = "Bit 5 - Enables read buffering feature for data reads to this Bank"]
+    #[inline]
+    pub fn bufd(&mut self) -> _BUFDW {
+        _BUFDW { w: self }
+    }
+    #[doc = "Bits 12:15 - Number of wait states for read"]
+    #[inline]
+    pub fn wait(&mut self) -> _WAITW {
+        _WAITW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_bank1_info_weprot.rs b/example-source/msp432p401r/src/flctl/flctl_bank1_info_weprot.rs
new file mode 100644
index 0000000..7febfe6
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_bank1_info_weprot.rs
@@ -0,0 +1,182 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_BANK1_INFO_WEPROT {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT0R {
+    bits: bool,
+}
+impl PROT0R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT1R {
+    bits: bool,
+}
+impl PROT1R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT0W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT1W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Protects Sector 0 from program or erase operations"]
+    #[inline]
+    pub fn prot0(&self) -> PROT0R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT0R { bits }
+    }
+    #[doc = "Bit 1 - Protects Sector 1 from program or erase operations"]
+    #[inline]
+    pub fn prot1(&self) -> PROT1R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT1R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 3 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Protects Sector 0 from program or erase operations"]
+    #[inline]
+    pub fn prot0(&mut self) -> _PROT0W {
+        _PROT0W { w: self }
+    }
+    #[doc = "Bit 1 - Protects Sector 1 from program or erase operations"]
+    #[inline]
+    pub fn prot1(&mut self) -> _PROT1W {
+        _PROT1W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_bank1_main_weprot.rs b/example-source/msp432p401r/src/flctl/flctl_bank1_main_weprot.rs
new file mode 100644
index 0000000..418b8aa
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_bank1_main_weprot.rs
@@ -0,0 +1,1952 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_BANK1_MAIN_WEPROT {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT0R {
+    bits: bool,
+}
+impl PROT0R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT1R {
+    bits: bool,
+}
+impl PROT1R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT2R {
+    bits: bool,
+}
+impl PROT2R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT3R {
+    bits: bool,
+}
+impl PROT3R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT4R {
+    bits: bool,
+}
+impl PROT4R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT5R {
+    bits: bool,
+}
+impl PROT5R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT6R {
+    bits: bool,
+}
+impl PROT6R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT7R {
+    bits: bool,
+}
+impl PROT7R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT8R {
+    bits: bool,
+}
+impl PROT8R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT9R {
+    bits: bool,
+}
+impl PROT9R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT10R {
+    bits: bool,
+}
+impl PROT10R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT11R {
+    bits: bool,
+}
+impl PROT11R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT12R {
+    bits: bool,
+}
+impl PROT12R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT13R {
+    bits: bool,
+}
+impl PROT13R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT14R {
+    bits: bool,
+}
+impl PROT14R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT15R {
+    bits: bool,
+}
+impl PROT15R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT16R {
+    bits: bool,
+}
+impl PROT16R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT17R {
+    bits: bool,
+}
+impl PROT17R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT18R {
+    bits: bool,
+}
+impl PROT18R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT19R {
+    bits: bool,
+}
+impl PROT19R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT20R {
+    bits: bool,
+}
+impl PROT20R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT21R {
+    bits: bool,
+}
+impl PROT21R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT22R {
+    bits: bool,
+}
+impl PROT22R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT23R {
+    bits: bool,
+}
+impl PROT23R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT24R {
+    bits: bool,
+}
+impl PROT24R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT25R {
+    bits: bool,
+}
+impl PROT25R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT26R {
+    bits: bool,
+}
+impl PROT26R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT27R {
+    bits: bool,
+}
+impl PROT27R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT28R {
+    bits: bool,
+}
+impl PROT28R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT29R {
+    bits: bool,
+}
+impl PROT29R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT30R {
+    bits: bool,
+}
+impl PROT30R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PROT31R {
+    bits: bool,
+}
+impl PROT31R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT0W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT1W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT2W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT3W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT4W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT4W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT5W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT5W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT6W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT6W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT7W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT7W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT8W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT8W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT9W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT9W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT10W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT10W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT11W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT11W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT12W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT12W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT13W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT13W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT14W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT14W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT15W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT15W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT16W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT16W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 16;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT17W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT17W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 17;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT18W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT18W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 18;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT19W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT19W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 19;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT20W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT20W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 20;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT21W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT21W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 21;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT22W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT22W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 22;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT23W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT23W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 23;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT24W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT24W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 24;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT25W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT25W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 25;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT26W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT26W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 26;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT27W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT27W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 27;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT28W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT28W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 28;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT29W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT29W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 29;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT30W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT30W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 30;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PROT31W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PROT31W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 31;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Protects Sector 0 from program or erase operations"]
+    #[inline]
+    pub fn prot0(&self) -> PROT0R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT0R { bits }
+    }
+    #[doc = "Bit 1 - Protects Sector 1 from program or erase operations"]
+    #[inline]
+    pub fn prot1(&self) -> PROT1R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT1R { bits }
+    }
+    #[doc = "Bit 2 - Protects Sector 2 from program or erase operations"]
+    #[inline]
+    pub fn prot2(&self) -> PROT2R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT2R { bits }
+    }
+    #[doc = "Bit 3 - Protects Sector 3 from program or erase operations"]
+    #[inline]
+    pub fn prot3(&self) -> PROT3R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT3R { bits }
+    }
+    #[doc = "Bit 4 - Protects Sector 4 from program or erase operations"]
+    #[inline]
+    pub fn prot4(&self) -> PROT4R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT4R { bits }
+    }
+    #[doc = "Bit 5 - Protects Sector 5 from program or erase operations"]
+    #[inline]
+    pub fn prot5(&self) -> PROT5R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT5R { bits }
+    }
+    #[doc = "Bit 6 - Protects Sector 6 from program or erase operations"]
+    #[inline]
+    pub fn prot6(&self) -> PROT6R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT6R { bits }
+    }
+    #[doc = "Bit 7 - Protects Sector 7 from program or erase operations"]
+    #[inline]
+    pub fn prot7(&self) -> PROT7R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT7R { bits }
+    }
+    #[doc = "Bit 8 - Protects Sector 8 from program or erase operations"]
+    #[inline]
+    pub fn prot8(&self) -> PROT8R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT8R { bits }
+    }
+    #[doc = "Bit 9 - Protects Sector 9 from program or erase operations"]
+    #[inline]
+    pub fn prot9(&self) -> PROT9R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT9R { bits }
+    }
+    #[doc = "Bit 10 - Protects Sector 10 from program or erase operations"]
+    #[inline]
+    pub fn prot10(&self) -> PROT10R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT10R { bits }
+    }
+    #[doc = "Bit 11 - Protects Sector 11 from program or erase operations"]
+    #[inline]
+    pub fn prot11(&self) -> PROT11R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT11R { bits }
+    }
+    #[doc = "Bit 12 - Protects Sector 12 from program or erase operations"]
+    #[inline]
+    pub fn prot12(&self) -> PROT12R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT12R { bits }
+    }
+    #[doc = "Bit 13 - Protects Sector 13 from program or erase operations"]
+    #[inline]
+    pub fn prot13(&self) -> PROT13R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT13R { bits }
+    }
+    #[doc = "Bit 14 - Protects Sector 14 from program or erase operations"]
+    #[inline]
+    pub fn prot14(&self) -> PROT14R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT14R { bits }
+    }
+    #[doc = "Bit 15 - Protects Sector 15 from program or erase operations"]
+    #[inline]
+    pub fn prot15(&self) -> PROT15R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT15R { bits }
+    }
+    #[doc = "Bit 16 - Protects Sector 16 from program or erase operations"]
+    #[inline]
+    pub fn prot16(&self) -> PROT16R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT16R { bits }
+    }
+    #[doc = "Bit 17 - Protects Sector 17 from program or erase operations"]
+    #[inline]
+    pub fn prot17(&self) -> PROT17R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 17;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT17R { bits }
+    }
+    #[doc = "Bit 18 - Protects Sector 18 from program or erase operations"]
+    #[inline]
+    pub fn prot18(&self) -> PROT18R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 18;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT18R { bits }
+    }
+    #[doc = "Bit 19 - Protects Sector 19 from program or erase operations"]
+    #[inline]
+    pub fn prot19(&self) -> PROT19R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 19;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT19R { bits }
+    }
+    #[doc = "Bit 20 - Protects Sector 20 from program or erase operations"]
+    #[inline]
+    pub fn prot20(&self) -> PROT20R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 20;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT20R { bits }
+    }
+    #[doc = "Bit 21 - Protects Sector 21 from program or erase operations"]
+    #[inline]
+    pub fn prot21(&self) -> PROT21R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 21;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT21R { bits }
+    }
+    #[doc = "Bit 22 - Protects Sector 22 from program or erase operations"]
+    #[inline]
+    pub fn prot22(&self) -> PROT22R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 22;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT22R { bits }
+    }
+    #[doc = "Bit 23 - Protects Sector 23 from program or erase operations"]
+    #[inline]
+    pub fn prot23(&self) -> PROT23R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 23;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT23R { bits }
+    }
+    #[doc = "Bit 24 - Protects Sector 24 from program or erase operations"]
+    #[inline]
+    pub fn prot24(&self) -> PROT24R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 24;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT24R { bits }
+    }
+    #[doc = "Bit 25 - Protects Sector 25 from program or erase operations"]
+    #[inline]
+    pub fn prot25(&self) -> PROT25R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 25;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT25R { bits }
+    }
+    #[doc = "Bit 26 - Protects Sector 26 from program or erase operations"]
+    #[inline]
+    pub fn prot26(&self) -> PROT26R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 26;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT26R { bits }
+    }
+    #[doc = "Bit 27 - Protects Sector 27 from program or erase operations"]
+    #[inline]
+    pub fn prot27(&self) -> PROT27R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 27;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT27R { bits }
+    }
+    #[doc = "Bit 28 - Protects Sector 28 from program or erase operations"]
+    #[inline]
+    pub fn prot28(&self) -> PROT28R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 28;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT28R { bits }
+    }
+    #[doc = "Bit 29 - Protects Sector 29 from program or erase operations"]
+    #[inline]
+    pub fn prot29(&self) -> PROT29R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 29;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT29R { bits }
+    }
+    #[doc = "Bit 30 - Protects Sector 30 from program or erase operations"]
+    #[inline]
+    pub fn prot30(&self) -> PROT30R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 30;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT30R { bits }
+    }
+    #[doc = "Bit 31 - Protects Sector 31 from program or erase operations"]
+    #[inline]
+    pub fn prot31(&self) -> PROT31R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 31;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PROT31R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 4294967295 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Protects Sector 0 from program or erase operations"]
+    #[inline]
+    pub fn prot0(&mut self) -> _PROT0W {
+        _PROT0W { w: self }
+    }
+    #[doc = "Bit 1 - Protects Sector 1 from program or erase operations"]
+    #[inline]
+    pub fn prot1(&mut self) -> _PROT1W {
+        _PROT1W { w: self }
+    }
+    #[doc = "Bit 2 - Protects Sector 2 from program or erase operations"]
+    #[inline]
+    pub fn prot2(&mut self) -> _PROT2W {
+        _PROT2W { w: self }
+    }
+    #[doc = "Bit 3 - Protects Sector 3 from program or erase operations"]
+    #[inline]
+    pub fn prot3(&mut self) -> _PROT3W {
+        _PROT3W { w: self }
+    }
+    #[doc = "Bit 4 - Protects Sector 4 from program or erase operations"]
+    #[inline]
+    pub fn prot4(&mut self) -> _PROT4W {
+        _PROT4W { w: self }
+    }
+    #[doc = "Bit 5 - Protects Sector 5 from program or erase operations"]
+    #[inline]
+    pub fn prot5(&mut self) -> _PROT5W {
+        _PROT5W { w: self }
+    }
+    #[doc = "Bit 6 - Protects Sector 6 from program or erase operations"]
+    #[inline]
+    pub fn prot6(&mut self) -> _PROT6W {
+        _PROT6W { w: self }
+    }
+    #[doc = "Bit 7 - Protects Sector 7 from program or erase operations"]
+    #[inline]
+    pub fn prot7(&mut self) -> _PROT7W {
+        _PROT7W { w: self }
+    }
+    #[doc = "Bit 8 - Protects Sector 8 from program or erase operations"]
+    #[inline]
+    pub fn prot8(&mut self) -> _PROT8W {
+        _PROT8W { w: self }
+    }
+    #[doc = "Bit 9 - Protects Sector 9 from program or erase operations"]
+    #[inline]
+    pub fn prot9(&mut self) -> _PROT9W {
+        _PROT9W { w: self }
+    }
+    #[doc = "Bit 10 - Protects Sector 10 from program or erase operations"]
+    #[inline]
+    pub fn prot10(&mut self) -> _PROT10W {
+        _PROT10W { w: self }
+    }
+    #[doc = "Bit 11 - Protects Sector 11 from program or erase operations"]
+    #[inline]
+    pub fn prot11(&mut self) -> _PROT11W {
+        _PROT11W { w: self }
+    }
+    #[doc = "Bit 12 - Protects Sector 12 from program or erase operations"]
+    #[inline]
+    pub fn prot12(&mut self) -> _PROT12W {
+        _PROT12W { w: self }
+    }
+    #[doc = "Bit 13 - Protects Sector 13 from program or erase operations"]
+    #[inline]
+    pub fn prot13(&mut self) -> _PROT13W {
+        _PROT13W { w: self }
+    }
+    #[doc = "Bit 14 - Protects Sector 14 from program or erase operations"]
+    #[inline]
+    pub fn prot14(&mut self) -> _PROT14W {
+        _PROT14W { w: self }
+    }
+    #[doc = "Bit 15 - Protects Sector 15 from program or erase operations"]
+    #[inline]
+    pub fn prot15(&mut self) -> _PROT15W {
+        _PROT15W { w: self }
+    }
+    #[doc = "Bit 16 - Protects Sector 16 from program or erase operations"]
+    #[inline]
+    pub fn prot16(&mut self) -> _PROT16W {
+        _PROT16W { w: self }
+    }
+    #[doc = "Bit 17 - Protects Sector 17 from program or erase operations"]
+    #[inline]
+    pub fn prot17(&mut self) -> _PROT17W {
+        _PROT17W { w: self }
+    }
+    #[doc = "Bit 18 - Protects Sector 18 from program or erase operations"]
+    #[inline]
+    pub fn prot18(&mut self) -> _PROT18W {
+        _PROT18W { w: self }
+    }
+    #[doc = "Bit 19 - Protects Sector 19 from program or erase operations"]
+    #[inline]
+    pub fn prot19(&mut self) -> _PROT19W {
+        _PROT19W { w: self }
+    }
+    #[doc = "Bit 20 - Protects Sector 20 from program or erase operations"]
+    #[inline]
+    pub fn prot20(&mut self) -> _PROT20W {
+        _PROT20W { w: self }
+    }
+    #[doc = "Bit 21 - Protects Sector 21 from program or erase operations"]
+    #[inline]
+    pub fn prot21(&mut self) -> _PROT21W {
+        _PROT21W { w: self }
+    }
+    #[doc = "Bit 22 - Protects Sector 22 from program or erase operations"]
+    #[inline]
+    pub fn prot22(&mut self) -> _PROT22W {
+        _PROT22W { w: self }
+    }
+    #[doc = "Bit 23 - Protects Sector 23 from program or erase operations"]
+    #[inline]
+    pub fn prot23(&mut self) -> _PROT23W {
+        _PROT23W { w: self }
+    }
+    #[doc = "Bit 24 - Protects Sector 24 from program or erase operations"]
+    #[inline]
+    pub fn prot24(&mut self) -> _PROT24W {
+        _PROT24W { w: self }
+    }
+    #[doc = "Bit 25 - Protects Sector 25 from program or erase operations"]
+    #[inline]
+    pub fn prot25(&mut self) -> _PROT25W {
+        _PROT25W { w: self }
+    }
+    #[doc = "Bit 26 - Protects Sector 26 from program or erase operations"]
+    #[inline]
+    pub fn prot26(&mut self) -> _PROT26W {
+        _PROT26W { w: self }
+    }
+    #[doc = "Bit 27 - Protects Sector 27 from program or erase operations"]
+    #[inline]
+    pub fn prot27(&mut self) -> _PROT27W {
+        _PROT27W { w: self }
+    }
+    #[doc = "Bit 28 - Protects Sector 28 from program or erase operations"]
+    #[inline]
+    pub fn prot28(&mut self) -> _PROT28W {
+        _PROT28W { w: self }
+    }
+    #[doc = "Bit 29 - Protects Sector 29 from program or erase operations"]
+    #[inline]
+    pub fn prot29(&mut self) -> _PROT29W {
+        _PROT29W { w: self }
+    }
+    #[doc = "Bit 30 - Protects Sector 30 from program or erase operations"]
+    #[inline]
+    pub fn prot30(&mut self) -> _PROT30W {
+        _PROT30W { w: self }
+    }
+    #[doc = "Bit 31 - Protects Sector 31 from program or erase operations"]
+    #[inline]
+    pub fn prot31(&mut self) -> _PROT31W {
+        _PROT31W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_bank1_rdctl.rs b/example-source/msp432p401r/src/flctl/flctl_bank1_rdctl.rs
new file mode 100644
index 0000000..c985e50
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_bank1_rdctl.rs
@@ -0,0 +1,831 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_BANK1_RDCTL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `RD_MODE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RD_MODER {
+    #[doc = "Normal read mode"]
+    RD_MODE_0,
+    #[doc = "Read Margin 0"]
+    RD_MODE_1,
+    #[doc = "Read Margin 1"]
+    RD_MODE_2,
+    #[doc = "Program Verify"]
+    RD_MODE_3,
+    #[doc = "Erase Verify"]
+    RD_MODE_4,
+    #[doc = "Leakage Verify"]
+    RD_MODE_5,
+    #[doc = "Read Margin 0B"]
+    RD_MODE_9,
+    #[doc = "Read Margin 1B"]
+    RD_MODE_10,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl RD_MODER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            RD_MODER::RD_MODE_0 => 0,
+            RD_MODER::RD_MODE_1 => 1,
+            RD_MODER::RD_MODE_2 => 2,
+            RD_MODER::RD_MODE_3 => 3,
+            RD_MODER::RD_MODE_4 => 4,
+            RD_MODER::RD_MODE_5 => 5,
+            RD_MODER::RD_MODE_9 => 9,
+            RD_MODER::RD_MODE_10 => 10,
+            RD_MODER::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> RD_MODER {
+        match value {
+            0 => RD_MODER::RD_MODE_0,
+            1 => RD_MODER::RD_MODE_1,
+            2 => RD_MODER::RD_MODE_2,
+            3 => RD_MODER::RD_MODE_3,
+            4 => RD_MODER::RD_MODE_4,
+            5 => RD_MODER::RD_MODE_5,
+            9 => RD_MODER::RD_MODE_9,
+            10 => RD_MODER::RD_MODE_10,
+            i => RD_MODER::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_0`"]
+    #[inline]
+    pub fn is_rd_mode_0(&self) -> bool {
+        *self == RD_MODER::RD_MODE_0
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_1`"]
+    #[inline]
+    pub fn is_rd_mode_1(&self) -> bool {
+        *self == RD_MODER::RD_MODE_1
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_2`"]
+    #[inline]
+    pub fn is_rd_mode_2(&self) -> bool {
+        *self == RD_MODER::RD_MODE_2
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_3`"]
+    #[inline]
+    pub fn is_rd_mode_3(&self) -> bool {
+        *self == RD_MODER::RD_MODE_3
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_4`"]
+    #[inline]
+    pub fn is_rd_mode_4(&self) -> bool {
+        *self == RD_MODER::RD_MODE_4
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_5`"]
+    #[inline]
+    pub fn is_rd_mode_5(&self) -> bool {
+        *self == RD_MODER::RD_MODE_5
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_9`"]
+    #[inline]
+    pub fn is_rd_mode_9(&self) -> bool {
+        *self == RD_MODER::RD_MODE_9
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_10`"]
+    #[inline]
+    pub fn is_rd_mode_10(&self) -> bool {
+        *self == RD_MODER::RD_MODE_10
+    }
+}
+#[doc = r" Value of the field"]
+pub struct BUFIR {
+    bits: bool,
+}
+impl BUFIR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct BUFDR {
+    bits: bool,
+}
+impl BUFDR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `RD_MODE_STATUS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RD_MODE_STATUSR {
+    #[doc = "Normal read mode"]
+    RD_MODE_STATUS_0,
+    #[doc = "Read Margin 0"]
+    RD_MODE_STATUS_1,
+    #[doc = "Read Margin 1"]
+    RD_MODE_STATUS_2,
+    #[doc = "Program Verify"]
+    RD_MODE_STATUS_3,
+    #[doc = "Erase Verify"]
+    RD_MODE_STATUS_4,
+    #[doc = "Leakage Verify"]
+    RD_MODE_STATUS_5,
+    #[doc = "Read Margin 0B"]
+    RD_MODE_STATUS_9,
+    #[doc = "Read Margin 1B"]
+    RD_MODE_STATUS_10,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl RD_MODE_STATUSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            RD_MODE_STATUSR::RD_MODE_STATUS_0 => 0,
+            RD_MODE_STATUSR::RD_MODE_STATUS_1 => 1,
+            RD_MODE_STATUSR::RD_MODE_STATUS_2 => 2,
+            RD_MODE_STATUSR::RD_MODE_STATUS_3 => 3,
+            RD_MODE_STATUSR::RD_MODE_STATUS_4 => 4,
+            RD_MODE_STATUSR::RD_MODE_STATUS_5 => 5,
+            RD_MODE_STATUSR::RD_MODE_STATUS_9 => 9,
+            RD_MODE_STATUSR::RD_MODE_STATUS_10 => 10,
+            RD_MODE_STATUSR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> RD_MODE_STATUSR {
+        match value {
+            0 => RD_MODE_STATUSR::RD_MODE_STATUS_0,
+            1 => RD_MODE_STATUSR::RD_MODE_STATUS_1,
+            2 => RD_MODE_STATUSR::RD_MODE_STATUS_2,
+            3 => RD_MODE_STATUSR::RD_MODE_STATUS_3,
+            4 => RD_MODE_STATUSR::RD_MODE_STATUS_4,
+            5 => RD_MODE_STATUSR::RD_MODE_STATUS_5,
+            9 => RD_MODE_STATUSR::RD_MODE_STATUS_9,
+            10 => RD_MODE_STATUSR::RD_MODE_STATUS_10,
+            i => RD_MODE_STATUSR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_STATUS_0`"]
+    #[inline]
+    pub fn is_rd_mode_status_0(&self) -> bool {
+        *self == RD_MODE_STATUSR::RD_MODE_STATUS_0
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_STATUS_1`"]
+    #[inline]
+    pub fn is_rd_mode_status_1(&self) -> bool {
+        *self == RD_MODE_STATUSR::RD_MODE_STATUS_1
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_STATUS_2`"]
+    #[inline]
+    pub fn is_rd_mode_status_2(&self) -> bool {
+        *self == RD_MODE_STATUSR::RD_MODE_STATUS_2
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_STATUS_3`"]
+    #[inline]
+    pub fn is_rd_mode_status_3(&self) -> bool {
+        *self == RD_MODE_STATUSR::RD_MODE_STATUS_3
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_STATUS_4`"]
+    #[inline]
+    pub fn is_rd_mode_status_4(&self) -> bool {
+        *self == RD_MODE_STATUSR::RD_MODE_STATUS_4
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_STATUS_5`"]
+    #[inline]
+    pub fn is_rd_mode_status_5(&self) -> bool {
+        *self == RD_MODE_STATUSR::RD_MODE_STATUS_5
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_STATUS_9`"]
+    #[inline]
+    pub fn is_rd_mode_status_9(&self) -> bool {
+        *self == RD_MODE_STATUSR::RD_MODE_STATUS_9
+    }
+    #[doc = "Checks if the value of the field is `RD_MODE_STATUS_10`"]
+    #[inline]
+    pub fn is_rd_mode_status_10(&self) -> bool {
+        *self == RD_MODE_STATUSR::RD_MODE_STATUS_10
+    }
+}
+#[doc = "Possible values of the field `WAIT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WAITR {
+    #[doc = "0 wait states"]
+    WAIT_0,
+    #[doc = "1 wait states"]
+    WAIT_1,
+    #[doc = "2 wait states"]
+    WAIT_2,
+    #[doc = "3 wait states"]
+    WAIT_3,
+    #[doc = "4 wait states"]
+    WAIT_4,
+    #[doc = "5 wait states"]
+    WAIT_5,
+    #[doc = "6 wait states"]
+    WAIT_6,
+    #[doc = "7 wait states"]
+    WAIT_7,
+    #[doc = "8 wait states"]
+    WAIT_8,
+    #[doc = "9 wait states"]
+    WAIT_9,
+    #[doc = "10 wait states"]
+    WAIT_10,
+    #[doc = "11 wait states"]
+    WAIT_11,
+    #[doc = "12 wait states"]
+    WAIT_12,
+    #[doc = "13 wait states"]
+    WAIT_13,
+    #[doc = "14 wait states"]
+    WAIT_14,
+    #[doc = "15 wait states"]
+    WAIT_15,
+}
+impl WAITR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            WAITR::WAIT_0 => 0,
+            WAITR::WAIT_1 => 1,
+            WAITR::WAIT_2 => 2,
+            WAITR::WAIT_3 => 3,
+            WAITR::WAIT_4 => 4,
+            WAITR::WAIT_5 => 5,
+            WAITR::WAIT_6 => 6,
+            WAITR::WAIT_7 => 7,
+            WAITR::WAIT_8 => 8,
+            WAITR::WAIT_9 => 9,
+            WAITR::WAIT_10 => 10,
+            WAITR::WAIT_11 => 11,
+            WAITR::WAIT_12 => 12,
+            WAITR::WAIT_13 => 13,
+            WAITR::WAIT_14 => 14,
+            WAITR::WAIT_15 => 15,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> WAITR {
+        match value {
+            0 => WAITR::WAIT_0,
+            1 => WAITR::WAIT_1,
+            2 => WAITR::WAIT_2,
+            3 => WAITR::WAIT_3,
+            4 => WAITR::WAIT_4,
+            5 => WAITR::WAIT_5,
+            6 => WAITR::WAIT_6,
+            7 => WAITR::WAIT_7,
+            8 => WAITR::WAIT_8,
+            9 => WAITR::WAIT_9,
+            10 => WAITR::WAIT_10,
+            11 => WAITR::WAIT_11,
+            12 => WAITR::WAIT_12,
+            13 => WAITR::WAIT_13,
+            14 => WAITR::WAIT_14,
+            15 => WAITR::WAIT_15,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `WAIT_0`"]
+    #[inline]
+    pub fn is_wait_0(&self) -> bool {
+        *self == WAITR::WAIT_0
+    }
+    #[doc = "Checks if the value of the field is `WAIT_1`"]
+    #[inline]
+    pub fn is_wait_1(&self) -> bool {
+        *self == WAITR::WAIT_1
+    }
+    #[doc = "Checks if the value of the field is `WAIT_2`"]
+    #[inline]
+    pub fn is_wait_2(&self) -> bool {
+        *self == WAITR::WAIT_2
+    }
+    #[doc = "Checks if the value of the field is `WAIT_3`"]
+    #[inline]
+    pub fn is_wait_3(&self) -> bool {
+        *self == WAITR::WAIT_3
+    }
+    #[doc = "Checks if the value of the field is `WAIT_4`"]
+    #[inline]
+    pub fn is_wait_4(&self) -> bool {
+        *self == WAITR::WAIT_4
+    }
+    #[doc = "Checks if the value of the field is `WAIT_5`"]
+    #[inline]
+    pub fn is_wait_5(&self) -> bool {
+        *self == WAITR::WAIT_5
+    }
+    #[doc = "Checks if the value of the field is `WAIT_6`"]
+    #[inline]
+    pub fn is_wait_6(&self) -> bool {
+        *self == WAITR::WAIT_6
+    }
+    #[doc = "Checks if the value of the field is `WAIT_7`"]
+    #[inline]
+    pub fn is_wait_7(&self) -> bool {
+        *self == WAITR::WAIT_7
+    }
+    #[doc = "Checks if the value of the field is `WAIT_8`"]
+    #[inline]
+    pub fn is_wait_8(&self) -> bool {
+        *self == WAITR::WAIT_8
+    }
+    #[doc = "Checks if the value of the field is `WAIT_9`"]
+    #[inline]
+    pub fn is_wait_9(&self) -> bool {
+        *self == WAITR::WAIT_9
+    }
+    #[doc = "Checks if the value of the field is `WAIT_10`"]
+    #[inline]
+    pub fn is_wait_10(&self) -> bool {
+        *self == WAITR::WAIT_10
+    }
+    #[doc = "Checks if the value of the field is `WAIT_11`"]
+    #[inline]
+    pub fn is_wait_11(&self) -> bool {
+        *self == WAITR::WAIT_11
+    }
+    #[doc = "Checks if the value of the field is `WAIT_12`"]
+    #[inline]
+    pub fn is_wait_12(&self) -> bool {
+        *self == WAITR::WAIT_12
+    }
+    #[doc = "Checks if the value of the field is `WAIT_13`"]
+    #[inline]
+    pub fn is_wait_13(&self) -> bool {
+        *self == WAITR::WAIT_13
+    }
+    #[doc = "Checks if the value of the field is `WAIT_14`"]
+    #[inline]
+    pub fn is_wait_14(&self) -> bool {
+        *self == WAITR::WAIT_14
+    }
+    #[doc = "Checks if the value of the field is `WAIT_15`"]
+    #[inline]
+    pub fn is_wait_15(&self) -> bool {
+        *self == WAITR::WAIT_15
+    }
+}
+#[doc = "Values that can be written to the field `RD_MODE`"]
+pub enum RD_MODEW {
+    #[doc = "Normal read mode"]
+    RD_MODE_0,
+    #[doc = "Read Margin 0"]
+    RD_MODE_1,
+    #[doc = "Read Margin 1"]
+    RD_MODE_2,
+    #[doc = "Program Verify"]
+    RD_MODE_3,
+    #[doc = "Erase Verify"]
+    RD_MODE_4,
+    #[doc = "Leakage Verify"]
+    RD_MODE_5,
+    #[doc = "Read Margin 0B"]
+    RD_MODE_9,
+    #[doc = "Read Margin 1B"]
+    RD_MODE_10,
+}
+impl RD_MODEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            RD_MODEW::RD_MODE_0 => 0,
+            RD_MODEW::RD_MODE_1 => 1,
+            RD_MODEW::RD_MODE_2 => 2,
+            RD_MODEW::RD_MODE_3 => 3,
+            RD_MODEW::RD_MODE_4 => 4,
+            RD_MODEW::RD_MODE_5 => 5,
+            RD_MODEW::RD_MODE_9 => 9,
+            RD_MODEW::RD_MODE_10 => 10,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RD_MODEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RD_MODEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: RD_MODEW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "Normal read mode"]
+    #[inline]
+    pub fn rd_mode_0(self) -> &'a mut W {
+        self.variant(RD_MODEW::RD_MODE_0)
+    }
+    #[doc = "Read Margin 0"]
+    #[inline]
+    pub fn rd_mode_1(self) -> &'a mut W {
+        self.variant(RD_MODEW::RD_MODE_1)
+    }
+    #[doc = "Read Margin 1"]
+    #[inline]
+    pub fn rd_mode_2(self) -> &'a mut W {
+        self.variant(RD_MODEW::RD_MODE_2)
+    }
+    #[doc = "Program Verify"]
+    #[inline]
+    pub fn rd_mode_3(self) -> &'a mut W {
+        self.variant(RD_MODEW::RD_MODE_3)
+    }
+    #[doc = "Erase Verify"]
+    #[inline]
+    pub fn rd_mode_4(self) -> &'a mut W {
+        self.variant(RD_MODEW::RD_MODE_4)
+    }
+    #[doc = "Leakage Verify"]
+    #[inline]
+    pub fn rd_mode_5(self) -> &'a mut W {
+        self.variant(RD_MODEW::RD_MODE_5)
+    }
+    #[doc = "Read Margin 0B"]
+    #[inline]
+    pub fn rd_mode_9(self) -> &'a mut W {
+        self.variant(RD_MODEW::RD_MODE_9)
+    }
+    #[doc = "Read Margin 1B"]
+    #[inline]
+    pub fn rd_mode_10(self) -> &'a mut W {
+        self.variant(RD_MODEW::RD_MODE_10)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _BUFIW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _BUFIW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _BUFDW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _BUFDW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `WAIT`"]
+pub enum WAITW {
+    #[doc = "0 wait states"]
+    WAIT_0,
+    #[doc = "1 wait states"]
+    WAIT_1,
+    #[doc = "2 wait states"]
+    WAIT_2,
+    #[doc = "3 wait states"]
+    WAIT_3,
+    #[doc = "4 wait states"]
+    WAIT_4,
+    #[doc = "5 wait states"]
+    WAIT_5,
+    #[doc = "6 wait states"]
+    WAIT_6,
+    #[doc = "7 wait states"]
+    WAIT_7,
+    #[doc = "8 wait states"]
+    WAIT_8,
+    #[doc = "9 wait states"]
+    WAIT_9,
+    #[doc = "10 wait states"]
+    WAIT_10,
+    #[doc = "11 wait states"]
+    WAIT_11,
+    #[doc = "12 wait states"]
+    WAIT_12,
+    #[doc = "13 wait states"]
+    WAIT_13,
+    #[doc = "14 wait states"]
+    WAIT_14,
+    #[doc = "15 wait states"]
+    WAIT_15,
+}
+impl WAITW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            WAITW::WAIT_0 => 0,
+            WAITW::WAIT_1 => 1,
+            WAITW::WAIT_2 => 2,
+            WAITW::WAIT_3 => 3,
+            WAITW::WAIT_4 => 4,
+            WAITW::WAIT_5 => 5,
+            WAITW::WAIT_6 => 6,
+            WAITW::WAIT_7 => 7,
+            WAITW::WAIT_8 => 8,
+            WAITW::WAIT_9 => 9,
+            WAITW::WAIT_10 => 10,
+            WAITW::WAIT_11 => 11,
+            WAITW::WAIT_12 => 12,
+            WAITW::WAIT_13 => 13,
+            WAITW::WAIT_14 => 14,
+            WAITW::WAIT_15 => 15,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _WAITW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _WAITW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: WAITW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "0 wait states"]
+    #[inline]
+    pub fn wait_0(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_0)
+    }
+    #[doc = "1 wait states"]
+    #[inline]
+    pub fn wait_1(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_1)
+    }
+    #[doc = "2 wait states"]
+    #[inline]
+    pub fn wait_2(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_2)
+    }
+    #[doc = "3 wait states"]
+    #[inline]
+    pub fn wait_3(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_3)
+    }
+    #[doc = "4 wait states"]
+    #[inline]
+    pub fn wait_4(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_4)
+    }
+    #[doc = "5 wait states"]
+    #[inline]
+    pub fn wait_5(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_5)
+    }
+    #[doc = "6 wait states"]
+    #[inline]
+    pub fn wait_6(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_6)
+    }
+    #[doc = "7 wait states"]
+    #[inline]
+    pub fn wait_7(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_7)
+    }
+    #[doc = "8 wait states"]
+    #[inline]
+    pub fn wait_8(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_8)
+    }
+    #[doc = "9 wait states"]
+    #[inline]
+    pub fn wait_9(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_9)
+    }
+    #[doc = "10 wait states"]
+    #[inline]
+    pub fn wait_10(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_10)
+    }
+    #[doc = "11 wait states"]
+    #[inline]
+    pub fn wait_11(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_11)
+    }
+    #[doc = "12 wait states"]
+    #[inline]
+    pub fn wait_12(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_12)
+    }
+    #[doc = "13 wait states"]
+    #[inline]
+    pub fn wait_13(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_13)
+    }
+    #[doc = "14 wait states"]
+    #[inline]
+    pub fn wait_14(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_14)
+    }
+    #[doc = "15 wait states"]
+    #[inline]
+    pub fn wait_15(self) -> &'a mut W {
+        self.variant(WAITW::WAIT_15)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:3 - Flash read mode control setting for Bank 0"]
+    #[inline]
+    pub fn rd_mode(&self) -> RD_MODER {
+        RD_MODER::_from({
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 4 - Enables read buffering feature for instruction fetches to this Bank"]
+    #[inline]
+    pub fn bufi(&self) -> BUFIR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        BUFIR { bits }
+    }
+    #[doc = "Bit 5 - Enables read buffering feature for data reads to this Bank"]
+    #[inline]
+    pub fn bufd(&self) -> BUFDR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        BUFDR { bits }
+    }
+    #[doc = "Bits 16:19 - Read mode"]
+    #[inline]
+    pub fn rd_mode_status(&self) -> RD_MODE_STATUSR {
+        RD_MODE_STATUSR::_from({
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 12:15 - Number of wait states for read"]
+    #[inline]
+    pub fn wait(&self) -> WAITR {
+        WAITR::_from({
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:3 - Flash read mode control setting for Bank 0"]
+    #[inline]
+    pub fn rd_mode(&mut self) -> _RD_MODEW {
+        _RD_MODEW { w: self }
+    }
+    #[doc = "Bit 4 - Enables read buffering feature for instruction fetches to this Bank"]
+    #[inline]
+    pub fn bufi(&mut self) -> _BUFIW {
+        _BUFIW { w: self }
+    }
+    #[doc = "Bit 5 - Enables read buffering feature for data reads to this Bank"]
+    #[inline]
+    pub fn bufd(&mut self) -> _BUFDW {
+        _BUFDW { w: self }
+    }
+    #[doc = "Bits 12:15 - Number of wait states for read"]
+    #[inline]
+    pub fn wait(&mut self) -> _WAITW {
+        _WAITW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_bmrk_cmp.rs b/example-source/msp432p401r/src/flctl/flctl_bmrk_cmp.rs
new file mode 100644
index 0000000..05865f6
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_bmrk_cmp.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_BMRK_CMP {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct COUNTR {
+    bits: u32,
+}
+impl COUNTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _COUNTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _COUNTW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Reflects the threshold value that is compared against either the IFETCH or DREAD Benchmark Counters"]
+    #[inline]
+    pub fn count(&self) -> COUNTR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        COUNTR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 65536 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Reflects the threshold value that is compared against either the IFETCH or DREAD Benchmark Counters"]
+    #[inline]
+    pub fn count(&mut self) -> _COUNTW {
+        _COUNTW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_bmrk_ctlstat.rs b/example-source/msp432p401r/src/flctl/flctl_bmrk_ctlstat.rs
new file mode 100644
index 0000000..a1ebf96
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_bmrk_ctlstat.rs
@@ -0,0 +1,360 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_BMRK_CTLSTAT {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct I_BMRKR {
+    bits: bool,
+}
+impl I_BMRKR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct D_BMRKR {
+    bits: bool,
+}
+impl D_BMRKR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CMP_ENR {
+    bits: bool,
+}
+impl CMP_ENR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `CMP_SEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CMP_SELR {
+    #[doc = "Compares the Instruction Benchmark Register against the threshold value"]
+    EN_1_0X0,
+    #[doc = "Compares the Data Benchmark Register against the threshold value"]
+    EN_2_0X1,
+}
+impl CMP_SELR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CMP_SELR::EN_1_0X0 => false,
+            CMP_SELR::EN_2_0X1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CMP_SELR {
+        match value {
+            false => CMP_SELR::EN_1_0X0,
+            true => CMP_SELR::EN_2_0X1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `EN_1_0X0`"]
+    #[inline]
+    pub fn is_en_1_0x0(&self) -> bool {
+        *self == CMP_SELR::EN_1_0X0
+    }
+    #[doc = "Checks if the value of the field is `EN_2_0X1`"]
+    #[inline]
+    pub fn is_en_2_0x1(&self) -> bool {
+        *self == CMP_SELR::EN_2_0X1
+    }
+}
+#[doc = r" Proxy"]
+pub struct _I_BMRKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _I_BMRKW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _D_BMRKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _D_BMRKW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CMP_ENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CMP_ENW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CMP_SEL`"]
+pub enum CMP_SELW {
+    #[doc = "Compares the Instruction Benchmark Register against the threshold value"]
+    EN_1_0X0,
+    #[doc = "Compares the Data Benchmark Register against the threshold value"]
+    EN_2_0X1,
+}
+impl CMP_SELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CMP_SELW::EN_1_0X0 => false,
+            CMP_SELW::EN_2_0X1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CMP_SELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CMP_SELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CMP_SELW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Compares the Instruction Benchmark Register against the threshold value"]
+    #[inline]
+    pub fn en_1_0x0(self) -> &'a mut W {
+        self.variant(CMP_SELW::EN_1_0X0)
+    }
+    #[doc = "Compares the Data Benchmark Register against the threshold value"]
+    #[inline]
+    pub fn en_2_0x1(self) -> &'a mut W {
+        self.variant(CMP_SELW::EN_2_0X1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - When 1, increments the Instruction Benchmark count register on each instruction fetch to the Flash"]
+    #[inline]
+    pub fn i_bmrk(&self) -> I_BMRKR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        I_BMRKR { bits }
+    }
+    #[doc = "Bit 1 - When 1, increments the Data Benchmark count register on each data read access to the Flash"]
+    #[inline]
+    pub fn d_bmrk(&self) -> D_BMRKR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        D_BMRKR { bits }
+    }
+    #[doc = "Bit 2 - When 1, enables comparison of the Instruction or Data Benchmark Registers against the threshold value"]
+    #[inline]
+    pub fn cmp_en(&self) -> CMP_ENR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CMP_ENR { bits }
+    }
+    #[doc = "Bit 3 - Selects which benchmark register should be compared against the threshold"]
+    #[inline]
+    pub fn cmp_sel(&self) -> CMP_SELR {
+        CMP_SELR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - When 1, increments the Instruction Benchmark count register on each instruction fetch to the Flash"]
+    #[inline]
+    pub fn i_bmrk(&mut self) -> _I_BMRKW {
+        _I_BMRKW { w: self }
+    }
+    #[doc = "Bit 1 - When 1, increments the Data Benchmark count register on each data read access to the Flash"]
+    #[inline]
+    pub fn d_bmrk(&mut self) -> _D_BMRKW {
+        _D_BMRKW { w: self }
+    }
+    #[doc = "Bit 2 - When 1, enables comparison of the Instruction or Data Benchmark Registers against the threshold value"]
+    #[inline]
+    pub fn cmp_en(&mut self) -> _CMP_ENW {
+        _CMP_ENW { w: self }
+    }
+    #[doc = "Bit 3 - Selects which benchmark register should be compared against the threshold"]
+    #[inline]
+    pub fn cmp_sel(&mut self) -> _CMP_SELW {
+        _CMP_SELW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_bmrk_dread.rs b/example-source/msp432p401r/src/flctl/flctl_bmrk_dread.rs
new file mode 100644
index 0000000..cdd94f3
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_bmrk_dread.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_BMRK_DREAD {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct COUNTR {
+    bits: u32,
+}
+impl COUNTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _COUNTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _COUNTW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Reflects the number of Data Read operations to the Flash (increments by one on each read)"]
+    #[inline]
+    pub fn count(&self) -> COUNTR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        COUNTR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Reflects the number of Data Read operations to the Flash (increments by one on each read)"]
+    #[inline]
+    pub fn count(&mut self) -> _COUNTW {
+        _COUNTW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_bmrk_ifetch.rs b/example-source/msp432p401r/src/flctl/flctl_bmrk_ifetch.rs
new file mode 100644
index 0000000..37ff1fc
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_bmrk_ifetch.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_BMRK_IFETCH {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct COUNTR {
+    bits: u32,
+}
+impl COUNTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _COUNTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _COUNTW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Reflects the number of Instruction Fetches to the Flash (increments by one on each fetch)"]
+    #[inline]
+    pub fn count(&self) -> COUNTR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        COUNTR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Reflects the number of Instruction Fetches to the Flash (increments by one on each fetch)"]
+    #[inline]
+    pub fn count(&mut self) -> _COUNTW {
+        _COUNTW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_burstprg_timctl.rs b/example-source/msp432p401r/src/flctl/flctl_burstprg_timctl.rs
new file mode 100644
index 0000000..0a7a130
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_burstprg_timctl.rs
@@ -0,0 +1,41 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::FLCTL_BURSTPRG_TIMCTL {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ACTIVER {
+    bits: u32,
+}
+impl ACTIVER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 8:27 - Length of the Active phase for this operation"]
+    #[inline]
+    pub fn active(&self) -> ACTIVER {
+        let bits = {
+            const MASK: u32 = 1048575;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        ACTIVER { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_clrifg.rs b/example-source/msp432p401r/src/flctl/flctl_clrifg.rs
new file mode 100644
index 0000000..df722ec
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_clrifg.rs
@@ -0,0 +1,253 @@
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_CLRIFG {
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RDBRSTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RDBRSTW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AVPREW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AVPREW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AVPSTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AVPSTW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PRGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PRGW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PRGBW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PRGBW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ERASEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ERASEW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _BMRKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _BMRKW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PRG_ERRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PRG_ERRW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn rdbrst(&mut self) -> _RDBRSTW {
+        _RDBRSTW { w: self }
+    }
+    #[doc = "Bit 1 - Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn avpre(&mut self) -> _AVPREW {
+        _AVPREW { w: self }
+    }
+    #[doc = "Bit 2 - Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn avpst(&mut self) -> _AVPSTW {
+        _AVPSTW { w: self }
+    }
+    #[doc = "Bit 3 - Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn prg(&mut self) -> _PRGW {
+        _PRGW { w: self }
+    }
+    #[doc = "Bit 4 - Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn prgb(&mut self) -> _PRGBW {
+        _PRGBW { w: self }
+    }
+    #[doc = "Bit 5 - Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn erase(&mut self) -> _ERASEW {
+        _ERASEW { w: self }
+    }
+    #[doc = "Bit 8 - Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn bmrk(&mut self) -> _BMRKW {
+        _BMRKW { w: self }
+    }
+    #[doc = "Bit 9 - Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn prg_err(&mut self) -> _PRG_ERRW {
+        _PRG_ERRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_erase_ctlstat.rs b/example-source/msp432p401r/src/flctl/flctl_erase_ctlstat.rs
new file mode 100644
index 0000000..fdad02a
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_erase_ctlstat.rs
@@ -0,0 +1,455 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_ERASE_CTLSTAT {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `MODE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum MODER {
+    #[doc = "Sector Erase (controlled by FLTCTL_ERASE_SECTADDR)"]
+    MODE_0,
+    #[doc = "Mass Erase (includes all Main and Information memory sectors that don't have corresponding WE bits set)"]
+    MODE_1,
+}
+impl MODER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            MODER::MODE_0 => false,
+            MODER::MODE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> MODER {
+        match value {
+            false => MODER::MODE_0,
+            true => MODER::MODE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `MODE_0`"]
+    #[inline]
+    pub fn is_mode_0(&self) -> bool {
+        *self == MODER::MODE_0
+    }
+    #[doc = "Checks if the value of the field is `MODE_1`"]
+    #[inline]
+    pub fn is_mode_1(&self) -> bool {
+        *self == MODER::MODE_1
+    }
+}
+#[doc = "Possible values of the field `TYPE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TYPER {
+    #[doc = "Main Memory"]
+    TYPE_0,
+    #[doc = "Information Memory"]
+    TYPE_1,
+    #[doc = "Engineering Memory"]
+    TYPE_3,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl TYPER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            TYPER::TYPE_0 => 0,
+            TYPER::TYPE_1 => 1,
+            TYPER::TYPE_3 => 3,
+            TYPER::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> TYPER {
+        match value {
+            0 => TYPER::TYPE_0,
+            1 => TYPER::TYPE_1,
+            3 => TYPER::TYPE_3,
+            i => TYPER::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `TYPE_0`"]
+    #[inline]
+    pub fn is_type_0(&self) -> bool {
+        *self == TYPER::TYPE_0
+    }
+    #[doc = "Checks if the value of the field is `TYPE_1`"]
+    #[inline]
+    pub fn is_type_1(&self) -> bool {
+        *self == TYPER::TYPE_1
+    }
+    #[doc = "Checks if the value of the field is `TYPE_3`"]
+    #[inline]
+    pub fn is_type_3(&self) -> bool {
+        *self == TYPER::TYPE_3
+    }
+}
+#[doc = "Possible values of the field `STATUS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum STATUSR {
+    #[doc = "Idle (no program operation currently active)"]
+    STATUS_0,
+    #[doc = "Erase operation triggered to START but pending"]
+    STATUS_1,
+    #[doc = "Erase operation in progress"]
+    STATUS_2,
+    #[doc = "Erase operation completed (status of completed erase remains in this state unless explicitly cleared by SW)"]
+    STATUS_3,
+}
+impl STATUSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            STATUSR::STATUS_0 => 0,
+            STATUSR::STATUS_1 => 1,
+            STATUSR::STATUS_2 => 2,
+            STATUSR::STATUS_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> STATUSR {
+        match value {
+            0 => STATUSR::STATUS_0,
+            1 => STATUSR::STATUS_1,
+            2 => STATUSR::STATUS_2,
+            3 => STATUSR::STATUS_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `STATUS_0`"]
+    #[inline]
+    pub fn is_status_0(&self) -> bool {
+        *self == STATUSR::STATUS_0
+    }
+    #[doc = "Checks if the value of the field is `STATUS_1`"]
+    #[inline]
+    pub fn is_status_1(&self) -> bool {
+        *self == STATUSR::STATUS_1
+    }
+    #[doc = "Checks if the value of the field is `STATUS_2`"]
+    #[inline]
+    pub fn is_status_2(&self) -> bool {
+        *self == STATUSR::STATUS_2
+    }
+    #[doc = "Checks if the value of the field is `STATUS_3`"]
+    #[inline]
+    pub fn is_status_3(&self) -> bool {
+        *self == STATUSR::STATUS_3
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ADDR_ERRR {
+    bits: bool,
+}
+impl ADDR_ERRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Proxy"]
+pub struct _STARTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _STARTW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `MODE`"]
+pub enum MODEW {
+    #[doc = "Sector Erase (controlled by FLTCTL_ERASE_SECTADDR)"]
+    MODE_0,
+    #[doc = "Mass Erase (includes all Main and Information memory sectors that don't have corresponding WE bits set)"]
+    MODE_1,
+}
+impl MODEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            MODEW::MODE_0 => false,
+            MODEW::MODE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MODEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MODEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: MODEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Sector Erase (controlled by FLTCTL_ERASE_SECTADDR)"]
+    #[inline]
+    pub fn mode_0(self) -> &'a mut W {
+        self.variant(MODEW::MODE_0)
+    }
+    #[doc = "Mass Erase (includes all Main and Information memory sectors that don't have corresponding WE bits set)"]
+    #[inline]
+    pub fn mode_1(self) -> &'a mut W {
+        self.variant(MODEW::MODE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TYPE`"]
+pub enum TYPEW {
+    #[doc = "Main Memory"]
+    TYPE_0,
+    #[doc = "Information Memory"]
+    TYPE_1,
+    #[doc = "Engineering Memory"]
+    TYPE_3,
+}
+impl TYPEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            TYPEW::TYPE_0 => 0,
+            TYPEW::TYPE_1 => 1,
+            TYPEW::TYPE_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TYPEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TYPEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TYPEW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "Main Memory"]
+    #[inline]
+    pub fn type_0(self) -> &'a mut W {
+        self.variant(TYPEW::TYPE_0)
+    }
+    #[doc = "Information Memory"]
+    #[inline]
+    pub fn type_1(self) -> &'a mut W {
+        self.variant(TYPEW::TYPE_1)
+    }
+    #[doc = "Engineering Memory"]
+    #[inline]
+    pub fn type_3(self) -> &'a mut W {
+        self.variant(TYPEW::TYPE_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLR_STATW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLR_STATW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 19;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 1 - Erase mode selected by application"]
+    #[inline]
+    pub fn mode(&self) -> MODER {
+        MODER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 2:3 - Type of memory that erase operation is carried out on"]
+    #[inline]
+    pub fn type_(&self) -> TYPER {
+        TYPER::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 16:17 - Status of erase operations in the Flash memory"]
+    #[inline]
+    pub fn status(&self) -> STATUSR {
+        STATUSR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 18 - Erase Operation was terminated due to attempted erase of reserved memory address"]
+    #[inline]
+    pub fn addr_err(&self) -> ADDR_ERRR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 18;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        ADDR_ERRR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Start of Erase operation"]
+    #[inline]
+    pub fn start(&mut self) -> _STARTW {
+        _STARTW { w: self }
+    }
+    #[doc = "Bit 1 - Erase mode selected by application"]
+    #[inline]
+    pub fn mode(&mut self) -> _MODEW {
+        _MODEW { w: self }
+    }
+    #[doc = "Bits 2:3 - Type of memory that erase operation is carried out on"]
+    #[inline]
+    pub fn type_(&mut self) -> _TYPEW {
+        _TYPEW { w: self }
+    }
+    #[doc = "Bit 19 - Clear status bits 18-16 of this register"]
+    #[inline]
+    pub fn clr_stat(&mut self) -> _CLR_STATW {
+        _CLR_STATW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_erase_sectaddr.rs b/example-source/msp432p401r/src/flctl/flctl_erase_sectaddr.rs
new file mode 100644
index 0000000..b6d8c60
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_erase_sectaddr.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_ERASE_SECTADDR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SECT_ADDRESSR {
+    bits: u32,
+}
+impl SECT_ADDRESSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SECT_ADDRESSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SECT_ADDRESSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4194303;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:21 - Address of Sector being Erased"]
+    #[inline]
+    pub fn sect_address(&self) -> SECT_ADDRESSR {
+        let bits = {
+            const MASK: u32 = 4194303;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        SECT_ADDRESSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:21 - Address of Sector being Erased"]
+    #[inline]
+    pub fn sect_address(&mut self) -> _SECT_ADDRESSW {
+        _SECT_ADDRESSW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_erase_timctl.rs b/example-source/msp432p401r/src/flctl/flctl_erase_timctl.rs
new file mode 100644
index 0000000..3d20ab9
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_erase_timctl.rs
@@ -0,0 +1,83 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::FLCTL_ERASE_TIMCTL {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SETUPR {
+    bits: u8,
+}
+impl SETUPR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ACTIVER {
+    bits: u32,
+}
+impl ACTIVER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct HOLDR {
+    bits: u8,
+}
+impl HOLDR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Length of the Setup phase for this operation"]
+    #[inline]
+    pub fn setup(&self) -> SETUPR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        SETUPR { bits }
+    }
+    #[doc = "Bits 8:27 - Length of the Active phase for this operation"]
+    #[inline]
+    pub fn active(&self) -> ACTIVER {
+        let bits = {
+            const MASK: u32 = 1048575;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        ACTIVER { bits }
+    }
+    #[doc = "Bits 28:31 - Length of the Hold phase for this operation"]
+    #[inline]
+    pub fn hold(&self) -> HOLDR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 28;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        HOLDR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_ersver_timctl.rs b/example-source/msp432p401r/src/flctl/flctl_ersver_timctl.rs
new file mode 100644
index 0000000..313aa8b
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_ersver_timctl.rs
@@ -0,0 +1,41 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::FLCTL_ERSVER_TIMCTL {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SETUPR {
+    bits: u8,
+}
+impl SETUPR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Length of the Setup phase for this operation"]
+    #[inline]
+    pub fn setup(&self) -> SETUPR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        SETUPR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_ie.rs b/example-source/msp432p401r/src/flctl/flctl_ie.rs
new file mode 100644
index 0000000..5cc6b9c
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_ie.rs
@@ -0,0 +1,536 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_IE {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct RDBRSTR {
+    bits: bool,
+}
+impl RDBRSTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct AVPRER {
+    bits: bool,
+}
+impl AVPRER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct AVPSTR {
+    bits: bool,
+}
+impl AVPSTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PRGR {
+    bits: bool,
+}
+impl PRGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PRGBR {
+    bits: bool,
+}
+impl PRGBR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ERASER {
+    bits: bool,
+}
+impl ERASER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct BMRKR {
+    bits: bool,
+}
+impl BMRKR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PRG_ERRR {
+    bits: bool,
+}
+impl PRG_ERRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RDBRSTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RDBRSTW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AVPREW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AVPREW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AVPSTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AVPSTW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PRGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PRGW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PRGBW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PRGBW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ERASEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ERASEW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _BMRKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _BMRKW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PRG_ERRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PRG_ERRW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn rdbrst(&self) -> RDBRSTR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        RDBRSTR { bits }
+    }
+    #[doc = "Bit 1 - If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn avpre(&self) -> AVPRER {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        AVPRER { bits }
+    }
+    #[doc = "Bit 2 - If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn avpst(&self) -> AVPSTR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        AVPSTR { bits }
+    }
+    #[doc = "Bit 3 - If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn prg(&self) -> PRGR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PRGR { bits }
+    }
+    #[doc = "Bit 4 - If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn prgb(&self) -> PRGBR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PRGBR { bits }
+    }
+    #[doc = "Bit 5 - If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn erase(&self) -> ERASER {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        ERASER { bits }
+    }
+    #[doc = "Bit 8 - If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn bmrk(&self) -> BMRKR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        BMRKR { bits }
+    }
+    #[doc = "Bit 9 - If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn prg_err(&self) -> PRG_ERRR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PRG_ERRR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn rdbrst(&mut self) -> _RDBRSTW {
+        _RDBRSTW { w: self }
+    }
+    #[doc = "Bit 1 - If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn avpre(&mut self) -> _AVPREW {
+        _AVPREW { w: self }
+    }
+    #[doc = "Bit 2 - If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn avpst(&mut self) -> _AVPSTW {
+        _AVPSTW { w: self }
+    }
+    #[doc = "Bit 3 - If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn prg(&mut self) -> _PRGW {
+        _PRGW { w: self }
+    }
+    #[doc = "Bit 4 - If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn prgb(&mut self) -> _PRGBW {
+        _PRGBW { w: self }
+    }
+    #[doc = "Bit 5 - If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn erase(&mut self) -> _ERASEW {
+        _ERASEW { w: self }
+    }
+    #[doc = "Bit 8 - If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn bmrk(&mut self) -> _BMRKW {
+        _BMRKW { w: self }
+    }
+    #[doc = "Bit 9 - If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn prg_err(&mut self) -> _PRG_ERRW {
+        _PRG_ERRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_ifg.rs b/example-source/msp432p401r/src/flctl/flctl_ifg.rs
new file mode 100644
index 0000000..3c6d6d6
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_ifg.rs
@@ -0,0 +1,268 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::FLCTL_IFG {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct RDBRSTR {
+    bits: bool,
+}
+impl RDBRSTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct AVPRER {
+    bits: bool,
+}
+impl AVPRER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct AVPSTR {
+    bits: bool,
+}
+impl AVPSTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PRGR {
+    bits: bool,
+}
+impl PRGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PRGBR {
+    bits: bool,
+}
+impl PRGBR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ERASER {
+    bits: bool,
+}
+impl ERASER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct BMRKR {
+    bits: bool,
+}
+impl BMRKR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PRG_ERRR {
+    bits: bool,
+}
+impl PRG_ERRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - If set to 1, indicates that the Read Burst/Compare operation is complete"]
+    #[inline]
+    pub fn rdbrst(&self) -> RDBRSTR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        RDBRSTR { bits }
+    }
+    #[doc = "Bit 1 - If set to 1, indicates that the pre-program verify operation has detected an error"]
+    #[inline]
+    pub fn avpre(&self) -> AVPRER {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        AVPRER { bits }
+    }
+    #[doc = "Bit 2 - If set to 1, indicates that the post-program verify operation has failed comparison"]
+    #[inline]
+    pub fn avpst(&self) -> AVPSTR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        AVPSTR { bits }
+    }
+    #[doc = "Bit 3 - If set to 1, indicates that a word Program operation is complete"]
+    #[inline]
+    pub fn prg(&self) -> PRGR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PRGR { bits }
+    }
+    #[doc = "Bit 4 - If set to 1, indicates that the configured Burst Program operation is complete"]
+    #[inline]
+    pub fn prgb(&self) -> PRGBR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PRGBR { bits }
+    }
+    #[doc = "Bit 5 - If set to 1, indicates that the Erase operation is complete"]
+    #[inline]
+    pub fn erase(&self) -> ERASER {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        ERASER { bits }
+    }
+    #[doc = "Bit 8 - If set to 1, indicates that a Benchmark Compare match occurred"]
+    #[inline]
+    pub fn bmrk(&self) -> BMRKR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        BMRKR { bits }
+    }
+    #[doc = "Bit 9 - If set to 1, indicates a word composition error in full word write mode (possible data loss due to writes crossing over to a new 128bit boundary before full word has been composed)"]
+    #[inline]
+    pub fn prg_err(&self) -> PRG_ERRR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PRG_ERRR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_lkgver_timctl.rs b/example-source/msp432p401r/src/flctl/flctl_lkgver_timctl.rs
new file mode 100644
index 0000000..448bc6c
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_lkgver_timctl.rs
@@ -0,0 +1,41 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::FLCTL_LKGVER_TIMCTL {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SETUPR {
+    bits: u8,
+}
+impl SETUPR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Length of the Setup phase for this operation"]
+    #[inline]
+    pub fn setup(&self) -> SETUPR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        SETUPR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_masserase_timctl.rs b/example-source/msp432p401r/src/flctl/flctl_masserase_timctl.rs
new file mode 100644
index 0000000..e571fa8
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_masserase_timctl.rs
@@ -0,0 +1,62 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::FLCTL_MASSERASE_TIMCTL {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct BOOST_ACTIVER {
+    bits: u8,
+}
+impl BOOST_ACTIVER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct BOOST_HOLDR {
+    bits: u8,
+}
+impl BOOST_HOLDR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Length of the time for which LDO Boost Signal is kept active"]
+    #[inline]
+    pub fn boost_active(&self) -> BOOST_ACTIVER {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        BOOST_ACTIVER { bits }
+    }
+    #[doc = "Bits 8:15 - Length for which Flash deactivates the LDO Boost signal before processing any new commands"]
+    #[inline]
+    pub fn boost_hold(&self) -> BOOST_HOLDR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        BOOST_HOLDR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_power_stat.rs b/example-source/msp432p401r/src/flctl/flctl_power_stat.rs
new file mode 100644
index 0000000..d7a4565
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_power_stat.rs
@@ -0,0 +1,401 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::FLCTL_POWER_STAT {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `PSTAT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PSTATR {
+    #[doc = "Flash IP in power-down mode"]
+    PSTAT_0,
+    #[doc = "Flash IP Vdd domain power-up in progress"]
+    PSTAT_1,
+    #[doc = "PSS LDO_GOOD, IREF_OK and VREF_OK check in progress"]
+    PSTAT_2,
+    #[doc = "Flash IP SAFE_LV check in progress"]
+    PSTAT_3,
+    #[doc = "Flash IP Active"]
+    PSTAT_4,
+    #[doc = "Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes."]
+    PSTAT_5,
+    #[doc = "Flash IP in Standby mode"]
+    PSTAT_6,
+    #[doc = "Flash IP in Current mirror boost state"]
+    PSTAT_7,
+}
+impl PSTATR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            PSTATR::PSTAT_0 => 0,
+            PSTATR::PSTAT_1 => 1,
+            PSTATR::PSTAT_2 => 2,
+            PSTATR::PSTAT_3 => 3,
+            PSTATR::PSTAT_4 => 4,
+            PSTATR::PSTAT_5 => 5,
+            PSTATR::PSTAT_6 => 6,
+            PSTATR::PSTAT_7 => 7,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> PSTATR {
+        match value {
+            0 => PSTATR::PSTAT_0,
+            1 => PSTATR::PSTAT_1,
+            2 => PSTATR::PSTAT_2,
+            3 => PSTATR::PSTAT_3,
+            4 => PSTATR::PSTAT_4,
+            5 => PSTATR::PSTAT_5,
+            6 => PSTATR::PSTAT_6,
+            7 => PSTATR::PSTAT_7,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `PSTAT_0`"]
+    #[inline]
+    pub fn is_pstat_0(&self) -> bool {
+        *self == PSTATR::PSTAT_0
+    }
+    #[doc = "Checks if the value of the field is `PSTAT_1`"]
+    #[inline]
+    pub fn is_pstat_1(&self) -> bool {
+        *self == PSTATR::PSTAT_1
+    }
+    #[doc = "Checks if the value of the field is `PSTAT_2`"]
+    #[inline]
+    pub fn is_pstat_2(&self) -> bool {
+        *self == PSTATR::PSTAT_2
+    }
+    #[doc = "Checks if the value of the field is `PSTAT_3`"]
+    #[inline]
+    pub fn is_pstat_3(&self) -> bool {
+        *self == PSTATR::PSTAT_3
+    }
+    #[doc = "Checks if the value of the field is `PSTAT_4`"]
+    #[inline]
+    pub fn is_pstat_4(&self) -> bool {
+        *self == PSTATR::PSTAT_4
+    }
+    #[doc = "Checks if the value of the field is `PSTAT_5`"]
+    #[inline]
+    pub fn is_pstat_5(&self) -> bool {
+        *self == PSTATR::PSTAT_5
+    }
+    #[doc = "Checks if the value of the field is `PSTAT_6`"]
+    #[inline]
+    pub fn is_pstat_6(&self) -> bool {
+        *self == PSTATR::PSTAT_6
+    }
+    #[doc = "Checks if the value of the field is `PSTAT_7`"]
+    #[inline]
+    pub fn is_pstat_7(&self) -> bool {
+        *self == PSTATR::PSTAT_7
+    }
+}
+#[doc = "Possible values of the field `LDOSTAT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LDOSTATR {
+    #[doc = "FLDO not GOOD"]
+    LDOSTAT_0,
+    #[doc = "FLDO GOOD"]
+    LDOSTAT_1,
+}
+impl LDOSTATR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            LDOSTATR::LDOSTAT_0 => false,
+            LDOSTATR::LDOSTAT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> LDOSTATR {
+        match value {
+            false => LDOSTATR::LDOSTAT_0,
+            true => LDOSTATR::LDOSTAT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `LDOSTAT_0`"]
+    #[inline]
+    pub fn is_ldostat_0(&self) -> bool {
+        *self == LDOSTATR::LDOSTAT_0
+    }
+    #[doc = "Checks if the value of the field is `LDOSTAT_1`"]
+    #[inline]
+    pub fn is_ldostat_1(&self) -> bool {
+        *self == LDOSTATR::LDOSTAT_1
+    }
+}
+#[doc = "Possible values of the field `VREFSTAT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum VREFSTATR {
+    #[doc = "Flash LDO not stable"]
+    VREFSTAT_0,
+    #[doc = "Flash LDO stable"]
+    VREFSTAT_1,
+}
+impl VREFSTATR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            VREFSTATR::VREFSTAT_0 => false,
+            VREFSTATR::VREFSTAT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> VREFSTATR {
+        match value {
+            false => VREFSTATR::VREFSTAT_0,
+            true => VREFSTATR::VREFSTAT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `VREFSTAT_0`"]
+    #[inline]
+    pub fn is_vrefstat_0(&self) -> bool {
+        *self == VREFSTATR::VREFSTAT_0
+    }
+    #[doc = "Checks if the value of the field is `VREFSTAT_1`"]
+    #[inline]
+    pub fn is_vrefstat_1(&self) -> bool {
+        *self == VREFSTATR::VREFSTAT_1
+    }
+}
+#[doc = "Possible values of the field `IREFSTAT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IREFSTATR {
+    #[doc = "IREF not stable"]
+    IREFSTAT_0,
+    #[doc = "IREF stable"]
+    IREFSTAT_1,
+}
+impl IREFSTATR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            IREFSTATR::IREFSTAT_0 => false,
+            IREFSTATR::IREFSTAT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> IREFSTATR {
+        match value {
+            false => IREFSTATR::IREFSTAT_0,
+            true => IREFSTATR::IREFSTAT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `IREFSTAT_0`"]
+    #[inline]
+    pub fn is_irefstat_0(&self) -> bool {
+        *self == IREFSTATR::IREFSTAT_0
+    }
+    #[doc = "Checks if the value of the field is `IREFSTAT_1`"]
+    #[inline]
+    pub fn is_irefstat_1(&self) -> bool {
+        *self == IREFSTATR::IREFSTAT_1
+    }
+}
+#[doc = "Possible values of the field `TRIMSTAT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TRIMSTATR {
+    #[doc = "PSS trim not complete"]
+    TRIMSTAT_0,
+    #[doc = "PSS trim complete"]
+    TRIMSTAT_1,
+}
+impl TRIMSTATR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TRIMSTATR::TRIMSTAT_0 => false,
+            TRIMSTATR::TRIMSTAT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TRIMSTATR {
+        match value {
+            false => TRIMSTATR::TRIMSTAT_0,
+            true => TRIMSTATR::TRIMSTAT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `TRIMSTAT_0`"]
+    #[inline]
+    pub fn is_trimstat_0(&self) -> bool {
+        *self == TRIMSTATR::TRIMSTAT_0
+    }
+    #[doc = "Checks if the value of the field is `TRIMSTAT_1`"]
+    #[inline]
+    pub fn is_trimstat_1(&self) -> bool {
+        *self == TRIMSTATR::TRIMSTAT_1
+    }
+}
+#[doc = "Possible values of the field `RD_2T`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RD_2TR {
+    #[doc = "Flash reads are in 1T mode"]
+    RD_2T_0,
+    #[doc = "Flash reads are in 2T mode"]
+    RD_2T_1,
+}
+impl RD_2TR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            RD_2TR::RD_2T_0 => false,
+            RD_2TR::RD_2T_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> RD_2TR {
+        match value {
+            false => RD_2TR::RD_2T_0,
+            true => RD_2TR::RD_2T_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RD_2T_0`"]
+    #[inline]
+    pub fn is_rd_2t_0(&self) -> bool {
+        *self == RD_2TR::RD_2T_0
+    }
+    #[doc = "Checks if the value of the field is `RD_2T_1`"]
+    #[inline]
+    pub fn is_rd_2t_1(&self) -> bool {
+        *self == RD_2TR::RD_2T_1
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:2 - Flash power status"]
+    #[inline]
+    pub fn pstat(&self) -> PSTATR {
+        PSTATR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 3 - PSS FLDO GOOD status"]
+    #[inline]
+    pub fn ldostat(&self) -> LDOSTATR {
+        LDOSTATR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 4 - PSS VREF stable status"]
+    #[inline]
+    pub fn vrefstat(&self) -> VREFSTATR {
+        VREFSTATR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 5 - PSS IREF stable status"]
+    #[inline]
+    pub fn irefstat(&self) -> IREFSTATR {
+        IREFSTATR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 6 - PSS trim done status"]
+    #[inline]
+    pub fn trimstat(&self) -> TRIMSTATR {
+        TRIMSTATR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 7 - Indicates if Flash is being accessed in 2T mode"]
+    #[inline]
+    pub fn rd_2t(&self) -> RD_2TR {
+        RD_2TR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_prg_ctlstat.rs b/example-source/msp432p401r/src/flctl/flctl_prg_ctlstat.rs
new file mode 100644
index 0000000..a403f95
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_prg_ctlstat.rs
@@ -0,0 +1,655 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_PRG_CTLSTAT {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `ENABLE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ENABLER {
+    #[doc = "Word program operation disabled"]
+    ENABLE_0,
+    #[doc = "Word program operation enabled"]
+    ENABLE_1,
+}
+impl ENABLER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ENABLER::ENABLE_0 => false,
+            ENABLER::ENABLE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ENABLER {
+        match value {
+            false => ENABLER::ENABLE_0,
+            true => ENABLER::ENABLE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ENABLE_0`"]
+    #[inline]
+    pub fn is_enable_0(&self) -> bool {
+        *self == ENABLER::ENABLE_0
+    }
+    #[doc = "Checks if the value of the field is `ENABLE_1`"]
+    #[inline]
+    pub fn is_enable_1(&self) -> bool {
+        *self == ENABLER::ENABLE_1
+    }
+}
+#[doc = "Possible values of the field `MODE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum MODER {
+    #[doc = "Write immediate mode. Starts program operation immediately on each write to the Flash"]
+    MODE_0,
+    #[doc = "Full word write mode. Flash controller collates data over multiple writes to compose the full 128bit word before initiating the program operation"]
+    MODE_1,
+}
+impl MODER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            MODER::MODE_0 => false,
+            MODER::MODE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> MODER {
+        match value {
+            false => MODER::MODE_0,
+            true => MODER::MODE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `MODE_0`"]
+    #[inline]
+    pub fn is_mode_0(&self) -> bool {
+        *self == MODER::MODE_0
+    }
+    #[doc = "Checks if the value of the field is `MODE_1`"]
+    #[inline]
+    pub fn is_mode_1(&self) -> bool {
+        *self == MODER::MODE_1
+    }
+}
+#[doc = "Possible values of the field `VER_PRE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum VER_PRER {
+    #[doc = "No pre program verification"]
+    VER_PRE_0,
+    #[doc = "Pre verify feature automatically invoked for each write operation (irrespective of the mode)"]
+    VER_PRE_1,
+}
+impl VER_PRER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            VER_PRER::VER_PRE_0 => false,
+            VER_PRER::VER_PRE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> VER_PRER {
+        match value {
+            false => VER_PRER::VER_PRE_0,
+            true => VER_PRER::VER_PRE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `VER_PRE_0`"]
+    #[inline]
+    pub fn is_ver_pre_0(&self) -> bool {
+        *self == VER_PRER::VER_PRE_0
+    }
+    #[doc = "Checks if the value of the field is `VER_PRE_1`"]
+    #[inline]
+    pub fn is_ver_pre_1(&self) -> bool {
+        *self == VER_PRER::VER_PRE_1
+    }
+}
+#[doc = "Possible values of the field `VER_PST`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum VER_PSTR {
+    #[doc = "No post program verification"]
+    VER_PST_0,
+    #[doc = "Post verify feature automatically invoked for each write operation (irrespective of the mode)"]
+    VER_PST_1,
+}
+impl VER_PSTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            VER_PSTR::VER_PST_0 => false,
+            VER_PSTR::VER_PST_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> VER_PSTR {
+        match value {
+            false => VER_PSTR::VER_PST_0,
+            true => VER_PSTR::VER_PST_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `VER_PST_0`"]
+    #[inline]
+    pub fn is_ver_pst_0(&self) -> bool {
+        *self == VER_PSTR::VER_PST_0
+    }
+    #[doc = "Checks if the value of the field is `VER_PST_1`"]
+    #[inline]
+    pub fn is_ver_pst_1(&self) -> bool {
+        *self == VER_PSTR::VER_PST_1
+    }
+}
+#[doc = "Possible values of the field `STATUS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum STATUSR {
+    #[doc = "Idle (no program operation currently active)"]
+    STATUS_0,
+    #[doc = "Single word program operation triggered, but pending"]
+    STATUS_1,
+    #[doc = "Single word program in progress"]
+    STATUS_2,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl STATUSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            STATUSR::STATUS_0 => 0,
+            STATUSR::STATUS_1 => 1,
+            STATUSR::STATUS_2 => 2,
+            STATUSR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> STATUSR {
+        match value {
+            0 => STATUSR::STATUS_0,
+            1 => STATUSR::STATUS_1,
+            2 => STATUSR::STATUS_2,
+            i => STATUSR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `STATUS_0`"]
+    #[inline]
+    pub fn is_status_0(&self) -> bool {
+        *self == STATUSR::STATUS_0
+    }
+    #[doc = "Checks if the value of the field is `STATUS_1`"]
+    #[inline]
+    pub fn is_status_1(&self) -> bool {
+        *self == STATUSR::STATUS_1
+    }
+    #[doc = "Checks if the value of the field is `STATUS_2`"]
+    #[inline]
+    pub fn is_status_2(&self) -> bool {
+        *self == STATUSR::STATUS_2
+    }
+}
+#[doc = "Possible values of the field `BNK_ACT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum BNK_ACTR {
+    #[doc = "Word in Bank0 being programmed"]
+    BNK_ACT_0,
+    #[doc = "Word in Bank1 being programmed"]
+    BNK_ACT_1,
+}
+impl BNK_ACTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            BNK_ACTR::BNK_ACT_0 => false,
+            BNK_ACTR::BNK_ACT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> BNK_ACTR {
+        match value {
+            false => BNK_ACTR::BNK_ACT_0,
+            true => BNK_ACTR::BNK_ACT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `BNK_ACT_0`"]
+    #[inline]
+    pub fn is_bnk_act_0(&self) -> bool {
+        *self == BNK_ACTR::BNK_ACT_0
+    }
+    #[doc = "Checks if the value of the field is `BNK_ACT_1`"]
+    #[inline]
+    pub fn is_bnk_act_1(&self) -> bool {
+        *self == BNK_ACTR::BNK_ACT_1
+    }
+}
+#[doc = "Values that can be written to the field `ENABLE`"]
+pub enum ENABLEW {
+    #[doc = "Word program operation disabled"]
+    ENABLE_0,
+    #[doc = "Word program operation enabled"]
+    ENABLE_1,
+}
+impl ENABLEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ENABLEW::ENABLE_0 => false,
+            ENABLEW::ENABLE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ENABLEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ENABLEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ENABLEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Word program operation disabled"]
+    #[inline]
+    pub fn enable_0(self) -> &'a mut W {
+        self.variant(ENABLEW::ENABLE_0)
+    }
+    #[doc = "Word program operation enabled"]
+    #[inline]
+    pub fn enable_1(self) -> &'a mut W {
+        self.variant(ENABLEW::ENABLE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `MODE`"]
+pub enum MODEW {
+    #[doc = "Write immediate mode. Starts program operation immediately on each write to the Flash"]
+    MODE_0,
+    #[doc = "Full word write mode. Flash controller collates data over multiple writes to compose the full 128bit word before initiating the program operation"]
+    MODE_1,
+}
+impl MODEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            MODEW::MODE_0 => false,
+            MODEW::MODE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MODEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MODEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: MODEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Write immediate mode. Starts program operation immediately on each write to the Flash"]
+    #[inline]
+    pub fn mode_0(self) -> &'a mut W {
+        self.variant(MODEW::MODE_0)
+    }
+    #[doc = "Full word write mode. Flash controller collates data over multiple writes to compose the full 128bit word before initiating the program operation"]
+    #[inline]
+    pub fn mode_1(self) -> &'a mut W {
+        self.variant(MODEW::MODE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `VER_PRE`"]
+pub enum VER_PREW {
+    #[doc = "No pre program verification"]
+    VER_PRE_0,
+    #[doc = "Pre verify feature automatically invoked for each write operation (irrespective of the mode)"]
+    VER_PRE_1,
+}
+impl VER_PREW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            VER_PREW::VER_PRE_0 => false,
+            VER_PREW::VER_PRE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _VER_PREW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _VER_PREW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: VER_PREW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No pre program verification"]
+    #[inline]
+    pub fn ver_pre_0(self) -> &'a mut W {
+        self.variant(VER_PREW::VER_PRE_0)
+    }
+    #[doc = "Pre verify feature automatically invoked for each write operation (irrespective of the mode)"]
+    #[inline]
+    pub fn ver_pre_1(self) -> &'a mut W {
+        self.variant(VER_PREW::VER_PRE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `VER_PST`"]
+pub enum VER_PSTW {
+    #[doc = "No post program verification"]
+    VER_PST_0,
+    #[doc = "Post verify feature automatically invoked for each write operation (irrespective of the mode)"]
+    VER_PST_1,
+}
+impl VER_PSTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            VER_PSTW::VER_PST_0 => false,
+            VER_PSTW::VER_PST_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _VER_PSTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _VER_PSTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: VER_PSTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No post program verification"]
+    #[inline]
+    pub fn ver_pst_0(self) -> &'a mut W {
+        self.variant(VER_PSTW::VER_PST_0)
+    }
+    #[doc = "Post verify feature automatically invoked for each write operation (irrespective of the mode)"]
+    #[inline]
+    pub fn ver_pst_1(self) -> &'a mut W {
+        self.variant(VER_PSTW::VER_PST_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Master control for all word program operations"]
+    #[inline]
+    pub fn enable(&self) -> ENABLER {
+        ENABLER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - Write mode"]
+    #[inline]
+    pub fn mode(&self) -> MODER {
+        MODER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - Controls automatic pre program verify operations"]
+    #[inline]
+    pub fn ver_pre(&self) -> VER_PRER {
+        VER_PRER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 3 - Controls automatic post program verify operations"]
+    #[inline]
+    pub fn ver_pst(&self) -> VER_PSTR {
+        VER_PSTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 16:17 - Status of program operations in the Flash memory"]
+    #[inline]
+    pub fn status(&self) -> STATUSR {
+        STATUSR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 18 - Bank active"]
+    #[inline]
+    pub fn bnk_act(&self) -> BNK_ACTR {
+        BNK_ACTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 18;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 12 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Master control for all word program operations"]
+    #[inline]
+    pub fn enable(&mut self) -> _ENABLEW {
+        _ENABLEW { w: self }
+    }
+    #[doc = "Bit 1 - Write mode"]
+    #[inline]
+    pub fn mode(&mut self) -> _MODEW {
+        _MODEW { w: self }
+    }
+    #[doc = "Bit 2 - Controls automatic pre program verify operations"]
+    #[inline]
+    pub fn ver_pre(&mut self) -> _VER_PREW {
+        _VER_PREW { w: self }
+    }
+    #[doc = "Bit 3 - Controls automatic post program verify operations"]
+    #[inline]
+    pub fn ver_pst(&mut self) -> _VER_PSTW {
+        _VER_PSTW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_prgbrst_ctlstat.rs b/example-source/msp432p401r/src/flctl/flctl_prgbrst_ctlstat.rs
new file mode 100644
index 0000000..9fd7d2c
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_prgbrst_ctlstat.rs
@@ -0,0 +1,820 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_PRGBRST_CTLSTAT {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `TYPE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TYPER {
+    #[doc = "Main Memory"]
+    TYPE_0,
+    #[doc = "Information Memory"]
+    TYPE_1,
+    #[doc = "Engineering Memory"]
+    TYPE_3,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl TYPER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            TYPER::TYPE_0 => 0,
+            TYPER::TYPE_1 => 1,
+            TYPER::TYPE_3 => 3,
+            TYPER::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> TYPER {
+        match value {
+            0 => TYPER::TYPE_0,
+            1 => TYPER::TYPE_1,
+            3 => TYPER::TYPE_3,
+            i => TYPER::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `TYPE_0`"]
+    #[inline]
+    pub fn is_type_0(&self) -> bool {
+        *self == TYPER::TYPE_0
+    }
+    #[doc = "Checks if the value of the field is `TYPE_1`"]
+    #[inline]
+    pub fn is_type_1(&self) -> bool {
+        *self == TYPER::TYPE_1
+    }
+    #[doc = "Checks if the value of the field is `TYPE_3`"]
+    #[inline]
+    pub fn is_type_3(&self) -> bool {
+        *self == TYPER::TYPE_3
+    }
+}
+#[doc = "Possible values of the field `LEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LENR {
+    #[doc = "No burst operation"]
+    LEN_0,
+    #[doc = "1 word burst of 128 bits, starting with address in the FLCTL_PRGBRST_STARTADDR Register"]
+    LEN_1,
+    #[doc = "2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register"]
+    LEN_2,
+    #[doc = "3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register"]
+    LEN_3,
+    #[doc = "4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register"]
+    LEN_4,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl LENR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            LENR::LEN_0 => 0,
+            LENR::LEN_1 => 1,
+            LENR::LEN_2 => 2,
+            LENR::LEN_3 => 3,
+            LENR::LEN_4 => 4,
+            LENR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> LENR {
+        match value {
+            0 => LENR::LEN_0,
+            1 => LENR::LEN_1,
+            2 => LENR::LEN_2,
+            3 => LENR::LEN_3,
+            4 => LENR::LEN_4,
+            i => LENR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `LEN_0`"]
+    #[inline]
+    pub fn is_len_0(&self) -> bool {
+        *self == LENR::LEN_0
+    }
+    #[doc = "Checks if the value of the field is `LEN_1`"]
+    #[inline]
+    pub fn is_len_1(&self) -> bool {
+        *self == LENR::LEN_1
+    }
+    #[doc = "Checks if the value of the field is `LEN_2`"]
+    #[inline]
+    pub fn is_len_2(&self) -> bool {
+        *self == LENR::LEN_2
+    }
+    #[doc = "Checks if the value of the field is `LEN_3`"]
+    #[inline]
+    pub fn is_len_3(&self) -> bool {
+        *self == LENR::LEN_3
+    }
+    #[doc = "Checks if the value of the field is `LEN_4`"]
+    #[inline]
+    pub fn is_len_4(&self) -> bool {
+        *self == LENR::LEN_4
+    }
+}
+#[doc = "Possible values of the field `AUTO_PRE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum AUTO_PRER {
+    #[doc = "No program verify operations carried out"]
+    AUTO_PRE_0,
+    #[doc = "Causes an automatic Burst Program Verify after the Burst Program Operation"]
+    AUTO_PRE_1,
+}
+impl AUTO_PRER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            AUTO_PRER::AUTO_PRE_0 => false,
+            AUTO_PRER::AUTO_PRE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> AUTO_PRER {
+        match value {
+            false => AUTO_PRER::AUTO_PRE_0,
+            true => AUTO_PRER::AUTO_PRE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `AUTO_PRE_0`"]
+    #[inline]
+    pub fn is_auto_pre_0(&self) -> bool {
+        *self == AUTO_PRER::AUTO_PRE_0
+    }
+    #[doc = "Checks if the value of the field is `AUTO_PRE_1`"]
+    #[inline]
+    pub fn is_auto_pre_1(&self) -> bool {
+        *self == AUTO_PRER::AUTO_PRE_1
+    }
+}
+#[doc = "Possible values of the field `AUTO_PST`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum AUTO_PSTR {
+    #[doc = "No program verify operations carried out"]
+    AUTO_PST_0,
+    #[doc = "Causes an automatic Burst Program Verify before the Burst Program Operation"]
+    AUTO_PST_1,
+}
+impl AUTO_PSTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            AUTO_PSTR::AUTO_PST_0 => false,
+            AUTO_PSTR::AUTO_PST_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> AUTO_PSTR {
+        match value {
+            false => AUTO_PSTR::AUTO_PST_0,
+            true => AUTO_PSTR::AUTO_PST_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `AUTO_PST_0`"]
+    #[inline]
+    pub fn is_auto_pst_0(&self) -> bool {
+        *self == AUTO_PSTR::AUTO_PST_0
+    }
+    #[doc = "Checks if the value of the field is `AUTO_PST_1`"]
+    #[inline]
+    pub fn is_auto_pst_1(&self) -> bool {
+        *self == AUTO_PSTR::AUTO_PST_1
+    }
+}
+#[doc = "Possible values of the field `BURST_STATUS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum BURST_STATUSR {
+    #[doc = "Idle (Burst not active)"]
+    BURST_STATUS_0,
+    #[doc = "Burst program started but pending"]
+    BURST_STATUS_1,
+    #[doc = "Burst active, with 1st 128 bit word being written into Flash"]
+    BURST_STATUS_2,
+    #[doc = "Burst active, with 2nd 128 bit word being written into Flash"]
+    BURST_STATUS_3,
+    #[doc = "Burst active, with 3rd 128 bit word being written into Flash"]
+    BURST_STATUS_4,
+    #[doc = "Burst active, with 4th 128 bit word being written into Flash"]
+    BURST_STATUS_5,
+    #[doc = "Burst Complete (status of completed burst remains in this state unless explicitly cleared by SW)"]
+    BURST_STATUS_7,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl BURST_STATUSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            BURST_STATUSR::BURST_STATUS_0 => 0,
+            BURST_STATUSR::BURST_STATUS_1 => 1,
+            BURST_STATUSR::BURST_STATUS_2 => 2,
+            BURST_STATUSR::BURST_STATUS_3 => 3,
+            BURST_STATUSR::BURST_STATUS_4 => 4,
+            BURST_STATUSR::BURST_STATUS_5 => 5,
+            BURST_STATUSR::BURST_STATUS_7 => 7,
+            BURST_STATUSR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> BURST_STATUSR {
+        match value {
+            0 => BURST_STATUSR::BURST_STATUS_0,
+            1 => BURST_STATUSR::BURST_STATUS_1,
+            2 => BURST_STATUSR::BURST_STATUS_2,
+            3 => BURST_STATUSR::BURST_STATUS_3,
+            4 => BURST_STATUSR::BURST_STATUS_4,
+            5 => BURST_STATUSR::BURST_STATUS_5,
+            7 => BURST_STATUSR::BURST_STATUS_7,
+            i => BURST_STATUSR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `BURST_STATUS_0`"]
+    #[inline]
+    pub fn is_burst_status_0(&self) -> bool {
+        *self == BURST_STATUSR::BURST_STATUS_0
+    }
+    #[doc = "Checks if the value of the field is `BURST_STATUS_1`"]
+    #[inline]
+    pub fn is_burst_status_1(&self) -> bool {
+        *self == BURST_STATUSR::BURST_STATUS_1
+    }
+    #[doc = "Checks if the value of the field is `BURST_STATUS_2`"]
+    #[inline]
+    pub fn is_burst_status_2(&self) -> bool {
+        *self == BURST_STATUSR::BURST_STATUS_2
+    }
+    #[doc = "Checks if the value of the field is `BURST_STATUS_3`"]
+    #[inline]
+    pub fn is_burst_status_3(&self) -> bool {
+        *self == BURST_STATUSR::BURST_STATUS_3
+    }
+    #[doc = "Checks if the value of the field is `BURST_STATUS_4`"]
+    #[inline]
+    pub fn is_burst_status_4(&self) -> bool {
+        *self == BURST_STATUSR::BURST_STATUS_4
+    }
+    #[doc = "Checks if the value of the field is `BURST_STATUS_5`"]
+    #[inline]
+    pub fn is_burst_status_5(&self) -> bool {
+        *self == BURST_STATUSR::BURST_STATUS_5
+    }
+    #[doc = "Checks if the value of the field is `BURST_STATUS_7`"]
+    #[inline]
+    pub fn is_burst_status_7(&self) -> bool {
+        *self == BURST_STATUSR::BURST_STATUS_7
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PRE_ERRR {
+    bits: bool,
+}
+impl PRE_ERRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PST_ERRR {
+    bits: bool,
+}
+impl PST_ERRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ADDR_ERRR {
+    bits: bool,
+}
+impl ADDR_ERRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Proxy"]
+pub struct _STARTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _STARTW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TYPE`"]
+pub enum TYPEW {
+    #[doc = "Main Memory"]
+    TYPE_0,
+    #[doc = "Information Memory"]
+    TYPE_1,
+    #[doc = "Engineering Memory"]
+    TYPE_3,
+}
+impl TYPEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            TYPEW::TYPE_0 => 0,
+            TYPEW::TYPE_1 => 1,
+            TYPEW::TYPE_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TYPEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TYPEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TYPEW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "Main Memory"]
+    #[inline]
+    pub fn type_0(self) -> &'a mut W {
+        self.variant(TYPEW::TYPE_0)
+    }
+    #[doc = "Information Memory"]
+    #[inline]
+    pub fn type_1(self) -> &'a mut W {
+        self.variant(TYPEW::TYPE_1)
+    }
+    #[doc = "Engineering Memory"]
+    #[inline]
+    pub fn type_3(self) -> &'a mut W {
+        self.variant(TYPEW::TYPE_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `LEN`"]
+pub enum LENW {
+    #[doc = "No burst operation"]
+    LEN_0,
+    #[doc = "1 word burst of 128 bits, starting with address in the FLCTL_PRGBRST_STARTADDR Register"]
+    LEN_1,
+    #[doc = "2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register"]
+    LEN_2,
+    #[doc = "3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register"]
+    LEN_3,
+    #[doc = "4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register"]
+    LEN_4,
+}
+impl LENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            LENW::LEN_0 => 0,
+            LENW::LEN_1 => 1,
+            LENW::LEN_2 => 2,
+            LENW::LEN_3 => 3,
+            LENW::LEN_4 => 4,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _LENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _LENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: LENW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "No burst operation"]
+    #[inline]
+    pub fn len_0(self) -> &'a mut W {
+        self.variant(LENW::LEN_0)
+    }
+    #[doc = "1 word burst of 128 bits, starting with address in the FLCTL_PRGBRST_STARTADDR Register"]
+    #[inline]
+    pub fn len_1(self) -> &'a mut W {
+        self.variant(LENW::LEN_1)
+    }
+    #[doc = "2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register"]
+    #[inline]
+    pub fn len_2(self) -> &'a mut W {
+        self.variant(LENW::LEN_2)
+    }
+    #[doc = "3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register"]
+    #[inline]
+    pub fn len_3(self) -> &'a mut W {
+        self.variant(LENW::LEN_3)
+    }
+    #[doc = "4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register"]
+    #[inline]
+    pub fn len_4(self) -> &'a mut W {
+        self.variant(LENW::LEN_4)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `AUTO_PRE`"]
+pub enum AUTO_PREW {
+    #[doc = "No program verify operations carried out"]
+    AUTO_PRE_0,
+    #[doc = "Causes an automatic Burst Program Verify after the Burst Program Operation"]
+    AUTO_PRE_1,
+}
+impl AUTO_PREW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            AUTO_PREW::AUTO_PRE_0 => false,
+            AUTO_PREW::AUTO_PRE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AUTO_PREW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AUTO_PREW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: AUTO_PREW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No program verify operations carried out"]
+    #[inline]
+    pub fn auto_pre_0(self) -> &'a mut W {
+        self.variant(AUTO_PREW::AUTO_PRE_0)
+    }
+    #[doc = "Causes an automatic Burst Program Verify after the Burst Program Operation"]
+    #[inline]
+    pub fn auto_pre_1(self) -> &'a mut W {
+        self.variant(AUTO_PREW::AUTO_PRE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `AUTO_PST`"]
+pub enum AUTO_PSTW {
+    #[doc = "No program verify operations carried out"]
+    AUTO_PST_0,
+    #[doc = "Causes an automatic Burst Program Verify before the Burst Program Operation"]
+    AUTO_PST_1,
+}
+impl AUTO_PSTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            AUTO_PSTW::AUTO_PST_0 => false,
+            AUTO_PSTW::AUTO_PST_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AUTO_PSTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AUTO_PSTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: AUTO_PSTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No program verify operations carried out"]
+    #[inline]
+    pub fn auto_pst_0(self) -> &'a mut W {
+        self.variant(AUTO_PSTW::AUTO_PST_0)
+    }
+    #[doc = "Causes an automatic Burst Program Verify before the Burst Program Operation"]
+    #[inline]
+    pub fn auto_pst_1(self) -> &'a mut W {
+        self.variant(AUTO_PSTW::AUTO_PST_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLR_STATW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLR_STATW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 23;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 1:2 - Type of memory that burst program is carried out on"]
+    #[inline]
+    pub fn type_(&self) -> TYPER {
+        TYPER::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 3:5 - Length of burst"]
+    #[inline]
+    pub fn len(&self) -> LENR {
+        LENR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 6 - Auto-Verify operation before the Burst Program"]
+    #[inline]
+    pub fn auto_pre(&self) -> AUTO_PRER {
+        AUTO_PRER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 7 - Auto-Verify operation after the Burst Program"]
+    #[inline]
+    pub fn auto_pst(&self) -> AUTO_PSTR {
+        AUTO_PSTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 16:18 - Status of a Burst Operation"]
+    #[inline]
+    pub fn burst_status(&self) -> BURST_STATUSR {
+        BURST_STATUSR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 19 - Burst Operation encountered preprogram auto-verify errors"]
+    #[inline]
+    pub fn pre_err(&self) -> PRE_ERRR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 19;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PRE_ERRR { bits }
+    }
+    #[doc = "Bit 20 - Burst Operation encountered postprogram auto-verify errors"]
+    #[inline]
+    pub fn pst_err(&self) -> PST_ERRR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 20;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PST_ERRR { bits }
+    }
+    #[doc = "Bit 21 - Burst Operation was terminated due to attempted program of reserved memory"]
+    #[inline]
+    pub fn addr_err(&self) -> ADDR_ERRR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 21;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        ADDR_ERRR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 192 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Trigger start of burst program operation"]
+    #[inline]
+    pub fn start(&mut self) -> _STARTW {
+        _STARTW { w: self }
+    }
+    #[doc = "Bits 1:2 - Type of memory that burst program is carried out on"]
+    #[inline]
+    pub fn type_(&mut self) -> _TYPEW {
+        _TYPEW { w: self }
+    }
+    #[doc = "Bits 3:5 - Length of burst"]
+    #[inline]
+    pub fn len(&mut self) -> _LENW {
+        _LENW { w: self }
+    }
+    #[doc = "Bit 6 - Auto-Verify operation before the Burst Program"]
+    #[inline]
+    pub fn auto_pre(&mut self) -> _AUTO_PREW {
+        _AUTO_PREW { w: self }
+    }
+    #[doc = "Bit 7 - Auto-Verify operation after the Burst Program"]
+    #[inline]
+    pub fn auto_pst(&mut self) -> _AUTO_PSTW {
+        _AUTO_PSTW { w: self }
+    }
+    #[doc = "Bit 23 - Clear status bits 21-16 of this register"]
+    #[inline]
+    pub fn clr_stat(&mut self) -> _CLR_STATW {
+        _CLR_STATW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_prgbrst_data0_0.rs b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data0_0.rs
new file mode 100644
index 0000000..d88c096
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data0_0.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_PRGBRST_DATA0_0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DATAINR {
+    bits: u32,
+}
+impl DATAINR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DATAINW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DATAINW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 0"]
+    #[inline]
+    pub fn datain(&self) -> DATAINR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        DATAINR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 4294967295 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 0"]
+    #[inline]
+    pub fn datain(&mut self) -> _DATAINW {
+        _DATAINW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_prgbrst_data0_1.rs b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data0_1.rs
new file mode 100644
index 0000000..461e10b
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data0_1.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_PRGBRST_DATA0_1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DATAINR {
+    bits: u32,
+}
+impl DATAINR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DATAINW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DATAINW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 0"]
+    #[inline]
+    pub fn datain(&self) -> DATAINR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        DATAINR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 4294967295 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 0"]
+    #[inline]
+    pub fn datain(&mut self) -> _DATAINW {
+        _DATAINW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_prgbrst_data0_2.rs b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data0_2.rs
new file mode 100644
index 0000000..4738fda
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data0_2.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_PRGBRST_DATA0_2 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DATAINR {
+    bits: u32,
+}
+impl DATAINR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DATAINW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DATAINW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 0"]
+    #[inline]
+    pub fn datain(&self) -> DATAINR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        DATAINR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 4294967295 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 0"]
+    #[inline]
+    pub fn datain(&mut self) -> _DATAINW {
+        _DATAINW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_prgbrst_data0_3.rs b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data0_3.rs
new file mode 100644
index 0000000..c8fb58a
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data0_3.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_PRGBRST_DATA0_3 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DATAINR {
+    bits: u32,
+}
+impl DATAINR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DATAINW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DATAINW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 0"]
+    #[inline]
+    pub fn datain(&self) -> DATAINR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        DATAINR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 4294967295 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 0"]
+    #[inline]
+    pub fn datain(&mut self) -> _DATAINW {
+        _DATAINW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_prgbrst_data1_0.rs b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data1_0.rs
new file mode 100644
index 0000000..e52a721
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data1_0.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_PRGBRST_DATA1_0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DATAINR {
+    bits: u32,
+}
+impl DATAINR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DATAINW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DATAINW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 1"]
+    #[inline]
+    pub fn datain(&self) -> DATAINR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        DATAINR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 4294967295 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 1"]
+    #[inline]
+    pub fn datain(&mut self) -> _DATAINW {
+        _DATAINW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_prgbrst_data1_1.rs b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data1_1.rs
new file mode 100644
index 0000000..3e527a6
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data1_1.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_PRGBRST_DATA1_1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DATAINR {
+    bits: u32,
+}
+impl DATAINR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DATAINW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DATAINW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 1"]
+    #[inline]
+    pub fn datain(&self) -> DATAINR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        DATAINR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 4294967295 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 1"]
+    #[inline]
+    pub fn datain(&mut self) -> _DATAINW {
+        _DATAINW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_prgbrst_data1_2.rs b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data1_2.rs
new file mode 100644
index 0000000..f9e7ccc
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data1_2.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_PRGBRST_DATA1_2 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DATAINR {
+    bits: u32,
+}
+impl DATAINR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DATAINW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DATAINW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 1"]
+    #[inline]
+    pub fn datain(&self) -> DATAINR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        DATAINR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 4294967295 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 1"]
+    #[inline]
+    pub fn datain(&mut self) -> _DATAINW {
+        _DATAINW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_prgbrst_data1_3.rs b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data1_3.rs
new file mode 100644
index 0000000..c4d7538
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data1_3.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_PRGBRST_DATA1_3 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DATAINR {
+    bits: u32,
+}
+impl DATAINR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DATAINW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DATAINW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 1"]
+    #[inline]
+    pub fn datain(&self) -> DATAINR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        DATAINR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 4294967295 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 1"]
+    #[inline]
+    pub fn datain(&mut self) -> _DATAINW {
+        _DATAINW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_prgbrst_data2_0.rs b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data2_0.rs
new file mode 100644
index 0000000..9d06130
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data2_0.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_PRGBRST_DATA2_0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DATAINR {
+    bits: u32,
+}
+impl DATAINR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DATAINW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DATAINW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 2"]
+    #[inline]
+    pub fn datain(&self) -> DATAINR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        DATAINR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 4294967295 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 2"]
+    #[inline]
+    pub fn datain(&mut self) -> _DATAINW {
+        _DATAINW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_prgbrst_data2_1.rs b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data2_1.rs
new file mode 100644
index 0000000..1e32e8f
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data2_1.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_PRGBRST_DATA2_1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DATAINR {
+    bits: u32,
+}
+impl DATAINR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DATAINW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DATAINW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 2"]
+    #[inline]
+    pub fn datain(&self) -> DATAINR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        DATAINR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 4294967295 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 2"]
+    #[inline]
+    pub fn datain(&mut self) -> _DATAINW {
+        _DATAINW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_prgbrst_data2_2.rs b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data2_2.rs
new file mode 100644
index 0000000..9c37691
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data2_2.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_PRGBRST_DATA2_2 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DATAINR {
+    bits: u32,
+}
+impl DATAINR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DATAINW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DATAINW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 2"]
+    #[inline]
+    pub fn datain(&self) -> DATAINR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        DATAINR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 4294967295 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 2"]
+    #[inline]
+    pub fn datain(&mut self) -> _DATAINW {
+        _DATAINW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_prgbrst_data2_3.rs b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data2_3.rs
new file mode 100644
index 0000000..f724316
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data2_3.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_PRGBRST_DATA2_3 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DATAINR {
+    bits: u32,
+}
+impl DATAINR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DATAINW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DATAINW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 2"]
+    #[inline]
+    pub fn datain(&self) -> DATAINR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        DATAINR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 4294967295 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 2"]
+    #[inline]
+    pub fn datain(&mut self) -> _DATAINW {
+        _DATAINW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_prgbrst_data3_0.rs b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data3_0.rs
new file mode 100644
index 0000000..92b44b8
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data3_0.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_PRGBRST_DATA3_0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DATAINR {
+    bits: u32,
+}
+impl DATAINR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DATAINW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DATAINW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 3"]
+    #[inline]
+    pub fn datain(&self) -> DATAINR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        DATAINR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 4294967295 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 3"]
+    #[inline]
+    pub fn datain(&mut self) -> _DATAINW {
+        _DATAINW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_prgbrst_data3_1.rs b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data3_1.rs
new file mode 100644
index 0000000..478439c
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data3_1.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_PRGBRST_DATA3_1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DATAINR {
+    bits: u32,
+}
+impl DATAINR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DATAINW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DATAINW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 3"]
+    #[inline]
+    pub fn datain(&self) -> DATAINR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        DATAINR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 4294967295 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 3"]
+    #[inline]
+    pub fn datain(&mut self) -> _DATAINW {
+        _DATAINW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_prgbrst_data3_2.rs b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data3_2.rs
new file mode 100644
index 0000000..435cab9
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data3_2.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_PRGBRST_DATA3_2 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DATAINR {
+    bits: u32,
+}
+impl DATAINR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DATAINW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DATAINW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 3"]
+    #[inline]
+    pub fn datain(&self) -> DATAINR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        DATAINR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 4294967295 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 3"]
+    #[inline]
+    pub fn datain(&mut self) -> _DATAINW {
+        _DATAINW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_prgbrst_data3_3.rs b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data3_3.rs
new file mode 100644
index 0000000..9a3f2f1
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_prgbrst_data3_3.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_PRGBRST_DATA3_3 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DATAINR {
+    bits: u32,
+}
+impl DATAINR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DATAINW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DATAINW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 3"]
+    #[inline]
+    pub fn datain(&self) -> DATAINR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        DATAINR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 4294967295 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Program Burst 128 bit Data Word 3"]
+    #[inline]
+    pub fn datain(&mut self) -> _DATAINW {
+        _DATAINW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_prgbrst_startaddr.rs b/example-source/msp432p401r/src/flctl/flctl_prgbrst_startaddr.rs
new file mode 100644
index 0000000..81437a0
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_prgbrst_startaddr.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_PRGBRST_STARTADDR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct START_ADDRESSR {
+    bits: u32,
+}
+impl START_ADDRESSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _START_ADDRESSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _START_ADDRESSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4194303;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:21 - Start Address of Program Burst Operation"]
+    #[inline]
+    pub fn start_address(&self) -> START_ADDRESSR {
+        let bits = {
+            const MASK: u32 = 4194303;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        START_ADDRESSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:21 - Start Address of Program Burst Operation"]
+    #[inline]
+    pub fn start_address(&mut self) -> _START_ADDRESSW {
+        _START_ADDRESSW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_prgver_timctl.rs b/example-source/msp432p401r/src/flctl/flctl_prgver_timctl.rs
new file mode 100644
index 0000000..85375d8
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_prgver_timctl.rs
@@ -0,0 +1,83 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::FLCTL_PRGVER_TIMCTL {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SETUPR {
+    bits: u8,
+}
+impl SETUPR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ACTIVER {
+    bits: u8,
+}
+impl ACTIVER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct HOLDR {
+    bits: u8,
+}
+impl HOLDR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Length of the Setup phase for this operation"]
+    #[inline]
+    pub fn setup(&self) -> SETUPR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        SETUPR { bits }
+    }
+    #[doc = "Bits 8:11 - Length of the Active phase for this operation"]
+    #[inline]
+    pub fn active(&self) -> ACTIVER {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        ACTIVER { bits }
+    }
+    #[doc = "Bits 12:15 - Length of the Hold phase for this operation"]
+    #[inline]
+    pub fn hold(&self) -> HOLDR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        HOLDR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_program_timctl.rs b/example-source/msp432p401r/src/flctl/flctl_program_timctl.rs
new file mode 100644
index 0000000..a5260c2
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_program_timctl.rs
@@ -0,0 +1,83 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::FLCTL_PROGRAM_TIMCTL {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SETUPR {
+    bits: u8,
+}
+impl SETUPR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ACTIVER {
+    bits: u32,
+}
+impl ACTIVER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct HOLDR {
+    bits: u8,
+}
+impl HOLDR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Length of the Setup phase for this operation"]
+    #[inline]
+    pub fn setup(&self) -> SETUPR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        SETUPR { bits }
+    }
+    #[doc = "Bits 8:27 - Length of the Active phase for this operation"]
+    #[inline]
+    pub fn active(&self) -> ACTIVER {
+        let bits = {
+            const MASK: u32 = 1048575;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        ACTIVER { bits }
+    }
+    #[doc = "Bits 28:31 - Length of the Hold phase for this operation"]
+    #[inline]
+    pub fn hold(&self) -> HOLDR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 28;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        HOLDR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_rdbrst_ctlstat.rs b/example-source/msp432p401r/src/flctl/flctl_rdbrst_ctlstat.rs
new file mode 100644
index 0000000..33f2584
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_rdbrst_ctlstat.rs
@@ -0,0 +1,604 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_RDBRST_CTLSTAT {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `MEM_TYPE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum MEM_TYPER {
+    #[doc = "Main Memory"]
+    MEM_TYPE_0,
+    #[doc = "Information Memory"]
+    MEM_TYPE_1,
+    #[doc = "Engineering Memory"]
+    MEM_TYPE_3,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl MEM_TYPER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            MEM_TYPER::MEM_TYPE_0 => 0,
+            MEM_TYPER::MEM_TYPE_1 => 1,
+            MEM_TYPER::MEM_TYPE_3 => 3,
+            MEM_TYPER::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> MEM_TYPER {
+        match value {
+            0 => MEM_TYPER::MEM_TYPE_0,
+            1 => MEM_TYPER::MEM_TYPE_1,
+            3 => MEM_TYPER::MEM_TYPE_3,
+            i => MEM_TYPER::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `MEM_TYPE_0`"]
+    #[inline]
+    pub fn is_mem_type_0(&self) -> bool {
+        *self == MEM_TYPER::MEM_TYPE_0
+    }
+    #[doc = "Checks if the value of the field is `MEM_TYPE_1`"]
+    #[inline]
+    pub fn is_mem_type_1(&self) -> bool {
+        *self == MEM_TYPER::MEM_TYPE_1
+    }
+    #[doc = "Checks if the value of the field is `MEM_TYPE_3`"]
+    #[inline]
+    pub fn is_mem_type_3(&self) -> bool {
+        *self == MEM_TYPER::MEM_TYPE_3
+    }
+}
+#[doc = r" Value of the field"]
+pub struct STOP_FAILR {
+    bits: bool,
+}
+impl STOP_FAILR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `DATA_CMP`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DATA_CMPR {
+    #[doc = "0000_0000_0000_0000_0000_0000_0000_0000"]
+    DATA_CMP_0,
+    #[doc = "FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF"]
+    DATA_CMP_1,
+}
+impl DATA_CMPR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            DATA_CMPR::DATA_CMP_0 => false,
+            DATA_CMPR::DATA_CMP_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> DATA_CMPR {
+        match value {
+            false => DATA_CMPR::DATA_CMP_0,
+            true => DATA_CMPR::DATA_CMP_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DATA_CMP_0`"]
+    #[inline]
+    pub fn is_data_cmp_0(&self) -> bool {
+        *self == DATA_CMPR::DATA_CMP_0
+    }
+    #[doc = "Checks if the value of the field is `DATA_CMP_1`"]
+    #[inline]
+    pub fn is_data_cmp_1(&self) -> bool {
+        *self == DATA_CMPR::DATA_CMP_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct TEST_ENR {
+    bits: bool,
+}
+impl TEST_ENR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `BRST_STAT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum BRST_STATR {
+    #[doc = "Idle"]
+    BRST_STAT_0,
+    #[doc = "Burst/Compare START bit written, but operation pending"]
+    BRST_STAT_1,
+    #[doc = "Burst/Compare in progress"]
+    BRST_STAT_2,
+    #[doc = "Burst complete (status of completed burst remains in this state unless explicitly cleared by SW)"]
+    BRST_STAT_3,
+}
+impl BRST_STATR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            BRST_STATR::BRST_STAT_0 => 0,
+            BRST_STATR::BRST_STAT_1 => 1,
+            BRST_STATR::BRST_STAT_2 => 2,
+            BRST_STATR::BRST_STAT_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> BRST_STATR {
+        match value {
+            0 => BRST_STATR::BRST_STAT_0,
+            1 => BRST_STATR::BRST_STAT_1,
+            2 => BRST_STATR::BRST_STAT_2,
+            3 => BRST_STATR::BRST_STAT_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `BRST_STAT_0`"]
+    #[inline]
+    pub fn is_brst_stat_0(&self) -> bool {
+        *self == BRST_STATR::BRST_STAT_0
+    }
+    #[doc = "Checks if the value of the field is `BRST_STAT_1`"]
+    #[inline]
+    pub fn is_brst_stat_1(&self) -> bool {
+        *self == BRST_STATR::BRST_STAT_1
+    }
+    #[doc = "Checks if the value of the field is `BRST_STAT_2`"]
+    #[inline]
+    pub fn is_brst_stat_2(&self) -> bool {
+        *self == BRST_STATR::BRST_STAT_2
+    }
+    #[doc = "Checks if the value of the field is `BRST_STAT_3`"]
+    #[inline]
+    pub fn is_brst_stat_3(&self) -> bool {
+        *self == BRST_STATR::BRST_STAT_3
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CMP_ERRR {
+    bits: bool,
+}
+impl CMP_ERRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ADDR_ERRR {
+    bits: bool,
+}
+impl ADDR_ERRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Proxy"]
+pub struct _STARTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _STARTW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `MEM_TYPE`"]
+pub enum MEM_TYPEW {
+    #[doc = "Main Memory"]
+    MEM_TYPE_0,
+    #[doc = "Information Memory"]
+    MEM_TYPE_1,
+    #[doc = "Engineering Memory"]
+    MEM_TYPE_3,
+}
+impl MEM_TYPEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            MEM_TYPEW::MEM_TYPE_0 => 0,
+            MEM_TYPEW::MEM_TYPE_1 => 1,
+            MEM_TYPEW::MEM_TYPE_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MEM_TYPEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MEM_TYPEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: MEM_TYPEW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "Main Memory"]
+    #[inline]
+    pub fn mem_type_0(self) -> &'a mut W {
+        self.variant(MEM_TYPEW::MEM_TYPE_0)
+    }
+    #[doc = "Information Memory"]
+    #[inline]
+    pub fn mem_type_1(self) -> &'a mut W {
+        self.variant(MEM_TYPEW::MEM_TYPE_1)
+    }
+    #[doc = "Engineering Memory"]
+    #[inline]
+    pub fn mem_type_3(self) -> &'a mut W {
+        self.variant(MEM_TYPEW::MEM_TYPE_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _STOP_FAILW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _STOP_FAILW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `DATA_CMP`"]
+pub enum DATA_CMPW {
+    #[doc = "0000_0000_0000_0000_0000_0000_0000_0000"]
+    DATA_CMP_0,
+    #[doc = "FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF"]
+    DATA_CMP_1,
+}
+impl DATA_CMPW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            DATA_CMPW::DATA_CMP_0 => false,
+            DATA_CMPW::DATA_CMP_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DATA_CMPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DATA_CMPW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: DATA_CMPW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "0000_0000_0000_0000_0000_0000_0000_0000"]
+    #[inline]
+    pub fn data_cmp_0(self) -> &'a mut W {
+        self.variant(DATA_CMPW::DATA_CMP_0)
+    }
+    #[doc = "FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF"]
+    #[inline]
+    pub fn data_cmp_1(self) -> &'a mut W {
+        self.variant(DATA_CMPW::DATA_CMP_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TEST_ENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TEST_ENW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLR_STATW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLR_STATW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 23;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 1:2 - Type of memory that burst is carried out on"]
+    #[inline]
+    pub fn mem_type(&self) -> MEM_TYPER {
+        MEM_TYPER::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 3 - Terminate burst/compare operation"]
+    #[inline]
+    pub fn stop_fail(&self) -> STOP_FAILR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        STOP_FAILR { bits }
+    }
+    #[doc = "Bit 4 - Data pattern used for comparison against memory read data"]
+    #[inline]
+    pub fn data_cmp(&self) -> DATA_CMPR {
+        DATA_CMPR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 6 - Enable comparison against test data compare registers"]
+    #[inline]
+    pub fn test_en(&self) -> TEST_ENR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        TEST_ENR { bits }
+    }
+    #[doc = "Bits 16:17 - Status of Burst/Compare operation"]
+    #[inline]
+    pub fn brst_stat(&self) -> BRST_STATR {
+        BRST_STATR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 18 - Burst/Compare Operation encountered atleast one data"]
+    #[inline]
+    pub fn cmp_err(&self) -> CMP_ERRR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 18;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CMP_ERRR { bits }
+    }
+    #[doc = "Bit 19 - Burst/Compare Operation was terminated due to access to"]
+    #[inline]
+    pub fn addr_err(&self) -> ADDR_ERRR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 19;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        ADDR_ERRR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Start of burst/compare operation"]
+    #[inline]
+    pub fn start(&mut self) -> _STARTW {
+        _STARTW { w: self }
+    }
+    #[doc = "Bits 1:2 - Type of memory that burst is carried out on"]
+    #[inline]
+    pub fn mem_type(&mut self) -> _MEM_TYPEW {
+        _MEM_TYPEW { w: self }
+    }
+    #[doc = "Bit 3 - Terminate burst/compare operation"]
+    #[inline]
+    pub fn stop_fail(&mut self) -> _STOP_FAILW {
+        _STOP_FAILW { w: self }
+    }
+    #[doc = "Bit 4 - Data pattern used for comparison against memory read data"]
+    #[inline]
+    pub fn data_cmp(&mut self) -> _DATA_CMPW {
+        _DATA_CMPW { w: self }
+    }
+    #[doc = "Bit 6 - Enable comparison against test data compare registers"]
+    #[inline]
+    pub fn test_en(&mut self) -> _TEST_ENW {
+        _TEST_ENW { w: self }
+    }
+    #[doc = "Bit 23 - Clear status bits 19-16 of this register"]
+    #[inline]
+    pub fn clr_stat(&mut self) -> _CLR_STATW {
+        _CLR_STATW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_rdbrst_failaddr.rs b/example-source/msp432p401r/src/flctl/flctl_rdbrst_failaddr.rs
new file mode 100644
index 0000000..aea6fce
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_rdbrst_failaddr.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_RDBRST_FAILADDR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct FAIL_ADDRESSR {
+    bits: u32,
+}
+impl FAIL_ADDRESSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FAIL_ADDRESSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FAIL_ADDRESSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 2097151;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:20 - Reflects address of last failed compare"]
+    #[inline]
+    pub fn fail_address(&self) -> FAIL_ADDRESSR {
+        let bits = {
+            const MASK: u32 = 2097151;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        FAIL_ADDRESSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:20 - Reflects address of last failed compare"]
+    #[inline]
+    pub fn fail_address(&mut self) -> _FAIL_ADDRESSW {
+        _FAIL_ADDRESSW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_rdbrst_failcnt.rs b/example-source/msp432p401r/src/flctl/flctl_rdbrst_failcnt.rs
new file mode 100644
index 0000000..08f92f4
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_rdbrst_failcnt.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_RDBRST_FAILCNT {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct FAIL_COUNTR {
+    bits: u32,
+}
+impl FAIL_COUNTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FAIL_COUNTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FAIL_COUNTW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 131071;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:16 - Number of failures encountered in burst operation"]
+    #[inline]
+    pub fn fail_count(&self) -> FAIL_COUNTR {
+        let bits = {
+            const MASK: u32 = 131071;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        FAIL_COUNTR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:16 - Number of failures encountered in burst operation"]
+    #[inline]
+    pub fn fail_count(&mut self) -> _FAIL_COUNTW {
+        _FAIL_COUNTW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_rdbrst_len.rs b/example-source/msp432p401r/src/flctl/flctl_rdbrst_len.rs
new file mode 100644
index 0000000..195062d
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_rdbrst_len.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_RDBRST_LEN {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct BURST_LENGTHR {
+    bits: u32,
+}
+impl BURST_LENGTHR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _BURST_LENGTHW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _BURST_LENGTHW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 2097151;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:20 - Length of Burst Operation"]
+    #[inline]
+    pub fn burst_length(&self) -> BURST_LENGTHR {
+        let bits = {
+            const MASK: u32 = 2097151;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        BURST_LENGTHR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:20 - Length of Burst Operation"]
+    #[inline]
+    pub fn burst_length(&mut self) -> _BURST_LENGTHW {
+        _BURST_LENGTHW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_rdbrst_startaddr.rs b/example-source/msp432p401r/src/flctl/flctl_rdbrst_startaddr.rs
new file mode 100644
index 0000000..0bd2768
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_rdbrst_startaddr.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_RDBRST_STARTADDR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct START_ADDRESSR {
+    bits: u32,
+}
+impl START_ADDRESSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _START_ADDRESSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _START_ADDRESSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 2097151;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:20 - Start Address of Burst Operation"]
+    #[inline]
+    pub fn start_address(&self) -> START_ADDRESSR {
+        let bits = {
+            const MASK: u32 = 2097151;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        START_ADDRESSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:20 - Start Address of Burst Operation"]
+    #[inline]
+    pub fn start_address(&mut self) -> _START_ADDRESSW {
+        _START_ADDRESSW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_read_timctl.rs b/example-source/msp432p401r/src/flctl/flctl_read_timctl.rs
new file mode 100644
index 0000000..4c1b732
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_read_timctl.rs
@@ -0,0 +1,83 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::FLCTL_READ_TIMCTL {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SETUPR {
+    bits: u8,
+}
+impl SETUPR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct IREF_BOOST1R {
+    bits: u8,
+}
+impl IREF_BOOST1R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SETUP_LONGR {
+    bits: u8,
+}
+impl SETUP_LONGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Configures the length of the Setup phase for this operation"]
+    #[inline]
+    pub fn setup(&self) -> SETUPR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        SETUPR { bits }
+    }
+    #[doc = "Bits 12:15 - Length of the IREF_BOOST1 signal of the IP"]
+    #[inline]
+    pub fn iref_boost1(&self) -> IREF_BOOST1R {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        IREF_BOOST1R { bits }
+    }
+    #[doc = "Bits 16:23 - Length of the Setup time into read mode when the device is recovering from one of the following conditions: Moving from Power-down or Standby back to Active and device is not trimmed. Moving from standby to active state in low-frequency active mode. Recovering from the LDO Boost operation after a Mass Erase."]
+    #[inline]
+    pub fn setup_long(&self) -> SETUP_LONGR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        SETUP_LONGR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_readmargin_timctl.rs b/example-source/msp432p401r/src/flctl/flctl_readmargin_timctl.rs
new file mode 100644
index 0000000..2c0299e
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_readmargin_timctl.rs
@@ -0,0 +1,41 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::FLCTL_READMARGIN_TIMCTL {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SETUPR {
+    bits: u8,
+}
+impl SETUPR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Length of the Setup phase for this operation"]
+    #[inline]
+    pub fn setup(&self) -> SETUPR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        SETUPR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/flctl/flctl_setifg.rs b/example-source/msp432p401r/src/flctl/flctl_setifg.rs
new file mode 100644
index 0000000..30232e5
--- /dev/null
+++ b/example-source/msp432p401r/src/flctl/flctl_setifg.rs
@@ -0,0 +1,253 @@
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLCTL_SETIFG {
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RDBRSTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RDBRSTW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AVPREW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AVPREW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AVPSTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AVPSTW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PRGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PRGW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PRGBW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PRGBW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ERASEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ERASEW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _BMRKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _BMRKW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PRG_ERRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PRG_ERRW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn rdbrst(&mut self) -> _RDBRSTW {
+        _RDBRSTW { w: self }
+    }
+    #[doc = "Bit 1 - Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn avpre(&mut self) -> _AVPREW {
+        _AVPREW { w: self }
+    }
+    #[doc = "Bit 2 - Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn avpst(&mut self) -> _AVPSTW {
+        _AVPSTW { w: self }
+    }
+    #[doc = "Bit 3 - Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn prg(&mut self) -> _PRGW {
+        _PRGW { w: self }
+    }
+    #[doc = "Bit 4 - Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn prgb(&mut self) -> _PRGBW {
+        _PRGBW { w: self }
+    }
+    #[doc = "Bit 5 - Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn erase(&mut self) -> _ERASEW {
+        _ERASEW { w: self }
+    }
+    #[doc = "Bit 8 - Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn bmrk(&mut self) -> _BMRKW {
+        _BMRKW { w: self }
+    }
+    #[doc = "Bit 9 - Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG"]
+    #[inline]
+    pub fn prg_err(&mut self) -> _PRG_ERRW {
+        _PRG_ERRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/lib.rs b/example-source/msp432p401r/src/lib.rs
new file mode 100644
index 0000000..8468206
--- /dev/null
+++ b/example-source/msp432p401r/src/lib.rs
@@ -0,0 +1,1165 @@
+#![doc = "Peripheral access API for MSP432P401R microcontrollers (generated using svd2rust v0.14.0)\n\nYou can find an overview of the API [here].\n\n[here]: https://docs.rs/svd2rust/0.14.0/svd2rust/#peripheral-api"]
+#![deny(missing_docs)]
+#![deny(warnings)]
+#![allow(non_camel_case_types)]
+#![no_std]
+extern crate bare_metal;
+extern crate cortex_m;
+#[cfg(feature = "rt")]
+extern crate cortex_m_rt;
+extern crate vcell;
+use core::marker::PhantomData;
+use core::ops::Deref;
+#[cfg(feature = "rt")]
+extern "C" {
+    fn PSS_IRQ();
+    fn CS_IRQ();
+    fn PCM_IRQ();
+    fn WDT_A_IRQ();
+    fn FPU_IRQ();
+    fn FLCTL_IRQ();
+    fn COMP_E0_IRQ();
+    fn COMP_E1_IRQ();
+    fn TA0_0_IRQ();
+    fn TA0_N_IRQ();
+    fn TA1_0_IRQ();
+    fn TA1_N_IRQ();
+    fn TA2_0_IRQ();
+    fn TA2_N_IRQ();
+    fn TA3_0_IRQ();
+    fn TA3_N_IRQ();
+    fn EUSCIA0_IRQ();
+    fn EUSCIA1_IRQ();
+    fn EUSCIA2_IRQ();
+    fn EUSCIA3_IRQ();
+    fn EUSCIB0_IRQ();
+    fn EUSCIB1_IRQ();
+    fn EUSCIB2_IRQ();
+    fn EUSCIB3_IRQ();
+    fn ADC14_IRQ();
+    fn T32_INT1_IRQ();
+    fn T32_INT2_IRQ();
+    fn T32_INTC_IRQ();
+    fn AES256_IRQ();
+    fn RTC_C_IRQ();
+    fn DMA_ERR_IRQ();
+    fn DMA_INT3_IRQ();
+    fn DMA_INT2_IRQ();
+    fn DMA_INT1_IRQ();
+    fn DMA_INT0_IRQ();
+    fn PORT1_IRQ();
+    fn PORT2_IRQ();
+    fn PORT3_IRQ();
+    fn PORT4_IRQ();
+    fn PORT5_IRQ();
+    fn PORT6_IRQ();
+}
+#[doc(hidden)]
+pub union Vector {
+    _handler: unsafe extern "C" fn(),
+    _reserved: u32,
+}
+#[cfg(feature = "rt")]
+#[doc(hidden)]
+#[link_section = ".vector_table.interrupts"]
+#[no_mangle]
+pub static __INTERRUPTS: [Vector; 41] = [
+    Vector { _handler: PSS_IRQ },
+    Vector { _handler: CS_IRQ },
+    Vector { _handler: PCM_IRQ },
+    Vector {
+        _handler: WDT_A_IRQ,
+    },
+    Vector { _handler: FPU_IRQ },
+    Vector {
+        _handler: FLCTL_IRQ,
+    },
+    Vector {
+        _handler: COMP_E0_IRQ,
+    },
+    Vector {
+        _handler: COMP_E1_IRQ,
+    },
+    Vector {
+        _handler: TA0_0_IRQ,
+    },
+    Vector {
+        _handler: TA0_N_IRQ,
+    },
+    Vector {
+        _handler: TA1_0_IRQ,
+    },
+    Vector {
+        _handler: TA1_N_IRQ,
+    },
+    Vector {
+        _handler: TA2_0_IRQ,
+    },
+    Vector {
+        _handler: TA2_N_IRQ,
+    },
+    Vector {
+        _handler: TA3_0_IRQ,
+    },
+    Vector {
+        _handler: TA3_N_IRQ,
+    },
+    Vector {
+        _handler: EUSCIA0_IRQ,
+    },
+    Vector {
+        _handler: EUSCIA1_IRQ,
+    },
+    Vector {
+        _handler: EUSCIA2_IRQ,
+    },
+    Vector {
+        _handler: EUSCIA3_IRQ,
+    },
+    Vector {
+        _handler: EUSCIB0_IRQ,
+    },
+    Vector {
+        _handler: EUSCIB1_IRQ,
+    },
+    Vector {
+        _handler: EUSCIB2_IRQ,
+    },
+    Vector {
+        _handler: EUSCIB3_IRQ,
+    },
+    Vector {
+        _handler: ADC14_IRQ,
+    },
+    Vector {
+        _handler: T32_INT1_IRQ,
+    },
+    Vector {
+        _handler: T32_INT2_IRQ,
+    },
+    Vector {
+        _handler: T32_INTC_IRQ,
+    },
+    Vector {
+        _handler: AES256_IRQ,
+    },
+    Vector {
+        _handler: RTC_C_IRQ,
+    },
+    Vector {
+        _handler: DMA_ERR_IRQ,
+    },
+    Vector {
+        _handler: DMA_INT3_IRQ,
+    },
+    Vector {
+        _handler: DMA_INT2_IRQ,
+    },
+    Vector {
+        _handler: DMA_INT1_IRQ,
+    },
+    Vector {
+        _handler: DMA_INT0_IRQ,
+    },
+    Vector {
+        _handler: PORT1_IRQ,
+    },
+    Vector {
+        _handler: PORT2_IRQ,
+    },
+    Vector {
+        _handler: PORT3_IRQ,
+    },
+    Vector {
+        _handler: PORT4_IRQ,
+    },
+    Vector {
+        _handler: PORT5_IRQ,
+    },
+    Vector {
+        _handler: PORT6_IRQ,
+    },
+];
+#[doc = r" Enumeration of all the interrupts"]
+pub enum Interrupt {
+    #[doc = "0 - PSS Interrupt"]
+    PSS_IRQ,
+    #[doc = "1 - CS Interrupt"]
+    CS_IRQ,
+    #[doc = "2 - PCM Interrupt"]
+    PCM_IRQ,
+    #[doc = "3 - WDT_A Interrupt"]
+    WDT_A_IRQ,
+    #[doc = "4 - FPU Interrupt"]
+    FPU_IRQ,
+    #[doc = "5 - Flash Controller Interrupt"]
+    FLCTL_IRQ,
+    #[doc = "6 - COMP_E0 Interrupt"]
+    COMP_E0_IRQ,
+    #[doc = "7 - COMP_E1 Interrupt"]
+    COMP_E1_IRQ,
+    #[doc = "8 - TA0_0 Interrupt"]
+    TA0_0_IRQ,
+    #[doc = "9 - TA0_N Interrupt"]
+    TA0_N_IRQ,
+    #[doc = "10 - TA1_0 Interrupt"]
+    TA1_0_IRQ,
+    #[doc = "11 - TA1_N Interrupt"]
+    TA1_N_IRQ,
+    #[doc = "12 - TA2_0 Interrupt"]
+    TA2_0_IRQ,
+    #[doc = "13 - TA2_N Interrupt"]
+    TA2_N_IRQ,
+    #[doc = "14 - TA3_0 Interrupt"]
+    TA3_0_IRQ,
+    #[doc = "15 - TA3_N Interrupt"]
+    TA3_N_IRQ,
+    #[doc = "16 - EUSCIA0 Interrupt"]
+    EUSCIA0_IRQ,
+    #[doc = "17 - EUSCIA1 Interrupt"]
+    EUSCIA1_IRQ,
+    #[doc = "18 - EUSCIA2 Interrupt"]
+    EUSCIA2_IRQ,
+    #[doc = "19 - EUSCIA3 Interrupt"]
+    EUSCIA3_IRQ,
+    #[doc = "20 - EUSCIB0 Interrupt"]
+    EUSCIB0_IRQ,
+    #[doc = "21 - EUSCIB1 Interrupt"]
+    EUSCIB1_IRQ,
+    #[doc = "22 - EUSCIB2 Interrupt"]
+    EUSCIB2_IRQ,
+    #[doc = "23 - EUSCIB3 Interrupt"]
+    EUSCIB3_IRQ,
+    #[doc = "24 - ADC14 Interrupt"]
+    ADC14_IRQ,
+    #[doc = "25 - T32_INT1 Interrupt"]
+    T32_INT1_IRQ,
+    #[doc = "26 - T32_INT2 Interrupt"]
+    T32_INT2_IRQ,
+    #[doc = "27 - T32_INTC Interrupt"]
+    T32_INTC_IRQ,
+    #[doc = "28 - AES256 Interrupt"]
+    AES256_IRQ,
+    #[doc = "29 - RTC_C Interrupt"]
+    RTC_C_IRQ,
+    #[doc = "30 - DMA_ERR Interrupt"]
+    DMA_ERR_IRQ,
+    #[doc = "31 - DMA_INT3 Interrupt"]
+    DMA_INT3_IRQ,
+    #[doc = "32 - DMA_INT2 Interrupt"]
+    DMA_INT2_IRQ,
+    #[doc = "33 - DMA_INT1 Interrupt"]
+    DMA_INT1_IRQ,
+    #[doc = "34 - DMA_INT0 Interrupt"]
+    DMA_INT0_IRQ,
+    #[doc = "35 - Port1 Interrupt"]
+    PORT1_IRQ,
+    #[doc = "36 - Port2 Interrupt"]
+    PORT2_IRQ,
+    #[doc = "37 - Port3 Interrupt"]
+    PORT3_IRQ,
+    #[doc = "38 - Port4 Interrupt"]
+    PORT4_IRQ,
+    #[doc = "39 - Port5 Interrupt"]
+    PORT5_IRQ,
+    #[doc = "40 - Port6 Interrupt"]
+    PORT6_IRQ,
+}
+unsafe impl ::bare_metal::Nr for Interrupt {
+    #[inline]
+    fn nr(&self) -> u8 {
+        match *self {
+            Interrupt::PSS_IRQ => 0,
+            Interrupt::CS_IRQ => 1,
+            Interrupt::PCM_IRQ => 2,
+            Interrupt::WDT_A_IRQ => 3,
+            Interrupt::FPU_IRQ => 4,
+            Interrupt::FLCTL_IRQ => 5,
+            Interrupt::COMP_E0_IRQ => 6,
+            Interrupt::COMP_E1_IRQ => 7,
+            Interrupt::TA0_0_IRQ => 8,
+            Interrupt::TA0_N_IRQ => 9,
+            Interrupt::TA1_0_IRQ => 10,
+            Interrupt::TA1_N_IRQ => 11,
+            Interrupt::TA2_0_IRQ => 12,
+            Interrupt::TA2_N_IRQ => 13,
+            Interrupt::TA3_0_IRQ => 14,
+            Interrupt::TA3_N_IRQ => 15,
+            Interrupt::EUSCIA0_IRQ => 16,
+            Interrupt::EUSCIA1_IRQ => 17,
+            Interrupt::EUSCIA2_IRQ => 18,
+            Interrupt::EUSCIA3_IRQ => 19,
+            Interrupt::EUSCIB0_IRQ => 20,
+            Interrupt::EUSCIB1_IRQ => 21,
+            Interrupt::EUSCIB2_IRQ => 22,
+            Interrupt::EUSCIB3_IRQ => 23,
+            Interrupt::ADC14_IRQ => 24,
+            Interrupt::T32_INT1_IRQ => 25,
+            Interrupt::T32_INT2_IRQ => 26,
+            Interrupt::T32_INTC_IRQ => 27,
+            Interrupt::AES256_IRQ => 28,
+            Interrupt::RTC_C_IRQ => 29,
+            Interrupt::DMA_ERR_IRQ => 30,
+            Interrupt::DMA_INT3_IRQ => 31,
+            Interrupt::DMA_INT2_IRQ => 32,
+            Interrupt::DMA_INT1_IRQ => 33,
+            Interrupt::DMA_INT0_IRQ => 34,
+            Interrupt::PORT1_IRQ => 35,
+            Interrupt::PORT2_IRQ => 36,
+            Interrupt::PORT3_IRQ => 37,
+            Interrupt::PORT4_IRQ => 38,
+            Interrupt::PORT5_IRQ => 39,
+            Interrupt::PORT6_IRQ => 40,
+        }
+    }
+}
+#[cfg(feature = "rt")]
+pub use self::Interrupt as interrupt;
+pub use cortex_m::peripheral::Peripherals as CorePeripherals;
+pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, SYST, TPIU};
+#[cfg(feature = "rt")]
+pub use cortex_m_rt::interrupt;
+#[doc = "TLV"]
+pub struct TLV {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for TLV {}
+impl TLV {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const tlv::RegisterBlock {
+        2101248 as *const _
+    }
+}
+impl Deref for TLV {
+    type Target = tlv::RegisterBlock;
+    fn deref(&self) -> &tlv::RegisterBlock {
+        unsafe { &*TLV::ptr() }
+    }
+}
+#[doc = "TLV"]
+pub mod tlv;
+#[doc = "TIMER_A0"]
+pub struct TIMER_A0 {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for TIMER_A0 {}
+impl TIMER_A0 {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const timer_a0::RegisterBlock {
+        1073741824 as *const _
+    }
+}
+impl Deref for TIMER_A0 {
+    type Target = timer_a0::RegisterBlock;
+    fn deref(&self) -> &timer_a0::RegisterBlock {
+        unsafe { &*TIMER_A0::ptr() }
+    }
+}
+#[doc = "TIMER_A0"]
+pub mod timer_a0;
+#[doc = "TIMER_A1"]
+pub struct TIMER_A1 {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for TIMER_A1 {}
+impl TIMER_A1 {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const timer_a1::RegisterBlock {
+        1073742848 as *const _
+    }
+}
+impl Deref for TIMER_A1 {
+    type Target = timer_a1::RegisterBlock;
+    fn deref(&self) -> &timer_a1::RegisterBlock {
+        unsafe { &*TIMER_A1::ptr() }
+    }
+}
+#[doc = "TIMER_A1"]
+pub mod timer_a1;
+#[doc = "TIMER_A2"]
+pub struct TIMER_A2 {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for TIMER_A2 {}
+impl TIMER_A2 {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const timer_a2::RegisterBlock {
+        1073743872 as *const _
+    }
+}
+impl Deref for TIMER_A2 {
+    type Target = timer_a2::RegisterBlock;
+    fn deref(&self) -> &timer_a2::RegisterBlock {
+        unsafe { &*TIMER_A2::ptr() }
+    }
+}
+#[doc = "TIMER_A2"]
+pub mod timer_a2;
+#[doc = "TIMER_A3"]
+pub struct TIMER_A3 {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for TIMER_A3 {}
+impl TIMER_A3 {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const timer_a3::RegisterBlock {
+        1073744896 as *const _
+    }
+}
+impl Deref for TIMER_A3 {
+    type Target = timer_a3::RegisterBlock;
+    fn deref(&self) -> &timer_a3::RegisterBlock {
+        unsafe { &*TIMER_A3::ptr() }
+    }
+}
+#[doc = "TIMER_A3"]
+pub mod timer_a3;
+#[doc = "EUSCI_A0"]
+pub struct EUSCI_A0 {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for EUSCI_A0 {}
+impl EUSCI_A0 {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const eusci_a0::RegisterBlock {
+        1073745920 as *const _
+    }
+}
+impl Deref for EUSCI_A0 {
+    type Target = eusci_a0::RegisterBlock;
+    fn deref(&self) -> &eusci_a0::RegisterBlock {
+        unsafe { &*EUSCI_A0::ptr() }
+    }
+}
+#[doc = "EUSCI_A0"]
+pub mod eusci_a0;
+#[doc = "EUSCI_A1"]
+pub struct EUSCI_A1 {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for EUSCI_A1 {}
+impl EUSCI_A1 {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const eusci_a1::RegisterBlock {
+        1073746944 as *const _
+    }
+}
+impl Deref for EUSCI_A1 {
+    type Target = eusci_a1::RegisterBlock;
+    fn deref(&self) -> &eusci_a1::RegisterBlock {
+        unsafe { &*EUSCI_A1::ptr() }
+    }
+}
+#[doc = "EUSCI_A1"]
+pub mod eusci_a1;
+#[doc = "EUSCI_A2"]
+pub struct EUSCI_A2 {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for EUSCI_A2 {}
+impl EUSCI_A2 {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const eusci_a2::RegisterBlock {
+        1073747968 as *const _
+    }
+}
+impl Deref for EUSCI_A2 {
+    type Target = eusci_a2::RegisterBlock;
+    fn deref(&self) -> &eusci_a2::RegisterBlock {
+        unsafe { &*EUSCI_A2::ptr() }
+    }
+}
+#[doc = "EUSCI_A2"]
+pub mod eusci_a2;
+#[doc = "EUSCI_A3"]
+pub struct EUSCI_A3 {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for EUSCI_A3 {}
+impl EUSCI_A3 {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const eusci_a3::RegisterBlock {
+        1073748992 as *const _
+    }
+}
+impl Deref for EUSCI_A3 {
+    type Target = eusci_a3::RegisterBlock;
+    fn deref(&self) -> &eusci_a3::RegisterBlock {
+        unsafe { &*EUSCI_A3::ptr() }
+    }
+}
+#[doc = "EUSCI_A3"]
+pub mod eusci_a3;
+#[doc = "EUSCI_B0"]
+pub struct EUSCI_B0 {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for EUSCI_B0 {}
+impl EUSCI_B0 {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const eusci_b0::RegisterBlock {
+        1073750016 as *const _
+    }
+}
+impl Deref for EUSCI_B0 {
+    type Target = eusci_b0::RegisterBlock;
+    fn deref(&self) -> &eusci_b0::RegisterBlock {
+        unsafe { &*EUSCI_B0::ptr() }
+    }
+}
+#[doc = "EUSCI_B0"]
+pub mod eusci_b0;
+#[doc = "EUSCI_B1"]
+pub struct EUSCI_B1 {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for EUSCI_B1 {}
+impl EUSCI_B1 {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const eusci_b1::RegisterBlock {
+        1073751040 as *const _
+    }
+}
+impl Deref for EUSCI_B1 {
+    type Target = eusci_b1::RegisterBlock;
+    fn deref(&self) -> &eusci_b1::RegisterBlock {
+        unsafe { &*EUSCI_B1::ptr() }
+    }
+}
+#[doc = "EUSCI_B1"]
+pub mod eusci_b1;
+#[doc = "EUSCI_B2"]
+pub struct EUSCI_B2 {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for EUSCI_B2 {}
+impl EUSCI_B2 {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const eusci_b2::RegisterBlock {
+        1073752064 as *const _
+    }
+}
+impl Deref for EUSCI_B2 {
+    type Target = eusci_b2::RegisterBlock;
+    fn deref(&self) -> &eusci_b2::RegisterBlock {
+        unsafe { &*EUSCI_B2::ptr() }
+    }
+}
+#[doc = "EUSCI_B2"]
+pub mod eusci_b2;
+#[doc = "EUSCI_B3"]
+pub struct EUSCI_B3 {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for EUSCI_B3 {}
+impl EUSCI_B3 {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const eusci_b3::RegisterBlock {
+        1073753088 as *const _
+    }
+}
+impl Deref for EUSCI_B3 {
+    type Target = eusci_b3::RegisterBlock;
+    fn deref(&self) -> &eusci_b3::RegisterBlock {
+        unsafe { &*EUSCI_B3::ptr() }
+    }
+}
+#[doc = "EUSCI_B3"]
+pub mod eusci_b3;
+#[doc = "REF_A"]
+pub struct REF_A {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for REF_A {}
+impl REF_A {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const ref_a::RegisterBlock {
+        1073754112 as *const _
+    }
+}
+impl Deref for REF_A {
+    type Target = ref_a::RegisterBlock;
+    fn deref(&self) -> &ref_a::RegisterBlock {
+        unsafe { &*REF_A::ptr() }
+    }
+}
+#[doc = "REF_A"]
+pub mod ref_a;
+#[doc = "COMP_E0"]
+pub struct COMP_E0 {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for COMP_E0 {}
+impl COMP_E0 {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const comp_e0::RegisterBlock {
+        1073755136 as *const _
+    }
+}
+impl Deref for COMP_E0 {
+    type Target = comp_e0::RegisterBlock;
+    fn deref(&self) -> &comp_e0::RegisterBlock {
+        unsafe { &*COMP_E0::ptr() }
+    }
+}
+#[doc = "COMP_E0"]
+pub mod comp_e0;
+#[doc = "COMP_E1"]
+pub struct COMP_E1 {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for COMP_E1 {}
+impl COMP_E1 {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const comp_e1::RegisterBlock {
+        1073756160 as *const _
+    }
+}
+impl Deref for COMP_E1 {
+    type Target = comp_e1::RegisterBlock;
+    fn deref(&self) -> &comp_e1::RegisterBlock {
+        unsafe { &*COMP_E1::ptr() }
+    }
+}
+#[doc = "COMP_E1"]
+pub mod comp_e1;
+#[doc = "AES256"]
+pub struct AES256 {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for AES256 {}
+impl AES256 {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const aes256::RegisterBlock {
+        1073757184 as *const _
+    }
+}
+impl Deref for AES256 {
+    type Target = aes256::RegisterBlock;
+    fn deref(&self) -> &aes256::RegisterBlock {
+        unsafe { &*AES256::ptr() }
+    }
+}
+#[doc = "AES256"]
+pub mod aes256;
+#[doc = "CRC32"]
+pub struct CRC32 {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for CRC32 {}
+impl CRC32 {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const crc32::RegisterBlock {
+        1073758208 as *const _
+    }
+}
+impl Deref for CRC32 {
+    type Target = crc32::RegisterBlock;
+    fn deref(&self) -> &crc32::RegisterBlock {
+        unsafe { &*CRC32::ptr() }
+    }
+}
+#[doc = "CRC32"]
+pub mod crc32;
+#[doc = "RTC_C"]
+pub struct RTC_C {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for RTC_C {}
+impl RTC_C {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const rtc_c::RegisterBlock {
+        1073759232 as *const _
+    }
+}
+impl Deref for RTC_C {
+    type Target = rtc_c::RegisterBlock;
+    fn deref(&self) -> &rtc_c::RegisterBlock {
+        unsafe { &*RTC_C::ptr() }
+    }
+}
+#[doc = "RTC_C"]
+pub mod rtc_c;
+#[doc = "WDT_A"]
+pub struct WDT_A {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for WDT_A {}
+impl WDT_A {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const wdt_a::RegisterBlock {
+        1073760256 as *const _
+    }
+}
+impl Deref for WDT_A {
+    type Target = wdt_a::RegisterBlock;
+    fn deref(&self) -> &wdt_a::RegisterBlock {
+        unsafe { &*WDT_A::ptr() }
+    }
+}
+#[doc = "WDT_A"]
+pub mod wdt_a;
+#[doc = "DIO"]
+pub struct DIO {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for DIO {}
+impl DIO {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const dio::RegisterBlock {
+        1073761280 as *const _
+    }
+}
+impl Deref for DIO {
+    type Target = dio::RegisterBlock;
+    fn deref(&self) -> &dio::RegisterBlock {
+        unsafe { &*DIO::ptr() }
+    }
+}
+#[doc = "DIO"]
+pub mod dio;
+#[doc = "PMAP"]
+pub struct PMAP {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for PMAP {}
+impl PMAP {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const pmap::RegisterBlock {
+        1073762304 as *const _
+    }
+}
+impl Deref for PMAP {
+    type Target = pmap::RegisterBlock;
+    fn deref(&self) -> &pmap::RegisterBlock {
+        unsafe { &*PMAP::ptr() }
+    }
+}
+#[doc = "PMAP"]
+pub mod pmap;
+#[doc = "CAPTIO0"]
+pub struct CAPTIO0 {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for CAPTIO0 {}
+impl CAPTIO0 {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const captio0::RegisterBlock {
+        1073763328 as *const _
+    }
+}
+impl Deref for CAPTIO0 {
+    type Target = captio0::RegisterBlock;
+    fn deref(&self) -> &captio0::RegisterBlock {
+        unsafe { &*CAPTIO0::ptr() }
+    }
+}
+#[doc = "CAPTIO0"]
+pub mod captio0;
+#[doc = "CAPTIO1"]
+pub struct CAPTIO1 {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for CAPTIO1 {}
+impl CAPTIO1 {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const captio1::RegisterBlock {
+        1073764352 as *const _
+    }
+}
+impl Deref for CAPTIO1 {
+    type Target = captio1::RegisterBlock;
+    fn deref(&self) -> &captio1::RegisterBlock {
+        unsafe { &*CAPTIO1::ptr() }
+    }
+}
+#[doc = "CAPTIO1"]
+pub mod captio1;
+#[doc = "TIMER32"]
+pub struct TIMER32 {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for TIMER32 {}
+impl TIMER32 {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const timer32::RegisterBlock {
+        1073790976 as *const _
+    }
+}
+impl Deref for TIMER32 {
+    type Target = timer32::RegisterBlock;
+    fn deref(&self) -> &timer32::RegisterBlock {
+        unsafe { &*TIMER32::ptr() }
+    }
+}
+#[doc = "TIMER32"]
+pub mod timer32;
+#[doc = "DMA"]
+pub struct DMA {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for DMA {}
+impl DMA {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const dma::RegisterBlock {
+        1073799168 as *const _
+    }
+}
+impl Deref for DMA {
+    type Target = dma::RegisterBlock;
+    fn deref(&self) -> &dma::RegisterBlock {
+        unsafe { &*DMA::ptr() }
+    }
+}
+#[doc = "DMA"]
+pub mod dma;
+#[doc = "PCM"]
+pub struct PCM {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for PCM {}
+impl PCM {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const pcm::RegisterBlock {
+        1073807360 as *const _
+    }
+}
+impl Deref for PCM {
+    type Target = pcm::RegisterBlock;
+    fn deref(&self) -> &pcm::RegisterBlock {
+        unsafe { &*PCM::ptr() }
+    }
+}
+#[doc = "PCM"]
+pub mod pcm;
+#[doc = "CS"]
+pub struct CS {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for CS {}
+impl CS {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const cs::RegisterBlock {
+        1073808384 as *const _
+    }
+}
+impl Deref for CS {
+    type Target = cs::RegisterBlock;
+    fn deref(&self) -> &cs::RegisterBlock {
+        unsafe { &*CS::ptr() }
+    }
+}
+#[doc = "CS"]
+pub mod cs;
+#[doc = "PSS"]
+pub struct PSS {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for PSS {}
+impl PSS {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const pss::RegisterBlock {
+        1073809408 as *const _
+    }
+}
+impl Deref for PSS {
+    type Target = pss::RegisterBlock;
+    fn deref(&self) -> &pss::RegisterBlock {
+        unsafe { &*PSS::ptr() }
+    }
+}
+#[doc = "PSS"]
+pub mod pss;
+#[doc = "FLCTL"]
+pub struct FLCTL {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for FLCTL {}
+impl FLCTL {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const flctl::RegisterBlock {
+        1073811456 as *const _
+    }
+}
+impl Deref for FLCTL {
+    type Target = flctl::RegisterBlock;
+    fn deref(&self) -> &flctl::RegisterBlock {
+        unsafe { &*FLCTL::ptr() }
+    }
+}
+#[doc = "FLCTL"]
+pub mod flctl;
+#[doc = "ADC14"]
+pub struct ADC14 {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for ADC14 {}
+impl ADC14 {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const adc14::RegisterBlock {
+        1073815552 as *const _
+    }
+}
+impl Deref for ADC14 {
+    type Target = adc14::RegisterBlock;
+    fn deref(&self) -> &adc14::RegisterBlock {
+        unsafe { &*ADC14::ptr() }
+    }
+}
+#[doc = "ADC14"]
+pub mod adc14;
+#[doc = "System Control Space for ARM core: SCnSCB, SCB, SysTick, NVIC, CoreDebug, MPU, FPU"]
+pub struct SYSTEMCONTROLSPACE {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for SYSTEMCONTROLSPACE {}
+impl SYSTEMCONTROLSPACE {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const system_control_space::RegisterBlock {
+        3758153728 as *const _
+    }
+}
+impl Deref for SYSTEMCONTROLSPACE {
+    type Target = system_control_space::RegisterBlock;
+    fn deref(&self) -> &system_control_space::RegisterBlock {
+        unsafe { &*SYSTEMCONTROLSPACE::ptr() }
+    }
+}
+#[doc = "System Control Space for ARM core: SCnSCB, SCB, SysTick, NVIC, CoreDebug, MPU, FPU"]
+pub mod system_control_space;
+#[doc = "RSTCTL"]
+pub struct RSTCTL {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for RSTCTL {}
+impl RSTCTL {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const rstctl::RegisterBlock {
+        3758366720 as *const _
+    }
+}
+impl Deref for RSTCTL {
+    type Target = rstctl::RegisterBlock;
+    fn deref(&self) -> &rstctl::RegisterBlock {
+        unsafe { &*RSTCTL::ptr() }
+    }
+}
+#[doc = "RSTCTL"]
+pub mod rstctl;
+#[doc = "SYSCTL"]
+pub struct SYSCTL {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for SYSCTL {}
+impl SYSCTL {
+    #[doc = r" Returns a pointer to the register block"]
+    pub fn ptr() -> *const sysctl::RegisterBlock {
+        3758370816 as *const _
+    }
+}
+impl Deref for SYSCTL {
+    type Target = sysctl::RegisterBlock;
+    fn deref(&self) -> &sysctl::RegisterBlock {
+        unsafe { &*SYSCTL::ptr() }
+    }
+}
+#[doc = "SYSCTL"]
+pub mod sysctl;
+#[allow(renamed_and_removed_lints)]
+#[allow(private_no_mangle_statics)]
+#[no_mangle]
+static mut DEVICE_PERIPHERALS: bool = false;
+#[doc = r" All the peripherals"]
+#[allow(non_snake_case)]
+pub struct Peripherals {
+    #[doc = "TLV"]
+    pub TLV: TLV,
+    #[doc = "TIMER_A0"]
+    pub TIMER_A0: TIMER_A0,
+    #[doc = "TIMER_A1"]
+    pub TIMER_A1: TIMER_A1,
+    #[doc = "TIMER_A2"]
+    pub TIMER_A2: TIMER_A2,
+    #[doc = "TIMER_A3"]
+    pub TIMER_A3: TIMER_A3,
+    #[doc = "EUSCI_A0"]
+    pub EUSCI_A0: EUSCI_A0,
+    #[doc = "EUSCI_A1"]
+    pub EUSCI_A1: EUSCI_A1,
+    #[doc = "EUSCI_A2"]
+    pub EUSCI_A2: EUSCI_A2,
+    #[doc = "EUSCI_A3"]
+    pub EUSCI_A3: EUSCI_A3,
+    #[doc = "EUSCI_B0"]
+    pub EUSCI_B0: EUSCI_B0,
+    #[doc = "EUSCI_B1"]
+    pub EUSCI_B1: EUSCI_B1,
+    #[doc = "EUSCI_B2"]
+    pub EUSCI_B2: EUSCI_B2,
+    #[doc = "EUSCI_B3"]
+    pub EUSCI_B3: EUSCI_B3,
+    #[doc = "REF_A"]
+    pub REF_A: REF_A,
+    #[doc = "COMP_E0"]
+    pub COMP_E0: COMP_E0,
+    #[doc = "COMP_E1"]
+    pub COMP_E1: COMP_E1,
+    #[doc = "AES256"]
+    pub AES256: AES256,
+    #[doc = "CRC32"]
+    pub CRC32: CRC32,
+    #[doc = "RTC_C"]
+    pub RTC_C: RTC_C,
+    #[doc = "WDT_A"]
+    pub WDT_A: WDT_A,
+    #[doc = "DIO"]
+    pub DIO: DIO,
+    #[doc = "PMAP"]
+    pub PMAP: PMAP,
+    #[doc = "CAPTIO0"]
+    pub CAPTIO0: CAPTIO0,
+    #[doc = "CAPTIO1"]
+    pub CAPTIO1: CAPTIO1,
+    #[doc = "TIMER32"]
+    pub TIMER32: TIMER32,
+    #[doc = "DMA"]
+    pub DMA: DMA,
+    #[doc = "PCM"]
+    pub PCM: PCM,
+    #[doc = "CS"]
+    pub CS: CS,
+    #[doc = "PSS"]
+    pub PSS: PSS,
+    #[doc = "FLCTL"]
+    pub FLCTL: FLCTL,
+    #[doc = "ADC14"]
+    pub ADC14: ADC14,
+    #[doc = "SYSTEMCONTROLSPACE"]
+    pub SYSTEMCONTROLSPACE: SYSTEMCONTROLSPACE,
+    #[doc = "RSTCTL"]
+    pub RSTCTL: RSTCTL,
+    #[doc = "SYSCTL"]
+    pub SYSCTL: SYSCTL,
+}
+impl Peripherals {
+    #[doc = r" Returns all the peripherals *once*"]
+    #[inline]
+    pub fn take() -> Option<Self> {
+        cortex_m::interrupt::free(|_| {
+            if unsafe { DEVICE_PERIPHERALS } {
+                None
+            } else {
+                Some(unsafe { Peripherals::steal() })
+            }
+        })
+    }
+    #[doc = r" Unchecked version of `Peripherals::take`"]
+    pub unsafe fn steal() -> Self {
+        debug_assert!(!DEVICE_PERIPHERALS);
+        DEVICE_PERIPHERALS = true;
+        Peripherals {
+            TLV: TLV {
+                _marker: PhantomData,
+            },
+            TIMER_A0: TIMER_A0 {
+                _marker: PhantomData,
+            },
+            TIMER_A1: TIMER_A1 {
+                _marker: PhantomData,
+            },
+            TIMER_A2: TIMER_A2 {
+                _marker: PhantomData,
+            },
+            TIMER_A3: TIMER_A3 {
+                _marker: PhantomData,
+            },
+            EUSCI_A0: EUSCI_A0 {
+                _marker: PhantomData,
+            },
+            EUSCI_A1: EUSCI_A1 {
+                _marker: PhantomData,
+            },
+            EUSCI_A2: EUSCI_A2 {
+                _marker: PhantomData,
+            },
+            EUSCI_A3: EUSCI_A3 {
+                _marker: PhantomData,
+            },
+            EUSCI_B0: EUSCI_B0 {
+                _marker: PhantomData,
+            },
+            EUSCI_B1: EUSCI_B1 {
+                _marker: PhantomData,
+            },
+            EUSCI_B2: EUSCI_B2 {
+                _marker: PhantomData,
+            },
+            EUSCI_B3: EUSCI_B3 {
+                _marker: PhantomData,
+            },
+            REF_A: REF_A {
+                _marker: PhantomData,
+            },
+            COMP_E0: COMP_E0 {
+                _marker: PhantomData,
+            },
+            COMP_E1: COMP_E1 {
+                _marker: PhantomData,
+            },
+            AES256: AES256 {
+                _marker: PhantomData,
+            },
+            CRC32: CRC32 {
+                _marker: PhantomData,
+            },
+            RTC_C: RTC_C {
+                _marker: PhantomData,
+            },
+            WDT_A: WDT_A {
+                _marker: PhantomData,
+            },
+            DIO: DIO {
+                _marker: PhantomData,
+            },
+            PMAP: PMAP {
+                _marker: PhantomData,
+            },
+            CAPTIO0: CAPTIO0 {
+                _marker: PhantomData,
+            },
+            CAPTIO1: CAPTIO1 {
+                _marker: PhantomData,
+            },
+            TIMER32: TIMER32 {
+                _marker: PhantomData,
+            },
+            DMA: DMA {
+                _marker: PhantomData,
+            },
+            PCM: PCM {
+                _marker: PhantomData,
+            },
+            CS: CS {
+                _marker: PhantomData,
+            },
+            PSS: PSS {
+                _marker: PhantomData,
+            },
+            FLCTL: FLCTL {
+                _marker: PhantomData,
+            },
+            ADC14: ADC14 {
+                _marker: PhantomData,
+            },
+            SYSTEMCONTROLSPACE: SYSTEMCONTROLSPACE {
+                _marker: PhantomData,
+            },
+            RSTCTL: RSTCTL {
+                _marker: PhantomData,
+            },
+            SYSCTL: SYSCTL {
+                _marker: PhantomData,
+            },
+        }
+    }
+}
diff --git a/example-source/msp432p401r/src/pcm.rs b/example-source/msp432p401r/src/pcm.rs
new file mode 100644
index 0000000..42b0c8f
--- /dev/null
+++ b/example-source/msp432p401r/src/pcm.rs
@@ -0,0 +1,44 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - Control 0 Register"]
+    pub pcmctl0: PCMCTL0,
+    #[doc = "0x04 - Control 1 Register"]
+    pub pcmctl1: PCMCTL1,
+    #[doc = "0x08 - Interrupt Enable Register"]
+    pub pcmie: PCMIE,
+    #[doc = "0x0c - Interrupt Flag Register"]
+    pub pcmifg: PCMIFG,
+    #[doc = "0x10 - Clear Interrupt Flag Register"]
+    pub pcmclrifg: PCMCLRIFG,
+}
+#[doc = "Control 0 Register"]
+pub struct PCMCTL0 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Control 0 Register"]
+pub mod pcmctl0;
+#[doc = "Control 1 Register"]
+pub struct PCMCTL1 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Control 1 Register"]
+pub mod pcmctl1;
+#[doc = "Interrupt Enable Register"]
+pub struct PCMIE {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Interrupt Enable Register"]
+pub mod pcmie;
+#[doc = "Interrupt Flag Register"]
+pub struct PCMIFG {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Interrupt Flag Register"]
+pub mod pcmifg;
+#[doc = "Clear Interrupt Flag Register"]
+pub struct PCMCLRIFG {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Clear Interrupt Flag Register"]
+pub mod pcmclrifg;
diff --git a/example-source/msp432p401r/src/pcm/pcmclrifg.rs b/example-source/msp432p401r/src/pcm/pcmclrifg.rs
new file mode 100644
index 0000000..267deb6
--- /dev/null
+++ b/example-source/msp432p401r/src/pcm/pcmclrifg.rs
@@ -0,0 +1,141 @@
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::PCMCLRIFG {
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLR_LPM_INVALID_TR_IFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLR_LPM_INVALID_TR_IFGW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLR_LPM_INVALID_CLK_IFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLR_LPM_INVALID_CLK_IFGW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLR_AM_INVALID_TR_IFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLR_AM_INVALID_TR_IFGW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLR_DCDC_ERROR_IFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLR_DCDC_ERROR_IFGW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Clear LPM invalid transition flag"]
+    #[inline]
+    pub fn clr_lpm_invalid_tr_ifg(&mut self) -> _CLR_LPM_INVALID_TR_IFGW {
+        _CLR_LPM_INVALID_TR_IFGW { w: self }
+    }
+    #[doc = "Bit 1 - Clear LPM invalid clock flag"]
+    #[inline]
+    pub fn clr_lpm_invalid_clk_ifg(&mut self) -> _CLR_LPM_INVALID_CLK_IFGW {
+        _CLR_LPM_INVALID_CLK_IFGW { w: self }
+    }
+    #[doc = "Bit 2 - Clear active mode invalid transition flag"]
+    #[inline]
+    pub fn clr_am_invalid_tr_ifg(&mut self) -> _CLR_AM_INVALID_TR_IFGW {
+        _CLR_AM_INVALID_TR_IFGW { w: self }
+    }
+    #[doc = "Bit 6 - Clear DC-DC error flag"]
+    #[inline]
+    pub fn clr_dcdc_error_ifg(&mut self) -> _CLR_DCDC_ERROR_IFGW {
+        _CLR_DCDC_ERROR_IFGW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pcm/pcmctl0.rs b/example-source/msp432p401r/src/pcm/pcmctl0.rs
new file mode 100644
index 0000000..c297021
--- /dev/null
+++ b/example-source/msp432p401r/src/pcm/pcmctl0.rs
@@ -0,0 +1,545 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::PCMCTL0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `AMR`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum AMRR {
+    #[doc = "LDO based Active Mode at Core voltage setting 0."]
+    AMR_0,
+    #[doc = "LDO based Active Mode at Core voltage setting 1."]
+    AMR_1,
+    #[doc = "DC-DC based Active Mode at Core voltage setting 0."]
+    AMR_4,
+    #[doc = "DC-DC based Active Mode at Core voltage setting 1."]
+    AMR_5,
+    #[doc = "Low-Frequency Active Mode at Core voltage setting 0."]
+    AMR_8,
+    #[doc = "Low-Frequency Active Mode at Core voltage setting 1."]
+    AMR_9,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl AMRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            AMRR::AMR_0 => 0,
+            AMRR::AMR_1 => 1,
+            AMRR::AMR_4 => 4,
+            AMRR::AMR_5 => 5,
+            AMRR::AMR_8 => 8,
+            AMRR::AMR_9 => 9,
+            AMRR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> AMRR {
+        match value {
+            0 => AMRR::AMR_0,
+            1 => AMRR::AMR_1,
+            4 => AMRR::AMR_4,
+            5 => AMRR::AMR_5,
+            8 => AMRR::AMR_8,
+            9 => AMRR::AMR_9,
+            i => AMRR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `AMR_0`"]
+    #[inline]
+    pub fn is_amr_0(&self) -> bool {
+        *self == AMRR::AMR_0
+    }
+    #[doc = "Checks if the value of the field is `AMR_1`"]
+    #[inline]
+    pub fn is_amr_1(&self) -> bool {
+        *self == AMRR::AMR_1
+    }
+    #[doc = "Checks if the value of the field is `AMR_4`"]
+    #[inline]
+    pub fn is_amr_4(&self) -> bool {
+        *self == AMRR::AMR_4
+    }
+    #[doc = "Checks if the value of the field is `AMR_5`"]
+    #[inline]
+    pub fn is_amr_5(&self) -> bool {
+        *self == AMRR::AMR_5
+    }
+    #[doc = "Checks if the value of the field is `AMR_8`"]
+    #[inline]
+    pub fn is_amr_8(&self) -> bool {
+        *self == AMRR::AMR_8
+    }
+    #[doc = "Checks if the value of the field is `AMR_9`"]
+    #[inline]
+    pub fn is_amr_9(&self) -> bool {
+        *self == AMRR::AMR_9
+    }
+}
+#[doc = "Possible values of the field `LPMR`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LPMRR {
+    #[doc = "LPM3. Core voltage setting is similar to the mode from which LPM3 is entered."]
+    LPMR_0,
+    #[doc = "LPM3.5. Core voltage setting 0."]
+    LPMR_10,
+    #[doc = "LPM4.5"]
+    LPMR_12,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl LPMRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            LPMRR::LPMR_0 => 0,
+            LPMRR::LPMR_10 => 10,
+            LPMRR::LPMR_12 => 12,
+            LPMRR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> LPMRR {
+        match value {
+            0 => LPMRR::LPMR_0,
+            10 => LPMRR::LPMR_10,
+            12 => LPMRR::LPMR_12,
+            i => LPMRR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `LPMR_0`"]
+    #[inline]
+    pub fn is_lpmr_0(&self) -> bool {
+        *self == LPMRR::LPMR_0
+    }
+    #[doc = "Checks if the value of the field is `LPMR_10`"]
+    #[inline]
+    pub fn is_lpmr_10(&self) -> bool {
+        *self == LPMRR::LPMR_10
+    }
+    #[doc = "Checks if the value of the field is `LPMR_12`"]
+    #[inline]
+    pub fn is_lpmr_12(&self) -> bool {
+        *self == LPMRR::LPMR_12
+    }
+}
+#[doc = "Possible values of the field `CPM`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CPMR {
+    #[doc = "LDO based Active Mode at Core voltage setting 0."]
+    CPM_0,
+    #[doc = "LDO based Active Mode at Core voltage setting 1."]
+    CPM_1,
+    #[doc = "DC-DC based Active Mode at Core voltage setting 0."]
+    CPM_4,
+    #[doc = "DC-DC based Active Mode at Core voltage setting 1."]
+    CPM_5,
+    #[doc = "Low-Frequency Active Mode at Core voltage setting 0."]
+    CPM_8,
+    #[doc = "Low-Frequency Active Mode at Core voltage setting 1."]
+    CPM_9,
+    #[doc = "LDO based LPM0 at Core voltage setting 0."]
+    CPM_16,
+    #[doc = "LDO based LPM0 at Core voltage setting 1."]
+    CPM_17,
+    #[doc = "DC-DC based LPM0 at Core voltage setting 0."]
+    CPM_20,
+    #[doc = "DC-DC based LPM0 at Core voltage setting 1."]
+    CPM_21,
+    #[doc = "Low-Frequency LPM0 at Core voltage setting 0."]
+    CPM_24,
+    #[doc = "Low-Frequency LPM0 at Core voltage setting 1."]
+    CPM_25,
+    #[doc = "LPM3"]
+    CPM_32,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl CPMR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            CPMR::CPM_0 => 0,
+            CPMR::CPM_1 => 1,
+            CPMR::CPM_4 => 4,
+            CPMR::CPM_5 => 5,
+            CPMR::CPM_8 => 8,
+            CPMR::CPM_9 => 9,
+            CPMR::CPM_16 => 16,
+            CPMR::CPM_17 => 17,
+            CPMR::CPM_20 => 20,
+            CPMR::CPM_21 => 21,
+            CPMR::CPM_24 => 24,
+            CPMR::CPM_25 => 25,
+            CPMR::CPM_32 => 32,
+            CPMR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> CPMR {
+        match value {
+            0 => CPMR::CPM_0,
+            1 => CPMR::CPM_1,
+            4 => CPMR::CPM_4,
+            5 => CPMR::CPM_5,
+            8 => CPMR::CPM_8,
+            9 => CPMR::CPM_9,
+            16 => CPMR::CPM_16,
+            17 => CPMR::CPM_17,
+            20 => CPMR::CPM_20,
+            21 => CPMR::CPM_21,
+            24 => CPMR::CPM_24,
+            25 => CPMR::CPM_25,
+            32 => CPMR::CPM_32,
+            i => CPMR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `CPM_0`"]
+    #[inline]
+    pub fn is_cpm_0(&self) -> bool {
+        *self == CPMR::CPM_0
+    }
+    #[doc = "Checks if the value of the field is `CPM_1`"]
+    #[inline]
+    pub fn is_cpm_1(&self) -> bool {
+        *self == CPMR::CPM_1
+    }
+    #[doc = "Checks if the value of the field is `CPM_4`"]
+    #[inline]
+    pub fn is_cpm_4(&self) -> bool {
+        *self == CPMR::CPM_4
+    }
+    #[doc = "Checks if the value of the field is `CPM_5`"]
+    #[inline]
+    pub fn is_cpm_5(&self) -> bool {
+        *self == CPMR::CPM_5
+    }
+    #[doc = "Checks if the value of the field is `CPM_8`"]
+    #[inline]
+    pub fn is_cpm_8(&self) -> bool {
+        *self == CPMR::CPM_8
+    }
+    #[doc = "Checks if the value of the field is `CPM_9`"]
+    #[inline]
+    pub fn is_cpm_9(&self) -> bool {
+        *self == CPMR::CPM_9
+    }
+    #[doc = "Checks if the value of the field is `CPM_16`"]
+    #[inline]
+    pub fn is_cpm_16(&self) -> bool {
+        *self == CPMR::CPM_16
+    }
+    #[doc = "Checks if the value of the field is `CPM_17`"]
+    #[inline]
+    pub fn is_cpm_17(&self) -> bool {
+        *self == CPMR::CPM_17
+    }
+    #[doc = "Checks if the value of the field is `CPM_20`"]
+    #[inline]
+    pub fn is_cpm_20(&self) -> bool {
+        *self == CPMR::CPM_20
+    }
+    #[doc = "Checks if the value of the field is `CPM_21`"]
+    #[inline]
+    pub fn is_cpm_21(&self) -> bool {
+        *self == CPMR::CPM_21
+    }
+    #[doc = "Checks if the value of the field is `CPM_24`"]
+    #[inline]
+    pub fn is_cpm_24(&self) -> bool {
+        *self == CPMR::CPM_24
+    }
+    #[doc = "Checks if the value of the field is `CPM_25`"]
+    #[inline]
+    pub fn is_cpm_25(&self) -> bool {
+        *self == CPMR::CPM_25
+    }
+    #[doc = "Checks if the value of the field is `CPM_32`"]
+    #[inline]
+    pub fn is_cpm_32(&self) -> bool {
+        *self == CPMR::CPM_32
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PCMKEYR {
+    bits: u16,
+}
+impl PCMKEYR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = "Values that can be written to the field `AMR`"]
+pub enum AMRW {
+    #[doc = "LDO based Active Mode at Core voltage setting 0."]
+    AMR_0,
+    #[doc = "LDO based Active Mode at Core voltage setting 1."]
+    AMR_1,
+    #[doc = "DC-DC based Active Mode at Core voltage setting 0."]
+    AMR_4,
+    #[doc = "DC-DC based Active Mode at Core voltage setting 1."]
+    AMR_5,
+    #[doc = "Low-Frequency Active Mode at Core voltage setting 0."]
+    AMR_8,
+    #[doc = "Low-Frequency Active Mode at Core voltage setting 1."]
+    AMR_9,
+}
+impl AMRW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            AMRW::AMR_0 => 0,
+            AMRW::AMR_1 => 1,
+            AMRW::AMR_4 => 4,
+            AMRW::AMR_5 => 5,
+            AMRW::AMR_8 => 8,
+            AMRW::AMR_9 => 9,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AMRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AMRW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: AMRW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "LDO based Active Mode at Core voltage setting 0."]
+    #[inline]
+    pub fn amr_0(self) -> &'a mut W {
+        self.variant(AMRW::AMR_0)
+    }
+    #[doc = "LDO based Active Mode at Core voltage setting 1."]
+    #[inline]
+    pub fn amr_1(self) -> &'a mut W {
+        self.variant(AMRW::AMR_1)
+    }
+    #[doc = "DC-DC based Active Mode at Core voltage setting 0."]
+    #[inline]
+    pub fn amr_4(self) -> &'a mut W {
+        self.variant(AMRW::AMR_4)
+    }
+    #[doc = "DC-DC based Active Mode at Core voltage setting 1."]
+    #[inline]
+    pub fn amr_5(self) -> &'a mut W {
+        self.variant(AMRW::AMR_5)
+    }
+    #[doc = "Low-Frequency Active Mode at Core voltage setting 0."]
+    #[inline]
+    pub fn amr_8(self) -> &'a mut W {
+        self.variant(AMRW::AMR_8)
+    }
+    #[doc = "Low-Frequency Active Mode at Core voltage setting 1."]
+    #[inline]
+    pub fn amr_9(self) -> &'a mut W {
+        self.variant(AMRW::AMR_9)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `LPMR`"]
+pub enum LPMRW {
+    #[doc = "LPM3. Core voltage setting is similar to the mode from which LPM3 is entered."]
+    LPMR_0,
+    #[doc = "LPM3.5. Core voltage setting 0."]
+    LPMR_10,
+    #[doc = "LPM4.5"]
+    LPMR_12,
+}
+impl LPMRW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            LPMRW::LPMR_0 => 0,
+            LPMRW::LPMR_10 => 10,
+            LPMRW::LPMR_12 => 12,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _LPMRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _LPMRW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: LPMRW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "LPM3. Core voltage setting is similar to the mode from which LPM3 is entered."]
+    #[inline]
+    pub fn lpmr_0(self) -> &'a mut W {
+        self.variant(LPMRW::LPMR_0)
+    }
+    #[doc = "LPM3.5. Core voltage setting 0."]
+    #[inline]
+    pub fn lpmr_10(self) -> &'a mut W {
+        self.variant(LPMRW::LPMR_10)
+    }
+    #[doc = "LPM4.5"]
+    #[inline]
+    pub fn lpmr_12(self) -> &'a mut W {
+        self.variant(LPMRW::LPMR_12)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PCMKEYW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PCMKEYW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 16;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:3 - Active Mode Request"]
+    #[inline]
+    pub fn amr(&self) -> AMRR {
+        AMRR::_from({
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 4:7 - Low Power Mode Request"]
+    #[inline]
+    pub fn lpmr(&self) -> LPMRR {
+        LPMRR::_from({
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 8:13 - Current Power Mode"]
+    #[inline]
+    pub fn cpm(&self) -> CPMR {
+        CPMR::_from({
+            const MASK: u8 = 63;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 16:31 - PCM key"]
+    #[inline]
+    pub fn pcmkey(&self) -> PCMKEYR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        PCMKEYR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 2778071040 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:3 - Active Mode Request"]
+    #[inline]
+    pub fn amr(&mut self) -> _AMRW {
+        _AMRW { w: self }
+    }
+    #[doc = "Bits 4:7 - Low Power Mode Request"]
+    #[inline]
+    pub fn lpmr(&mut self) -> _LPMRW {
+        _LPMRW { w: self }
+    }
+    #[doc = "Bits 16:31 - PCM key"]
+    #[inline]
+    pub fn pcmkey(&mut self) -> _PCMKEYW {
+        _PCMKEYW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pcm/pcmctl1.rs b/example-source/msp432p401r/src/pcm/pcmctl1.rs
new file mode 100644
index 0000000..ecddfbe
--- /dev/null
+++ b/example-source/msp432p401r/src/pcm/pcmctl1.rs
@@ -0,0 +1,521 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::PCMCTL1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `LOCKLPM5`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LOCKLPM5R {
+    #[doc = "LPMx.5 configuration defaults to reset condition"]
+    LOCKLPM5_0,
+    #[doc = "LPMx.5 configuration remains locked during LPMx.5 entry and exit"]
+    LOCKLPM5_1,
+}
+impl LOCKLPM5R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            LOCKLPM5R::LOCKLPM5_0 => false,
+            LOCKLPM5R::LOCKLPM5_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> LOCKLPM5R {
+        match value {
+            false => LOCKLPM5R::LOCKLPM5_0,
+            true => LOCKLPM5R::LOCKLPM5_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `LOCKLPM5_0`"]
+    #[inline]
+    pub fn is_locklpm5_0(&self) -> bool {
+        *self == LOCKLPM5R::LOCKLPM5_0
+    }
+    #[doc = "Checks if the value of the field is `LOCKLPM5_1`"]
+    #[inline]
+    pub fn is_locklpm5_1(&self) -> bool {
+        *self == LOCKLPM5R::LOCKLPM5_1
+    }
+}
+#[doc = "Possible values of the field `LOCKBKUP`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LOCKBKUPR {
+    #[doc = "Backup domain configuration defaults to reset condition"]
+    LOCKBKUP_0,
+    #[doc = "Backup domain configuration remains locked during LPM3.5 entry and exit"]
+    LOCKBKUP_1,
+}
+impl LOCKBKUPR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            LOCKBKUPR::LOCKBKUP_0 => false,
+            LOCKBKUPR::LOCKBKUP_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> LOCKBKUPR {
+        match value {
+            false => LOCKBKUPR::LOCKBKUP_0,
+            true => LOCKBKUPR::LOCKBKUP_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `LOCKBKUP_0`"]
+    #[inline]
+    pub fn is_lockbkup_0(&self) -> bool {
+        *self == LOCKBKUPR::LOCKBKUP_0
+    }
+    #[doc = "Checks if the value of the field is `LOCKBKUP_1`"]
+    #[inline]
+    pub fn is_lockbkup_1(&self) -> bool {
+        *self == LOCKBKUPR::LOCKBKUP_1
+    }
+}
+#[doc = "Possible values of the field `FORCE_LPM_ENTRY`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FORCE_LPM_ENTRYR {
+    #[doc = "PCM aborts LPM3/LPMx.5 transition if the active clock configuration does not meet the LPM3/LPMx.5 entry criteria. PCM generates the LPM_INVALID_CLK flag on abort to LPM3/LPMx.5 entry."]
+    FORCE_LPM_ENTRY_0,
+    #[doc = "PCM enters LPM3/LPMx.5 after shuting off the clocks forcefully. Application needs to ensure RTC and WDT are clocked using BCLK tree to keep these modules alive in LPM3/LPM3.5. In LPM4.5 all clocks are forcefully shutoff and the core voltage is turned off."]
+    FORCE_LPM_ENTRY_1,
+}
+impl FORCE_LPM_ENTRYR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            FORCE_LPM_ENTRYR::FORCE_LPM_ENTRY_0 => false,
+            FORCE_LPM_ENTRYR::FORCE_LPM_ENTRY_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> FORCE_LPM_ENTRYR {
+        match value {
+            false => FORCE_LPM_ENTRYR::FORCE_LPM_ENTRY_0,
+            true => FORCE_LPM_ENTRYR::FORCE_LPM_ENTRY_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `FORCE_LPM_ENTRY_0`"]
+    #[inline]
+    pub fn is_force_lpm_entry_0(&self) -> bool {
+        *self == FORCE_LPM_ENTRYR::FORCE_LPM_ENTRY_0
+    }
+    #[doc = "Checks if the value of the field is `FORCE_LPM_ENTRY_1`"]
+    #[inline]
+    pub fn is_force_lpm_entry_1(&self) -> bool {
+        *self == FORCE_LPM_ENTRYR::FORCE_LPM_ENTRY_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PMR_BUSYR {
+    bits: bool,
+}
+impl PMR_BUSYR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PCMKEYR {
+    bits: u16,
+}
+impl PCMKEYR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = "Values that can be written to the field `LOCKLPM5`"]
+pub enum LOCKLPM5W {
+    #[doc = "LPMx.5 configuration defaults to reset condition"]
+    LOCKLPM5_0,
+    #[doc = "LPMx.5 configuration remains locked during LPMx.5 entry and exit"]
+    LOCKLPM5_1,
+}
+impl LOCKLPM5W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            LOCKLPM5W::LOCKLPM5_0 => false,
+            LOCKLPM5W::LOCKLPM5_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _LOCKLPM5W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _LOCKLPM5W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: LOCKLPM5W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "LPMx.5 configuration defaults to reset condition"]
+    #[inline]
+    pub fn locklpm5_0(self) -> &'a mut W {
+        self.variant(LOCKLPM5W::LOCKLPM5_0)
+    }
+    #[doc = "LPMx.5 configuration remains locked during LPMx.5 entry and exit"]
+    #[inline]
+    pub fn locklpm5_1(self) -> &'a mut W {
+        self.variant(LOCKLPM5W::LOCKLPM5_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `LOCKBKUP`"]
+pub enum LOCKBKUPW {
+    #[doc = "Backup domain configuration defaults to reset condition"]
+    LOCKBKUP_0,
+    #[doc = "Backup domain configuration remains locked during LPM3.5 entry and exit"]
+    LOCKBKUP_1,
+}
+impl LOCKBKUPW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            LOCKBKUPW::LOCKBKUP_0 => false,
+            LOCKBKUPW::LOCKBKUP_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _LOCKBKUPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _LOCKBKUPW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: LOCKBKUPW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Backup domain configuration defaults to reset condition"]
+    #[inline]
+    pub fn lockbkup_0(self) -> &'a mut W {
+        self.variant(LOCKBKUPW::LOCKBKUP_0)
+    }
+    #[doc = "Backup domain configuration remains locked during LPM3.5 entry and exit"]
+    #[inline]
+    pub fn lockbkup_1(self) -> &'a mut W {
+        self.variant(LOCKBKUPW::LOCKBKUP_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `FORCE_LPM_ENTRY`"]
+pub enum FORCE_LPM_ENTRYW {
+    #[doc = "PCM aborts LPM3/LPMx.5 transition if the active clock configuration does not meet the LPM3/LPMx.5 entry criteria. PCM generates the LPM_INVALID_CLK flag on abort to LPM3/LPMx.5 entry."]
+    FORCE_LPM_ENTRY_0,
+    #[doc = "PCM enters LPM3/LPMx.5 after shuting off the clocks forcefully. Application needs to ensure RTC and WDT are clocked using BCLK tree to keep these modules alive in LPM3/LPM3.5. In LPM4.5 all clocks are forcefully shutoff and the core voltage is turned off."]
+    FORCE_LPM_ENTRY_1,
+}
+impl FORCE_LPM_ENTRYW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            FORCE_LPM_ENTRYW::FORCE_LPM_ENTRY_0 => false,
+            FORCE_LPM_ENTRYW::FORCE_LPM_ENTRY_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FORCE_LPM_ENTRYW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FORCE_LPM_ENTRYW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: FORCE_LPM_ENTRYW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "PCM aborts LPM3/LPMx.5 transition if the active clock configuration does not meet the LPM3/LPMx.5 entry criteria. PCM generates the LPM_INVALID_CLK flag on abort to LPM3/LPMx.5 entry."]
+    #[inline]
+    pub fn force_lpm_entry_0(self) -> &'a mut W {
+        self.variant(FORCE_LPM_ENTRYW::FORCE_LPM_ENTRY_0)
+    }
+    #[doc = "PCM enters LPM3/LPMx.5 after shuting off the clocks forcefully. Application needs to ensure RTC and WDT are clocked using BCLK tree to keep these modules alive in LPM3/LPM3.5. In LPM4.5 all clocks are forcefully shutoff and the core voltage is turned off."]
+    #[inline]
+    pub fn force_lpm_entry_1(self) -> &'a mut W {
+        self.variant(FORCE_LPM_ENTRYW::FORCE_LPM_ENTRY_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PMR_BUSYW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PMR_BUSYW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PCMKEYW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PCMKEYW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 16;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Lock LPM5"]
+    #[inline]
+    pub fn locklpm5(&self) -> LOCKLPM5R {
+        LOCKLPM5R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - Lock Backup"]
+    #[inline]
+    pub fn lockbkup(&self) -> LOCKBKUPR {
+        LOCKBKUPR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - Force LPM entry"]
+    #[inline]
+    pub fn force_lpm_entry(&self) -> FORCE_LPM_ENTRYR {
+        FORCE_LPM_ENTRYR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 8 - Power mode request busy flag"]
+    #[inline]
+    pub fn pmr_busy(&self) -> PMR_BUSYR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        PMR_BUSYR { bits }
+    }
+    #[doc = "Bits 16:31 - PCM key"]
+    #[inline]
+    pub fn pcmkey(&self) -> PCMKEYR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        PCMKEYR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 2778071040 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Lock LPM5"]
+    #[inline]
+    pub fn locklpm5(&mut self) -> _LOCKLPM5W {
+        _LOCKLPM5W { w: self }
+    }
+    #[doc = "Bit 1 - Lock Backup"]
+    #[inline]
+    pub fn lockbkup(&mut self) -> _LOCKBKUPW {
+        _LOCKBKUPW { w: self }
+    }
+    #[doc = "Bit 2 - Force LPM entry"]
+    #[inline]
+    pub fn force_lpm_entry(&mut self) -> _FORCE_LPM_ENTRYW {
+        _FORCE_LPM_ENTRYW { w: self }
+    }
+    #[doc = "Bit 8 - Power mode request busy flag"]
+    #[inline]
+    pub fn pmr_busy(&mut self) -> _PMR_BUSYW {
+        _PMR_BUSYW { w: self }
+    }
+    #[doc = "Bits 16:31 - PCM key"]
+    #[inline]
+    pub fn pcmkey(&mut self) -> _PCMKEYW {
+        _PCMKEYW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pcm/pcmie.rs b/example-source/msp432p401r/src/pcm/pcmie.rs
new file mode 100644
index 0000000..6a11653
--- /dev/null
+++ b/example-source/msp432p401r/src/pcm/pcmie.rs
@@ -0,0 +1,540 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::PCMIE {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `LPM_INVALID_TR_IE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LPM_INVALID_TR_IER {
+    #[doc = "Disabled"]
+    LPM_INVALID_TR_IE_0,
+    #[doc = "Enabled"]
+    LPM_INVALID_TR_IE_1,
+}
+impl LPM_INVALID_TR_IER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            LPM_INVALID_TR_IER::LPM_INVALID_TR_IE_0 => false,
+            LPM_INVALID_TR_IER::LPM_INVALID_TR_IE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> LPM_INVALID_TR_IER {
+        match value {
+            false => LPM_INVALID_TR_IER::LPM_INVALID_TR_IE_0,
+            true => LPM_INVALID_TR_IER::LPM_INVALID_TR_IE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `LPM_INVALID_TR_IE_0`"]
+    #[inline]
+    pub fn is_lpm_invalid_tr_ie_0(&self) -> bool {
+        *self == LPM_INVALID_TR_IER::LPM_INVALID_TR_IE_0
+    }
+    #[doc = "Checks if the value of the field is `LPM_INVALID_TR_IE_1`"]
+    #[inline]
+    pub fn is_lpm_invalid_tr_ie_1(&self) -> bool {
+        *self == LPM_INVALID_TR_IER::LPM_INVALID_TR_IE_1
+    }
+}
+#[doc = "Possible values of the field `LPM_INVALID_CLK_IE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LPM_INVALID_CLK_IER {
+    #[doc = "Disabled"]
+    LPM_INVALID_CLK_IE_0,
+    #[doc = "Enabled"]
+    LPM_INVALID_CLK_IE_1,
+}
+impl LPM_INVALID_CLK_IER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            LPM_INVALID_CLK_IER::LPM_INVALID_CLK_IE_0 => false,
+            LPM_INVALID_CLK_IER::LPM_INVALID_CLK_IE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> LPM_INVALID_CLK_IER {
+        match value {
+            false => LPM_INVALID_CLK_IER::LPM_INVALID_CLK_IE_0,
+            true => LPM_INVALID_CLK_IER::LPM_INVALID_CLK_IE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `LPM_INVALID_CLK_IE_0`"]
+    #[inline]
+    pub fn is_lpm_invalid_clk_ie_0(&self) -> bool {
+        *self == LPM_INVALID_CLK_IER::LPM_INVALID_CLK_IE_0
+    }
+    #[doc = "Checks if the value of the field is `LPM_INVALID_CLK_IE_1`"]
+    #[inline]
+    pub fn is_lpm_invalid_clk_ie_1(&self) -> bool {
+        *self == LPM_INVALID_CLK_IER::LPM_INVALID_CLK_IE_1
+    }
+}
+#[doc = "Possible values of the field `AM_INVALID_TR_IE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum AM_INVALID_TR_IER {
+    #[doc = "Disabled"]
+    AM_INVALID_TR_IE_0,
+    #[doc = "Enabled"]
+    AM_INVALID_TR_IE_1,
+}
+impl AM_INVALID_TR_IER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            AM_INVALID_TR_IER::AM_INVALID_TR_IE_0 => false,
+            AM_INVALID_TR_IER::AM_INVALID_TR_IE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> AM_INVALID_TR_IER {
+        match value {
+            false => AM_INVALID_TR_IER::AM_INVALID_TR_IE_0,
+            true => AM_INVALID_TR_IER::AM_INVALID_TR_IE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `AM_INVALID_TR_IE_0`"]
+    #[inline]
+    pub fn is_am_invalid_tr_ie_0(&self) -> bool {
+        *self == AM_INVALID_TR_IER::AM_INVALID_TR_IE_0
+    }
+    #[doc = "Checks if the value of the field is `AM_INVALID_TR_IE_1`"]
+    #[inline]
+    pub fn is_am_invalid_tr_ie_1(&self) -> bool {
+        *self == AM_INVALID_TR_IER::AM_INVALID_TR_IE_1
+    }
+}
+#[doc = "Possible values of the field `DCDC_ERROR_IE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DCDC_ERROR_IER {
+    #[doc = "Disabled"]
+    DCDC_ERROR_IE_0,
+    #[doc = "Enabled"]
+    DCDC_ERROR_IE_1,
+}
+impl DCDC_ERROR_IER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            DCDC_ERROR_IER::DCDC_ERROR_IE_0 => false,
+            DCDC_ERROR_IER::DCDC_ERROR_IE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> DCDC_ERROR_IER {
+        match value {
+            false => DCDC_ERROR_IER::DCDC_ERROR_IE_0,
+            true => DCDC_ERROR_IER::DCDC_ERROR_IE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DCDC_ERROR_IE_0`"]
+    #[inline]
+    pub fn is_dcdc_error_ie_0(&self) -> bool {
+        *self == DCDC_ERROR_IER::DCDC_ERROR_IE_0
+    }
+    #[doc = "Checks if the value of the field is `DCDC_ERROR_IE_1`"]
+    #[inline]
+    pub fn is_dcdc_error_ie_1(&self) -> bool {
+        *self == DCDC_ERROR_IER::DCDC_ERROR_IE_1
+    }
+}
+#[doc = "Values that can be written to the field `LPM_INVALID_TR_IE`"]
+pub enum LPM_INVALID_TR_IEW {
+    #[doc = "Disabled"]
+    LPM_INVALID_TR_IE_0,
+    #[doc = "Enabled"]
+    LPM_INVALID_TR_IE_1,
+}
+impl LPM_INVALID_TR_IEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            LPM_INVALID_TR_IEW::LPM_INVALID_TR_IE_0 => false,
+            LPM_INVALID_TR_IEW::LPM_INVALID_TR_IE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _LPM_INVALID_TR_IEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _LPM_INVALID_TR_IEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: LPM_INVALID_TR_IEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disabled"]
+    #[inline]
+    pub fn lpm_invalid_tr_ie_0(self) -> &'a mut W {
+        self.variant(LPM_INVALID_TR_IEW::LPM_INVALID_TR_IE_0)
+    }
+    #[doc = "Enabled"]
+    #[inline]
+    pub fn lpm_invalid_tr_ie_1(self) -> &'a mut W {
+        self.variant(LPM_INVALID_TR_IEW::LPM_INVALID_TR_IE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `LPM_INVALID_CLK_IE`"]
+pub enum LPM_INVALID_CLK_IEW {
+    #[doc = "Disabled"]
+    LPM_INVALID_CLK_IE_0,
+    #[doc = "Enabled"]
+    LPM_INVALID_CLK_IE_1,
+}
+impl LPM_INVALID_CLK_IEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            LPM_INVALID_CLK_IEW::LPM_INVALID_CLK_IE_0 => false,
+            LPM_INVALID_CLK_IEW::LPM_INVALID_CLK_IE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _LPM_INVALID_CLK_IEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _LPM_INVALID_CLK_IEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: LPM_INVALID_CLK_IEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disabled"]
+    #[inline]
+    pub fn lpm_invalid_clk_ie_0(self) -> &'a mut W {
+        self.variant(LPM_INVALID_CLK_IEW::LPM_INVALID_CLK_IE_0)
+    }
+    #[doc = "Enabled"]
+    #[inline]
+    pub fn lpm_invalid_clk_ie_1(self) -> &'a mut W {
+        self.variant(LPM_INVALID_CLK_IEW::LPM_INVALID_CLK_IE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `AM_INVALID_TR_IE`"]
+pub enum AM_INVALID_TR_IEW {
+    #[doc = "Disabled"]
+    AM_INVALID_TR_IE_0,
+    #[doc = "Enabled"]
+    AM_INVALID_TR_IE_1,
+}
+impl AM_INVALID_TR_IEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            AM_INVALID_TR_IEW::AM_INVALID_TR_IE_0 => false,
+            AM_INVALID_TR_IEW::AM_INVALID_TR_IE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AM_INVALID_TR_IEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AM_INVALID_TR_IEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: AM_INVALID_TR_IEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disabled"]
+    #[inline]
+    pub fn am_invalid_tr_ie_0(self) -> &'a mut W {
+        self.variant(AM_INVALID_TR_IEW::AM_INVALID_TR_IE_0)
+    }
+    #[doc = "Enabled"]
+    #[inline]
+    pub fn am_invalid_tr_ie_1(self) -> &'a mut W {
+        self.variant(AM_INVALID_TR_IEW::AM_INVALID_TR_IE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `DCDC_ERROR_IE`"]
+pub enum DCDC_ERROR_IEW {
+    #[doc = "Disabled"]
+    DCDC_ERROR_IE_0,
+    #[doc = "Enabled"]
+    DCDC_ERROR_IE_1,
+}
+impl DCDC_ERROR_IEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            DCDC_ERROR_IEW::DCDC_ERROR_IE_0 => false,
+            DCDC_ERROR_IEW::DCDC_ERROR_IE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DCDC_ERROR_IEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DCDC_ERROR_IEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: DCDC_ERROR_IEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disabled"]
+    #[inline]
+    pub fn dcdc_error_ie_0(self) -> &'a mut W {
+        self.variant(DCDC_ERROR_IEW::DCDC_ERROR_IE_0)
+    }
+    #[doc = "Enabled"]
+    #[inline]
+    pub fn dcdc_error_ie_1(self) -> &'a mut W {
+        self.variant(DCDC_ERROR_IEW::DCDC_ERROR_IE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - LPM invalid transition interrupt enable"]
+    #[inline]
+    pub fn lpm_invalid_tr_ie(&self) -> LPM_INVALID_TR_IER {
+        LPM_INVALID_TR_IER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - LPM invalid clock interrupt enable"]
+    #[inline]
+    pub fn lpm_invalid_clk_ie(&self) -> LPM_INVALID_CLK_IER {
+        LPM_INVALID_CLK_IER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - Active mode invalid transition interrupt enable"]
+    #[inline]
+    pub fn am_invalid_tr_ie(&self) -> AM_INVALID_TR_IER {
+        AM_INVALID_TR_IER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 6 - DC-DC error interrupt enable"]
+    #[inline]
+    pub fn dcdc_error_ie(&self) -> DCDC_ERROR_IER {
+        DCDC_ERROR_IER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - LPM invalid transition interrupt enable"]
+    #[inline]
+    pub fn lpm_invalid_tr_ie(&mut self) -> _LPM_INVALID_TR_IEW {
+        _LPM_INVALID_TR_IEW { w: self }
+    }
+    #[doc = "Bit 1 - LPM invalid clock interrupt enable"]
+    #[inline]
+    pub fn lpm_invalid_clk_ie(&mut self) -> _LPM_INVALID_CLK_IEW {
+        _LPM_INVALID_CLK_IEW { w: self }
+    }
+    #[doc = "Bit 2 - Active mode invalid transition interrupt enable"]
+    #[inline]
+    pub fn am_invalid_tr_ie(&mut self) -> _AM_INVALID_TR_IEW {
+        _AM_INVALID_TR_IEW { w: self }
+    }
+    #[doc = "Bit 6 - DC-DC error interrupt enable"]
+    #[inline]
+    pub fn dcdc_error_ie(&mut self) -> _DCDC_ERROR_IEW {
+        _DCDC_ERROR_IEW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pcm/pcmifg.rs b/example-source/msp432p401r/src/pcm/pcmifg.rs
new file mode 100644
index 0000000..7f851e5
--- /dev/null
+++ b/example-source/msp432p401r/src/pcm/pcmifg.rs
@@ -0,0 +1,144 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::PCMIFG {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct LPM_INVALID_TR_IFGR {
+    bits: bool,
+}
+impl LPM_INVALID_TR_IFGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct LPM_INVALID_CLK_IFGR {
+    bits: bool,
+}
+impl LPM_INVALID_CLK_IFGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct AM_INVALID_TR_IFGR {
+    bits: bool,
+}
+impl AM_INVALID_TR_IFGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DCDC_ERROR_IFGR {
+    bits: bool,
+}
+impl DCDC_ERROR_IFGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - LPM invalid transition flag"]
+    #[inline]
+    pub fn lpm_invalid_tr_ifg(&self) -> LPM_INVALID_TR_IFGR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        LPM_INVALID_TR_IFGR { bits }
+    }
+    #[doc = "Bit 1 - LPM invalid clock flag"]
+    #[inline]
+    pub fn lpm_invalid_clk_ifg(&self) -> LPM_INVALID_CLK_IFGR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        LPM_INVALID_CLK_IFGR { bits }
+    }
+    #[doc = "Bit 2 - Active mode invalid transition flag"]
+    #[inline]
+    pub fn am_invalid_tr_ifg(&self) -> AM_INVALID_TR_IFGR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        AM_INVALID_TR_IFGR { bits }
+    }
+    #[doc = "Bit 6 - DC-DC error flag"]
+    #[inline]
+    pub fn dcdc_error_ifg(&self) -> DCDC_ERROR_IFGR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        DCDC_ERROR_IFGR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/pmap.rs b/example-source/msp432p401r/src/pmap.rs
new file mode 100644
index 0000000..2ea6ccb
--- /dev/null
+++ b/example-source/msp432p401r/src/pmap.rs
@@ -0,0 +1,245 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - Port Mapping Key Register"]
+    pub pmapkeyid: PMAPKEYID,
+    #[doc = "0x02 - Port Mapping Control Register"]
+    pub pmapctl: PMAPCTL,
+    _reserved0: [u8; 4usize],
+    #[doc = "0x08 - Port mapping register, P1.0 and P1.1"]
+    pub p1map01: P1MAP01,
+    #[doc = "0x0a - Port mapping register, P1.2 and P1.3"]
+    pub p1map23: P1MAP23,
+    #[doc = "0x0c - Port mapping register, P1.4 and P1.5"]
+    pub p1map45: P1MAP45,
+    #[doc = "0x0e - Port mapping register, P1.6 and P1.7"]
+    pub p1map67: P1MAP67,
+    #[doc = "0x10 - Port mapping register, P2.0 and P2.1"]
+    pub p2map01: P2MAP01,
+    #[doc = "0x12 - Port mapping register, P2.2 and P2.3"]
+    pub p2map23: P2MAP23,
+    #[doc = "0x14 - Port mapping register, P2.4 and P2.5"]
+    pub p2map45: P2MAP45,
+    #[doc = "0x16 - Port mapping register, P2.6 and P2.7"]
+    pub p2map67: P2MAP67,
+    #[doc = "0x18 - Port mapping register, P3.0 and P3.1"]
+    pub p3map01: P3MAP01,
+    #[doc = "0x1a - Port mapping register, P3.2 and P3.3"]
+    pub p3map23: P3MAP23,
+    #[doc = "0x1c - Port mapping register, P3.4 and P3.5"]
+    pub p3map45: P3MAP45,
+    #[doc = "0x1e - Port mapping register, P3.6 and P3.7"]
+    pub p3map67: P3MAP67,
+    #[doc = "0x20 - Port mapping register, P4.0 and P4.1"]
+    pub p4map01: P4MAP01,
+    #[doc = "0x22 - Port mapping register, P4.2 and P4.3"]
+    pub p4map23: P4MAP23,
+    #[doc = "0x24 - Port mapping register, P4.4 and P4.5"]
+    pub p4map45: P4MAP45,
+    #[doc = "0x26 - Port mapping register, P4.6 and P4.7"]
+    pub p4map67: P4MAP67,
+    #[doc = "0x28 - Port mapping register, P5.0 and P5.1"]
+    pub p5map01: P5MAP01,
+    #[doc = "0x2a - Port mapping register, P5.2 and P5.3"]
+    pub p5map23: P5MAP23,
+    #[doc = "0x2c - Port mapping register, P5.4 and P5.5"]
+    pub p5map45: P5MAP45,
+    #[doc = "0x2e - Port mapping register, P5.6 and P5.7"]
+    pub p5map67: P5MAP67,
+    #[doc = "0x30 - Port mapping register, P6.0 and P6.1"]
+    pub p6map01: P6MAP01,
+    #[doc = "0x32 - Port mapping register, P6.2 and P6.3"]
+    pub p6map23: P6MAP23,
+    #[doc = "0x34 - Port mapping register, P6.4 and P6.5"]
+    pub p6map45: P6MAP45,
+    #[doc = "0x36 - Port mapping register, P6.6 and P6.7"]
+    pub p6map67: P6MAP67,
+    #[doc = "0x38 - Port mapping register, P7.0 and P7.1"]
+    pub p7map01: P7MAP01,
+    #[doc = "0x3a - Port mapping register, P7.2 and P7.3"]
+    pub p7map23: P7MAP23,
+    #[doc = "0x3c - Port mapping register, P7.4 and P7.5"]
+    pub p7map45: P7MAP45,
+    #[doc = "0x3e - Port mapping register, P7.6 and P7.7"]
+    pub p7map67: P7MAP67,
+}
+#[doc = "Port Mapping Key Register"]
+pub struct PMAPKEYID {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port Mapping Key Register"]
+pub mod pmapkeyid;
+#[doc = "Port Mapping Control Register"]
+pub struct PMAPCTL {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port Mapping Control Register"]
+pub mod pmapctl;
+#[doc = "Port mapping register, P1.0 and P1.1"]
+pub struct P1MAP01 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port mapping register, P1.0 and P1.1"]
+pub mod p1map01;
+#[doc = "Port mapping register, P1.2 and P1.3"]
+pub struct P1MAP23 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port mapping register, P1.2 and P1.3"]
+pub mod p1map23;
+#[doc = "Port mapping register, P1.4 and P1.5"]
+pub struct P1MAP45 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port mapping register, P1.4 and P1.5"]
+pub mod p1map45;
+#[doc = "Port mapping register, P1.6 and P1.7"]
+pub struct P1MAP67 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port mapping register, P1.6 and P1.7"]
+pub mod p1map67;
+#[doc = "Port mapping register, P2.0 and P2.1"]
+pub struct P2MAP01 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port mapping register, P2.0 and P2.1"]
+pub mod p2map01;
+#[doc = "Port mapping register, P2.2 and P2.3"]
+pub struct P2MAP23 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port mapping register, P2.2 and P2.3"]
+pub mod p2map23;
+#[doc = "Port mapping register, P2.4 and P2.5"]
+pub struct P2MAP45 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port mapping register, P2.4 and P2.5"]
+pub mod p2map45;
+#[doc = "Port mapping register, P2.6 and P2.7"]
+pub struct P2MAP67 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port mapping register, P2.6 and P2.7"]
+pub mod p2map67;
+#[doc = "Port mapping register, P3.0 and P3.1"]
+pub struct P3MAP01 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port mapping register, P3.0 and P3.1"]
+pub mod p3map01;
+#[doc = "Port mapping register, P3.2 and P3.3"]
+pub struct P3MAP23 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port mapping register, P3.2 and P3.3"]
+pub mod p3map23;
+#[doc = "Port mapping register, P3.4 and P3.5"]
+pub struct P3MAP45 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port mapping register, P3.4 and P3.5"]
+pub mod p3map45;
+#[doc = "Port mapping register, P3.6 and P3.7"]
+pub struct P3MAP67 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port mapping register, P3.6 and P3.7"]
+pub mod p3map67;
+#[doc = "Port mapping register, P4.0 and P4.1"]
+pub struct P4MAP01 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port mapping register, P4.0 and P4.1"]
+pub mod p4map01;
+#[doc = "Port mapping register, P4.2 and P4.3"]
+pub struct P4MAP23 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port mapping register, P4.2 and P4.3"]
+pub mod p4map23;
+#[doc = "Port mapping register, P4.4 and P4.5"]
+pub struct P4MAP45 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port mapping register, P4.4 and P4.5"]
+pub mod p4map45;
+#[doc = "Port mapping register, P4.6 and P4.7"]
+pub struct P4MAP67 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port mapping register, P4.6 and P4.7"]
+pub mod p4map67;
+#[doc = "Port mapping register, P5.0 and P5.1"]
+pub struct P5MAP01 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port mapping register, P5.0 and P5.1"]
+pub mod p5map01;
+#[doc = "Port mapping register, P5.2 and P5.3"]
+pub struct P5MAP23 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port mapping register, P5.2 and P5.3"]
+pub mod p5map23;
+#[doc = "Port mapping register, P5.4 and P5.5"]
+pub struct P5MAP45 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port mapping register, P5.4 and P5.5"]
+pub mod p5map45;
+#[doc = "Port mapping register, P5.6 and P5.7"]
+pub struct P5MAP67 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port mapping register, P5.6 and P5.7"]
+pub mod p5map67;
+#[doc = "Port mapping register, P6.0 and P6.1"]
+pub struct P6MAP01 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port mapping register, P6.0 and P6.1"]
+pub mod p6map01;
+#[doc = "Port mapping register, P6.2 and P6.3"]
+pub struct P6MAP23 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port mapping register, P6.2 and P6.3"]
+pub mod p6map23;
+#[doc = "Port mapping register, P6.4 and P6.5"]
+pub struct P6MAP45 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port mapping register, P6.4 and P6.5"]
+pub mod p6map45;
+#[doc = "Port mapping register, P6.6 and P6.7"]
+pub struct P6MAP67 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port mapping register, P6.6 and P6.7"]
+pub mod p6map67;
+#[doc = "Port mapping register, P7.0 and P7.1"]
+pub struct P7MAP01 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port mapping register, P7.0 and P7.1"]
+pub mod p7map01;
+#[doc = "Port mapping register, P7.2 and P7.3"]
+pub struct P7MAP23 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port mapping register, P7.2 and P7.3"]
+pub mod p7map23;
+#[doc = "Port mapping register, P7.4 and P7.5"]
+pub struct P7MAP45 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port mapping register, P7.4 and P7.5"]
+pub mod p7map45;
+#[doc = "Port mapping register, P7.6 and P7.7"]
+pub struct P7MAP67 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Port mapping register, P7.6 and P7.7"]
+pub mod p7map67;
diff --git a/example-source/msp432p401r/src/pmap/p1map01.rs b/example-source/msp432p401r/src/pmap/p1map01.rs
new file mode 100644
index 0000000..bfa3d63
--- /dev/null
+++ b/example-source/msp432p401r/src/pmap/p1map01.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::P1MAP01 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PMAPXR {
+    bits: u16,
+}
+impl PMAPXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PMAPXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PMAPXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&self) -> PMAPXR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PMAPXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&mut self) -> _PMAPXW {
+        _PMAPXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pmap/p1map23.rs b/example-source/msp432p401r/src/pmap/p1map23.rs
new file mode 100644
index 0000000..5c4a5e4
--- /dev/null
+++ b/example-source/msp432p401r/src/pmap/p1map23.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::P1MAP23 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PMAPXR {
+    bits: u16,
+}
+impl PMAPXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PMAPXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PMAPXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&self) -> PMAPXR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PMAPXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&mut self) -> _PMAPXW {
+        _PMAPXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pmap/p1map45.rs b/example-source/msp432p401r/src/pmap/p1map45.rs
new file mode 100644
index 0000000..eb49711
--- /dev/null
+++ b/example-source/msp432p401r/src/pmap/p1map45.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::P1MAP45 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PMAPXR {
+    bits: u16,
+}
+impl PMAPXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PMAPXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PMAPXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&self) -> PMAPXR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PMAPXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&mut self) -> _PMAPXW {
+        _PMAPXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pmap/p1map67.rs b/example-source/msp432p401r/src/pmap/p1map67.rs
new file mode 100644
index 0000000..7c6d855
--- /dev/null
+++ b/example-source/msp432p401r/src/pmap/p1map67.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::P1MAP67 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PMAPXR {
+    bits: u16,
+}
+impl PMAPXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PMAPXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PMAPXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&self) -> PMAPXR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PMAPXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&mut self) -> _PMAPXW {
+        _PMAPXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pmap/p2map01.rs b/example-source/msp432p401r/src/pmap/p2map01.rs
new file mode 100644
index 0000000..5fbe059
--- /dev/null
+++ b/example-source/msp432p401r/src/pmap/p2map01.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::P2MAP01 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PMAPXR {
+    bits: u16,
+}
+impl PMAPXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PMAPXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PMAPXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&self) -> PMAPXR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PMAPXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&mut self) -> _PMAPXW {
+        _PMAPXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pmap/p2map23.rs b/example-source/msp432p401r/src/pmap/p2map23.rs
new file mode 100644
index 0000000..91be051
--- /dev/null
+++ b/example-source/msp432p401r/src/pmap/p2map23.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::P2MAP23 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PMAPXR {
+    bits: u16,
+}
+impl PMAPXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PMAPXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PMAPXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&self) -> PMAPXR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PMAPXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&mut self) -> _PMAPXW {
+        _PMAPXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pmap/p2map45.rs b/example-source/msp432p401r/src/pmap/p2map45.rs
new file mode 100644
index 0000000..d1e30be
--- /dev/null
+++ b/example-source/msp432p401r/src/pmap/p2map45.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::P2MAP45 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PMAPXR {
+    bits: u16,
+}
+impl PMAPXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PMAPXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PMAPXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&self) -> PMAPXR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PMAPXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&mut self) -> _PMAPXW {
+        _PMAPXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pmap/p2map67.rs b/example-source/msp432p401r/src/pmap/p2map67.rs
new file mode 100644
index 0000000..7edf48f
--- /dev/null
+++ b/example-source/msp432p401r/src/pmap/p2map67.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::P2MAP67 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PMAPXR {
+    bits: u16,
+}
+impl PMAPXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PMAPXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PMAPXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&self) -> PMAPXR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PMAPXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&mut self) -> _PMAPXW {
+        _PMAPXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pmap/p3map01.rs b/example-source/msp432p401r/src/pmap/p3map01.rs
new file mode 100644
index 0000000..0f32103
--- /dev/null
+++ b/example-source/msp432p401r/src/pmap/p3map01.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::P3MAP01 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PMAPXR {
+    bits: u16,
+}
+impl PMAPXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PMAPXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PMAPXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&self) -> PMAPXR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PMAPXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&mut self) -> _PMAPXW {
+        _PMAPXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pmap/p3map23.rs b/example-source/msp432p401r/src/pmap/p3map23.rs
new file mode 100644
index 0000000..dce07e9
--- /dev/null
+++ b/example-source/msp432p401r/src/pmap/p3map23.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::P3MAP23 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PMAPXR {
+    bits: u16,
+}
+impl PMAPXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PMAPXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PMAPXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&self) -> PMAPXR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PMAPXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&mut self) -> _PMAPXW {
+        _PMAPXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pmap/p3map45.rs b/example-source/msp432p401r/src/pmap/p3map45.rs
new file mode 100644
index 0000000..b511094
--- /dev/null
+++ b/example-source/msp432p401r/src/pmap/p3map45.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::P3MAP45 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PMAPXR {
+    bits: u16,
+}
+impl PMAPXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PMAPXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PMAPXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&self) -> PMAPXR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PMAPXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&mut self) -> _PMAPXW {
+        _PMAPXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pmap/p3map67.rs b/example-source/msp432p401r/src/pmap/p3map67.rs
new file mode 100644
index 0000000..41fb684
--- /dev/null
+++ b/example-source/msp432p401r/src/pmap/p3map67.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::P3MAP67 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PMAPXR {
+    bits: u16,
+}
+impl PMAPXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PMAPXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PMAPXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&self) -> PMAPXR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PMAPXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&mut self) -> _PMAPXW {
+        _PMAPXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pmap/p4map01.rs b/example-source/msp432p401r/src/pmap/p4map01.rs
new file mode 100644
index 0000000..2d8c865
--- /dev/null
+++ b/example-source/msp432p401r/src/pmap/p4map01.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::P4MAP01 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PMAPXR {
+    bits: u16,
+}
+impl PMAPXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PMAPXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PMAPXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&self) -> PMAPXR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PMAPXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&mut self) -> _PMAPXW {
+        _PMAPXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pmap/p4map23.rs b/example-source/msp432p401r/src/pmap/p4map23.rs
new file mode 100644
index 0000000..1f50ad4
--- /dev/null
+++ b/example-source/msp432p401r/src/pmap/p4map23.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::P4MAP23 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PMAPXR {
+    bits: u16,
+}
+impl PMAPXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PMAPXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PMAPXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&self) -> PMAPXR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PMAPXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&mut self) -> _PMAPXW {
+        _PMAPXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pmap/p4map45.rs b/example-source/msp432p401r/src/pmap/p4map45.rs
new file mode 100644
index 0000000..8b93c0e
--- /dev/null
+++ b/example-source/msp432p401r/src/pmap/p4map45.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::P4MAP45 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PMAPXR {
+    bits: u16,
+}
+impl PMAPXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PMAPXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PMAPXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&self) -> PMAPXR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PMAPXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&mut self) -> _PMAPXW {
+        _PMAPXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pmap/p4map67.rs b/example-source/msp432p401r/src/pmap/p4map67.rs
new file mode 100644
index 0000000..4336aa8
--- /dev/null
+++ b/example-source/msp432p401r/src/pmap/p4map67.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::P4MAP67 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PMAPXR {
+    bits: u16,
+}
+impl PMAPXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PMAPXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PMAPXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&self) -> PMAPXR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PMAPXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&mut self) -> _PMAPXW {
+        _PMAPXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pmap/p5map01.rs b/example-source/msp432p401r/src/pmap/p5map01.rs
new file mode 100644
index 0000000..f52873f
--- /dev/null
+++ b/example-source/msp432p401r/src/pmap/p5map01.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::P5MAP01 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PMAPXR {
+    bits: u16,
+}
+impl PMAPXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PMAPXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PMAPXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&self) -> PMAPXR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PMAPXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&mut self) -> _PMAPXW {
+        _PMAPXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pmap/p5map23.rs b/example-source/msp432p401r/src/pmap/p5map23.rs
new file mode 100644
index 0000000..6c624d3
--- /dev/null
+++ b/example-source/msp432p401r/src/pmap/p5map23.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::P5MAP23 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PMAPXR {
+    bits: u16,
+}
+impl PMAPXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PMAPXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PMAPXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&self) -> PMAPXR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PMAPXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&mut self) -> _PMAPXW {
+        _PMAPXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pmap/p5map45.rs b/example-source/msp432p401r/src/pmap/p5map45.rs
new file mode 100644
index 0000000..ef286b1
--- /dev/null
+++ b/example-source/msp432p401r/src/pmap/p5map45.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::P5MAP45 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PMAPXR {
+    bits: u16,
+}
+impl PMAPXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PMAPXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PMAPXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&self) -> PMAPXR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PMAPXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&mut self) -> _PMAPXW {
+        _PMAPXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pmap/p5map67.rs b/example-source/msp432p401r/src/pmap/p5map67.rs
new file mode 100644
index 0000000..9143eaf
--- /dev/null
+++ b/example-source/msp432p401r/src/pmap/p5map67.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::P5MAP67 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PMAPXR {
+    bits: u16,
+}
+impl PMAPXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PMAPXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PMAPXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&self) -> PMAPXR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PMAPXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&mut self) -> _PMAPXW {
+        _PMAPXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pmap/p6map01.rs b/example-source/msp432p401r/src/pmap/p6map01.rs
new file mode 100644
index 0000000..76f1f88
--- /dev/null
+++ b/example-source/msp432p401r/src/pmap/p6map01.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::P6MAP01 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PMAPXR {
+    bits: u16,
+}
+impl PMAPXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PMAPXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PMAPXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&self) -> PMAPXR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PMAPXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&mut self) -> _PMAPXW {
+        _PMAPXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pmap/p6map23.rs b/example-source/msp432p401r/src/pmap/p6map23.rs
new file mode 100644
index 0000000..2617597
--- /dev/null
+++ b/example-source/msp432p401r/src/pmap/p6map23.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::P6MAP23 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PMAPXR {
+    bits: u16,
+}
+impl PMAPXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PMAPXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PMAPXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&self) -> PMAPXR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PMAPXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&mut self) -> _PMAPXW {
+        _PMAPXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pmap/p6map45.rs b/example-source/msp432p401r/src/pmap/p6map45.rs
new file mode 100644
index 0000000..09d3f7c
--- /dev/null
+++ b/example-source/msp432p401r/src/pmap/p6map45.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::P6MAP45 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PMAPXR {
+    bits: u16,
+}
+impl PMAPXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PMAPXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PMAPXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&self) -> PMAPXR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PMAPXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&mut self) -> _PMAPXW {
+        _PMAPXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pmap/p6map67.rs b/example-source/msp432p401r/src/pmap/p6map67.rs
new file mode 100644
index 0000000..6ae6043
--- /dev/null
+++ b/example-source/msp432p401r/src/pmap/p6map67.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::P6MAP67 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PMAPXR {
+    bits: u16,
+}
+impl PMAPXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PMAPXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PMAPXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&self) -> PMAPXR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PMAPXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&mut self) -> _PMAPXW {
+        _PMAPXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pmap/p7map01.rs b/example-source/msp432p401r/src/pmap/p7map01.rs
new file mode 100644
index 0000000..166dc6a
--- /dev/null
+++ b/example-source/msp432p401r/src/pmap/p7map01.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::P7MAP01 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PMAPXR {
+    bits: u16,
+}
+impl PMAPXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PMAPXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PMAPXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&self) -> PMAPXR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PMAPXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&mut self) -> _PMAPXW {
+        _PMAPXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pmap/p7map23.rs b/example-source/msp432p401r/src/pmap/p7map23.rs
new file mode 100644
index 0000000..93a2b06
--- /dev/null
+++ b/example-source/msp432p401r/src/pmap/p7map23.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::P7MAP23 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PMAPXR {
+    bits: u16,
+}
+impl PMAPXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PMAPXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PMAPXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&self) -> PMAPXR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PMAPXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&mut self) -> _PMAPXW {
+        _PMAPXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pmap/p7map45.rs b/example-source/msp432p401r/src/pmap/p7map45.rs
new file mode 100644
index 0000000..6672e92
--- /dev/null
+++ b/example-source/msp432p401r/src/pmap/p7map45.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::P7MAP45 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PMAPXR {
+    bits: u16,
+}
+impl PMAPXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PMAPXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PMAPXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&self) -> PMAPXR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PMAPXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&mut self) -> _PMAPXW {
+        _PMAPXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pmap/p7map67.rs b/example-source/msp432p401r/src/pmap/p7map67.rs
new file mode 100644
index 0000000..d457c07
--- /dev/null
+++ b/example-source/msp432p401r/src/pmap/p7map67.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::P7MAP67 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PMAPXR {
+    bits: u16,
+}
+impl PMAPXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PMAPXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PMAPXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&self) -> PMAPXR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PMAPXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Selects secondary port function"]
+    #[inline]
+    pub fn pmapx(&mut self) -> _PMAPXW {
+        _PMAPXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pmap/pmapctl.rs b/example-source/msp432p401r/src/pmap/pmapctl.rs
new file mode 100644
index 0000000..680ce24
--- /dev/null
+++ b/example-source/msp432p401r/src/pmap/pmapctl.rs
@@ -0,0 +1,239 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PMAPCTL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `PMAPLOCKED`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PMAPLOCKEDR {
+    #[doc = "Access to mapping registers is granted"]
+    PMAPLOCKED_0,
+    #[doc = "Access to mapping registers is locked"]
+    PMAPLOCKED_1,
+}
+impl PMAPLOCKEDR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            PMAPLOCKEDR::PMAPLOCKED_0 => false,
+            PMAPLOCKEDR::PMAPLOCKED_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> PMAPLOCKEDR {
+        match value {
+            false => PMAPLOCKEDR::PMAPLOCKED_0,
+            true => PMAPLOCKEDR::PMAPLOCKED_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `PMAPLOCKED_0`"]
+    #[inline]
+    pub fn is_pmaplocked_0(&self) -> bool {
+        *self == PMAPLOCKEDR::PMAPLOCKED_0
+    }
+    #[doc = "Checks if the value of the field is `PMAPLOCKED_1`"]
+    #[inline]
+    pub fn is_pmaplocked_1(&self) -> bool {
+        *self == PMAPLOCKEDR::PMAPLOCKED_1
+    }
+}
+#[doc = "Possible values of the field `PMAPRECFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PMAPRECFGR {
+    #[doc = "Configuration allowed only once"]
+    PMAPRECFG_0,
+    #[doc = "Allow reconfiguration of port mapping"]
+    PMAPRECFG_1,
+}
+impl PMAPRECFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            PMAPRECFGR::PMAPRECFG_0 => false,
+            PMAPRECFGR::PMAPRECFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> PMAPRECFGR {
+        match value {
+            false => PMAPRECFGR::PMAPRECFG_0,
+            true => PMAPRECFGR::PMAPRECFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `PMAPRECFG_0`"]
+    #[inline]
+    pub fn is_pmaprecfg_0(&self) -> bool {
+        *self == PMAPRECFGR::PMAPRECFG_0
+    }
+    #[doc = "Checks if the value of the field is `PMAPRECFG_1`"]
+    #[inline]
+    pub fn is_pmaprecfg_1(&self) -> bool {
+        *self == PMAPRECFGR::PMAPRECFG_1
+    }
+}
+#[doc = "Values that can be written to the field `PMAPRECFG`"]
+pub enum PMAPRECFGW {
+    #[doc = "Configuration allowed only once"]
+    PMAPRECFG_0,
+    #[doc = "Allow reconfiguration of port mapping"]
+    PMAPRECFG_1,
+}
+impl PMAPRECFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            PMAPRECFGW::PMAPRECFG_0 => false,
+            PMAPRECFGW::PMAPRECFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PMAPRECFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PMAPRECFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: PMAPRECFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Configuration allowed only once"]
+    #[inline]
+    pub fn pmaprecfg_0(self) -> &'a mut W {
+        self.variant(PMAPRECFGW::PMAPRECFG_0)
+    }
+    #[doc = "Allow reconfiguration of port mapping"]
+    #[inline]
+    pub fn pmaprecfg_1(self) -> &'a mut W {
+        self.variant(PMAPRECFGW::PMAPRECFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Port mapping lock bit"]
+    #[inline]
+    pub fn pmaplocked(&self) -> PMAPLOCKEDR {
+        PMAPLOCKEDR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Port mapping reconfiguration control bit"]
+    #[inline]
+    pub fn pmaprecfg(&self) -> PMAPRECFGR {
+        PMAPRECFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 1 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 1 - Port mapping reconfiguration control bit"]
+    #[inline]
+    pub fn pmaprecfg(&mut self) -> _PMAPRECFGW {
+        _PMAPRECFGW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pmap/pmapkeyid.rs b/example-source/msp432p401r/src/pmap/pmapkeyid.rs
new file mode 100644
index 0000000..822c5ec
--- /dev/null
+++ b/example-source/msp432p401r/src/pmap/pmapkeyid.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::PMAPKEYID {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PMAPKEYR {
+    bits: u16,
+}
+impl PMAPKEYR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PMAPKEYW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PMAPKEYW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Port mapping controller write access key"]
+    #[inline]
+    pub fn pmapkey(&self) -> PMAPKEYR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        PMAPKEYR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 38565 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Port mapping controller write access key"]
+    #[inline]
+    pub fn pmapkey(&mut self) -> _PMAPKEYW {
+        _PMAPKEYW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pss.rs b/example-source/msp432p401r/src/pss.rs
new file mode 100644
index 0000000..2e5e3b7
--- /dev/null
+++ b/example-source/msp432p401r/src/pss.rs
@@ -0,0 +1,45 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - Key Register"]
+    pub psskey: PSSKEY,
+    #[doc = "0x04 - Control 0 Register"]
+    pub pssctl0: PSSCTL0,
+    _reserved0: [u8; 44usize],
+    #[doc = "0x34 - Interrupt Enable Register"]
+    pub pssie: PSSIE,
+    #[doc = "0x38 - Interrupt Flag Register"]
+    pub pssifg: PSSIFG,
+    #[doc = "0x3c - Clear Interrupt Flag Register"]
+    pub pssclrifg: PSSCLRIFG,
+}
+#[doc = "Key Register"]
+pub struct PSSKEY {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Key Register"]
+pub mod psskey;
+#[doc = "Control 0 Register"]
+pub struct PSSCTL0 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Control 0 Register"]
+pub mod pssctl0;
+#[doc = "Interrupt Enable Register"]
+pub struct PSSIE {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Interrupt Enable Register"]
+pub mod pssie;
+#[doc = "Interrupt Flag Register"]
+pub struct PSSIFG {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Interrupt Flag Register"]
+pub mod pssifg;
+#[doc = "Clear Interrupt Flag Register"]
+pub struct PSSCLRIFG {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Clear Interrupt Flag Register"]
+pub mod pssclrifg;
diff --git a/example-source/msp432p401r/src/pss/pssclrifg.rs b/example-source/msp432p401r/src/pss/pssclrifg.rs
new file mode 100644
index 0000000..16aa783
--- /dev/null
+++ b/example-source/msp432p401r/src/pss/pssclrifg.rs
@@ -0,0 +1,127 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::PSSCLRIFG {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Values that can be written to the field `CLRSVSMHIFG`"]
+pub enum CLRSVSMHIFGW {
+    #[doc = "No effect"]
+    CLRSVSMHIFG_0,
+    #[doc = "Clear pending interrupt flag"]
+    CLRSVSMHIFG_1,
+}
+impl CLRSVSMHIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CLRSVSMHIFGW::CLRSVSMHIFG_0 => false,
+            CLRSVSMHIFGW::CLRSVSMHIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRSVSMHIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRSVSMHIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CLRSVSMHIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No effect"]
+    #[inline]
+    pub fn clrsvsmhifg_0(self) -> &'a mut W {
+        self.variant(CLRSVSMHIFGW::CLRSVSMHIFG_0)
+    }
+    #[doc = "Clear pending interrupt flag"]
+    #[inline]
+    pub fn clrsvsmhifg_1(self) -> &'a mut W {
+        self.variant(CLRSVSMHIFGW::CLRSVSMHIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 1 - SVSMH clear interrupt flag"]
+    #[inline]
+    pub fn clrsvsmhifg(&mut self) -> _CLRSVSMHIFGW {
+        _CLRSVSMHIFGW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pss/pssctl0.rs b/example-source/msp432p401r/src/pss/pssctl0.rs
new file mode 100644
index 0000000..1b8f67b
--- /dev/null
+++ b/example-source/msp432p401r/src/pss/pssctl0.rs
@@ -0,0 +1,955 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::PSSCTL0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `SVSMHOFF`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SVSMHOFFR {
+    #[doc = "The SVSMH is on"]
+    SVSMHOFF_0,
+    #[doc = "The SVSMH is off"]
+    SVSMHOFF_1,
+}
+impl SVSMHOFFR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            SVSMHOFFR::SVSMHOFF_0 => false,
+            SVSMHOFFR::SVSMHOFF_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> SVSMHOFFR {
+        match value {
+            false => SVSMHOFFR::SVSMHOFF_0,
+            true => SVSMHOFFR::SVSMHOFF_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SVSMHOFF_0`"]
+    #[inline]
+    pub fn is_svsmhoff_0(&self) -> bool {
+        *self == SVSMHOFFR::SVSMHOFF_0
+    }
+    #[doc = "Checks if the value of the field is `SVSMHOFF_1`"]
+    #[inline]
+    pub fn is_svsmhoff_1(&self) -> bool {
+        *self == SVSMHOFFR::SVSMHOFF_1
+    }
+}
+#[doc = "Possible values of the field `SVSMHLP`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SVSMHLPR {
+    #[doc = "Full performance mode. See the device-specific data sheet for response times."]
+    SVSMHLP_0,
+    #[doc = "Low power normal performance mode in LPM3, LPM4, and LPMx.5, full performance in all other modes. See the device-specific data sheet for response times."]
+    SVSMHLP_1,
+}
+impl SVSMHLPR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            SVSMHLPR::SVSMHLP_0 => false,
+            SVSMHLPR::SVSMHLP_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> SVSMHLPR {
+        match value {
+            false => SVSMHLPR::SVSMHLP_0,
+            true => SVSMHLPR::SVSMHLP_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SVSMHLP_0`"]
+    #[inline]
+    pub fn is_svsmhlp_0(&self) -> bool {
+        *self == SVSMHLPR::SVSMHLP_0
+    }
+    #[doc = "Checks if the value of the field is `SVSMHLP_1`"]
+    #[inline]
+    pub fn is_svsmhlp_1(&self) -> bool {
+        *self == SVSMHLPR::SVSMHLP_1
+    }
+}
+#[doc = "Possible values of the field `SVSMHS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SVSMHSR {
+    #[doc = "Configure as SVSH"]
+    SVSMHS_0,
+    #[doc = "Configure as SVMH"]
+    SVSMHS_1,
+}
+impl SVSMHSR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            SVSMHSR::SVSMHS_0 => false,
+            SVSMHSR::SVSMHS_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> SVSMHSR {
+        match value {
+            false => SVSMHSR::SVSMHS_0,
+            true => SVSMHSR::SVSMHS_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SVSMHS_0`"]
+    #[inline]
+    pub fn is_svsmhs_0(&self) -> bool {
+        *self == SVSMHSR::SVSMHS_0
+    }
+    #[doc = "Checks if the value of the field is `SVSMHS_1`"]
+    #[inline]
+    pub fn is_svsmhs_1(&self) -> bool {
+        *self == SVSMHSR::SVSMHS_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SVSMHTHR {
+    bits: u8,
+}
+impl SVSMHTHR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `SVMHOE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SVMHOER {
+    #[doc = "SVSMHIFG bit is not output"]
+    SVMHOE_0,
+    #[doc = "SVSMHIFG bit is output to the device SVMHOUT pin. The device-specific port logic must be configured accordingly"]
+    SVMHOE_1,
+}
+impl SVMHOER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            SVMHOER::SVMHOE_0 => false,
+            SVMHOER::SVMHOE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> SVMHOER {
+        match value {
+            false => SVMHOER::SVMHOE_0,
+            true => SVMHOER::SVMHOE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SVMHOE_0`"]
+    #[inline]
+    pub fn is_svmhoe_0(&self) -> bool {
+        *self == SVMHOER::SVMHOE_0
+    }
+    #[doc = "Checks if the value of the field is `SVMHOE_1`"]
+    #[inline]
+    pub fn is_svmhoe_1(&self) -> bool {
+        *self == SVMHOER::SVMHOE_1
+    }
+}
+#[doc = "Possible values of the field `SVMHOUTPOLAL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SVMHOUTPOLALR {
+    #[doc = "SVMHOUT is active high. An error condition is signaled by a 1 at the SVMHOUT pin"]
+    SVMHOUTPOLAL_0,
+    #[doc = "SVMHOUT is active low. An error condition is signaled by a 0 at the SVMHOUT pin"]
+    SVMHOUTPOLAL_1,
+}
+impl SVMHOUTPOLALR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            SVMHOUTPOLALR::SVMHOUTPOLAL_0 => false,
+            SVMHOUTPOLALR::SVMHOUTPOLAL_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> SVMHOUTPOLALR {
+        match value {
+            false => SVMHOUTPOLALR::SVMHOUTPOLAL_0,
+            true => SVMHOUTPOLALR::SVMHOUTPOLAL_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SVMHOUTPOLAL_0`"]
+    #[inline]
+    pub fn is_svmhoutpolal_0(&self) -> bool {
+        *self == SVMHOUTPOLALR::SVMHOUTPOLAL_0
+    }
+    #[doc = "Checks if the value of the field is `SVMHOUTPOLAL_1`"]
+    #[inline]
+    pub fn is_svmhoutpolal_1(&self) -> bool {
+        *self == SVMHOUTPOLALR::SVMHOUTPOLAL_1
+    }
+}
+#[doc = "Possible values of the field `DCDC_FORCE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DCDC_FORCER {
+    #[doc = "DC-DC regulator operation not forced. Automatic fail-safe mechanism switches the core voltage regulator from DC-DC to LDO when the supply voltage falls below the minimum supply voltage necessary for DC-DC operation."]
+    DCDC_FORCE_0,
+    #[doc = "DC-DC regulator operation forced. Automatic fail-safe mechanism is disabled and device continues to operate out of DC-DC regulator."]
+    DCDC_FORCE_1,
+}
+impl DCDC_FORCER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            DCDC_FORCER::DCDC_FORCE_0 => false,
+            DCDC_FORCER::DCDC_FORCE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> DCDC_FORCER {
+        match value {
+            false => DCDC_FORCER::DCDC_FORCE_0,
+            true => DCDC_FORCER::DCDC_FORCE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DCDC_FORCE_0`"]
+    #[inline]
+    pub fn is_dcdc_force_0(&self) -> bool {
+        *self == DCDC_FORCER::DCDC_FORCE_0
+    }
+    #[doc = "Checks if the value of the field is `DCDC_FORCE_1`"]
+    #[inline]
+    pub fn is_dcdc_force_1(&self) -> bool {
+        *self == DCDC_FORCER::DCDC_FORCE_1
+    }
+}
+#[doc = "Possible values of the field `VCORETRAN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum VCORETRANR {
+    #[doc = "32 s / 100 mV"]
+    VCORETRAN_0,
+    #[doc = "64 s / 100 mV"]
+    VCORETRAN_1,
+    #[doc = "128 s / 100 mV (default)"]
+    VCORETRAN_2,
+    #[doc = "256 s / 100 mV"]
+    VCORETRAN_3,
+}
+impl VCORETRANR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            VCORETRANR::VCORETRAN_0 => 0,
+            VCORETRANR::VCORETRAN_1 => 1,
+            VCORETRANR::VCORETRAN_2 => 2,
+            VCORETRANR::VCORETRAN_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> VCORETRANR {
+        match value {
+            0 => VCORETRANR::VCORETRAN_0,
+            1 => VCORETRANR::VCORETRAN_1,
+            2 => VCORETRANR::VCORETRAN_2,
+            3 => VCORETRANR::VCORETRAN_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `VCORETRAN_0`"]
+    #[inline]
+    pub fn is_vcoretran_0(&self) -> bool {
+        *self == VCORETRANR::VCORETRAN_0
+    }
+    #[doc = "Checks if the value of the field is `VCORETRAN_1`"]
+    #[inline]
+    pub fn is_vcoretran_1(&self) -> bool {
+        *self == VCORETRANR::VCORETRAN_1
+    }
+    #[doc = "Checks if the value of the field is `VCORETRAN_2`"]
+    #[inline]
+    pub fn is_vcoretran_2(&self) -> bool {
+        *self == VCORETRANR::VCORETRAN_2
+    }
+    #[doc = "Checks if the value of the field is `VCORETRAN_3`"]
+    #[inline]
+    pub fn is_vcoretran_3(&self) -> bool {
+        *self == VCORETRANR::VCORETRAN_3
+    }
+}
+#[doc = "Values that can be written to the field `SVSMHOFF`"]
+pub enum SVSMHOFFW {
+    #[doc = "The SVSMH is on"]
+    SVSMHOFF_0,
+    #[doc = "The SVSMH is off"]
+    SVSMHOFF_1,
+}
+impl SVSMHOFFW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            SVSMHOFFW::SVSMHOFF_0 => false,
+            SVSMHOFFW::SVSMHOFF_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SVSMHOFFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SVSMHOFFW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SVSMHOFFW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The SVSMH is on"]
+    #[inline]
+    pub fn svsmhoff_0(self) -> &'a mut W {
+        self.variant(SVSMHOFFW::SVSMHOFF_0)
+    }
+    #[doc = "The SVSMH is off"]
+    #[inline]
+    pub fn svsmhoff_1(self) -> &'a mut W {
+        self.variant(SVSMHOFFW::SVSMHOFF_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `SVSMHLP`"]
+pub enum SVSMHLPW {
+    #[doc = "Full performance mode. See the device-specific data sheet for response times."]
+    SVSMHLP_0,
+    #[doc = "Low power normal performance mode in LPM3, LPM4, and LPMx.5, full performance in all other modes. See the device-specific data sheet for response times."]
+    SVSMHLP_1,
+}
+impl SVSMHLPW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            SVSMHLPW::SVSMHLP_0 => false,
+            SVSMHLPW::SVSMHLP_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SVSMHLPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SVSMHLPW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SVSMHLPW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Full performance mode. See the device-specific data sheet for response times."]
+    #[inline]
+    pub fn svsmhlp_0(self) -> &'a mut W {
+        self.variant(SVSMHLPW::SVSMHLP_0)
+    }
+    #[doc = "Low power normal performance mode in LPM3, LPM4, and LPMx.5, full performance in all other modes. See the device-specific data sheet for response times."]
+    #[inline]
+    pub fn svsmhlp_1(self) -> &'a mut W {
+        self.variant(SVSMHLPW::SVSMHLP_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `SVSMHS`"]
+pub enum SVSMHSW {
+    #[doc = "Configure as SVSH"]
+    SVSMHS_0,
+    #[doc = "Configure as SVMH"]
+    SVSMHS_1,
+}
+impl SVSMHSW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            SVSMHSW::SVSMHS_0 => false,
+            SVSMHSW::SVSMHS_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SVSMHSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SVSMHSW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SVSMHSW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Configure as SVSH"]
+    #[inline]
+    pub fn svsmhs_0(self) -> &'a mut W {
+        self.variant(SVSMHSW::SVSMHS_0)
+    }
+    #[doc = "Configure as SVMH"]
+    #[inline]
+    pub fn svsmhs_1(self) -> &'a mut W {
+        self.variant(SVSMHSW::SVSMHS_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SVSMHTHW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SVSMHTHW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `SVMHOE`"]
+pub enum SVMHOEW {
+    #[doc = "SVSMHIFG bit is not output"]
+    SVMHOE_0,
+    #[doc = "SVSMHIFG bit is output to the device SVMHOUT pin. The device-specific port logic must be configured accordingly"]
+    SVMHOE_1,
+}
+impl SVMHOEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            SVMHOEW::SVMHOE_0 => false,
+            SVMHOEW::SVMHOE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SVMHOEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SVMHOEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SVMHOEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "SVSMHIFG bit is not output"]
+    #[inline]
+    pub fn svmhoe_0(self) -> &'a mut W {
+        self.variant(SVMHOEW::SVMHOE_0)
+    }
+    #[doc = "SVSMHIFG bit is output to the device SVMHOUT pin. The device-specific port logic must be configured accordingly"]
+    #[inline]
+    pub fn svmhoe_1(self) -> &'a mut W {
+        self.variant(SVMHOEW::SVMHOE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `SVMHOUTPOLAL`"]
+pub enum SVMHOUTPOLALW {
+    #[doc = "SVMHOUT is active high. An error condition is signaled by a 1 at the SVMHOUT pin"]
+    SVMHOUTPOLAL_0,
+    #[doc = "SVMHOUT is active low. An error condition is signaled by a 0 at the SVMHOUT pin"]
+    SVMHOUTPOLAL_1,
+}
+impl SVMHOUTPOLALW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            SVMHOUTPOLALW::SVMHOUTPOLAL_0 => false,
+            SVMHOUTPOLALW::SVMHOUTPOLAL_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SVMHOUTPOLALW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SVMHOUTPOLALW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SVMHOUTPOLALW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "SVMHOUT is active high. An error condition is signaled by a 1 at the SVMHOUT pin"]
+    #[inline]
+    pub fn svmhoutpolal_0(self) -> &'a mut W {
+        self.variant(SVMHOUTPOLALW::SVMHOUTPOLAL_0)
+    }
+    #[doc = "SVMHOUT is active low. An error condition is signaled by a 0 at the SVMHOUT pin"]
+    #[inline]
+    pub fn svmhoutpolal_1(self) -> &'a mut W {
+        self.variant(SVMHOUTPOLALW::SVMHOUTPOLAL_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `DCDC_FORCE`"]
+pub enum DCDC_FORCEW {
+    #[doc = "DC-DC regulator operation not forced. Automatic fail-safe mechanism switches the core voltage regulator from DC-DC to LDO when the supply voltage falls below the minimum supply voltage necessary for DC-DC operation."]
+    DCDC_FORCE_0,
+    #[doc = "DC-DC regulator operation forced. Automatic fail-safe mechanism is disabled and device continues to operate out of DC-DC regulator."]
+    DCDC_FORCE_1,
+}
+impl DCDC_FORCEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            DCDC_FORCEW::DCDC_FORCE_0 => false,
+            DCDC_FORCEW::DCDC_FORCE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DCDC_FORCEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DCDC_FORCEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: DCDC_FORCEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "DC-DC regulator operation not forced. Automatic fail-safe mechanism switches the core voltage regulator from DC-DC to LDO when the supply voltage falls below the minimum supply voltage necessary for DC-DC operation."]
+    #[inline]
+    pub fn dcdc_force_0(self) -> &'a mut W {
+        self.variant(DCDC_FORCEW::DCDC_FORCE_0)
+    }
+    #[doc = "DC-DC regulator operation forced. Automatic fail-safe mechanism is disabled and device continues to operate out of DC-DC regulator."]
+    #[inline]
+    pub fn dcdc_force_1(self) -> &'a mut W {
+        self.variant(DCDC_FORCEW::DCDC_FORCE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `VCORETRAN`"]
+pub enum VCORETRANW {
+    #[doc = "32 s / 100 mV"]
+    VCORETRAN_0,
+    #[doc = "64 s / 100 mV"]
+    VCORETRAN_1,
+    #[doc = "128 s / 100 mV (default)"]
+    VCORETRAN_2,
+    #[doc = "256 s / 100 mV"]
+    VCORETRAN_3,
+}
+impl VCORETRANW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            VCORETRANW::VCORETRAN_0 => 0,
+            VCORETRANW::VCORETRAN_1 => 1,
+            VCORETRANW::VCORETRAN_2 => 2,
+            VCORETRANW::VCORETRAN_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _VCORETRANW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _VCORETRANW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: VCORETRANW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "32 s / 100 mV"]
+    #[inline]
+    pub fn vcoretran_0(self) -> &'a mut W {
+        self.variant(VCORETRANW::VCORETRAN_0)
+    }
+    #[doc = "64 s / 100 mV"]
+    #[inline]
+    pub fn vcoretran_1(self) -> &'a mut W {
+        self.variant(VCORETRANW::VCORETRAN_1)
+    }
+    #[doc = "128 s / 100 mV (default)"]
+    #[inline]
+    pub fn vcoretran_2(self) -> &'a mut W {
+        self.variant(VCORETRANW::VCORETRAN_2)
+    }
+    #[doc = "256 s / 100 mV"]
+    #[inline]
+    pub fn vcoretran_3(self) -> &'a mut W {
+        self.variant(VCORETRANW::VCORETRAN_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - SVSM high-side off"]
+    #[inline]
+    pub fn svsmhoff(&self) -> SVSMHOFFR {
+        SVSMHOFFR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - SVSM high-side low power normal performance mode"]
+    #[inline]
+    pub fn svsmhlp(&self) -> SVSMHLPR {
+        SVSMHLPR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - Supply supervisor or monitor selection for the high-side"]
+    #[inline]
+    pub fn svsmhs(&self) -> SVSMHSR {
+        SVSMHSR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 3:5 - SVSM high-side reset voltage level"]
+    #[inline]
+    pub fn svsmhth(&self) -> SVSMHTHR {
+        let bits = {
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        SVSMHTHR { bits }
+    }
+    #[doc = "Bit 6 - SVSM high-side output enable"]
+    #[inline]
+    pub fn svmhoe(&self) -> SVMHOER {
+        SVMHOER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 7 - SVMHOUT pin polarity active low"]
+    #[inline]
+    pub fn svmhoutpolal(&self) -> SVMHOUTPOLALR {
+        SVMHOUTPOLALR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 10 - Force DC-DC regulator operation"]
+    #[inline]
+    pub fn dcdc_force(&self) -> DCDC_FORCER {
+        DCDC_FORCER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 12:13 - Controls core voltage level transition time"]
+    #[inline]
+    pub fn vcoretran(&self) -> VCORETRANR {
+        VCORETRANR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 8192 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - SVSM high-side off"]
+    #[inline]
+    pub fn svsmhoff(&mut self) -> _SVSMHOFFW {
+        _SVSMHOFFW { w: self }
+    }
+    #[doc = "Bit 1 - SVSM high-side low power normal performance mode"]
+    #[inline]
+    pub fn svsmhlp(&mut self) -> _SVSMHLPW {
+        _SVSMHLPW { w: self }
+    }
+    #[doc = "Bit 2 - Supply supervisor or monitor selection for the high-side"]
+    #[inline]
+    pub fn svsmhs(&mut self) -> _SVSMHSW {
+        _SVSMHSW { w: self }
+    }
+    #[doc = "Bits 3:5 - SVSM high-side reset voltage level"]
+    #[inline]
+    pub fn svsmhth(&mut self) -> _SVSMHTHW {
+        _SVSMHTHW { w: self }
+    }
+    #[doc = "Bit 6 - SVSM high-side output enable"]
+    #[inline]
+    pub fn svmhoe(&mut self) -> _SVMHOEW {
+        _SVMHOEW { w: self }
+    }
+    #[doc = "Bit 7 - SVMHOUT pin polarity active low"]
+    #[inline]
+    pub fn svmhoutpolal(&mut self) -> _SVMHOUTPOLALW {
+        _SVMHOUTPOLALW { w: self }
+    }
+    #[doc = "Bit 10 - Force DC-DC regulator operation"]
+    #[inline]
+    pub fn dcdc_force(&mut self) -> _DCDC_FORCEW {
+        _DCDC_FORCEW { w: self }
+    }
+    #[doc = "Bits 12:13 - Controls core voltage level transition time"]
+    #[inline]
+    pub fn vcoretran(&mut self) -> _VCORETRANW {
+        _VCORETRANW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pss/pssie.rs b/example-source/msp432p401r/src/pss/pssie.rs
new file mode 100644
index 0000000..15923ff
--- /dev/null
+++ b/example-source/msp432p401r/src/pss/pssie.rs
@@ -0,0 +1,183 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::PSSIE {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `SVSMHIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SVSMHIER {
+    #[doc = "Interrupt disabled"]
+    SVSMHIE_0,
+    #[doc = "Interrupt enabled"]
+    SVSMHIE_1,
+}
+impl SVSMHIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            SVSMHIER::SVSMHIE_0 => false,
+            SVSMHIER::SVSMHIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> SVSMHIER {
+        match value {
+            false => SVSMHIER::SVSMHIE_0,
+            true => SVSMHIER::SVSMHIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SVSMHIE_0`"]
+    #[inline]
+    pub fn is_svsmhie_0(&self) -> bool {
+        *self == SVSMHIER::SVSMHIE_0
+    }
+    #[doc = "Checks if the value of the field is `SVSMHIE_1`"]
+    #[inline]
+    pub fn is_svsmhie_1(&self) -> bool {
+        *self == SVSMHIER::SVSMHIE_1
+    }
+}
+#[doc = "Values that can be written to the field `SVSMHIE`"]
+pub enum SVSMHIEW {
+    #[doc = "Interrupt disabled"]
+    SVSMHIE_0,
+    #[doc = "Interrupt enabled"]
+    SVSMHIE_1,
+}
+impl SVSMHIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            SVSMHIEW::SVSMHIE_0 => false,
+            SVSMHIEW::SVSMHIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SVSMHIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SVSMHIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SVSMHIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn svsmhie_0(self) -> &'a mut W {
+        self.variant(SVSMHIEW::SVSMHIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn svsmhie_1(self) -> &'a mut W {
+        self.variant(SVSMHIEW::SVSMHIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 1 - High-side SVSM interrupt enable"]
+    #[inline]
+    pub fn svsmhie(&self) -> SVSMHIER {
+        SVSMHIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 1 - High-side SVSM interrupt enable"]
+    #[inline]
+    pub fn svsmhie(&mut self) -> _SVSMHIEW {
+        _SVSMHIEW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/pss/pssifg.rs b/example-source/msp432p401r/src/pss/pssifg.rs
new file mode 100644
index 0000000..7b10858
--- /dev/null
+++ b/example-source/msp432p401r/src/pss/pssifg.rs
@@ -0,0 +1,76 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::PSSIFG {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `SVSMHIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SVSMHIFGR {
+    #[doc = "No interrupt pending"]
+    SVSMHIFG_0,
+    #[doc = "Interrupt due to SVSMH"]
+    SVSMHIFG_1,
+}
+impl SVSMHIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            SVSMHIFGR::SVSMHIFG_0 => false,
+            SVSMHIFGR::SVSMHIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> SVSMHIFGR {
+        match value {
+            false => SVSMHIFGR::SVSMHIFG_0,
+            true => SVSMHIFGR::SVSMHIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SVSMHIFG_0`"]
+    #[inline]
+    pub fn is_svsmhifg_0(&self) -> bool {
+        *self == SVSMHIFGR::SVSMHIFG_0
+    }
+    #[doc = "Checks if the value of the field is `SVSMHIFG_1`"]
+    #[inline]
+    pub fn is_svsmhifg_1(&self) -> bool {
+        *self == SVSMHIFGR::SVSMHIFG_1
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 1 - High-side SVSM interrupt flag"]
+    #[inline]
+    pub fn svsmhifg(&self) -> SVSMHIFGR {
+        SVSMHIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/pss/psskey.rs b/example-source/msp432p401r/src/pss/psskey.rs
new file mode 100644
index 0000000..d2b5664
--- /dev/null
+++ b/example-source/msp432p401r/src/pss/psskey.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::PSSKEY {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PSSKEYR {
+    bits: u16,
+}
+impl PSSKEYR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PSSKEYW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PSSKEYW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - PSS control key"]
+    #[inline]
+    pub fn psskey(&self) -> PSSKEYR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        PSSKEYR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 42390 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - PSS control key"]
+    #[inline]
+    pub fn psskey(&mut self) -> _PSSKEYW {
+        _PSSKEYW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/ref_a.rs b/example-source/msp432p401r/src/ref_a.rs
new file mode 100644
index 0000000..cfbf3c6
--- /dev/null
+++ b/example-source/msp432p401r/src/ref_a.rs
@@ -0,0 +1,12 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - REF Control Register 0"]
+    pub refctl0: REFCTL0,
+}
+#[doc = "REF Control Register 0"]
+pub struct REFCTL0 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "REF Control Register 0"]
+pub mod refctl0;
diff --git a/example-source/msp432p401r/src/ref_a/refctl0.rs b/example-source/msp432p401r/src/ref_a/refctl0.rs
new file mode 100644
index 0000000..2aa41f8
--- /dev/null
+++ b/example-source/msp432p401r/src/ref_a/refctl0.rs
@@ -0,0 +1,1115 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::REFCTL0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `REFON`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum REFONR {
+    #[doc = "Disables reference if no other reference requests are pending"]
+    REFON_0,
+    #[doc = "Enables reference in static mode"]
+    REFON_1,
+}
+impl REFONR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            REFONR::REFON_0 => false,
+            REFONR::REFON_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> REFONR {
+        match value {
+            false => REFONR::REFON_0,
+            true => REFONR::REFON_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `REFON_0`"]
+    #[inline]
+    pub fn is_refon_0(&self) -> bool {
+        *self == REFONR::REFON_0
+    }
+    #[doc = "Checks if the value of the field is `REFON_1`"]
+    #[inline]
+    pub fn is_refon_1(&self) -> bool {
+        *self == REFONR::REFON_1
+    }
+}
+#[doc = "Possible values of the field `REFOUT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum REFOUTR {
+    #[doc = "Reference output not available externally"]
+    REFOUT_0,
+    #[doc = "Reference output available externally. If ADC14REFBURST = 0, output is available continuously. If ADC14REFBURST = 1, output is available only during an ADC14 conversion."]
+    REFOUT_1,
+}
+impl REFOUTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            REFOUTR::REFOUT_0 => false,
+            REFOUTR::REFOUT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> REFOUTR {
+        match value {
+            false => REFOUTR::REFOUT_0,
+            true => REFOUTR::REFOUT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `REFOUT_0`"]
+    #[inline]
+    pub fn is_refout_0(&self) -> bool {
+        *self == REFOUTR::REFOUT_0
+    }
+    #[doc = "Checks if the value of the field is `REFOUT_1`"]
+    #[inline]
+    pub fn is_refout_1(&self) -> bool {
+        *self == REFOUTR::REFOUT_1
+    }
+}
+#[doc = "Possible values of the field `REFTCOFF`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum REFTCOFFR {
+    #[doc = "Temperature sensor enabled"]
+    REFTCOFF_0,
+    #[doc = "Temperature sensor disabled to save power"]
+    REFTCOFF_1,
+}
+impl REFTCOFFR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            REFTCOFFR::REFTCOFF_0 => false,
+            REFTCOFFR::REFTCOFF_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> REFTCOFFR {
+        match value {
+            false => REFTCOFFR::REFTCOFF_0,
+            true => REFTCOFFR::REFTCOFF_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `REFTCOFF_0`"]
+    #[inline]
+    pub fn is_reftcoff_0(&self) -> bool {
+        *self == REFTCOFFR::REFTCOFF_0
+    }
+    #[doc = "Checks if the value of the field is `REFTCOFF_1`"]
+    #[inline]
+    pub fn is_reftcoff_1(&self) -> bool {
+        *self == REFTCOFFR::REFTCOFF_1
+    }
+}
+#[doc = "Possible values of the field `REFVSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum REFVSELR {
+    #[doc = "1.2 V available when reference requested or REFON = 1"]
+    REFVSEL_0,
+    #[doc = "1.45 V available when reference requested or REFON = 1"]
+    REFVSEL_1,
+    #[doc = "2.5 V available when reference requested or REFON = 1"]
+    REFVSEL_3,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl REFVSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            REFVSELR::REFVSEL_0 => 0,
+            REFVSELR::REFVSEL_1 => 1,
+            REFVSELR::REFVSEL_3 => 3,
+            REFVSELR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> REFVSELR {
+        match value {
+            0 => REFVSELR::REFVSEL_0,
+            1 => REFVSELR::REFVSEL_1,
+            3 => REFVSELR::REFVSEL_3,
+            i => REFVSELR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `REFVSEL_0`"]
+    #[inline]
+    pub fn is_refvsel_0(&self) -> bool {
+        *self == REFVSELR::REFVSEL_0
+    }
+    #[doc = "Checks if the value of the field is `REFVSEL_1`"]
+    #[inline]
+    pub fn is_refvsel_1(&self) -> bool {
+        *self == REFVSELR::REFVSEL_1
+    }
+    #[doc = "Checks if the value of the field is `REFVSEL_3`"]
+    #[inline]
+    pub fn is_refvsel_3(&self) -> bool {
+        *self == REFVSELR::REFVSEL_3
+    }
+}
+#[doc = "Possible values of the field `REFGENOT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum REFGENOTR {
+    #[doc = "No trigger"]
+    REFGENOT_0,
+    #[doc = "Generation of the reference voltage is started by writing 1 or by a hardware trigger"]
+    REFGENOT_1,
+}
+impl REFGENOTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            REFGENOTR::REFGENOT_0 => false,
+            REFGENOTR::REFGENOT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> REFGENOTR {
+        match value {
+            false => REFGENOTR::REFGENOT_0,
+            true => REFGENOTR::REFGENOT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `REFGENOT_0`"]
+    #[inline]
+    pub fn is_refgenot_0(&self) -> bool {
+        *self == REFGENOTR::REFGENOT_0
+    }
+    #[doc = "Checks if the value of the field is `REFGENOT_1`"]
+    #[inline]
+    pub fn is_refgenot_1(&self) -> bool {
+        *self == REFGENOTR::REFGENOT_1
+    }
+}
+#[doc = "Possible values of the field `REFBGOT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum REFBGOTR {
+    #[doc = "No trigger"]
+    REFBGOT_0,
+    #[doc = "Generation of the bandgap voltage is started by writing 1 or by a hardware trigger"]
+    REFBGOT_1,
+}
+impl REFBGOTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            REFBGOTR::REFBGOT_0 => false,
+            REFBGOTR::REFBGOT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> REFBGOTR {
+        match value {
+            false => REFBGOTR::REFBGOT_0,
+            true => REFBGOTR::REFBGOT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `REFBGOT_0`"]
+    #[inline]
+    pub fn is_refbgot_0(&self) -> bool {
+        *self == REFBGOTR::REFBGOT_0
+    }
+    #[doc = "Checks if the value of the field is `REFBGOT_1`"]
+    #[inline]
+    pub fn is_refbgot_1(&self) -> bool {
+        *self == REFBGOTR::REFBGOT_1
+    }
+}
+#[doc = "Possible values of the field `REFGENACT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum REFGENACTR {
+    #[doc = "Reference generator not active"]
+    REFGENACT_0,
+    #[doc = "Reference generator active"]
+    REFGENACT_1,
+}
+impl REFGENACTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            REFGENACTR::REFGENACT_0 => false,
+            REFGENACTR::REFGENACT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> REFGENACTR {
+        match value {
+            false => REFGENACTR::REFGENACT_0,
+            true => REFGENACTR::REFGENACT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `REFGENACT_0`"]
+    #[inline]
+    pub fn is_refgenact_0(&self) -> bool {
+        *self == REFGENACTR::REFGENACT_0
+    }
+    #[doc = "Checks if the value of the field is `REFGENACT_1`"]
+    #[inline]
+    pub fn is_refgenact_1(&self) -> bool {
+        *self == REFGENACTR::REFGENACT_1
+    }
+}
+#[doc = "Possible values of the field `REFBGACT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum REFBGACTR {
+    #[doc = "Reference bandgap buffer not active"]
+    REFBGACT_0,
+    #[doc = "Reference bandgap buffer active"]
+    REFBGACT_1,
+}
+impl REFBGACTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            REFBGACTR::REFBGACT_0 => false,
+            REFBGACTR::REFBGACT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> REFBGACTR {
+        match value {
+            false => REFBGACTR::REFBGACT_0,
+            true => REFBGACTR::REFBGACT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `REFBGACT_0`"]
+    #[inline]
+    pub fn is_refbgact_0(&self) -> bool {
+        *self == REFBGACTR::REFBGACT_0
+    }
+    #[doc = "Checks if the value of the field is `REFBGACT_1`"]
+    #[inline]
+    pub fn is_refbgact_1(&self) -> bool {
+        *self == REFBGACTR::REFBGACT_1
+    }
+}
+#[doc = "Possible values of the field `REFGENBUSY`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum REFGENBUSYR {
+    #[doc = "Reference generator not busy"]
+    REFGENBUSY_0,
+    #[doc = "Reference generator busy"]
+    REFGENBUSY_1,
+}
+impl REFGENBUSYR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            REFGENBUSYR::REFGENBUSY_0 => false,
+            REFGENBUSYR::REFGENBUSY_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> REFGENBUSYR {
+        match value {
+            false => REFGENBUSYR::REFGENBUSY_0,
+            true => REFGENBUSYR::REFGENBUSY_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `REFGENBUSY_0`"]
+    #[inline]
+    pub fn is_refgenbusy_0(&self) -> bool {
+        *self == REFGENBUSYR::REFGENBUSY_0
+    }
+    #[doc = "Checks if the value of the field is `REFGENBUSY_1`"]
+    #[inline]
+    pub fn is_refgenbusy_1(&self) -> bool {
+        *self == REFGENBUSYR::REFGENBUSY_1
+    }
+}
+#[doc = "Possible values of the field `BGMODE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum BGMODER {
+    #[doc = "Static mode"]
+    BGMODE_0,
+    #[doc = "Sampled mode"]
+    BGMODE_1,
+}
+impl BGMODER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            BGMODER::BGMODE_0 => false,
+            BGMODER::BGMODE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> BGMODER {
+        match value {
+            false => BGMODER::BGMODE_0,
+            true => BGMODER::BGMODE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `BGMODE_0`"]
+    #[inline]
+    pub fn is_bgmode_0(&self) -> bool {
+        *self == BGMODER::BGMODE_0
+    }
+    #[doc = "Checks if the value of the field is `BGMODE_1`"]
+    #[inline]
+    pub fn is_bgmode_1(&self) -> bool {
+        *self == BGMODER::BGMODE_1
+    }
+}
+#[doc = "Possible values of the field `REFGENRDY`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum REFGENRDYR {
+    #[doc = "Reference voltage output is not ready to be used"]
+    REFGENRDY_0,
+    #[doc = "Reference voltage output is ready to be used"]
+    REFGENRDY_1,
+}
+impl REFGENRDYR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            REFGENRDYR::REFGENRDY_0 => false,
+            REFGENRDYR::REFGENRDY_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> REFGENRDYR {
+        match value {
+            false => REFGENRDYR::REFGENRDY_0,
+            true => REFGENRDYR::REFGENRDY_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `REFGENRDY_0`"]
+    #[inline]
+    pub fn is_refgenrdy_0(&self) -> bool {
+        *self == REFGENRDYR::REFGENRDY_0
+    }
+    #[doc = "Checks if the value of the field is `REFGENRDY_1`"]
+    #[inline]
+    pub fn is_refgenrdy_1(&self) -> bool {
+        *self == REFGENRDYR::REFGENRDY_1
+    }
+}
+#[doc = "Possible values of the field `REFBGRDY`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum REFBGRDYR {
+    #[doc = "Buffered bandgap voltage is not ready to be used"]
+    REFBGRDY_0,
+    #[doc = "Buffered bandgap voltage is ready to be used"]
+    REFBGRDY_1,
+}
+impl REFBGRDYR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            REFBGRDYR::REFBGRDY_0 => false,
+            REFBGRDYR::REFBGRDY_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> REFBGRDYR {
+        match value {
+            false => REFBGRDYR::REFBGRDY_0,
+            true => REFBGRDYR::REFBGRDY_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `REFBGRDY_0`"]
+    #[inline]
+    pub fn is_refbgrdy_0(&self) -> bool {
+        *self == REFBGRDYR::REFBGRDY_0
+    }
+    #[doc = "Checks if the value of the field is `REFBGRDY_1`"]
+    #[inline]
+    pub fn is_refbgrdy_1(&self) -> bool {
+        *self == REFBGRDYR::REFBGRDY_1
+    }
+}
+#[doc = "Values that can be written to the field `REFON`"]
+pub enum REFONW {
+    #[doc = "Disables reference if no other reference requests are pending"]
+    REFON_0,
+    #[doc = "Enables reference in static mode"]
+    REFON_1,
+}
+impl REFONW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            REFONW::REFON_0 => false,
+            REFONW::REFON_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _REFONW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _REFONW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: REFONW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disables reference if no other reference requests are pending"]
+    #[inline]
+    pub fn refon_0(self) -> &'a mut W {
+        self.variant(REFONW::REFON_0)
+    }
+    #[doc = "Enables reference in static mode"]
+    #[inline]
+    pub fn refon_1(self) -> &'a mut W {
+        self.variant(REFONW::REFON_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `REFOUT`"]
+pub enum REFOUTW {
+    #[doc = "Reference output not available externally"]
+    REFOUT_0,
+    #[doc = "Reference output available externally. If ADC14REFBURST = 0, output is available continuously. If ADC14REFBURST = 1, output is available only during an ADC14 conversion."]
+    REFOUT_1,
+}
+impl REFOUTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            REFOUTW::REFOUT_0 => false,
+            REFOUTW::REFOUT_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _REFOUTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _REFOUTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: REFOUTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Reference output not available externally"]
+    #[inline]
+    pub fn refout_0(self) -> &'a mut W {
+        self.variant(REFOUTW::REFOUT_0)
+    }
+    #[doc = "Reference output available externally. If ADC14REFBURST = 0, output is available continuously. If ADC14REFBURST = 1, output is available only during an ADC14 conversion."]
+    #[inline]
+    pub fn refout_1(self) -> &'a mut W {
+        self.variant(REFOUTW::REFOUT_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `REFTCOFF`"]
+pub enum REFTCOFFW {
+    #[doc = "Temperature sensor enabled"]
+    REFTCOFF_0,
+    #[doc = "Temperature sensor disabled to save power"]
+    REFTCOFF_1,
+}
+impl REFTCOFFW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            REFTCOFFW::REFTCOFF_0 => false,
+            REFTCOFFW::REFTCOFF_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _REFTCOFFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _REFTCOFFW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: REFTCOFFW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Temperature sensor enabled"]
+    #[inline]
+    pub fn reftcoff_0(self) -> &'a mut W {
+        self.variant(REFTCOFFW::REFTCOFF_0)
+    }
+    #[doc = "Temperature sensor disabled to save power"]
+    #[inline]
+    pub fn reftcoff_1(self) -> &'a mut W {
+        self.variant(REFTCOFFW::REFTCOFF_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `REFVSEL`"]
+pub enum REFVSELW {
+    #[doc = "1.2 V available when reference requested or REFON = 1"]
+    REFVSEL_0,
+    #[doc = "1.45 V available when reference requested or REFON = 1"]
+    REFVSEL_1,
+    #[doc = "2.5 V available when reference requested or REFON = 1"]
+    REFVSEL_3,
+}
+impl REFVSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            REFVSELW::REFVSEL_0 => 0,
+            REFVSELW::REFVSEL_1 => 1,
+            REFVSELW::REFVSEL_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _REFVSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _REFVSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: REFVSELW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "1.2 V available when reference requested or REFON = 1"]
+    #[inline]
+    pub fn refvsel_0(self) -> &'a mut W {
+        self.variant(REFVSELW::REFVSEL_0)
+    }
+    #[doc = "1.45 V available when reference requested or REFON = 1"]
+    #[inline]
+    pub fn refvsel_1(self) -> &'a mut W {
+        self.variant(REFVSELW::REFVSEL_1)
+    }
+    #[doc = "2.5 V available when reference requested or REFON = 1"]
+    #[inline]
+    pub fn refvsel_3(self) -> &'a mut W {
+        self.variant(REFVSELW::REFVSEL_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `REFGENOT`"]
+pub enum REFGENOTW {
+    #[doc = "No trigger"]
+    REFGENOT_0,
+    #[doc = "Generation of the reference voltage is started by writing 1 or by a hardware trigger"]
+    REFGENOT_1,
+}
+impl REFGENOTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            REFGENOTW::REFGENOT_0 => false,
+            REFGENOTW::REFGENOT_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _REFGENOTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _REFGENOTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: REFGENOTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No trigger"]
+    #[inline]
+    pub fn refgenot_0(self) -> &'a mut W {
+        self.variant(REFGENOTW::REFGENOT_0)
+    }
+    #[doc = "Generation of the reference voltage is started by writing 1 or by a hardware trigger"]
+    #[inline]
+    pub fn refgenot_1(self) -> &'a mut W {
+        self.variant(REFGENOTW::REFGENOT_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `REFBGOT`"]
+pub enum REFBGOTW {
+    #[doc = "No trigger"]
+    REFBGOT_0,
+    #[doc = "Generation of the bandgap voltage is started by writing 1 or by a hardware trigger"]
+    REFBGOT_1,
+}
+impl REFBGOTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            REFBGOTW::REFBGOT_0 => false,
+            REFBGOTW::REFBGOT_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _REFBGOTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _REFBGOTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: REFBGOTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No trigger"]
+    #[inline]
+    pub fn refbgot_0(self) -> &'a mut W {
+        self.variant(REFBGOTW::REFBGOT_0)
+    }
+    #[doc = "Generation of the bandgap voltage is started by writing 1 or by a hardware trigger"]
+    #[inline]
+    pub fn refbgot_1(self) -> &'a mut W {
+        self.variant(REFBGOTW::REFBGOT_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Reference enable"]
+    #[inline]
+    pub fn refon(&self) -> REFONR {
+        REFONR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Reference output buffer"]
+    #[inline]
+    pub fn refout(&self) -> REFOUTR {
+        REFOUTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Temperature sensor disabled"]
+    #[inline]
+    pub fn reftcoff(&self) -> REFTCOFFR {
+        REFTCOFFR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 4:5 - Reference voltage level select"]
+    #[inline]
+    pub fn refvsel(&self) -> REFVSELR {
+        REFVSELR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 6 - Reference generator one-time trigger"]
+    #[inline]
+    pub fn refgenot(&self) -> REFGENOTR {
+        REFGENOTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 7 - Bandgap and bandgap buffer one-time trigger"]
+    #[inline]
+    pub fn refbgot(&self) -> REFBGOTR {
+        REFBGOTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 8 - Reference generator active"]
+    #[inline]
+    pub fn refgenact(&self) -> REFGENACTR {
+        REFGENACTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 9 - Reference bandgap active"]
+    #[inline]
+    pub fn refbgact(&self) -> REFBGACTR {
+        REFBGACTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 10 - Reference generator busy"]
+    #[inline]
+    pub fn refgenbusy(&self) -> REFGENBUSYR {
+        REFGENBUSYR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 11 - Bandgap mode"]
+    #[inline]
+    pub fn bgmode(&self) -> BGMODER {
+        BGMODER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 12 - Variable reference voltage ready status"]
+    #[inline]
+    pub fn refgenrdy(&self) -> REFGENRDYR {
+        REFGENRDYR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 13 - Buffered bandgap voltage ready status"]
+    #[inline]
+    pub fn refbgrdy(&self) -> REFBGRDYR {
+        REFBGRDYR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Reference enable"]
+    #[inline]
+    pub fn refon(&mut self) -> _REFONW {
+        _REFONW { w: self }
+    }
+    #[doc = "Bit 1 - Reference output buffer"]
+    #[inline]
+    pub fn refout(&mut self) -> _REFOUTW {
+        _REFOUTW { w: self }
+    }
+    #[doc = "Bit 3 - Temperature sensor disabled"]
+    #[inline]
+    pub fn reftcoff(&mut self) -> _REFTCOFFW {
+        _REFTCOFFW { w: self }
+    }
+    #[doc = "Bits 4:5 - Reference voltage level select"]
+    #[inline]
+    pub fn refvsel(&mut self) -> _REFVSELW {
+        _REFVSELW { w: self }
+    }
+    #[doc = "Bit 6 - Reference generator one-time trigger"]
+    #[inline]
+    pub fn refgenot(&mut self) -> _REFGENOTW {
+        _REFGENOTW { w: self }
+    }
+    #[doc = "Bit 7 - Bandgap and bandgap buffer one-time trigger"]
+    #[inline]
+    pub fn refbgot(&mut self) -> _REFBGOTW {
+        _REFBGOTW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/rstctl.rs b/example-source/msp432p401r/src/rstctl.rs
new file mode 100644
index 0000000..eb9045d
--- /dev/null
+++ b/example-source/msp432p401r/src/rstctl.rs
@@ -0,0 +1,141 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - Reset Request Register"]
+    pub rstctl_reset_req: RSTCTL_RESET_REQ,
+    #[doc = "0x04 - Hard Reset Status Register"]
+    pub rstctl_hardreset_stat: RSTCTL_HARDRESET_STAT,
+    #[doc = "0x08 - Hard Reset Status Clear Register"]
+    pub rstctl_hardreset_clr: RSTCTL_HARDRESET_CLR,
+    #[doc = "0x0c - Hard Reset Status Set Register"]
+    pub rstctl_hardreset_set: RSTCTL_HARDRESET_SET,
+    #[doc = "0x10 - Soft Reset Status Register"]
+    pub rstctl_softreset_stat: RSTCTL_SOFTRESET_STAT,
+    #[doc = "0x14 - Soft Reset Status Clear Register"]
+    pub rstctl_softreset_clr: RSTCTL_SOFTRESET_CLR,
+    #[doc = "0x18 - Soft Reset Status Set Register"]
+    pub rstctl_softreset_set: RSTCTL_SOFTRESET_SET,
+    _reserved0: [u8; 228usize],
+    #[doc = "0x100 - PSS Reset Status Register"]
+    pub rstctl_pssreset_stat: RSTCTL_PSSRESET_STAT,
+    #[doc = "0x104 - PSS Reset Status Clear Register"]
+    pub rstctl_pssreset_clr: RSTCTL_PSSRESET_CLR,
+    #[doc = "0x108 - PCM Reset Status Register"]
+    pub rstctl_pcmreset_stat: RSTCTL_PCMRESET_STAT,
+    #[doc = "0x10c - PCM Reset Status Clear Register"]
+    pub rstctl_pcmreset_clr: RSTCTL_PCMRESET_CLR,
+    #[doc = "0x110 - Pin Reset Status Register"]
+    pub rstctl_pinreset_stat: RSTCTL_PINRESET_STAT,
+    #[doc = "0x114 - Pin Reset Status Clear Register"]
+    pub rstctl_pinreset_clr: RSTCTL_PINRESET_CLR,
+    #[doc = "0x118 - Reboot Reset Status Register"]
+    pub rstctl_rebootreset_stat: RSTCTL_REBOOTRESET_STAT,
+    #[doc = "0x11c - Reboot Reset Status Clear Register"]
+    pub rstctl_rebootreset_clr: RSTCTL_REBOOTRESET_CLR,
+    #[doc = "0x120 - CS Reset Status Register"]
+    pub rstctl_csreset_stat: RSTCTL_CSRESET_STAT,
+    #[doc = "0x124 - CS Reset Status Clear Register"]
+    pub rstctl_csreset_clr: RSTCTL_CSRESET_CLR,
+}
+#[doc = "Reset Request Register"]
+pub struct RSTCTL_RESET_REQ {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reset Request Register"]
+pub mod rstctl_reset_req;
+#[doc = "Hard Reset Status Register"]
+pub struct RSTCTL_HARDRESET_STAT {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Hard Reset Status Register"]
+pub mod rstctl_hardreset_stat;
+#[doc = "Hard Reset Status Clear Register"]
+pub struct RSTCTL_HARDRESET_CLR {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Hard Reset Status Clear Register"]
+pub mod rstctl_hardreset_clr;
+#[doc = "Hard Reset Status Set Register"]
+pub struct RSTCTL_HARDRESET_SET {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Hard Reset Status Set Register"]
+pub mod rstctl_hardreset_set;
+#[doc = "Soft Reset Status Register"]
+pub struct RSTCTL_SOFTRESET_STAT {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Soft Reset Status Register"]
+pub mod rstctl_softreset_stat;
+#[doc = "Soft Reset Status Clear Register"]
+pub struct RSTCTL_SOFTRESET_CLR {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Soft Reset Status Clear Register"]
+pub mod rstctl_softreset_clr;
+#[doc = "Soft Reset Status Set Register"]
+pub struct RSTCTL_SOFTRESET_SET {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Soft Reset Status Set Register"]
+pub mod rstctl_softreset_set;
+#[doc = "PSS Reset Status Register"]
+pub struct RSTCTL_PSSRESET_STAT {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "PSS Reset Status Register"]
+pub mod rstctl_pssreset_stat;
+#[doc = "PSS Reset Status Clear Register"]
+pub struct RSTCTL_PSSRESET_CLR {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "PSS Reset Status Clear Register"]
+pub mod rstctl_pssreset_clr;
+#[doc = "PCM Reset Status Register"]
+pub struct RSTCTL_PCMRESET_STAT {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "PCM Reset Status Register"]
+pub mod rstctl_pcmreset_stat;
+#[doc = "PCM Reset Status Clear Register"]
+pub struct RSTCTL_PCMRESET_CLR {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "PCM Reset Status Clear Register"]
+pub mod rstctl_pcmreset_clr;
+#[doc = "Pin Reset Status Register"]
+pub struct RSTCTL_PINRESET_STAT {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Pin Reset Status Register"]
+pub mod rstctl_pinreset_stat;
+#[doc = "Pin Reset Status Clear Register"]
+pub struct RSTCTL_PINRESET_CLR {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Pin Reset Status Clear Register"]
+pub mod rstctl_pinreset_clr;
+#[doc = "Reboot Reset Status Register"]
+pub struct RSTCTL_REBOOTRESET_STAT {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reboot Reset Status Register"]
+pub mod rstctl_rebootreset_stat;
+#[doc = "Reboot Reset Status Clear Register"]
+pub struct RSTCTL_REBOOTRESET_CLR {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reboot Reset Status Clear Register"]
+pub mod rstctl_rebootreset_clr;
+#[doc = "CS Reset Status Register"]
+pub struct RSTCTL_CSRESET_STAT {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "CS Reset Status Register"]
+pub mod rstctl_csreset_stat;
+#[doc = "CS Reset Status Clear Register"]
+pub struct RSTCTL_CSRESET_CLR {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "CS Reset Status Clear Register"]
+pub mod rstctl_csreset_clr;
diff --git a/example-source/msp432p401r/src/rstctl/rstctl_csreset_clr.rs b/example-source/msp432p401r/src/rstctl/rstctl_csreset_clr.rs
new file mode 100644
index 0000000..c3aadb3
--- /dev/null
+++ b/example-source/msp432p401r/src/rstctl/rstctl_csreset_clr.rs
@@ -0,0 +1,92 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::RSTCTL_CSRESET_CLR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Write 1 clears the DCOR_SHT Flag in RSTCTL_CSRESET_STAT as well as DCOR_SHTIFG flag in CSIFG register of clock system"]
+    #[inline]
+    pub fn clr(&mut self) -> _CLRW {
+        _CLRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/rstctl/rstctl_csreset_stat.rs b/example-source/msp432p401r/src/rstctl/rstctl_csreset_stat.rs
new file mode 100644
index 0000000..bb2b04c
--- /dev/null
+++ b/example-source/msp432p401r/src/rstctl/rstctl_csreset_stat.rs
@@ -0,0 +1,51 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RSTCTL_CSRESET_STAT {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DCOR_SHTR {
+    bits: bool,
+}
+impl DCOR_SHTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Indicates if POR was caused by DCO short circuit fault in the external resistor mode"]
+    #[inline]
+    pub fn dcor_sht(&self) -> DCOR_SHTR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        DCOR_SHTR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/rstctl/rstctl_hardreset_clr.rs b/example-source/msp432p401r/src/rstctl/rstctl_hardreset_clr.rs
new file mode 100644
index 0000000..f0b1bad
--- /dev/null
+++ b/example-source/msp432p401r/src/rstctl/rstctl_hardreset_clr.rs
@@ -0,0 +1,512 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::RSTCTL_HARDRESET_CLR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC0W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC1W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC2W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC3W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC4W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC4W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC5W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC5W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC6W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC6W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC7W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC7W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC8W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC8W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC9W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC9W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC10W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC10W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC11W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC11W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC12W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC12W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC13W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC13W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC14W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC14W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC15W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC15W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT"]
+    #[inline]
+    pub fn src0(&mut self) -> _SRC0W {
+        _SRC0W { w: self }
+    }
+    #[doc = "Bit 1 - Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT"]
+    #[inline]
+    pub fn src1(&mut self) -> _SRC1W {
+        _SRC1W { w: self }
+    }
+    #[doc = "Bit 2 - Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT"]
+    #[inline]
+    pub fn src2(&mut self) -> _SRC2W {
+        _SRC2W { w: self }
+    }
+    #[doc = "Bit 3 - Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT"]
+    #[inline]
+    pub fn src3(&mut self) -> _SRC3W {
+        _SRC3W { w: self }
+    }
+    #[doc = "Bit 4 - Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT"]
+    #[inline]
+    pub fn src4(&mut self) -> _SRC4W {
+        _SRC4W { w: self }
+    }
+    #[doc = "Bit 5 - Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT"]
+    #[inline]
+    pub fn src5(&mut self) -> _SRC5W {
+        _SRC5W { w: self }
+    }
+    #[doc = "Bit 6 - Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT"]
+    #[inline]
+    pub fn src6(&mut self) -> _SRC6W {
+        _SRC6W { w: self }
+    }
+    #[doc = "Bit 7 - Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT"]
+    #[inline]
+    pub fn src7(&mut self) -> _SRC7W {
+        _SRC7W { w: self }
+    }
+    #[doc = "Bit 8 - Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT"]
+    #[inline]
+    pub fn src8(&mut self) -> _SRC8W {
+        _SRC8W { w: self }
+    }
+    #[doc = "Bit 9 - Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT"]
+    #[inline]
+    pub fn src9(&mut self) -> _SRC9W {
+        _SRC9W { w: self }
+    }
+    #[doc = "Bit 10 - Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT"]
+    #[inline]
+    pub fn src10(&mut self) -> _SRC10W {
+        _SRC10W { w: self }
+    }
+    #[doc = "Bit 11 - Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT"]
+    #[inline]
+    pub fn src11(&mut self) -> _SRC11W {
+        _SRC11W { w: self }
+    }
+    #[doc = "Bit 12 - Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT"]
+    #[inline]
+    pub fn src12(&mut self) -> _SRC12W {
+        _SRC12W { w: self }
+    }
+    #[doc = "Bit 13 - Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT"]
+    #[inline]
+    pub fn src13(&mut self) -> _SRC13W {
+        _SRC13W { w: self }
+    }
+    #[doc = "Bit 14 - Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT"]
+    #[inline]
+    pub fn src14(&mut self) -> _SRC14W {
+        _SRC14W { w: self }
+    }
+    #[doc = "Bit 15 - Write 1 clears the corresponding bit in the RSTCTL_HRDRESETSTAT_REG"]
+    #[inline]
+    pub fn src15(&mut self) -> _SRC15W {
+        _SRC15W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/rstctl/rstctl_hardreset_set.rs b/example-source/msp432p401r/src/rstctl/rstctl_hardreset_set.rs
new file mode 100644
index 0000000..18e4b06
--- /dev/null
+++ b/example-source/msp432p401r/src/rstctl/rstctl_hardreset_set.rs
@@ -0,0 +1,512 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::RSTCTL_HARDRESET_SET {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC0W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC1W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC2W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC3W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC4W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC4W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC5W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC5W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC6W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC6W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC7W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC7W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC8W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC8W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC9W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC9W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC10W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC10W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC11W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC11W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC12W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC12W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC13W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC13W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC14W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC14W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC15W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC15W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)"]
+    #[inline]
+    pub fn src0(&mut self) -> _SRC0W {
+        _SRC0W { w: self }
+    }
+    #[doc = "Bit 1 - Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)"]
+    #[inline]
+    pub fn src1(&mut self) -> _SRC1W {
+        _SRC1W { w: self }
+    }
+    #[doc = "Bit 2 - Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)"]
+    #[inline]
+    pub fn src2(&mut self) -> _SRC2W {
+        _SRC2W { w: self }
+    }
+    #[doc = "Bit 3 - Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)"]
+    #[inline]
+    pub fn src3(&mut self) -> _SRC3W {
+        _SRC3W { w: self }
+    }
+    #[doc = "Bit 4 - Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)"]
+    #[inline]
+    pub fn src4(&mut self) -> _SRC4W {
+        _SRC4W { w: self }
+    }
+    #[doc = "Bit 5 - Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)"]
+    #[inline]
+    pub fn src5(&mut self) -> _SRC5W {
+        _SRC5W { w: self }
+    }
+    #[doc = "Bit 6 - Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)"]
+    #[inline]
+    pub fn src6(&mut self) -> _SRC6W {
+        _SRC6W { w: self }
+    }
+    #[doc = "Bit 7 - Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)"]
+    #[inline]
+    pub fn src7(&mut self) -> _SRC7W {
+        _SRC7W { w: self }
+    }
+    #[doc = "Bit 8 - Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)"]
+    #[inline]
+    pub fn src8(&mut self) -> _SRC8W {
+        _SRC8W { w: self }
+    }
+    #[doc = "Bit 9 - Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)"]
+    #[inline]
+    pub fn src9(&mut self) -> _SRC9W {
+        _SRC9W { w: self }
+    }
+    #[doc = "Bit 10 - Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)"]
+    #[inline]
+    pub fn src10(&mut self) -> _SRC10W {
+        _SRC10W { w: self }
+    }
+    #[doc = "Bit 11 - Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)"]
+    #[inline]
+    pub fn src11(&mut self) -> _SRC11W {
+        _SRC11W { w: self }
+    }
+    #[doc = "Bit 12 - Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)"]
+    #[inline]
+    pub fn src12(&mut self) -> _SRC12W {
+        _SRC12W { w: self }
+    }
+    #[doc = "Bit 13 - Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)"]
+    #[inline]
+    pub fn src13(&mut self) -> _SRC13W {
+        _SRC13W { w: self }
+    }
+    #[doc = "Bit 14 - Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)"]
+    #[inline]
+    pub fn src14(&mut self) -> _SRC14W {
+        _SRC14W { w: self }
+    }
+    #[doc = "Bit 15 - Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)"]
+    #[inline]
+    pub fn src15(&mut self) -> _SRC15W {
+        _SRC15W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/rstctl/rstctl_hardreset_stat.rs b/example-source/msp432p401r/src/rstctl/rstctl_hardreset_stat.rs
new file mode 100644
index 0000000..e1b2d42
--- /dev/null
+++ b/example-source/msp432p401r/src/rstctl/rstctl_hardreset_stat.rs
@@ -0,0 +1,516 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RSTCTL_HARDRESET_STAT {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC0R {
+    bits: bool,
+}
+impl SRC0R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC1R {
+    bits: bool,
+}
+impl SRC1R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC2R {
+    bits: bool,
+}
+impl SRC2R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC3R {
+    bits: bool,
+}
+impl SRC3R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC4R {
+    bits: bool,
+}
+impl SRC4R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC5R {
+    bits: bool,
+}
+impl SRC5R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC6R {
+    bits: bool,
+}
+impl SRC6R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC7R {
+    bits: bool,
+}
+impl SRC7R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC8R {
+    bits: bool,
+}
+impl SRC8R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC9R {
+    bits: bool,
+}
+impl SRC9R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC10R {
+    bits: bool,
+}
+impl SRC10R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC11R {
+    bits: bool,
+}
+impl SRC11R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC12R {
+    bits: bool,
+}
+impl SRC12R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC13R {
+    bits: bool,
+}
+impl SRC13R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC14R {
+    bits: bool,
+}
+impl SRC14R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC15R {
+    bits: bool,
+}
+impl SRC15R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Indicates that SRC0 was the source of the Hard Reset"]
+    #[inline]
+    pub fn src0(&self) -> SRC0R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC0R { bits }
+    }
+    #[doc = "Bit 1 - Indicates that SRC1 was the source of the Hard Reset"]
+    #[inline]
+    pub fn src1(&self) -> SRC1R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC1R { bits }
+    }
+    #[doc = "Bit 2 - Indicates that SRC2 was the source of the Hard Reset"]
+    #[inline]
+    pub fn src2(&self) -> SRC2R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC2R { bits }
+    }
+    #[doc = "Bit 3 - Indicates that SRC3 was the source of the Hard Reset"]
+    #[inline]
+    pub fn src3(&self) -> SRC3R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC3R { bits }
+    }
+    #[doc = "Bit 4 - Indicates that SRC4 was the source of the Hard Reset"]
+    #[inline]
+    pub fn src4(&self) -> SRC4R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC4R { bits }
+    }
+    #[doc = "Bit 5 - Indicates that SRC5 was the source of the Hard Reset"]
+    #[inline]
+    pub fn src5(&self) -> SRC5R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC5R { bits }
+    }
+    #[doc = "Bit 6 - Indicates that SRC6 was the source of the Hard Reset"]
+    #[inline]
+    pub fn src6(&self) -> SRC6R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC6R { bits }
+    }
+    #[doc = "Bit 7 - Indicates that SRC7 was the source of the Hard Reset"]
+    #[inline]
+    pub fn src7(&self) -> SRC7R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC7R { bits }
+    }
+    #[doc = "Bit 8 - Indicates that SRC8 was the source of the Hard Reset"]
+    #[inline]
+    pub fn src8(&self) -> SRC8R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC8R { bits }
+    }
+    #[doc = "Bit 9 - Indicates that SRC9 was the source of the Hard Reset"]
+    #[inline]
+    pub fn src9(&self) -> SRC9R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC9R { bits }
+    }
+    #[doc = "Bit 10 - Indicates that SRC10 was the source of the Hard Reset"]
+    #[inline]
+    pub fn src10(&self) -> SRC10R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC10R { bits }
+    }
+    #[doc = "Bit 11 - Indicates that SRC11 was the source of the Hard Reset"]
+    #[inline]
+    pub fn src11(&self) -> SRC11R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC11R { bits }
+    }
+    #[doc = "Bit 12 - Indicates that SRC12 was the source of the Hard Reset"]
+    #[inline]
+    pub fn src12(&self) -> SRC12R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC12R { bits }
+    }
+    #[doc = "Bit 13 - Indicates that SRC13 was the source of the Hard Reset"]
+    #[inline]
+    pub fn src13(&self) -> SRC13R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC13R { bits }
+    }
+    #[doc = "Bit 14 - Indicates that SRC14 was the source of the Hard Reset"]
+    #[inline]
+    pub fn src14(&self) -> SRC14R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC14R { bits }
+    }
+    #[doc = "Bit 15 - Indicates that SRC15 was the source of the Hard Reset"]
+    #[inline]
+    pub fn src15(&self) -> SRC15R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC15R { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/rstctl/rstctl_pcmreset_clr.rs b/example-source/msp432p401r/src/rstctl/rstctl_pcmreset_clr.rs
new file mode 100644
index 0000000..b773e02
--- /dev/null
+++ b/example-source/msp432p401r/src/rstctl/rstctl_pcmreset_clr.rs
@@ -0,0 +1,92 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::RSTCTL_PCMRESET_CLR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Write 1 clears all PCM Reset Flags in the RSTCTL_PCMRESET_STAT"]
+    #[inline]
+    pub fn clr(&mut self) -> _CLRW {
+        _CLRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/rstctl/rstctl_pcmreset_stat.rs b/example-source/msp432p401r/src/rstctl/rstctl_pcmreset_stat.rs
new file mode 100644
index 0000000..f777a0d
--- /dev/null
+++ b/example-source/msp432p401r/src/rstctl/rstctl_pcmreset_stat.rs
@@ -0,0 +1,82 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RSTCTL_PCMRESET_STAT {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct LPM35R {
+    bits: bool,
+}
+impl LPM35R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct LPM45R {
+    bits: bool,
+}
+impl LPM45R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Indicates if POR was caused by PCM due to an exit from LPM3.5"]
+    #[inline]
+    pub fn lpm35(&self) -> LPM35R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        LPM35R { bits }
+    }
+    #[doc = "Bit 1 - Indicates if POR was caused by PCM due to an exit from LPM4.5"]
+    #[inline]
+    pub fn lpm45(&self) -> LPM45R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        LPM45R { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/rstctl/rstctl_pinreset_clr.rs b/example-source/msp432p401r/src/rstctl/rstctl_pinreset_clr.rs
new file mode 100644
index 0000000..0c5e820
--- /dev/null
+++ b/example-source/msp432p401r/src/rstctl/rstctl_pinreset_clr.rs
@@ -0,0 +1,92 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::RSTCTL_PINRESET_CLR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Write 1 clears the RSTn/NMI Pin Reset Flag in RSTCTL_PINRESET_STAT"]
+    #[inline]
+    pub fn clr(&mut self) -> _CLRW {
+        _CLRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/rstctl/rstctl_pinreset_stat.rs b/example-source/msp432p401r/src/rstctl/rstctl_pinreset_stat.rs
new file mode 100644
index 0000000..049bb76
--- /dev/null
+++ b/example-source/msp432p401r/src/rstctl/rstctl_pinreset_stat.rs
@@ -0,0 +1,51 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RSTCTL_PINRESET_STAT {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct RSTNMIR {
+    bits: bool,
+}
+impl RSTNMIR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - POR was caused by RSTn/NMI pin based reset event"]
+    #[inline]
+    pub fn rstnmi(&self) -> RSTNMIR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        RSTNMIR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/rstctl/rstctl_pssreset_clr.rs b/example-source/msp432p401r/src/rstctl/rstctl_pssreset_clr.rs
new file mode 100644
index 0000000..5afa714
--- /dev/null
+++ b/example-source/msp432p401r/src/rstctl/rstctl_pssreset_clr.rs
@@ -0,0 +1,92 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::RSTCTL_PSSRESET_CLR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Write 1 clears all PSS Reset Flags in the RSTCTL_PSSRESET_STAT"]
+    #[inline]
+    pub fn clr(&mut self) -> _CLRW {
+        _CLRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/rstctl/rstctl_pssreset_stat.rs b/example-source/msp432p401r/src/rstctl/rstctl_pssreset_stat.rs
new file mode 100644
index 0000000..0d237ae
--- /dev/null
+++ b/example-source/msp432p401r/src/rstctl/rstctl_pssreset_stat.rs
@@ -0,0 +1,144 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RSTCTL_PSSRESET_STAT {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SVSMHR {
+    bits: bool,
+}
+impl SVSMHR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct BGREFR {
+    bits: bool,
+}
+impl BGREFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct VCCDETR {
+    bits: bool,
+}
+impl VCCDETR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SVSLR {
+    bits: bool,
+}
+impl SVSLR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 1 - Indicates if POR was caused by an SVSMH trip condition int the PSS"]
+    #[inline]
+    pub fn svsmh(&self) -> SVSMHR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SVSMHR { bits }
+    }
+    #[doc = "Bit 2 - Indicates if POR was caused by a BGREF not okay condition in the PSS"]
+    #[inline]
+    pub fn bgref(&self) -> BGREFR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        BGREFR { bits }
+    }
+    #[doc = "Bit 3 - Indicates if POR was caused by a VCCDET trip condition in the PSS"]
+    #[inline]
+    pub fn vccdet(&self) -> VCCDETR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        VCCDETR { bits }
+    }
+    #[doc = "Bit 0 - Indicates if POR was caused by an SVSL trip condition in the PSS"]
+    #[inline]
+    pub fn svsl(&self) -> SVSLR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SVSLR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/rstctl/rstctl_rebootreset_clr.rs b/example-source/msp432p401r/src/rstctl/rstctl_rebootreset_clr.rs
new file mode 100644
index 0000000..02edc71
--- /dev/null
+++ b/example-source/msp432p401r/src/rstctl/rstctl_rebootreset_clr.rs
@@ -0,0 +1,92 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::RSTCTL_REBOOTRESET_CLR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Write 1 clears the Reboot Reset Flag in RSTCTL_REBOOTRESET_STAT"]
+    #[inline]
+    pub fn clr(&mut self) -> _CLRW {
+        _CLRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/rstctl/rstctl_rebootreset_stat.rs b/example-source/msp432p401r/src/rstctl/rstctl_rebootreset_stat.rs
new file mode 100644
index 0000000..ea63c3b
--- /dev/null
+++ b/example-source/msp432p401r/src/rstctl/rstctl_rebootreset_stat.rs
@@ -0,0 +1,51 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RSTCTL_REBOOTRESET_STAT {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct REBOOTR {
+    bits: bool,
+}
+impl REBOOTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Indicates if Reboot reset was caused by the SYSCTL module."]
+    #[inline]
+    pub fn reboot(&self) -> REBOOTR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        REBOOTR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/rstctl/rstctl_reset_req.rs b/example-source/msp432p401r/src/rstctl/rstctl_reset_req.rs
new file mode 100644
index 0000000..82a4a16
--- /dev/null
+++ b/example-source/msp432p401r/src/rstctl/rstctl_reset_req.rs
@@ -0,0 +1,140 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::RSTCTL_RESET_REQ {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SOFT_REQW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SOFT_REQW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _HARD_REQW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _HARD_REQW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RSTKEYW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RSTKEYW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Soft Reset request"]
+    #[inline]
+    pub fn soft_req(&mut self) -> _SOFT_REQW {
+        _SOFT_REQW { w: self }
+    }
+    #[doc = "Bit 1 - Hard Reset request"]
+    #[inline]
+    pub fn hard_req(&mut self) -> _HARD_REQW {
+        _HARD_REQW { w: self }
+    }
+    #[doc = "Bits 8:15 - Write key to unlock reset request bits"]
+    #[inline]
+    pub fn rstkey(&mut self) -> _RSTKEYW {
+        _RSTKEYW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/rstctl/rstctl_softreset_clr.rs b/example-source/msp432p401r/src/rstctl/rstctl_softreset_clr.rs
new file mode 100644
index 0000000..bac940d
--- /dev/null
+++ b/example-source/msp432p401r/src/rstctl/rstctl_softreset_clr.rs
@@ -0,0 +1,512 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::RSTCTL_SOFTRESET_CLR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC0W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC1W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC2W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC3W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC4W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC4W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC5W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC5W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC6W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC6W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC7W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC7W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC8W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC8W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC9W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC9W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC10W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC10W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC11W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC11W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC12W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC12W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC13W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC13W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC14W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC14W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC15W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC15W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT"]
+    #[inline]
+    pub fn src0(&mut self) -> _SRC0W {
+        _SRC0W { w: self }
+    }
+    #[doc = "Bit 1 - Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT"]
+    #[inline]
+    pub fn src1(&mut self) -> _SRC1W {
+        _SRC1W { w: self }
+    }
+    #[doc = "Bit 2 - Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT"]
+    #[inline]
+    pub fn src2(&mut self) -> _SRC2W {
+        _SRC2W { w: self }
+    }
+    #[doc = "Bit 3 - Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT"]
+    #[inline]
+    pub fn src3(&mut self) -> _SRC3W {
+        _SRC3W { w: self }
+    }
+    #[doc = "Bit 4 - Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT"]
+    #[inline]
+    pub fn src4(&mut self) -> _SRC4W {
+        _SRC4W { w: self }
+    }
+    #[doc = "Bit 5 - Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT"]
+    #[inline]
+    pub fn src5(&mut self) -> _SRC5W {
+        _SRC5W { w: self }
+    }
+    #[doc = "Bit 6 - Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT"]
+    #[inline]
+    pub fn src6(&mut self) -> _SRC6W {
+        _SRC6W { w: self }
+    }
+    #[doc = "Bit 7 - Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT"]
+    #[inline]
+    pub fn src7(&mut self) -> _SRC7W {
+        _SRC7W { w: self }
+    }
+    #[doc = "Bit 8 - Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT"]
+    #[inline]
+    pub fn src8(&mut self) -> _SRC8W {
+        _SRC8W { w: self }
+    }
+    #[doc = "Bit 9 - Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT"]
+    #[inline]
+    pub fn src9(&mut self) -> _SRC9W {
+        _SRC9W { w: self }
+    }
+    #[doc = "Bit 10 - Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT"]
+    #[inline]
+    pub fn src10(&mut self) -> _SRC10W {
+        _SRC10W { w: self }
+    }
+    #[doc = "Bit 11 - Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT"]
+    #[inline]
+    pub fn src11(&mut self) -> _SRC11W {
+        _SRC11W { w: self }
+    }
+    #[doc = "Bit 12 - Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT"]
+    #[inline]
+    pub fn src12(&mut self) -> _SRC12W {
+        _SRC12W { w: self }
+    }
+    #[doc = "Bit 13 - Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT"]
+    #[inline]
+    pub fn src13(&mut self) -> _SRC13W {
+        _SRC13W { w: self }
+    }
+    #[doc = "Bit 14 - Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT"]
+    #[inline]
+    pub fn src14(&mut self) -> _SRC14W {
+        _SRC14W { w: self }
+    }
+    #[doc = "Bit 15 - Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT"]
+    #[inline]
+    pub fn src15(&mut self) -> _SRC15W {
+        _SRC15W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/rstctl/rstctl_softreset_set.rs b/example-source/msp432p401r/src/rstctl/rstctl_softreset_set.rs
new file mode 100644
index 0000000..52a2cf8
--- /dev/null
+++ b/example-source/msp432p401r/src/rstctl/rstctl_softreset_set.rs
@@ -0,0 +1,512 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::RSTCTL_SOFTRESET_SET {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC0W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC1W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC2W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC3W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC4W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC4W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC5W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC5W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC6W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC6W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC7W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC7W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC8W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC8W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC9W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC9W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC10W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC10W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC11W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC11W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC12W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC12W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC13W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC13W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC14W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC14W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRC15W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRC15W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)"]
+    #[inline]
+    pub fn src0(&mut self) -> _SRC0W {
+        _SRC0W { w: self }
+    }
+    #[doc = "Bit 1 - Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)"]
+    #[inline]
+    pub fn src1(&mut self) -> _SRC1W {
+        _SRC1W { w: self }
+    }
+    #[doc = "Bit 2 - Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)"]
+    #[inline]
+    pub fn src2(&mut self) -> _SRC2W {
+        _SRC2W { w: self }
+    }
+    #[doc = "Bit 3 - Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)"]
+    #[inline]
+    pub fn src3(&mut self) -> _SRC3W {
+        _SRC3W { w: self }
+    }
+    #[doc = "Bit 4 - Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)"]
+    #[inline]
+    pub fn src4(&mut self) -> _SRC4W {
+        _SRC4W { w: self }
+    }
+    #[doc = "Bit 5 - Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)"]
+    #[inline]
+    pub fn src5(&mut self) -> _SRC5W {
+        _SRC5W { w: self }
+    }
+    #[doc = "Bit 6 - Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)"]
+    #[inline]
+    pub fn src6(&mut self) -> _SRC6W {
+        _SRC6W { w: self }
+    }
+    #[doc = "Bit 7 - Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)"]
+    #[inline]
+    pub fn src7(&mut self) -> _SRC7W {
+        _SRC7W { w: self }
+    }
+    #[doc = "Bit 8 - Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)"]
+    #[inline]
+    pub fn src8(&mut self) -> _SRC8W {
+        _SRC8W { w: self }
+    }
+    #[doc = "Bit 9 - Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)"]
+    #[inline]
+    pub fn src9(&mut self) -> _SRC9W {
+        _SRC9W { w: self }
+    }
+    #[doc = "Bit 10 - Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)"]
+    #[inline]
+    pub fn src10(&mut self) -> _SRC10W {
+        _SRC10W { w: self }
+    }
+    #[doc = "Bit 11 - Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)"]
+    #[inline]
+    pub fn src11(&mut self) -> _SRC11W {
+        _SRC11W { w: self }
+    }
+    #[doc = "Bit 12 - Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)"]
+    #[inline]
+    pub fn src12(&mut self) -> _SRC12W {
+        _SRC12W { w: self }
+    }
+    #[doc = "Bit 13 - Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)"]
+    #[inline]
+    pub fn src13(&mut self) -> _SRC13W {
+        _SRC13W { w: self }
+    }
+    #[doc = "Bit 14 - Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)"]
+    #[inline]
+    pub fn src14(&mut self) -> _SRC14W {
+        _SRC14W { w: self }
+    }
+    #[doc = "Bit 15 - Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)"]
+    #[inline]
+    pub fn src15(&mut self) -> _SRC15W {
+        _SRC15W { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/rstctl/rstctl_softreset_stat.rs b/example-source/msp432p401r/src/rstctl/rstctl_softreset_stat.rs
new file mode 100644
index 0000000..c0ef832
--- /dev/null
+++ b/example-source/msp432p401r/src/rstctl/rstctl_softreset_stat.rs
@@ -0,0 +1,516 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RSTCTL_SOFTRESET_STAT {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC0R {
+    bits: bool,
+}
+impl SRC0R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC1R {
+    bits: bool,
+}
+impl SRC1R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC2R {
+    bits: bool,
+}
+impl SRC2R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC3R {
+    bits: bool,
+}
+impl SRC3R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC4R {
+    bits: bool,
+}
+impl SRC4R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC5R {
+    bits: bool,
+}
+impl SRC5R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC6R {
+    bits: bool,
+}
+impl SRC6R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC7R {
+    bits: bool,
+}
+impl SRC7R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC8R {
+    bits: bool,
+}
+impl SRC8R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC9R {
+    bits: bool,
+}
+impl SRC9R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC10R {
+    bits: bool,
+}
+impl SRC10R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC11R {
+    bits: bool,
+}
+impl SRC11R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC12R {
+    bits: bool,
+}
+impl SRC12R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC13R {
+    bits: bool,
+}
+impl SRC13R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC14R {
+    bits: bool,
+}
+impl SRC14R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SRC15R {
+    bits: bool,
+}
+impl SRC15R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - If 1, indicates that SRC0 was the source of the Soft Reset"]
+    #[inline]
+    pub fn src0(&self) -> SRC0R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC0R { bits }
+    }
+    #[doc = "Bit 1 - If 1, indicates that SRC1 was the source of the Soft Reset"]
+    #[inline]
+    pub fn src1(&self) -> SRC1R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC1R { bits }
+    }
+    #[doc = "Bit 2 - If 1, indicates that SRC2 was the source of the Soft Reset"]
+    #[inline]
+    pub fn src2(&self) -> SRC2R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC2R { bits }
+    }
+    #[doc = "Bit 3 - If 1, indicates that SRC3 was the source of the Soft Reset"]
+    #[inline]
+    pub fn src3(&self) -> SRC3R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC3R { bits }
+    }
+    #[doc = "Bit 4 - If 1, indicates that SRC4 was the source of the Soft Reset"]
+    #[inline]
+    pub fn src4(&self) -> SRC4R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC4R { bits }
+    }
+    #[doc = "Bit 5 - If 1, indicates that SRC5 was the source of the Soft Reset"]
+    #[inline]
+    pub fn src5(&self) -> SRC5R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC5R { bits }
+    }
+    #[doc = "Bit 6 - If 1, indicates that SRC6 was the source of the Soft Reset"]
+    #[inline]
+    pub fn src6(&self) -> SRC6R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC6R { bits }
+    }
+    #[doc = "Bit 7 - If 1, indicates that SRC7 was the source of the Soft Reset"]
+    #[inline]
+    pub fn src7(&self) -> SRC7R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC7R { bits }
+    }
+    #[doc = "Bit 8 - If 1, indicates that SRC8 was the source of the Soft Reset"]
+    #[inline]
+    pub fn src8(&self) -> SRC8R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC8R { bits }
+    }
+    #[doc = "Bit 9 - If 1, indicates that SRC9 was the source of the Soft Reset"]
+    #[inline]
+    pub fn src9(&self) -> SRC9R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC9R { bits }
+    }
+    #[doc = "Bit 10 - If 1, indicates that SRC10 was the source of the Soft Reset"]
+    #[inline]
+    pub fn src10(&self) -> SRC10R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC10R { bits }
+    }
+    #[doc = "Bit 11 - If 1, indicates that SRC11 was the source of the Soft Reset"]
+    #[inline]
+    pub fn src11(&self) -> SRC11R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC11R { bits }
+    }
+    #[doc = "Bit 12 - If 1, indicates that SRC12 was the source of the Soft Reset"]
+    #[inline]
+    pub fn src12(&self) -> SRC12R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC12R { bits }
+    }
+    #[doc = "Bit 13 - If 1, indicates that SRC13 was the source of the Soft Reset"]
+    #[inline]
+    pub fn src13(&self) -> SRC13R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC13R { bits }
+    }
+    #[doc = "Bit 14 - If 1, indicates that SRC14 was the source of the Soft Reset"]
+    #[inline]
+    pub fn src14(&self) -> SRC14R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC14R { bits }
+    }
+    #[doc = "Bit 15 - If 1, indicates that SRC15 was the source of the Soft Reset"]
+    #[inline]
+    pub fn src15(&self) -> SRC15R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SRC15R { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/rtc_c.rs b/example-source/msp432p401r/src/rtc_c.rs
new file mode 100644
index 0000000..5cce619
--- /dev/null
+++ b/example-source/msp432p401r/src/rtc_c.rs
@@ -0,0 +1,132 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - RTCCTL0 Register"]
+    pub rtcctl0: RTCCTL0,
+    #[doc = "0x02 - RTCCTL13 Register"]
+    pub rtcctl13: RTCCTL13,
+    #[doc = "0x04 - RTCOCAL Register"]
+    pub rtcocal: RTCOCAL,
+    #[doc = "0x06 - RTCTCMP Register"]
+    pub rtctcmp: RTCTCMP,
+    #[doc = "0x08 - Real-Time Clock Prescale Timer 0 Control Register"]
+    pub rtcps0ctl: RTCPS0CTL,
+    #[doc = "0x0a - Real-Time Clock Prescale Timer 1 Control Register"]
+    pub rtcps1ctl: RTCPS1CTL,
+    #[doc = "0x0c - Real-Time Clock Prescale Timer Counter Register"]
+    pub rtcps: RTCPS,
+    #[doc = "0x0e - Real-Time Clock Interrupt Vector Register"]
+    pub rtciv: RTCIV,
+    #[doc = "0x10 - RTCTIM0 Register Hexadecimal Format"]
+    pub rtctim0: RTCTIM0,
+    #[doc = "0x12 - Real-Time Clock Hour, Day of Week"]
+    pub rtctim1: RTCTIM1,
+    #[doc = "0x14 - RTCDATE - Hexadecimal Format"]
+    pub rtcdate: RTCDATE,
+    #[doc = "0x16 - RTCYEAR Register Hexadecimal Format"]
+    pub rtcyear: RTCYEAR,
+    #[doc = "0x18 - RTCMINHR - Hexadecimal Format"]
+    pub rtcaminhr: RTCAMINHR,
+    #[doc = "0x1a - RTCADOWDAY - Hexadecimal Format"]
+    pub rtcadowday: RTCADOWDAY,
+    #[doc = "0x1c - Binary-to-BCD Conversion Register"]
+    pub rtcbin2bcd: RTCBIN2BCD,
+    #[doc = "0x1e - BCD-to-Binary Conversion Register"]
+    pub rtcbcd2bin: RTCBCD2BIN,
+}
+#[doc = "RTCCTL0 Register"]
+pub struct RTCCTL0 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "RTCCTL0 Register"]
+pub mod rtcctl0;
+#[doc = "RTCCTL13 Register"]
+pub struct RTCCTL13 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "RTCCTL13 Register"]
+pub mod rtcctl13;
+#[doc = "RTCOCAL Register"]
+pub struct RTCOCAL {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "RTCOCAL Register"]
+pub mod rtcocal;
+#[doc = "RTCTCMP Register"]
+pub struct RTCTCMP {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "RTCTCMP Register"]
+pub mod rtctcmp;
+#[doc = "Real-Time Clock Prescale Timer 0 Control Register"]
+pub struct RTCPS0CTL {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Real-Time Clock Prescale Timer 0 Control Register"]
+pub mod rtcps0ctl;
+#[doc = "Real-Time Clock Prescale Timer 1 Control Register"]
+pub struct RTCPS1CTL {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Real-Time Clock Prescale Timer 1 Control Register"]
+pub mod rtcps1ctl;
+#[doc = "Real-Time Clock Prescale Timer Counter Register"]
+pub struct RTCPS {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Real-Time Clock Prescale Timer Counter Register"]
+pub mod rtcps;
+#[doc = "Real-Time Clock Interrupt Vector Register"]
+pub struct RTCIV {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Real-Time Clock Interrupt Vector Register"]
+pub mod rtciv;
+#[doc = "RTCTIM0 Register Hexadecimal Format"]
+pub struct RTCTIM0 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "RTCTIM0 Register Hexadecimal Format"]
+pub mod rtctim0;
+#[doc = "Real-Time Clock Hour, Day of Week"]
+pub struct RTCTIM1 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Real-Time Clock Hour, Day of Week"]
+pub mod rtctim1;
+#[doc = "RTCDATE - Hexadecimal Format"]
+pub struct RTCDATE {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "RTCDATE - Hexadecimal Format"]
+pub mod rtcdate;
+#[doc = "RTCYEAR Register Hexadecimal Format"]
+pub struct RTCYEAR {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "RTCYEAR Register Hexadecimal Format"]
+pub mod rtcyear;
+#[doc = "RTCMINHR - Hexadecimal Format"]
+pub struct RTCAMINHR {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "RTCMINHR - Hexadecimal Format"]
+pub mod rtcaminhr;
+#[doc = "RTCADOWDAY - Hexadecimal Format"]
+pub struct RTCADOWDAY {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "RTCADOWDAY - Hexadecimal Format"]
+pub mod rtcadowday;
+#[doc = "Binary-to-BCD Conversion Register"]
+pub struct RTCBIN2BCD {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Binary-to-BCD Conversion Register"]
+pub mod rtcbin2bcd;
+#[doc = "BCD-to-Binary Conversion Register"]
+pub struct RTCBCD2BIN {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "BCD-to-Binary Conversion Register"]
+pub mod rtcbcd2bin;
diff --git a/example-source/msp432p401r/src/rtc_c/rtcadowday.rs b/example-source/msp432p401r/src/rtc_c/rtcadowday.rs
new file mode 100644
index 0000000..7fe61f2
--- /dev/null
+++ b/example-source/msp432p401r/src/rtc_c/rtcadowday.rs
@@ -0,0 +1,264 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::RTCADOWDAY {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DAYOFWEEKR {
+    bits: u8,
+}
+impl DAYOFWEEKR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DOWAER {
+    bits: bool,
+}
+impl DOWAER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DAYOFMONTHR {
+    bits: u8,
+}
+impl DAYOFMONTHR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DAYAER {
+    bits: bool,
+}
+impl DAYAER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DAYOFWEEKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DAYOFWEEKW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DOWAEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DOWAEW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DAYOFMONTHW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DAYOFMONTHW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 31;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DAYAEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DAYAEW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:2 - Day of week (0 to 6)"]
+    #[inline]
+    pub fn dayof_week(&self) -> DAYOFWEEKR {
+        let bits = {
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        DAYOFWEEKR { bits }
+    }
+    #[doc = "Bit 7 - Alarm enable"]
+    #[inline]
+    pub fn dowae(&self) -> DOWAER {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        };
+        DOWAER { bits }
+    }
+    #[doc = "Bits 8:12 - Day of month (1 to 28, 29, 30, 31)"]
+    #[inline]
+    pub fn dayof_month(&self) -> DAYOFMONTHR {
+        let bits = {
+            const MASK: u8 = 31;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        DAYOFMONTHR { bits }
+    }
+    #[doc = "Bit 15 - Alarm enable"]
+    #[inline]
+    pub fn dayae(&self) -> DAYAER {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        };
+        DAYAER { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:2 - Day of week (0 to 6)"]
+    #[inline]
+    pub fn dayof_week(&mut self) -> _DAYOFWEEKW {
+        _DAYOFWEEKW { w: self }
+    }
+    #[doc = "Bit 7 - Alarm enable"]
+    #[inline]
+    pub fn dowae(&mut self) -> _DOWAEW {
+        _DOWAEW { w: self }
+    }
+    #[doc = "Bits 8:12 - Day of month (1 to 28, 29, 30, 31)"]
+    #[inline]
+    pub fn dayof_month(&mut self) -> _DAYOFMONTHW {
+        _DAYOFMONTHW { w: self }
+    }
+    #[doc = "Bit 15 - Alarm enable"]
+    #[inline]
+    pub fn dayae(&mut self) -> _DAYAEW {
+        _DAYAEW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/rtc_c/rtcaminhr.rs b/example-source/msp432p401r/src/rtc_c/rtcaminhr.rs
new file mode 100644
index 0000000..4584d4a
--- /dev/null
+++ b/example-source/msp432p401r/src/rtc_c/rtcaminhr.rs
@@ -0,0 +1,264 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::RTCAMINHR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct MINUTESR {
+    bits: u8,
+}
+impl MINUTESR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct MINAER {
+    bits: bool,
+}
+impl MINAER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct HOURSR {
+    bits: u8,
+}
+impl HOURSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct HOURAER {
+    bits: bool,
+}
+impl HOURAER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MINUTESW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MINUTESW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 63;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MINAEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MINAEW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _HOURSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _HOURSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 31;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _HOURAEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _HOURAEW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:5 - Minutes (0 to 59)"]
+    #[inline]
+    pub fn minutes(&self) -> MINUTESR {
+        let bits = {
+            const MASK: u8 = 63;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        MINUTESR { bits }
+    }
+    #[doc = "Bit 7 - Alarm enable"]
+    #[inline]
+    pub fn minae(&self) -> MINAER {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        };
+        MINAER { bits }
+    }
+    #[doc = "Bits 8:12 - Hours (0 to 23)"]
+    #[inline]
+    pub fn hours(&self) -> HOURSR {
+        let bits = {
+            const MASK: u8 = 31;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        HOURSR { bits }
+    }
+    #[doc = "Bit 15 - Alarm enable"]
+    #[inline]
+    pub fn hourae(&self) -> HOURAER {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        };
+        HOURAER { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:5 - Minutes (0 to 59)"]
+    #[inline]
+    pub fn minutes(&mut self) -> _MINUTESW {
+        _MINUTESW { w: self }
+    }
+    #[doc = "Bit 7 - Alarm enable"]
+    #[inline]
+    pub fn minae(&mut self) -> _MINAEW {
+        _MINAEW { w: self }
+    }
+    #[doc = "Bits 8:12 - Hours (0 to 23)"]
+    #[inline]
+    pub fn hours(&mut self) -> _HOURSW {
+        _HOURSW { w: self }
+    }
+    #[doc = "Bit 15 - Alarm enable"]
+    #[inline]
+    pub fn hourae(&mut self) -> _HOURAEW {
+        _HOURAEW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/rtc_c/rtcbcd2bin.rs b/example-source/msp432p401r/src/rtc_c/rtcbcd2bin.rs
new file mode 100644
index 0000000..9e2a19a
--- /dev/null
+++ b/example-source/msp432p401r/src/rtc_c/rtcbcd2bin.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::RTCBCD2BIN {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct BCD2BINR {
+    bits: u16,
+}
+impl BCD2BINR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _BCD2BINW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _BCD2BINW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - bcd to bin conversion"]
+    #[inline]
+    pub fn bcd2bin(&self) -> BCD2BINR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        BCD2BINR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - bcd to bin conversion"]
+    #[inline]
+    pub fn bcd2bin(&mut self) -> _BCD2BINW {
+        _BCD2BINW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/rtc_c/rtcbin2bcd.rs b/example-source/msp432p401r/src/rtc_c/rtcbin2bcd.rs
new file mode 100644
index 0000000..4c16b2d
--- /dev/null
+++ b/example-source/msp432p401r/src/rtc_c/rtcbin2bcd.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::RTCBIN2BCD {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct BIN2BCDR {
+    bits: u16,
+}
+impl BIN2BCDR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _BIN2BCDW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _BIN2BCDW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - bin to bcd conversion"]
+    #[inline]
+    pub fn bin2bcd(&self) -> BIN2BCDR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        BIN2BCDR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - bin to bcd conversion"]
+    #[inline]
+    pub fn bin2bcd(&mut self) -> _BIN2BCDW {
+        _BIN2BCDW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/rtc_c/rtcctl0.rs b/example-source/msp432p401r/src/rtc_c/rtcctl0.rs
new file mode 100644
index 0000000..1041b30
--- /dev/null
+++ b/example-source/msp432p401r/src/rtc_c/rtcctl0.rs
@@ -0,0 +1,1057 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::RTCCTL0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `RTCRDYIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RTCRDYIFGR {
+    #[doc = "RTC cannot be read safely"]
+    RTCRDYIFG_0,
+    #[doc = "RTC can be read safely"]
+    RTCRDYIFG_1,
+}
+impl RTCRDYIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            RTCRDYIFGR::RTCRDYIFG_0 => false,
+            RTCRDYIFGR::RTCRDYIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> RTCRDYIFGR {
+        match value {
+            false => RTCRDYIFGR::RTCRDYIFG_0,
+            true => RTCRDYIFGR::RTCRDYIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RTCRDYIFG_0`"]
+    #[inline]
+    pub fn is_rtcrdyifg_0(&self) -> bool {
+        *self == RTCRDYIFGR::RTCRDYIFG_0
+    }
+    #[doc = "Checks if the value of the field is `RTCRDYIFG_1`"]
+    #[inline]
+    pub fn is_rtcrdyifg_1(&self) -> bool {
+        *self == RTCRDYIFGR::RTCRDYIFG_1
+    }
+}
+#[doc = "Possible values of the field `RTCAIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RTCAIFGR {
+    #[doc = "No time event occurred"]
+    RTCAIFG_0,
+    #[doc = "Time event occurred"]
+    RTCAIFG_1,
+}
+impl RTCAIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            RTCAIFGR::RTCAIFG_0 => false,
+            RTCAIFGR::RTCAIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> RTCAIFGR {
+        match value {
+            false => RTCAIFGR::RTCAIFG_0,
+            true => RTCAIFGR::RTCAIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RTCAIFG_0`"]
+    #[inline]
+    pub fn is_rtcaifg_0(&self) -> bool {
+        *self == RTCAIFGR::RTCAIFG_0
+    }
+    #[doc = "Checks if the value of the field is `RTCAIFG_1`"]
+    #[inline]
+    pub fn is_rtcaifg_1(&self) -> bool {
+        *self == RTCAIFGR::RTCAIFG_1
+    }
+}
+#[doc = "Possible values of the field `RTCTEVIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RTCTEVIFGR {
+    #[doc = "No time event occurred"]
+    RTCTEVIFG_0,
+    #[doc = "Time event occurred"]
+    RTCTEVIFG_1,
+}
+impl RTCTEVIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            RTCTEVIFGR::RTCTEVIFG_0 => false,
+            RTCTEVIFGR::RTCTEVIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> RTCTEVIFGR {
+        match value {
+            false => RTCTEVIFGR::RTCTEVIFG_0,
+            true => RTCTEVIFGR::RTCTEVIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RTCTEVIFG_0`"]
+    #[inline]
+    pub fn is_rtctevifg_0(&self) -> bool {
+        *self == RTCTEVIFGR::RTCTEVIFG_0
+    }
+    #[doc = "Checks if the value of the field is `RTCTEVIFG_1`"]
+    #[inline]
+    pub fn is_rtctevifg_1(&self) -> bool {
+        *self == RTCTEVIFGR::RTCTEVIFG_1
+    }
+}
+#[doc = "Possible values of the field `RTCOFIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RTCOFIFGR {
+    #[doc = "No interrupt pending"]
+    RTCOFIFG_0,
+    #[doc = "Interrupt pending. A 32-kHz crystal oscillator fault occurred after last reset."]
+    RTCOFIFG_1,
+}
+impl RTCOFIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            RTCOFIFGR::RTCOFIFG_0 => false,
+            RTCOFIFGR::RTCOFIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> RTCOFIFGR {
+        match value {
+            false => RTCOFIFGR::RTCOFIFG_0,
+            true => RTCOFIFGR::RTCOFIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RTCOFIFG_0`"]
+    #[inline]
+    pub fn is_rtcofifg_0(&self) -> bool {
+        *self == RTCOFIFGR::RTCOFIFG_0
+    }
+    #[doc = "Checks if the value of the field is `RTCOFIFG_1`"]
+    #[inline]
+    pub fn is_rtcofifg_1(&self) -> bool {
+        *self == RTCOFIFGR::RTCOFIFG_1
+    }
+}
+#[doc = "Possible values of the field `RTCRDYIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RTCRDYIER {
+    #[doc = "Interrupt not enabled"]
+    RTCRDYIE_0,
+    #[doc = "Interrupt enabled"]
+    RTCRDYIE_1,
+}
+impl RTCRDYIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            RTCRDYIER::RTCRDYIE_0 => false,
+            RTCRDYIER::RTCRDYIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> RTCRDYIER {
+        match value {
+            false => RTCRDYIER::RTCRDYIE_0,
+            true => RTCRDYIER::RTCRDYIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RTCRDYIE_0`"]
+    #[inline]
+    pub fn is_rtcrdyie_0(&self) -> bool {
+        *self == RTCRDYIER::RTCRDYIE_0
+    }
+    #[doc = "Checks if the value of the field is `RTCRDYIE_1`"]
+    #[inline]
+    pub fn is_rtcrdyie_1(&self) -> bool {
+        *self == RTCRDYIER::RTCRDYIE_1
+    }
+}
+#[doc = "Possible values of the field `RTCAIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RTCAIER {
+    #[doc = "Interrupt not enabled"]
+    RTCAIE_0,
+    #[doc = "Interrupt enabled (LPM3/LPM3.5 wake-up enabled)"]
+    RTCAIE_1,
+}
+impl RTCAIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            RTCAIER::RTCAIE_0 => false,
+            RTCAIER::RTCAIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> RTCAIER {
+        match value {
+            false => RTCAIER::RTCAIE_0,
+            true => RTCAIER::RTCAIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RTCAIE_0`"]
+    #[inline]
+    pub fn is_rtcaie_0(&self) -> bool {
+        *self == RTCAIER::RTCAIE_0
+    }
+    #[doc = "Checks if the value of the field is `RTCAIE_1`"]
+    #[inline]
+    pub fn is_rtcaie_1(&self) -> bool {
+        *self == RTCAIER::RTCAIE_1
+    }
+}
+#[doc = "Possible values of the field `RTCTEVIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RTCTEVIER {
+    #[doc = "Interrupt not enabled"]
+    RTCTEVIE_0,
+    #[doc = "Interrupt enabled (LPM3/LPM3.5 wake-up enabled)"]
+    RTCTEVIE_1,
+}
+impl RTCTEVIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            RTCTEVIER::RTCTEVIE_0 => false,
+            RTCTEVIER::RTCTEVIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> RTCTEVIER {
+        match value {
+            false => RTCTEVIER::RTCTEVIE_0,
+            true => RTCTEVIER::RTCTEVIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RTCTEVIE_0`"]
+    #[inline]
+    pub fn is_rtctevie_0(&self) -> bool {
+        *self == RTCTEVIER::RTCTEVIE_0
+    }
+    #[doc = "Checks if the value of the field is `RTCTEVIE_1`"]
+    #[inline]
+    pub fn is_rtctevie_1(&self) -> bool {
+        *self == RTCTEVIER::RTCTEVIE_1
+    }
+}
+#[doc = "Possible values of the field `RTCOFIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RTCOFIER {
+    #[doc = "Interrupt not enabled"]
+    RTCOFIE_0,
+    #[doc = "Interrupt enabled (LPM3/LPM3.5 wake-up enabled)"]
+    RTCOFIE_1,
+}
+impl RTCOFIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            RTCOFIER::RTCOFIE_0 => false,
+            RTCOFIER::RTCOFIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> RTCOFIER {
+        match value {
+            false => RTCOFIER::RTCOFIE_0,
+            true => RTCOFIER::RTCOFIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RTCOFIE_0`"]
+    #[inline]
+    pub fn is_rtcofie_0(&self) -> bool {
+        *self == RTCOFIER::RTCOFIE_0
+    }
+    #[doc = "Checks if the value of the field is `RTCOFIE_1`"]
+    #[inline]
+    pub fn is_rtcofie_1(&self) -> bool {
+        *self == RTCOFIER::RTCOFIE_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct RTCKEYR {
+    bits: u8,
+}
+impl RTCKEYR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Values that can be written to the field `RTCRDYIFG`"]
+pub enum RTCRDYIFGW {
+    #[doc = "RTC cannot be read safely"]
+    RTCRDYIFG_0,
+    #[doc = "RTC can be read safely"]
+    RTCRDYIFG_1,
+}
+impl RTCRDYIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            RTCRDYIFGW::RTCRDYIFG_0 => false,
+            RTCRDYIFGW::RTCRDYIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RTCRDYIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RTCRDYIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: RTCRDYIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "RTC cannot be read safely"]
+    #[inline]
+    pub fn rtcrdyifg_0(self) -> &'a mut W {
+        self.variant(RTCRDYIFGW::RTCRDYIFG_0)
+    }
+    #[doc = "RTC can be read safely"]
+    #[inline]
+    pub fn rtcrdyifg_1(self) -> &'a mut W {
+        self.variant(RTCRDYIFGW::RTCRDYIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `RTCAIFG`"]
+pub enum RTCAIFGW {
+    #[doc = "No time event occurred"]
+    RTCAIFG_0,
+    #[doc = "Time event occurred"]
+    RTCAIFG_1,
+}
+impl RTCAIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            RTCAIFGW::RTCAIFG_0 => false,
+            RTCAIFGW::RTCAIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RTCAIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RTCAIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: RTCAIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No time event occurred"]
+    #[inline]
+    pub fn rtcaifg_0(self) -> &'a mut W {
+        self.variant(RTCAIFGW::RTCAIFG_0)
+    }
+    #[doc = "Time event occurred"]
+    #[inline]
+    pub fn rtcaifg_1(self) -> &'a mut W {
+        self.variant(RTCAIFGW::RTCAIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `RTCTEVIFG`"]
+pub enum RTCTEVIFGW {
+    #[doc = "No time event occurred"]
+    RTCTEVIFG_0,
+    #[doc = "Time event occurred"]
+    RTCTEVIFG_1,
+}
+impl RTCTEVIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            RTCTEVIFGW::RTCTEVIFG_0 => false,
+            RTCTEVIFGW::RTCTEVIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RTCTEVIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RTCTEVIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: RTCTEVIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No time event occurred"]
+    #[inline]
+    pub fn rtctevifg_0(self) -> &'a mut W {
+        self.variant(RTCTEVIFGW::RTCTEVIFG_0)
+    }
+    #[doc = "Time event occurred"]
+    #[inline]
+    pub fn rtctevifg_1(self) -> &'a mut W {
+        self.variant(RTCTEVIFGW::RTCTEVIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `RTCOFIFG`"]
+pub enum RTCOFIFGW {
+    #[doc = "No interrupt pending"]
+    RTCOFIFG_0,
+    #[doc = "Interrupt pending. A 32-kHz crystal oscillator fault occurred after last reset."]
+    RTCOFIFG_1,
+}
+impl RTCOFIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            RTCOFIFGW::RTCOFIFG_0 => false,
+            RTCOFIFGW::RTCOFIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RTCOFIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RTCOFIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: RTCOFIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn rtcofifg_0(self) -> &'a mut W {
+        self.variant(RTCOFIFGW::RTCOFIFG_0)
+    }
+    #[doc = "Interrupt pending. A 32-kHz crystal oscillator fault occurred after last reset."]
+    #[inline]
+    pub fn rtcofifg_1(self) -> &'a mut W {
+        self.variant(RTCOFIFGW::RTCOFIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `RTCRDYIE`"]
+pub enum RTCRDYIEW {
+    #[doc = "Interrupt not enabled"]
+    RTCRDYIE_0,
+    #[doc = "Interrupt enabled"]
+    RTCRDYIE_1,
+}
+impl RTCRDYIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            RTCRDYIEW::RTCRDYIE_0 => false,
+            RTCRDYIEW::RTCRDYIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RTCRDYIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RTCRDYIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: RTCRDYIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt not enabled"]
+    #[inline]
+    pub fn rtcrdyie_0(self) -> &'a mut W {
+        self.variant(RTCRDYIEW::RTCRDYIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn rtcrdyie_1(self) -> &'a mut W {
+        self.variant(RTCRDYIEW::RTCRDYIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `RTCAIE`"]
+pub enum RTCAIEW {
+    #[doc = "Interrupt not enabled"]
+    RTCAIE_0,
+    #[doc = "Interrupt enabled (LPM3/LPM3.5 wake-up enabled)"]
+    RTCAIE_1,
+}
+impl RTCAIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            RTCAIEW::RTCAIE_0 => false,
+            RTCAIEW::RTCAIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RTCAIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RTCAIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: RTCAIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt not enabled"]
+    #[inline]
+    pub fn rtcaie_0(self) -> &'a mut W {
+        self.variant(RTCAIEW::RTCAIE_0)
+    }
+    #[doc = "Interrupt enabled (LPM3/LPM3.5 wake-up enabled)"]
+    #[inline]
+    pub fn rtcaie_1(self) -> &'a mut W {
+        self.variant(RTCAIEW::RTCAIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `RTCTEVIE`"]
+pub enum RTCTEVIEW {
+    #[doc = "Interrupt not enabled"]
+    RTCTEVIE_0,
+    #[doc = "Interrupt enabled (LPM3/LPM3.5 wake-up enabled)"]
+    RTCTEVIE_1,
+}
+impl RTCTEVIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            RTCTEVIEW::RTCTEVIE_0 => false,
+            RTCTEVIEW::RTCTEVIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RTCTEVIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RTCTEVIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: RTCTEVIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt not enabled"]
+    #[inline]
+    pub fn rtctevie_0(self) -> &'a mut W {
+        self.variant(RTCTEVIEW::RTCTEVIE_0)
+    }
+    #[doc = "Interrupt enabled (LPM3/LPM3.5 wake-up enabled)"]
+    #[inline]
+    pub fn rtctevie_1(self) -> &'a mut W {
+        self.variant(RTCTEVIEW::RTCTEVIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `RTCOFIE`"]
+pub enum RTCOFIEW {
+    #[doc = "Interrupt not enabled"]
+    RTCOFIE_0,
+    #[doc = "Interrupt enabled (LPM3/LPM3.5 wake-up enabled)"]
+    RTCOFIE_1,
+}
+impl RTCOFIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            RTCOFIEW::RTCOFIE_0 => false,
+            RTCOFIEW::RTCOFIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RTCOFIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RTCOFIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: RTCOFIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt not enabled"]
+    #[inline]
+    pub fn rtcofie_0(self) -> &'a mut W {
+        self.variant(RTCOFIEW::RTCOFIE_0)
+    }
+    #[doc = "Interrupt enabled (LPM3/LPM3.5 wake-up enabled)"]
+    #[inline]
+    pub fn rtcofie_1(self) -> &'a mut W {
+        self.variant(RTCOFIEW::RTCOFIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RTCKEYW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RTCKEYW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Real-time clock ready interrupt flag"]
+    #[inline]
+    pub fn rtcrdyifg(&self) -> RTCRDYIFGR {
+        RTCRDYIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Real-time clock alarm interrupt flag"]
+    #[inline]
+    pub fn rtcaifg(&self) -> RTCAIFGR {
+        RTCAIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - Real-time clock time event interrupt flag"]
+    #[inline]
+    pub fn rtctevifg(&self) -> RTCTEVIFGR {
+        RTCTEVIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - 32-kHz crystal oscillator fault interrupt flag"]
+    #[inline]
+    pub fn rtcofifg(&self) -> RTCOFIFGR {
+        RTCOFIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 4 - Real-time clock ready interrupt enable"]
+    #[inline]
+    pub fn rtcrdyie(&self) -> RTCRDYIER {
+        RTCRDYIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5 - Real-time clock alarm interrupt enable"]
+    #[inline]
+    pub fn rtcaie(&self) -> RTCAIER {
+        RTCAIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 6 - Real-time clock time event interrupt enable"]
+    #[inline]
+    pub fn rtctevie(&self) -> RTCTEVIER {
+        RTCTEVIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 7 - 32-kHz crystal oscillator fault interrupt enable"]
+    #[inline]
+    pub fn rtcofie(&self) -> RTCOFIER {
+        RTCOFIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 8:15 - Real-time clock key"]
+    #[inline]
+    pub fn rtckey(&self) -> RTCKEYR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        RTCKEYR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 38408 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Real-time clock ready interrupt flag"]
+    #[inline]
+    pub fn rtcrdyifg(&mut self) -> _RTCRDYIFGW {
+        _RTCRDYIFGW { w: self }
+    }
+    #[doc = "Bit 1 - Real-time clock alarm interrupt flag"]
+    #[inline]
+    pub fn rtcaifg(&mut self) -> _RTCAIFGW {
+        _RTCAIFGW { w: self }
+    }
+    #[doc = "Bit 2 - Real-time clock time event interrupt flag"]
+    #[inline]
+    pub fn rtctevifg(&mut self) -> _RTCTEVIFGW {
+        _RTCTEVIFGW { w: self }
+    }
+    #[doc = "Bit 3 - 32-kHz crystal oscillator fault interrupt flag"]
+    #[inline]
+    pub fn rtcofifg(&mut self) -> _RTCOFIFGW {
+        _RTCOFIFGW { w: self }
+    }
+    #[doc = "Bit 4 - Real-time clock ready interrupt enable"]
+    #[inline]
+    pub fn rtcrdyie(&mut self) -> _RTCRDYIEW {
+        _RTCRDYIEW { w: self }
+    }
+    #[doc = "Bit 5 - Real-time clock alarm interrupt enable"]
+    #[inline]
+    pub fn rtcaie(&mut self) -> _RTCAIEW {
+        _RTCAIEW { w: self }
+    }
+    #[doc = "Bit 6 - Real-time clock time event interrupt enable"]
+    #[inline]
+    pub fn rtctevie(&mut self) -> _RTCTEVIEW {
+        _RTCTEVIEW { w: self }
+    }
+    #[doc = "Bit 7 - 32-kHz crystal oscillator fault interrupt enable"]
+    #[inline]
+    pub fn rtcofie(&mut self) -> _RTCOFIEW {
+        _RTCOFIEW { w: self }
+    }
+    #[doc = "Bits 8:15 - Real-time clock key"]
+    #[inline]
+    pub fn rtckey(&mut self) -> _RTCKEYW {
+        _RTCKEYW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/rtc_c/rtcctl13.rs b/example-source/msp432p401r/src/rtc_c/rtcctl13.rs
new file mode 100644
index 0000000..6d01395
--- /dev/null
+++ b/example-source/msp432p401r/src/rtc_c/rtcctl13.rs
@@ -0,0 +1,767 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::RTCCTL13 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `RTCTEV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RTCTEVR {
+    #[doc = "Minute changed"]
+    RTCTEV_0,
+    #[doc = "Hour changed"]
+    RTCTEV_1,
+    #[doc = "Every day at midnight (00:00)"]
+    RTCTEV_2,
+    #[doc = "Every day at noon (12:00)"]
+    RTCTEV_3,
+}
+impl RTCTEVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            RTCTEVR::RTCTEV_0 => 0,
+            RTCTEVR::RTCTEV_1 => 1,
+            RTCTEVR::RTCTEV_2 => 2,
+            RTCTEVR::RTCTEV_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> RTCTEVR {
+        match value {
+            0 => RTCTEVR::RTCTEV_0,
+            1 => RTCTEVR::RTCTEV_1,
+            2 => RTCTEVR::RTCTEV_2,
+            3 => RTCTEVR::RTCTEV_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `RTCTEV_0`"]
+    #[inline]
+    pub fn is_rtctev_0(&self) -> bool {
+        *self == RTCTEVR::RTCTEV_0
+    }
+    #[doc = "Checks if the value of the field is `RTCTEV_1`"]
+    #[inline]
+    pub fn is_rtctev_1(&self) -> bool {
+        *self == RTCTEVR::RTCTEV_1
+    }
+    #[doc = "Checks if the value of the field is `RTCTEV_2`"]
+    #[inline]
+    pub fn is_rtctev_2(&self) -> bool {
+        *self == RTCTEVR::RTCTEV_2
+    }
+    #[doc = "Checks if the value of the field is `RTCTEV_3`"]
+    #[inline]
+    pub fn is_rtctev_3(&self) -> bool {
+        *self == RTCTEVR::RTCTEV_3
+    }
+}
+#[doc = "Possible values of the field `RTCSSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RTCSSELR {
+    #[doc = "BCLK"]
+    RTCSSEL_0,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl RTCSSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            RTCSSELR::RTCSSEL_0 => 0,
+            RTCSSELR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> RTCSSELR {
+        match value {
+            0 => RTCSSELR::RTCSSEL_0,
+            i => RTCSSELR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `RTCSSEL_0`"]
+    #[inline]
+    pub fn is_rtcssel_0(&self) -> bool {
+        *self == RTCSSELR::RTCSSEL_0
+    }
+}
+#[doc = "Possible values of the field `RTCRDY`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RTCRDYR {
+    #[doc = "RTC time values in transition"]
+    RTCRDY_0,
+    #[doc = "RTC time values safe for reading. This bit indicates when the real-time clock time values are safe for reading."]
+    RTCRDY_1,
+}
+impl RTCRDYR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            RTCRDYR::RTCRDY_0 => false,
+            RTCRDYR::RTCRDY_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> RTCRDYR {
+        match value {
+            false => RTCRDYR::RTCRDY_0,
+            true => RTCRDYR::RTCRDY_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RTCRDY_0`"]
+    #[inline]
+    pub fn is_rtcrdy_0(&self) -> bool {
+        *self == RTCRDYR::RTCRDY_0
+    }
+    #[doc = "Checks if the value of the field is `RTCRDY_1`"]
+    #[inline]
+    pub fn is_rtcrdy_1(&self) -> bool {
+        *self == RTCRDYR::RTCRDY_1
+    }
+}
+#[doc = "Possible values of the field `RTCMODE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RTCMODER {
+    #[doc = "Calendar mode. Always reads a value of 1."]
+    RTCMODE_1,
+    #[doc = r" Reserved"]
+    _Reserved(bool),
+}
+impl RTCMODER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            RTCMODER::RTCMODE_1 => true,
+            RTCMODER::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> RTCMODER {
+        match value {
+            true => RTCMODER::RTCMODE_1,
+            i => RTCMODER::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `RTCMODE_1`"]
+    #[inline]
+    pub fn is_rtcmode_1(&self) -> bool {
+        *self == RTCMODER::RTCMODE_1
+    }
+}
+#[doc = "Possible values of the field `RTCHOLD`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RTCHOLDR {
+    #[doc = "Real-time clock is operational"]
+    RTCHOLD_0,
+    #[doc = "When set, the calendar is stopped as well as the prescale counters, RT0PS and RT1PS are don't care"]
+    RTCHOLD_1,
+}
+impl RTCHOLDR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            RTCHOLDR::RTCHOLD_0 => false,
+            RTCHOLDR::RTCHOLD_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> RTCHOLDR {
+        match value {
+            false => RTCHOLDR::RTCHOLD_0,
+            true => RTCHOLDR::RTCHOLD_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RTCHOLD_0`"]
+    #[inline]
+    pub fn is_rtchold_0(&self) -> bool {
+        *self == RTCHOLDR::RTCHOLD_0
+    }
+    #[doc = "Checks if the value of the field is `RTCHOLD_1`"]
+    #[inline]
+    pub fn is_rtchold_1(&self) -> bool {
+        *self == RTCHOLDR::RTCHOLD_1
+    }
+}
+#[doc = "Possible values of the field `RTCBCD`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RTCBCDR {
+    #[doc = "Binary (hexadecimal) code selected"]
+    RTCBCD_0,
+    #[doc = "Binary coded decimal (BCD) code selected"]
+    RTCBCD_1,
+}
+impl RTCBCDR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            RTCBCDR::RTCBCD_0 => false,
+            RTCBCDR::RTCBCD_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> RTCBCDR {
+        match value {
+            false => RTCBCDR::RTCBCD_0,
+            true => RTCBCDR::RTCBCD_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RTCBCD_0`"]
+    #[inline]
+    pub fn is_rtcbcd_0(&self) -> bool {
+        *self == RTCBCDR::RTCBCD_0
+    }
+    #[doc = "Checks if the value of the field is `RTCBCD_1`"]
+    #[inline]
+    pub fn is_rtcbcd_1(&self) -> bool {
+        *self == RTCBCDR::RTCBCD_1
+    }
+}
+#[doc = "Possible values of the field `RTCCALF`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RTCCALFR {
+    #[doc = "No frequency output to RTCCLK pin"]
+    RTCCALF_0,
+    #[doc = "512 Hz"]
+    RTCCALF_1,
+    #[doc = "256 Hz"]
+    RTCCALF_2,
+    #[doc = "1 Hz"]
+    RTCCALF_3,
+}
+impl RTCCALFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            RTCCALFR::RTCCALF_0 => 0,
+            RTCCALFR::RTCCALF_1 => 1,
+            RTCCALFR::RTCCALF_2 => 2,
+            RTCCALFR::RTCCALF_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> RTCCALFR {
+        match value {
+            0 => RTCCALFR::RTCCALF_0,
+            1 => RTCCALFR::RTCCALF_1,
+            2 => RTCCALFR::RTCCALF_2,
+            3 => RTCCALFR::RTCCALF_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `RTCCALF_0`"]
+    #[inline]
+    pub fn is_rtccalf_0(&self) -> bool {
+        *self == RTCCALFR::RTCCALF_0
+    }
+    #[doc = "Checks if the value of the field is `RTCCALF_1`"]
+    #[inline]
+    pub fn is_rtccalf_1(&self) -> bool {
+        *self == RTCCALFR::RTCCALF_1
+    }
+    #[doc = "Checks if the value of the field is `RTCCALF_2`"]
+    #[inline]
+    pub fn is_rtccalf_2(&self) -> bool {
+        *self == RTCCALFR::RTCCALF_2
+    }
+    #[doc = "Checks if the value of the field is `RTCCALF_3`"]
+    #[inline]
+    pub fn is_rtccalf_3(&self) -> bool {
+        *self == RTCCALFR::RTCCALF_3
+    }
+}
+#[doc = "Values that can be written to the field `RTCTEV`"]
+pub enum RTCTEVW {
+    #[doc = "Minute changed"]
+    RTCTEV_0,
+    #[doc = "Hour changed"]
+    RTCTEV_1,
+    #[doc = "Every day at midnight (00:00)"]
+    RTCTEV_2,
+    #[doc = "Every day at noon (12:00)"]
+    RTCTEV_3,
+}
+impl RTCTEVW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            RTCTEVW::RTCTEV_0 => 0,
+            RTCTEVW::RTCTEV_1 => 1,
+            RTCTEVW::RTCTEV_2 => 2,
+            RTCTEVW::RTCTEV_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RTCTEVW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RTCTEVW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: RTCTEVW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Minute changed"]
+    #[inline]
+    pub fn rtctev_0(self) -> &'a mut W {
+        self.variant(RTCTEVW::RTCTEV_0)
+    }
+    #[doc = "Hour changed"]
+    #[inline]
+    pub fn rtctev_1(self) -> &'a mut W {
+        self.variant(RTCTEVW::RTCTEV_1)
+    }
+    #[doc = "Every day at midnight (00:00)"]
+    #[inline]
+    pub fn rtctev_2(self) -> &'a mut W {
+        self.variant(RTCTEVW::RTCTEV_2)
+    }
+    #[doc = "Every day at noon (12:00)"]
+    #[inline]
+    pub fn rtctev_3(self) -> &'a mut W {
+        self.variant(RTCTEVW::RTCTEV_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `RTCSSEL`"]
+pub enum RTCSSELW {
+    #[doc = "BCLK"]
+    RTCSSEL_0,
+}
+impl RTCSSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            RTCSSELW::RTCSSEL_0 => 0,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RTCSSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RTCSSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: RTCSSELW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "BCLK"]
+    #[inline]
+    pub fn rtcssel_0(self) -> &'a mut W {
+        self.variant(RTCSSELW::RTCSSEL_0)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `RTCHOLD`"]
+pub enum RTCHOLDW {
+    #[doc = "Real-time clock is operational"]
+    RTCHOLD_0,
+    #[doc = "When set, the calendar is stopped as well as the prescale counters, RT0PS and RT1PS are don't care"]
+    RTCHOLD_1,
+}
+impl RTCHOLDW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            RTCHOLDW::RTCHOLD_0 => false,
+            RTCHOLDW::RTCHOLD_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RTCHOLDW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RTCHOLDW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: RTCHOLDW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Real-time clock is operational"]
+    #[inline]
+    pub fn rtchold_0(self) -> &'a mut W {
+        self.variant(RTCHOLDW::RTCHOLD_0)
+    }
+    #[doc = "When set, the calendar is stopped as well as the prescale counters, RT0PS and RT1PS are don't care"]
+    #[inline]
+    pub fn rtchold_1(self) -> &'a mut W {
+        self.variant(RTCHOLDW::RTCHOLD_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `RTCBCD`"]
+pub enum RTCBCDW {
+    #[doc = "Binary (hexadecimal) code selected"]
+    RTCBCD_0,
+    #[doc = "Binary coded decimal (BCD) code selected"]
+    RTCBCD_1,
+}
+impl RTCBCDW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            RTCBCDW::RTCBCD_0 => false,
+            RTCBCDW::RTCBCD_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RTCBCDW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RTCBCDW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: RTCBCDW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Binary (hexadecimal) code selected"]
+    #[inline]
+    pub fn rtcbcd_0(self) -> &'a mut W {
+        self.variant(RTCBCDW::RTCBCD_0)
+    }
+    #[doc = "Binary coded decimal (BCD) code selected"]
+    #[inline]
+    pub fn rtcbcd_1(self) -> &'a mut W {
+        self.variant(RTCBCDW::RTCBCD_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `RTCCALF`"]
+pub enum RTCCALFW {
+    #[doc = "No frequency output to RTCCLK pin"]
+    RTCCALF_0,
+    #[doc = "512 Hz"]
+    RTCCALF_1,
+    #[doc = "256 Hz"]
+    RTCCALF_2,
+    #[doc = "1 Hz"]
+    RTCCALF_3,
+}
+impl RTCCALFW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            RTCCALFW::RTCCALF_0 => 0,
+            RTCCALFW::RTCCALF_1 => 1,
+            RTCCALFW::RTCCALF_2 => 2,
+            RTCCALFW::RTCCALF_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RTCCALFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RTCCALFW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: RTCCALFW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "No frequency output to RTCCLK pin"]
+    #[inline]
+    pub fn rtccalf_0(self) -> &'a mut W {
+        self.variant(RTCCALFW::RTCCALF_0)
+    }
+    #[doc = "512 Hz"]
+    #[inline]
+    pub fn rtccalf_1(self) -> &'a mut W {
+        self.variant(RTCCALFW::RTCCALF_1)
+    }
+    #[doc = "256 Hz"]
+    #[inline]
+    pub fn rtccalf_2(self) -> &'a mut W {
+        self.variant(RTCCALFW::RTCCALF_2)
+    }
+    #[doc = "1 Hz"]
+    #[inline]
+    pub fn rtccalf_3(self) -> &'a mut W {
+        self.variant(RTCCALFW::RTCCALF_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:1 - Real-time clock time event"]
+    #[inline]
+    pub fn rtctev(&self) -> RTCTEVR {
+        RTCTEVR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bits 2:3 - Real-time clock source select"]
+    #[inline]
+    pub fn rtcssel(&self) -> RTCSSELR {
+        RTCSSELR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 4 - Real-time clock ready"]
+    #[inline]
+    pub fn rtcrdy(&self) -> RTCRDYR {
+        RTCRDYR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 5"]
+    #[inline]
+    pub fn rtcmode(&self) -> RTCMODER {
+        RTCMODER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 6 - Real-time clock hold"]
+    #[inline]
+    pub fn rtchold(&self) -> RTCHOLDR {
+        RTCHOLDR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 7 - Real-time clock BCD select"]
+    #[inline]
+    pub fn rtcbcd(&self) -> RTCBCDR {
+        RTCBCDR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 8:9 - Real-time clock calibration frequency"]
+    #[inline]
+    pub fn rtccalf(&self) -> RTCCALFR {
+        RTCCALFR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 112 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:1 - Real-time clock time event"]
+    #[inline]
+    pub fn rtctev(&mut self) -> _RTCTEVW {
+        _RTCTEVW { w: self }
+    }
+    #[doc = "Bits 2:3 - Real-time clock source select"]
+    #[inline]
+    pub fn rtcssel(&mut self) -> _RTCSSELW {
+        _RTCSSELW { w: self }
+    }
+    #[doc = "Bit 6 - Real-time clock hold"]
+    #[inline]
+    pub fn rtchold(&mut self) -> _RTCHOLDW {
+        _RTCHOLDW { w: self }
+    }
+    #[doc = "Bit 7 - Real-time clock BCD select"]
+    #[inline]
+    pub fn rtcbcd(&mut self) -> _RTCBCDW {
+        _RTCBCDW { w: self }
+    }
+    #[doc = "Bits 8:9 - Real-time clock calibration frequency"]
+    #[inline]
+    pub fn rtccalf(&mut self) -> _RTCCALFW {
+        _RTCCALFW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/rtc_c/rtcdate.rs b/example-source/msp432p401r/src/rtc_c/rtcdate.rs
new file mode 100644
index 0000000..96034e1
--- /dev/null
+++ b/example-source/msp432p401r/src/rtc_c/rtcdate.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::RTCDATE {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DAYR {
+    bits: u8,
+}
+impl DAYR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct MONTHR {
+    bits: u8,
+}
+impl MONTHR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DAYW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DAYW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 31;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MONTHW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MONTHW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:4 - Day of month (1 to 28, 29, 30, 31)"]
+    #[inline]
+    pub fn day(&self) -> DAYR {
+        let bits = {
+            const MASK: u8 = 31;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        DAYR { bits }
+    }
+    #[doc = "Bits 8:11 - Month (1 to 12)"]
+    #[inline]
+    pub fn month(&self) -> MONTHR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        MONTHR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:4 - Day of month (1 to 28, 29, 30, 31)"]
+    #[inline]
+    pub fn day(&mut self) -> _DAYW {
+        _DAYW { w: self }
+    }
+    #[doc = "Bits 8:11 - Month (1 to 12)"]
+    #[inline]
+    pub fn month(&mut self) -> _MONTHW {
+        _MONTHW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/rtc_c/rtciv.rs b/example-source/msp432p401r/src/rtc_c/rtciv.rs
new file mode 100644
index 0000000..3c63650
--- /dev/null
+++ b/example-source/msp432p401r/src/rtc_c/rtciv.rs
@@ -0,0 +1,115 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::RTCIV {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `RTCIV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RTCIVR {
+    #[doc = "No interrupt pending"]
+    RTCIV_0,
+    #[doc = "Interrupt Source: RTC oscillator failure; Interrupt Flag: RTCOFIFG; Interrupt Priority: Highest"]
+    RTCIV_2,
+    #[doc = "Interrupt Source: RTC ready; Interrupt Flag: RTCRDYIFG"]
+    RTCIV_4,
+    #[doc = "Interrupt Source: RTC interval timer; Interrupt Flag: RTCTEVIFG"]
+    RTCIV_6,
+    #[doc = "Interrupt Source: RTC user alarm; Interrupt Flag: RTCAIFG"]
+    RTCIV_8,
+    #[doc = "Interrupt Source: RTC prescaler 0; Interrupt Flag: RT0PSIFG"]
+    RTCIV_10,
+    #[doc = "Interrupt Source: RTC prescaler 1; Interrupt Flag: RT1PSIFG"]
+    RTCIV_12,
+    #[doc = r" Reserved"]
+    _Reserved(u16),
+}
+impl RTCIVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        match *self {
+            RTCIVR::RTCIV_0 => 0,
+            RTCIVR::RTCIV_2 => 2,
+            RTCIVR::RTCIV_4 => 4,
+            RTCIVR::RTCIV_6 => 6,
+            RTCIVR::RTCIV_8 => 8,
+            RTCIVR::RTCIV_10 => 10,
+            RTCIVR::RTCIV_12 => 12,
+            RTCIVR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u16) -> RTCIVR {
+        match value {
+            0 => RTCIVR::RTCIV_0,
+            2 => RTCIVR::RTCIV_2,
+            4 => RTCIVR::RTCIV_4,
+            6 => RTCIVR::RTCIV_6,
+            8 => RTCIVR::RTCIV_8,
+            10 => RTCIVR::RTCIV_10,
+            12 => RTCIVR::RTCIV_12,
+            i => RTCIVR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `RTCIV_0`"]
+    #[inline]
+    pub fn is_rtciv_0(&self) -> bool {
+        *self == RTCIVR::RTCIV_0
+    }
+    #[doc = "Checks if the value of the field is `RTCIV_2`"]
+    #[inline]
+    pub fn is_rtciv_2(&self) -> bool {
+        *self == RTCIVR::RTCIV_2
+    }
+    #[doc = "Checks if the value of the field is `RTCIV_4`"]
+    #[inline]
+    pub fn is_rtciv_4(&self) -> bool {
+        *self == RTCIVR::RTCIV_4
+    }
+    #[doc = "Checks if the value of the field is `RTCIV_6`"]
+    #[inline]
+    pub fn is_rtciv_6(&self) -> bool {
+        *self == RTCIVR::RTCIV_6
+    }
+    #[doc = "Checks if the value of the field is `RTCIV_8`"]
+    #[inline]
+    pub fn is_rtciv_8(&self) -> bool {
+        *self == RTCIVR::RTCIV_8
+    }
+    #[doc = "Checks if the value of the field is `RTCIV_10`"]
+    #[inline]
+    pub fn is_rtciv_10(&self) -> bool {
+        *self == RTCIVR::RTCIV_10
+    }
+    #[doc = "Checks if the value of the field is `RTCIV_12`"]
+    #[inline]
+    pub fn is_rtciv_12(&self) -> bool {
+        *self == RTCIVR::RTCIV_12
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Real-time clock interrupt vector value"]
+    #[inline]
+    pub fn rtciv(&self) -> RTCIVR {
+        RTCIVR::_from({
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/rtc_c/rtcocal.rs b/example-source/msp432p401r/src/rtc_c/rtcocal.rs
new file mode 100644
index 0000000..3ad505c
--- /dev/null
+++ b/example-source/msp432p401r/src/rtc_c/rtcocal.rs
@@ -0,0 +1,224 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::RTCOCAL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct RTCOCALR {
+    bits: u8,
+}
+impl RTCOCALR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `RTCOCALS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RTCOCALSR {
+    #[doc = "Down calibration. Frequency adjusted down."]
+    RTCOCALS_0,
+    #[doc = "Up calibration. Frequency adjusted up."]
+    RTCOCALS_1,
+}
+impl RTCOCALSR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            RTCOCALSR::RTCOCALS_0 => false,
+            RTCOCALSR::RTCOCALS_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> RTCOCALSR {
+        match value {
+            false => RTCOCALSR::RTCOCALS_0,
+            true => RTCOCALSR::RTCOCALS_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RTCOCALS_0`"]
+    #[inline]
+    pub fn is_rtcocals_0(&self) -> bool {
+        *self == RTCOCALSR::RTCOCALS_0
+    }
+    #[doc = "Checks if the value of the field is `RTCOCALS_1`"]
+    #[inline]
+    pub fn is_rtcocals_1(&self) -> bool {
+        *self == RTCOCALSR::RTCOCALS_1
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RTCOCALW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RTCOCALW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `RTCOCALS`"]
+pub enum RTCOCALSW {
+    #[doc = "Down calibration. Frequency adjusted down."]
+    RTCOCALS_0,
+    #[doc = "Up calibration. Frequency adjusted up."]
+    RTCOCALS_1,
+}
+impl RTCOCALSW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            RTCOCALSW::RTCOCALS_0 => false,
+            RTCOCALSW::RTCOCALS_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RTCOCALSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RTCOCALSW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: RTCOCALSW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Down calibration. Frequency adjusted down."]
+    #[inline]
+    pub fn rtcocals_0(self) -> &'a mut W {
+        self.variant(RTCOCALSW::RTCOCALS_0)
+    }
+    #[doc = "Up calibration. Frequency adjusted up."]
+    #[inline]
+    pub fn rtcocals_1(self) -> &'a mut W {
+        self.variant(RTCOCALSW::RTCOCALS_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Real-time clock offset error calibration"]
+    #[inline]
+    pub fn rtcocal(&self) -> RTCOCALR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        RTCOCALR { bits }
+    }
+    #[doc = "Bit 15 - Real-time clock offset error calibration sign"]
+    #[inline]
+    pub fn rtcocals(&self) -> RTCOCALSR {
+        RTCOCALSR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Real-time clock offset error calibration"]
+    #[inline]
+    pub fn rtcocal(&mut self) -> _RTCOCALW {
+        _RTCOCALW { w: self }
+    }
+    #[doc = "Bit 15 - Real-time clock offset error calibration sign"]
+    #[inline]
+    pub fn rtcocals(&mut self) -> _RTCOCALSW {
+        _RTCOCALSW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/rtc_c/rtcps.rs b/example-source/msp432p401r/src/rtc_c/rtcps.rs
new file mode 100644
index 0000000..6104099
--- /dev/null
+++ b/example-source/msp432p401r/src/rtc_c/rtcps.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::RTCPS {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct RT0PSR {
+    bits: u8,
+}
+impl RT0PSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct RT1PSR {
+    bits: u8,
+}
+impl RT1PSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RT0PSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RT0PSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RT1PSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RT1PSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Prescale timer 0 counter value"]
+    #[inline]
+    pub fn rt0ps(&self) -> RT0PSR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        RT0PSR { bits }
+    }
+    #[doc = "Bits 8:15 - Prescale timer 1 counter value"]
+    #[inline]
+    pub fn rt1ps(&self) -> RT1PSR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        RT1PSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Prescale timer 0 counter value"]
+    #[inline]
+    pub fn rt0ps(&mut self) -> _RT0PSW {
+        _RT0PSW { w: self }
+    }
+    #[doc = "Bits 8:15 - Prescale timer 1 counter value"]
+    #[inline]
+    pub fn rt1ps(&mut self) -> _RT1PSW {
+        _RT1PSW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/rtc_c/rtcps0ctl.rs b/example-source/msp432p401r/src/rtc_c/rtcps0ctl.rs
new file mode 100644
index 0000000..c43e6f1
--- /dev/null
+++ b/example-source/msp432p401r/src/rtc_c/rtcps0ctl.rs
@@ -0,0 +1,506 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::RTCPS0CTL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `RT0PSIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RT0PSIFGR {
+    #[doc = "No time event occurred"]
+    RT0PSIFG_0,
+    #[doc = "Time event occurred"]
+    RT0PSIFG_1,
+}
+impl RT0PSIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            RT0PSIFGR::RT0PSIFG_0 => false,
+            RT0PSIFGR::RT0PSIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> RT0PSIFGR {
+        match value {
+            false => RT0PSIFGR::RT0PSIFG_0,
+            true => RT0PSIFGR::RT0PSIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RT0PSIFG_0`"]
+    #[inline]
+    pub fn is_rt0psifg_0(&self) -> bool {
+        *self == RT0PSIFGR::RT0PSIFG_0
+    }
+    #[doc = "Checks if the value of the field is `RT0PSIFG_1`"]
+    #[inline]
+    pub fn is_rt0psifg_1(&self) -> bool {
+        *self == RT0PSIFGR::RT0PSIFG_1
+    }
+}
+#[doc = "Possible values of the field `RT0PSIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RT0PSIER {
+    #[doc = "Interrupt not enabled"]
+    RT0PSIE_0,
+    #[doc = "Interrupt enabled (LPM3/LPM3.5 wake-up enabled)"]
+    RT0PSIE_1,
+}
+impl RT0PSIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            RT0PSIER::RT0PSIE_0 => false,
+            RT0PSIER::RT0PSIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> RT0PSIER {
+        match value {
+            false => RT0PSIER::RT0PSIE_0,
+            true => RT0PSIER::RT0PSIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RT0PSIE_0`"]
+    #[inline]
+    pub fn is_rt0psie_0(&self) -> bool {
+        *self == RT0PSIER::RT0PSIE_0
+    }
+    #[doc = "Checks if the value of the field is `RT0PSIE_1`"]
+    #[inline]
+    pub fn is_rt0psie_1(&self) -> bool {
+        *self == RT0PSIER::RT0PSIE_1
+    }
+}
+#[doc = "Possible values of the field `RT0IP`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RT0IPR {
+    #[doc = "Divide by 2"]
+    RT0IP_0,
+    #[doc = "Divide by 4"]
+    RT0IP_1,
+    #[doc = "Divide by 8"]
+    RT0IP_2,
+    #[doc = "Divide by 16"]
+    RT0IP_3,
+    #[doc = "Divide by 32"]
+    RT0IP_4,
+    #[doc = "Divide by 64"]
+    RT0IP_5,
+    #[doc = "Divide by 128"]
+    RT0IP_6,
+    #[doc = "Divide by 256"]
+    RT0IP_7,
+}
+impl RT0IPR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            RT0IPR::RT0IP_0 => 0,
+            RT0IPR::RT0IP_1 => 1,
+            RT0IPR::RT0IP_2 => 2,
+            RT0IPR::RT0IP_3 => 3,
+            RT0IPR::RT0IP_4 => 4,
+            RT0IPR::RT0IP_5 => 5,
+            RT0IPR::RT0IP_6 => 6,
+            RT0IPR::RT0IP_7 => 7,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> RT0IPR {
+        match value {
+            0 => RT0IPR::RT0IP_0,
+            1 => RT0IPR::RT0IP_1,
+            2 => RT0IPR::RT0IP_2,
+            3 => RT0IPR::RT0IP_3,
+            4 => RT0IPR::RT0IP_4,
+            5 => RT0IPR::RT0IP_5,
+            6 => RT0IPR::RT0IP_6,
+            7 => RT0IPR::RT0IP_7,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `RT0IP_0`"]
+    #[inline]
+    pub fn is_rt0ip_0(&self) -> bool {
+        *self == RT0IPR::RT0IP_0
+    }
+    #[doc = "Checks if the value of the field is `RT0IP_1`"]
+    #[inline]
+    pub fn is_rt0ip_1(&self) -> bool {
+        *self == RT0IPR::RT0IP_1
+    }
+    #[doc = "Checks if the value of the field is `RT0IP_2`"]
+    #[inline]
+    pub fn is_rt0ip_2(&self) -> bool {
+        *self == RT0IPR::RT0IP_2
+    }
+    #[doc = "Checks if the value of the field is `RT0IP_3`"]
+    #[inline]
+    pub fn is_rt0ip_3(&self) -> bool {
+        *self == RT0IPR::RT0IP_3
+    }
+    #[doc = "Checks if the value of the field is `RT0IP_4`"]
+    #[inline]
+    pub fn is_rt0ip_4(&self) -> bool {
+        *self == RT0IPR::RT0IP_4
+    }
+    #[doc = "Checks if the value of the field is `RT0IP_5`"]
+    #[inline]
+    pub fn is_rt0ip_5(&self) -> bool {
+        *self == RT0IPR::RT0IP_5
+    }
+    #[doc = "Checks if the value of the field is `RT0IP_6`"]
+    #[inline]
+    pub fn is_rt0ip_6(&self) -> bool {
+        *self == RT0IPR::RT0IP_6
+    }
+    #[doc = "Checks if the value of the field is `RT0IP_7`"]
+    #[inline]
+    pub fn is_rt0ip_7(&self) -> bool {
+        *self == RT0IPR::RT0IP_7
+    }
+}
+#[doc = "Values that can be written to the field `RT0PSIFG`"]
+pub enum RT0PSIFGW {
+    #[doc = "No time event occurred"]
+    RT0PSIFG_0,
+    #[doc = "Time event occurred"]
+    RT0PSIFG_1,
+}
+impl RT0PSIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            RT0PSIFGW::RT0PSIFG_0 => false,
+            RT0PSIFGW::RT0PSIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RT0PSIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RT0PSIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: RT0PSIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No time event occurred"]
+    #[inline]
+    pub fn rt0psifg_0(self) -> &'a mut W {
+        self.variant(RT0PSIFGW::RT0PSIFG_0)
+    }
+    #[doc = "Time event occurred"]
+    #[inline]
+    pub fn rt0psifg_1(self) -> &'a mut W {
+        self.variant(RT0PSIFGW::RT0PSIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `RT0PSIE`"]
+pub enum RT0PSIEW {
+    #[doc = "Interrupt not enabled"]
+    RT0PSIE_0,
+    #[doc = "Interrupt enabled (LPM3/LPM3.5 wake-up enabled)"]
+    RT0PSIE_1,
+}
+impl RT0PSIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            RT0PSIEW::RT0PSIE_0 => false,
+            RT0PSIEW::RT0PSIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RT0PSIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RT0PSIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: RT0PSIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt not enabled"]
+    #[inline]
+    pub fn rt0psie_0(self) -> &'a mut W {
+        self.variant(RT0PSIEW::RT0PSIE_0)
+    }
+    #[doc = "Interrupt enabled (LPM3/LPM3.5 wake-up enabled)"]
+    #[inline]
+    pub fn rt0psie_1(self) -> &'a mut W {
+        self.variant(RT0PSIEW::RT0PSIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `RT0IP`"]
+pub enum RT0IPW {
+    #[doc = "Divide by 2"]
+    RT0IP_0,
+    #[doc = "Divide by 4"]
+    RT0IP_1,
+    #[doc = "Divide by 8"]
+    RT0IP_2,
+    #[doc = "Divide by 16"]
+    RT0IP_3,
+    #[doc = "Divide by 32"]
+    RT0IP_4,
+    #[doc = "Divide by 64"]
+    RT0IP_5,
+    #[doc = "Divide by 128"]
+    RT0IP_6,
+    #[doc = "Divide by 256"]
+    RT0IP_7,
+}
+impl RT0IPW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            RT0IPW::RT0IP_0 => 0,
+            RT0IPW::RT0IP_1 => 1,
+            RT0IPW::RT0IP_2 => 2,
+            RT0IPW::RT0IP_3 => 3,
+            RT0IPW::RT0IP_4 => 4,
+            RT0IPW::RT0IP_5 => 5,
+            RT0IPW::RT0IP_6 => 6,
+            RT0IPW::RT0IP_7 => 7,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RT0IPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RT0IPW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: RT0IPW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Divide by 2"]
+    #[inline]
+    pub fn rt0ip_0(self) -> &'a mut W {
+        self.variant(RT0IPW::RT0IP_0)
+    }
+    #[doc = "Divide by 4"]
+    #[inline]
+    pub fn rt0ip_1(self) -> &'a mut W {
+        self.variant(RT0IPW::RT0IP_1)
+    }
+    #[doc = "Divide by 8"]
+    #[inline]
+    pub fn rt0ip_2(self) -> &'a mut W {
+        self.variant(RT0IPW::RT0IP_2)
+    }
+    #[doc = "Divide by 16"]
+    #[inline]
+    pub fn rt0ip_3(self) -> &'a mut W {
+        self.variant(RT0IPW::RT0IP_3)
+    }
+    #[doc = "Divide by 32"]
+    #[inline]
+    pub fn rt0ip_4(self) -> &'a mut W {
+        self.variant(RT0IPW::RT0IP_4)
+    }
+    #[doc = "Divide by 64"]
+    #[inline]
+    pub fn rt0ip_5(self) -> &'a mut W {
+        self.variant(RT0IPW::RT0IP_5)
+    }
+    #[doc = "Divide by 128"]
+    #[inline]
+    pub fn rt0ip_6(self) -> &'a mut W {
+        self.variant(RT0IPW::RT0IP_6)
+    }
+    #[doc = "Divide by 256"]
+    #[inline]
+    pub fn rt0ip_7(self) -> &'a mut W {
+        self.variant(RT0IPW::RT0IP_7)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Prescale timer 0 interrupt flag"]
+    #[inline]
+    pub fn rt0psifg(&self) -> RT0PSIFGR {
+        RT0PSIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Prescale timer 0 interrupt enable"]
+    #[inline]
+    pub fn rt0psie(&self) -> RT0PSIER {
+        RT0PSIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 2:4 - Prescale timer 0 interrupt interval"]
+    #[inline]
+    pub fn rt0ip(&self) -> RT0IPR {
+        RT0IPR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Prescale timer 0 interrupt flag"]
+    #[inline]
+    pub fn rt0psifg(&mut self) -> _RT0PSIFGW {
+        _RT0PSIFGW { w: self }
+    }
+    #[doc = "Bit 1 - Prescale timer 0 interrupt enable"]
+    #[inline]
+    pub fn rt0psie(&mut self) -> _RT0PSIEW {
+        _RT0PSIEW { w: self }
+    }
+    #[doc = "Bits 2:4 - Prescale timer 0 interrupt interval"]
+    #[inline]
+    pub fn rt0ip(&mut self) -> _RT0IPW {
+        _RT0IPW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/rtc_c/rtcps1ctl.rs b/example-source/msp432p401r/src/rtc_c/rtcps1ctl.rs
new file mode 100644
index 0000000..7e645a9
--- /dev/null
+++ b/example-source/msp432p401r/src/rtc_c/rtcps1ctl.rs
@@ -0,0 +1,506 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::RTCPS1CTL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `RT1PSIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RT1PSIFGR {
+    #[doc = "No time event occurred"]
+    RT1PSIFG_0,
+    #[doc = "Time event occurred"]
+    RT1PSIFG_1,
+}
+impl RT1PSIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            RT1PSIFGR::RT1PSIFG_0 => false,
+            RT1PSIFGR::RT1PSIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> RT1PSIFGR {
+        match value {
+            false => RT1PSIFGR::RT1PSIFG_0,
+            true => RT1PSIFGR::RT1PSIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RT1PSIFG_0`"]
+    #[inline]
+    pub fn is_rt1psifg_0(&self) -> bool {
+        *self == RT1PSIFGR::RT1PSIFG_0
+    }
+    #[doc = "Checks if the value of the field is `RT1PSIFG_1`"]
+    #[inline]
+    pub fn is_rt1psifg_1(&self) -> bool {
+        *self == RT1PSIFGR::RT1PSIFG_1
+    }
+}
+#[doc = "Possible values of the field `RT1PSIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RT1PSIER {
+    #[doc = "Interrupt not enabled"]
+    RT1PSIE_0,
+    #[doc = "Interrupt enabled (LPM3/LPM3.5 wake-up enabled)"]
+    RT1PSIE_1,
+}
+impl RT1PSIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            RT1PSIER::RT1PSIE_0 => false,
+            RT1PSIER::RT1PSIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> RT1PSIER {
+        match value {
+            false => RT1PSIER::RT1PSIE_0,
+            true => RT1PSIER::RT1PSIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RT1PSIE_0`"]
+    #[inline]
+    pub fn is_rt1psie_0(&self) -> bool {
+        *self == RT1PSIER::RT1PSIE_0
+    }
+    #[doc = "Checks if the value of the field is `RT1PSIE_1`"]
+    #[inline]
+    pub fn is_rt1psie_1(&self) -> bool {
+        *self == RT1PSIER::RT1PSIE_1
+    }
+}
+#[doc = "Possible values of the field `RT1IP`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RT1IPR {
+    #[doc = "Divide by 2"]
+    RT1IP_0,
+    #[doc = "Divide by 4"]
+    RT1IP_1,
+    #[doc = "Divide by 8"]
+    RT1IP_2,
+    #[doc = "Divide by 16"]
+    RT1IP_3,
+    #[doc = "Divide by 32"]
+    RT1IP_4,
+    #[doc = "Divide by 64"]
+    RT1IP_5,
+    #[doc = "Divide by 128"]
+    RT1IP_6,
+    #[doc = "Divide by 256"]
+    RT1IP_7,
+}
+impl RT1IPR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            RT1IPR::RT1IP_0 => 0,
+            RT1IPR::RT1IP_1 => 1,
+            RT1IPR::RT1IP_2 => 2,
+            RT1IPR::RT1IP_3 => 3,
+            RT1IPR::RT1IP_4 => 4,
+            RT1IPR::RT1IP_5 => 5,
+            RT1IPR::RT1IP_6 => 6,
+            RT1IPR::RT1IP_7 => 7,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> RT1IPR {
+        match value {
+            0 => RT1IPR::RT1IP_0,
+            1 => RT1IPR::RT1IP_1,
+            2 => RT1IPR::RT1IP_2,
+            3 => RT1IPR::RT1IP_3,
+            4 => RT1IPR::RT1IP_4,
+            5 => RT1IPR::RT1IP_5,
+            6 => RT1IPR::RT1IP_6,
+            7 => RT1IPR::RT1IP_7,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `RT1IP_0`"]
+    #[inline]
+    pub fn is_rt1ip_0(&self) -> bool {
+        *self == RT1IPR::RT1IP_0
+    }
+    #[doc = "Checks if the value of the field is `RT1IP_1`"]
+    #[inline]
+    pub fn is_rt1ip_1(&self) -> bool {
+        *self == RT1IPR::RT1IP_1
+    }
+    #[doc = "Checks if the value of the field is `RT1IP_2`"]
+    #[inline]
+    pub fn is_rt1ip_2(&self) -> bool {
+        *self == RT1IPR::RT1IP_2
+    }
+    #[doc = "Checks if the value of the field is `RT1IP_3`"]
+    #[inline]
+    pub fn is_rt1ip_3(&self) -> bool {
+        *self == RT1IPR::RT1IP_3
+    }
+    #[doc = "Checks if the value of the field is `RT1IP_4`"]
+    #[inline]
+    pub fn is_rt1ip_4(&self) -> bool {
+        *self == RT1IPR::RT1IP_4
+    }
+    #[doc = "Checks if the value of the field is `RT1IP_5`"]
+    #[inline]
+    pub fn is_rt1ip_5(&self) -> bool {
+        *self == RT1IPR::RT1IP_5
+    }
+    #[doc = "Checks if the value of the field is `RT1IP_6`"]
+    #[inline]
+    pub fn is_rt1ip_6(&self) -> bool {
+        *self == RT1IPR::RT1IP_6
+    }
+    #[doc = "Checks if the value of the field is `RT1IP_7`"]
+    #[inline]
+    pub fn is_rt1ip_7(&self) -> bool {
+        *self == RT1IPR::RT1IP_7
+    }
+}
+#[doc = "Values that can be written to the field `RT1PSIFG`"]
+pub enum RT1PSIFGW {
+    #[doc = "No time event occurred"]
+    RT1PSIFG_0,
+    #[doc = "Time event occurred"]
+    RT1PSIFG_1,
+}
+impl RT1PSIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            RT1PSIFGW::RT1PSIFG_0 => false,
+            RT1PSIFGW::RT1PSIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RT1PSIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RT1PSIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: RT1PSIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No time event occurred"]
+    #[inline]
+    pub fn rt1psifg_0(self) -> &'a mut W {
+        self.variant(RT1PSIFGW::RT1PSIFG_0)
+    }
+    #[doc = "Time event occurred"]
+    #[inline]
+    pub fn rt1psifg_1(self) -> &'a mut W {
+        self.variant(RT1PSIFGW::RT1PSIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `RT1PSIE`"]
+pub enum RT1PSIEW {
+    #[doc = "Interrupt not enabled"]
+    RT1PSIE_0,
+    #[doc = "Interrupt enabled (LPM3/LPM3.5 wake-up enabled)"]
+    RT1PSIE_1,
+}
+impl RT1PSIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            RT1PSIEW::RT1PSIE_0 => false,
+            RT1PSIEW::RT1PSIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RT1PSIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RT1PSIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: RT1PSIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt not enabled"]
+    #[inline]
+    pub fn rt1psie_0(self) -> &'a mut W {
+        self.variant(RT1PSIEW::RT1PSIE_0)
+    }
+    #[doc = "Interrupt enabled (LPM3/LPM3.5 wake-up enabled)"]
+    #[inline]
+    pub fn rt1psie_1(self) -> &'a mut W {
+        self.variant(RT1PSIEW::RT1PSIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `RT1IP`"]
+pub enum RT1IPW {
+    #[doc = "Divide by 2"]
+    RT1IP_0,
+    #[doc = "Divide by 4"]
+    RT1IP_1,
+    #[doc = "Divide by 8"]
+    RT1IP_2,
+    #[doc = "Divide by 16"]
+    RT1IP_3,
+    #[doc = "Divide by 32"]
+    RT1IP_4,
+    #[doc = "Divide by 64"]
+    RT1IP_5,
+    #[doc = "Divide by 128"]
+    RT1IP_6,
+    #[doc = "Divide by 256"]
+    RT1IP_7,
+}
+impl RT1IPW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            RT1IPW::RT1IP_0 => 0,
+            RT1IPW::RT1IP_1 => 1,
+            RT1IPW::RT1IP_2 => 2,
+            RT1IPW::RT1IP_3 => 3,
+            RT1IPW::RT1IP_4 => 4,
+            RT1IPW::RT1IP_5 => 5,
+            RT1IPW::RT1IP_6 => 6,
+            RT1IPW::RT1IP_7 => 7,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RT1IPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RT1IPW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: RT1IPW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Divide by 2"]
+    #[inline]
+    pub fn rt1ip_0(self) -> &'a mut W {
+        self.variant(RT1IPW::RT1IP_0)
+    }
+    #[doc = "Divide by 4"]
+    #[inline]
+    pub fn rt1ip_1(self) -> &'a mut W {
+        self.variant(RT1IPW::RT1IP_1)
+    }
+    #[doc = "Divide by 8"]
+    #[inline]
+    pub fn rt1ip_2(self) -> &'a mut W {
+        self.variant(RT1IPW::RT1IP_2)
+    }
+    #[doc = "Divide by 16"]
+    #[inline]
+    pub fn rt1ip_3(self) -> &'a mut W {
+        self.variant(RT1IPW::RT1IP_3)
+    }
+    #[doc = "Divide by 32"]
+    #[inline]
+    pub fn rt1ip_4(self) -> &'a mut W {
+        self.variant(RT1IPW::RT1IP_4)
+    }
+    #[doc = "Divide by 64"]
+    #[inline]
+    pub fn rt1ip_5(self) -> &'a mut W {
+        self.variant(RT1IPW::RT1IP_5)
+    }
+    #[doc = "Divide by 128"]
+    #[inline]
+    pub fn rt1ip_6(self) -> &'a mut W {
+        self.variant(RT1IPW::RT1IP_6)
+    }
+    #[doc = "Divide by 256"]
+    #[inline]
+    pub fn rt1ip_7(self) -> &'a mut W {
+        self.variant(RT1IPW::RT1IP_7)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Prescale timer 1 interrupt flag"]
+    #[inline]
+    pub fn rt1psifg(&self) -> RT1PSIFGR {
+        RT1PSIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Prescale timer 1 interrupt enable"]
+    #[inline]
+    pub fn rt1psie(&self) -> RT1PSIER {
+        RT1PSIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 2:4 - Prescale timer 1 interrupt interval"]
+    #[inline]
+    pub fn rt1ip(&self) -> RT1IPR {
+        RT1IPR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Prescale timer 1 interrupt flag"]
+    #[inline]
+    pub fn rt1psifg(&mut self) -> _RT1PSIFGW {
+        _RT1PSIFGW { w: self }
+    }
+    #[doc = "Bit 1 - Prescale timer 1 interrupt enable"]
+    #[inline]
+    pub fn rt1psie(&mut self) -> _RT1PSIEW {
+        _RT1PSIEW { w: self }
+    }
+    #[doc = "Bits 2:4 - Prescale timer 1 interrupt interval"]
+    #[inline]
+    pub fn rt1ip(&mut self) -> _RT1IPW {
+        _RT1IPW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/rtc_c/rtctcmp.rs b/example-source/msp432p401r/src/rtc_c/rtctcmp.rs
new file mode 100644
index 0000000..0301158
--- /dev/null
+++ b/example-source/msp432p401r/src/rtc_c/rtctcmp.rs
@@ -0,0 +1,311 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::RTCTCMP {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct RTCTCMPR {
+    bits: u8,
+}
+impl RTCTCMPR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `RTCTCOK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RTCTCOKR {
+    #[doc = "Write to RTCTCMPx is unsuccessful"]
+    RTCTCOK_0,
+    #[doc = "Write to RTCTCMPx is successful"]
+    RTCTCOK_1,
+}
+impl RTCTCOKR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            RTCTCOKR::RTCTCOK_0 => false,
+            RTCTCOKR::RTCTCOK_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> RTCTCOKR {
+        match value {
+            false => RTCTCOKR::RTCTCOK_0,
+            true => RTCTCOKR::RTCTCOK_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RTCTCOK_0`"]
+    #[inline]
+    pub fn is_rtctcok_0(&self) -> bool {
+        *self == RTCTCOKR::RTCTCOK_0
+    }
+    #[doc = "Checks if the value of the field is `RTCTCOK_1`"]
+    #[inline]
+    pub fn is_rtctcok_1(&self) -> bool {
+        *self == RTCTCOKR::RTCTCOK_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct RTCTCRDYR {
+    bits: bool,
+}
+impl RTCTCRDYR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `RTCTCMPS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RTCTCMPSR {
+    #[doc = "Down calibration. Frequency adjusted down"]
+    RTCTCMPS_0,
+    #[doc = "Up calibration. Frequency adjusted up"]
+    RTCTCMPS_1,
+}
+impl RTCTCMPSR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            RTCTCMPSR::RTCTCMPS_0 => false,
+            RTCTCMPSR::RTCTCMPS_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> RTCTCMPSR {
+        match value {
+            false => RTCTCMPSR::RTCTCMPS_0,
+            true => RTCTCMPSR::RTCTCMPS_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RTCTCMPS_0`"]
+    #[inline]
+    pub fn is_rtctcmps_0(&self) -> bool {
+        *self == RTCTCMPSR::RTCTCMPS_0
+    }
+    #[doc = "Checks if the value of the field is `RTCTCMPS_1`"]
+    #[inline]
+    pub fn is_rtctcmps_1(&self) -> bool {
+        *self == RTCTCMPSR::RTCTCMPS_1
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RTCTCMPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RTCTCMPW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `RTCTCMPS`"]
+pub enum RTCTCMPSW {
+    #[doc = "Down calibration. Frequency adjusted down"]
+    RTCTCMPS_0,
+    #[doc = "Up calibration. Frequency adjusted up"]
+    RTCTCMPS_1,
+}
+impl RTCTCMPSW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            RTCTCMPSW::RTCTCMPS_0 => false,
+            RTCTCMPSW::RTCTCMPS_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RTCTCMPSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RTCTCMPSW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: RTCTCMPSW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Down calibration. Frequency adjusted down"]
+    #[inline]
+    pub fn rtctcmps_0(self) -> &'a mut W {
+        self.variant(RTCTCMPSW::RTCTCMPS_0)
+    }
+    #[doc = "Up calibration. Frequency adjusted up"]
+    #[inline]
+    pub fn rtctcmps_1(self) -> &'a mut W {
+        self.variant(RTCTCMPSW::RTCTCMPS_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Real-time clock temperature compensation"]
+    #[inline]
+    pub fn rtctcmp(&self) -> RTCTCMPR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        RTCTCMPR { bits }
+    }
+    #[doc = "Bit 13 - Real-time clock temperature compensation write OK"]
+    #[inline]
+    pub fn rtctcok(&self) -> RTCTCOKR {
+        RTCTCOKR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 14 - Real-time clock temperature compensation ready"]
+    #[inline]
+    pub fn rtctcrdy(&self) -> RTCTCRDYR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        };
+        RTCTCRDYR { bits }
+    }
+    #[doc = "Bit 15 - Real-time clock temperature compensation sign"]
+    #[inline]
+    pub fn rtctcmps(&self) -> RTCTCMPSR {
+        RTCTCMPSR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 16384 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Real-time clock temperature compensation"]
+    #[inline]
+    pub fn rtctcmp(&mut self) -> _RTCTCMPW {
+        _RTCTCMPW { w: self }
+    }
+    #[doc = "Bit 15 - Real-time clock temperature compensation sign"]
+    #[inline]
+    pub fn rtctcmps(&mut self) -> _RTCTCMPSW {
+        _RTCTCMPSW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/rtc_c/rtctim0.rs b/example-source/msp432p401r/src/rtc_c/rtctim0.rs
new file mode 100644
index 0000000..e85d1d4
--- /dev/null
+++ b/example-source/msp432p401r/src/rtc_c/rtctim0.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::RTCTIM0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SECONDSR {
+    bits: u8,
+}
+impl SECONDSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct MINUTESR {
+    bits: u8,
+}
+impl MINUTESR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SECONDSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SECONDSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 63;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MINUTESW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MINUTESW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 63;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:5 - Seconds (0 to 59)"]
+    #[inline]
+    pub fn seconds(&self) -> SECONDSR {
+        let bits = {
+            const MASK: u8 = 63;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        SECONDSR { bits }
+    }
+    #[doc = "Bits 8:13 - Minutes (0 to 59)"]
+    #[inline]
+    pub fn minutes(&self) -> MINUTESR {
+        let bits = {
+            const MASK: u8 = 63;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        MINUTESR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:5 - Seconds (0 to 59)"]
+    #[inline]
+    pub fn seconds(&mut self) -> _SECONDSW {
+        _SECONDSW { w: self }
+    }
+    #[doc = "Bits 8:13 - Minutes (0 to 59)"]
+    #[inline]
+    pub fn minutes(&mut self) -> _MINUTESW {
+        _MINUTESW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/rtc_c/rtctim1.rs b/example-source/msp432p401r/src/rtc_c/rtctim1.rs
new file mode 100644
index 0000000..2445aa8
--- /dev/null
+++ b/example-source/msp432p401r/src/rtc_c/rtctim1.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::RTCTIM1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct HOURSR {
+    bits: u8,
+}
+impl HOURSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DAYOFWEEKR {
+    bits: u8,
+}
+impl DAYOFWEEKR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _HOURSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _HOURSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 31;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DAYOFWEEKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DAYOFWEEKW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:4 - Hours (0 to 23)"]
+    #[inline]
+    pub fn hours(&self) -> HOURSR {
+        let bits = {
+            const MASK: u8 = 31;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        HOURSR { bits }
+    }
+    #[doc = "Bits 8:10 - Day of week (0 to 6)"]
+    #[inline]
+    pub fn dayof_week(&self) -> DAYOFWEEKR {
+        let bits = {
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        DAYOFWEEKR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:4 - Hours (0 to 23)"]
+    #[inline]
+    pub fn hours(&mut self) -> _HOURSW {
+        _HOURSW { w: self }
+    }
+    #[doc = "Bits 8:10 - Day of week (0 to 6)"]
+    #[inline]
+    pub fn dayof_week(&mut self) -> _DAYOFWEEKW {
+        _DAYOFWEEKW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/rtc_c/rtcyear.rs b/example-source/msp432p401r/src/rtc_c/rtcyear.rs
new file mode 100644
index 0000000..f6e8842
--- /dev/null
+++ b/example-source/msp432p401r/src/rtc_c/rtcyear.rs
@@ -0,0 +1,146 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::RTCYEAR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct YEARLOWBYTER {
+    bits: u8,
+}
+impl YEARLOWBYTER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct YEARHIGHBYTER {
+    bits: u8,
+}
+impl YEARHIGHBYTER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _YEARLOWBYTEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _YEARLOWBYTEW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _YEARHIGHBYTEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _YEARHIGHBYTEW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Year low byte. Valid values for Year are 0 to 4095."]
+    #[inline]
+    pub fn year_low_byte(&self) -> YEARLOWBYTER {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        YEARLOWBYTER { bits }
+    }
+    #[doc = "Bits 8:11 - Year high byte. Valid values for Year are 0 to 4095."]
+    #[inline]
+    pub fn year_high_byte(&self) -> YEARHIGHBYTER {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        YEARHIGHBYTER { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Year low byte. Valid values for Year are 0 to 4095."]
+    #[inline]
+    pub fn year_low_byte(&mut self) -> _YEARLOWBYTEW {
+        _YEARLOWBYTEW { w: self }
+    }
+    #[doc = "Bits 8:11 - Year high byte. Valid values for Year are 0 to 4095."]
+    #[inline]
+    pub fn year_high_byte(&mut self) -> _YEARHIGHBYTEW {
+        _YEARHIGHBYTEW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/sysctl.rs b/example-source/msp432p401r/src/sysctl.rs
new file mode 100644
index 0000000..1dc0297
--- /dev/null
+++ b/example-source/msp432p401r/src/sysctl.rs
@@ -0,0 +1,137 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - Reboot Control Register"]
+    pub sys_reboot_ctl: SYS_REBOOT_CTL,
+    #[doc = "0x04 - NMI Control and Status Register"]
+    pub sys_nmi_ctlstat: SYS_NMI_CTLSTAT,
+    #[doc = "0x08 - Watchdog Reset Control Register"]
+    pub sys_wdtreset_ctl: SYS_WDTRESET_CTL,
+    #[doc = "0x0c - Peripheral Halt Control Register"]
+    pub sys_perihalt_ctl: SYS_PERIHALT_CTL,
+    #[doc = "0x10 - SRAM Size Register"]
+    pub sys_sram_size: SYS_SRAM_SIZE,
+    #[doc = "0x14 - SRAM Bank Enable Register"]
+    pub sys_sram_banken: SYS_SRAM_BANKEN,
+    #[doc = "0x18 - SRAM Bank Retention Control Register"]
+    pub sys_sram_bankret: SYS_SRAM_BANKRET,
+    _reserved0: [u8; 4usize],
+    #[doc = "0x20 - Flash Size Register"]
+    pub sys_flash_size: SYS_FLASH_SIZE,
+    _reserved1: [u8; 12usize],
+    #[doc = "0x30 - Digital I/O Glitch Filter Control Register"]
+    pub sys_dio_gltflt_ctl: SYS_DIO_GLTFLT_CTL,
+    _reserved2: [u8; 12usize],
+    #[doc = "0x40 - IP Protected Secure Zone Data Access Unlock Register"]
+    pub sys_secdata_unlock: SYS_SECDATA_UNLOCK,
+    _reserved3: [u8; 4028usize],
+    #[doc = "0x1000 - Master Unlock Register"]
+    pub sys_master_unlock: SYS_MASTER_UNLOCK,
+    #[doc = "0x1004 - Boot Override Request Register"]
+    pub sys_bootover_req: [SYS_BOOTOVER_REQ; 2],
+    #[doc = "0x100c - Boot Override Acknowledge Register"]
+    pub sys_bootover_ack: SYS_BOOTOVER_ACK,
+    #[doc = "0x1010 - Reset Request Register"]
+    pub sys_reset_req: SYS_RESET_REQ,
+    #[doc = "0x1014 - Reset Status and Override Register"]
+    pub sys_reset_statover: SYS_RESET_STATOVER,
+    _reserved4: [u8; 8usize],
+    #[doc = "0x1020 - System Status Register"]
+    pub sys_system_stat: SYS_SYSTEM_STAT,
+}
+#[doc = "Reboot Control Register"]
+pub struct SYS_REBOOT_CTL {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reboot Control Register"]
+pub mod sys_reboot_ctl;
+#[doc = "NMI Control and Status Register"]
+pub struct SYS_NMI_CTLSTAT {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "NMI Control and Status Register"]
+pub mod sys_nmi_ctlstat;
+#[doc = "Watchdog Reset Control Register"]
+pub struct SYS_WDTRESET_CTL {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Watchdog Reset Control Register"]
+pub mod sys_wdtreset_ctl;
+#[doc = "Peripheral Halt Control Register"]
+pub struct SYS_PERIHALT_CTL {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Peripheral Halt Control Register"]
+pub mod sys_perihalt_ctl;
+#[doc = "SRAM Size Register"]
+pub struct SYS_SRAM_SIZE {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "SRAM Size Register"]
+pub mod sys_sram_size;
+#[doc = "SRAM Bank Enable Register"]
+pub struct SYS_SRAM_BANKEN {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "SRAM Bank Enable Register"]
+pub mod sys_sram_banken;
+#[doc = "SRAM Bank Retention Control Register"]
+pub struct SYS_SRAM_BANKRET {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "SRAM Bank Retention Control Register"]
+pub mod sys_sram_bankret;
+#[doc = "Flash Size Register"]
+pub struct SYS_FLASH_SIZE {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Flash Size Register"]
+pub mod sys_flash_size;
+#[doc = "Digital I/O Glitch Filter Control Register"]
+pub struct SYS_DIO_GLTFLT_CTL {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Digital I/O Glitch Filter Control Register"]
+pub mod sys_dio_gltflt_ctl;
+#[doc = "IP Protected Secure Zone Data Access Unlock Register"]
+pub struct SYS_SECDATA_UNLOCK {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "IP Protected Secure Zone Data Access Unlock Register"]
+pub mod sys_secdata_unlock;
+#[doc = "Master Unlock Register"]
+pub struct SYS_MASTER_UNLOCK {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Master Unlock Register"]
+pub mod sys_master_unlock;
+#[doc = "Boot Override Request Register"]
+pub struct SYS_BOOTOVER_REQ {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Boot Override Request Register"]
+pub mod sys_bootover_req;
+#[doc = "Boot Override Acknowledge Register"]
+pub struct SYS_BOOTOVER_ACK {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Boot Override Acknowledge Register"]
+pub mod sys_bootover_ack;
+#[doc = "Reset Request Register"]
+pub struct SYS_RESET_REQ {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reset Request Register"]
+pub mod sys_reset_req;
+#[doc = "Reset Status and Override Register"]
+pub struct SYS_RESET_STATOVER {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reset Status and Override Register"]
+pub mod sys_reset_statover;
+#[doc = "System Status Register"]
+pub struct SYS_SYSTEM_STAT {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "System Status Register"]
+pub mod sys_system_stat;
diff --git a/example-source/msp432p401r/src/sysctl/sys_bootover_ack.rs b/example-source/msp432p401r/src/sysctl/sys_bootover_ack.rs
new file mode 100644
index 0000000..4708a71
--- /dev/null
+++ b/example-source/msp432p401r/src/sysctl/sys_bootover_ack.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SYS_BOOTOVER_ACK {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct REGVALR {
+    bits: u32,
+}
+impl REGVALR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _REGVALW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _REGVALW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Value set by CPU, read/clear by the debugger"]
+    #[inline]
+    pub fn regval(&self) -> REGVALR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        REGVALR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Value set by CPU, read/clear by the debugger"]
+    #[inline]
+    pub fn regval(&mut self) -> _REGVALW {
+        _REGVALW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/sysctl/sys_bootover_req.rs b/example-source/msp432p401r/src/sysctl/sys_bootover_req.rs
new file mode 100644
index 0000000..6d523a6
--- /dev/null
+++ b/example-source/msp432p401r/src/sysctl/sys_bootover_req.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SYS_BOOTOVER_REQ {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct REGVALR {
+    bits: u32,
+}
+impl REGVALR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _REGVALW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _REGVALW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Value set by debugger, read and clear by the CPU"]
+    #[inline]
+    pub fn regval(&self) -> REGVALR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        REGVALR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Value set by debugger, read and clear by the CPU"]
+    #[inline]
+    pub fn regval(&mut self) -> _REGVALW {
+        _REGVALW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/sysctl/sys_dio_gltflt_ctl.rs b/example-source/msp432p401r/src/sysctl/sys_dio_gltflt_ctl.rs
new file mode 100644
index 0000000..01d673d
--- /dev/null
+++ b/example-source/msp432p401r/src/sysctl/sys_dio_gltflt_ctl.rs
@@ -0,0 +1,183 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SYS_DIO_GLTFLT_CTL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `GLTCH_EN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum GLTCH_ENR {
+    #[doc = "Disables glitch filter on the digital I/Os"]
+    GLTCH_EN_0,
+    #[doc = "Enables glitch filter on the digital I/Os"]
+    GLTCH_EN_1,
+}
+impl GLTCH_ENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            GLTCH_ENR::GLTCH_EN_0 => false,
+            GLTCH_ENR::GLTCH_EN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> GLTCH_ENR {
+        match value {
+            false => GLTCH_ENR::GLTCH_EN_0,
+            true => GLTCH_ENR::GLTCH_EN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `GLTCH_EN_0`"]
+    #[inline]
+    pub fn is_gltch_en_0(&self) -> bool {
+        *self == GLTCH_ENR::GLTCH_EN_0
+    }
+    #[doc = "Checks if the value of the field is `GLTCH_EN_1`"]
+    #[inline]
+    pub fn is_gltch_en_1(&self) -> bool {
+        *self == GLTCH_ENR::GLTCH_EN_1
+    }
+}
+#[doc = "Values that can be written to the field `GLTCH_EN`"]
+pub enum GLTCH_ENW {
+    #[doc = "Disables glitch filter on the digital I/Os"]
+    GLTCH_EN_0,
+    #[doc = "Enables glitch filter on the digital I/Os"]
+    GLTCH_EN_1,
+}
+impl GLTCH_ENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            GLTCH_ENW::GLTCH_EN_0 => false,
+            GLTCH_ENW::GLTCH_EN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _GLTCH_ENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _GLTCH_ENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: GLTCH_ENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disables glitch filter on the digital I/Os"]
+    #[inline]
+    pub fn gltch_en_0(self) -> &'a mut W {
+        self.variant(GLTCH_ENW::GLTCH_EN_0)
+    }
+    #[doc = "Enables glitch filter on the digital I/Os"]
+    #[inline]
+    pub fn gltch_en_1(self) -> &'a mut W {
+        self.variant(GLTCH_ENW::GLTCH_EN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Glitch filter enable"]
+    #[inline]
+    pub fn gltch_en(&self) -> GLTCH_ENR {
+        GLTCH_ENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 1 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Glitch filter enable"]
+    #[inline]
+    pub fn gltch_en(&mut self) -> _GLTCH_ENW {
+        _GLTCH_ENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/sysctl/sys_flash_size.rs b/example-source/msp432p401r/src/sysctl/sys_flash_size.rs
new file mode 100644
index 0000000..74a8f86
--- /dev/null
+++ b/example-source/msp432p401r/src/sysctl/sys_flash_size.rs
@@ -0,0 +1,41 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::SYS_FLASH_SIZE {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SIZER {
+    bits: u32,
+}
+impl SIZER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Flash User Region size"]
+    #[inline]
+    pub fn size(&self) -> SIZER {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        SIZER { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/sysctl/sys_master_unlock.rs b/example-source/msp432p401r/src/sysctl/sys_master_unlock.rs
new file mode 100644
index 0000000..cc8f134
--- /dev/null
+++ b/example-source/msp432p401r/src/sysctl/sys_master_unlock.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SYS_MASTER_UNLOCK {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UNLKEYR {
+    bits: u16,
+}
+impl UNLKEYR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UNLKEYW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UNLKEYW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Unlock Key"]
+    #[inline]
+    pub fn unlkey(&self) -> UNLKEYR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        UNLKEYR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Unlock Key"]
+    #[inline]
+    pub fn unlkey(&mut self) -> _UNLKEYW {
+        _UNLKEYW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/sysctl/sys_nmi_ctlstat.rs b/example-source/msp432p401r/src/sysctl/sys_nmi_ctlstat.rs
new file mode 100644
index 0000000..2233758
--- /dev/null
+++ b/example-source/msp432p401r/src/sysctl/sys_nmi_ctlstat.rs
@@ -0,0 +1,827 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SYS_NMI_CTLSTAT {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `CS_SRC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CS_SRCR {
+    #[doc = "Disables CS interrupt as a source of NMI"]
+    CS_SRC_0,
+    #[doc = "Enables CS interrupt as a source of NMI"]
+    CS_SRC_1,
+}
+impl CS_SRCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CS_SRCR::CS_SRC_0 => false,
+            CS_SRCR::CS_SRC_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CS_SRCR {
+        match value {
+            false => CS_SRCR::CS_SRC_0,
+            true => CS_SRCR::CS_SRC_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CS_SRC_0`"]
+    #[inline]
+    pub fn is_cs_src_0(&self) -> bool {
+        *self == CS_SRCR::CS_SRC_0
+    }
+    #[doc = "Checks if the value of the field is `CS_SRC_1`"]
+    #[inline]
+    pub fn is_cs_src_1(&self) -> bool {
+        *self == CS_SRCR::CS_SRC_1
+    }
+}
+#[doc = "Possible values of the field `PSS_SRC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PSS_SRCR {
+    #[doc = "Disables the PSS interrupt as a source of NMI"]
+    PSS_SRC_0,
+    #[doc = "Enables the PSS interrupt as a source of NMI"]
+    PSS_SRC_1,
+}
+impl PSS_SRCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            PSS_SRCR::PSS_SRC_0 => false,
+            PSS_SRCR::PSS_SRC_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> PSS_SRCR {
+        match value {
+            false => PSS_SRCR::PSS_SRC_0,
+            true => PSS_SRCR::PSS_SRC_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `PSS_SRC_0`"]
+    #[inline]
+    pub fn is_pss_src_0(&self) -> bool {
+        *self == PSS_SRCR::PSS_SRC_0
+    }
+    #[doc = "Checks if the value of the field is `PSS_SRC_1`"]
+    #[inline]
+    pub fn is_pss_src_1(&self) -> bool {
+        *self == PSS_SRCR::PSS_SRC_1
+    }
+}
+#[doc = "Possible values of the field `PCM_SRC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PCM_SRCR {
+    #[doc = "Disbles the PCM interrupt as a source of NMI"]
+    PCM_SRC_0,
+    #[doc = "Enables the PCM interrupt as a source of NMI"]
+    PCM_SRC_1,
+}
+impl PCM_SRCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            PCM_SRCR::PCM_SRC_0 => false,
+            PCM_SRCR::PCM_SRC_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> PCM_SRCR {
+        match value {
+            false => PCM_SRCR::PCM_SRC_0,
+            true => PCM_SRCR::PCM_SRC_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `PCM_SRC_0`"]
+    #[inline]
+    pub fn is_pcm_src_0(&self) -> bool {
+        *self == PCM_SRCR::PCM_SRC_0
+    }
+    #[doc = "Checks if the value of the field is `PCM_SRC_1`"]
+    #[inline]
+    pub fn is_pcm_src_1(&self) -> bool {
+        *self == PCM_SRCR::PCM_SRC_1
+    }
+}
+#[doc = "Possible values of the field `PIN_SRC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PIN_SRCR {
+    #[doc = "Configures the RSTn_NMI pin as a source of POR Class Reset"]
+    PIN_SRC_0,
+    #[doc = "Configures the RSTn_NMI pin as a source of NMI"]
+    PIN_SRC_1,
+}
+impl PIN_SRCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            PIN_SRCR::PIN_SRC_0 => false,
+            PIN_SRCR::PIN_SRC_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> PIN_SRCR {
+        match value {
+            false => PIN_SRCR::PIN_SRC_0,
+            true => PIN_SRCR::PIN_SRC_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `PIN_SRC_0`"]
+    #[inline]
+    pub fn is_pin_src_0(&self) -> bool {
+        *self == PIN_SRCR::PIN_SRC_0
+    }
+    #[doc = "Checks if the value of the field is `PIN_SRC_1`"]
+    #[inline]
+    pub fn is_pin_src_1(&self) -> bool {
+        *self == PIN_SRCR::PIN_SRC_1
+    }
+}
+#[doc = "Possible values of the field `CS_FLG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CS_FLGR {
+    #[doc = "indicates CS interrupt was not the source of NMI"]
+    CS_FLG_0,
+    #[doc = "indicates CS interrupt was the source of NMI"]
+    CS_FLG_1,
+}
+impl CS_FLGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CS_FLGR::CS_FLG_0 => false,
+            CS_FLGR::CS_FLG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CS_FLGR {
+        match value {
+            false => CS_FLGR::CS_FLG_0,
+            true => CS_FLGR::CS_FLG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CS_FLG_0`"]
+    #[inline]
+    pub fn is_cs_flg_0(&self) -> bool {
+        *self == CS_FLGR::CS_FLG_0
+    }
+    #[doc = "Checks if the value of the field is `CS_FLG_1`"]
+    #[inline]
+    pub fn is_cs_flg_1(&self) -> bool {
+        *self == CS_FLGR::CS_FLG_1
+    }
+}
+#[doc = "Possible values of the field `PSS_FLG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PSS_FLGR {
+    #[doc = "indicates the PSS interrupt was not the source of NMI"]
+    PSS_FLG_0,
+    #[doc = "indicates the PSS interrupt was the source of NMI"]
+    PSS_FLG_1,
+}
+impl PSS_FLGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            PSS_FLGR::PSS_FLG_0 => false,
+            PSS_FLGR::PSS_FLG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> PSS_FLGR {
+        match value {
+            false => PSS_FLGR::PSS_FLG_0,
+            true => PSS_FLGR::PSS_FLG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `PSS_FLG_0`"]
+    #[inline]
+    pub fn is_pss_flg_0(&self) -> bool {
+        *self == PSS_FLGR::PSS_FLG_0
+    }
+    #[doc = "Checks if the value of the field is `PSS_FLG_1`"]
+    #[inline]
+    pub fn is_pss_flg_1(&self) -> bool {
+        *self == PSS_FLGR::PSS_FLG_1
+    }
+}
+#[doc = "Possible values of the field `PCM_FLG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PCM_FLGR {
+    #[doc = "indicates the PCM interrupt was not the source of NMI"]
+    PCM_FLG_0,
+    #[doc = "indicates the PCM interrupt was the source of NMI"]
+    PCM_FLG_1,
+}
+impl PCM_FLGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            PCM_FLGR::PCM_FLG_0 => false,
+            PCM_FLGR::PCM_FLG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> PCM_FLGR {
+        match value {
+            false => PCM_FLGR::PCM_FLG_0,
+            true => PCM_FLGR::PCM_FLG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `PCM_FLG_0`"]
+    #[inline]
+    pub fn is_pcm_flg_0(&self) -> bool {
+        *self == PCM_FLGR::PCM_FLG_0
+    }
+    #[doc = "Checks if the value of the field is `PCM_FLG_1`"]
+    #[inline]
+    pub fn is_pcm_flg_1(&self) -> bool {
+        *self == PCM_FLGR::PCM_FLG_1
+    }
+}
+#[doc = "Possible values of the field `PIN_FLG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PIN_FLGR {
+    #[doc = "Indicates the RSTn_NMI pin was not the source of NMI"]
+    PIN_FLG_0,
+    #[doc = "Indicates the RSTn_NMI pin was the source of NMI"]
+    PIN_FLG_1,
+}
+impl PIN_FLGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            PIN_FLGR::PIN_FLG_0 => false,
+            PIN_FLGR::PIN_FLG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> PIN_FLGR {
+        match value {
+            false => PIN_FLGR::PIN_FLG_0,
+            true => PIN_FLGR::PIN_FLG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `PIN_FLG_0`"]
+    #[inline]
+    pub fn is_pin_flg_0(&self) -> bool {
+        *self == PIN_FLGR::PIN_FLG_0
+    }
+    #[doc = "Checks if the value of the field is `PIN_FLG_1`"]
+    #[inline]
+    pub fn is_pin_flg_1(&self) -> bool {
+        *self == PIN_FLGR::PIN_FLG_1
+    }
+}
+#[doc = "Values that can be written to the field `CS_SRC`"]
+pub enum CS_SRCW {
+    #[doc = "Disables CS interrupt as a source of NMI"]
+    CS_SRC_0,
+    #[doc = "Enables CS interrupt as a source of NMI"]
+    CS_SRC_1,
+}
+impl CS_SRCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CS_SRCW::CS_SRC_0 => false,
+            CS_SRCW::CS_SRC_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CS_SRCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CS_SRCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CS_SRCW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disables CS interrupt as a source of NMI"]
+    #[inline]
+    pub fn cs_src_0(self) -> &'a mut W {
+        self.variant(CS_SRCW::CS_SRC_0)
+    }
+    #[doc = "Enables CS interrupt as a source of NMI"]
+    #[inline]
+    pub fn cs_src_1(self) -> &'a mut W {
+        self.variant(CS_SRCW::CS_SRC_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `PSS_SRC`"]
+pub enum PSS_SRCW {
+    #[doc = "Disables the PSS interrupt as a source of NMI"]
+    PSS_SRC_0,
+    #[doc = "Enables the PSS interrupt as a source of NMI"]
+    PSS_SRC_1,
+}
+impl PSS_SRCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            PSS_SRCW::PSS_SRC_0 => false,
+            PSS_SRCW::PSS_SRC_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PSS_SRCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PSS_SRCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: PSS_SRCW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disables the PSS interrupt as a source of NMI"]
+    #[inline]
+    pub fn pss_src_0(self) -> &'a mut W {
+        self.variant(PSS_SRCW::PSS_SRC_0)
+    }
+    #[doc = "Enables the PSS interrupt as a source of NMI"]
+    #[inline]
+    pub fn pss_src_1(self) -> &'a mut W {
+        self.variant(PSS_SRCW::PSS_SRC_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `PCM_SRC`"]
+pub enum PCM_SRCW {
+    #[doc = "Disbles the PCM interrupt as a source of NMI"]
+    PCM_SRC_0,
+    #[doc = "Enables the PCM interrupt as a source of NMI"]
+    PCM_SRC_1,
+}
+impl PCM_SRCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            PCM_SRCW::PCM_SRC_0 => false,
+            PCM_SRCW::PCM_SRC_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PCM_SRCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PCM_SRCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: PCM_SRCW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disbles the PCM interrupt as a source of NMI"]
+    #[inline]
+    pub fn pcm_src_0(self) -> &'a mut W {
+        self.variant(PCM_SRCW::PCM_SRC_0)
+    }
+    #[doc = "Enables the PCM interrupt as a source of NMI"]
+    #[inline]
+    pub fn pcm_src_1(self) -> &'a mut W {
+        self.variant(PCM_SRCW::PCM_SRC_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `PIN_SRC`"]
+pub enum PIN_SRCW {
+    #[doc = "Configures the RSTn_NMI pin as a source of POR Class Reset"]
+    PIN_SRC_0,
+    #[doc = "Configures the RSTn_NMI pin as a source of NMI"]
+    PIN_SRC_1,
+}
+impl PIN_SRCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            PIN_SRCW::PIN_SRC_0 => false,
+            PIN_SRCW::PIN_SRC_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PIN_SRCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PIN_SRCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: PIN_SRCW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Configures the RSTn_NMI pin as a source of POR Class Reset"]
+    #[inline]
+    pub fn pin_src_0(self) -> &'a mut W {
+        self.variant(PIN_SRCW::PIN_SRC_0)
+    }
+    #[doc = "Configures the RSTn_NMI pin as a source of NMI"]
+    #[inline]
+    pub fn pin_src_1(self) -> &'a mut W {
+        self.variant(PIN_SRCW::PIN_SRC_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `PIN_FLG`"]
+pub enum PIN_FLGW {
+    #[doc = "Indicates the RSTn_NMI pin was not the source of NMI"]
+    PIN_FLG_0,
+    #[doc = "Indicates the RSTn_NMI pin was the source of NMI"]
+    PIN_FLG_1,
+}
+impl PIN_FLGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            PIN_FLGW::PIN_FLG_0 => false,
+            PIN_FLGW::PIN_FLG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PIN_FLGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PIN_FLGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: PIN_FLGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Indicates the RSTn_NMI pin was not the source of NMI"]
+    #[inline]
+    pub fn pin_flg_0(self) -> &'a mut W {
+        self.variant(PIN_FLGW::PIN_FLG_0)
+    }
+    #[doc = "Indicates the RSTn_NMI pin was the source of NMI"]
+    #[inline]
+    pub fn pin_flg_1(self) -> &'a mut W {
+        self.variant(PIN_FLGW::PIN_FLG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 19;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - CS interrupt as a source of NMI"]
+    #[inline]
+    pub fn cs_src(&self) -> CS_SRCR {
+        CS_SRCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - PSS interrupt as a source of NMI"]
+    #[inline]
+    pub fn pss_src(&self) -> PSS_SRCR {
+        PSS_SRCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - PCM interrupt as a source of NMI"]
+    #[inline]
+    pub fn pcm_src(&self) -> PCM_SRCR {
+        PCM_SRCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 3 - RSTn/NMI pin configuration Note: When the device enters LPM3/LPM4 modes of operation, the functionality selected by this bit is retained. If selected as an NMI, activity on this pin in LPM3/LPM4 wakes the device and processes the interrupt, without causing a POR. If selected as a Reset, activity on this pin in LPM3/LPM4 causes a device-level POR When the device enters LPM3.5/LPM4.5 modes of operation, this bit is always cleared to 0. In other words, the RSTn/NMI pin always assumes a reset functionality in LPM3.5/LPM4.5 modes."]
+    #[inline]
+    pub fn pin_src(&self) -> PIN_SRCR {
+        PIN_SRCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 16 - CS interrupt was the source of NMI"]
+    #[inline]
+    pub fn cs_flg(&self) -> CS_FLGR {
+        CS_FLGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 17 - PSS interrupt was the source of NMI"]
+    #[inline]
+    pub fn pss_flg(&self) -> PSS_FLGR {
+        PSS_FLGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 17;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 18 - PCM interrupt was the source of NMI"]
+    #[inline]
+    pub fn pcm_flg(&self) -> PCM_FLGR {
+        PCM_FLGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 18;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 19 - RSTn/NMI pin was the source of NMI"]
+    #[inline]
+    pub fn pin_flg(&self) -> PIN_FLGR {
+        PIN_FLGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 19;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 7 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - CS interrupt as a source of NMI"]
+    #[inline]
+    pub fn cs_src(&mut self) -> _CS_SRCW {
+        _CS_SRCW { w: self }
+    }
+    #[doc = "Bit 1 - PSS interrupt as a source of NMI"]
+    #[inline]
+    pub fn pss_src(&mut self) -> _PSS_SRCW {
+        _PSS_SRCW { w: self }
+    }
+    #[doc = "Bit 2 - PCM interrupt as a source of NMI"]
+    #[inline]
+    pub fn pcm_src(&mut self) -> _PCM_SRCW {
+        _PCM_SRCW { w: self }
+    }
+    #[doc = "Bit 3 - RSTn/NMI pin configuration Note: When the device enters LPM3/LPM4 modes of operation, the functionality selected by this bit is retained. If selected as an NMI, activity on this pin in LPM3/LPM4 wakes the device and processes the interrupt, without causing a POR. If selected as a Reset, activity on this pin in LPM3/LPM4 causes a device-level POR When the device enters LPM3.5/LPM4.5 modes of operation, this bit is always cleared to 0. In other words, the RSTn/NMI pin always assumes a reset functionality in LPM3.5/LPM4.5 modes."]
+    #[inline]
+    pub fn pin_src(&mut self) -> _PIN_SRCW {
+        _PIN_SRCW { w: self }
+    }
+    #[doc = "Bit 19 - RSTn/NMI pin was the source of NMI"]
+    #[inline]
+    pub fn pin_flg(&mut self) -> _PIN_FLGW {
+        _PIN_FLGW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/sysctl/sys_perihalt_ctl.rs b/example-source/msp432p401r/src/sysctl/sys_perihalt_ctl.rs
new file mode 100644
index 0000000..53daea6
--- /dev/null
+++ b/example-source/msp432p401r/src/sysctl/sys_perihalt_ctl.rs
@@ -0,0 +1,1968 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SYS_PERIHALT_CTL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `HALT_T16_0`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HALT_T16_0R {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_T16_0_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_T16_0_1,
+}
+impl HALT_T16_0R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            HALT_T16_0R::HALT_T16_0_0 => false,
+            HALT_T16_0R::HALT_T16_0_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> HALT_T16_0R {
+        match value {
+            false => HALT_T16_0R::HALT_T16_0_0,
+            true => HALT_T16_0R::HALT_T16_0_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `HALT_T16_0_0`"]
+    #[inline]
+    pub fn is_halt_t16_0_0(&self) -> bool {
+        *self == HALT_T16_0R::HALT_T16_0_0
+    }
+    #[doc = "Checks if the value of the field is `HALT_T16_0_1`"]
+    #[inline]
+    pub fn is_halt_t16_0_1(&self) -> bool {
+        *self == HALT_T16_0R::HALT_T16_0_1
+    }
+}
+#[doc = "Possible values of the field `HALT_T16_1`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HALT_T16_1R {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_T16_1_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_T16_1_1,
+}
+impl HALT_T16_1R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            HALT_T16_1R::HALT_T16_1_0 => false,
+            HALT_T16_1R::HALT_T16_1_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> HALT_T16_1R {
+        match value {
+            false => HALT_T16_1R::HALT_T16_1_0,
+            true => HALT_T16_1R::HALT_T16_1_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `HALT_T16_1_0`"]
+    #[inline]
+    pub fn is_halt_t16_1_0(&self) -> bool {
+        *self == HALT_T16_1R::HALT_T16_1_0
+    }
+    #[doc = "Checks if the value of the field is `HALT_T16_1_1`"]
+    #[inline]
+    pub fn is_halt_t16_1_1(&self) -> bool {
+        *self == HALT_T16_1R::HALT_T16_1_1
+    }
+}
+#[doc = "Possible values of the field `HALT_T16_2`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HALT_T16_2R {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_T16_2_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_T16_2_1,
+}
+impl HALT_T16_2R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            HALT_T16_2R::HALT_T16_2_0 => false,
+            HALT_T16_2R::HALT_T16_2_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> HALT_T16_2R {
+        match value {
+            false => HALT_T16_2R::HALT_T16_2_0,
+            true => HALT_T16_2R::HALT_T16_2_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `HALT_T16_2_0`"]
+    #[inline]
+    pub fn is_halt_t16_2_0(&self) -> bool {
+        *self == HALT_T16_2R::HALT_T16_2_0
+    }
+    #[doc = "Checks if the value of the field is `HALT_T16_2_1`"]
+    #[inline]
+    pub fn is_halt_t16_2_1(&self) -> bool {
+        *self == HALT_T16_2R::HALT_T16_2_1
+    }
+}
+#[doc = "Possible values of the field `HALT_T16_3`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HALT_T16_3R {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_T16_3_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_T16_3_1,
+}
+impl HALT_T16_3R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            HALT_T16_3R::HALT_T16_3_0 => false,
+            HALT_T16_3R::HALT_T16_3_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> HALT_T16_3R {
+        match value {
+            false => HALT_T16_3R::HALT_T16_3_0,
+            true => HALT_T16_3R::HALT_T16_3_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `HALT_T16_3_0`"]
+    #[inline]
+    pub fn is_halt_t16_3_0(&self) -> bool {
+        *self == HALT_T16_3R::HALT_T16_3_0
+    }
+    #[doc = "Checks if the value of the field is `HALT_T16_3_1`"]
+    #[inline]
+    pub fn is_halt_t16_3_1(&self) -> bool {
+        *self == HALT_T16_3R::HALT_T16_3_1
+    }
+}
+#[doc = "Possible values of the field `HALT_T32_0`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HALT_T32_0R {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_T32_0_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_T32_0_1,
+}
+impl HALT_T32_0R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            HALT_T32_0R::HALT_T32_0_0 => false,
+            HALT_T32_0R::HALT_T32_0_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> HALT_T32_0R {
+        match value {
+            false => HALT_T32_0R::HALT_T32_0_0,
+            true => HALT_T32_0R::HALT_T32_0_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `HALT_T32_0_0`"]
+    #[inline]
+    pub fn is_halt_t32_0_0(&self) -> bool {
+        *self == HALT_T32_0R::HALT_T32_0_0
+    }
+    #[doc = "Checks if the value of the field is `HALT_T32_0_1`"]
+    #[inline]
+    pub fn is_halt_t32_0_1(&self) -> bool {
+        *self == HALT_T32_0R::HALT_T32_0_1
+    }
+}
+#[doc = "Possible values of the field `HALT_eUA0`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HALT_EUA0R {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_EUA0_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_EUA0_1,
+}
+impl HALT_EUA0R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            HALT_EUA0R::HALT_EUA0_0 => false,
+            HALT_EUA0R::HALT_EUA0_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> HALT_EUA0R {
+        match value {
+            false => HALT_EUA0R::HALT_EUA0_0,
+            true => HALT_EUA0R::HALT_EUA0_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `HALT_EUA0_0`"]
+    #[inline]
+    pub fn is_halt_e_ua0_0(&self) -> bool {
+        *self == HALT_EUA0R::HALT_EUA0_0
+    }
+    #[doc = "Checks if the value of the field is `HALT_EUA0_1`"]
+    #[inline]
+    pub fn is_halt_e_ua0_1(&self) -> bool {
+        *self == HALT_EUA0R::HALT_EUA0_1
+    }
+}
+#[doc = "Possible values of the field `HALT_eUA1`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HALT_EUA1R {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_EUA1_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_EUA1_1,
+}
+impl HALT_EUA1R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            HALT_EUA1R::HALT_EUA1_0 => false,
+            HALT_EUA1R::HALT_EUA1_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> HALT_EUA1R {
+        match value {
+            false => HALT_EUA1R::HALT_EUA1_0,
+            true => HALT_EUA1R::HALT_EUA1_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `HALT_EUA1_0`"]
+    #[inline]
+    pub fn is_halt_e_ua1_0(&self) -> bool {
+        *self == HALT_EUA1R::HALT_EUA1_0
+    }
+    #[doc = "Checks if the value of the field is `HALT_EUA1_1`"]
+    #[inline]
+    pub fn is_halt_e_ua1_1(&self) -> bool {
+        *self == HALT_EUA1R::HALT_EUA1_1
+    }
+}
+#[doc = "Possible values of the field `HALT_eUA2`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HALT_EUA2R {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_EUA2_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_EUA2_1,
+}
+impl HALT_EUA2R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            HALT_EUA2R::HALT_EUA2_0 => false,
+            HALT_EUA2R::HALT_EUA2_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> HALT_EUA2R {
+        match value {
+            false => HALT_EUA2R::HALT_EUA2_0,
+            true => HALT_EUA2R::HALT_EUA2_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `HALT_EUA2_0`"]
+    #[inline]
+    pub fn is_halt_e_ua2_0(&self) -> bool {
+        *self == HALT_EUA2R::HALT_EUA2_0
+    }
+    #[doc = "Checks if the value of the field is `HALT_EUA2_1`"]
+    #[inline]
+    pub fn is_halt_e_ua2_1(&self) -> bool {
+        *self == HALT_EUA2R::HALT_EUA2_1
+    }
+}
+#[doc = "Possible values of the field `HALT_eUA3`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HALT_EUA3R {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_EUA3_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_EUA3_1,
+}
+impl HALT_EUA3R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            HALT_EUA3R::HALT_EUA3_0 => false,
+            HALT_EUA3R::HALT_EUA3_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> HALT_EUA3R {
+        match value {
+            false => HALT_EUA3R::HALT_EUA3_0,
+            true => HALT_EUA3R::HALT_EUA3_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `HALT_EUA3_0`"]
+    #[inline]
+    pub fn is_halt_e_ua3_0(&self) -> bool {
+        *self == HALT_EUA3R::HALT_EUA3_0
+    }
+    #[doc = "Checks if the value of the field is `HALT_EUA3_1`"]
+    #[inline]
+    pub fn is_halt_e_ua3_1(&self) -> bool {
+        *self == HALT_EUA3R::HALT_EUA3_1
+    }
+}
+#[doc = "Possible values of the field `HALT_eUB0`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HALT_EUB0R {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_EUB0_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_EUB0_1,
+}
+impl HALT_EUB0R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            HALT_EUB0R::HALT_EUB0_0 => false,
+            HALT_EUB0R::HALT_EUB0_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> HALT_EUB0R {
+        match value {
+            false => HALT_EUB0R::HALT_EUB0_0,
+            true => HALT_EUB0R::HALT_EUB0_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `HALT_EUB0_0`"]
+    #[inline]
+    pub fn is_halt_e_ub0_0(&self) -> bool {
+        *self == HALT_EUB0R::HALT_EUB0_0
+    }
+    #[doc = "Checks if the value of the field is `HALT_EUB0_1`"]
+    #[inline]
+    pub fn is_halt_e_ub0_1(&self) -> bool {
+        *self == HALT_EUB0R::HALT_EUB0_1
+    }
+}
+#[doc = "Possible values of the field `HALT_eUB1`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HALT_EUB1R {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_EUB1_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_EUB1_1,
+}
+impl HALT_EUB1R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            HALT_EUB1R::HALT_EUB1_0 => false,
+            HALT_EUB1R::HALT_EUB1_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> HALT_EUB1R {
+        match value {
+            false => HALT_EUB1R::HALT_EUB1_0,
+            true => HALT_EUB1R::HALT_EUB1_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `HALT_EUB1_0`"]
+    #[inline]
+    pub fn is_halt_e_ub1_0(&self) -> bool {
+        *self == HALT_EUB1R::HALT_EUB1_0
+    }
+    #[doc = "Checks if the value of the field is `HALT_EUB1_1`"]
+    #[inline]
+    pub fn is_halt_e_ub1_1(&self) -> bool {
+        *self == HALT_EUB1R::HALT_EUB1_1
+    }
+}
+#[doc = "Possible values of the field `HALT_eUB2`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HALT_EUB2R {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_EUB2_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_EUB2_1,
+}
+impl HALT_EUB2R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            HALT_EUB2R::HALT_EUB2_0 => false,
+            HALT_EUB2R::HALT_EUB2_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> HALT_EUB2R {
+        match value {
+            false => HALT_EUB2R::HALT_EUB2_0,
+            true => HALT_EUB2R::HALT_EUB2_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `HALT_EUB2_0`"]
+    #[inline]
+    pub fn is_halt_e_ub2_0(&self) -> bool {
+        *self == HALT_EUB2R::HALT_EUB2_0
+    }
+    #[doc = "Checks if the value of the field is `HALT_EUB2_1`"]
+    #[inline]
+    pub fn is_halt_e_ub2_1(&self) -> bool {
+        *self == HALT_EUB2R::HALT_EUB2_1
+    }
+}
+#[doc = "Possible values of the field `HALT_eUB3`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HALT_EUB3R {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_EUB3_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_EUB3_1,
+}
+impl HALT_EUB3R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            HALT_EUB3R::HALT_EUB3_0 => false,
+            HALT_EUB3R::HALT_EUB3_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> HALT_EUB3R {
+        match value {
+            false => HALT_EUB3R::HALT_EUB3_0,
+            true => HALT_EUB3R::HALT_EUB3_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `HALT_EUB3_0`"]
+    #[inline]
+    pub fn is_halt_e_ub3_0(&self) -> bool {
+        *self == HALT_EUB3R::HALT_EUB3_0
+    }
+    #[doc = "Checks if the value of the field is `HALT_EUB3_1`"]
+    #[inline]
+    pub fn is_halt_e_ub3_1(&self) -> bool {
+        *self == HALT_EUB3R::HALT_EUB3_1
+    }
+}
+#[doc = "Possible values of the field `HALT_ADC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HALT_ADCR {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_ADC_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_ADC_1,
+}
+impl HALT_ADCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            HALT_ADCR::HALT_ADC_0 => false,
+            HALT_ADCR::HALT_ADC_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> HALT_ADCR {
+        match value {
+            false => HALT_ADCR::HALT_ADC_0,
+            true => HALT_ADCR::HALT_ADC_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `HALT_ADC_0`"]
+    #[inline]
+    pub fn is_halt_adc_0(&self) -> bool {
+        *self == HALT_ADCR::HALT_ADC_0
+    }
+    #[doc = "Checks if the value of the field is `HALT_ADC_1`"]
+    #[inline]
+    pub fn is_halt_adc_1(&self) -> bool {
+        *self == HALT_ADCR::HALT_ADC_1
+    }
+}
+#[doc = "Possible values of the field `HALT_WDT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HALT_WDTR {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_WDT_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_WDT_1,
+}
+impl HALT_WDTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            HALT_WDTR::HALT_WDT_0 => false,
+            HALT_WDTR::HALT_WDT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> HALT_WDTR {
+        match value {
+            false => HALT_WDTR::HALT_WDT_0,
+            true => HALT_WDTR::HALT_WDT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `HALT_WDT_0`"]
+    #[inline]
+    pub fn is_halt_wdt_0(&self) -> bool {
+        *self == HALT_WDTR::HALT_WDT_0
+    }
+    #[doc = "Checks if the value of the field is `HALT_WDT_1`"]
+    #[inline]
+    pub fn is_halt_wdt_1(&self) -> bool {
+        *self == HALT_WDTR::HALT_WDT_1
+    }
+}
+#[doc = "Possible values of the field `HALT_DMA`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HALT_DMAR {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_DMA_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_DMA_1,
+}
+impl HALT_DMAR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            HALT_DMAR::HALT_DMA_0 => false,
+            HALT_DMAR::HALT_DMA_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> HALT_DMAR {
+        match value {
+            false => HALT_DMAR::HALT_DMA_0,
+            true => HALT_DMAR::HALT_DMA_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `HALT_DMA_0`"]
+    #[inline]
+    pub fn is_halt_dma_0(&self) -> bool {
+        *self == HALT_DMAR::HALT_DMA_0
+    }
+    #[doc = "Checks if the value of the field is `HALT_DMA_1`"]
+    #[inline]
+    pub fn is_halt_dma_1(&self) -> bool {
+        *self == HALT_DMAR::HALT_DMA_1
+    }
+}
+#[doc = "Values that can be written to the field `HALT_T16_0`"]
+pub enum HALT_T16_0W {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_T16_0_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_T16_0_1,
+}
+impl HALT_T16_0W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            HALT_T16_0W::HALT_T16_0_0 => false,
+            HALT_T16_0W::HALT_T16_0_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _HALT_T16_0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _HALT_T16_0W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: HALT_T16_0W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "IP operation unaffected when CPU is halted"]
+    #[inline]
+    pub fn halt_t16_0_0(self) -> &'a mut W {
+        self.variant(HALT_T16_0W::HALT_T16_0_0)
+    }
+    #[doc = "freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_t16_0_1(self) -> &'a mut W {
+        self.variant(HALT_T16_0W::HALT_T16_0_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `HALT_T16_1`"]
+pub enum HALT_T16_1W {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_T16_1_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_T16_1_1,
+}
+impl HALT_T16_1W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            HALT_T16_1W::HALT_T16_1_0 => false,
+            HALT_T16_1W::HALT_T16_1_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _HALT_T16_1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _HALT_T16_1W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: HALT_T16_1W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "IP operation unaffected when CPU is halted"]
+    #[inline]
+    pub fn halt_t16_1_0(self) -> &'a mut W {
+        self.variant(HALT_T16_1W::HALT_T16_1_0)
+    }
+    #[doc = "freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_t16_1_1(self) -> &'a mut W {
+        self.variant(HALT_T16_1W::HALT_T16_1_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `HALT_T16_2`"]
+pub enum HALT_T16_2W {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_T16_2_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_T16_2_1,
+}
+impl HALT_T16_2W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            HALT_T16_2W::HALT_T16_2_0 => false,
+            HALT_T16_2W::HALT_T16_2_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _HALT_T16_2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _HALT_T16_2W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: HALT_T16_2W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "IP operation unaffected when CPU is halted"]
+    #[inline]
+    pub fn halt_t16_2_0(self) -> &'a mut W {
+        self.variant(HALT_T16_2W::HALT_T16_2_0)
+    }
+    #[doc = "freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_t16_2_1(self) -> &'a mut W {
+        self.variant(HALT_T16_2W::HALT_T16_2_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `HALT_T16_3`"]
+pub enum HALT_T16_3W {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_T16_3_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_T16_3_1,
+}
+impl HALT_T16_3W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            HALT_T16_3W::HALT_T16_3_0 => false,
+            HALT_T16_3W::HALT_T16_3_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _HALT_T16_3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _HALT_T16_3W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: HALT_T16_3W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "IP operation unaffected when CPU is halted"]
+    #[inline]
+    pub fn halt_t16_3_0(self) -> &'a mut W {
+        self.variant(HALT_T16_3W::HALT_T16_3_0)
+    }
+    #[doc = "freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_t16_3_1(self) -> &'a mut W {
+        self.variant(HALT_T16_3W::HALT_T16_3_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `HALT_T32_0`"]
+pub enum HALT_T32_0W {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_T32_0_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_T32_0_1,
+}
+impl HALT_T32_0W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            HALT_T32_0W::HALT_T32_0_0 => false,
+            HALT_T32_0W::HALT_T32_0_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _HALT_T32_0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _HALT_T32_0W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: HALT_T32_0W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "IP operation unaffected when CPU is halted"]
+    #[inline]
+    pub fn halt_t32_0_0(self) -> &'a mut W {
+        self.variant(HALT_T32_0W::HALT_T32_0_0)
+    }
+    #[doc = "freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_t32_0_1(self) -> &'a mut W {
+        self.variant(HALT_T32_0W::HALT_T32_0_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `HALT_eUA0`"]
+pub enum HALT_EUA0W {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_EUA0_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_EUA0_1,
+}
+impl HALT_EUA0W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            HALT_EUA0W::HALT_EUA0_0 => false,
+            HALT_EUA0W::HALT_EUA0_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _HALT_EUA0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _HALT_EUA0W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: HALT_EUA0W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "IP operation unaffected when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ua0_0(self) -> &'a mut W {
+        self.variant(HALT_EUA0W::HALT_EUA0_0)
+    }
+    #[doc = "freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ua0_1(self) -> &'a mut W {
+        self.variant(HALT_EUA0W::HALT_EUA0_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `HALT_eUA1`"]
+pub enum HALT_EUA1W {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_EUA1_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_EUA1_1,
+}
+impl HALT_EUA1W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            HALT_EUA1W::HALT_EUA1_0 => false,
+            HALT_EUA1W::HALT_EUA1_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _HALT_EUA1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _HALT_EUA1W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: HALT_EUA1W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "IP operation unaffected when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ua1_0(self) -> &'a mut W {
+        self.variant(HALT_EUA1W::HALT_EUA1_0)
+    }
+    #[doc = "freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ua1_1(self) -> &'a mut W {
+        self.variant(HALT_EUA1W::HALT_EUA1_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `HALT_eUA2`"]
+pub enum HALT_EUA2W {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_EUA2_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_EUA2_1,
+}
+impl HALT_EUA2W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            HALT_EUA2W::HALT_EUA2_0 => false,
+            HALT_EUA2W::HALT_EUA2_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _HALT_EUA2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _HALT_EUA2W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: HALT_EUA2W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "IP operation unaffected when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ua2_0(self) -> &'a mut W {
+        self.variant(HALT_EUA2W::HALT_EUA2_0)
+    }
+    #[doc = "freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ua2_1(self) -> &'a mut W {
+        self.variant(HALT_EUA2W::HALT_EUA2_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `HALT_eUA3`"]
+pub enum HALT_EUA3W {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_EUA3_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_EUA3_1,
+}
+impl HALT_EUA3W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            HALT_EUA3W::HALT_EUA3_0 => false,
+            HALT_EUA3W::HALT_EUA3_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _HALT_EUA3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _HALT_EUA3W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: HALT_EUA3W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "IP operation unaffected when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ua3_0(self) -> &'a mut W {
+        self.variant(HALT_EUA3W::HALT_EUA3_0)
+    }
+    #[doc = "freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ua3_1(self) -> &'a mut W {
+        self.variant(HALT_EUA3W::HALT_EUA3_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `HALT_eUB0`"]
+pub enum HALT_EUB0W {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_EUB0_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_EUB0_1,
+}
+impl HALT_EUB0W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            HALT_EUB0W::HALT_EUB0_0 => false,
+            HALT_EUB0W::HALT_EUB0_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _HALT_EUB0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _HALT_EUB0W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: HALT_EUB0W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "IP operation unaffected when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ub0_0(self) -> &'a mut W {
+        self.variant(HALT_EUB0W::HALT_EUB0_0)
+    }
+    #[doc = "freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ub0_1(self) -> &'a mut W {
+        self.variant(HALT_EUB0W::HALT_EUB0_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `HALT_eUB1`"]
+pub enum HALT_EUB1W {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_EUB1_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_EUB1_1,
+}
+impl HALT_EUB1W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            HALT_EUB1W::HALT_EUB1_0 => false,
+            HALT_EUB1W::HALT_EUB1_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _HALT_EUB1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _HALT_EUB1W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: HALT_EUB1W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "IP operation unaffected when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ub1_0(self) -> &'a mut W {
+        self.variant(HALT_EUB1W::HALT_EUB1_0)
+    }
+    #[doc = "freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ub1_1(self) -> &'a mut W {
+        self.variant(HALT_EUB1W::HALT_EUB1_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `HALT_eUB2`"]
+pub enum HALT_EUB2W {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_EUB2_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_EUB2_1,
+}
+impl HALT_EUB2W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            HALT_EUB2W::HALT_EUB2_0 => false,
+            HALT_EUB2W::HALT_EUB2_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _HALT_EUB2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _HALT_EUB2W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: HALT_EUB2W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "IP operation unaffected when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ub2_0(self) -> &'a mut W {
+        self.variant(HALT_EUB2W::HALT_EUB2_0)
+    }
+    #[doc = "freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ub2_1(self) -> &'a mut W {
+        self.variant(HALT_EUB2W::HALT_EUB2_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `HALT_eUB3`"]
+pub enum HALT_EUB3W {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_EUB3_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_EUB3_1,
+}
+impl HALT_EUB3W {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            HALT_EUB3W::HALT_EUB3_0 => false,
+            HALT_EUB3W::HALT_EUB3_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _HALT_EUB3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _HALT_EUB3W<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: HALT_EUB3W) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "IP operation unaffected when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ub3_0(self) -> &'a mut W {
+        self.variant(HALT_EUB3W::HALT_EUB3_0)
+    }
+    #[doc = "freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ub3_1(self) -> &'a mut W {
+        self.variant(HALT_EUB3W::HALT_EUB3_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `HALT_ADC`"]
+pub enum HALT_ADCW {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_ADC_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_ADC_1,
+}
+impl HALT_ADCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            HALT_ADCW::HALT_ADC_0 => false,
+            HALT_ADCW::HALT_ADC_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _HALT_ADCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _HALT_ADCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: HALT_ADCW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "IP operation unaffected when CPU is halted"]
+    #[inline]
+    pub fn halt_adc_0(self) -> &'a mut W {
+        self.variant(HALT_ADCW::HALT_ADC_0)
+    }
+    #[doc = "freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_adc_1(self) -> &'a mut W {
+        self.variant(HALT_ADCW::HALT_ADC_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 13;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `HALT_WDT`"]
+pub enum HALT_WDTW {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_WDT_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_WDT_1,
+}
+impl HALT_WDTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            HALT_WDTW::HALT_WDT_0 => false,
+            HALT_WDTW::HALT_WDT_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _HALT_WDTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _HALT_WDTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: HALT_WDTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "IP operation unaffected when CPU is halted"]
+    #[inline]
+    pub fn halt_wdt_0(self) -> &'a mut W {
+        self.variant(HALT_WDTW::HALT_WDT_0)
+    }
+    #[doc = "freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_wdt_1(self) -> &'a mut W {
+        self.variant(HALT_WDTW::HALT_WDT_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `HALT_DMA`"]
+pub enum HALT_DMAW {
+    #[doc = "IP operation unaffected when CPU is halted"]
+    HALT_DMA_0,
+    #[doc = "freezes IP operation when CPU is halted"]
+    HALT_DMA_1,
+}
+impl HALT_DMAW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            HALT_DMAW::HALT_DMA_0 => false,
+            HALT_DMAW::HALT_DMA_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _HALT_DMAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _HALT_DMAW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: HALT_DMAW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "IP operation unaffected when CPU is halted"]
+    #[inline]
+    pub fn halt_dma_0(self) -> &'a mut W {
+        self.variant(HALT_DMAW::HALT_DMA_0)
+    }
+    #[doc = "freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_dma_1(self) -> &'a mut W {
+        self.variant(HALT_DMAW::HALT_DMA_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_t16_0(&self) -> HALT_T16_0R {
+        HALT_T16_0R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_t16_1(&self) -> HALT_T16_1R {
+        HALT_T16_1R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_t16_2(&self) -> HALT_T16_2R {
+        HALT_T16_2R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 3 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_t16_3(&self) -> HALT_T16_3R {
+        HALT_T16_3R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 4 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_t32_0(&self) -> HALT_T32_0R {
+        HALT_T32_0R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 5 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ua0(&self) -> HALT_EUA0R {
+        HALT_EUA0R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 6 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ua1(&self) -> HALT_EUA1R {
+        HALT_EUA1R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 7 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ua2(&self) -> HALT_EUA2R {
+        HALT_EUA2R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 8 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ua3(&self) -> HALT_EUA3R {
+        HALT_EUA3R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 9 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ub0(&self) -> HALT_EUB0R {
+        HALT_EUB0R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 10 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ub1(&self) -> HALT_EUB1R {
+        HALT_EUB1R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 11 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ub2(&self) -> HALT_EUB2R {
+        HALT_EUB2R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 12 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ub3(&self) -> HALT_EUB3R {
+        HALT_EUB3R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 13 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_adc(&self) -> HALT_ADCR {
+        HALT_ADCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 14 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_wdt(&self) -> HALT_WDTR {
+        HALT_WDTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 15 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_dma(&self) -> HALT_DMAR {
+        HALT_DMAR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 16384 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_t16_0(&mut self) -> _HALT_T16_0W {
+        _HALT_T16_0W { w: self }
+    }
+    #[doc = "Bit 1 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_t16_1(&mut self) -> _HALT_T16_1W {
+        _HALT_T16_1W { w: self }
+    }
+    #[doc = "Bit 2 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_t16_2(&mut self) -> _HALT_T16_2W {
+        _HALT_T16_2W { w: self }
+    }
+    #[doc = "Bit 3 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_t16_3(&mut self) -> _HALT_T16_3W {
+        _HALT_T16_3W { w: self }
+    }
+    #[doc = "Bit 4 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_t32_0(&mut self) -> _HALT_T32_0W {
+        _HALT_T32_0W { w: self }
+    }
+    #[doc = "Bit 5 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ua0(&mut self) -> _HALT_EUA0W {
+        _HALT_EUA0W { w: self }
+    }
+    #[doc = "Bit 6 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ua1(&mut self) -> _HALT_EUA1W {
+        _HALT_EUA1W { w: self }
+    }
+    #[doc = "Bit 7 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ua2(&mut self) -> _HALT_EUA2W {
+        _HALT_EUA2W { w: self }
+    }
+    #[doc = "Bit 8 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ua3(&mut self) -> _HALT_EUA3W {
+        _HALT_EUA3W { w: self }
+    }
+    #[doc = "Bit 9 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ub0(&mut self) -> _HALT_EUB0W {
+        _HALT_EUB0W { w: self }
+    }
+    #[doc = "Bit 10 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ub1(&mut self) -> _HALT_EUB1W {
+        _HALT_EUB1W { w: self }
+    }
+    #[doc = "Bit 11 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ub2(&mut self) -> _HALT_EUB2W {
+        _HALT_EUB2W { w: self }
+    }
+    #[doc = "Bit 12 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_e_ub3(&mut self) -> _HALT_EUB3W {
+        _HALT_EUB3W { w: self }
+    }
+    #[doc = "Bit 13 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_adc(&mut self) -> _HALT_ADCW {
+        _HALT_ADCW { w: self }
+    }
+    #[doc = "Bit 14 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_wdt(&mut self) -> _HALT_WDTW {
+        _HALT_WDTW { w: self }
+    }
+    #[doc = "Bit 15 - Freezes IP operation when CPU is halted"]
+    #[inline]
+    pub fn halt_dma(&mut self) -> _HALT_DMAW {
+        _HALT_DMAW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/sysctl/sys_reboot_ctl.rs b/example-source/msp432p401r/src/sysctl/sys_reboot_ctl.rs
new file mode 100644
index 0000000..dbb646a
--- /dev/null
+++ b/example-source/msp432p401r/src/sysctl/sys_reboot_ctl.rs
@@ -0,0 +1,143 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SYS_REBOOT_CTL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct REBOOTR {
+    bits: bool,
+}
+impl REBOOTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Proxy"]
+pub struct _REBOOTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _REBOOTW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _WKEYW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _WKEYW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Write 1 initiates a Reboot of the device"]
+    #[inline]
+    pub fn reboot(&self) -> REBOOTR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        REBOOTR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 254 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Write 1 initiates a Reboot of the device"]
+    #[inline]
+    pub fn reboot(&mut self) -> _REBOOTW {
+        _REBOOTW { w: self }
+    }
+    #[doc = "Bits 8:15 - Key to enable writes to bit 0"]
+    #[inline]
+    pub fn wkey(&mut self) -> _WKEYW {
+        _WKEYW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/sysctl/sys_reset_req.rs b/example-source/msp432p401r/src/sysctl/sys_reset_req.rs
new file mode 100644
index 0000000..eac6e00
--- /dev/null
+++ b/example-source/msp432p401r/src/sysctl/sys_reset_req.rs
@@ -0,0 +1,140 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SYS_RESET_REQ {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PORW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PORW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _REBOOTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _REBOOTW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _WKEYW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _WKEYW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Generate POR"]
+    #[inline]
+    pub fn por(&mut self) -> _PORW {
+        _PORW { w: self }
+    }
+    #[doc = "Bit 1 - Generate Reboot_Reset"]
+    #[inline]
+    pub fn reboot(&mut self) -> _REBOOTW {
+        _REBOOTW { w: self }
+    }
+    #[doc = "Bits 8:15 - Write key"]
+    #[inline]
+    pub fn wkey(&mut self) -> _WKEYW {
+        _WKEYW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/sysctl/sys_reset_statover.rs b/example-source/msp432p401r/src/sysctl/sys_reset_statover.rs
new file mode 100644
index 0000000..28c8c1c
--- /dev/null
+++ b/example-source/msp432p401r/src/sysctl/sys_reset_statover.rs
@@ -0,0 +1,334 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SYS_RESET_STATOVER {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SOFTR {
+    bits: bool,
+}
+impl SOFTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct HARDR {
+    bits: bool,
+}
+impl HARDR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct REBOOTR {
+    bits: bool,
+}
+impl REBOOTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SOFT_OVERR {
+    bits: bool,
+}
+impl SOFT_OVERR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct HARD_OVERR {
+    bits: bool,
+}
+impl HARD_OVERR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct RBT_OVERR {
+    bits: bool,
+}
+impl RBT_OVERR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SOFT_OVERW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SOFT_OVERW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _HARD_OVERW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _HARD_OVERW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RBT_OVERW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RBT_OVERW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Indicates if SOFT Reset is active"]
+    #[inline]
+    pub fn soft(&self) -> SOFTR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SOFTR { bits }
+    }
+    #[doc = "Bit 1 - Indicates if HARD Reset is active"]
+    #[inline]
+    pub fn hard(&self) -> HARDR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        HARDR { bits }
+    }
+    #[doc = "Bit 2 - Indicates if Reboot Reset is active"]
+    #[inline]
+    pub fn reboot(&self) -> REBOOTR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        REBOOTR { bits }
+    }
+    #[doc = "Bit 8 - SOFT_Reset overwrite request"]
+    #[inline]
+    pub fn soft_over(&self) -> SOFT_OVERR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SOFT_OVERR { bits }
+    }
+    #[doc = "Bit 9 - HARD_Reset overwrite request"]
+    #[inline]
+    pub fn hard_over(&self) -> HARD_OVERR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        HARD_OVERR { bits }
+    }
+    #[doc = "Bit 10 - Reboot Reset overwrite request"]
+    #[inline]
+    pub fn rbt_over(&self) -> RBT_OVERR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        RBT_OVERR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 8 - SOFT_Reset overwrite request"]
+    #[inline]
+    pub fn soft_over(&mut self) -> _SOFT_OVERW {
+        _SOFT_OVERW { w: self }
+    }
+    #[doc = "Bit 9 - HARD_Reset overwrite request"]
+    #[inline]
+    pub fn hard_over(&mut self) -> _HARD_OVERW {
+        _HARD_OVERW { w: self }
+    }
+    #[doc = "Bit 10 - Reboot Reset overwrite request"]
+    #[inline]
+    pub fn rbt_over(&mut self) -> _RBT_OVERW {
+        _RBT_OVERW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/sysctl/sys_secdata_unlock.rs b/example-source/msp432p401r/src/sysctl/sys_secdata_unlock.rs
new file mode 100644
index 0000000..f1dd2c8
--- /dev/null
+++ b/example-source/msp432p401r/src/sysctl/sys_secdata_unlock.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SYS_SECDATA_UNLOCK {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UNLKEYR {
+    bits: u16,
+}
+impl UNLKEYR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UNLKEYW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UNLKEYW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Unlock key"]
+    #[inline]
+    pub fn unlkey(&self) -> UNLKEYR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        UNLKEYR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Unlock key"]
+    #[inline]
+    pub fn unlkey(&mut self) -> _UNLKEYW {
+        _UNLKEYW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/sysctl/sys_sram_banken.rs b/example-source/msp432p401r/src/sysctl/sys_sram_banken.rs
new file mode 100644
index 0000000..9fd8b8b
--- /dev/null
+++ b/example-source/msp432p401r/src/sysctl/sys_sram_banken.rs
@@ -0,0 +1,984 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SYS_SRAM_BANKEN {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct BNK0_ENR {
+    bits: bool,
+}
+impl BNK0_ENR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `BNK1_EN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum BNK1_ENR {
+    #[doc = "Disables Bank1 of the SRAM"]
+    BNK1_EN_0,
+    #[doc = "Enables Bank1 of the SRAM"]
+    BNK1_EN_1,
+}
+impl BNK1_ENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            BNK1_ENR::BNK1_EN_0 => false,
+            BNK1_ENR::BNK1_EN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> BNK1_ENR {
+        match value {
+            false => BNK1_ENR::BNK1_EN_0,
+            true => BNK1_ENR::BNK1_EN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `BNK1_EN_0`"]
+    #[inline]
+    pub fn is_bnk1_en_0(&self) -> bool {
+        *self == BNK1_ENR::BNK1_EN_0
+    }
+    #[doc = "Checks if the value of the field is `BNK1_EN_1`"]
+    #[inline]
+    pub fn is_bnk1_en_1(&self) -> bool {
+        *self == BNK1_ENR::BNK1_EN_1
+    }
+}
+#[doc = "Possible values of the field `BNK2_EN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum BNK2_ENR {
+    #[doc = "Disables Bank2 of the SRAM"]
+    BNK2_EN_0,
+    #[doc = "Enables Bank2 of the SRAM"]
+    BNK2_EN_1,
+}
+impl BNK2_ENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            BNK2_ENR::BNK2_EN_0 => false,
+            BNK2_ENR::BNK2_EN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> BNK2_ENR {
+        match value {
+            false => BNK2_ENR::BNK2_EN_0,
+            true => BNK2_ENR::BNK2_EN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `BNK2_EN_0`"]
+    #[inline]
+    pub fn is_bnk2_en_0(&self) -> bool {
+        *self == BNK2_ENR::BNK2_EN_0
+    }
+    #[doc = "Checks if the value of the field is `BNK2_EN_1`"]
+    #[inline]
+    pub fn is_bnk2_en_1(&self) -> bool {
+        *self == BNK2_ENR::BNK2_EN_1
+    }
+}
+#[doc = "Possible values of the field `BNK3_EN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum BNK3_ENR {
+    #[doc = "Disables Bank3 of the SRAM"]
+    BNK3_EN_0,
+    #[doc = "Enables Bank3 of the SRAM"]
+    BNK3_EN_1,
+}
+impl BNK3_ENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            BNK3_ENR::BNK3_EN_0 => false,
+            BNK3_ENR::BNK3_EN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> BNK3_ENR {
+        match value {
+            false => BNK3_ENR::BNK3_EN_0,
+            true => BNK3_ENR::BNK3_EN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `BNK3_EN_0`"]
+    #[inline]
+    pub fn is_bnk3_en_0(&self) -> bool {
+        *self == BNK3_ENR::BNK3_EN_0
+    }
+    #[doc = "Checks if the value of the field is `BNK3_EN_1`"]
+    #[inline]
+    pub fn is_bnk3_en_1(&self) -> bool {
+        *self == BNK3_ENR::BNK3_EN_1
+    }
+}
+#[doc = "Possible values of the field `BNK4_EN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum BNK4_ENR {
+    #[doc = "Disables Bank4 of the SRAM"]
+    BNK4_EN_0,
+    #[doc = "Enables Bank4 of the SRAM"]
+    BNK4_EN_1,
+}
+impl BNK4_ENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            BNK4_ENR::BNK4_EN_0 => false,
+            BNK4_ENR::BNK4_EN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> BNK4_ENR {
+        match value {
+            false => BNK4_ENR::BNK4_EN_0,
+            true => BNK4_ENR::BNK4_EN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `BNK4_EN_0`"]
+    #[inline]
+    pub fn is_bnk4_en_0(&self) -> bool {
+        *self == BNK4_ENR::BNK4_EN_0
+    }
+    #[doc = "Checks if the value of the field is `BNK4_EN_1`"]
+    #[inline]
+    pub fn is_bnk4_en_1(&self) -> bool {
+        *self == BNK4_ENR::BNK4_EN_1
+    }
+}
+#[doc = "Possible values of the field `BNK5_EN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum BNK5_ENR {
+    #[doc = "Disables Bank5 of the SRAM"]
+    BNK5_EN_0,
+    #[doc = "Enables Bank5 of the SRAM"]
+    BNK5_EN_1,
+}
+impl BNK5_ENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            BNK5_ENR::BNK5_EN_0 => false,
+            BNK5_ENR::BNK5_EN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> BNK5_ENR {
+        match value {
+            false => BNK5_ENR::BNK5_EN_0,
+            true => BNK5_ENR::BNK5_EN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `BNK5_EN_0`"]
+    #[inline]
+    pub fn is_bnk5_en_0(&self) -> bool {
+        *self == BNK5_ENR::BNK5_EN_0
+    }
+    #[doc = "Checks if the value of the field is `BNK5_EN_1`"]
+    #[inline]
+    pub fn is_bnk5_en_1(&self) -> bool {
+        *self == BNK5_ENR::BNK5_EN_1
+    }
+}
+#[doc = "Possible values of the field `BNK6_EN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum BNK6_ENR {
+    #[doc = "Disables Bank6 of the SRAM"]
+    BNK6_EN_0,
+    #[doc = "Enables Bank6 of the SRAM"]
+    BNK6_EN_1,
+}
+impl BNK6_ENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            BNK6_ENR::BNK6_EN_0 => false,
+            BNK6_ENR::BNK6_EN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> BNK6_ENR {
+        match value {
+            false => BNK6_ENR::BNK6_EN_0,
+            true => BNK6_ENR::BNK6_EN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `BNK6_EN_0`"]
+    #[inline]
+    pub fn is_bnk6_en_0(&self) -> bool {
+        *self == BNK6_ENR::BNK6_EN_0
+    }
+    #[doc = "Checks if the value of the field is `BNK6_EN_1`"]
+    #[inline]
+    pub fn is_bnk6_en_1(&self) -> bool {
+        *self == BNK6_ENR::BNK6_EN_1
+    }
+}
+#[doc = "Possible values of the field `BNK7_EN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum BNK7_ENR {
+    #[doc = "Disables Bank7 of the SRAM"]
+    BNK7_EN_0,
+    #[doc = "Enables Bank7 of the SRAM"]
+    BNK7_EN_1,
+}
+impl BNK7_ENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            BNK7_ENR::BNK7_EN_0 => false,
+            BNK7_ENR::BNK7_EN_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> BNK7_ENR {
+        match value {
+            false => BNK7_ENR::BNK7_EN_0,
+            true => BNK7_ENR::BNK7_EN_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `BNK7_EN_0`"]
+    #[inline]
+    pub fn is_bnk7_en_0(&self) -> bool {
+        *self == BNK7_ENR::BNK7_EN_0
+    }
+    #[doc = "Checks if the value of the field is `BNK7_EN_1`"]
+    #[inline]
+    pub fn is_bnk7_en_1(&self) -> bool {
+        *self == BNK7_ENR::BNK7_EN_1
+    }
+}
+#[doc = "Possible values of the field `SRAM_RDY`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SRAM_RDYR {
+    #[doc = "SRAM is not ready for accesses. Banks are undergoing an enable or disable sequence, and reads or writes to SRAM are stalled until the banks are ready"]
+    SRAM_RDY_0,
+    #[doc = "SRAM is ready for accesses. All SRAM banks are enabled/disabled according to values of bits 7:0 of this register"]
+    SRAM_RDY_1,
+}
+impl SRAM_RDYR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            SRAM_RDYR::SRAM_RDY_0 => false,
+            SRAM_RDYR::SRAM_RDY_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> SRAM_RDYR {
+        match value {
+            false => SRAM_RDYR::SRAM_RDY_0,
+            true => SRAM_RDYR::SRAM_RDY_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SRAM_RDY_0`"]
+    #[inline]
+    pub fn is_sram_rdy_0(&self) -> bool {
+        *self == SRAM_RDYR::SRAM_RDY_0
+    }
+    #[doc = "Checks if the value of the field is `SRAM_RDY_1`"]
+    #[inline]
+    pub fn is_sram_rdy_1(&self) -> bool {
+        *self == SRAM_RDYR::SRAM_RDY_1
+    }
+}
+#[doc = "Values that can be written to the field `BNK1_EN`"]
+pub enum BNK1_ENW {
+    #[doc = "Disables Bank1 of the SRAM"]
+    BNK1_EN_0,
+    #[doc = "Enables Bank1 of the SRAM"]
+    BNK1_EN_1,
+}
+impl BNK1_ENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            BNK1_ENW::BNK1_EN_0 => false,
+            BNK1_ENW::BNK1_EN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _BNK1_ENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _BNK1_ENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: BNK1_ENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disables Bank1 of the SRAM"]
+    #[inline]
+    pub fn bnk1_en_0(self) -> &'a mut W {
+        self.variant(BNK1_ENW::BNK1_EN_0)
+    }
+    #[doc = "Enables Bank1 of the SRAM"]
+    #[inline]
+    pub fn bnk1_en_1(self) -> &'a mut W {
+        self.variant(BNK1_ENW::BNK1_EN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `BNK2_EN`"]
+pub enum BNK2_ENW {
+    #[doc = "Disables Bank2 of the SRAM"]
+    BNK2_EN_0,
+    #[doc = "Enables Bank2 of the SRAM"]
+    BNK2_EN_1,
+}
+impl BNK2_ENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            BNK2_ENW::BNK2_EN_0 => false,
+            BNK2_ENW::BNK2_EN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _BNK2_ENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _BNK2_ENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: BNK2_ENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disables Bank2 of the SRAM"]
+    #[inline]
+    pub fn bnk2_en_0(self) -> &'a mut W {
+        self.variant(BNK2_ENW::BNK2_EN_0)
+    }
+    #[doc = "Enables Bank2 of the SRAM"]
+    #[inline]
+    pub fn bnk2_en_1(self) -> &'a mut W {
+        self.variant(BNK2_ENW::BNK2_EN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `BNK3_EN`"]
+pub enum BNK3_ENW {
+    #[doc = "Disables Bank3 of the SRAM"]
+    BNK3_EN_0,
+    #[doc = "Enables Bank3 of the SRAM"]
+    BNK3_EN_1,
+}
+impl BNK3_ENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            BNK3_ENW::BNK3_EN_0 => false,
+            BNK3_ENW::BNK3_EN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _BNK3_ENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _BNK3_ENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: BNK3_ENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disables Bank3 of the SRAM"]
+    #[inline]
+    pub fn bnk3_en_0(self) -> &'a mut W {
+        self.variant(BNK3_ENW::BNK3_EN_0)
+    }
+    #[doc = "Enables Bank3 of the SRAM"]
+    #[inline]
+    pub fn bnk3_en_1(self) -> &'a mut W {
+        self.variant(BNK3_ENW::BNK3_EN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `BNK4_EN`"]
+pub enum BNK4_ENW {
+    #[doc = "Disables Bank4 of the SRAM"]
+    BNK4_EN_0,
+    #[doc = "Enables Bank4 of the SRAM"]
+    BNK4_EN_1,
+}
+impl BNK4_ENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            BNK4_ENW::BNK4_EN_0 => false,
+            BNK4_ENW::BNK4_EN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _BNK4_ENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _BNK4_ENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: BNK4_ENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disables Bank4 of the SRAM"]
+    #[inline]
+    pub fn bnk4_en_0(self) -> &'a mut W {
+        self.variant(BNK4_ENW::BNK4_EN_0)
+    }
+    #[doc = "Enables Bank4 of the SRAM"]
+    #[inline]
+    pub fn bnk4_en_1(self) -> &'a mut W {
+        self.variant(BNK4_ENW::BNK4_EN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `BNK5_EN`"]
+pub enum BNK5_ENW {
+    #[doc = "Disables Bank5 of the SRAM"]
+    BNK5_EN_0,
+    #[doc = "Enables Bank5 of the SRAM"]
+    BNK5_EN_1,
+}
+impl BNK5_ENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            BNK5_ENW::BNK5_EN_0 => false,
+            BNK5_ENW::BNK5_EN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _BNK5_ENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _BNK5_ENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: BNK5_ENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disables Bank5 of the SRAM"]
+    #[inline]
+    pub fn bnk5_en_0(self) -> &'a mut W {
+        self.variant(BNK5_ENW::BNK5_EN_0)
+    }
+    #[doc = "Enables Bank5 of the SRAM"]
+    #[inline]
+    pub fn bnk5_en_1(self) -> &'a mut W {
+        self.variant(BNK5_ENW::BNK5_EN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `BNK6_EN`"]
+pub enum BNK6_ENW {
+    #[doc = "Disables Bank6 of the SRAM"]
+    BNK6_EN_0,
+    #[doc = "Enables Bank6 of the SRAM"]
+    BNK6_EN_1,
+}
+impl BNK6_ENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            BNK6_ENW::BNK6_EN_0 => false,
+            BNK6_ENW::BNK6_EN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _BNK6_ENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _BNK6_ENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: BNK6_ENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disables Bank6 of the SRAM"]
+    #[inline]
+    pub fn bnk6_en_0(self) -> &'a mut W {
+        self.variant(BNK6_ENW::BNK6_EN_0)
+    }
+    #[doc = "Enables Bank6 of the SRAM"]
+    #[inline]
+    pub fn bnk6_en_1(self) -> &'a mut W {
+        self.variant(BNK6_ENW::BNK6_EN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `BNK7_EN`"]
+pub enum BNK7_ENW {
+    #[doc = "Disables Bank7 of the SRAM"]
+    BNK7_EN_0,
+    #[doc = "Enables Bank7 of the SRAM"]
+    BNK7_EN_1,
+}
+impl BNK7_ENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            BNK7_ENW::BNK7_EN_0 => false,
+            BNK7_ENW::BNK7_EN_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _BNK7_ENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _BNK7_ENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: BNK7_ENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disables Bank7 of the SRAM"]
+    #[inline]
+    pub fn bnk7_en_0(self) -> &'a mut W {
+        self.variant(BNK7_ENW::BNK7_EN_0)
+    }
+    #[doc = "Enables Bank7 of the SRAM"]
+    #[inline]
+    pub fn bnk7_en_1(self) -> &'a mut W {
+        self.variant(BNK7_ENW::BNK7_EN_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - SRAM Bank0 enable"]
+    #[inline]
+    pub fn bnk0_en(&self) -> BNK0_ENR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        BNK0_ENR { bits }
+    }
+    #[doc = "Bit 1 - SRAM Bank1 enable"]
+    #[inline]
+    pub fn bnk1_en(&self) -> BNK1_ENR {
+        BNK1_ENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - SRAM Bank1 enable"]
+    #[inline]
+    pub fn bnk2_en(&self) -> BNK2_ENR {
+        BNK2_ENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 3 - SRAM Bank1 enable"]
+    #[inline]
+    pub fn bnk3_en(&self) -> BNK3_ENR {
+        BNK3_ENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 4 - SRAM Bank1 enable"]
+    #[inline]
+    pub fn bnk4_en(&self) -> BNK4_ENR {
+        BNK4_ENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 5 - SRAM Bank1 enable"]
+    #[inline]
+    pub fn bnk5_en(&self) -> BNK5_ENR {
+        BNK5_ENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 6 - SRAM Bank1 enable"]
+    #[inline]
+    pub fn bnk6_en(&self) -> BNK6_ENR {
+        BNK6_ENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 7 - SRAM Bank1 enable"]
+    #[inline]
+    pub fn bnk7_en(&self) -> BNK7_ENR {
+        BNK7_ENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 16 - SRAM ready"]
+    #[inline]
+    pub fn sram_rdy(&self) -> SRAM_RDYR {
+        SRAM_RDYR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 255 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 1 - SRAM Bank1 enable"]
+    #[inline]
+    pub fn bnk1_en(&mut self) -> _BNK1_ENW {
+        _BNK1_ENW { w: self }
+    }
+    #[doc = "Bit 2 - SRAM Bank1 enable"]
+    #[inline]
+    pub fn bnk2_en(&mut self) -> _BNK2_ENW {
+        _BNK2_ENW { w: self }
+    }
+    #[doc = "Bit 3 - SRAM Bank1 enable"]
+    #[inline]
+    pub fn bnk3_en(&mut self) -> _BNK3_ENW {
+        _BNK3_ENW { w: self }
+    }
+    #[doc = "Bit 4 - SRAM Bank1 enable"]
+    #[inline]
+    pub fn bnk4_en(&mut self) -> _BNK4_ENW {
+        _BNK4_ENW { w: self }
+    }
+    #[doc = "Bit 5 - SRAM Bank1 enable"]
+    #[inline]
+    pub fn bnk5_en(&mut self) -> _BNK5_ENW {
+        _BNK5_ENW { w: self }
+    }
+    #[doc = "Bit 6 - SRAM Bank1 enable"]
+    #[inline]
+    pub fn bnk6_en(&mut self) -> _BNK6_ENW {
+        _BNK6_ENW { w: self }
+    }
+    #[doc = "Bit 7 - SRAM Bank1 enable"]
+    #[inline]
+    pub fn bnk7_en(&mut self) -> _BNK7_ENW {
+        _BNK7_ENW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/sysctl/sys_sram_bankret.rs b/example-source/msp432p401r/src/sysctl/sys_sram_bankret.rs
new file mode 100644
index 0000000..894cac4
--- /dev/null
+++ b/example-source/msp432p401r/src/sysctl/sys_sram_bankret.rs
@@ -0,0 +1,984 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SYS_SRAM_BANKRET {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct BNK0_RETR {
+    bits: bool,
+}
+impl BNK0_RETR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `BNK1_RET`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum BNK1_RETR {
+    #[doc = "Bank1 of the SRAM is not retained in LPM3 or LPM4"]
+    BNK1_RET_0,
+    #[doc = "Bank1 of the SRAM is retained in LPM3 and LPM4"]
+    BNK1_RET_1,
+}
+impl BNK1_RETR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            BNK1_RETR::BNK1_RET_0 => false,
+            BNK1_RETR::BNK1_RET_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> BNK1_RETR {
+        match value {
+            false => BNK1_RETR::BNK1_RET_0,
+            true => BNK1_RETR::BNK1_RET_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `BNK1_RET_0`"]
+    #[inline]
+    pub fn is_bnk1_ret_0(&self) -> bool {
+        *self == BNK1_RETR::BNK1_RET_0
+    }
+    #[doc = "Checks if the value of the field is `BNK1_RET_1`"]
+    #[inline]
+    pub fn is_bnk1_ret_1(&self) -> bool {
+        *self == BNK1_RETR::BNK1_RET_1
+    }
+}
+#[doc = "Possible values of the field `BNK2_RET`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum BNK2_RETR {
+    #[doc = "Bank2 of the SRAM is not retained in LPM3 or LPM4"]
+    BNK2_RET_0,
+    #[doc = "Bank2 of the SRAM is retained in LPM3 and LPM4"]
+    BNK2_RET_1,
+}
+impl BNK2_RETR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            BNK2_RETR::BNK2_RET_0 => false,
+            BNK2_RETR::BNK2_RET_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> BNK2_RETR {
+        match value {
+            false => BNK2_RETR::BNK2_RET_0,
+            true => BNK2_RETR::BNK2_RET_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `BNK2_RET_0`"]
+    #[inline]
+    pub fn is_bnk2_ret_0(&self) -> bool {
+        *self == BNK2_RETR::BNK2_RET_0
+    }
+    #[doc = "Checks if the value of the field is `BNK2_RET_1`"]
+    #[inline]
+    pub fn is_bnk2_ret_1(&self) -> bool {
+        *self == BNK2_RETR::BNK2_RET_1
+    }
+}
+#[doc = "Possible values of the field `BNK3_RET`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum BNK3_RETR {
+    #[doc = "Bank3 of the SRAM is not retained in LPM3 or LPM4"]
+    BNK3_RET_0,
+    #[doc = "Bank3 of the SRAM is retained in LPM3 and LPM4"]
+    BNK3_RET_1,
+}
+impl BNK3_RETR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            BNK3_RETR::BNK3_RET_0 => false,
+            BNK3_RETR::BNK3_RET_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> BNK3_RETR {
+        match value {
+            false => BNK3_RETR::BNK3_RET_0,
+            true => BNK3_RETR::BNK3_RET_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `BNK3_RET_0`"]
+    #[inline]
+    pub fn is_bnk3_ret_0(&self) -> bool {
+        *self == BNK3_RETR::BNK3_RET_0
+    }
+    #[doc = "Checks if the value of the field is `BNK3_RET_1`"]
+    #[inline]
+    pub fn is_bnk3_ret_1(&self) -> bool {
+        *self == BNK3_RETR::BNK3_RET_1
+    }
+}
+#[doc = "Possible values of the field `BNK4_RET`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum BNK4_RETR {
+    #[doc = "Bank4 of the SRAM is not retained in LPM3 or LPM4"]
+    BNK4_RET_0,
+    #[doc = "Bank4 of the SRAM is retained in LPM3 and LPM4"]
+    BNK4_RET_1,
+}
+impl BNK4_RETR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            BNK4_RETR::BNK4_RET_0 => false,
+            BNK4_RETR::BNK4_RET_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> BNK4_RETR {
+        match value {
+            false => BNK4_RETR::BNK4_RET_0,
+            true => BNK4_RETR::BNK4_RET_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `BNK4_RET_0`"]
+    #[inline]
+    pub fn is_bnk4_ret_0(&self) -> bool {
+        *self == BNK4_RETR::BNK4_RET_0
+    }
+    #[doc = "Checks if the value of the field is `BNK4_RET_1`"]
+    #[inline]
+    pub fn is_bnk4_ret_1(&self) -> bool {
+        *self == BNK4_RETR::BNK4_RET_1
+    }
+}
+#[doc = "Possible values of the field `BNK5_RET`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum BNK5_RETR {
+    #[doc = "Bank5 of the SRAM is not retained in LPM3 or LPM4"]
+    BNK5_RET_0,
+    #[doc = "Bank5 of the SRAM is retained in LPM3 and LPM4"]
+    BNK5_RET_1,
+}
+impl BNK5_RETR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            BNK5_RETR::BNK5_RET_0 => false,
+            BNK5_RETR::BNK5_RET_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> BNK5_RETR {
+        match value {
+            false => BNK5_RETR::BNK5_RET_0,
+            true => BNK5_RETR::BNK5_RET_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `BNK5_RET_0`"]
+    #[inline]
+    pub fn is_bnk5_ret_0(&self) -> bool {
+        *self == BNK5_RETR::BNK5_RET_0
+    }
+    #[doc = "Checks if the value of the field is `BNK5_RET_1`"]
+    #[inline]
+    pub fn is_bnk5_ret_1(&self) -> bool {
+        *self == BNK5_RETR::BNK5_RET_1
+    }
+}
+#[doc = "Possible values of the field `BNK6_RET`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum BNK6_RETR {
+    #[doc = "Bank6 of the SRAM is not retained in LPM3 or LPM4"]
+    BNK6_RET_0,
+    #[doc = "Bank6 of the SRAM is retained in LPM3 and LPM4"]
+    BNK6_RET_1,
+}
+impl BNK6_RETR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            BNK6_RETR::BNK6_RET_0 => false,
+            BNK6_RETR::BNK6_RET_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> BNK6_RETR {
+        match value {
+            false => BNK6_RETR::BNK6_RET_0,
+            true => BNK6_RETR::BNK6_RET_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `BNK6_RET_0`"]
+    #[inline]
+    pub fn is_bnk6_ret_0(&self) -> bool {
+        *self == BNK6_RETR::BNK6_RET_0
+    }
+    #[doc = "Checks if the value of the field is `BNK6_RET_1`"]
+    #[inline]
+    pub fn is_bnk6_ret_1(&self) -> bool {
+        *self == BNK6_RETR::BNK6_RET_1
+    }
+}
+#[doc = "Possible values of the field `BNK7_RET`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum BNK7_RETR {
+    #[doc = "Bank7 of the SRAM is not retained in LPM3 or LPM4"]
+    BNK7_RET_0,
+    #[doc = "Bank7 of the SRAM is retained in LPM3 and LPM4"]
+    BNK7_RET_1,
+}
+impl BNK7_RETR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            BNK7_RETR::BNK7_RET_0 => false,
+            BNK7_RETR::BNK7_RET_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> BNK7_RETR {
+        match value {
+            false => BNK7_RETR::BNK7_RET_0,
+            true => BNK7_RETR::BNK7_RET_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `BNK7_RET_0`"]
+    #[inline]
+    pub fn is_bnk7_ret_0(&self) -> bool {
+        *self == BNK7_RETR::BNK7_RET_0
+    }
+    #[doc = "Checks if the value of the field is `BNK7_RET_1`"]
+    #[inline]
+    pub fn is_bnk7_ret_1(&self) -> bool {
+        *self == BNK7_RETR::BNK7_RET_1
+    }
+}
+#[doc = "Possible values of the field `SRAM_RDY`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SRAM_RDYR {
+    #[doc = "SRAM banks are being set up for retention. Entry into LPM3, LPM4 should not be attempted until this bit is set to 1"]
+    SRAM_RDY_0,
+    #[doc = "SRAM is ready for accesses. All SRAM banks are enabled/disabled for retention according to values of bits 7:0 of this register"]
+    SRAM_RDY_1,
+}
+impl SRAM_RDYR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            SRAM_RDYR::SRAM_RDY_0 => false,
+            SRAM_RDYR::SRAM_RDY_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> SRAM_RDYR {
+        match value {
+            false => SRAM_RDYR::SRAM_RDY_0,
+            true => SRAM_RDYR::SRAM_RDY_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SRAM_RDY_0`"]
+    #[inline]
+    pub fn is_sram_rdy_0(&self) -> bool {
+        *self == SRAM_RDYR::SRAM_RDY_0
+    }
+    #[doc = "Checks if the value of the field is `SRAM_RDY_1`"]
+    #[inline]
+    pub fn is_sram_rdy_1(&self) -> bool {
+        *self == SRAM_RDYR::SRAM_RDY_1
+    }
+}
+#[doc = "Values that can be written to the field `BNK1_RET`"]
+pub enum BNK1_RETW {
+    #[doc = "Bank1 of the SRAM is not retained in LPM3 or LPM4"]
+    BNK1_RET_0,
+    #[doc = "Bank1 of the SRAM is retained in LPM3 and LPM4"]
+    BNK1_RET_1,
+}
+impl BNK1_RETW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            BNK1_RETW::BNK1_RET_0 => false,
+            BNK1_RETW::BNK1_RET_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _BNK1_RETW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _BNK1_RETW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: BNK1_RETW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Bank1 of the SRAM is not retained in LPM3 or LPM4"]
+    #[inline]
+    pub fn bnk1_ret_0(self) -> &'a mut W {
+        self.variant(BNK1_RETW::BNK1_RET_0)
+    }
+    #[doc = "Bank1 of the SRAM is retained in LPM3 and LPM4"]
+    #[inline]
+    pub fn bnk1_ret_1(self) -> &'a mut W {
+        self.variant(BNK1_RETW::BNK1_RET_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `BNK2_RET`"]
+pub enum BNK2_RETW {
+    #[doc = "Bank2 of the SRAM is not retained in LPM3 or LPM4"]
+    BNK2_RET_0,
+    #[doc = "Bank2 of the SRAM is retained in LPM3 and LPM4"]
+    BNK2_RET_1,
+}
+impl BNK2_RETW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            BNK2_RETW::BNK2_RET_0 => false,
+            BNK2_RETW::BNK2_RET_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _BNK2_RETW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _BNK2_RETW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: BNK2_RETW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Bank2 of the SRAM is not retained in LPM3 or LPM4"]
+    #[inline]
+    pub fn bnk2_ret_0(self) -> &'a mut W {
+        self.variant(BNK2_RETW::BNK2_RET_0)
+    }
+    #[doc = "Bank2 of the SRAM is retained in LPM3 and LPM4"]
+    #[inline]
+    pub fn bnk2_ret_1(self) -> &'a mut W {
+        self.variant(BNK2_RETW::BNK2_RET_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `BNK3_RET`"]
+pub enum BNK3_RETW {
+    #[doc = "Bank3 of the SRAM is not retained in LPM3 or LPM4"]
+    BNK3_RET_0,
+    #[doc = "Bank3 of the SRAM is retained in LPM3 and LPM4"]
+    BNK3_RET_1,
+}
+impl BNK3_RETW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            BNK3_RETW::BNK3_RET_0 => false,
+            BNK3_RETW::BNK3_RET_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _BNK3_RETW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _BNK3_RETW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: BNK3_RETW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Bank3 of the SRAM is not retained in LPM3 or LPM4"]
+    #[inline]
+    pub fn bnk3_ret_0(self) -> &'a mut W {
+        self.variant(BNK3_RETW::BNK3_RET_0)
+    }
+    #[doc = "Bank3 of the SRAM is retained in LPM3 and LPM4"]
+    #[inline]
+    pub fn bnk3_ret_1(self) -> &'a mut W {
+        self.variant(BNK3_RETW::BNK3_RET_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `BNK4_RET`"]
+pub enum BNK4_RETW {
+    #[doc = "Bank4 of the SRAM is not retained in LPM3 or LPM4"]
+    BNK4_RET_0,
+    #[doc = "Bank4 of the SRAM is retained in LPM3 and LPM4"]
+    BNK4_RET_1,
+}
+impl BNK4_RETW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            BNK4_RETW::BNK4_RET_0 => false,
+            BNK4_RETW::BNK4_RET_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _BNK4_RETW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _BNK4_RETW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: BNK4_RETW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Bank4 of the SRAM is not retained in LPM3 or LPM4"]
+    #[inline]
+    pub fn bnk4_ret_0(self) -> &'a mut W {
+        self.variant(BNK4_RETW::BNK4_RET_0)
+    }
+    #[doc = "Bank4 of the SRAM is retained in LPM3 and LPM4"]
+    #[inline]
+    pub fn bnk4_ret_1(self) -> &'a mut W {
+        self.variant(BNK4_RETW::BNK4_RET_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `BNK5_RET`"]
+pub enum BNK5_RETW {
+    #[doc = "Bank5 of the SRAM is not retained in LPM3 or LPM4"]
+    BNK5_RET_0,
+    #[doc = "Bank5 of the SRAM is retained in LPM3 and LPM4"]
+    BNK5_RET_1,
+}
+impl BNK5_RETW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            BNK5_RETW::BNK5_RET_0 => false,
+            BNK5_RETW::BNK5_RET_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _BNK5_RETW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _BNK5_RETW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: BNK5_RETW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Bank5 of the SRAM is not retained in LPM3 or LPM4"]
+    #[inline]
+    pub fn bnk5_ret_0(self) -> &'a mut W {
+        self.variant(BNK5_RETW::BNK5_RET_0)
+    }
+    #[doc = "Bank5 of the SRAM is retained in LPM3 and LPM4"]
+    #[inline]
+    pub fn bnk5_ret_1(self) -> &'a mut W {
+        self.variant(BNK5_RETW::BNK5_RET_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `BNK6_RET`"]
+pub enum BNK6_RETW {
+    #[doc = "Bank6 of the SRAM is not retained in LPM3 or LPM4"]
+    BNK6_RET_0,
+    #[doc = "Bank6 of the SRAM is retained in LPM3 and LPM4"]
+    BNK6_RET_1,
+}
+impl BNK6_RETW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            BNK6_RETW::BNK6_RET_0 => false,
+            BNK6_RETW::BNK6_RET_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _BNK6_RETW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _BNK6_RETW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: BNK6_RETW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Bank6 of the SRAM is not retained in LPM3 or LPM4"]
+    #[inline]
+    pub fn bnk6_ret_0(self) -> &'a mut W {
+        self.variant(BNK6_RETW::BNK6_RET_0)
+    }
+    #[doc = "Bank6 of the SRAM is retained in LPM3 and LPM4"]
+    #[inline]
+    pub fn bnk6_ret_1(self) -> &'a mut W {
+        self.variant(BNK6_RETW::BNK6_RET_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `BNK7_RET`"]
+pub enum BNK7_RETW {
+    #[doc = "Bank7 of the SRAM is not retained in LPM3 or LPM4"]
+    BNK7_RET_0,
+    #[doc = "Bank7 of the SRAM is retained in LPM3 and LPM4"]
+    BNK7_RET_1,
+}
+impl BNK7_RETW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            BNK7_RETW::BNK7_RET_0 => false,
+            BNK7_RETW::BNK7_RET_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _BNK7_RETW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _BNK7_RETW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: BNK7_RETW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Bank7 of the SRAM is not retained in LPM3 or LPM4"]
+    #[inline]
+    pub fn bnk7_ret_0(self) -> &'a mut W {
+        self.variant(BNK7_RETW::BNK7_RET_0)
+    }
+    #[doc = "Bank7 of the SRAM is retained in LPM3 and LPM4"]
+    #[inline]
+    pub fn bnk7_ret_1(self) -> &'a mut W {
+        self.variant(BNK7_RETW::BNK7_RET_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Bank0 retention"]
+    #[inline]
+    pub fn bnk0_ret(&self) -> BNK0_RETR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        BNK0_RETR { bits }
+    }
+    #[doc = "Bit 1 - Bank1 retention"]
+    #[inline]
+    pub fn bnk1_ret(&self) -> BNK1_RETR {
+        BNK1_RETR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - Bank2 retention"]
+    #[inline]
+    pub fn bnk2_ret(&self) -> BNK2_RETR {
+        BNK2_RETR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 3 - Bank3 retention"]
+    #[inline]
+    pub fn bnk3_ret(&self) -> BNK3_RETR {
+        BNK3_RETR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 4 - Bank4 retention"]
+    #[inline]
+    pub fn bnk4_ret(&self) -> BNK4_RETR {
+        BNK4_RETR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 5 - Bank5 retention"]
+    #[inline]
+    pub fn bnk5_ret(&self) -> BNK5_RETR {
+        BNK5_RETR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 6 - Bank6 retention"]
+    #[inline]
+    pub fn bnk6_ret(&self) -> BNK6_RETR {
+        BNK6_RETR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 7 - Bank7 retention"]
+    #[inline]
+    pub fn bnk7_ret(&self) -> BNK7_RETR {
+        BNK7_RETR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 16 - SRAM ready"]
+    #[inline]
+    pub fn sram_rdy(&self) -> SRAM_RDYR {
+        SRAM_RDYR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 255 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 1 - Bank1 retention"]
+    #[inline]
+    pub fn bnk1_ret(&mut self) -> _BNK1_RETW {
+        _BNK1_RETW { w: self }
+    }
+    #[doc = "Bit 2 - Bank2 retention"]
+    #[inline]
+    pub fn bnk2_ret(&mut self) -> _BNK2_RETW {
+        _BNK2_RETW { w: self }
+    }
+    #[doc = "Bit 3 - Bank3 retention"]
+    #[inline]
+    pub fn bnk3_ret(&mut self) -> _BNK3_RETW {
+        _BNK3_RETW { w: self }
+    }
+    #[doc = "Bit 4 - Bank4 retention"]
+    #[inline]
+    pub fn bnk4_ret(&mut self) -> _BNK4_RETW {
+        _BNK4_RETW { w: self }
+    }
+    #[doc = "Bit 5 - Bank5 retention"]
+    #[inline]
+    pub fn bnk5_ret(&mut self) -> _BNK5_RETW {
+        _BNK5_RETW { w: self }
+    }
+    #[doc = "Bit 6 - Bank6 retention"]
+    #[inline]
+    pub fn bnk6_ret(&mut self) -> _BNK6_RETW {
+        _BNK6_RETW { w: self }
+    }
+    #[doc = "Bit 7 - Bank7 retention"]
+    #[inline]
+    pub fn bnk7_ret(&mut self) -> _BNK7_RETW {
+        _BNK7_RETW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/sysctl/sys_sram_size.rs b/example-source/msp432p401r/src/sysctl/sys_sram_size.rs
new file mode 100644
index 0000000..f66dba2
--- /dev/null
+++ b/example-source/msp432p401r/src/sysctl/sys_sram_size.rs
@@ -0,0 +1,41 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::SYS_SRAM_SIZE {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SIZER {
+    bits: u32,
+}
+impl SIZER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Indicates the size of SRAM on the device"]
+    #[inline]
+    pub fn size(&self) -> SIZER {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        SIZER { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/sysctl/sys_system_stat.rs b/example-source/msp432p401r/src/sysctl/sys_system_stat.rs
new file mode 100644
index 0000000..88708af
--- /dev/null
+++ b/example-source/msp432p401r/src/sysctl/sys_system_stat.rs
@@ -0,0 +1,113 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::SYS_SYSTEM_STAT {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DBG_SEC_ACTR {
+    bits: bool,
+}
+impl DBG_SEC_ACTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct JTAG_SWD_LOCK_ACTR {
+    bits: bool,
+}
+impl JTAG_SWD_LOCK_ACTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct IP_PROT_ACTR {
+    bits: bool,
+}
+impl IP_PROT_ACTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 3 - Debug Security active"]
+    #[inline]
+    pub fn dbg_sec_act(&self) -> DBG_SEC_ACTR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        DBG_SEC_ACTR { bits }
+    }
+    #[doc = "Bit 4 - Indicates if JTAG and SWD Lock is active"]
+    #[inline]
+    pub fn jtag_swd_lock_act(&self) -> JTAG_SWD_LOCK_ACTR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        JTAG_SWD_LOCK_ACTR { bits }
+    }
+    #[doc = "Bit 5 - Indicates if IP protection is active"]
+    #[inline]
+    pub fn ip_prot_act(&self) -> IP_PROT_ACTR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        IP_PROT_ACTR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/sysctl/sys_wdtreset_ctl.rs b/example-source/msp432p401r/src/sysctl/sys_wdtreset_ctl.rs
new file mode 100644
index 0000000..39515ba
--- /dev/null
+++ b/example-source/msp432p401r/src/sysctl/sys_wdtreset_ctl.rs
@@ -0,0 +1,302 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SYS_WDTRESET_CTL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `TIMEOUT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TIMEOUTR {
+    #[doc = "WDT timeout event generates Soft reset"]
+    TIMEOUT_0,
+    #[doc = "WDT timeout event generates Hard reset"]
+    TIMEOUT_1,
+}
+impl TIMEOUTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TIMEOUTR::TIMEOUT_0 => false,
+            TIMEOUTR::TIMEOUT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TIMEOUTR {
+        match value {
+            false => TIMEOUTR::TIMEOUT_0,
+            true => TIMEOUTR::TIMEOUT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `TIMEOUT_0`"]
+    #[inline]
+    pub fn is_timeout_0(&self) -> bool {
+        *self == TIMEOUTR::TIMEOUT_0
+    }
+    #[doc = "Checks if the value of the field is `TIMEOUT_1`"]
+    #[inline]
+    pub fn is_timeout_1(&self) -> bool {
+        *self == TIMEOUTR::TIMEOUT_1
+    }
+}
+#[doc = "Possible values of the field `VIOLATION`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum VIOLATIONR {
+    #[doc = "WDT password violation event generates Soft reset"]
+    VIOLATION_0,
+    #[doc = "WDT password violation event generates Hard reset"]
+    VIOLATION_1,
+}
+impl VIOLATIONR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            VIOLATIONR::VIOLATION_0 => false,
+            VIOLATIONR::VIOLATION_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> VIOLATIONR {
+        match value {
+            false => VIOLATIONR::VIOLATION_0,
+            true => VIOLATIONR::VIOLATION_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `VIOLATION_0`"]
+    #[inline]
+    pub fn is_violation_0(&self) -> bool {
+        *self == VIOLATIONR::VIOLATION_0
+    }
+    #[doc = "Checks if the value of the field is `VIOLATION_1`"]
+    #[inline]
+    pub fn is_violation_1(&self) -> bool {
+        *self == VIOLATIONR::VIOLATION_1
+    }
+}
+#[doc = "Values that can be written to the field `TIMEOUT`"]
+pub enum TIMEOUTW {
+    #[doc = "WDT timeout event generates Soft reset"]
+    TIMEOUT_0,
+    #[doc = "WDT timeout event generates Hard reset"]
+    TIMEOUT_1,
+}
+impl TIMEOUTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TIMEOUTW::TIMEOUT_0 => false,
+            TIMEOUTW::TIMEOUT_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TIMEOUTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TIMEOUTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TIMEOUTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "WDT timeout event generates Soft reset"]
+    #[inline]
+    pub fn timeout_0(self) -> &'a mut W {
+        self.variant(TIMEOUTW::TIMEOUT_0)
+    }
+    #[doc = "WDT timeout event generates Hard reset"]
+    #[inline]
+    pub fn timeout_1(self) -> &'a mut W {
+        self.variant(TIMEOUTW::TIMEOUT_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `VIOLATION`"]
+pub enum VIOLATIONW {
+    #[doc = "WDT password violation event generates Soft reset"]
+    VIOLATION_0,
+    #[doc = "WDT password violation event generates Hard reset"]
+    VIOLATION_1,
+}
+impl VIOLATIONW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            VIOLATIONW::VIOLATION_0 => false,
+            VIOLATIONW::VIOLATION_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _VIOLATIONW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _VIOLATIONW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: VIOLATIONW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "WDT password violation event generates Soft reset"]
+    #[inline]
+    pub fn violation_0(self) -> &'a mut W {
+        self.variant(VIOLATIONW::VIOLATION_0)
+    }
+    #[doc = "WDT password violation event generates Hard reset"]
+    #[inline]
+    pub fn violation_1(self) -> &'a mut W {
+        self.variant(VIOLATIONW::VIOLATION_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - WDT timeout reset type"]
+    #[inline]
+    pub fn timeout(&self) -> TIMEOUTR {
+        TIMEOUTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - WDT password violation reset type"]
+    #[inline]
+    pub fn violation(&self) -> VIOLATIONR {
+        VIOLATIONR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 3 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - WDT timeout reset type"]
+    #[inline]
+    pub fn timeout(&mut self) -> _TIMEOUTW {
+        _TIMEOUTW { w: self }
+    }
+    #[doc = "Bit 1 - WDT password violation reset type"]
+    #[inline]
+    pub fn violation(&mut self) -> _VIOLATIONW {
+        _VIOLATIONW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/system_control_space.rs b/example-source/msp432p401r/src/system_control_space.rs
new file mode 100644
index 0000000..6d8b202
--- /dev/null
+++ b/example-source/msp432p401r/src/system_control_space.rs
@@ -0,0 +1,21 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    _reserved0: [u8; 4usize],
+    #[doc = "0x04 - Interrupt Control Type Register"]
+    pub ictr: ICTR,
+    #[doc = "0x08 - Auxiliary Control Register"]
+    pub actlr: ACTLR,
+}
+#[doc = "Interrupt Control Type Register"]
+pub struct ICTR {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Interrupt Control Type Register"]
+pub mod ictr;
+#[doc = "Auxiliary Control Register"]
+pub struct ACTLR {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Auxiliary Control Register"]
+pub mod actlr;
diff --git a/example-source/msp432p401r/src/system_control_space/actlr.rs b/example-source/msp432p401r/src/system_control_space/actlr.rs
new file mode 100644
index 0000000..abcb035
--- /dev/null
+++ b/example-source/msp432p401r/src/system_control_space/actlr.rs
@@ -0,0 +1,359 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::ACTLR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DISMCYCINTR {
+    bits: bool,
+}
+impl DISMCYCINTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DISDEFWBUFR {
+    bits: bool,
+}
+impl DISDEFWBUFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DISFOLDR {
+    bits: bool,
+}
+impl DISFOLDR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DISFPCAR {
+    bits: bool,
+}
+impl DISFPCAR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DISOOFPR {
+    bits: bool,
+}
+impl DISOOFPR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DISMCYCINTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DISMCYCINTW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DISDEFWBUFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DISDEFWBUFW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DISFOLDW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DISFOLDW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DISFPCAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DISFPCAW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DISOOFPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DISOOFPW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Disables interruption of multi-cycle instructions. This increases the interrupt latency of the processor becuase LDM/STM completes before interrupt stacking occurs."]
+    #[inline]
+    pub fn dismcycint(&self) -> DISMCYCINTR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        DISMCYCINTR { bits }
+    }
+    #[doc = "Bit 1 - Disables write buffer us during default memorty map accesses. This causes all bus faults to be precise bus faults but decreases the performance of the processor because the stores to memory have to complete before the next instruction can be executed."]
+    #[inline]
+    pub fn disdefwbuf(&self) -> DISDEFWBUFR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        DISDEFWBUFR { bits }
+    }
+    #[doc = "Bit 2 - Disables IT folding."]
+    #[inline]
+    pub fn disfold(&self) -> DISFOLDR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        DISFOLDR { bits }
+    }
+    #[doc = "Bit 8 - Disable automatic update of CONTROL.FPCA"]
+    #[inline]
+    pub fn disfpca(&self) -> DISFPCAR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        DISFPCAR { bits }
+    }
+    #[doc = "Bit 9 - Disables floating point instructions completing out of order with respect to integer instructions."]
+    #[inline]
+    pub fn disoofp(&self) -> DISOOFPR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        DISOOFPR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Disables interruption of multi-cycle instructions. This increases the interrupt latency of the processor becuase LDM/STM completes before interrupt stacking occurs."]
+    #[inline]
+    pub fn dismcycint(&mut self) -> _DISMCYCINTW {
+        _DISMCYCINTW { w: self }
+    }
+    #[doc = "Bit 1 - Disables write buffer us during default memorty map accesses. This causes all bus faults to be precise bus faults but decreases the performance of the processor because the stores to memory have to complete before the next instruction can be executed."]
+    #[inline]
+    pub fn disdefwbuf(&mut self) -> _DISDEFWBUFW {
+        _DISDEFWBUFW { w: self }
+    }
+    #[doc = "Bit 2 - Disables IT folding."]
+    #[inline]
+    pub fn disfold(&mut self) -> _DISFOLDW {
+        _DISFOLDW { w: self }
+    }
+    #[doc = "Bit 8 - Disable automatic update of CONTROL.FPCA"]
+    #[inline]
+    pub fn disfpca(&mut self) -> _DISFPCAW {
+        _DISFPCAW { w: self }
+    }
+    #[doc = "Bit 9 - Disables floating point instructions completing out of order with respect to integer instructions."]
+    #[inline]
+    pub fn disoofp(&mut self) -> _DISOOFPW {
+        _DISOOFPW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/system_control_space/ictr.rs b/example-source/msp432p401r/src/system_control_space/ictr.rs
new file mode 100644
index 0000000..a761e12
--- /dev/null
+++ b/example-source/msp432p401r/src/system_control_space/ictr.rs
@@ -0,0 +1,41 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::ICTR {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct INTLINESNUMR {
+    bits: u8,
+}
+impl INTLINESNUMR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:4 - Total number of interrupt lines in groups of 32."]
+    #[inline]
+    pub fn intlinesnum(&self) -> INTLINESNUMR {
+        let bits = {
+            const MASK: u8 = 31;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        INTLINESNUMR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/timer32.rs b/example-source/msp432p401r/src/timer32.rs
new file mode 100644
index 0000000..6810339
--- /dev/null
+++ b/example-source/msp432p401r/src/timer32.rs
@@ -0,0 +1,117 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - Timer 1 Load Register"]
+    pub t32load1: T32LOAD1,
+    #[doc = "0x04 - Timer 1 Current Value Register"]
+    pub t32value1: T32VALUE1,
+    #[doc = "0x08 - Timer 1 Timer Control Register"]
+    pub t32control1: T32CONTROL1,
+    #[doc = "0x0c - Timer 1 Interrupt Clear Register"]
+    pub t32intclr1: T32INTCLR1,
+    #[doc = "0x10 - Timer 1 Raw Interrupt Status Register"]
+    pub t32ris1: T32RIS1,
+    #[doc = "0x14 - Timer 1 Interrupt Status Register"]
+    pub t32mis1: T32MIS1,
+    #[doc = "0x18 - Timer 1 Background Load Register"]
+    pub t32bgload1: T32BGLOAD1,
+    _reserved0: [u8; 4usize],
+    #[doc = "0x20 - Timer 2 Load Register"]
+    pub t32load2: T32LOAD2,
+    #[doc = "0x24 - Timer 2 Current Value Register"]
+    pub t32value2: T32VALUE2,
+    #[doc = "0x28 - Timer 2 Timer Control Register"]
+    pub t32control2: T32CONTROL2,
+    #[doc = "0x2c - Timer 2 Interrupt Clear Register"]
+    pub t32intclr2: T32INTCLR2,
+    #[doc = "0x30 - Timer 2 Raw Interrupt Status Register"]
+    pub t32ris2: T32RIS2,
+    #[doc = "0x34 - Timer 2 Interrupt Status Register"]
+    pub t32mis2: T32MIS2,
+    #[doc = "0x38 - Timer 2 Background Load Register"]
+    pub t32bgload2: T32BGLOAD2,
+}
+#[doc = "Timer 1 Load Register"]
+pub struct T32LOAD1 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Timer 1 Load Register"]
+pub mod t32load1;
+#[doc = "Timer 1 Current Value Register"]
+pub struct T32VALUE1 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Timer 1 Current Value Register"]
+pub mod t32value1;
+#[doc = "Timer 1 Timer Control Register"]
+pub struct T32CONTROL1 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Timer 1 Timer Control Register"]
+pub mod t32control1;
+#[doc = "Timer 1 Interrupt Clear Register"]
+pub struct T32INTCLR1 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Timer 1 Interrupt Clear Register"]
+pub mod t32intclr1;
+#[doc = "Timer 1 Raw Interrupt Status Register"]
+pub struct T32RIS1 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Timer 1 Raw Interrupt Status Register"]
+pub mod t32ris1;
+#[doc = "Timer 1 Interrupt Status Register"]
+pub struct T32MIS1 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Timer 1 Interrupt Status Register"]
+pub mod t32mis1;
+#[doc = "Timer 1 Background Load Register"]
+pub struct T32BGLOAD1 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Timer 1 Background Load Register"]
+pub mod t32bgload1;
+#[doc = "Timer 2 Load Register"]
+pub struct T32LOAD2 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Timer 2 Load Register"]
+pub mod t32load2;
+#[doc = "Timer 2 Current Value Register"]
+pub struct T32VALUE2 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Timer 2 Current Value Register"]
+pub mod t32value2;
+#[doc = "Timer 2 Timer Control Register"]
+pub struct T32CONTROL2 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Timer 2 Timer Control Register"]
+pub mod t32control2;
+#[doc = "Timer 2 Interrupt Clear Register"]
+pub struct T32INTCLR2 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Timer 2 Interrupt Clear Register"]
+pub mod t32intclr2;
+#[doc = "Timer 2 Raw Interrupt Status Register"]
+pub struct T32RIS2 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Timer 2 Raw Interrupt Status Register"]
+pub mod t32ris2;
+#[doc = "Timer 2 Interrupt Status Register"]
+pub struct T32MIS2 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Timer 2 Interrupt Status Register"]
+pub mod t32mis2;
+#[doc = "Timer 2 Background Load Register"]
+pub struct T32BGLOAD2 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Timer 2 Background Load Register"]
+pub mod t32bgload2;
diff --git a/example-source/msp432p401r/src/timer32/t32bgload1.rs b/example-source/msp432p401r/src/timer32/t32bgload1.rs
new file mode 100644
index 0000000..f7b6ae4
--- /dev/null
+++ b/example-source/msp432p401r/src/timer32/t32bgload1.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::T32BGLOAD1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct BGLOADR {
+    bits: u32,
+}
+impl BGLOADR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _BGLOADW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _BGLOADW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Value from which the counter decrements"]
+    #[inline]
+    pub fn bgload(&self) -> BGLOADR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        BGLOADR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Value from which the counter decrements"]
+    #[inline]
+    pub fn bgload(&mut self) -> _BGLOADW {
+        _BGLOADW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/timer32/t32bgload2.rs b/example-source/msp432p401r/src/timer32/t32bgload2.rs
new file mode 100644
index 0000000..628f364
--- /dev/null
+++ b/example-source/msp432p401r/src/timer32/t32bgload2.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::T32BGLOAD2 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct BGLOADR {
+    bits: u32,
+}
+impl BGLOADR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _BGLOADW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _BGLOADW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Value from which the counter decrements"]
+    #[inline]
+    pub fn bgload(&self) -> BGLOADR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        BGLOADR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Value from which the counter decrements"]
+    #[inline]
+    pub fn bgload(&mut self) -> _BGLOADW {
+        _BGLOADW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/timer32/t32control1.rs b/example-source/msp432p401r/src/timer32/t32control1.rs
new file mode 100644
index 0000000..301f8c2
--- /dev/null
+++ b/example-source/msp432p401r/src/timer32/t32control1.rs
@@ -0,0 +1,779 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::T32CONTROL1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `ONESHOT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ONESHOTR {
+    #[doc = "wrapping mode"]
+    ONESHOT_0,
+    #[doc = "one-shot mode"]
+    ONESHOT_1,
+}
+impl ONESHOTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ONESHOTR::ONESHOT_0 => false,
+            ONESHOTR::ONESHOT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ONESHOTR {
+        match value {
+            false => ONESHOTR::ONESHOT_0,
+            true => ONESHOTR::ONESHOT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ONESHOT_0`"]
+    #[inline]
+    pub fn is_oneshot_0(&self) -> bool {
+        *self == ONESHOTR::ONESHOT_0
+    }
+    #[doc = "Checks if the value of the field is `ONESHOT_1`"]
+    #[inline]
+    pub fn is_oneshot_1(&self) -> bool {
+        *self == ONESHOTR::ONESHOT_1
+    }
+}
+#[doc = "Possible values of the field `SIZE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SIZER {
+    #[doc = "16-bit counter"]
+    SIZE_0,
+    #[doc = "32-bit counter"]
+    SIZE_1,
+}
+impl SIZER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            SIZER::SIZE_0 => false,
+            SIZER::SIZE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> SIZER {
+        match value {
+            false => SIZER::SIZE_0,
+            true => SIZER::SIZE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SIZE_0`"]
+    #[inline]
+    pub fn is_size_0(&self) -> bool {
+        *self == SIZER::SIZE_0
+    }
+    #[doc = "Checks if the value of the field is `SIZE_1`"]
+    #[inline]
+    pub fn is_size_1(&self) -> bool {
+        *self == SIZER::SIZE_1
+    }
+}
+#[doc = "Possible values of the field `PRESCALE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PRESCALER {
+    #[doc = "0 stages of prescale, clock is divided by 1"]
+    PRESCALE_0,
+    #[doc = "4 stages of prescale, clock is divided by 16"]
+    PRESCALE_1,
+    #[doc = "8 stages of prescale, clock is divided by 256"]
+    PRESCALE_2,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl PRESCALER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            PRESCALER::PRESCALE_0 => 0,
+            PRESCALER::PRESCALE_1 => 1,
+            PRESCALER::PRESCALE_2 => 2,
+            PRESCALER::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> PRESCALER {
+        match value {
+            0 => PRESCALER::PRESCALE_0,
+            1 => PRESCALER::PRESCALE_1,
+            2 => PRESCALER::PRESCALE_2,
+            i => PRESCALER::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `PRESCALE_0`"]
+    #[inline]
+    pub fn is_prescale_0(&self) -> bool {
+        *self == PRESCALER::PRESCALE_0
+    }
+    #[doc = "Checks if the value of the field is `PRESCALE_1`"]
+    #[inline]
+    pub fn is_prescale_1(&self) -> bool {
+        *self == PRESCALER::PRESCALE_1
+    }
+    #[doc = "Checks if the value of the field is `PRESCALE_2`"]
+    #[inline]
+    pub fn is_prescale_2(&self) -> bool {
+        *self == PRESCALER::PRESCALE_2
+    }
+}
+#[doc = "Possible values of the field `IE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IER {
+    #[doc = "Timer interrupt disabled"]
+    IE_0,
+    #[doc = "Timer interrupt enabled"]
+    IE_1,
+}
+impl IER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            IER::IE_0 => false,
+            IER::IE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> IER {
+        match value {
+            false => IER::IE_0,
+            true => IER::IE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `IE_0`"]
+    #[inline]
+    pub fn is_ie_0(&self) -> bool {
+        *self == IER::IE_0
+    }
+    #[doc = "Checks if the value of the field is `IE_1`"]
+    #[inline]
+    pub fn is_ie_1(&self) -> bool {
+        *self == IER::IE_1
+    }
+}
+#[doc = "Possible values of the field `MODE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum MODER {
+    #[doc = "Timer is in free-running mode"]
+    MODE_0,
+    #[doc = "Timer is in periodic mode"]
+    MODE_1,
+}
+impl MODER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            MODER::MODE_0 => false,
+            MODER::MODE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> MODER {
+        match value {
+            false => MODER::MODE_0,
+            true => MODER::MODE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `MODE_0`"]
+    #[inline]
+    pub fn is_mode_0(&self) -> bool {
+        *self == MODER::MODE_0
+    }
+    #[doc = "Checks if the value of the field is `MODE_1`"]
+    #[inline]
+    pub fn is_mode_1(&self) -> bool {
+        *self == MODER::MODE_1
+    }
+}
+#[doc = "Possible values of the field `ENABLE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ENABLER {
+    #[doc = "Timer disabled"]
+    ENABLE_0,
+    #[doc = "Timer enabled"]
+    ENABLE_1,
+}
+impl ENABLER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ENABLER::ENABLE_0 => false,
+            ENABLER::ENABLE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ENABLER {
+        match value {
+            false => ENABLER::ENABLE_0,
+            true => ENABLER::ENABLE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ENABLE_0`"]
+    #[inline]
+    pub fn is_enable_0(&self) -> bool {
+        *self == ENABLER::ENABLE_0
+    }
+    #[doc = "Checks if the value of the field is `ENABLE_1`"]
+    #[inline]
+    pub fn is_enable_1(&self) -> bool {
+        *self == ENABLER::ENABLE_1
+    }
+}
+#[doc = "Values that can be written to the field `ONESHOT`"]
+pub enum ONESHOTW {
+    #[doc = "wrapping mode"]
+    ONESHOT_0,
+    #[doc = "one-shot mode"]
+    ONESHOT_1,
+}
+impl ONESHOTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ONESHOTW::ONESHOT_0 => false,
+            ONESHOTW::ONESHOT_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ONESHOTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ONESHOTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ONESHOTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "wrapping mode"]
+    #[inline]
+    pub fn oneshot_0(self) -> &'a mut W {
+        self.variant(ONESHOTW::ONESHOT_0)
+    }
+    #[doc = "one-shot mode"]
+    #[inline]
+    pub fn oneshot_1(self) -> &'a mut W {
+        self.variant(ONESHOTW::ONESHOT_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `SIZE`"]
+pub enum SIZEW {
+    #[doc = "16-bit counter"]
+    SIZE_0,
+    #[doc = "32-bit counter"]
+    SIZE_1,
+}
+impl SIZEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            SIZEW::SIZE_0 => false,
+            SIZEW::SIZE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SIZEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SIZEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SIZEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "16-bit counter"]
+    #[inline]
+    pub fn size_0(self) -> &'a mut W {
+        self.variant(SIZEW::SIZE_0)
+    }
+    #[doc = "32-bit counter"]
+    #[inline]
+    pub fn size_1(self) -> &'a mut W {
+        self.variant(SIZEW::SIZE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `PRESCALE`"]
+pub enum PRESCALEW {
+    #[doc = "0 stages of prescale, clock is divided by 1"]
+    PRESCALE_0,
+    #[doc = "4 stages of prescale, clock is divided by 16"]
+    PRESCALE_1,
+    #[doc = "8 stages of prescale, clock is divided by 256"]
+    PRESCALE_2,
+}
+impl PRESCALEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            PRESCALEW::PRESCALE_0 => 0,
+            PRESCALEW::PRESCALE_1 => 1,
+            PRESCALEW::PRESCALE_2 => 2,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PRESCALEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PRESCALEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: PRESCALEW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "0 stages of prescale, clock is divided by 1"]
+    #[inline]
+    pub fn prescale_0(self) -> &'a mut W {
+        self.variant(PRESCALEW::PRESCALE_0)
+    }
+    #[doc = "4 stages of prescale, clock is divided by 16"]
+    #[inline]
+    pub fn prescale_1(self) -> &'a mut W {
+        self.variant(PRESCALEW::PRESCALE_1)
+    }
+    #[doc = "8 stages of prescale, clock is divided by 256"]
+    #[inline]
+    pub fn prescale_2(self) -> &'a mut W {
+        self.variant(PRESCALEW::PRESCALE_2)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `IE`"]
+pub enum IEW {
+    #[doc = "Timer interrupt disabled"]
+    IE_0,
+    #[doc = "Timer interrupt enabled"]
+    IE_1,
+}
+impl IEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            IEW::IE_0 => false,
+            IEW::IE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _IEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _IEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: IEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Timer interrupt disabled"]
+    #[inline]
+    pub fn ie_0(self) -> &'a mut W {
+        self.variant(IEW::IE_0)
+    }
+    #[doc = "Timer interrupt enabled"]
+    #[inline]
+    pub fn ie_1(self) -> &'a mut W {
+        self.variant(IEW::IE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `MODE`"]
+pub enum MODEW {
+    #[doc = "Timer is in free-running mode"]
+    MODE_0,
+    #[doc = "Timer is in periodic mode"]
+    MODE_1,
+}
+impl MODEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            MODEW::MODE_0 => false,
+            MODEW::MODE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MODEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MODEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: MODEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Timer is in free-running mode"]
+    #[inline]
+    pub fn mode_0(self) -> &'a mut W {
+        self.variant(MODEW::MODE_0)
+    }
+    #[doc = "Timer is in periodic mode"]
+    #[inline]
+    pub fn mode_1(self) -> &'a mut W {
+        self.variant(MODEW::MODE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ENABLE`"]
+pub enum ENABLEW {
+    #[doc = "Timer disabled"]
+    ENABLE_0,
+    #[doc = "Timer enabled"]
+    ENABLE_1,
+}
+impl ENABLEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ENABLEW::ENABLE_0 => false,
+            ENABLEW::ENABLE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ENABLEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ENABLEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ENABLEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Timer disabled"]
+    #[inline]
+    pub fn enable_0(self) -> &'a mut W {
+        self.variant(ENABLEW::ENABLE_0)
+    }
+    #[doc = "Timer enabled"]
+    #[inline]
+    pub fn enable_1(self) -> &'a mut W {
+        self.variant(ENABLEW::ENABLE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Selects one-shot or wrapping counter mode"]
+    #[inline]
+    pub fn oneshot(&self) -> ONESHOTR {
+        ONESHOTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - Selects 16 or 32 bit counter operation"]
+    #[inline]
+    pub fn size(&self) -> SIZER {
+        SIZER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 2:3 - Prescale bits"]
+    #[inline]
+    pub fn prescale(&self) -> PRESCALER {
+        PRESCALER::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 5 - Interrupt enable bit"]
+    #[inline]
+    pub fn ie(&self) -> IER {
+        IER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 6 - Mode bit"]
+    #[inline]
+    pub fn mode(&self) -> MODER {
+        MODER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 7 - Enable bit"]
+    #[inline]
+    pub fn enable(&self) -> ENABLER {
+        ENABLER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 32 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Selects one-shot or wrapping counter mode"]
+    #[inline]
+    pub fn oneshot(&mut self) -> _ONESHOTW {
+        _ONESHOTW { w: self }
+    }
+    #[doc = "Bit 1 - Selects 16 or 32 bit counter operation"]
+    #[inline]
+    pub fn size(&mut self) -> _SIZEW {
+        _SIZEW { w: self }
+    }
+    #[doc = "Bits 2:3 - Prescale bits"]
+    #[inline]
+    pub fn prescale(&mut self) -> _PRESCALEW {
+        _PRESCALEW { w: self }
+    }
+    #[doc = "Bit 5 - Interrupt enable bit"]
+    #[inline]
+    pub fn ie(&mut self) -> _IEW {
+        _IEW { w: self }
+    }
+    #[doc = "Bit 6 - Mode bit"]
+    #[inline]
+    pub fn mode(&mut self) -> _MODEW {
+        _MODEW { w: self }
+    }
+    #[doc = "Bit 7 - Enable bit"]
+    #[inline]
+    pub fn enable(&mut self) -> _ENABLEW {
+        _ENABLEW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/timer32/t32control2.rs b/example-source/msp432p401r/src/timer32/t32control2.rs
new file mode 100644
index 0000000..adbb7d7
--- /dev/null
+++ b/example-source/msp432p401r/src/timer32/t32control2.rs
@@ -0,0 +1,779 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::T32CONTROL2 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `ONESHOT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ONESHOTR {
+    #[doc = "wrapping mode"]
+    ONESHOT_0,
+    #[doc = "one-shot mode"]
+    ONESHOT_1,
+}
+impl ONESHOTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ONESHOTR::ONESHOT_0 => false,
+            ONESHOTR::ONESHOT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ONESHOTR {
+        match value {
+            false => ONESHOTR::ONESHOT_0,
+            true => ONESHOTR::ONESHOT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ONESHOT_0`"]
+    #[inline]
+    pub fn is_oneshot_0(&self) -> bool {
+        *self == ONESHOTR::ONESHOT_0
+    }
+    #[doc = "Checks if the value of the field is `ONESHOT_1`"]
+    #[inline]
+    pub fn is_oneshot_1(&self) -> bool {
+        *self == ONESHOTR::ONESHOT_1
+    }
+}
+#[doc = "Possible values of the field `SIZE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SIZER {
+    #[doc = "16-bit counter"]
+    SIZE_0,
+    #[doc = "32-bit counter"]
+    SIZE_1,
+}
+impl SIZER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            SIZER::SIZE_0 => false,
+            SIZER::SIZE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> SIZER {
+        match value {
+            false => SIZER::SIZE_0,
+            true => SIZER::SIZE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SIZE_0`"]
+    #[inline]
+    pub fn is_size_0(&self) -> bool {
+        *self == SIZER::SIZE_0
+    }
+    #[doc = "Checks if the value of the field is `SIZE_1`"]
+    #[inline]
+    pub fn is_size_1(&self) -> bool {
+        *self == SIZER::SIZE_1
+    }
+}
+#[doc = "Possible values of the field `PRESCALE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PRESCALER {
+    #[doc = "0 stages of prescale, clock is divided by 1"]
+    PRESCALE_0,
+    #[doc = "4 stages of prescale, clock is divided by 16"]
+    PRESCALE_1,
+    #[doc = "8 stages of prescale, clock is divided by 256"]
+    PRESCALE_2,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl PRESCALER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            PRESCALER::PRESCALE_0 => 0,
+            PRESCALER::PRESCALE_1 => 1,
+            PRESCALER::PRESCALE_2 => 2,
+            PRESCALER::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> PRESCALER {
+        match value {
+            0 => PRESCALER::PRESCALE_0,
+            1 => PRESCALER::PRESCALE_1,
+            2 => PRESCALER::PRESCALE_2,
+            i => PRESCALER::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `PRESCALE_0`"]
+    #[inline]
+    pub fn is_prescale_0(&self) -> bool {
+        *self == PRESCALER::PRESCALE_0
+    }
+    #[doc = "Checks if the value of the field is `PRESCALE_1`"]
+    #[inline]
+    pub fn is_prescale_1(&self) -> bool {
+        *self == PRESCALER::PRESCALE_1
+    }
+    #[doc = "Checks if the value of the field is `PRESCALE_2`"]
+    #[inline]
+    pub fn is_prescale_2(&self) -> bool {
+        *self == PRESCALER::PRESCALE_2
+    }
+}
+#[doc = "Possible values of the field `IE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IER {
+    #[doc = "Timer interrupt disabled"]
+    IE_0,
+    #[doc = "Timer interrupt enabled"]
+    IE_1,
+}
+impl IER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            IER::IE_0 => false,
+            IER::IE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> IER {
+        match value {
+            false => IER::IE_0,
+            true => IER::IE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `IE_0`"]
+    #[inline]
+    pub fn is_ie_0(&self) -> bool {
+        *self == IER::IE_0
+    }
+    #[doc = "Checks if the value of the field is `IE_1`"]
+    #[inline]
+    pub fn is_ie_1(&self) -> bool {
+        *self == IER::IE_1
+    }
+}
+#[doc = "Possible values of the field `MODE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum MODER {
+    #[doc = "Timer is in free-running mode"]
+    MODE_0,
+    #[doc = "Timer is in periodic mode"]
+    MODE_1,
+}
+impl MODER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            MODER::MODE_0 => false,
+            MODER::MODE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> MODER {
+        match value {
+            false => MODER::MODE_0,
+            true => MODER::MODE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `MODE_0`"]
+    #[inline]
+    pub fn is_mode_0(&self) -> bool {
+        *self == MODER::MODE_0
+    }
+    #[doc = "Checks if the value of the field is `MODE_1`"]
+    #[inline]
+    pub fn is_mode_1(&self) -> bool {
+        *self == MODER::MODE_1
+    }
+}
+#[doc = "Possible values of the field `ENABLE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ENABLER {
+    #[doc = "Timer disabled"]
+    ENABLE_0,
+    #[doc = "Timer enabled"]
+    ENABLE_1,
+}
+impl ENABLER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ENABLER::ENABLE_0 => false,
+            ENABLER::ENABLE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ENABLER {
+        match value {
+            false => ENABLER::ENABLE_0,
+            true => ENABLER::ENABLE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ENABLE_0`"]
+    #[inline]
+    pub fn is_enable_0(&self) -> bool {
+        *self == ENABLER::ENABLE_0
+    }
+    #[doc = "Checks if the value of the field is `ENABLE_1`"]
+    #[inline]
+    pub fn is_enable_1(&self) -> bool {
+        *self == ENABLER::ENABLE_1
+    }
+}
+#[doc = "Values that can be written to the field `ONESHOT`"]
+pub enum ONESHOTW {
+    #[doc = "wrapping mode"]
+    ONESHOT_0,
+    #[doc = "one-shot mode"]
+    ONESHOT_1,
+}
+impl ONESHOTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ONESHOTW::ONESHOT_0 => false,
+            ONESHOTW::ONESHOT_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ONESHOTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ONESHOTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ONESHOTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "wrapping mode"]
+    #[inline]
+    pub fn oneshot_0(self) -> &'a mut W {
+        self.variant(ONESHOTW::ONESHOT_0)
+    }
+    #[doc = "one-shot mode"]
+    #[inline]
+    pub fn oneshot_1(self) -> &'a mut W {
+        self.variant(ONESHOTW::ONESHOT_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `SIZE`"]
+pub enum SIZEW {
+    #[doc = "16-bit counter"]
+    SIZE_0,
+    #[doc = "32-bit counter"]
+    SIZE_1,
+}
+impl SIZEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            SIZEW::SIZE_0 => false,
+            SIZEW::SIZE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SIZEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SIZEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SIZEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "16-bit counter"]
+    #[inline]
+    pub fn size_0(self) -> &'a mut W {
+        self.variant(SIZEW::SIZE_0)
+    }
+    #[doc = "32-bit counter"]
+    #[inline]
+    pub fn size_1(self) -> &'a mut W {
+        self.variant(SIZEW::SIZE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `PRESCALE`"]
+pub enum PRESCALEW {
+    #[doc = "0 stages of prescale, clock is divided by 1"]
+    PRESCALE_0,
+    #[doc = "4 stages of prescale, clock is divided by 16"]
+    PRESCALE_1,
+    #[doc = "8 stages of prescale, clock is divided by 256"]
+    PRESCALE_2,
+}
+impl PRESCALEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            PRESCALEW::PRESCALE_0 => 0,
+            PRESCALEW::PRESCALE_1 => 1,
+            PRESCALEW::PRESCALE_2 => 2,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PRESCALEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PRESCALEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: PRESCALEW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "0 stages of prescale, clock is divided by 1"]
+    #[inline]
+    pub fn prescale_0(self) -> &'a mut W {
+        self.variant(PRESCALEW::PRESCALE_0)
+    }
+    #[doc = "4 stages of prescale, clock is divided by 16"]
+    #[inline]
+    pub fn prescale_1(self) -> &'a mut W {
+        self.variant(PRESCALEW::PRESCALE_1)
+    }
+    #[doc = "8 stages of prescale, clock is divided by 256"]
+    #[inline]
+    pub fn prescale_2(self) -> &'a mut W {
+        self.variant(PRESCALEW::PRESCALE_2)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `IE`"]
+pub enum IEW {
+    #[doc = "Timer interrupt disabled"]
+    IE_0,
+    #[doc = "Timer interrupt enabled"]
+    IE_1,
+}
+impl IEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            IEW::IE_0 => false,
+            IEW::IE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _IEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _IEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: IEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Timer interrupt disabled"]
+    #[inline]
+    pub fn ie_0(self) -> &'a mut W {
+        self.variant(IEW::IE_0)
+    }
+    #[doc = "Timer interrupt enabled"]
+    #[inline]
+    pub fn ie_1(self) -> &'a mut W {
+        self.variant(IEW::IE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `MODE`"]
+pub enum MODEW {
+    #[doc = "Timer is in free-running mode"]
+    MODE_0,
+    #[doc = "Timer is in periodic mode"]
+    MODE_1,
+}
+impl MODEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            MODEW::MODE_0 => false,
+            MODEW::MODE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MODEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MODEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: MODEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Timer is in free-running mode"]
+    #[inline]
+    pub fn mode_0(self) -> &'a mut W {
+        self.variant(MODEW::MODE_0)
+    }
+    #[doc = "Timer is in periodic mode"]
+    #[inline]
+    pub fn mode_1(self) -> &'a mut W {
+        self.variant(MODEW::MODE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ENABLE`"]
+pub enum ENABLEW {
+    #[doc = "Timer disabled"]
+    ENABLE_0,
+    #[doc = "Timer enabled"]
+    ENABLE_1,
+}
+impl ENABLEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ENABLEW::ENABLE_0 => false,
+            ENABLEW::ENABLE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ENABLEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ENABLEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ENABLEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Timer disabled"]
+    #[inline]
+    pub fn enable_0(self) -> &'a mut W {
+        self.variant(ENABLEW::ENABLE_0)
+    }
+    #[doc = "Timer enabled"]
+    #[inline]
+    pub fn enable_1(self) -> &'a mut W {
+        self.variant(ENABLEW::ENABLE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Selects one-shot or wrapping counter mode"]
+    #[inline]
+    pub fn oneshot(&self) -> ONESHOTR {
+        ONESHOTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - Selects 16 or 32 bit counter operation"]
+    #[inline]
+    pub fn size(&self) -> SIZER {
+        SIZER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 2:3 - Prescale bits"]
+    #[inline]
+    pub fn prescale(&self) -> PRESCALER {
+        PRESCALER::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 5 - Interrupt enable bit"]
+    #[inline]
+    pub fn ie(&self) -> IER {
+        IER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 6 - Mode bit"]
+    #[inline]
+    pub fn mode(&self) -> MODER {
+        MODER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 7 - Enable bit"]
+    #[inline]
+    pub fn enable(&self) -> ENABLER {
+        ENABLER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 32 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Selects one-shot or wrapping counter mode"]
+    #[inline]
+    pub fn oneshot(&mut self) -> _ONESHOTW {
+        _ONESHOTW { w: self }
+    }
+    #[doc = "Bit 1 - Selects 16 or 32 bit counter operation"]
+    #[inline]
+    pub fn size(&mut self) -> _SIZEW {
+        _SIZEW { w: self }
+    }
+    #[doc = "Bits 2:3 - Prescale bits"]
+    #[inline]
+    pub fn prescale(&mut self) -> _PRESCALEW {
+        _PRESCALEW { w: self }
+    }
+    #[doc = "Bit 5 - Interrupt enable bit"]
+    #[inline]
+    pub fn ie(&mut self) -> _IEW {
+        _IEW { w: self }
+    }
+    #[doc = "Bit 6 - Mode bit"]
+    #[inline]
+    pub fn mode(&mut self) -> _MODEW {
+        _MODEW { w: self }
+    }
+    #[doc = "Bit 7 - Enable bit"]
+    #[inline]
+    pub fn enable(&mut self) -> _ENABLEW {
+        _ENABLEW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/timer32/t32intclr1.rs b/example-source/msp432p401r/src/timer32/t32intclr1.rs
new file mode 100644
index 0000000..5d318f7
--- /dev/null
+++ b/example-source/msp432p401r/src/timer32/t32intclr1.rs
@@ -0,0 +1,49 @@
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::T32INTCLR1 {
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+}
+#[doc = r" Proxy"]
+pub struct _INTCLRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _INTCLRW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Write clears interrupt output"]
+    #[inline]
+    pub fn intclr(&mut self) -> _INTCLRW {
+        _INTCLRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/timer32/t32intclr2.rs b/example-source/msp432p401r/src/timer32/t32intclr2.rs
new file mode 100644
index 0000000..9a9b944
--- /dev/null
+++ b/example-source/msp432p401r/src/timer32/t32intclr2.rs
@@ -0,0 +1,49 @@
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::T32INTCLR2 {
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+}
+#[doc = r" Proxy"]
+pub struct _INTCLRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _INTCLRW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Write clears the interrupt output"]
+    #[inline]
+    pub fn intclr(&mut self) -> _INTCLRW {
+        _INTCLRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/timer32/t32load1.rs b/example-source/msp432p401r/src/timer32/t32load1.rs
new file mode 100644
index 0000000..c9d575e
--- /dev/null
+++ b/example-source/msp432p401r/src/timer32/t32load1.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::T32LOAD1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct LOADR {
+    bits: u32,
+}
+impl LOADR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _LOADW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _LOADW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - The value from which the Timer 1 counter decrements"]
+    #[inline]
+    pub fn load(&self) -> LOADR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        LOADR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - The value from which the Timer 1 counter decrements"]
+    #[inline]
+    pub fn load(&mut self) -> _LOADW {
+        _LOADW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/timer32/t32load2.rs b/example-source/msp432p401r/src/timer32/t32load2.rs
new file mode 100644
index 0000000..69d1b94
--- /dev/null
+++ b/example-source/msp432p401r/src/timer32/t32load2.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::T32LOAD2 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct LOADR {
+    bits: u32,
+}
+impl LOADR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _LOADW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _LOADW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - The value from which the Timer 2 counter decrements"]
+    #[inline]
+    pub fn load(&self) -> LOADR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        LOADR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - The value from which the Timer 2 counter decrements"]
+    #[inline]
+    pub fn load(&mut self) -> _LOADW {
+        _LOADW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/timer32/t32mis1.rs b/example-source/msp432p401r/src/timer32/t32mis1.rs
new file mode 100644
index 0000000..9284733
--- /dev/null
+++ b/example-source/msp432p401r/src/timer32/t32mis1.rs
@@ -0,0 +1,51 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::T32MIS1 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct IFGR {
+    bits: bool,
+}
+impl IFGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Enabled interrupt status"]
+    #[inline]
+    pub fn ifg(&self) -> IFGR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        IFGR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/timer32/t32mis2.rs b/example-source/msp432p401r/src/timer32/t32mis2.rs
new file mode 100644
index 0000000..6a1267a
--- /dev/null
+++ b/example-source/msp432p401r/src/timer32/t32mis2.rs
@@ -0,0 +1,51 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::T32MIS2 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct IFGR {
+    bits: bool,
+}
+impl IFGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Enabled interrupt status"]
+    #[inline]
+    pub fn ifg(&self) -> IFGR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        IFGR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/timer32/t32ris1.rs b/example-source/msp432p401r/src/timer32/t32ris1.rs
new file mode 100644
index 0000000..f30e056
--- /dev/null
+++ b/example-source/msp432p401r/src/timer32/t32ris1.rs
@@ -0,0 +1,51 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::T32RIS1 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct RAW_IFGR {
+    bits: bool,
+}
+impl RAW_IFGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Raw interrupt status"]
+    #[inline]
+    pub fn raw_ifg(&self) -> RAW_IFGR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        RAW_IFGR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/timer32/t32ris2.rs b/example-source/msp432p401r/src/timer32/t32ris2.rs
new file mode 100644
index 0000000..7b68aa9
--- /dev/null
+++ b/example-source/msp432p401r/src/timer32/t32ris2.rs
@@ -0,0 +1,51 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::T32RIS2 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct RAW_IFGR {
+    bits: bool,
+}
+impl RAW_IFGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Raw interrupt status"]
+    #[inline]
+    pub fn raw_ifg(&self) -> RAW_IFGR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        RAW_IFGR { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/timer32/t32value1.rs b/example-source/msp432p401r/src/timer32/t32value1.rs
new file mode 100644
index 0000000..6141b25
--- /dev/null
+++ b/example-source/msp432p401r/src/timer32/t32value1.rs
@@ -0,0 +1,41 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::T32VALUE1 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct VALUER {
+    bits: u32,
+}
+impl VALUER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Current value"]
+    #[inline]
+    pub fn value(&self) -> VALUER {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        VALUER { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/timer32/t32value2.rs b/example-source/msp432p401r/src/timer32/t32value2.rs
new file mode 100644
index 0000000..c6153db
--- /dev/null
+++ b/example-source/msp432p401r/src/timer32/t32value2.rs
@@ -0,0 +1,41 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::T32VALUE2 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct VALUER {
+    bits: u32,
+}
+impl VALUER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Current value of the decrementing counter"]
+    #[inline]
+    pub fn value(&self) -> VALUER {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        VALUER { bits }
+    }
+}
diff --git a/example-source/msp432p401r/src/timer_a0.rs b/example-source/msp432p401r/src/timer_a0.rs
new file mode 100644
index 0000000..89bd30a
--- /dev/null
+++ b/example-source/msp432p401r/src/timer_a0.rs
@@ -0,0 +1,55 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - TimerAx Control Register"]
+    pub tax_ctl: TAXCTL,
+    #[doc = "0x02 - Timer_A Capture/Compare Control Register"]
+    pub tax_cctl: [TAXCCTL; 5],
+    _reserved0: [u8; 4usize],
+    #[doc = "0x10 - TimerA register"]
+    pub tax_r: TAXR,
+    #[doc = "0x12 - Timer_A Capture/Compare Register"]
+    pub tax_ccr: [TAXCCR; 5],
+    _reserved1: [u8; 4usize],
+    #[doc = "0x20 - TimerAx Expansion 0 Register"]
+    pub tax_ex0: TAXEX0,
+    _reserved2: [u8; 12usize],
+    #[doc = "0x2e - TimerAx Interrupt Vector Register"]
+    pub tax_iv: TAXIV,
+}
+#[doc = "TimerAx Control Register"]
+pub struct TAXCTL {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "TimerAx Control Register"]
+pub mod tax_ctl;
+#[doc = "Timer_A Capture/Compare Control Register"]
+pub struct TAXCCTL {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Timer_A Capture/Compare Control Register"]
+pub mod tax_cctl;
+#[doc = "TimerA register"]
+pub struct TAXR {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "TimerA register"]
+pub mod tax_r;
+#[doc = "Timer_A Capture/Compare Register"]
+pub struct TAXCCR {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Timer_A Capture/Compare Register"]
+pub mod tax_ccr;
+#[doc = "TimerAx Expansion 0 Register"]
+pub struct TAXEX0 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "TimerAx Expansion 0 Register"]
+pub mod tax_ex0;
+#[doc = "TimerAx Interrupt Vector Register"]
+pub struct TAXIV {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "TimerAx Interrupt Vector Register"]
+pub mod tax_iv;
diff --git a/example-source/msp432p401r/src/timer_a0/tax_ccr.rs b/example-source/msp432p401r/src/timer_a0/tax_ccr.rs
new file mode 100644
index 0000000..f533aed
--- /dev/null
+++ b/example-source/msp432p401r/src/timer_a0/tax_ccr.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::TAXCCR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct TAXRR {
+    bits: u16,
+}
+impl TAXRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TAXRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TAXRW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - TimerA register"]
+    #[inline]
+    pub fn tax_r(&self) -> TAXRR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        TAXRR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - TimerA register"]
+    #[inline]
+    pub fn tax_r(&mut self) -> _TAXRW {
+        _TAXRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/timer_a0/tax_cctl.rs b/example-source/msp432p401r/src/timer_a0/tax_cctl.rs
new file mode 100644
index 0000000..65d41c1
--- /dev/null
+++ b/example-source/msp432p401r/src/timer_a0/tax_cctl.rs
@@ -0,0 +1,1344 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::TAXCCTL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `CCIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CCIFGR {
+    #[doc = "No interrupt pending"]
+    CCIFG_0,
+    #[doc = "Interrupt pending"]
+    CCIFG_1,
+}
+impl CCIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CCIFGR::CCIFG_0 => false,
+            CCIFGR::CCIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CCIFGR {
+        match value {
+            false => CCIFGR::CCIFG_0,
+            true => CCIFGR::CCIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CCIFG_0`"]
+    #[inline]
+    pub fn is_ccifg_0(&self) -> bool {
+        *self == CCIFGR::CCIFG_0
+    }
+    #[doc = "Checks if the value of the field is `CCIFG_1`"]
+    #[inline]
+    pub fn is_ccifg_1(&self) -> bool {
+        *self == CCIFGR::CCIFG_1
+    }
+}
+#[doc = "Possible values of the field `COV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum COVR {
+    #[doc = "No capture overflow occurred"]
+    COV_0,
+    #[doc = "Capture overflow occurred"]
+    COV_1,
+}
+impl COVR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            COVR::COV_0 => false,
+            COVR::COV_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> COVR {
+        match value {
+            false => COVR::COV_0,
+            true => COVR::COV_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `COV_0`"]
+    #[inline]
+    pub fn is_cov_0(&self) -> bool {
+        *self == COVR::COV_0
+    }
+    #[doc = "Checks if the value of the field is `COV_1`"]
+    #[inline]
+    pub fn is_cov_1(&self) -> bool {
+        *self == COVR::COV_1
+    }
+}
+#[doc = "Possible values of the field `OUT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum OUTR {
+    #[doc = "Output low"]
+    OUT_0,
+    #[doc = "Output high"]
+    OUT_1,
+}
+impl OUTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            OUTR::OUT_0 => false,
+            OUTR::OUT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> OUTR {
+        match value {
+            false => OUTR::OUT_0,
+            true => OUTR::OUT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `OUT_0`"]
+    #[inline]
+    pub fn is_out_0(&self) -> bool {
+        *self == OUTR::OUT_0
+    }
+    #[doc = "Checks if the value of the field is `OUT_1`"]
+    #[inline]
+    pub fn is_out_1(&self) -> bool {
+        *self == OUTR::OUT_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CCIR {
+    bits: bool,
+}
+impl CCIR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `CCIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CCIER {
+    #[doc = "Interrupt disabled"]
+    CCIE_0,
+    #[doc = "Interrupt enabled"]
+    CCIE_1,
+}
+impl CCIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CCIER::CCIE_0 => false,
+            CCIER::CCIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CCIER {
+        match value {
+            false => CCIER::CCIE_0,
+            true => CCIER::CCIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CCIE_0`"]
+    #[inline]
+    pub fn is_ccie_0(&self) -> bool {
+        *self == CCIER::CCIE_0
+    }
+    #[doc = "Checks if the value of the field is `CCIE_1`"]
+    #[inline]
+    pub fn is_ccie_1(&self) -> bool {
+        *self == CCIER::CCIE_1
+    }
+}
+#[doc = "Possible values of the field `OUTMOD`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum OUTMODR {
+    #[doc = "OUT bit value"]
+    OUTMOD_0,
+    #[doc = "Set"]
+    OUTMOD_1,
+    #[doc = "Toggle/reset"]
+    OUTMOD_2,
+    #[doc = "Set/reset"]
+    OUTMOD_3,
+    #[doc = "Toggle"]
+    OUTMOD_4,
+    #[doc = "Reset"]
+    OUTMOD_5,
+    #[doc = "Toggle/set"]
+    OUTMOD_6,
+    #[doc = "Reset/set"]
+    OUTMOD_7,
+}
+impl OUTMODR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            OUTMODR::OUTMOD_0 => 0,
+            OUTMODR::OUTMOD_1 => 1,
+            OUTMODR::OUTMOD_2 => 2,
+            OUTMODR::OUTMOD_3 => 3,
+            OUTMODR::OUTMOD_4 => 4,
+            OUTMODR::OUTMOD_5 => 5,
+            OUTMODR::OUTMOD_6 => 6,
+            OUTMODR::OUTMOD_7 => 7,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> OUTMODR {
+        match value {
+            0 => OUTMODR::OUTMOD_0,
+            1 => OUTMODR::OUTMOD_1,
+            2 => OUTMODR::OUTMOD_2,
+            3 => OUTMODR::OUTMOD_3,
+            4 => OUTMODR::OUTMOD_4,
+            5 => OUTMODR::OUTMOD_5,
+            6 => OUTMODR::OUTMOD_6,
+            7 => OUTMODR::OUTMOD_7,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_0`"]
+    #[inline]
+    pub fn is_outmod_0(&self) -> bool {
+        *self == OUTMODR::OUTMOD_0
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_1`"]
+    #[inline]
+    pub fn is_outmod_1(&self) -> bool {
+        *self == OUTMODR::OUTMOD_1
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_2`"]
+    #[inline]
+    pub fn is_outmod_2(&self) -> bool {
+        *self == OUTMODR::OUTMOD_2
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_3`"]
+    #[inline]
+    pub fn is_outmod_3(&self) -> bool {
+        *self == OUTMODR::OUTMOD_3
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_4`"]
+    #[inline]
+    pub fn is_outmod_4(&self) -> bool {
+        *self == OUTMODR::OUTMOD_4
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_5`"]
+    #[inline]
+    pub fn is_outmod_5(&self) -> bool {
+        *self == OUTMODR::OUTMOD_5
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_6`"]
+    #[inline]
+    pub fn is_outmod_6(&self) -> bool {
+        *self == OUTMODR::OUTMOD_6
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_7`"]
+    #[inline]
+    pub fn is_outmod_7(&self) -> bool {
+        *self == OUTMODR::OUTMOD_7
+    }
+}
+#[doc = "Possible values of the field `CAP`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CAPR {
+    #[doc = "Compare mode"]
+    CAP_0,
+    #[doc = "Capture mode"]
+    CAP_1,
+}
+impl CAPR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CAPR::CAP_0 => false,
+            CAPR::CAP_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CAPR {
+        match value {
+            false => CAPR::CAP_0,
+            true => CAPR::CAP_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CAP_0`"]
+    #[inline]
+    pub fn is_cap_0(&self) -> bool {
+        *self == CAPR::CAP_0
+    }
+    #[doc = "Checks if the value of the field is `CAP_1`"]
+    #[inline]
+    pub fn is_cap_1(&self) -> bool {
+        *self == CAPR::CAP_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SCCIR {
+    bits: bool,
+}
+impl SCCIR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `SCS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SCSR {
+    #[doc = "Asynchronous capture"]
+    SCS_0,
+    #[doc = "Synchronous capture"]
+    SCS_1,
+}
+impl SCSR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            SCSR::SCS_0 => false,
+            SCSR::SCS_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> SCSR {
+        match value {
+            false => SCSR::SCS_0,
+            true => SCSR::SCS_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SCS_0`"]
+    #[inline]
+    pub fn is_scs_0(&self) -> bool {
+        *self == SCSR::SCS_0
+    }
+    #[doc = "Checks if the value of the field is `SCS_1`"]
+    #[inline]
+    pub fn is_scs_1(&self) -> bool {
+        *self == SCSR::SCS_1
+    }
+}
+#[doc = "Possible values of the field `CCIS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CCISR {
+    #[doc = "CCIxA"]
+    CCIS_0,
+    #[doc = "CCIxB"]
+    CCIS_1,
+    #[doc = "GND"]
+    CCIS_2,
+    #[doc = "VCC"]
+    CCIS_3,
+}
+impl CCISR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            CCISR::CCIS_0 => 0,
+            CCISR::CCIS_1 => 1,
+            CCISR::CCIS_2 => 2,
+            CCISR::CCIS_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> CCISR {
+        match value {
+            0 => CCISR::CCIS_0,
+            1 => CCISR::CCIS_1,
+            2 => CCISR::CCIS_2,
+            3 => CCISR::CCIS_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `CCIS_0`"]
+    #[inline]
+    pub fn is_ccis_0(&self) -> bool {
+        *self == CCISR::CCIS_0
+    }
+    #[doc = "Checks if the value of the field is `CCIS_1`"]
+    #[inline]
+    pub fn is_ccis_1(&self) -> bool {
+        *self == CCISR::CCIS_1
+    }
+    #[doc = "Checks if the value of the field is `CCIS_2`"]
+    #[inline]
+    pub fn is_ccis_2(&self) -> bool {
+        *self == CCISR::CCIS_2
+    }
+    #[doc = "Checks if the value of the field is `CCIS_3`"]
+    #[inline]
+    pub fn is_ccis_3(&self) -> bool {
+        *self == CCISR::CCIS_3
+    }
+}
+#[doc = "Possible values of the field `CM`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CMR {
+    #[doc = "No capture"]
+    CM_0,
+    #[doc = "Capture on rising edge"]
+    CM_1,
+    #[doc = "Capture on falling edge"]
+    CM_2,
+    #[doc = "Capture on both rising and falling edges"]
+    CM_3,
+}
+impl CMR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            CMR::CM_0 => 0,
+            CMR::CM_1 => 1,
+            CMR::CM_2 => 2,
+            CMR::CM_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> CMR {
+        match value {
+            0 => CMR::CM_0,
+            1 => CMR::CM_1,
+            2 => CMR::CM_2,
+            3 => CMR::CM_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `CM_0`"]
+    #[inline]
+    pub fn is_cm_0(&self) -> bool {
+        *self == CMR::CM_0
+    }
+    #[doc = "Checks if the value of the field is `CM_1`"]
+    #[inline]
+    pub fn is_cm_1(&self) -> bool {
+        *self == CMR::CM_1
+    }
+    #[doc = "Checks if the value of the field is `CM_2`"]
+    #[inline]
+    pub fn is_cm_2(&self) -> bool {
+        *self == CMR::CM_2
+    }
+    #[doc = "Checks if the value of the field is `CM_3`"]
+    #[inline]
+    pub fn is_cm_3(&self) -> bool {
+        *self == CMR::CM_3
+    }
+}
+#[doc = "Values that can be written to the field `CCIFG`"]
+pub enum CCIFGW {
+    #[doc = "No interrupt pending"]
+    CCIFG_0,
+    #[doc = "Interrupt pending"]
+    CCIFG_1,
+}
+impl CCIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CCIFGW::CCIFG_0 => false,
+            CCIFGW::CCIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CCIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CCIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CCIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ccifg_0(self) -> &'a mut W {
+        self.variant(CCIFGW::CCIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ccifg_1(self) -> &'a mut W {
+        self.variant(CCIFGW::CCIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `COV`"]
+pub enum COVW {
+    #[doc = "No capture overflow occurred"]
+    COV_0,
+    #[doc = "Capture overflow occurred"]
+    COV_1,
+}
+impl COVW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            COVW::COV_0 => false,
+            COVW::COV_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _COVW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _COVW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: COVW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No capture overflow occurred"]
+    #[inline]
+    pub fn cov_0(self) -> &'a mut W {
+        self.variant(COVW::COV_0)
+    }
+    #[doc = "Capture overflow occurred"]
+    #[inline]
+    pub fn cov_1(self) -> &'a mut W {
+        self.variant(COVW::COV_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `OUT`"]
+pub enum OUTW {
+    #[doc = "Output low"]
+    OUT_0,
+    #[doc = "Output high"]
+    OUT_1,
+}
+impl OUTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            OUTW::OUT_0 => false,
+            OUTW::OUT_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _OUTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _OUTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: OUTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Output low"]
+    #[inline]
+    pub fn out_0(self) -> &'a mut W {
+        self.variant(OUTW::OUT_0)
+    }
+    #[doc = "Output high"]
+    #[inline]
+    pub fn out_1(self) -> &'a mut W {
+        self.variant(OUTW::OUT_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CCIE`"]
+pub enum CCIEW {
+    #[doc = "Interrupt disabled"]
+    CCIE_0,
+    #[doc = "Interrupt enabled"]
+    CCIE_1,
+}
+impl CCIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CCIEW::CCIE_0 => false,
+            CCIEW::CCIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CCIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CCIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CCIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ccie_0(self) -> &'a mut W {
+        self.variant(CCIEW::CCIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ccie_1(self) -> &'a mut W {
+        self.variant(CCIEW::CCIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `OUTMOD`"]
+pub enum OUTMODW {
+    #[doc = "OUT bit value"]
+    OUTMOD_0,
+    #[doc = "Set"]
+    OUTMOD_1,
+    #[doc = "Toggle/reset"]
+    OUTMOD_2,
+    #[doc = "Set/reset"]
+    OUTMOD_3,
+    #[doc = "Toggle"]
+    OUTMOD_4,
+    #[doc = "Reset"]
+    OUTMOD_5,
+    #[doc = "Toggle/set"]
+    OUTMOD_6,
+    #[doc = "Reset/set"]
+    OUTMOD_7,
+}
+impl OUTMODW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            OUTMODW::OUTMOD_0 => 0,
+            OUTMODW::OUTMOD_1 => 1,
+            OUTMODW::OUTMOD_2 => 2,
+            OUTMODW::OUTMOD_3 => 3,
+            OUTMODW::OUTMOD_4 => 4,
+            OUTMODW::OUTMOD_5 => 5,
+            OUTMODW::OUTMOD_6 => 6,
+            OUTMODW::OUTMOD_7 => 7,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _OUTMODW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _OUTMODW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: OUTMODW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "OUT bit value"]
+    #[inline]
+    pub fn outmod_0(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_0)
+    }
+    #[doc = "Set"]
+    #[inline]
+    pub fn outmod_1(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_1)
+    }
+    #[doc = "Toggle/reset"]
+    #[inline]
+    pub fn outmod_2(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_2)
+    }
+    #[doc = "Set/reset"]
+    #[inline]
+    pub fn outmod_3(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_3)
+    }
+    #[doc = "Toggle"]
+    #[inline]
+    pub fn outmod_4(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_4)
+    }
+    #[doc = "Reset"]
+    #[inline]
+    pub fn outmod_5(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_5)
+    }
+    #[doc = "Toggle/set"]
+    #[inline]
+    pub fn outmod_6(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_6)
+    }
+    #[doc = "Reset/set"]
+    #[inline]
+    pub fn outmod_7(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_7)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CAP`"]
+pub enum CAPW {
+    #[doc = "Compare mode"]
+    CAP_0,
+    #[doc = "Capture mode"]
+    CAP_1,
+}
+impl CAPW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CAPW::CAP_0 => false,
+            CAPW::CAP_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CAPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CAPW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CAPW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Compare mode"]
+    #[inline]
+    pub fn cap_0(self) -> &'a mut W {
+        self.variant(CAPW::CAP_0)
+    }
+    #[doc = "Capture mode"]
+    #[inline]
+    pub fn cap_1(self) -> &'a mut W {
+        self.variant(CAPW::CAP_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SCCIW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SCCIW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `SCS`"]
+pub enum SCSW {
+    #[doc = "Asynchronous capture"]
+    SCS_0,
+    #[doc = "Synchronous capture"]
+    SCS_1,
+}
+impl SCSW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            SCSW::SCS_0 => false,
+            SCSW::SCS_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SCSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SCSW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SCSW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Asynchronous capture"]
+    #[inline]
+    pub fn scs_0(self) -> &'a mut W {
+        self.variant(SCSW::SCS_0)
+    }
+    #[doc = "Synchronous capture"]
+    #[inline]
+    pub fn scs_1(self) -> &'a mut W {
+        self.variant(SCSW::SCS_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CCIS`"]
+pub enum CCISW {
+    #[doc = "CCIxA"]
+    CCIS_0,
+    #[doc = "CCIxB"]
+    CCIS_1,
+    #[doc = "GND"]
+    CCIS_2,
+    #[doc = "VCC"]
+    CCIS_3,
+}
+impl CCISW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            CCISW::CCIS_0 => 0,
+            CCISW::CCIS_1 => 1,
+            CCISW::CCIS_2 => 2,
+            CCISW::CCIS_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CCISW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CCISW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CCISW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "CCIxA"]
+    #[inline]
+    pub fn ccis_0(self) -> &'a mut W {
+        self.variant(CCISW::CCIS_0)
+    }
+    #[doc = "CCIxB"]
+    #[inline]
+    pub fn ccis_1(self) -> &'a mut W {
+        self.variant(CCISW::CCIS_1)
+    }
+    #[doc = "GND"]
+    #[inline]
+    pub fn ccis_2(self) -> &'a mut W {
+        self.variant(CCISW::CCIS_2)
+    }
+    #[doc = "VCC"]
+    #[inline]
+    pub fn ccis_3(self) -> &'a mut W {
+        self.variant(CCISW::CCIS_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CM`"]
+pub enum CMW {
+    #[doc = "No capture"]
+    CM_0,
+    #[doc = "Capture on rising edge"]
+    CM_1,
+    #[doc = "Capture on falling edge"]
+    CM_2,
+    #[doc = "Capture on both rising and falling edges"]
+    CM_3,
+}
+impl CMW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            CMW::CM_0 => 0,
+            CMW::CM_1 => 1,
+            CMW::CM_2 => 2,
+            CMW::CM_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CMW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CMW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CMW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "No capture"]
+    #[inline]
+    pub fn cm_0(self) -> &'a mut W {
+        self.variant(CMW::CM_0)
+    }
+    #[doc = "Capture on rising edge"]
+    #[inline]
+    pub fn cm_1(self) -> &'a mut W {
+        self.variant(CMW::CM_1)
+    }
+    #[doc = "Capture on falling edge"]
+    #[inline]
+    pub fn cm_2(self) -> &'a mut W {
+        self.variant(CMW::CM_2)
+    }
+    #[doc = "Capture on both rising and falling edges"]
+    #[inline]
+    pub fn cm_3(self) -> &'a mut W {
+        self.variant(CMW::CM_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Capture/compare interrupt flag"]
+    #[inline]
+    pub fn ccifg(&self) -> CCIFGR {
+        CCIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Capture overflow"]
+    #[inline]
+    pub fn cov(&self) -> COVR {
+        COVR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - Output"]
+    #[inline]
+    pub fn out(&self) -> OUTR {
+        OUTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Capture/compare input"]
+    #[inline]
+    pub fn cci(&self) -> CCIR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        };
+        CCIR { bits }
+    }
+    #[doc = "Bit 4 - Capture/compare interrupt enable"]
+    #[inline]
+    pub fn ccie(&self) -> CCIER {
+        CCIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 5:7 - Output mode"]
+    #[inline]
+    pub fn outmod(&self) -> OUTMODR {
+        OUTMODR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 8 - Capture mode"]
+    #[inline]
+    pub fn cap(&self) -> CAPR {
+        CAPR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 10 - Synchronized capture/compare input"]
+    #[inline]
+    pub fn scci(&self) -> SCCIR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        };
+        SCCIR { bits }
+    }
+    #[doc = "Bit 11 - Synchronize capture source"]
+    #[inline]
+    pub fn scs(&self) -> SCSR {
+        SCSR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 12:13 - Capture/compare input select"]
+    #[inline]
+    pub fn ccis(&self) -> CCISR {
+        CCISR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bits 14:15 - Capture mode"]
+    #[inline]
+    pub fn cm(&self) -> CMR {
+        CMR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Capture/compare interrupt flag"]
+    #[inline]
+    pub fn ccifg(&mut self) -> _CCIFGW {
+        _CCIFGW { w: self }
+    }
+    #[doc = "Bit 1 - Capture overflow"]
+    #[inline]
+    pub fn cov(&mut self) -> _COVW {
+        _COVW { w: self }
+    }
+    #[doc = "Bit 2 - Output"]
+    #[inline]
+    pub fn out(&mut self) -> _OUTW {
+        _OUTW { w: self }
+    }
+    #[doc = "Bit 4 - Capture/compare interrupt enable"]
+    #[inline]
+    pub fn ccie(&mut self) -> _CCIEW {
+        _CCIEW { w: self }
+    }
+    #[doc = "Bits 5:7 - Output mode"]
+    #[inline]
+    pub fn outmod(&mut self) -> _OUTMODW {
+        _OUTMODW { w: self }
+    }
+    #[doc = "Bit 8 - Capture mode"]
+    #[inline]
+    pub fn cap(&mut self) -> _CAPW {
+        _CAPW { w: self }
+    }
+    #[doc = "Bit 10 - Synchronized capture/compare input"]
+    #[inline]
+    pub fn scci(&mut self) -> _SCCIW {
+        _SCCIW { w: self }
+    }
+    #[doc = "Bit 11 - Synchronize capture source"]
+    #[inline]
+    pub fn scs(&mut self) -> _SCSW {
+        _SCSW { w: self }
+    }
+    #[doc = "Bits 12:13 - Capture/compare input select"]
+    #[inline]
+    pub fn ccis(&mut self) -> _CCISW {
+        _CCISW { w: self }
+    }
+    #[doc = "Bits 14:15 - Capture mode"]
+    #[inline]
+    pub fn cm(&mut self) -> _CMW {
+        _CMW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/timer_a0/tax_ctl.rs b/example-source/msp432p401r/src/timer_a0/tax_ctl.rs
new file mode 100644
index 0000000..938a26f
--- /dev/null
+++ b/example-source/msp432p401r/src/timer_a0/tax_ctl.rs
@@ -0,0 +1,769 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::TAXCTL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `TAIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TAIFGR {
+    #[doc = "No interrupt pending"]
+    TAIFG_0,
+    #[doc = "Interrupt pending"]
+    TAIFG_1,
+}
+impl TAIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TAIFGR::TAIFG_0 => false,
+            TAIFGR::TAIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TAIFGR {
+        match value {
+            false => TAIFGR::TAIFG_0,
+            true => TAIFGR::TAIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `TAIFG_0`"]
+    #[inline]
+    pub fn is_taifg_0(&self) -> bool {
+        *self == TAIFGR::TAIFG_0
+    }
+    #[doc = "Checks if the value of the field is `TAIFG_1`"]
+    #[inline]
+    pub fn is_taifg_1(&self) -> bool {
+        *self == TAIFGR::TAIFG_1
+    }
+}
+#[doc = "Possible values of the field `TAIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TAIER {
+    #[doc = "Interrupt disabled"]
+    TAIE_0,
+    #[doc = "Interrupt enabled"]
+    TAIE_1,
+}
+impl TAIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TAIER::TAIE_0 => false,
+            TAIER::TAIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TAIER {
+        match value {
+            false => TAIER::TAIE_0,
+            true => TAIER::TAIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `TAIE_0`"]
+    #[inline]
+    pub fn is_taie_0(&self) -> bool {
+        *self == TAIER::TAIE_0
+    }
+    #[doc = "Checks if the value of the field is `TAIE_1`"]
+    #[inline]
+    pub fn is_taie_1(&self) -> bool {
+        *self == TAIER::TAIE_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct TACLRR {
+    bits: bool,
+}
+impl TACLRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `MC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum MCR {
+    #[doc = "Stop mode: Timer is halted"]
+    MC_0,
+    #[doc = "Up mode: Timer counts up to TAxCCR0"]
+    MC_1,
+    #[doc = "Continuous mode: Timer counts up to 0FFFFh"]
+    MC_2,
+    #[doc = "Up/down mode: Timer counts up to TAxCCR0 then down to 0000h"]
+    MC_3,
+}
+impl MCR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            MCR::MC_0 => 0,
+            MCR::MC_1 => 1,
+            MCR::MC_2 => 2,
+            MCR::MC_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> MCR {
+        match value {
+            0 => MCR::MC_0,
+            1 => MCR::MC_1,
+            2 => MCR::MC_2,
+            3 => MCR::MC_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `MC_0`"]
+    #[inline]
+    pub fn is_mc_0(&self) -> bool {
+        *self == MCR::MC_0
+    }
+    #[doc = "Checks if the value of the field is `MC_1`"]
+    #[inline]
+    pub fn is_mc_1(&self) -> bool {
+        *self == MCR::MC_1
+    }
+    #[doc = "Checks if the value of the field is `MC_2`"]
+    #[inline]
+    pub fn is_mc_2(&self) -> bool {
+        *self == MCR::MC_2
+    }
+    #[doc = "Checks if the value of the field is `MC_3`"]
+    #[inline]
+    pub fn is_mc_3(&self) -> bool {
+        *self == MCR::MC_3
+    }
+}
+#[doc = "Possible values of the field `ID`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IDR {
+    #[doc = "/1"]
+    ID_0,
+    #[doc = "/2"]
+    ID_1,
+    #[doc = "/4"]
+    ID_2,
+    #[doc = "/8"]
+    ID_3,
+}
+impl IDR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            IDR::ID_0 => 0,
+            IDR::ID_1 => 1,
+            IDR::ID_2 => 2,
+            IDR::ID_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> IDR {
+        match value {
+            0 => IDR::ID_0,
+            1 => IDR::ID_1,
+            2 => IDR::ID_2,
+            3 => IDR::ID_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `ID_0`"]
+    #[inline]
+    pub fn is_id_0(&self) -> bool {
+        *self == IDR::ID_0
+    }
+    #[doc = "Checks if the value of the field is `ID_1`"]
+    #[inline]
+    pub fn is_id_1(&self) -> bool {
+        *self == IDR::ID_1
+    }
+    #[doc = "Checks if the value of the field is `ID_2`"]
+    #[inline]
+    pub fn is_id_2(&self) -> bool {
+        *self == IDR::ID_2
+    }
+    #[doc = "Checks if the value of the field is `ID_3`"]
+    #[inline]
+    pub fn is_id_3(&self) -> bool {
+        *self == IDR::ID_3
+    }
+}
+#[doc = "Possible values of the field `TASSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TASSELR {
+    #[doc = "TAxCLK"]
+    TASSEL_0,
+    #[doc = "ACLK"]
+    TASSEL_1,
+    #[doc = "SMCLK"]
+    TASSEL_2,
+    #[doc = "INCLK"]
+    TASSEL_3,
+}
+impl TASSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            TASSELR::TASSEL_0 => 0,
+            TASSELR::TASSEL_1 => 1,
+            TASSELR::TASSEL_2 => 2,
+            TASSELR::TASSEL_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> TASSELR {
+        match value {
+            0 => TASSELR::TASSEL_0,
+            1 => TASSELR::TASSEL_1,
+            2 => TASSELR::TASSEL_2,
+            3 => TASSELR::TASSEL_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `TASSEL_0`"]
+    #[inline]
+    pub fn is_tassel_0(&self) -> bool {
+        *self == TASSELR::TASSEL_0
+    }
+    #[doc = "Checks if the value of the field is `TASSEL_1`"]
+    #[inline]
+    pub fn is_tassel_1(&self) -> bool {
+        *self == TASSELR::TASSEL_1
+    }
+    #[doc = "Checks if the value of the field is `TASSEL_2`"]
+    #[inline]
+    pub fn is_tassel_2(&self) -> bool {
+        *self == TASSELR::TASSEL_2
+    }
+    #[doc = "Checks if the value of the field is `TASSEL_3`"]
+    #[inline]
+    pub fn is_tassel_3(&self) -> bool {
+        *self == TASSELR::TASSEL_3
+    }
+}
+#[doc = "Values that can be written to the field `TAIFG`"]
+pub enum TAIFGW {
+    #[doc = "No interrupt pending"]
+    TAIFG_0,
+    #[doc = "Interrupt pending"]
+    TAIFG_1,
+}
+impl TAIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TAIFGW::TAIFG_0 => false,
+            TAIFGW::TAIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TAIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TAIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TAIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn taifg_0(self) -> &'a mut W {
+        self.variant(TAIFGW::TAIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn taifg_1(self) -> &'a mut W {
+        self.variant(TAIFGW::TAIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TAIE`"]
+pub enum TAIEW {
+    #[doc = "Interrupt disabled"]
+    TAIE_0,
+    #[doc = "Interrupt enabled"]
+    TAIE_1,
+}
+impl TAIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TAIEW::TAIE_0 => false,
+            TAIEW::TAIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TAIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TAIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TAIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn taie_0(self) -> &'a mut W {
+        self.variant(TAIEW::TAIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn taie_1(self) -> &'a mut W {
+        self.variant(TAIEW::TAIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TACLRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TACLRW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `MC`"]
+pub enum MCW {
+    #[doc = "Stop mode: Timer is halted"]
+    MC_0,
+    #[doc = "Up mode: Timer counts up to TAxCCR0"]
+    MC_1,
+    #[doc = "Continuous mode: Timer counts up to 0FFFFh"]
+    MC_2,
+    #[doc = "Up/down mode: Timer counts up to TAxCCR0 then down to 0000h"]
+    MC_3,
+}
+impl MCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            MCW::MC_0 => 0,
+            MCW::MC_1 => 1,
+            MCW::MC_2 => 2,
+            MCW::MC_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: MCW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Stop mode: Timer is halted"]
+    #[inline]
+    pub fn mc_0(self) -> &'a mut W {
+        self.variant(MCW::MC_0)
+    }
+    #[doc = "Up mode: Timer counts up to TAxCCR0"]
+    #[inline]
+    pub fn mc_1(self) -> &'a mut W {
+        self.variant(MCW::MC_1)
+    }
+    #[doc = "Continuous mode: Timer counts up to 0FFFFh"]
+    #[inline]
+    pub fn mc_2(self) -> &'a mut W {
+        self.variant(MCW::MC_2)
+    }
+    #[doc = "Up/down mode: Timer counts up to TAxCCR0 then down to 0000h"]
+    #[inline]
+    pub fn mc_3(self) -> &'a mut W {
+        self.variant(MCW::MC_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ID`"]
+pub enum IDW {
+    #[doc = "/1"]
+    ID_0,
+    #[doc = "/2"]
+    ID_1,
+    #[doc = "/4"]
+    ID_2,
+    #[doc = "/8"]
+    ID_3,
+}
+impl IDW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            IDW::ID_0 => 0,
+            IDW::ID_1 => 1,
+            IDW::ID_2 => 2,
+            IDW::ID_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _IDW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _IDW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: IDW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "/1"]
+    #[inline]
+    pub fn id_0(self) -> &'a mut W {
+        self.variant(IDW::ID_0)
+    }
+    #[doc = "/2"]
+    #[inline]
+    pub fn id_1(self) -> &'a mut W {
+        self.variant(IDW::ID_1)
+    }
+    #[doc = "/4"]
+    #[inline]
+    pub fn id_2(self) -> &'a mut W {
+        self.variant(IDW::ID_2)
+    }
+    #[doc = "/8"]
+    #[inline]
+    pub fn id_3(self) -> &'a mut W {
+        self.variant(IDW::ID_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TASSEL`"]
+pub enum TASSELW {
+    #[doc = "TAxCLK"]
+    TASSEL_0,
+    #[doc = "ACLK"]
+    TASSEL_1,
+    #[doc = "SMCLK"]
+    TASSEL_2,
+    #[doc = "INCLK"]
+    TASSEL_3,
+}
+impl TASSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            TASSELW::TASSEL_0 => 0,
+            TASSELW::TASSEL_1 => 1,
+            TASSELW::TASSEL_2 => 2,
+            TASSELW::TASSEL_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TASSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TASSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TASSELW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "TAxCLK"]
+    #[inline]
+    pub fn tassel_0(self) -> &'a mut W {
+        self.variant(TASSELW::TASSEL_0)
+    }
+    #[doc = "ACLK"]
+    #[inline]
+    pub fn tassel_1(self) -> &'a mut W {
+        self.variant(TASSELW::TASSEL_1)
+    }
+    #[doc = "SMCLK"]
+    #[inline]
+    pub fn tassel_2(self) -> &'a mut W {
+        self.variant(TASSELW::TASSEL_2)
+    }
+    #[doc = "INCLK"]
+    #[inline]
+    pub fn tassel_3(self) -> &'a mut W {
+        self.variant(TASSELW::TASSEL_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - TimerA interrupt flag"]
+    #[inline]
+    pub fn taifg(&self) -> TAIFGR {
+        TAIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - TimerA interrupt enable"]
+    #[inline]
+    pub fn taie(&self) -> TAIER {
+        TAIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - TimerA clear"]
+    #[inline]
+    pub fn taclr(&self) -> TACLRR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        };
+        TACLRR { bits }
+    }
+    #[doc = "Bits 4:5 - Mode control"]
+    #[inline]
+    pub fn mc(&self) -> MCR {
+        MCR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bits 6:7 - Input divider"]
+    #[inline]
+    pub fn id(&self) -> IDR {
+        IDR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bits 8:9 - TimerA clock source select"]
+    #[inline]
+    pub fn tassel(&self) -> TASSELR {
+        TASSELR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - TimerA interrupt flag"]
+    #[inline]
+    pub fn taifg(&mut self) -> _TAIFGW {
+        _TAIFGW { w: self }
+    }
+    #[doc = "Bit 1 - TimerA interrupt enable"]
+    #[inline]
+    pub fn taie(&mut self) -> _TAIEW {
+        _TAIEW { w: self }
+    }
+    #[doc = "Bit 2 - TimerA clear"]
+    #[inline]
+    pub fn taclr(&mut self) -> _TACLRW {
+        _TACLRW { w: self }
+    }
+    #[doc = "Bits 4:5 - Mode control"]
+    #[inline]
+    pub fn mc(&mut self) -> _MCW {
+        _MCW { w: self }
+    }
+    #[doc = "Bits 6:7 - Input divider"]
+    #[inline]
+    pub fn id(&mut self) -> _IDW {
+        _IDW { w: self }
+    }
+    #[doc = "Bits 8:9 - TimerA clock source select"]
+    #[inline]
+    pub fn tassel(&mut self) -> _TASSELW {
+        _TASSELW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/timer_a0/tax_ex0.rs b/example-source/msp432p401r/src/timer_a0/tax_ex0.rs
new file mode 100644
index 0000000..cc9bd3f
--- /dev/null
+++ b/example-source/msp432p401r/src/timer_a0/tax_ex0.rs
@@ -0,0 +1,268 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::TAXEX0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `TAIDEX`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TAIDEXR {
+    #[doc = "Divide by 1"]
+    TAIDEX_0,
+    #[doc = "Divide by 2"]
+    TAIDEX_1,
+    #[doc = "Divide by 3"]
+    TAIDEX_2,
+    #[doc = "Divide by 4"]
+    TAIDEX_3,
+    #[doc = "Divide by 5"]
+    TAIDEX_4,
+    #[doc = "Divide by 6"]
+    TAIDEX_5,
+    #[doc = "Divide by 7"]
+    TAIDEX_6,
+    #[doc = "Divide by 8"]
+    TAIDEX_7,
+}
+impl TAIDEXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            TAIDEXR::TAIDEX_0 => 0,
+            TAIDEXR::TAIDEX_1 => 1,
+            TAIDEXR::TAIDEX_2 => 2,
+            TAIDEXR::TAIDEX_3 => 3,
+            TAIDEXR::TAIDEX_4 => 4,
+            TAIDEXR::TAIDEX_5 => 5,
+            TAIDEXR::TAIDEX_6 => 6,
+            TAIDEXR::TAIDEX_7 => 7,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> TAIDEXR {
+        match value {
+            0 => TAIDEXR::TAIDEX_0,
+            1 => TAIDEXR::TAIDEX_1,
+            2 => TAIDEXR::TAIDEX_2,
+            3 => TAIDEXR::TAIDEX_3,
+            4 => TAIDEXR::TAIDEX_4,
+            5 => TAIDEXR::TAIDEX_5,
+            6 => TAIDEXR::TAIDEX_6,
+            7 => TAIDEXR::TAIDEX_7,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_0`"]
+    #[inline]
+    pub fn is_taidex_0(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_0
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_1`"]
+    #[inline]
+    pub fn is_taidex_1(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_1
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_2`"]
+    #[inline]
+    pub fn is_taidex_2(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_2
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_3`"]
+    #[inline]
+    pub fn is_taidex_3(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_3
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_4`"]
+    #[inline]
+    pub fn is_taidex_4(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_4
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_5`"]
+    #[inline]
+    pub fn is_taidex_5(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_5
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_6`"]
+    #[inline]
+    pub fn is_taidex_6(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_6
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_7`"]
+    #[inline]
+    pub fn is_taidex_7(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_7
+    }
+}
+#[doc = "Values that can be written to the field `TAIDEX`"]
+pub enum TAIDEXW {
+    #[doc = "Divide by 1"]
+    TAIDEX_0,
+    #[doc = "Divide by 2"]
+    TAIDEX_1,
+    #[doc = "Divide by 3"]
+    TAIDEX_2,
+    #[doc = "Divide by 4"]
+    TAIDEX_3,
+    #[doc = "Divide by 5"]
+    TAIDEX_4,
+    #[doc = "Divide by 6"]
+    TAIDEX_5,
+    #[doc = "Divide by 7"]
+    TAIDEX_6,
+    #[doc = "Divide by 8"]
+    TAIDEX_7,
+}
+impl TAIDEXW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            TAIDEXW::TAIDEX_0 => 0,
+            TAIDEXW::TAIDEX_1 => 1,
+            TAIDEXW::TAIDEX_2 => 2,
+            TAIDEXW::TAIDEX_3 => 3,
+            TAIDEXW::TAIDEX_4 => 4,
+            TAIDEXW::TAIDEX_5 => 5,
+            TAIDEXW::TAIDEX_6 => 6,
+            TAIDEXW::TAIDEX_7 => 7,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TAIDEXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TAIDEXW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TAIDEXW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Divide by 1"]
+    #[inline]
+    pub fn taidex_0(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_0)
+    }
+    #[doc = "Divide by 2"]
+    #[inline]
+    pub fn taidex_1(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_1)
+    }
+    #[doc = "Divide by 3"]
+    #[inline]
+    pub fn taidex_2(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_2)
+    }
+    #[doc = "Divide by 4"]
+    #[inline]
+    pub fn taidex_3(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_3)
+    }
+    #[doc = "Divide by 5"]
+    #[inline]
+    pub fn taidex_4(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_4)
+    }
+    #[doc = "Divide by 6"]
+    #[inline]
+    pub fn taidex_5(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_5)
+    }
+    #[doc = "Divide by 7"]
+    #[inline]
+    pub fn taidex_6(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_6)
+    }
+    #[doc = "Divide by 8"]
+    #[inline]
+    pub fn taidex_7(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_7)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:2 - Input divider expansion"]
+    #[inline]
+    pub fn taidex(&self) -> TAIDEXR {
+        TAIDEXR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:2 - Input divider expansion"]
+    #[inline]
+    pub fn taidex(&mut self) -> _TAIDEXW {
+        _TAIDEXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/timer_a0/tax_iv.rs b/example-source/msp432p401r/src/timer_a0/tax_iv.rs
new file mode 100644
index 0000000..a83ed36
--- /dev/null
+++ b/example-source/msp432p401r/src/timer_a0/tax_iv.rs
@@ -0,0 +1,124 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::TAXIV {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `TAIV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TAIVR {
+    #[doc = "No interrupt pending"]
+    TAIV_0,
+    #[doc = "Interrupt Source: Capture/compare 1; Interrupt Flag: TAxCCR1 CCIFG; Interrupt Priority: Highest"]
+    TAIV_2,
+    #[doc = "Interrupt Source: Capture/compare 2; Interrupt Flag: TAxCCR2 CCIFG"]
+    TAIV_4,
+    #[doc = "Interrupt Source: Capture/compare 3; Interrupt Flag: TAxCCR3 CCIFG"]
+    TAIV_6,
+    #[doc = "Interrupt Source: Capture/compare 4; Interrupt Flag: TAxCCR4 CCIFG"]
+    TAIV_8,
+    #[doc = "Interrupt Source: Capture/compare 5; Interrupt Flag: TAxCCR5 CCIFG"]
+    TAIV_10,
+    #[doc = "Interrupt Source: Capture/compare 6; Interrupt Flag: TAxCCR6 CCIFG"]
+    TAIV_12,
+    #[doc = "Interrupt Source: Timer overflow; Interrupt Flag: TAxCTL TAIFG; Interrupt Priority: Lowest"]
+    TAIV_14,
+    #[doc = r" Reserved"]
+    _Reserved(u16),
+}
+impl TAIVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        match *self {
+            TAIVR::TAIV_0 => 0,
+            TAIVR::TAIV_2 => 2,
+            TAIVR::TAIV_4 => 4,
+            TAIVR::TAIV_6 => 6,
+            TAIVR::TAIV_8 => 8,
+            TAIVR::TAIV_10 => 10,
+            TAIVR::TAIV_12 => 12,
+            TAIVR::TAIV_14 => 14,
+            TAIVR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u16) -> TAIVR {
+        match value {
+            0 => TAIVR::TAIV_0,
+            2 => TAIVR::TAIV_2,
+            4 => TAIVR::TAIV_4,
+            6 => TAIVR::TAIV_6,
+            8 => TAIVR::TAIV_8,
+            10 => TAIVR::TAIV_10,
+            12 => TAIVR::TAIV_12,
+            14 => TAIVR::TAIV_14,
+            i => TAIVR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `TAIV_0`"]
+    #[inline]
+    pub fn is_taiv_0(&self) -> bool {
+        *self == TAIVR::TAIV_0
+    }
+    #[doc = "Checks if the value of the field is `TAIV_2`"]
+    #[inline]
+    pub fn is_taiv_2(&self) -> bool {
+        *self == TAIVR::TAIV_2
+    }
+    #[doc = "Checks if the value of the field is `TAIV_4`"]
+    #[inline]
+    pub fn is_taiv_4(&self) -> bool {
+        *self == TAIVR::TAIV_4
+    }
+    #[doc = "Checks if the value of the field is `TAIV_6`"]
+    #[inline]
+    pub fn is_taiv_6(&self) -> bool {
+        *self == TAIVR::TAIV_6
+    }
+    #[doc = "Checks if the value of the field is `TAIV_8`"]
+    #[inline]
+    pub fn is_taiv_8(&self) -> bool {
+        *self == TAIVR::TAIV_8
+    }
+    #[doc = "Checks if the value of the field is `TAIV_10`"]
+    #[inline]
+    pub fn is_taiv_10(&self) -> bool {
+        *self == TAIVR::TAIV_10
+    }
+    #[doc = "Checks if the value of the field is `TAIV_12`"]
+    #[inline]
+    pub fn is_taiv_12(&self) -> bool {
+        *self == TAIVR::TAIV_12
+    }
+    #[doc = "Checks if the value of the field is `TAIV_14`"]
+    #[inline]
+    pub fn is_taiv_14(&self) -> bool {
+        *self == TAIVR::TAIV_14
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - TimerA interrupt vector value"]
+    #[inline]
+    pub fn taiv(&self) -> TAIVR {
+        TAIVR::_from({
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/timer_a0/tax_r.rs b/example-source/msp432p401r/src/timer_a0/tax_r.rs
new file mode 100644
index 0000000..3542361
--- /dev/null
+++ b/example-source/msp432p401r/src/timer_a0/tax_r.rs
@@ -0,0 +1,64 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::TAXR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+}
diff --git a/example-source/msp432p401r/src/timer_a1.rs b/example-source/msp432p401r/src/timer_a1.rs
new file mode 100644
index 0000000..89bd30a
--- /dev/null
+++ b/example-source/msp432p401r/src/timer_a1.rs
@@ -0,0 +1,55 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - TimerAx Control Register"]
+    pub tax_ctl: TAXCTL,
+    #[doc = "0x02 - Timer_A Capture/Compare Control Register"]
+    pub tax_cctl: [TAXCCTL; 5],
+    _reserved0: [u8; 4usize],
+    #[doc = "0x10 - TimerA register"]
+    pub tax_r: TAXR,
+    #[doc = "0x12 - Timer_A Capture/Compare Register"]
+    pub tax_ccr: [TAXCCR; 5],
+    _reserved1: [u8; 4usize],
+    #[doc = "0x20 - TimerAx Expansion 0 Register"]
+    pub tax_ex0: TAXEX0,
+    _reserved2: [u8; 12usize],
+    #[doc = "0x2e - TimerAx Interrupt Vector Register"]
+    pub tax_iv: TAXIV,
+}
+#[doc = "TimerAx Control Register"]
+pub struct TAXCTL {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "TimerAx Control Register"]
+pub mod tax_ctl;
+#[doc = "Timer_A Capture/Compare Control Register"]
+pub struct TAXCCTL {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Timer_A Capture/Compare Control Register"]
+pub mod tax_cctl;
+#[doc = "TimerA register"]
+pub struct TAXR {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "TimerA register"]
+pub mod tax_r;
+#[doc = "Timer_A Capture/Compare Register"]
+pub struct TAXCCR {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Timer_A Capture/Compare Register"]
+pub mod tax_ccr;
+#[doc = "TimerAx Expansion 0 Register"]
+pub struct TAXEX0 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "TimerAx Expansion 0 Register"]
+pub mod tax_ex0;
+#[doc = "TimerAx Interrupt Vector Register"]
+pub struct TAXIV {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "TimerAx Interrupt Vector Register"]
+pub mod tax_iv;
diff --git a/example-source/msp432p401r/src/timer_a1/tax_ccr.rs b/example-source/msp432p401r/src/timer_a1/tax_ccr.rs
new file mode 100644
index 0000000..f533aed
--- /dev/null
+++ b/example-source/msp432p401r/src/timer_a1/tax_ccr.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::TAXCCR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct TAXRR {
+    bits: u16,
+}
+impl TAXRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TAXRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TAXRW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - TimerA register"]
+    #[inline]
+    pub fn tax_r(&self) -> TAXRR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        TAXRR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - TimerA register"]
+    #[inline]
+    pub fn tax_r(&mut self) -> _TAXRW {
+        _TAXRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/timer_a1/tax_cctl.rs b/example-source/msp432p401r/src/timer_a1/tax_cctl.rs
new file mode 100644
index 0000000..65d41c1
--- /dev/null
+++ b/example-source/msp432p401r/src/timer_a1/tax_cctl.rs
@@ -0,0 +1,1344 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::TAXCCTL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `CCIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CCIFGR {
+    #[doc = "No interrupt pending"]
+    CCIFG_0,
+    #[doc = "Interrupt pending"]
+    CCIFG_1,
+}
+impl CCIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CCIFGR::CCIFG_0 => false,
+            CCIFGR::CCIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CCIFGR {
+        match value {
+            false => CCIFGR::CCIFG_0,
+            true => CCIFGR::CCIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CCIFG_0`"]
+    #[inline]
+    pub fn is_ccifg_0(&self) -> bool {
+        *self == CCIFGR::CCIFG_0
+    }
+    #[doc = "Checks if the value of the field is `CCIFG_1`"]
+    #[inline]
+    pub fn is_ccifg_1(&self) -> bool {
+        *self == CCIFGR::CCIFG_1
+    }
+}
+#[doc = "Possible values of the field `COV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum COVR {
+    #[doc = "No capture overflow occurred"]
+    COV_0,
+    #[doc = "Capture overflow occurred"]
+    COV_1,
+}
+impl COVR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            COVR::COV_0 => false,
+            COVR::COV_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> COVR {
+        match value {
+            false => COVR::COV_0,
+            true => COVR::COV_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `COV_0`"]
+    #[inline]
+    pub fn is_cov_0(&self) -> bool {
+        *self == COVR::COV_0
+    }
+    #[doc = "Checks if the value of the field is `COV_1`"]
+    #[inline]
+    pub fn is_cov_1(&self) -> bool {
+        *self == COVR::COV_1
+    }
+}
+#[doc = "Possible values of the field `OUT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum OUTR {
+    #[doc = "Output low"]
+    OUT_0,
+    #[doc = "Output high"]
+    OUT_1,
+}
+impl OUTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            OUTR::OUT_0 => false,
+            OUTR::OUT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> OUTR {
+        match value {
+            false => OUTR::OUT_0,
+            true => OUTR::OUT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `OUT_0`"]
+    #[inline]
+    pub fn is_out_0(&self) -> bool {
+        *self == OUTR::OUT_0
+    }
+    #[doc = "Checks if the value of the field is `OUT_1`"]
+    #[inline]
+    pub fn is_out_1(&self) -> bool {
+        *self == OUTR::OUT_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CCIR {
+    bits: bool,
+}
+impl CCIR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `CCIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CCIER {
+    #[doc = "Interrupt disabled"]
+    CCIE_0,
+    #[doc = "Interrupt enabled"]
+    CCIE_1,
+}
+impl CCIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CCIER::CCIE_0 => false,
+            CCIER::CCIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CCIER {
+        match value {
+            false => CCIER::CCIE_0,
+            true => CCIER::CCIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CCIE_0`"]
+    #[inline]
+    pub fn is_ccie_0(&self) -> bool {
+        *self == CCIER::CCIE_0
+    }
+    #[doc = "Checks if the value of the field is `CCIE_1`"]
+    #[inline]
+    pub fn is_ccie_1(&self) -> bool {
+        *self == CCIER::CCIE_1
+    }
+}
+#[doc = "Possible values of the field `OUTMOD`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum OUTMODR {
+    #[doc = "OUT bit value"]
+    OUTMOD_0,
+    #[doc = "Set"]
+    OUTMOD_1,
+    #[doc = "Toggle/reset"]
+    OUTMOD_2,
+    #[doc = "Set/reset"]
+    OUTMOD_3,
+    #[doc = "Toggle"]
+    OUTMOD_4,
+    #[doc = "Reset"]
+    OUTMOD_5,
+    #[doc = "Toggle/set"]
+    OUTMOD_6,
+    #[doc = "Reset/set"]
+    OUTMOD_7,
+}
+impl OUTMODR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            OUTMODR::OUTMOD_0 => 0,
+            OUTMODR::OUTMOD_1 => 1,
+            OUTMODR::OUTMOD_2 => 2,
+            OUTMODR::OUTMOD_3 => 3,
+            OUTMODR::OUTMOD_4 => 4,
+            OUTMODR::OUTMOD_5 => 5,
+            OUTMODR::OUTMOD_6 => 6,
+            OUTMODR::OUTMOD_7 => 7,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> OUTMODR {
+        match value {
+            0 => OUTMODR::OUTMOD_0,
+            1 => OUTMODR::OUTMOD_1,
+            2 => OUTMODR::OUTMOD_2,
+            3 => OUTMODR::OUTMOD_3,
+            4 => OUTMODR::OUTMOD_4,
+            5 => OUTMODR::OUTMOD_5,
+            6 => OUTMODR::OUTMOD_6,
+            7 => OUTMODR::OUTMOD_7,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_0`"]
+    #[inline]
+    pub fn is_outmod_0(&self) -> bool {
+        *self == OUTMODR::OUTMOD_0
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_1`"]
+    #[inline]
+    pub fn is_outmod_1(&self) -> bool {
+        *self == OUTMODR::OUTMOD_1
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_2`"]
+    #[inline]
+    pub fn is_outmod_2(&self) -> bool {
+        *self == OUTMODR::OUTMOD_2
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_3`"]
+    #[inline]
+    pub fn is_outmod_3(&self) -> bool {
+        *self == OUTMODR::OUTMOD_3
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_4`"]
+    #[inline]
+    pub fn is_outmod_4(&self) -> bool {
+        *self == OUTMODR::OUTMOD_4
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_5`"]
+    #[inline]
+    pub fn is_outmod_5(&self) -> bool {
+        *self == OUTMODR::OUTMOD_5
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_6`"]
+    #[inline]
+    pub fn is_outmod_6(&self) -> bool {
+        *self == OUTMODR::OUTMOD_6
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_7`"]
+    #[inline]
+    pub fn is_outmod_7(&self) -> bool {
+        *self == OUTMODR::OUTMOD_7
+    }
+}
+#[doc = "Possible values of the field `CAP`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CAPR {
+    #[doc = "Compare mode"]
+    CAP_0,
+    #[doc = "Capture mode"]
+    CAP_1,
+}
+impl CAPR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CAPR::CAP_0 => false,
+            CAPR::CAP_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CAPR {
+        match value {
+            false => CAPR::CAP_0,
+            true => CAPR::CAP_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CAP_0`"]
+    #[inline]
+    pub fn is_cap_0(&self) -> bool {
+        *self == CAPR::CAP_0
+    }
+    #[doc = "Checks if the value of the field is `CAP_1`"]
+    #[inline]
+    pub fn is_cap_1(&self) -> bool {
+        *self == CAPR::CAP_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SCCIR {
+    bits: bool,
+}
+impl SCCIR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `SCS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SCSR {
+    #[doc = "Asynchronous capture"]
+    SCS_0,
+    #[doc = "Synchronous capture"]
+    SCS_1,
+}
+impl SCSR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            SCSR::SCS_0 => false,
+            SCSR::SCS_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> SCSR {
+        match value {
+            false => SCSR::SCS_0,
+            true => SCSR::SCS_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SCS_0`"]
+    #[inline]
+    pub fn is_scs_0(&self) -> bool {
+        *self == SCSR::SCS_0
+    }
+    #[doc = "Checks if the value of the field is `SCS_1`"]
+    #[inline]
+    pub fn is_scs_1(&self) -> bool {
+        *self == SCSR::SCS_1
+    }
+}
+#[doc = "Possible values of the field `CCIS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CCISR {
+    #[doc = "CCIxA"]
+    CCIS_0,
+    #[doc = "CCIxB"]
+    CCIS_1,
+    #[doc = "GND"]
+    CCIS_2,
+    #[doc = "VCC"]
+    CCIS_3,
+}
+impl CCISR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            CCISR::CCIS_0 => 0,
+            CCISR::CCIS_1 => 1,
+            CCISR::CCIS_2 => 2,
+            CCISR::CCIS_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> CCISR {
+        match value {
+            0 => CCISR::CCIS_0,
+            1 => CCISR::CCIS_1,
+            2 => CCISR::CCIS_2,
+            3 => CCISR::CCIS_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `CCIS_0`"]
+    #[inline]
+    pub fn is_ccis_0(&self) -> bool {
+        *self == CCISR::CCIS_0
+    }
+    #[doc = "Checks if the value of the field is `CCIS_1`"]
+    #[inline]
+    pub fn is_ccis_1(&self) -> bool {
+        *self == CCISR::CCIS_1
+    }
+    #[doc = "Checks if the value of the field is `CCIS_2`"]
+    #[inline]
+    pub fn is_ccis_2(&self) -> bool {
+        *self == CCISR::CCIS_2
+    }
+    #[doc = "Checks if the value of the field is `CCIS_3`"]
+    #[inline]
+    pub fn is_ccis_3(&self) -> bool {
+        *self == CCISR::CCIS_3
+    }
+}
+#[doc = "Possible values of the field `CM`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CMR {
+    #[doc = "No capture"]
+    CM_0,
+    #[doc = "Capture on rising edge"]
+    CM_1,
+    #[doc = "Capture on falling edge"]
+    CM_2,
+    #[doc = "Capture on both rising and falling edges"]
+    CM_3,
+}
+impl CMR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            CMR::CM_0 => 0,
+            CMR::CM_1 => 1,
+            CMR::CM_2 => 2,
+            CMR::CM_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> CMR {
+        match value {
+            0 => CMR::CM_0,
+            1 => CMR::CM_1,
+            2 => CMR::CM_2,
+            3 => CMR::CM_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `CM_0`"]
+    #[inline]
+    pub fn is_cm_0(&self) -> bool {
+        *self == CMR::CM_0
+    }
+    #[doc = "Checks if the value of the field is `CM_1`"]
+    #[inline]
+    pub fn is_cm_1(&self) -> bool {
+        *self == CMR::CM_1
+    }
+    #[doc = "Checks if the value of the field is `CM_2`"]
+    #[inline]
+    pub fn is_cm_2(&self) -> bool {
+        *self == CMR::CM_2
+    }
+    #[doc = "Checks if the value of the field is `CM_3`"]
+    #[inline]
+    pub fn is_cm_3(&self) -> bool {
+        *self == CMR::CM_3
+    }
+}
+#[doc = "Values that can be written to the field `CCIFG`"]
+pub enum CCIFGW {
+    #[doc = "No interrupt pending"]
+    CCIFG_0,
+    #[doc = "Interrupt pending"]
+    CCIFG_1,
+}
+impl CCIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CCIFGW::CCIFG_0 => false,
+            CCIFGW::CCIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CCIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CCIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CCIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ccifg_0(self) -> &'a mut W {
+        self.variant(CCIFGW::CCIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ccifg_1(self) -> &'a mut W {
+        self.variant(CCIFGW::CCIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `COV`"]
+pub enum COVW {
+    #[doc = "No capture overflow occurred"]
+    COV_0,
+    #[doc = "Capture overflow occurred"]
+    COV_1,
+}
+impl COVW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            COVW::COV_0 => false,
+            COVW::COV_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _COVW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _COVW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: COVW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No capture overflow occurred"]
+    #[inline]
+    pub fn cov_0(self) -> &'a mut W {
+        self.variant(COVW::COV_0)
+    }
+    #[doc = "Capture overflow occurred"]
+    #[inline]
+    pub fn cov_1(self) -> &'a mut W {
+        self.variant(COVW::COV_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `OUT`"]
+pub enum OUTW {
+    #[doc = "Output low"]
+    OUT_0,
+    #[doc = "Output high"]
+    OUT_1,
+}
+impl OUTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            OUTW::OUT_0 => false,
+            OUTW::OUT_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _OUTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _OUTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: OUTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Output low"]
+    #[inline]
+    pub fn out_0(self) -> &'a mut W {
+        self.variant(OUTW::OUT_0)
+    }
+    #[doc = "Output high"]
+    #[inline]
+    pub fn out_1(self) -> &'a mut W {
+        self.variant(OUTW::OUT_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CCIE`"]
+pub enum CCIEW {
+    #[doc = "Interrupt disabled"]
+    CCIE_0,
+    #[doc = "Interrupt enabled"]
+    CCIE_1,
+}
+impl CCIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CCIEW::CCIE_0 => false,
+            CCIEW::CCIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CCIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CCIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CCIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ccie_0(self) -> &'a mut W {
+        self.variant(CCIEW::CCIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ccie_1(self) -> &'a mut W {
+        self.variant(CCIEW::CCIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `OUTMOD`"]
+pub enum OUTMODW {
+    #[doc = "OUT bit value"]
+    OUTMOD_0,
+    #[doc = "Set"]
+    OUTMOD_1,
+    #[doc = "Toggle/reset"]
+    OUTMOD_2,
+    #[doc = "Set/reset"]
+    OUTMOD_3,
+    #[doc = "Toggle"]
+    OUTMOD_4,
+    #[doc = "Reset"]
+    OUTMOD_5,
+    #[doc = "Toggle/set"]
+    OUTMOD_6,
+    #[doc = "Reset/set"]
+    OUTMOD_7,
+}
+impl OUTMODW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            OUTMODW::OUTMOD_0 => 0,
+            OUTMODW::OUTMOD_1 => 1,
+            OUTMODW::OUTMOD_2 => 2,
+            OUTMODW::OUTMOD_3 => 3,
+            OUTMODW::OUTMOD_4 => 4,
+            OUTMODW::OUTMOD_5 => 5,
+            OUTMODW::OUTMOD_6 => 6,
+            OUTMODW::OUTMOD_7 => 7,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _OUTMODW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _OUTMODW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: OUTMODW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "OUT bit value"]
+    #[inline]
+    pub fn outmod_0(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_0)
+    }
+    #[doc = "Set"]
+    #[inline]
+    pub fn outmod_1(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_1)
+    }
+    #[doc = "Toggle/reset"]
+    #[inline]
+    pub fn outmod_2(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_2)
+    }
+    #[doc = "Set/reset"]
+    #[inline]
+    pub fn outmod_3(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_3)
+    }
+    #[doc = "Toggle"]
+    #[inline]
+    pub fn outmod_4(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_4)
+    }
+    #[doc = "Reset"]
+    #[inline]
+    pub fn outmod_5(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_5)
+    }
+    #[doc = "Toggle/set"]
+    #[inline]
+    pub fn outmod_6(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_6)
+    }
+    #[doc = "Reset/set"]
+    #[inline]
+    pub fn outmod_7(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_7)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CAP`"]
+pub enum CAPW {
+    #[doc = "Compare mode"]
+    CAP_0,
+    #[doc = "Capture mode"]
+    CAP_1,
+}
+impl CAPW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CAPW::CAP_0 => false,
+            CAPW::CAP_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CAPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CAPW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CAPW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Compare mode"]
+    #[inline]
+    pub fn cap_0(self) -> &'a mut W {
+        self.variant(CAPW::CAP_0)
+    }
+    #[doc = "Capture mode"]
+    #[inline]
+    pub fn cap_1(self) -> &'a mut W {
+        self.variant(CAPW::CAP_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SCCIW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SCCIW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `SCS`"]
+pub enum SCSW {
+    #[doc = "Asynchronous capture"]
+    SCS_0,
+    #[doc = "Synchronous capture"]
+    SCS_1,
+}
+impl SCSW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            SCSW::SCS_0 => false,
+            SCSW::SCS_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SCSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SCSW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SCSW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Asynchronous capture"]
+    #[inline]
+    pub fn scs_0(self) -> &'a mut W {
+        self.variant(SCSW::SCS_0)
+    }
+    #[doc = "Synchronous capture"]
+    #[inline]
+    pub fn scs_1(self) -> &'a mut W {
+        self.variant(SCSW::SCS_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CCIS`"]
+pub enum CCISW {
+    #[doc = "CCIxA"]
+    CCIS_0,
+    #[doc = "CCIxB"]
+    CCIS_1,
+    #[doc = "GND"]
+    CCIS_2,
+    #[doc = "VCC"]
+    CCIS_3,
+}
+impl CCISW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            CCISW::CCIS_0 => 0,
+            CCISW::CCIS_1 => 1,
+            CCISW::CCIS_2 => 2,
+            CCISW::CCIS_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CCISW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CCISW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CCISW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "CCIxA"]
+    #[inline]
+    pub fn ccis_0(self) -> &'a mut W {
+        self.variant(CCISW::CCIS_0)
+    }
+    #[doc = "CCIxB"]
+    #[inline]
+    pub fn ccis_1(self) -> &'a mut W {
+        self.variant(CCISW::CCIS_1)
+    }
+    #[doc = "GND"]
+    #[inline]
+    pub fn ccis_2(self) -> &'a mut W {
+        self.variant(CCISW::CCIS_2)
+    }
+    #[doc = "VCC"]
+    #[inline]
+    pub fn ccis_3(self) -> &'a mut W {
+        self.variant(CCISW::CCIS_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CM`"]
+pub enum CMW {
+    #[doc = "No capture"]
+    CM_0,
+    #[doc = "Capture on rising edge"]
+    CM_1,
+    #[doc = "Capture on falling edge"]
+    CM_2,
+    #[doc = "Capture on both rising and falling edges"]
+    CM_3,
+}
+impl CMW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            CMW::CM_0 => 0,
+            CMW::CM_1 => 1,
+            CMW::CM_2 => 2,
+            CMW::CM_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CMW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CMW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CMW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "No capture"]
+    #[inline]
+    pub fn cm_0(self) -> &'a mut W {
+        self.variant(CMW::CM_0)
+    }
+    #[doc = "Capture on rising edge"]
+    #[inline]
+    pub fn cm_1(self) -> &'a mut W {
+        self.variant(CMW::CM_1)
+    }
+    #[doc = "Capture on falling edge"]
+    #[inline]
+    pub fn cm_2(self) -> &'a mut W {
+        self.variant(CMW::CM_2)
+    }
+    #[doc = "Capture on both rising and falling edges"]
+    #[inline]
+    pub fn cm_3(self) -> &'a mut W {
+        self.variant(CMW::CM_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Capture/compare interrupt flag"]
+    #[inline]
+    pub fn ccifg(&self) -> CCIFGR {
+        CCIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Capture overflow"]
+    #[inline]
+    pub fn cov(&self) -> COVR {
+        COVR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - Output"]
+    #[inline]
+    pub fn out(&self) -> OUTR {
+        OUTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Capture/compare input"]
+    #[inline]
+    pub fn cci(&self) -> CCIR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        };
+        CCIR { bits }
+    }
+    #[doc = "Bit 4 - Capture/compare interrupt enable"]
+    #[inline]
+    pub fn ccie(&self) -> CCIER {
+        CCIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 5:7 - Output mode"]
+    #[inline]
+    pub fn outmod(&self) -> OUTMODR {
+        OUTMODR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 8 - Capture mode"]
+    #[inline]
+    pub fn cap(&self) -> CAPR {
+        CAPR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 10 - Synchronized capture/compare input"]
+    #[inline]
+    pub fn scci(&self) -> SCCIR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        };
+        SCCIR { bits }
+    }
+    #[doc = "Bit 11 - Synchronize capture source"]
+    #[inline]
+    pub fn scs(&self) -> SCSR {
+        SCSR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 12:13 - Capture/compare input select"]
+    #[inline]
+    pub fn ccis(&self) -> CCISR {
+        CCISR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bits 14:15 - Capture mode"]
+    #[inline]
+    pub fn cm(&self) -> CMR {
+        CMR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Capture/compare interrupt flag"]
+    #[inline]
+    pub fn ccifg(&mut self) -> _CCIFGW {
+        _CCIFGW { w: self }
+    }
+    #[doc = "Bit 1 - Capture overflow"]
+    #[inline]
+    pub fn cov(&mut self) -> _COVW {
+        _COVW { w: self }
+    }
+    #[doc = "Bit 2 - Output"]
+    #[inline]
+    pub fn out(&mut self) -> _OUTW {
+        _OUTW { w: self }
+    }
+    #[doc = "Bit 4 - Capture/compare interrupt enable"]
+    #[inline]
+    pub fn ccie(&mut self) -> _CCIEW {
+        _CCIEW { w: self }
+    }
+    #[doc = "Bits 5:7 - Output mode"]
+    #[inline]
+    pub fn outmod(&mut self) -> _OUTMODW {
+        _OUTMODW { w: self }
+    }
+    #[doc = "Bit 8 - Capture mode"]
+    #[inline]
+    pub fn cap(&mut self) -> _CAPW {
+        _CAPW { w: self }
+    }
+    #[doc = "Bit 10 - Synchronized capture/compare input"]
+    #[inline]
+    pub fn scci(&mut self) -> _SCCIW {
+        _SCCIW { w: self }
+    }
+    #[doc = "Bit 11 - Synchronize capture source"]
+    #[inline]
+    pub fn scs(&mut self) -> _SCSW {
+        _SCSW { w: self }
+    }
+    #[doc = "Bits 12:13 - Capture/compare input select"]
+    #[inline]
+    pub fn ccis(&mut self) -> _CCISW {
+        _CCISW { w: self }
+    }
+    #[doc = "Bits 14:15 - Capture mode"]
+    #[inline]
+    pub fn cm(&mut self) -> _CMW {
+        _CMW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/timer_a1/tax_ctl.rs b/example-source/msp432p401r/src/timer_a1/tax_ctl.rs
new file mode 100644
index 0000000..938a26f
--- /dev/null
+++ b/example-source/msp432p401r/src/timer_a1/tax_ctl.rs
@@ -0,0 +1,769 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::TAXCTL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `TAIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TAIFGR {
+    #[doc = "No interrupt pending"]
+    TAIFG_0,
+    #[doc = "Interrupt pending"]
+    TAIFG_1,
+}
+impl TAIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TAIFGR::TAIFG_0 => false,
+            TAIFGR::TAIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TAIFGR {
+        match value {
+            false => TAIFGR::TAIFG_0,
+            true => TAIFGR::TAIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `TAIFG_0`"]
+    #[inline]
+    pub fn is_taifg_0(&self) -> bool {
+        *self == TAIFGR::TAIFG_0
+    }
+    #[doc = "Checks if the value of the field is `TAIFG_1`"]
+    #[inline]
+    pub fn is_taifg_1(&self) -> bool {
+        *self == TAIFGR::TAIFG_1
+    }
+}
+#[doc = "Possible values of the field `TAIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TAIER {
+    #[doc = "Interrupt disabled"]
+    TAIE_0,
+    #[doc = "Interrupt enabled"]
+    TAIE_1,
+}
+impl TAIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TAIER::TAIE_0 => false,
+            TAIER::TAIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TAIER {
+        match value {
+            false => TAIER::TAIE_0,
+            true => TAIER::TAIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `TAIE_0`"]
+    #[inline]
+    pub fn is_taie_0(&self) -> bool {
+        *self == TAIER::TAIE_0
+    }
+    #[doc = "Checks if the value of the field is `TAIE_1`"]
+    #[inline]
+    pub fn is_taie_1(&self) -> bool {
+        *self == TAIER::TAIE_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct TACLRR {
+    bits: bool,
+}
+impl TACLRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `MC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum MCR {
+    #[doc = "Stop mode: Timer is halted"]
+    MC_0,
+    #[doc = "Up mode: Timer counts up to TAxCCR0"]
+    MC_1,
+    #[doc = "Continuous mode: Timer counts up to 0FFFFh"]
+    MC_2,
+    #[doc = "Up/down mode: Timer counts up to TAxCCR0 then down to 0000h"]
+    MC_3,
+}
+impl MCR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            MCR::MC_0 => 0,
+            MCR::MC_1 => 1,
+            MCR::MC_2 => 2,
+            MCR::MC_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> MCR {
+        match value {
+            0 => MCR::MC_0,
+            1 => MCR::MC_1,
+            2 => MCR::MC_2,
+            3 => MCR::MC_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `MC_0`"]
+    #[inline]
+    pub fn is_mc_0(&self) -> bool {
+        *self == MCR::MC_0
+    }
+    #[doc = "Checks if the value of the field is `MC_1`"]
+    #[inline]
+    pub fn is_mc_1(&self) -> bool {
+        *self == MCR::MC_1
+    }
+    #[doc = "Checks if the value of the field is `MC_2`"]
+    #[inline]
+    pub fn is_mc_2(&self) -> bool {
+        *self == MCR::MC_2
+    }
+    #[doc = "Checks if the value of the field is `MC_3`"]
+    #[inline]
+    pub fn is_mc_3(&self) -> bool {
+        *self == MCR::MC_3
+    }
+}
+#[doc = "Possible values of the field `ID`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IDR {
+    #[doc = "/1"]
+    ID_0,
+    #[doc = "/2"]
+    ID_1,
+    #[doc = "/4"]
+    ID_2,
+    #[doc = "/8"]
+    ID_3,
+}
+impl IDR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            IDR::ID_0 => 0,
+            IDR::ID_1 => 1,
+            IDR::ID_2 => 2,
+            IDR::ID_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> IDR {
+        match value {
+            0 => IDR::ID_0,
+            1 => IDR::ID_1,
+            2 => IDR::ID_2,
+            3 => IDR::ID_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `ID_0`"]
+    #[inline]
+    pub fn is_id_0(&self) -> bool {
+        *self == IDR::ID_0
+    }
+    #[doc = "Checks if the value of the field is `ID_1`"]
+    #[inline]
+    pub fn is_id_1(&self) -> bool {
+        *self == IDR::ID_1
+    }
+    #[doc = "Checks if the value of the field is `ID_2`"]
+    #[inline]
+    pub fn is_id_2(&self) -> bool {
+        *self == IDR::ID_2
+    }
+    #[doc = "Checks if the value of the field is `ID_3`"]
+    #[inline]
+    pub fn is_id_3(&self) -> bool {
+        *self == IDR::ID_3
+    }
+}
+#[doc = "Possible values of the field `TASSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TASSELR {
+    #[doc = "TAxCLK"]
+    TASSEL_0,
+    #[doc = "ACLK"]
+    TASSEL_1,
+    #[doc = "SMCLK"]
+    TASSEL_2,
+    #[doc = "INCLK"]
+    TASSEL_3,
+}
+impl TASSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            TASSELR::TASSEL_0 => 0,
+            TASSELR::TASSEL_1 => 1,
+            TASSELR::TASSEL_2 => 2,
+            TASSELR::TASSEL_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> TASSELR {
+        match value {
+            0 => TASSELR::TASSEL_0,
+            1 => TASSELR::TASSEL_1,
+            2 => TASSELR::TASSEL_2,
+            3 => TASSELR::TASSEL_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `TASSEL_0`"]
+    #[inline]
+    pub fn is_tassel_0(&self) -> bool {
+        *self == TASSELR::TASSEL_0
+    }
+    #[doc = "Checks if the value of the field is `TASSEL_1`"]
+    #[inline]
+    pub fn is_tassel_1(&self) -> bool {
+        *self == TASSELR::TASSEL_1
+    }
+    #[doc = "Checks if the value of the field is `TASSEL_2`"]
+    #[inline]
+    pub fn is_tassel_2(&self) -> bool {
+        *self == TASSELR::TASSEL_2
+    }
+    #[doc = "Checks if the value of the field is `TASSEL_3`"]
+    #[inline]
+    pub fn is_tassel_3(&self) -> bool {
+        *self == TASSELR::TASSEL_3
+    }
+}
+#[doc = "Values that can be written to the field `TAIFG`"]
+pub enum TAIFGW {
+    #[doc = "No interrupt pending"]
+    TAIFG_0,
+    #[doc = "Interrupt pending"]
+    TAIFG_1,
+}
+impl TAIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TAIFGW::TAIFG_0 => false,
+            TAIFGW::TAIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TAIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TAIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TAIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn taifg_0(self) -> &'a mut W {
+        self.variant(TAIFGW::TAIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn taifg_1(self) -> &'a mut W {
+        self.variant(TAIFGW::TAIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TAIE`"]
+pub enum TAIEW {
+    #[doc = "Interrupt disabled"]
+    TAIE_0,
+    #[doc = "Interrupt enabled"]
+    TAIE_1,
+}
+impl TAIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TAIEW::TAIE_0 => false,
+            TAIEW::TAIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TAIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TAIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TAIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn taie_0(self) -> &'a mut W {
+        self.variant(TAIEW::TAIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn taie_1(self) -> &'a mut W {
+        self.variant(TAIEW::TAIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TACLRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TACLRW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `MC`"]
+pub enum MCW {
+    #[doc = "Stop mode: Timer is halted"]
+    MC_0,
+    #[doc = "Up mode: Timer counts up to TAxCCR0"]
+    MC_1,
+    #[doc = "Continuous mode: Timer counts up to 0FFFFh"]
+    MC_2,
+    #[doc = "Up/down mode: Timer counts up to TAxCCR0 then down to 0000h"]
+    MC_3,
+}
+impl MCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            MCW::MC_0 => 0,
+            MCW::MC_1 => 1,
+            MCW::MC_2 => 2,
+            MCW::MC_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: MCW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Stop mode: Timer is halted"]
+    #[inline]
+    pub fn mc_0(self) -> &'a mut W {
+        self.variant(MCW::MC_0)
+    }
+    #[doc = "Up mode: Timer counts up to TAxCCR0"]
+    #[inline]
+    pub fn mc_1(self) -> &'a mut W {
+        self.variant(MCW::MC_1)
+    }
+    #[doc = "Continuous mode: Timer counts up to 0FFFFh"]
+    #[inline]
+    pub fn mc_2(self) -> &'a mut W {
+        self.variant(MCW::MC_2)
+    }
+    #[doc = "Up/down mode: Timer counts up to TAxCCR0 then down to 0000h"]
+    #[inline]
+    pub fn mc_3(self) -> &'a mut W {
+        self.variant(MCW::MC_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ID`"]
+pub enum IDW {
+    #[doc = "/1"]
+    ID_0,
+    #[doc = "/2"]
+    ID_1,
+    #[doc = "/4"]
+    ID_2,
+    #[doc = "/8"]
+    ID_3,
+}
+impl IDW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            IDW::ID_0 => 0,
+            IDW::ID_1 => 1,
+            IDW::ID_2 => 2,
+            IDW::ID_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _IDW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _IDW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: IDW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "/1"]
+    #[inline]
+    pub fn id_0(self) -> &'a mut W {
+        self.variant(IDW::ID_0)
+    }
+    #[doc = "/2"]
+    #[inline]
+    pub fn id_1(self) -> &'a mut W {
+        self.variant(IDW::ID_1)
+    }
+    #[doc = "/4"]
+    #[inline]
+    pub fn id_2(self) -> &'a mut W {
+        self.variant(IDW::ID_2)
+    }
+    #[doc = "/8"]
+    #[inline]
+    pub fn id_3(self) -> &'a mut W {
+        self.variant(IDW::ID_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TASSEL`"]
+pub enum TASSELW {
+    #[doc = "TAxCLK"]
+    TASSEL_0,
+    #[doc = "ACLK"]
+    TASSEL_1,
+    #[doc = "SMCLK"]
+    TASSEL_2,
+    #[doc = "INCLK"]
+    TASSEL_3,
+}
+impl TASSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            TASSELW::TASSEL_0 => 0,
+            TASSELW::TASSEL_1 => 1,
+            TASSELW::TASSEL_2 => 2,
+            TASSELW::TASSEL_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TASSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TASSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TASSELW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "TAxCLK"]
+    #[inline]
+    pub fn tassel_0(self) -> &'a mut W {
+        self.variant(TASSELW::TASSEL_0)
+    }
+    #[doc = "ACLK"]
+    #[inline]
+    pub fn tassel_1(self) -> &'a mut W {
+        self.variant(TASSELW::TASSEL_1)
+    }
+    #[doc = "SMCLK"]
+    #[inline]
+    pub fn tassel_2(self) -> &'a mut W {
+        self.variant(TASSELW::TASSEL_2)
+    }
+    #[doc = "INCLK"]
+    #[inline]
+    pub fn tassel_3(self) -> &'a mut W {
+        self.variant(TASSELW::TASSEL_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - TimerA interrupt flag"]
+    #[inline]
+    pub fn taifg(&self) -> TAIFGR {
+        TAIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - TimerA interrupt enable"]
+    #[inline]
+    pub fn taie(&self) -> TAIER {
+        TAIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - TimerA clear"]
+    #[inline]
+    pub fn taclr(&self) -> TACLRR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        };
+        TACLRR { bits }
+    }
+    #[doc = "Bits 4:5 - Mode control"]
+    #[inline]
+    pub fn mc(&self) -> MCR {
+        MCR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bits 6:7 - Input divider"]
+    #[inline]
+    pub fn id(&self) -> IDR {
+        IDR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bits 8:9 - TimerA clock source select"]
+    #[inline]
+    pub fn tassel(&self) -> TASSELR {
+        TASSELR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - TimerA interrupt flag"]
+    #[inline]
+    pub fn taifg(&mut self) -> _TAIFGW {
+        _TAIFGW { w: self }
+    }
+    #[doc = "Bit 1 - TimerA interrupt enable"]
+    #[inline]
+    pub fn taie(&mut self) -> _TAIEW {
+        _TAIEW { w: self }
+    }
+    #[doc = "Bit 2 - TimerA clear"]
+    #[inline]
+    pub fn taclr(&mut self) -> _TACLRW {
+        _TACLRW { w: self }
+    }
+    #[doc = "Bits 4:5 - Mode control"]
+    #[inline]
+    pub fn mc(&mut self) -> _MCW {
+        _MCW { w: self }
+    }
+    #[doc = "Bits 6:7 - Input divider"]
+    #[inline]
+    pub fn id(&mut self) -> _IDW {
+        _IDW { w: self }
+    }
+    #[doc = "Bits 8:9 - TimerA clock source select"]
+    #[inline]
+    pub fn tassel(&mut self) -> _TASSELW {
+        _TASSELW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/timer_a1/tax_ex0.rs b/example-source/msp432p401r/src/timer_a1/tax_ex0.rs
new file mode 100644
index 0000000..cc9bd3f
--- /dev/null
+++ b/example-source/msp432p401r/src/timer_a1/tax_ex0.rs
@@ -0,0 +1,268 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::TAXEX0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `TAIDEX`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TAIDEXR {
+    #[doc = "Divide by 1"]
+    TAIDEX_0,
+    #[doc = "Divide by 2"]
+    TAIDEX_1,
+    #[doc = "Divide by 3"]
+    TAIDEX_2,
+    #[doc = "Divide by 4"]
+    TAIDEX_3,
+    #[doc = "Divide by 5"]
+    TAIDEX_4,
+    #[doc = "Divide by 6"]
+    TAIDEX_5,
+    #[doc = "Divide by 7"]
+    TAIDEX_6,
+    #[doc = "Divide by 8"]
+    TAIDEX_7,
+}
+impl TAIDEXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            TAIDEXR::TAIDEX_0 => 0,
+            TAIDEXR::TAIDEX_1 => 1,
+            TAIDEXR::TAIDEX_2 => 2,
+            TAIDEXR::TAIDEX_3 => 3,
+            TAIDEXR::TAIDEX_4 => 4,
+            TAIDEXR::TAIDEX_5 => 5,
+            TAIDEXR::TAIDEX_6 => 6,
+            TAIDEXR::TAIDEX_7 => 7,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> TAIDEXR {
+        match value {
+            0 => TAIDEXR::TAIDEX_0,
+            1 => TAIDEXR::TAIDEX_1,
+            2 => TAIDEXR::TAIDEX_2,
+            3 => TAIDEXR::TAIDEX_3,
+            4 => TAIDEXR::TAIDEX_4,
+            5 => TAIDEXR::TAIDEX_5,
+            6 => TAIDEXR::TAIDEX_6,
+            7 => TAIDEXR::TAIDEX_7,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_0`"]
+    #[inline]
+    pub fn is_taidex_0(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_0
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_1`"]
+    #[inline]
+    pub fn is_taidex_1(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_1
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_2`"]
+    #[inline]
+    pub fn is_taidex_2(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_2
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_3`"]
+    #[inline]
+    pub fn is_taidex_3(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_3
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_4`"]
+    #[inline]
+    pub fn is_taidex_4(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_4
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_5`"]
+    #[inline]
+    pub fn is_taidex_5(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_5
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_6`"]
+    #[inline]
+    pub fn is_taidex_6(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_6
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_7`"]
+    #[inline]
+    pub fn is_taidex_7(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_7
+    }
+}
+#[doc = "Values that can be written to the field `TAIDEX`"]
+pub enum TAIDEXW {
+    #[doc = "Divide by 1"]
+    TAIDEX_0,
+    #[doc = "Divide by 2"]
+    TAIDEX_1,
+    #[doc = "Divide by 3"]
+    TAIDEX_2,
+    #[doc = "Divide by 4"]
+    TAIDEX_3,
+    #[doc = "Divide by 5"]
+    TAIDEX_4,
+    #[doc = "Divide by 6"]
+    TAIDEX_5,
+    #[doc = "Divide by 7"]
+    TAIDEX_6,
+    #[doc = "Divide by 8"]
+    TAIDEX_7,
+}
+impl TAIDEXW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            TAIDEXW::TAIDEX_0 => 0,
+            TAIDEXW::TAIDEX_1 => 1,
+            TAIDEXW::TAIDEX_2 => 2,
+            TAIDEXW::TAIDEX_3 => 3,
+            TAIDEXW::TAIDEX_4 => 4,
+            TAIDEXW::TAIDEX_5 => 5,
+            TAIDEXW::TAIDEX_6 => 6,
+            TAIDEXW::TAIDEX_7 => 7,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TAIDEXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TAIDEXW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TAIDEXW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Divide by 1"]
+    #[inline]
+    pub fn taidex_0(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_0)
+    }
+    #[doc = "Divide by 2"]
+    #[inline]
+    pub fn taidex_1(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_1)
+    }
+    #[doc = "Divide by 3"]
+    #[inline]
+    pub fn taidex_2(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_2)
+    }
+    #[doc = "Divide by 4"]
+    #[inline]
+    pub fn taidex_3(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_3)
+    }
+    #[doc = "Divide by 5"]
+    #[inline]
+    pub fn taidex_4(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_4)
+    }
+    #[doc = "Divide by 6"]
+    #[inline]
+    pub fn taidex_5(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_5)
+    }
+    #[doc = "Divide by 7"]
+    #[inline]
+    pub fn taidex_6(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_6)
+    }
+    #[doc = "Divide by 8"]
+    #[inline]
+    pub fn taidex_7(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_7)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:2 - Input divider expansion"]
+    #[inline]
+    pub fn taidex(&self) -> TAIDEXR {
+        TAIDEXR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:2 - Input divider expansion"]
+    #[inline]
+    pub fn taidex(&mut self) -> _TAIDEXW {
+        _TAIDEXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/timer_a1/tax_iv.rs b/example-source/msp432p401r/src/timer_a1/tax_iv.rs
new file mode 100644
index 0000000..a83ed36
--- /dev/null
+++ b/example-source/msp432p401r/src/timer_a1/tax_iv.rs
@@ -0,0 +1,124 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::TAXIV {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `TAIV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TAIVR {
+    #[doc = "No interrupt pending"]
+    TAIV_0,
+    #[doc = "Interrupt Source: Capture/compare 1; Interrupt Flag: TAxCCR1 CCIFG; Interrupt Priority: Highest"]
+    TAIV_2,
+    #[doc = "Interrupt Source: Capture/compare 2; Interrupt Flag: TAxCCR2 CCIFG"]
+    TAIV_4,
+    #[doc = "Interrupt Source: Capture/compare 3; Interrupt Flag: TAxCCR3 CCIFG"]
+    TAIV_6,
+    #[doc = "Interrupt Source: Capture/compare 4; Interrupt Flag: TAxCCR4 CCIFG"]
+    TAIV_8,
+    #[doc = "Interrupt Source: Capture/compare 5; Interrupt Flag: TAxCCR5 CCIFG"]
+    TAIV_10,
+    #[doc = "Interrupt Source: Capture/compare 6; Interrupt Flag: TAxCCR6 CCIFG"]
+    TAIV_12,
+    #[doc = "Interrupt Source: Timer overflow; Interrupt Flag: TAxCTL TAIFG; Interrupt Priority: Lowest"]
+    TAIV_14,
+    #[doc = r" Reserved"]
+    _Reserved(u16),
+}
+impl TAIVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        match *self {
+            TAIVR::TAIV_0 => 0,
+            TAIVR::TAIV_2 => 2,
+            TAIVR::TAIV_4 => 4,
+            TAIVR::TAIV_6 => 6,
+            TAIVR::TAIV_8 => 8,
+            TAIVR::TAIV_10 => 10,
+            TAIVR::TAIV_12 => 12,
+            TAIVR::TAIV_14 => 14,
+            TAIVR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u16) -> TAIVR {
+        match value {
+            0 => TAIVR::TAIV_0,
+            2 => TAIVR::TAIV_2,
+            4 => TAIVR::TAIV_4,
+            6 => TAIVR::TAIV_6,
+            8 => TAIVR::TAIV_8,
+            10 => TAIVR::TAIV_10,
+            12 => TAIVR::TAIV_12,
+            14 => TAIVR::TAIV_14,
+            i => TAIVR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `TAIV_0`"]
+    #[inline]
+    pub fn is_taiv_0(&self) -> bool {
+        *self == TAIVR::TAIV_0
+    }
+    #[doc = "Checks if the value of the field is `TAIV_2`"]
+    #[inline]
+    pub fn is_taiv_2(&self) -> bool {
+        *self == TAIVR::TAIV_2
+    }
+    #[doc = "Checks if the value of the field is `TAIV_4`"]
+    #[inline]
+    pub fn is_taiv_4(&self) -> bool {
+        *self == TAIVR::TAIV_4
+    }
+    #[doc = "Checks if the value of the field is `TAIV_6`"]
+    #[inline]
+    pub fn is_taiv_6(&self) -> bool {
+        *self == TAIVR::TAIV_6
+    }
+    #[doc = "Checks if the value of the field is `TAIV_8`"]
+    #[inline]
+    pub fn is_taiv_8(&self) -> bool {
+        *self == TAIVR::TAIV_8
+    }
+    #[doc = "Checks if the value of the field is `TAIV_10`"]
+    #[inline]
+    pub fn is_taiv_10(&self) -> bool {
+        *self == TAIVR::TAIV_10
+    }
+    #[doc = "Checks if the value of the field is `TAIV_12`"]
+    #[inline]
+    pub fn is_taiv_12(&self) -> bool {
+        *self == TAIVR::TAIV_12
+    }
+    #[doc = "Checks if the value of the field is `TAIV_14`"]
+    #[inline]
+    pub fn is_taiv_14(&self) -> bool {
+        *self == TAIVR::TAIV_14
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - TimerA interrupt vector value"]
+    #[inline]
+    pub fn taiv(&self) -> TAIVR {
+        TAIVR::_from({
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/timer_a1/tax_r.rs b/example-source/msp432p401r/src/timer_a1/tax_r.rs
new file mode 100644
index 0000000..3542361
--- /dev/null
+++ b/example-source/msp432p401r/src/timer_a1/tax_r.rs
@@ -0,0 +1,64 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::TAXR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+}
diff --git a/example-source/msp432p401r/src/timer_a2.rs b/example-source/msp432p401r/src/timer_a2.rs
new file mode 100644
index 0000000..89bd30a
--- /dev/null
+++ b/example-source/msp432p401r/src/timer_a2.rs
@@ -0,0 +1,55 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - TimerAx Control Register"]
+    pub tax_ctl: TAXCTL,
+    #[doc = "0x02 - Timer_A Capture/Compare Control Register"]
+    pub tax_cctl: [TAXCCTL; 5],
+    _reserved0: [u8; 4usize],
+    #[doc = "0x10 - TimerA register"]
+    pub tax_r: TAXR,
+    #[doc = "0x12 - Timer_A Capture/Compare Register"]
+    pub tax_ccr: [TAXCCR; 5],
+    _reserved1: [u8; 4usize],
+    #[doc = "0x20 - TimerAx Expansion 0 Register"]
+    pub tax_ex0: TAXEX0,
+    _reserved2: [u8; 12usize],
+    #[doc = "0x2e - TimerAx Interrupt Vector Register"]
+    pub tax_iv: TAXIV,
+}
+#[doc = "TimerAx Control Register"]
+pub struct TAXCTL {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "TimerAx Control Register"]
+pub mod tax_ctl;
+#[doc = "Timer_A Capture/Compare Control Register"]
+pub struct TAXCCTL {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Timer_A Capture/Compare Control Register"]
+pub mod tax_cctl;
+#[doc = "TimerA register"]
+pub struct TAXR {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "TimerA register"]
+pub mod tax_r;
+#[doc = "Timer_A Capture/Compare Register"]
+pub struct TAXCCR {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Timer_A Capture/Compare Register"]
+pub mod tax_ccr;
+#[doc = "TimerAx Expansion 0 Register"]
+pub struct TAXEX0 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "TimerAx Expansion 0 Register"]
+pub mod tax_ex0;
+#[doc = "TimerAx Interrupt Vector Register"]
+pub struct TAXIV {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "TimerAx Interrupt Vector Register"]
+pub mod tax_iv;
diff --git a/example-source/msp432p401r/src/timer_a2/tax_ccr.rs b/example-source/msp432p401r/src/timer_a2/tax_ccr.rs
new file mode 100644
index 0000000..f533aed
--- /dev/null
+++ b/example-source/msp432p401r/src/timer_a2/tax_ccr.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::TAXCCR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct TAXRR {
+    bits: u16,
+}
+impl TAXRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TAXRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TAXRW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - TimerA register"]
+    #[inline]
+    pub fn tax_r(&self) -> TAXRR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        TAXRR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - TimerA register"]
+    #[inline]
+    pub fn tax_r(&mut self) -> _TAXRW {
+        _TAXRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/timer_a2/tax_cctl.rs b/example-source/msp432p401r/src/timer_a2/tax_cctl.rs
new file mode 100644
index 0000000..65d41c1
--- /dev/null
+++ b/example-source/msp432p401r/src/timer_a2/tax_cctl.rs
@@ -0,0 +1,1344 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::TAXCCTL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `CCIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CCIFGR {
+    #[doc = "No interrupt pending"]
+    CCIFG_0,
+    #[doc = "Interrupt pending"]
+    CCIFG_1,
+}
+impl CCIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CCIFGR::CCIFG_0 => false,
+            CCIFGR::CCIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CCIFGR {
+        match value {
+            false => CCIFGR::CCIFG_0,
+            true => CCIFGR::CCIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CCIFG_0`"]
+    #[inline]
+    pub fn is_ccifg_0(&self) -> bool {
+        *self == CCIFGR::CCIFG_0
+    }
+    #[doc = "Checks if the value of the field is `CCIFG_1`"]
+    #[inline]
+    pub fn is_ccifg_1(&self) -> bool {
+        *self == CCIFGR::CCIFG_1
+    }
+}
+#[doc = "Possible values of the field `COV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum COVR {
+    #[doc = "No capture overflow occurred"]
+    COV_0,
+    #[doc = "Capture overflow occurred"]
+    COV_1,
+}
+impl COVR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            COVR::COV_0 => false,
+            COVR::COV_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> COVR {
+        match value {
+            false => COVR::COV_0,
+            true => COVR::COV_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `COV_0`"]
+    #[inline]
+    pub fn is_cov_0(&self) -> bool {
+        *self == COVR::COV_0
+    }
+    #[doc = "Checks if the value of the field is `COV_1`"]
+    #[inline]
+    pub fn is_cov_1(&self) -> bool {
+        *self == COVR::COV_1
+    }
+}
+#[doc = "Possible values of the field `OUT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum OUTR {
+    #[doc = "Output low"]
+    OUT_0,
+    #[doc = "Output high"]
+    OUT_1,
+}
+impl OUTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            OUTR::OUT_0 => false,
+            OUTR::OUT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> OUTR {
+        match value {
+            false => OUTR::OUT_0,
+            true => OUTR::OUT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `OUT_0`"]
+    #[inline]
+    pub fn is_out_0(&self) -> bool {
+        *self == OUTR::OUT_0
+    }
+    #[doc = "Checks if the value of the field is `OUT_1`"]
+    #[inline]
+    pub fn is_out_1(&self) -> bool {
+        *self == OUTR::OUT_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CCIR {
+    bits: bool,
+}
+impl CCIR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `CCIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CCIER {
+    #[doc = "Interrupt disabled"]
+    CCIE_0,
+    #[doc = "Interrupt enabled"]
+    CCIE_1,
+}
+impl CCIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CCIER::CCIE_0 => false,
+            CCIER::CCIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CCIER {
+        match value {
+            false => CCIER::CCIE_0,
+            true => CCIER::CCIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CCIE_0`"]
+    #[inline]
+    pub fn is_ccie_0(&self) -> bool {
+        *self == CCIER::CCIE_0
+    }
+    #[doc = "Checks if the value of the field is `CCIE_1`"]
+    #[inline]
+    pub fn is_ccie_1(&self) -> bool {
+        *self == CCIER::CCIE_1
+    }
+}
+#[doc = "Possible values of the field `OUTMOD`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum OUTMODR {
+    #[doc = "OUT bit value"]
+    OUTMOD_0,
+    #[doc = "Set"]
+    OUTMOD_1,
+    #[doc = "Toggle/reset"]
+    OUTMOD_2,
+    #[doc = "Set/reset"]
+    OUTMOD_3,
+    #[doc = "Toggle"]
+    OUTMOD_4,
+    #[doc = "Reset"]
+    OUTMOD_5,
+    #[doc = "Toggle/set"]
+    OUTMOD_6,
+    #[doc = "Reset/set"]
+    OUTMOD_7,
+}
+impl OUTMODR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            OUTMODR::OUTMOD_0 => 0,
+            OUTMODR::OUTMOD_1 => 1,
+            OUTMODR::OUTMOD_2 => 2,
+            OUTMODR::OUTMOD_3 => 3,
+            OUTMODR::OUTMOD_4 => 4,
+            OUTMODR::OUTMOD_5 => 5,
+            OUTMODR::OUTMOD_6 => 6,
+            OUTMODR::OUTMOD_7 => 7,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> OUTMODR {
+        match value {
+            0 => OUTMODR::OUTMOD_0,
+            1 => OUTMODR::OUTMOD_1,
+            2 => OUTMODR::OUTMOD_2,
+            3 => OUTMODR::OUTMOD_3,
+            4 => OUTMODR::OUTMOD_4,
+            5 => OUTMODR::OUTMOD_5,
+            6 => OUTMODR::OUTMOD_6,
+            7 => OUTMODR::OUTMOD_7,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_0`"]
+    #[inline]
+    pub fn is_outmod_0(&self) -> bool {
+        *self == OUTMODR::OUTMOD_0
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_1`"]
+    #[inline]
+    pub fn is_outmod_1(&self) -> bool {
+        *self == OUTMODR::OUTMOD_1
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_2`"]
+    #[inline]
+    pub fn is_outmod_2(&self) -> bool {
+        *self == OUTMODR::OUTMOD_2
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_3`"]
+    #[inline]
+    pub fn is_outmod_3(&self) -> bool {
+        *self == OUTMODR::OUTMOD_3
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_4`"]
+    #[inline]
+    pub fn is_outmod_4(&self) -> bool {
+        *self == OUTMODR::OUTMOD_4
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_5`"]
+    #[inline]
+    pub fn is_outmod_5(&self) -> bool {
+        *self == OUTMODR::OUTMOD_5
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_6`"]
+    #[inline]
+    pub fn is_outmod_6(&self) -> bool {
+        *self == OUTMODR::OUTMOD_6
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_7`"]
+    #[inline]
+    pub fn is_outmod_7(&self) -> bool {
+        *self == OUTMODR::OUTMOD_7
+    }
+}
+#[doc = "Possible values of the field `CAP`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CAPR {
+    #[doc = "Compare mode"]
+    CAP_0,
+    #[doc = "Capture mode"]
+    CAP_1,
+}
+impl CAPR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CAPR::CAP_0 => false,
+            CAPR::CAP_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CAPR {
+        match value {
+            false => CAPR::CAP_0,
+            true => CAPR::CAP_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CAP_0`"]
+    #[inline]
+    pub fn is_cap_0(&self) -> bool {
+        *self == CAPR::CAP_0
+    }
+    #[doc = "Checks if the value of the field is `CAP_1`"]
+    #[inline]
+    pub fn is_cap_1(&self) -> bool {
+        *self == CAPR::CAP_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SCCIR {
+    bits: bool,
+}
+impl SCCIR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `SCS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SCSR {
+    #[doc = "Asynchronous capture"]
+    SCS_0,
+    #[doc = "Synchronous capture"]
+    SCS_1,
+}
+impl SCSR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            SCSR::SCS_0 => false,
+            SCSR::SCS_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> SCSR {
+        match value {
+            false => SCSR::SCS_0,
+            true => SCSR::SCS_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SCS_0`"]
+    #[inline]
+    pub fn is_scs_0(&self) -> bool {
+        *self == SCSR::SCS_0
+    }
+    #[doc = "Checks if the value of the field is `SCS_1`"]
+    #[inline]
+    pub fn is_scs_1(&self) -> bool {
+        *self == SCSR::SCS_1
+    }
+}
+#[doc = "Possible values of the field `CCIS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CCISR {
+    #[doc = "CCIxA"]
+    CCIS_0,
+    #[doc = "CCIxB"]
+    CCIS_1,
+    #[doc = "GND"]
+    CCIS_2,
+    #[doc = "VCC"]
+    CCIS_3,
+}
+impl CCISR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            CCISR::CCIS_0 => 0,
+            CCISR::CCIS_1 => 1,
+            CCISR::CCIS_2 => 2,
+            CCISR::CCIS_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> CCISR {
+        match value {
+            0 => CCISR::CCIS_0,
+            1 => CCISR::CCIS_1,
+            2 => CCISR::CCIS_2,
+            3 => CCISR::CCIS_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `CCIS_0`"]
+    #[inline]
+    pub fn is_ccis_0(&self) -> bool {
+        *self == CCISR::CCIS_0
+    }
+    #[doc = "Checks if the value of the field is `CCIS_1`"]
+    #[inline]
+    pub fn is_ccis_1(&self) -> bool {
+        *self == CCISR::CCIS_1
+    }
+    #[doc = "Checks if the value of the field is `CCIS_2`"]
+    #[inline]
+    pub fn is_ccis_2(&self) -> bool {
+        *self == CCISR::CCIS_2
+    }
+    #[doc = "Checks if the value of the field is `CCIS_3`"]
+    #[inline]
+    pub fn is_ccis_3(&self) -> bool {
+        *self == CCISR::CCIS_3
+    }
+}
+#[doc = "Possible values of the field `CM`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CMR {
+    #[doc = "No capture"]
+    CM_0,
+    #[doc = "Capture on rising edge"]
+    CM_1,
+    #[doc = "Capture on falling edge"]
+    CM_2,
+    #[doc = "Capture on both rising and falling edges"]
+    CM_3,
+}
+impl CMR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            CMR::CM_0 => 0,
+            CMR::CM_1 => 1,
+            CMR::CM_2 => 2,
+            CMR::CM_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> CMR {
+        match value {
+            0 => CMR::CM_0,
+            1 => CMR::CM_1,
+            2 => CMR::CM_2,
+            3 => CMR::CM_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `CM_0`"]
+    #[inline]
+    pub fn is_cm_0(&self) -> bool {
+        *self == CMR::CM_0
+    }
+    #[doc = "Checks if the value of the field is `CM_1`"]
+    #[inline]
+    pub fn is_cm_1(&self) -> bool {
+        *self == CMR::CM_1
+    }
+    #[doc = "Checks if the value of the field is `CM_2`"]
+    #[inline]
+    pub fn is_cm_2(&self) -> bool {
+        *self == CMR::CM_2
+    }
+    #[doc = "Checks if the value of the field is `CM_3`"]
+    #[inline]
+    pub fn is_cm_3(&self) -> bool {
+        *self == CMR::CM_3
+    }
+}
+#[doc = "Values that can be written to the field `CCIFG`"]
+pub enum CCIFGW {
+    #[doc = "No interrupt pending"]
+    CCIFG_0,
+    #[doc = "Interrupt pending"]
+    CCIFG_1,
+}
+impl CCIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CCIFGW::CCIFG_0 => false,
+            CCIFGW::CCIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CCIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CCIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CCIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ccifg_0(self) -> &'a mut W {
+        self.variant(CCIFGW::CCIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ccifg_1(self) -> &'a mut W {
+        self.variant(CCIFGW::CCIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `COV`"]
+pub enum COVW {
+    #[doc = "No capture overflow occurred"]
+    COV_0,
+    #[doc = "Capture overflow occurred"]
+    COV_1,
+}
+impl COVW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            COVW::COV_0 => false,
+            COVW::COV_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _COVW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _COVW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: COVW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No capture overflow occurred"]
+    #[inline]
+    pub fn cov_0(self) -> &'a mut W {
+        self.variant(COVW::COV_0)
+    }
+    #[doc = "Capture overflow occurred"]
+    #[inline]
+    pub fn cov_1(self) -> &'a mut W {
+        self.variant(COVW::COV_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `OUT`"]
+pub enum OUTW {
+    #[doc = "Output low"]
+    OUT_0,
+    #[doc = "Output high"]
+    OUT_1,
+}
+impl OUTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            OUTW::OUT_0 => false,
+            OUTW::OUT_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _OUTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _OUTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: OUTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Output low"]
+    #[inline]
+    pub fn out_0(self) -> &'a mut W {
+        self.variant(OUTW::OUT_0)
+    }
+    #[doc = "Output high"]
+    #[inline]
+    pub fn out_1(self) -> &'a mut W {
+        self.variant(OUTW::OUT_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CCIE`"]
+pub enum CCIEW {
+    #[doc = "Interrupt disabled"]
+    CCIE_0,
+    #[doc = "Interrupt enabled"]
+    CCIE_1,
+}
+impl CCIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CCIEW::CCIE_0 => false,
+            CCIEW::CCIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CCIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CCIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CCIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ccie_0(self) -> &'a mut W {
+        self.variant(CCIEW::CCIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ccie_1(self) -> &'a mut W {
+        self.variant(CCIEW::CCIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `OUTMOD`"]
+pub enum OUTMODW {
+    #[doc = "OUT bit value"]
+    OUTMOD_0,
+    #[doc = "Set"]
+    OUTMOD_1,
+    #[doc = "Toggle/reset"]
+    OUTMOD_2,
+    #[doc = "Set/reset"]
+    OUTMOD_3,
+    #[doc = "Toggle"]
+    OUTMOD_4,
+    #[doc = "Reset"]
+    OUTMOD_5,
+    #[doc = "Toggle/set"]
+    OUTMOD_6,
+    #[doc = "Reset/set"]
+    OUTMOD_7,
+}
+impl OUTMODW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            OUTMODW::OUTMOD_0 => 0,
+            OUTMODW::OUTMOD_1 => 1,
+            OUTMODW::OUTMOD_2 => 2,
+            OUTMODW::OUTMOD_3 => 3,
+            OUTMODW::OUTMOD_4 => 4,
+            OUTMODW::OUTMOD_5 => 5,
+            OUTMODW::OUTMOD_6 => 6,
+            OUTMODW::OUTMOD_7 => 7,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _OUTMODW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _OUTMODW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: OUTMODW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "OUT bit value"]
+    #[inline]
+    pub fn outmod_0(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_0)
+    }
+    #[doc = "Set"]
+    #[inline]
+    pub fn outmod_1(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_1)
+    }
+    #[doc = "Toggle/reset"]
+    #[inline]
+    pub fn outmod_2(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_2)
+    }
+    #[doc = "Set/reset"]
+    #[inline]
+    pub fn outmod_3(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_3)
+    }
+    #[doc = "Toggle"]
+    #[inline]
+    pub fn outmod_4(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_4)
+    }
+    #[doc = "Reset"]
+    #[inline]
+    pub fn outmod_5(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_5)
+    }
+    #[doc = "Toggle/set"]
+    #[inline]
+    pub fn outmod_6(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_6)
+    }
+    #[doc = "Reset/set"]
+    #[inline]
+    pub fn outmod_7(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_7)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CAP`"]
+pub enum CAPW {
+    #[doc = "Compare mode"]
+    CAP_0,
+    #[doc = "Capture mode"]
+    CAP_1,
+}
+impl CAPW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CAPW::CAP_0 => false,
+            CAPW::CAP_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CAPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CAPW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CAPW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Compare mode"]
+    #[inline]
+    pub fn cap_0(self) -> &'a mut W {
+        self.variant(CAPW::CAP_0)
+    }
+    #[doc = "Capture mode"]
+    #[inline]
+    pub fn cap_1(self) -> &'a mut W {
+        self.variant(CAPW::CAP_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SCCIW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SCCIW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `SCS`"]
+pub enum SCSW {
+    #[doc = "Asynchronous capture"]
+    SCS_0,
+    #[doc = "Synchronous capture"]
+    SCS_1,
+}
+impl SCSW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            SCSW::SCS_0 => false,
+            SCSW::SCS_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SCSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SCSW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SCSW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Asynchronous capture"]
+    #[inline]
+    pub fn scs_0(self) -> &'a mut W {
+        self.variant(SCSW::SCS_0)
+    }
+    #[doc = "Synchronous capture"]
+    #[inline]
+    pub fn scs_1(self) -> &'a mut W {
+        self.variant(SCSW::SCS_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CCIS`"]
+pub enum CCISW {
+    #[doc = "CCIxA"]
+    CCIS_0,
+    #[doc = "CCIxB"]
+    CCIS_1,
+    #[doc = "GND"]
+    CCIS_2,
+    #[doc = "VCC"]
+    CCIS_3,
+}
+impl CCISW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            CCISW::CCIS_0 => 0,
+            CCISW::CCIS_1 => 1,
+            CCISW::CCIS_2 => 2,
+            CCISW::CCIS_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CCISW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CCISW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CCISW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "CCIxA"]
+    #[inline]
+    pub fn ccis_0(self) -> &'a mut W {
+        self.variant(CCISW::CCIS_0)
+    }
+    #[doc = "CCIxB"]
+    #[inline]
+    pub fn ccis_1(self) -> &'a mut W {
+        self.variant(CCISW::CCIS_1)
+    }
+    #[doc = "GND"]
+    #[inline]
+    pub fn ccis_2(self) -> &'a mut W {
+        self.variant(CCISW::CCIS_2)
+    }
+    #[doc = "VCC"]
+    #[inline]
+    pub fn ccis_3(self) -> &'a mut W {
+        self.variant(CCISW::CCIS_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CM`"]
+pub enum CMW {
+    #[doc = "No capture"]
+    CM_0,
+    #[doc = "Capture on rising edge"]
+    CM_1,
+    #[doc = "Capture on falling edge"]
+    CM_2,
+    #[doc = "Capture on both rising and falling edges"]
+    CM_3,
+}
+impl CMW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            CMW::CM_0 => 0,
+            CMW::CM_1 => 1,
+            CMW::CM_2 => 2,
+            CMW::CM_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CMW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CMW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CMW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "No capture"]
+    #[inline]
+    pub fn cm_0(self) -> &'a mut W {
+        self.variant(CMW::CM_0)
+    }
+    #[doc = "Capture on rising edge"]
+    #[inline]
+    pub fn cm_1(self) -> &'a mut W {
+        self.variant(CMW::CM_1)
+    }
+    #[doc = "Capture on falling edge"]
+    #[inline]
+    pub fn cm_2(self) -> &'a mut W {
+        self.variant(CMW::CM_2)
+    }
+    #[doc = "Capture on both rising and falling edges"]
+    #[inline]
+    pub fn cm_3(self) -> &'a mut W {
+        self.variant(CMW::CM_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Capture/compare interrupt flag"]
+    #[inline]
+    pub fn ccifg(&self) -> CCIFGR {
+        CCIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Capture overflow"]
+    #[inline]
+    pub fn cov(&self) -> COVR {
+        COVR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - Output"]
+    #[inline]
+    pub fn out(&self) -> OUTR {
+        OUTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Capture/compare input"]
+    #[inline]
+    pub fn cci(&self) -> CCIR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        };
+        CCIR { bits }
+    }
+    #[doc = "Bit 4 - Capture/compare interrupt enable"]
+    #[inline]
+    pub fn ccie(&self) -> CCIER {
+        CCIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 5:7 - Output mode"]
+    #[inline]
+    pub fn outmod(&self) -> OUTMODR {
+        OUTMODR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 8 - Capture mode"]
+    #[inline]
+    pub fn cap(&self) -> CAPR {
+        CAPR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 10 - Synchronized capture/compare input"]
+    #[inline]
+    pub fn scci(&self) -> SCCIR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        };
+        SCCIR { bits }
+    }
+    #[doc = "Bit 11 - Synchronize capture source"]
+    #[inline]
+    pub fn scs(&self) -> SCSR {
+        SCSR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 12:13 - Capture/compare input select"]
+    #[inline]
+    pub fn ccis(&self) -> CCISR {
+        CCISR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bits 14:15 - Capture mode"]
+    #[inline]
+    pub fn cm(&self) -> CMR {
+        CMR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Capture/compare interrupt flag"]
+    #[inline]
+    pub fn ccifg(&mut self) -> _CCIFGW {
+        _CCIFGW { w: self }
+    }
+    #[doc = "Bit 1 - Capture overflow"]
+    #[inline]
+    pub fn cov(&mut self) -> _COVW {
+        _COVW { w: self }
+    }
+    #[doc = "Bit 2 - Output"]
+    #[inline]
+    pub fn out(&mut self) -> _OUTW {
+        _OUTW { w: self }
+    }
+    #[doc = "Bit 4 - Capture/compare interrupt enable"]
+    #[inline]
+    pub fn ccie(&mut self) -> _CCIEW {
+        _CCIEW { w: self }
+    }
+    #[doc = "Bits 5:7 - Output mode"]
+    #[inline]
+    pub fn outmod(&mut self) -> _OUTMODW {
+        _OUTMODW { w: self }
+    }
+    #[doc = "Bit 8 - Capture mode"]
+    #[inline]
+    pub fn cap(&mut self) -> _CAPW {
+        _CAPW { w: self }
+    }
+    #[doc = "Bit 10 - Synchronized capture/compare input"]
+    #[inline]
+    pub fn scci(&mut self) -> _SCCIW {
+        _SCCIW { w: self }
+    }
+    #[doc = "Bit 11 - Synchronize capture source"]
+    #[inline]
+    pub fn scs(&mut self) -> _SCSW {
+        _SCSW { w: self }
+    }
+    #[doc = "Bits 12:13 - Capture/compare input select"]
+    #[inline]
+    pub fn ccis(&mut self) -> _CCISW {
+        _CCISW { w: self }
+    }
+    #[doc = "Bits 14:15 - Capture mode"]
+    #[inline]
+    pub fn cm(&mut self) -> _CMW {
+        _CMW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/timer_a2/tax_ctl.rs b/example-source/msp432p401r/src/timer_a2/tax_ctl.rs
new file mode 100644
index 0000000..938a26f
--- /dev/null
+++ b/example-source/msp432p401r/src/timer_a2/tax_ctl.rs
@@ -0,0 +1,769 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::TAXCTL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `TAIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TAIFGR {
+    #[doc = "No interrupt pending"]
+    TAIFG_0,
+    #[doc = "Interrupt pending"]
+    TAIFG_1,
+}
+impl TAIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TAIFGR::TAIFG_0 => false,
+            TAIFGR::TAIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TAIFGR {
+        match value {
+            false => TAIFGR::TAIFG_0,
+            true => TAIFGR::TAIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `TAIFG_0`"]
+    #[inline]
+    pub fn is_taifg_0(&self) -> bool {
+        *self == TAIFGR::TAIFG_0
+    }
+    #[doc = "Checks if the value of the field is `TAIFG_1`"]
+    #[inline]
+    pub fn is_taifg_1(&self) -> bool {
+        *self == TAIFGR::TAIFG_1
+    }
+}
+#[doc = "Possible values of the field `TAIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TAIER {
+    #[doc = "Interrupt disabled"]
+    TAIE_0,
+    #[doc = "Interrupt enabled"]
+    TAIE_1,
+}
+impl TAIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TAIER::TAIE_0 => false,
+            TAIER::TAIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TAIER {
+        match value {
+            false => TAIER::TAIE_0,
+            true => TAIER::TAIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `TAIE_0`"]
+    #[inline]
+    pub fn is_taie_0(&self) -> bool {
+        *self == TAIER::TAIE_0
+    }
+    #[doc = "Checks if the value of the field is `TAIE_1`"]
+    #[inline]
+    pub fn is_taie_1(&self) -> bool {
+        *self == TAIER::TAIE_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct TACLRR {
+    bits: bool,
+}
+impl TACLRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `MC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum MCR {
+    #[doc = "Stop mode: Timer is halted"]
+    MC_0,
+    #[doc = "Up mode: Timer counts up to TAxCCR0"]
+    MC_1,
+    #[doc = "Continuous mode: Timer counts up to 0FFFFh"]
+    MC_2,
+    #[doc = "Up/down mode: Timer counts up to TAxCCR0 then down to 0000h"]
+    MC_3,
+}
+impl MCR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            MCR::MC_0 => 0,
+            MCR::MC_1 => 1,
+            MCR::MC_2 => 2,
+            MCR::MC_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> MCR {
+        match value {
+            0 => MCR::MC_0,
+            1 => MCR::MC_1,
+            2 => MCR::MC_2,
+            3 => MCR::MC_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `MC_0`"]
+    #[inline]
+    pub fn is_mc_0(&self) -> bool {
+        *self == MCR::MC_0
+    }
+    #[doc = "Checks if the value of the field is `MC_1`"]
+    #[inline]
+    pub fn is_mc_1(&self) -> bool {
+        *self == MCR::MC_1
+    }
+    #[doc = "Checks if the value of the field is `MC_2`"]
+    #[inline]
+    pub fn is_mc_2(&self) -> bool {
+        *self == MCR::MC_2
+    }
+    #[doc = "Checks if the value of the field is `MC_3`"]
+    #[inline]
+    pub fn is_mc_3(&self) -> bool {
+        *self == MCR::MC_3
+    }
+}
+#[doc = "Possible values of the field `ID`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IDR {
+    #[doc = "/1"]
+    ID_0,
+    #[doc = "/2"]
+    ID_1,
+    #[doc = "/4"]
+    ID_2,
+    #[doc = "/8"]
+    ID_3,
+}
+impl IDR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            IDR::ID_0 => 0,
+            IDR::ID_1 => 1,
+            IDR::ID_2 => 2,
+            IDR::ID_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> IDR {
+        match value {
+            0 => IDR::ID_0,
+            1 => IDR::ID_1,
+            2 => IDR::ID_2,
+            3 => IDR::ID_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `ID_0`"]
+    #[inline]
+    pub fn is_id_0(&self) -> bool {
+        *self == IDR::ID_0
+    }
+    #[doc = "Checks if the value of the field is `ID_1`"]
+    #[inline]
+    pub fn is_id_1(&self) -> bool {
+        *self == IDR::ID_1
+    }
+    #[doc = "Checks if the value of the field is `ID_2`"]
+    #[inline]
+    pub fn is_id_2(&self) -> bool {
+        *self == IDR::ID_2
+    }
+    #[doc = "Checks if the value of the field is `ID_3`"]
+    #[inline]
+    pub fn is_id_3(&self) -> bool {
+        *self == IDR::ID_3
+    }
+}
+#[doc = "Possible values of the field `TASSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TASSELR {
+    #[doc = "TAxCLK"]
+    TASSEL_0,
+    #[doc = "ACLK"]
+    TASSEL_1,
+    #[doc = "SMCLK"]
+    TASSEL_2,
+    #[doc = "INCLK"]
+    TASSEL_3,
+}
+impl TASSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            TASSELR::TASSEL_0 => 0,
+            TASSELR::TASSEL_1 => 1,
+            TASSELR::TASSEL_2 => 2,
+            TASSELR::TASSEL_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> TASSELR {
+        match value {
+            0 => TASSELR::TASSEL_0,
+            1 => TASSELR::TASSEL_1,
+            2 => TASSELR::TASSEL_2,
+            3 => TASSELR::TASSEL_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `TASSEL_0`"]
+    #[inline]
+    pub fn is_tassel_0(&self) -> bool {
+        *self == TASSELR::TASSEL_0
+    }
+    #[doc = "Checks if the value of the field is `TASSEL_1`"]
+    #[inline]
+    pub fn is_tassel_1(&self) -> bool {
+        *self == TASSELR::TASSEL_1
+    }
+    #[doc = "Checks if the value of the field is `TASSEL_2`"]
+    #[inline]
+    pub fn is_tassel_2(&self) -> bool {
+        *self == TASSELR::TASSEL_2
+    }
+    #[doc = "Checks if the value of the field is `TASSEL_3`"]
+    #[inline]
+    pub fn is_tassel_3(&self) -> bool {
+        *self == TASSELR::TASSEL_3
+    }
+}
+#[doc = "Values that can be written to the field `TAIFG`"]
+pub enum TAIFGW {
+    #[doc = "No interrupt pending"]
+    TAIFG_0,
+    #[doc = "Interrupt pending"]
+    TAIFG_1,
+}
+impl TAIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TAIFGW::TAIFG_0 => false,
+            TAIFGW::TAIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TAIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TAIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TAIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn taifg_0(self) -> &'a mut W {
+        self.variant(TAIFGW::TAIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn taifg_1(self) -> &'a mut W {
+        self.variant(TAIFGW::TAIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TAIE`"]
+pub enum TAIEW {
+    #[doc = "Interrupt disabled"]
+    TAIE_0,
+    #[doc = "Interrupt enabled"]
+    TAIE_1,
+}
+impl TAIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TAIEW::TAIE_0 => false,
+            TAIEW::TAIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TAIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TAIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TAIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn taie_0(self) -> &'a mut W {
+        self.variant(TAIEW::TAIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn taie_1(self) -> &'a mut W {
+        self.variant(TAIEW::TAIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TACLRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TACLRW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `MC`"]
+pub enum MCW {
+    #[doc = "Stop mode: Timer is halted"]
+    MC_0,
+    #[doc = "Up mode: Timer counts up to TAxCCR0"]
+    MC_1,
+    #[doc = "Continuous mode: Timer counts up to 0FFFFh"]
+    MC_2,
+    #[doc = "Up/down mode: Timer counts up to TAxCCR0 then down to 0000h"]
+    MC_3,
+}
+impl MCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            MCW::MC_0 => 0,
+            MCW::MC_1 => 1,
+            MCW::MC_2 => 2,
+            MCW::MC_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: MCW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Stop mode: Timer is halted"]
+    #[inline]
+    pub fn mc_0(self) -> &'a mut W {
+        self.variant(MCW::MC_0)
+    }
+    #[doc = "Up mode: Timer counts up to TAxCCR0"]
+    #[inline]
+    pub fn mc_1(self) -> &'a mut W {
+        self.variant(MCW::MC_1)
+    }
+    #[doc = "Continuous mode: Timer counts up to 0FFFFh"]
+    #[inline]
+    pub fn mc_2(self) -> &'a mut W {
+        self.variant(MCW::MC_2)
+    }
+    #[doc = "Up/down mode: Timer counts up to TAxCCR0 then down to 0000h"]
+    #[inline]
+    pub fn mc_3(self) -> &'a mut W {
+        self.variant(MCW::MC_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ID`"]
+pub enum IDW {
+    #[doc = "/1"]
+    ID_0,
+    #[doc = "/2"]
+    ID_1,
+    #[doc = "/4"]
+    ID_2,
+    #[doc = "/8"]
+    ID_3,
+}
+impl IDW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            IDW::ID_0 => 0,
+            IDW::ID_1 => 1,
+            IDW::ID_2 => 2,
+            IDW::ID_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _IDW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _IDW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: IDW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "/1"]
+    #[inline]
+    pub fn id_0(self) -> &'a mut W {
+        self.variant(IDW::ID_0)
+    }
+    #[doc = "/2"]
+    #[inline]
+    pub fn id_1(self) -> &'a mut W {
+        self.variant(IDW::ID_1)
+    }
+    #[doc = "/4"]
+    #[inline]
+    pub fn id_2(self) -> &'a mut W {
+        self.variant(IDW::ID_2)
+    }
+    #[doc = "/8"]
+    #[inline]
+    pub fn id_3(self) -> &'a mut W {
+        self.variant(IDW::ID_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TASSEL`"]
+pub enum TASSELW {
+    #[doc = "TAxCLK"]
+    TASSEL_0,
+    #[doc = "ACLK"]
+    TASSEL_1,
+    #[doc = "SMCLK"]
+    TASSEL_2,
+    #[doc = "INCLK"]
+    TASSEL_3,
+}
+impl TASSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            TASSELW::TASSEL_0 => 0,
+            TASSELW::TASSEL_1 => 1,
+            TASSELW::TASSEL_2 => 2,
+            TASSELW::TASSEL_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TASSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TASSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TASSELW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "TAxCLK"]
+    #[inline]
+    pub fn tassel_0(self) -> &'a mut W {
+        self.variant(TASSELW::TASSEL_0)
+    }
+    #[doc = "ACLK"]
+    #[inline]
+    pub fn tassel_1(self) -> &'a mut W {
+        self.variant(TASSELW::TASSEL_1)
+    }
+    #[doc = "SMCLK"]
+    #[inline]
+    pub fn tassel_2(self) -> &'a mut W {
+        self.variant(TASSELW::TASSEL_2)
+    }
+    #[doc = "INCLK"]
+    #[inline]
+    pub fn tassel_3(self) -> &'a mut W {
+        self.variant(TASSELW::TASSEL_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - TimerA interrupt flag"]
+    #[inline]
+    pub fn taifg(&self) -> TAIFGR {
+        TAIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - TimerA interrupt enable"]
+    #[inline]
+    pub fn taie(&self) -> TAIER {
+        TAIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - TimerA clear"]
+    #[inline]
+    pub fn taclr(&self) -> TACLRR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        };
+        TACLRR { bits }
+    }
+    #[doc = "Bits 4:5 - Mode control"]
+    #[inline]
+    pub fn mc(&self) -> MCR {
+        MCR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bits 6:7 - Input divider"]
+    #[inline]
+    pub fn id(&self) -> IDR {
+        IDR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bits 8:9 - TimerA clock source select"]
+    #[inline]
+    pub fn tassel(&self) -> TASSELR {
+        TASSELR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - TimerA interrupt flag"]
+    #[inline]
+    pub fn taifg(&mut self) -> _TAIFGW {
+        _TAIFGW { w: self }
+    }
+    #[doc = "Bit 1 - TimerA interrupt enable"]
+    #[inline]
+    pub fn taie(&mut self) -> _TAIEW {
+        _TAIEW { w: self }
+    }
+    #[doc = "Bit 2 - TimerA clear"]
+    #[inline]
+    pub fn taclr(&mut self) -> _TACLRW {
+        _TACLRW { w: self }
+    }
+    #[doc = "Bits 4:5 - Mode control"]
+    #[inline]
+    pub fn mc(&mut self) -> _MCW {
+        _MCW { w: self }
+    }
+    #[doc = "Bits 6:7 - Input divider"]
+    #[inline]
+    pub fn id(&mut self) -> _IDW {
+        _IDW { w: self }
+    }
+    #[doc = "Bits 8:9 - TimerA clock source select"]
+    #[inline]
+    pub fn tassel(&mut self) -> _TASSELW {
+        _TASSELW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/timer_a2/tax_ex0.rs b/example-source/msp432p401r/src/timer_a2/tax_ex0.rs
new file mode 100644
index 0000000..cc9bd3f
--- /dev/null
+++ b/example-source/msp432p401r/src/timer_a2/tax_ex0.rs
@@ -0,0 +1,268 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::TAXEX0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `TAIDEX`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TAIDEXR {
+    #[doc = "Divide by 1"]
+    TAIDEX_0,
+    #[doc = "Divide by 2"]
+    TAIDEX_1,
+    #[doc = "Divide by 3"]
+    TAIDEX_2,
+    #[doc = "Divide by 4"]
+    TAIDEX_3,
+    #[doc = "Divide by 5"]
+    TAIDEX_4,
+    #[doc = "Divide by 6"]
+    TAIDEX_5,
+    #[doc = "Divide by 7"]
+    TAIDEX_6,
+    #[doc = "Divide by 8"]
+    TAIDEX_7,
+}
+impl TAIDEXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            TAIDEXR::TAIDEX_0 => 0,
+            TAIDEXR::TAIDEX_1 => 1,
+            TAIDEXR::TAIDEX_2 => 2,
+            TAIDEXR::TAIDEX_3 => 3,
+            TAIDEXR::TAIDEX_4 => 4,
+            TAIDEXR::TAIDEX_5 => 5,
+            TAIDEXR::TAIDEX_6 => 6,
+            TAIDEXR::TAIDEX_7 => 7,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> TAIDEXR {
+        match value {
+            0 => TAIDEXR::TAIDEX_0,
+            1 => TAIDEXR::TAIDEX_1,
+            2 => TAIDEXR::TAIDEX_2,
+            3 => TAIDEXR::TAIDEX_3,
+            4 => TAIDEXR::TAIDEX_4,
+            5 => TAIDEXR::TAIDEX_5,
+            6 => TAIDEXR::TAIDEX_6,
+            7 => TAIDEXR::TAIDEX_7,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_0`"]
+    #[inline]
+    pub fn is_taidex_0(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_0
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_1`"]
+    #[inline]
+    pub fn is_taidex_1(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_1
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_2`"]
+    #[inline]
+    pub fn is_taidex_2(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_2
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_3`"]
+    #[inline]
+    pub fn is_taidex_3(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_3
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_4`"]
+    #[inline]
+    pub fn is_taidex_4(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_4
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_5`"]
+    #[inline]
+    pub fn is_taidex_5(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_5
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_6`"]
+    #[inline]
+    pub fn is_taidex_6(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_6
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_7`"]
+    #[inline]
+    pub fn is_taidex_7(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_7
+    }
+}
+#[doc = "Values that can be written to the field `TAIDEX`"]
+pub enum TAIDEXW {
+    #[doc = "Divide by 1"]
+    TAIDEX_0,
+    #[doc = "Divide by 2"]
+    TAIDEX_1,
+    #[doc = "Divide by 3"]
+    TAIDEX_2,
+    #[doc = "Divide by 4"]
+    TAIDEX_3,
+    #[doc = "Divide by 5"]
+    TAIDEX_4,
+    #[doc = "Divide by 6"]
+    TAIDEX_5,
+    #[doc = "Divide by 7"]
+    TAIDEX_6,
+    #[doc = "Divide by 8"]
+    TAIDEX_7,
+}
+impl TAIDEXW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            TAIDEXW::TAIDEX_0 => 0,
+            TAIDEXW::TAIDEX_1 => 1,
+            TAIDEXW::TAIDEX_2 => 2,
+            TAIDEXW::TAIDEX_3 => 3,
+            TAIDEXW::TAIDEX_4 => 4,
+            TAIDEXW::TAIDEX_5 => 5,
+            TAIDEXW::TAIDEX_6 => 6,
+            TAIDEXW::TAIDEX_7 => 7,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TAIDEXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TAIDEXW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TAIDEXW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Divide by 1"]
+    #[inline]
+    pub fn taidex_0(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_0)
+    }
+    #[doc = "Divide by 2"]
+    #[inline]
+    pub fn taidex_1(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_1)
+    }
+    #[doc = "Divide by 3"]
+    #[inline]
+    pub fn taidex_2(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_2)
+    }
+    #[doc = "Divide by 4"]
+    #[inline]
+    pub fn taidex_3(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_3)
+    }
+    #[doc = "Divide by 5"]
+    #[inline]
+    pub fn taidex_4(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_4)
+    }
+    #[doc = "Divide by 6"]
+    #[inline]
+    pub fn taidex_5(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_5)
+    }
+    #[doc = "Divide by 7"]
+    #[inline]
+    pub fn taidex_6(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_6)
+    }
+    #[doc = "Divide by 8"]
+    #[inline]
+    pub fn taidex_7(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_7)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:2 - Input divider expansion"]
+    #[inline]
+    pub fn taidex(&self) -> TAIDEXR {
+        TAIDEXR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:2 - Input divider expansion"]
+    #[inline]
+    pub fn taidex(&mut self) -> _TAIDEXW {
+        _TAIDEXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/timer_a2/tax_iv.rs b/example-source/msp432p401r/src/timer_a2/tax_iv.rs
new file mode 100644
index 0000000..a83ed36
--- /dev/null
+++ b/example-source/msp432p401r/src/timer_a2/tax_iv.rs
@@ -0,0 +1,124 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::TAXIV {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `TAIV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TAIVR {
+    #[doc = "No interrupt pending"]
+    TAIV_0,
+    #[doc = "Interrupt Source: Capture/compare 1; Interrupt Flag: TAxCCR1 CCIFG; Interrupt Priority: Highest"]
+    TAIV_2,
+    #[doc = "Interrupt Source: Capture/compare 2; Interrupt Flag: TAxCCR2 CCIFG"]
+    TAIV_4,
+    #[doc = "Interrupt Source: Capture/compare 3; Interrupt Flag: TAxCCR3 CCIFG"]
+    TAIV_6,
+    #[doc = "Interrupt Source: Capture/compare 4; Interrupt Flag: TAxCCR4 CCIFG"]
+    TAIV_8,
+    #[doc = "Interrupt Source: Capture/compare 5; Interrupt Flag: TAxCCR5 CCIFG"]
+    TAIV_10,
+    #[doc = "Interrupt Source: Capture/compare 6; Interrupt Flag: TAxCCR6 CCIFG"]
+    TAIV_12,
+    #[doc = "Interrupt Source: Timer overflow; Interrupt Flag: TAxCTL TAIFG; Interrupt Priority: Lowest"]
+    TAIV_14,
+    #[doc = r" Reserved"]
+    _Reserved(u16),
+}
+impl TAIVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        match *self {
+            TAIVR::TAIV_0 => 0,
+            TAIVR::TAIV_2 => 2,
+            TAIVR::TAIV_4 => 4,
+            TAIVR::TAIV_6 => 6,
+            TAIVR::TAIV_8 => 8,
+            TAIVR::TAIV_10 => 10,
+            TAIVR::TAIV_12 => 12,
+            TAIVR::TAIV_14 => 14,
+            TAIVR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u16) -> TAIVR {
+        match value {
+            0 => TAIVR::TAIV_0,
+            2 => TAIVR::TAIV_2,
+            4 => TAIVR::TAIV_4,
+            6 => TAIVR::TAIV_6,
+            8 => TAIVR::TAIV_8,
+            10 => TAIVR::TAIV_10,
+            12 => TAIVR::TAIV_12,
+            14 => TAIVR::TAIV_14,
+            i => TAIVR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `TAIV_0`"]
+    #[inline]
+    pub fn is_taiv_0(&self) -> bool {
+        *self == TAIVR::TAIV_0
+    }
+    #[doc = "Checks if the value of the field is `TAIV_2`"]
+    #[inline]
+    pub fn is_taiv_2(&self) -> bool {
+        *self == TAIVR::TAIV_2
+    }
+    #[doc = "Checks if the value of the field is `TAIV_4`"]
+    #[inline]
+    pub fn is_taiv_4(&self) -> bool {
+        *self == TAIVR::TAIV_4
+    }
+    #[doc = "Checks if the value of the field is `TAIV_6`"]
+    #[inline]
+    pub fn is_taiv_6(&self) -> bool {
+        *self == TAIVR::TAIV_6
+    }
+    #[doc = "Checks if the value of the field is `TAIV_8`"]
+    #[inline]
+    pub fn is_taiv_8(&self) -> bool {
+        *self == TAIVR::TAIV_8
+    }
+    #[doc = "Checks if the value of the field is `TAIV_10`"]
+    #[inline]
+    pub fn is_taiv_10(&self) -> bool {
+        *self == TAIVR::TAIV_10
+    }
+    #[doc = "Checks if the value of the field is `TAIV_12`"]
+    #[inline]
+    pub fn is_taiv_12(&self) -> bool {
+        *self == TAIVR::TAIV_12
+    }
+    #[doc = "Checks if the value of the field is `TAIV_14`"]
+    #[inline]
+    pub fn is_taiv_14(&self) -> bool {
+        *self == TAIVR::TAIV_14
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - TimerA interrupt vector value"]
+    #[inline]
+    pub fn taiv(&self) -> TAIVR {
+        TAIVR::_from({
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/timer_a2/tax_r.rs b/example-source/msp432p401r/src/timer_a2/tax_r.rs
new file mode 100644
index 0000000..3542361
--- /dev/null
+++ b/example-source/msp432p401r/src/timer_a2/tax_r.rs
@@ -0,0 +1,64 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::TAXR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+}
diff --git a/example-source/msp432p401r/src/timer_a3.rs b/example-source/msp432p401r/src/timer_a3.rs
new file mode 100644
index 0000000..89bd30a
--- /dev/null
+++ b/example-source/msp432p401r/src/timer_a3.rs
@@ -0,0 +1,55 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - TimerAx Control Register"]
+    pub tax_ctl: TAXCTL,
+    #[doc = "0x02 - Timer_A Capture/Compare Control Register"]
+    pub tax_cctl: [TAXCCTL; 5],
+    _reserved0: [u8; 4usize],
+    #[doc = "0x10 - TimerA register"]
+    pub tax_r: TAXR,
+    #[doc = "0x12 - Timer_A Capture/Compare Register"]
+    pub tax_ccr: [TAXCCR; 5],
+    _reserved1: [u8; 4usize],
+    #[doc = "0x20 - TimerAx Expansion 0 Register"]
+    pub tax_ex0: TAXEX0,
+    _reserved2: [u8; 12usize],
+    #[doc = "0x2e - TimerAx Interrupt Vector Register"]
+    pub tax_iv: TAXIV,
+}
+#[doc = "TimerAx Control Register"]
+pub struct TAXCTL {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "TimerAx Control Register"]
+pub mod tax_ctl;
+#[doc = "Timer_A Capture/Compare Control Register"]
+pub struct TAXCCTL {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Timer_A Capture/Compare Control Register"]
+pub mod tax_cctl;
+#[doc = "TimerA register"]
+pub struct TAXR {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "TimerA register"]
+pub mod tax_r;
+#[doc = "Timer_A Capture/Compare Register"]
+pub struct TAXCCR {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Timer_A Capture/Compare Register"]
+pub mod tax_ccr;
+#[doc = "TimerAx Expansion 0 Register"]
+pub struct TAXEX0 {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "TimerAx Expansion 0 Register"]
+pub mod tax_ex0;
+#[doc = "TimerAx Interrupt Vector Register"]
+pub struct TAXIV {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "TimerAx Interrupt Vector Register"]
+pub mod tax_iv;
diff --git a/example-source/msp432p401r/src/timer_a3/tax_ccr.rs b/example-source/msp432p401r/src/timer_a3/tax_ccr.rs
new file mode 100644
index 0000000..f533aed
--- /dev/null
+++ b/example-source/msp432p401r/src/timer_a3/tax_ccr.rs
@@ -0,0 +1,105 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::TAXCCR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct TAXRR {
+    bits: u16,
+}
+impl TAXRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TAXRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TAXRW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - TimerA register"]
+    #[inline]
+    pub fn tax_r(&self) -> TAXRR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        };
+        TAXRR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - TimerA register"]
+    #[inline]
+    pub fn tax_r(&mut self) -> _TAXRW {
+        _TAXRW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/timer_a3/tax_cctl.rs b/example-source/msp432p401r/src/timer_a3/tax_cctl.rs
new file mode 100644
index 0000000..65d41c1
--- /dev/null
+++ b/example-source/msp432p401r/src/timer_a3/tax_cctl.rs
@@ -0,0 +1,1344 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::TAXCCTL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `CCIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CCIFGR {
+    #[doc = "No interrupt pending"]
+    CCIFG_0,
+    #[doc = "Interrupt pending"]
+    CCIFG_1,
+}
+impl CCIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CCIFGR::CCIFG_0 => false,
+            CCIFGR::CCIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CCIFGR {
+        match value {
+            false => CCIFGR::CCIFG_0,
+            true => CCIFGR::CCIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CCIFG_0`"]
+    #[inline]
+    pub fn is_ccifg_0(&self) -> bool {
+        *self == CCIFGR::CCIFG_0
+    }
+    #[doc = "Checks if the value of the field is `CCIFG_1`"]
+    #[inline]
+    pub fn is_ccifg_1(&self) -> bool {
+        *self == CCIFGR::CCIFG_1
+    }
+}
+#[doc = "Possible values of the field `COV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum COVR {
+    #[doc = "No capture overflow occurred"]
+    COV_0,
+    #[doc = "Capture overflow occurred"]
+    COV_1,
+}
+impl COVR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            COVR::COV_0 => false,
+            COVR::COV_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> COVR {
+        match value {
+            false => COVR::COV_0,
+            true => COVR::COV_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `COV_0`"]
+    #[inline]
+    pub fn is_cov_0(&self) -> bool {
+        *self == COVR::COV_0
+    }
+    #[doc = "Checks if the value of the field is `COV_1`"]
+    #[inline]
+    pub fn is_cov_1(&self) -> bool {
+        *self == COVR::COV_1
+    }
+}
+#[doc = "Possible values of the field `OUT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum OUTR {
+    #[doc = "Output low"]
+    OUT_0,
+    #[doc = "Output high"]
+    OUT_1,
+}
+impl OUTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            OUTR::OUT_0 => false,
+            OUTR::OUT_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> OUTR {
+        match value {
+            false => OUTR::OUT_0,
+            true => OUTR::OUT_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `OUT_0`"]
+    #[inline]
+    pub fn is_out_0(&self) -> bool {
+        *self == OUTR::OUT_0
+    }
+    #[doc = "Checks if the value of the field is `OUT_1`"]
+    #[inline]
+    pub fn is_out_1(&self) -> bool {
+        *self == OUTR::OUT_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CCIR {
+    bits: bool,
+}
+impl CCIR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `CCIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CCIER {
+    #[doc = "Interrupt disabled"]
+    CCIE_0,
+    #[doc = "Interrupt enabled"]
+    CCIE_1,
+}
+impl CCIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CCIER::CCIE_0 => false,
+            CCIER::CCIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CCIER {
+        match value {
+            false => CCIER::CCIE_0,
+            true => CCIER::CCIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CCIE_0`"]
+    #[inline]
+    pub fn is_ccie_0(&self) -> bool {
+        *self == CCIER::CCIE_0
+    }
+    #[doc = "Checks if the value of the field is `CCIE_1`"]
+    #[inline]
+    pub fn is_ccie_1(&self) -> bool {
+        *self == CCIER::CCIE_1
+    }
+}
+#[doc = "Possible values of the field `OUTMOD`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum OUTMODR {
+    #[doc = "OUT bit value"]
+    OUTMOD_0,
+    #[doc = "Set"]
+    OUTMOD_1,
+    #[doc = "Toggle/reset"]
+    OUTMOD_2,
+    #[doc = "Set/reset"]
+    OUTMOD_3,
+    #[doc = "Toggle"]
+    OUTMOD_4,
+    #[doc = "Reset"]
+    OUTMOD_5,
+    #[doc = "Toggle/set"]
+    OUTMOD_6,
+    #[doc = "Reset/set"]
+    OUTMOD_7,
+}
+impl OUTMODR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            OUTMODR::OUTMOD_0 => 0,
+            OUTMODR::OUTMOD_1 => 1,
+            OUTMODR::OUTMOD_2 => 2,
+            OUTMODR::OUTMOD_3 => 3,
+            OUTMODR::OUTMOD_4 => 4,
+            OUTMODR::OUTMOD_5 => 5,
+            OUTMODR::OUTMOD_6 => 6,
+            OUTMODR::OUTMOD_7 => 7,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> OUTMODR {
+        match value {
+            0 => OUTMODR::OUTMOD_0,
+            1 => OUTMODR::OUTMOD_1,
+            2 => OUTMODR::OUTMOD_2,
+            3 => OUTMODR::OUTMOD_3,
+            4 => OUTMODR::OUTMOD_4,
+            5 => OUTMODR::OUTMOD_5,
+            6 => OUTMODR::OUTMOD_6,
+            7 => OUTMODR::OUTMOD_7,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_0`"]
+    #[inline]
+    pub fn is_outmod_0(&self) -> bool {
+        *self == OUTMODR::OUTMOD_0
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_1`"]
+    #[inline]
+    pub fn is_outmod_1(&self) -> bool {
+        *self == OUTMODR::OUTMOD_1
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_2`"]
+    #[inline]
+    pub fn is_outmod_2(&self) -> bool {
+        *self == OUTMODR::OUTMOD_2
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_3`"]
+    #[inline]
+    pub fn is_outmod_3(&self) -> bool {
+        *self == OUTMODR::OUTMOD_3
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_4`"]
+    #[inline]
+    pub fn is_outmod_4(&self) -> bool {
+        *self == OUTMODR::OUTMOD_4
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_5`"]
+    #[inline]
+    pub fn is_outmod_5(&self) -> bool {
+        *self == OUTMODR::OUTMOD_5
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_6`"]
+    #[inline]
+    pub fn is_outmod_6(&self) -> bool {
+        *self == OUTMODR::OUTMOD_6
+    }
+    #[doc = "Checks if the value of the field is `OUTMOD_7`"]
+    #[inline]
+    pub fn is_outmod_7(&self) -> bool {
+        *self == OUTMODR::OUTMOD_7
+    }
+}
+#[doc = "Possible values of the field `CAP`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CAPR {
+    #[doc = "Compare mode"]
+    CAP_0,
+    #[doc = "Capture mode"]
+    CAP_1,
+}
+impl CAPR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CAPR::CAP_0 => false,
+            CAPR::CAP_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CAPR {
+        match value {
+            false => CAPR::CAP_0,
+            true => CAPR::CAP_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CAP_0`"]
+    #[inline]
+    pub fn is_cap_0(&self) -> bool {
+        *self == CAPR::CAP_0
+    }
+    #[doc = "Checks if the value of the field is `CAP_1`"]
+    #[inline]
+    pub fn is_cap_1(&self) -> bool {
+        *self == CAPR::CAP_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SCCIR {
+    bits: bool,
+}
+impl SCCIR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `SCS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SCSR {
+    #[doc = "Asynchronous capture"]
+    SCS_0,
+    #[doc = "Synchronous capture"]
+    SCS_1,
+}
+impl SCSR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            SCSR::SCS_0 => false,
+            SCSR::SCS_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> SCSR {
+        match value {
+            false => SCSR::SCS_0,
+            true => SCSR::SCS_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SCS_0`"]
+    #[inline]
+    pub fn is_scs_0(&self) -> bool {
+        *self == SCSR::SCS_0
+    }
+    #[doc = "Checks if the value of the field is `SCS_1`"]
+    #[inline]
+    pub fn is_scs_1(&self) -> bool {
+        *self == SCSR::SCS_1
+    }
+}
+#[doc = "Possible values of the field `CCIS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CCISR {
+    #[doc = "CCIxA"]
+    CCIS_0,
+    #[doc = "CCIxB"]
+    CCIS_1,
+    #[doc = "GND"]
+    CCIS_2,
+    #[doc = "VCC"]
+    CCIS_3,
+}
+impl CCISR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            CCISR::CCIS_0 => 0,
+            CCISR::CCIS_1 => 1,
+            CCISR::CCIS_2 => 2,
+            CCISR::CCIS_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> CCISR {
+        match value {
+            0 => CCISR::CCIS_0,
+            1 => CCISR::CCIS_1,
+            2 => CCISR::CCIS_2,
+            3 => CCISR::CCIS_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `CCIS_0`"]
+    #[inline]
+    pub fn is_ccis_0(&self) -> bool {
+        *self == CCISR::CCIS_0
+    }
+    #[doc = "Checks if the value of the field is `CCIS_1`"]
+    #[inline]
+    pub fn is_ccis_1(&self) -> bool {
+        *self == CCISR::CCIS_1
+    }
+    #[doc = "Checks if the value of the field is `CCIS_2`"]
+    #[inline]
+    pub fn is_ccis_2(&self) -> bool {
+        *self == CCISR::CCIS_2
+    }
+    #[doc = "Checks if the value of the field is `CCIS_3`"]
+    #[inline]
+    pub fn is_ccis_3(&self) -> bool {
+        *self == CCISR::CCIS_3
+    }
+}
+#[doc = "Possible values of the field `CM`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CMR {
+    #[doc = "No capture"]
+    CM_0,
+    #[doc = "Capture on rising edge"]
+    CM_1,
+    #[doc = "Capture on falling edge"]
+    CM_2,
+    #[doc = "Capture on both rising and falling edges"]
+    CM_3,
+}
+impl CMR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            CMR::CM_0 => 0,
+            CMR::CM_1 => 1,
+            CMR::CM_2 => 2,
+            CMR::CM_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> CMR {
+        match value {
+            0 => CMR::CM_0,
+            1 => CMR::CM_1,
+            2 => CMR::CM_2,
+            3 => CMR::CM_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `CM_0`"]
+    #[inline]
+    pub fn is_cm_0(&self) -> bool {
+        *self == CMR::CM_0
+    }
+    #[doc = "Checks if the value of the field is `CM_1`"]
+    #[inline]
+    pub fn is_cm_1(&self) -> bool {
+        *self == CMR::CM_1
+    }
+    #[doc = "Checks if the value of the field is `CM_2`"]
+    #[inline]
+    pub fn is_cm_2(&self) -> bool {
+        *self == CMR::CM_2
+    }
+    #[doc = "Checks if the value of the field is `CM_3`"]
+    #[inline]
+    pub fn is_cm_3(&self) -> bool {
+        *self == CMR::CM_3
+    }
+}
+#[doc = "Values that can be written to the field `CCIFG`"]
+pub enum CCIFGW {
+    #[doc = "No interrupt pending"]
+    CCIFG_0,
+    #[doc = "Interrupt pending"]
+    CCIFG_1,
+}
+impl CCIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CCIFGW::CCIFG_0 => false,
+            CCIFGW::CCIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CCIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CCIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CCIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn ccifg_0(self) -> &'a mut W {
+        self.variant(CCIFGW::CCIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn ccifg_1(self) -> &'a mut W {
+        self.variant(CCIFGW::CCIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `COV`"]
+pub enum COVW {
+    #[doc = "No capture overflow occurred"]
+    COV_0,
+    #[doc = "Capture overflow occurred"]
+    COV_1,
+}
+impl COVW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            COVW::COV_0 => false,
+            COVW::COV_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _COVW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _COVW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: COVW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No capture overflow occurred"]
+    #[inline]
+    pub fn cov_0(self) -> &'a mut W {
+        self.variant(COVW::COV_0)
+    }
+    #[doc = "Capture overflow occurred"]
+    #[inline]
+    pub fn cov_1(self) -> &'a mut W {
+        self.variant(COVW::COV_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `OUT`"]
+pub enum OUTW {
+    #[doc = "Output low"]
+    OUT_0,
+    #[doc = "Output high"]
+    OUT_1,
+}
+impl OUTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            OUTW::OUT_0 => false,
+            OUTW::OUT_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _OUTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _OUTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: OUTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Output low"]
+    #[inline]
+    pub fn out_0(self) -> &'a mut W {
+        self.variant(OUTW::OUT_0)
+    }
+    #[doc = "Output high"]
+    #[inline]
+    pub fn out_1(self) -> &'a mut W {
+        self.variant(OUTW::OUT_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CCIE`"]
+pub enum CCIEW {
+    #[doc = "Interrupt disabled"]
+    CCIE_0,
+    #[doc = "Interrupt enabled"]
+    CCIE_1,
+}
+impl CCIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CCIEW::CCIE_0 => false,
+            CCIEW::CCIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CCIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CCIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CCIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn ccie_0(self) -> &'a mut W {
+        self.variant(CCIEW::CCIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn ccie_1(self) -> &'a mut W {
+        self.variant(CCIEW::CCIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `OUTMOD`"]
+pub enum OUTMODW {
+    #[doc = "OUT bit value"]
+    OUTMOD_0,
+    #[doc = "Set"]
+    OUTMOD_1,
+    #[doc = "Toggle/reset"]
+    OUTMOD_2,
+    #[doc = "Set/reset"]
+    OUTMOD_3,
+    #[doc = "Toggle"]
+    OUTMOD_4,
+    #[doc = "Reset"]
+    OUTMOD_5,
+    #[doc = "Toggle/set"]
+    OUTMOD_6,
+    #[doc = "Reset/set"]
+    OUTMOD_7,
+}
+impl OUTMODW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            OUTMODW::OUTMOD_0 => 0,
+            OUTMODW::OUTMOD_1 => 1,
+            OUTMODW::OUTMOD_2 => 2,
+            OUTMODW::OUTMOD_3 => 3,
+            OUTMODW::OUTMOD_4 => 4,
+            OUTMODW::OUTMOD_5 => 5,
+            OUTMODW::OUTMOD_6 => 6,
+            OUTMODW::OUTMOD_7 => 7,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _OUTMODW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _OUTMODW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: OUTMODW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "OUT bit value"]
+    #[inline]
+    pub fn outmod_0(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_0)
+    }
+    #[doc = "Set"]
+    #[inline]
+    pub fn outmod_1(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_1)
+    }
+    #[doc = "Toggle/reset"]
+    #[inline]
+    pub fn outmod_2(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_2)
+    }
+    #[doc = "Set/reset"]
+    #[inline]
+    pub fn outmod_3(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_3)
+    }
+    #[doc = "Toggle"]
+    #[inline]
+    pub fn outmod_4(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_4)
+    }
+    #[doc = "Reset"]
+    #[inline]
+    pub fn outmod_5(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_5)
+    }
+    #[doc = "Toggle/set"]
+    #[inline]
+    pub fn outmod_6(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_6)
+    }
+    #[doc = "Reset/set"]
+    #[inline]
+    pub fn outmod_7(self) -> &'a mut W {
+        self.variant(OUTMODW::OUTMOD_7)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CAP`"]
+pub enum CAPW {
+    #[doc = "Compare mode"]
+    CAP_0,
+    #[doc = "Capture mode"]
+    CAP_1,
+}
+impl CAPW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CAPW::CAP_0 => false,
+            CAPW::CAP_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CAPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CAPW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CAPW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Compare mode"]
+    #[inline]
+    pub fn cap_0(self) -> &'a mut W {
+        self.variant(CAPW::CAP_0)
+    }
+    #[doc = "Capture mode"]
+    #[inline]
+    pub fn cap_1(self) -> &'a mut W {
+        self.variant(CAPW::CAP_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SCCIW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SCCIW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `SCS`"]
+pub enum SCSW {
+    #[doc = "Asynchronous capture"]
+    SCS_0,
+    #[doc = "Synchronous capture"]
+    SCS_1,
+}
+impl SCSW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            SCSW::SCS_0 => false,
+            SCSW::SCS_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SCSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SCSW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SCSW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Asynchronous capture"]
+    #[inline]
+    pub fn scs_0(self) -> &'a mut W {
+        self.variant(SCSW::SCS_0)
+    }
+    #[doc = "Synchronous capture"]
+    #[inline]
+    pub fn scs_1(self) -> &'a mut W {
+        self.variant(SCSW::SCS_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CCIS`"]
+pub enum CCISW {
+    #[doc = "CCIxA"]
+    CCIS_0,
+    #[doc = "CCIxB"]
+    CCIS_1,
+    #[doc = "GND"]
+    CCIS_2,
+    #[doc = "VCC"]
+    CCIS_3,
+}
+impl CCISW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            CCISW::CCIS_0 => 0,
+            CCISW::CCIS_1 => 1,
+            CCISW::CCIS_2 => 2,
+            CCISW::CCIS_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CCISW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CCISW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CCISW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "CCIxA"]
+    #[inline]
+    pub fn ccis_0(self) -> &'a mut W {
+        self.variant(CCISW::CCIS_0)
+    }
+    #[doc = "CCIxB"]
+    #[inline]
+    pub fn ccis_1(self) -> &'a mut W {
+        self.variant(CCISW::CCIS_1)
+    }
+    #[doc = "GND"]
+    #[inline]
+    pub fn ccis_2(self) -> &'a mut W {
+        self.variant(CCISW::CCIS_2)
+    }
+    #[doc = "VCC"]
+    #[inline]
+    pub fn ccis_3(self) -> &'a mut W {
+        self.variant(CCISW::CCIS_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CM`"]
+pub enum CMW {
+    #[doc = "No capture"]
+    CM_0,
+    #[doc = "Capture on rising edge"]
+    CM_1,
+    #[doc = "Capture on falling edge"]
+    CM_2,
+    #[doc = "Capture on both rising and falling edges"]
+    CM_3,
+}
+impl CMW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            CMW::CM_0 => 0,
+            CMW::CM_1 => 1,
+            CMW::CM_2 => 2,
+            CMW::CM_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CMW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CMW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CMW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "No capture"]
+    #[inline]
+    pub fn cm_0(self) -> &'a mut W {
+        self.variant(CMW::CM_0)
+    }
+    #[doc = "Capture on rising edge"]
+    #[inline]
+    pub fn cm_1(self) -> &'a mut W {
+        self.variant(CMW::CM_1)
+    }
+    #[doc = "Capture on falling edge"]
+    #[inline]
+    pub fn cm_2(self) -> &'a mut W {
+        self.variant(CMW::CM_2)
+    }
+    #[doc = "Capture on both rising and falling edges"]
+    #[inline]
+    pub fn cm_3(self) -> &'a mut W {
+        self.variant(CMW::CM_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 14;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Capture/compare interrupt flag"]
+    #[inline]
+    pub fn ccifg(&self) -> CCIFGR {
+        CCIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - Capture overflow"]
+    #[inline]
+    pub fn cov(&self) -> COVR {
+        COVR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - Output"]
+    #[inline]
+    pub fn out(&self) -> OUTR {
+        OUTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 3 - Capture/compare input"]
+    #[inline]
+    pub fn cci(&self) -> CCIR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        };
+        CCIR { bits }
+    }
+    #[doc = "Bit 4 - Capture/compare interrupt enable"]
+    #[inline]
+    pub fn ccie(&self) -> CCIER {
+        CCIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 5:7 - Output mode"]
+    #[inline]
+    pub fn outmod(&self) -> OUTMODR {
+        OUTMODR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 8 - Capture mode"]
+    #[inline]
+    pub fn cap(&self) -> CAPR {
+        CAPR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 10 - Synchronized capture/compare input"]
+    #[inline]
+    pub fn scci(&self) -> SCCIR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        };
+        SCCIR { bits }
+    }
+    #[doc = "Bit 11 - Synchronize capture source"]
+    #[inline]
+    pub fn scs(&self) -> SCSR {
+        SCSR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 12:13 - Capture/compare input select"]
+    #[inline]
+    pub fn ccis(&self) -> CCISR {
+        CCISR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bits 14:15 - Capture mode"]
+    #[inline]
+    pub fn cm(&self) -> CMR {
+        CMR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 14;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Capture/compare interrupt flag"]
+    #[inline]
+    pub fn ccifg(&mut self) -> _CCIFGW {
+        _CCIFGW { w: self }
+    }
+    #[doc = "Bit 1 - Capture overflow"]
+    #[inline]
+    pub fn cov(&mut self) -> _COVW {
+        _COVW { w: self }
+    }
+    #[doc = "Bit 2 - Output"]
+    #[inline]
+    pub fn out(&mut self) -> _OUTW {
+        _OUTW { w: self }
+    }
+    #[doc = "Bit 4 - Capture/compare interrupt enable"]
+    #[inline]
+    pub fn ccie(&mut self) -> _CCIEW {
+        _CCIEW { w: self }
+    }
+    #[doc = "Bits 5:7 - Output mode"]
+    #[inline]
+    pub fn outmod(&mut self) -> _OUTMODW {
+        _OUTMODW { w: self }
+    }
+    #[doc = "Bit 8 - Capture mode"]
+    #[inline]
+    pub fn cap(&mut self) -> _CAPW {
+        _CAPW { w: self }
+    }
+    #[doc = "Bit 10 - Synchronized capture/compare input"]
+    #[inline]
+    pub fn scci(&mut self) -> _SCCIW {
+        _SCCIW { w: self }
+    }
+    #[doc = "Bit 11 - Synchronize capture source"]
+    #[inline]
+    pub fn scs(&mut self) -> _SCSW {
+        _SCSW { w: self }
+    }
+    #[doc = "Bits 12:13 - Capture/compare input select"]
+    #[inline]
+    pub fn ccis(&mut self) -> _CCISW {
+        _CCISW { w: self }
+    }
+    #[doc = "Bits 14:15 - Capture mode"]
+    #[inline]
+    pub fn cm(&mut self) -> _CMW {
+        _CMW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/timer_a3/tax_ctl.rs b/example-source/msp432p401r/src/timer_a3/tax_ctl.rs
new file mode 100644
index 0000000..938a26f
--- /dev/null
+++ b/example-source/msp432p401r/src/timer_a3/tax_ctl.rs
@@ -0,0 +1,769 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::TAXCTL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `TAIFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TAIFGR {
+    #[doc = "No interrupt pending"]
+    TAIFG_0,
+    #[doc = "Interrupt pending"]
+    TAIFG_1,
+}
+impl TAIFGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TAIFGR::TAIFG_0 => false,
+            TAIFGR::TAIFG_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TAIFGR {
+        match value {
+            false => TAIFGR::TAIFG_0,
+            true => TAIFGR::TAIFG_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `TAIFG_0`"]
+    #[inline]
+    pub fn is_taifg_0(&self) -> bool {
+        *self == TAIFGR::TAIFG_0
+    }
+    #[doc = "Checks if the value of the field is `TAIFG_1`"]
+    #[inline]
+    pub fn is_taifg_1(&self) -> bool {
+        *self == TAIFGR::TAIFG_1
+    }
+}
+#[doc = "Possible values of the field `TAIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TAIER {
+    #[doc = "Interrupt disabled"]
+    TAIE_0,
+    #[doc = "Interrupt enabled"]
+    TAIE_1,
+}
+impl TAIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TAIER::TAIE_0 => false,
+            TAIER::TAIE_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TAIER {
+        match value {
+            false => TAIER::TAIE_0,
+            true => TAIER::TAIE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `TAIE_0`"]
+    #[inline]
+    pub fn is_taie_0(&self) -> bool {
+        *self == TAIER::TAIE_0
+    }
+    #[doc = "Checks if the value of the field is `TAIE_1`"]
+    #[inline]
+    pub fn is_taie_1(&self) -> bool {
+        *self == TAIER::TAIE_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct TACLRR {
+    bits: bool,
+}
+impl TACLRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `MC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum MCR {
+    #[doc = "Stop mode: Timer is halted"]
+    MC_0,
+    #[doc = "Up mode: Timer counts up to TAxCCR0"]
+    MC_1,
+    #[doc = "Continuous mode: Timer counts up to 0FFFFh"]
+    MC_2,
+    #[doc = "Up/down mode: Timer counts up to TAxCCR0 then down to 0000h"]
+    MC_3,
+}
+impl MCR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            MCR::MC_0 => 0,
+            MCR::MC_1 => 1,
+            MCR::MC_2 => 2,
+            MCR::MC_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> MCR {
+        match value {
+            0 => MCR::MC_0,
+            1 => MCR::MC_1,
+            2 => MCR::MC_2,
+            3 => MCR::MC_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `MC_0`"]
+    #[inline]
+    pub fn is_mc_0(&self) -> bool {
+        *self == MCR::MC_0
+    }
+    #[doc = "Checks if the value of the field is `MC_1`"]
+    #[inline]
+    pub fn is_mc_1(&self) -> bool {
+        *self == MCR::MC_1
+    }
+    #[doc = "Checks if the value of the field is `MC_2`"]
+    #[inline]
+    pub fn is_mc_2(&self) -> bool {
+        *self == MCR::MC_2
+    }
+    #[doc = "Checks if the value of the field is `MC_3`"]
+    #[inline]
+    pub fn is_mc_3(&self) -> bool {
+        *self == MCR::MC_3
+    }
+}
+#[doc = "Possible values of the field `ID`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IDR {
+    #[doc = "/1"]
+    ID_0,
+    #[doc = "/2"]
+    ID_1,
+    #[doc = "/4"]
+    ID_2,
+    #[doc = "/8"]
+    ID_3,
+}
+impl IDR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            IDR::ID_0 => 0,
+            IDR::ID_1 => 1,
+            IDR::ID_2 => 2,
+            IDR::ID_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> IDR {
+        match value {
+            0 => IDR::ID_0,
+            1 => IDR::ID_1,
+            2 => IDR::ID_2,
+            3 => IDR::ID_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `ID_0`"]
+    #[inline]
+    pub fn is_id_0(&self) -> bool {
+        *self == IDR::ID_0
+    }
+    #[doc = "Checks if the value of the field is `ID_1`"]
+    #[inline]
+    pub fn is_id_1(&self) -> bool {
+        *self == IDR::ID_1
+    }
+    #[doc = "Checks if the value of the field is `ID_2`"]
+    #[inline]
+    pub fn is_id_2(&self) -> bool {
+        *self == IDR::ID_2
+    }
+    #[doc = "Checks if the value of the field is `ID_3`"]
+    #[inline]
+    pub fn is_id_3(&self) -> bool {
+        *self == IDR::ID_3
+    }
+}
+#[doc = "Possible values of the field `TASSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TASSELR {
+    #[doc = "TAxCLK"]
+    TASSEL_0,
+    #[doc = "ACLK"]
+    TASSEL_1,
+    #[doc = "SMCLK"]
+    TASSEL_2,
+    #[doc = "INCLK"]
+    TASSEL_3,
+}
+impl TASSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            TASSELR::TASSEL_0 => 0,
+            TASSELR::TASSEL_1 => 1,
+            TASSELR::TASSEL_2 => 2,
+            TASSELR::TASSEL_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> TASSELR {
+        match value {
+            0 => TASSELR::TASSEL_0,
+            1 => TASSELR::TASSEL_1,
+            2 => TASSELR::TASSEL_2,
+            3 => TASSELR::TASSEL_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `TASSEL_0`"]
+    #[inline]
+    pub fn is_tassel_0(&self) -> bool {
+        *self == TASSELR::TASSEL_0
+    }
+    #[doc = "Checks if the value of the field is `TASSEL_1`"]
+    #[inline]
+    pub fn is_tassel_1(&self) -> bool {
+        *self == TASSELR::TASSEL_1
+    }
+    #[doc = "Checks if the value of the field is `TASSEL_2`"]
+    #[inline]
+    pub fn is_tassel_2(&self) -> bool {
+        *self == TASSELR::TASSEL_2
+    }
+    #[doc = "Checks if the value of the field is `TASSEL_3`"]
+    #[inline]
+    pub fn is_tassel_3(&self) -> bool {
+        *self == TASSELR::TASSEL_3
+    }
+}
+#[doc = "Values that can be written to the field `TAIFG`"]
+pub enum TAIFGW {
+    #[doc = "No interrupt pending"]
+    TAIFG_0,
+    #[doc = "Interrupt pending"]
+    TAIFG_1,
+}
+impl TAIFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TAIFGW::TAIFG_0 => false,
+            TAIFGW::TAIFG_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TAIFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TAIFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TAIFGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No interrupt pending"]
+    #[inline]
+    pub fn taifg_0(self) -> &'a mut W {
+        self.variant(TAIFGW::TAIFG_0)
+    }
+    #[doc = "Interrupt pending"]
+    #[inline]
+    pub fn taifg_1(self) -> &'a mut W {
+        self.variant(TAIFGW::TAIFG_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TAIE`"]
+pub enum TAIEW {
+    #[doc = "Interrupt disabled"]
+    TAIE_0,
+    #[doc = "Interrupt enabled"]
+    TAIE_1,
+}
+impl TAIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TAIEW::TAIE_0 => false,
+            TAIEW::TAIE_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TAIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TAIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TAIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Interrupt disabled"]
+    #[inline]
+    pub fn taie_0(self) -> &'a mut W {
+        self.variant(TAIEW::TAIE_0)
+    }
+    #[doc = "Interrupt enabled"]
+    #[inline]
+    pub fn taie_1(self) -> &'a mut W {
+        self.variant(TAIEW::TAIE_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TACLRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TACLRW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `MC`"]
+pub enum MCW {
+    #[doc = "Stop mode: Timer is halted"]
+    MC_0,
+    #[doc = "Up mode: Timer counts up to TAxCCR0"]
+    MC_1,
+    #[doc = "Continuous mode: Timer counts up to 0FFFFh"]
+    MC_2,
+    #[doc = "Up/down mode: Timer counts up to TAxCCR0 then down to 0000h"]
+    MC_3,
+}
+impl MCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            MCW::MC_0 => 0,
+            MCW::MC_1 => 1,
+            MCW::MC_2 => 2,
+            MCW::MC_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: MCW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Stop mode: Timer is halted"]
+    #[inline]
+    pub fn mc_0(self) -> &'a mut W {
+        self.variant(MCW::MC_0)
+    }
+    #[doc = "Up mode: Timer counts up to TAxCCR0"]
+    #[inline]
+    pub fn mc_1(self) -> &'a mut W {
+        self.variant(MCW::MC_1)
+    }
+    #[doc = "Continuous mode: Timer counts up to 0FFFFh"]
+    #[inline]
+    pub fn mc_2(self) -> &'a mut W {
+        self.variant(MCW::MC_2)
+    }
+    #[doc = "Up/down mode: Timer counts up to TAxCCR0 then down to 0000h"]
+    #[inline]
+    pub fn mc_3(self) -> &'a mut W {
+        self.variant(MCW::MC_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ID`"]
+pub enum IDW {
+    #[doc = "/1"]
+    ID_0,
+    #[doc = "/2"]
+    ID_1,
+    #[doc = "/4"]
+    ID_2,
+    #[doc = "/8"]
+    ID_3,
+}
+impl IDW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            IDW::ID_0 => 0,
+            IDW::ID_1 => 1,
+            IDW::ID_2 => 2,
+            IDW::ID_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _IDW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _IDW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: IDW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "/1"]
+    #[inline]
+    pub fn id_0(self) -> &'a mut W {
+        self.variant(IDW::ID_0)
+    }
+    #[doc = "/2"]
+    #[inline]
+    pub fn id_1(self) -> &'a mut W {
+        self.variant(IDW::ID_1)
+    }
+    #[doc = "/4"]
+    #[inline]
+    pub fn id_2(self) -> &'a mut W {
+        self.variant(IDW::ID_2)
+    }
+    #[doc = "/8"]
+    #[inline]
+    pub fn id_3(self) -> &'a mut W {
+        self.variant(IDW::ID_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TASSEL`"]
+pub enum TASSELW {
+    #[doc = "TAxCLK"]
+    TASSEL_0,
+    #[doc = "ACLK"]
+    TASSEL_1,
+    #[doc = "SMCLK"]
+    TASSEL_2,
+    #[doc = "INCLK"]
+    TASSEL_3,
+}
+impl TASSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            TASSELW::TASSEL_0 => 0,
+            TASSELW::TASSEL_1 => 1,
+            TASSELW::TASSEL_2 => 2,
+            TASSELW::TASSEL_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TASSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TASSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TASSELW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "TAxCLK"]
+    #[inline]
+    pub fn tassel_0(self) -> &'a mut W {
+        self.variant(TASSELW::TASSEL_0)
+    }
+    #[doc = "ACLK"]
+    #[inline]
+    pub fn tassel_1(self) -> &'a mut W {
+        self.variant(TASSELW::TASSEL_1)
+    }
+    #[doc = "SMCLK"]
+    #[inline]
+    pub fn tassel_2(self) -> &'a mut W {
+        self.variant(TASSELW::TASSEL_2)
+    }
+    #[doc = "INCLK"]
+    #[inline]
+    pub fn tassel_3(self) -> &'a mut W {
+        self.variant(TASSELW::TASSEL_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bit 0 - TimerA interrupt flag"]
+    #[inline]
+    pub fn taifg(&self) -> TAIFGR {
+        TAIFGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 1 - TimerA interrupt enable"]
+    #[inline]
+    pub fn taie(&self) -> TAIER {
+        TAIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bit 2 - TimerA clear"]
+    #[inline]
+    pub fn taclr(&self) -> TACLRR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        };
+        TACLRR { bits }
+    }
+    #[doc = "Bits 4:5 - Mode control"]
+    #[inline]
+    pub fn mc(&self) -> MCR {
+        MCR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bits 6:7 - Input divider"]
+    #[inline]
+    pub fn id(&self) -> IDR {
+        IDR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bits 8:9 - TimerA clock source select"]
+    #[inline]
+    pub fn tassel(&self) -> TASSELR {
+        TASSELR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - TimerA interrupt flag"]
+    #[inline]
+    pub fn taifg(&mut self) -> _TAIFGW {
+        _TAIFGW { w: self }
+    }
+    #[doc = "Bit 1 - TimerA interrupt enable"]
+    #[inline]
+    pub fn taie(&mut self) -> _TAIEW {
+        _TAIEW { w: self }
+    }
+    #[doc = "Bit 2 - TimerA clear"]
+    #[inline]
+    pub fn taclr(&mut self) -> _TACLRW {
+        _TACLRW { w: self }
+    }
+    #[doc = "Bits 4:5 - Mode control"]
+    #[inline]
+    pub fn mc(&mut self) -> _MCW {
+        _MCW { w: self }
+    }
+    #[doc = "Bits 6:7 - Input divider"]
+    #[inline]
+    pub fn id(&mut self) -> _IDW {
+        _IDW { w: self }
+    }
+    #[doc = "Bits 8:9 - TimerA clock source select"]
+    #[inline]
+    pub fn tassel(&mut self) -> _TASSELW {
+        _TASSELW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/timer_a3/tax_ex0.rs b/example-source/msp432p401r/src/timer_a3/tax_ex0.rs
new file mode 100644
index 0000000..cc9bd3f
--- /dev/null
+++ b/example-source/msp432p401r/src/timer_a3/tax_ex0.rs
@@ -0,0 +1,268 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::TAXEX0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `TAIDEX`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TAIDEXR {
+    #[doc = "Divide by 1"]
+    TAIDEX_0,
+    #[doc = "Divide by 2"]
+    TAIDEX_1,
+    #[doc = "Divide by 3"]
+    TAIDEX_2,
+    #[doc = "Divide by 4"]
+    TAIDEX_3,
+    #[doc = "Divide by 5"]
+    TAIDEX_4,
+    #[doc = "Divide by 6"]
+    TAIDEX_5,
+    #[doc = "Divide by 7"]
+    TAIDEX_6,
+    #[doc = "Divide by 8"]
+    TAIDEX_7,
+}
+impl TAIDEXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            TAIDEXR::TAIDEX_0 => 0,
+            TAIDEXR::TAIDEX_1 => 1,
+            TAIDEXR::TAIDEX_2 => 2,
+            TAIDEXR::TAIDEX_3 => 3,
+            TAIDEXR::TAIDEX_4 => 4,
+            TAIDEXR::TAIDEX_5 => 5,
+            TAIDEXR::TAIDEX_6 => 6,
+            TAIDEXR::TAIDEX_7 => 7,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> TAIDEXR {
+        match value {
+            0 => TAIDEXR::TAIDEX_0,
+            1 => TAIDEXR::TAIDEX_1,
+            2 => TAIDEXR::TAIDEX_2,
+            3 => TAIDEXR::TAIDEX_3,
+            4 => TAIDEXR::TAIDEX_4,
+            5 => TAIDEXR::TAIDEX_5,
+            6 => TAIDEXR::TAIDEX_6,
+            7 => TAIDEXR::TAIDEX_7,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_0`"]
+    #[inline]
+    pub fn is_taidex_0(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_0
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_1`"]
+    #[inline]
+    pub fn is_taidex_1(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_1
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_2`"]
+    #[inline]
+    pub fn is_taidex_2(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_2
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_3`"]
+    #[inline]
+    pub fn is_taidex_3(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_3
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_4`"]
+    #[inline]
+    pub fn is_taidex_4(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_4
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_5`"]
+    #[inline]
+    pub fn is_taidex_5(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_5
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_6`"]
+    #[inline]
+    pub fn is_taidex_6(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_6
+    }
+    #[doc = "Checks if the value of the field is `TAIDEX_7`"]
+    #[inline]
+    pub fn is_taidex_7(&self) -> bool {
+        *self == TAIDEXR::TAIDEX_7
+    }
+}
+#[doc = "Values that can be written to the field `TAIDEX`"]
+pub enum TAIDEXW {
+    #[doc = "Divide by 1"]
+    TAIDEX_0,
+    #[doc = "Divide by 2"]
+    TAIDEX_1,
+    #[doc = "Divide by 3"]
+    TAIDEX_2,
+    #[doc = "Divide by 4"]
+    TAIDEX_3,
+    #[doc = "Divide by 5"]
+    TAIDEX_4,
+    #[doc = "Divide by 6"]
+    TAIDEX_5,
+    #[doc = "Divide by 7"]
+    TAIDEX_6,
+    #[doc = "Divide by 8"]
+    TAIDEX_7,
+}
+impl TAIDEXW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            TAIDEXW::TAIDEX_0 => 0,
+            TAIDEXW::TAIDEX_1 => 1,
+            TAIDEXW::TAIDEX_2 => 2,
+            TAIDEXW::TAIDEX_3 => 3,
+            TAIDEXW::TAIDEX_4 => 4,
+            TAIDEXW::TAIDEX_5 => 5,
+            TAIDEXW::TAIDEX_6 => 6,
+            TAIDEXW::TAIDEX_7 => 7,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TAIDEXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TAIDEXW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TAIDEXW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Divide by 1"]
+    #[inline]
+    pub fn taidex_0(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_0)
+    }
+    #[doc = "Divide by 2"]
+    #[inline]
+    pub fn taidex_1(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_1)
+    }
+    #[doc = "Divide by 3"]
+    #[inline]
+    pub fn taidex_2(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_2)
+    }
+    #[doc = "Divide by 4"]
+    #[inline]
+    pub fn taidex_3(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_3)
+    }
+    #[doc = "Divide by 5"]
+    #[inline]
+    pub fn taidex_4(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_4)
+    }
+    #[doc = "Divide by 6"]
+    #[inline]
+    pub fn taidex_5(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_5)
+    }
+    #[doc = "Divide by 7"]
+    #[inline]
+    pub fn taidex_6(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_6)
+    }
+    #[doc = "Divide by 8"]
+    #[inline]
+    pub fn taidex_7(self) -> &'a mut W {
+        self.variant(TAIDEXW::TAIDEX_7)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:2 - Input divider expansion"]
+    #[inline]
+    pub fn taidex(&self) -> TAIDEXR {
+        TAIDEXR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:2 - Input divider expansion"]
+    #[inline]
+    pub fn taidex(&mut self) -> _TAIDEXW {
+        _TAIDEXW { w: self }
+    }
+}
diff --git a/example-source/msp432p401r/src/timer_a3/tax_iv.rs b/example-source/msp432p401r/src/timer_a3/tax_iv.rs
new file mode 100644
index 0000000..a83ed36
--- /dev/null
+++ b/example-source/msp432p401r/src/timer_a3/tax_iv.rs
@@ -0,0 +1,124 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::TAXIV {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `TAIV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TAIVR {
+    #[doc = "No interrupt pending"]
+    TAIV_0,
+    #[doc = "Interrupt Source: Capture/compare 1; Interrupt Flag: TAxCCR1 CCIFG; Interrupt Priority: Highest"]
+    TAIV_2,
+    #[doc = "Interrupt Source: Capture/compare 2; Interrupt Flag: TAxCCR2 CCIFG"]
+    TAIV_4,
+    #[doc = "Interrupt Source: Capture/compare 3; Interrupt Flag: TAxCCR3 CCIFG"]
+    TAIV_6,
+    #[doc = "Interrupt Source: Capture/compare 4; Interrupt Flag: TAxCCR4 CCIFG"]
+    TAIV_8,
+    #[doc = "Interrupt Source: Capture/compare 5; Interrupt Flag: TAxCCR5 CCIFG"]
+    TAIV_10,
+    #[doc = "Interrupt Source: Capture/compare 6; Interrupt Flag: TAxCCR6 CCIFG"]
+    TAIV_12,
+    #[doc = "Interrupt Source: Timer overflow; Interrupt Flag: TAxCTL TAIFG; Interrupt Priority: Lowest"]
+    TAIV_14,
+    #[doc = r" Reserved"]
+    _Reserved(u16),
+}
+impl TAIVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        match *self {
+            TAIVR::TAIV_0 => 0,
+            TAIVR::TAIV_2 => 2,
+            TAIVR::TAIV_4 => 4,
+            TAIVR::TAIV_6 => 6,
+            TAIVR::TAIV_8 => 8,
+            TAIVR::TAIV_10 => 10,
+            TAIVR::TAIV_12 => 12,
+            TAIVR::TAIV_14 => 14,
+            TAIVR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u16) -> TAIVR {
+        match value {
+            0 => TAIVR::TAIV_0,
+            2 => TAIVR::TAIV_2,
+            4 => TAIVR::TAIV_4,
+            6 => TAIVR::TAIV_6,
+            8 => TAIVR::TAIV_8,
+            10 => TAIVR::TAIV_10,
+            12 => TAIVR::TAIV_12,
+            14 => TAIVR::TAIV_14,
+            i => TAIVR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `TAIV_0`"]
+    #[inline]
+    pub fn is_taiv_0(&self) -> bool {
+        *self == TAIVR::TAIV_0
+    }
+    #[doc = "Checks if the value of the field is `TAIV_2`"]
+    #[inline]
+    pub fn is_taiv_2(&self) -> bool {
+        *self == TAIVR::TAIV_2
+    }
+    #[doc = "Checks if the value of the field is `TAIV_4`"]
+    #[inline]
+    pub fn is_taiv_4(&self) -> bool {
+        *self == TAIVR::TAIV_4
+    }
+    #[doc = "Checks if the value of the field is `TAIV_6`"]
+    #[inline]
+    pub fn is_taiv_6(&self) -> bool {
+        *self == TAIVR::TAIV_6
+    }
+    #[doc = "Checks if the value of the field is `TAIV_8`"]
+    #[inline]
+    pub fn is_taiv_8(&self) -> bool {
+        *self == TAIVR::TAIV_8
+    }
+    #[doc = "Checks if the value of the field is `TAIV_10`"]
+    #[inline]
+    pub fn is_taiv_10(&self) -> bool {
+        *self == TAIVR::TAIV_10
+    }
+    #[doc = "Checks if the value of the field is `TAIV_12`"]
+    #[inline]
+    pub fn is_taiv_12(&self) -> bool {
+        *self == TAIVR::TAIV_12
+    }
+    #[doc = "Checks if the value of the field is `TAIV_14`"]
+    #[inline]
+    pub fn is_taiv_14(&self) -> bool {
+        *self == TAIVR::TAIV_14
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - TimerA interrupt vector value"]
+    #[inline]
+    pub fn taiv(&self) -> TAIVR {
+        TAIVR::_from({
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u16
+        })
+    }
+}
diff --git a/example-source/msp432p401r/src/timer_a3/tax_r.rs b/example-source/msp432p401r/src/timer_a3/tax_r.rs
new file mode 100644
index 0000000..3542361
--- /dev/null
+++ b/example-source/msp432p401r/src/timer_a3/tax_r.rs
@@ -0,0 +1,64 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::TAXR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv.rs b/example-source/msp432p401r/src/tlv.rs
new file mode 100644
index 0000000..a1f3eb9
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv.rs
@@ -0,0 +1,668 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - TLV Checksum"]
+    pub tlv_checksum: TLV_CHECKSUM,
+    #[doc = "0x04 - Device Info Tag"]
+    pub device_info_tag: DEVICE_INFO_TAG,
+    #[doc = "0x08 - Device Info Length"]
+    pub device_info_len: DEVICE_INFO_LEN,
+    #[doc = "0x0c - Device ID"]
+    pub device_id: DEVICE_ID,
+    #[doc = "0x10 - HW Revision"]
+    pub hwrev: HWREV,
+    #[doc = "0x14 - Boot Code Revision"]
+    pub bcrev: BCREV,
+    #[doc = "0x18 - ROM Driver Library Revision"]
+    pub rom_drvlib_rev: ROM_DRVLIB_REV,
+    #[doc = "0x1c - Die Record Tag"]
+    pub die_rec_tag: DIE_REC_TAG,
+    #[doc = "0x20 - Die Record Length"]
+    pub die_rec_len: DIE_REC_LEN,
+    #[doc = "0x24 - Die X-Position"]
+    pub die_xpos: DIE_XPOS,
+    #[doc = "0x28 - Die Y-Position"]
+    pub die_ypos: DIE_YPOS,
+    #[doc = "0x2c - Wafer ID"]
+    pub wafer_id: WAFER_ID,
+    #[doc = "0x30 - Lot ID"]
+    pub lot_id: LOT_ID,
+    #[doc = "0x34 - Reserved"]
+    pub reserved0: RESERVED0,
+    #[doc = "0x38 - Reserved"]
+    pub reserved1: RESERVED1,
+    #[doc = "0x3c - Reserved"]
+    pub reserved2: RESERVED2,
+    #[doc = "0x40 - Test Results"]
+    pub test_results: TEST_RESULTS,
+    #[doc = "0x44 - Clock System Calibration Tag"]
+    pub cs_cal_tag: CS_CAL_TAG,
+    #[doc = "0x48 - Clock System Calibration Length"]
+    pub cs_cal_len: CS_CAL_LEN,
+    #[doc = "0x4c - DCO IR mode: Frequency calibration for DCORSEL 0 to 4"]
+    pub dcoir_fcal_rsel04: DCOIR_FCAL_RSEL04,
+    #[doc = "0x50 - DCO IR mode: Frequency calibration for DCORSEL 5"]
+    pub dcoir_fcal_rsel5: DCOIR_FCAL_RSEL5,
+    #[doc = "0x54 - Reserved"]
+    pub reserved3: RESERVED3,
+    #[doc = "0x58 - Reserved"]
+    pub reserved4: RESERVED4,
+    #[doc = "0x5c - Reserved"]
+    pub reserved5: RESERVED5,
+    #[doc = "0x60 - Reserved"]
+    pub reserved6: RESERVED6,
+    #[doc = "0x64 - DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4"]
+    pub dcoir_constk_rsel04: DCOIR_CONSTK_RSEL04,
+    #[doc = "0x68 - DCO IR mode: DCO Constant (K) for DCORSEL 5"]
+    pub dcoir_constk_rsel5: DCOIR_CONSTK_RSEL5,
+    #[doc = "0x6c - DCO ER mode: Frequency calibration for DCORSEL 0 to 4"]
+    pub dcoer_fcal_rsel04: DCOER_FCAL_RSEL04,
+    #[doc = "0x70 - DCO ER mode: Frequency calibration for DCORSEL 5"]
+    pub dcoer_fcal_rsel5: DCOER_FCAL_RSEL5,
+    #[doc = "0x74 - Reserved"]
+    pub reserved7: RESERVED7,
+    #[doc = "0x78 - Reserved"]
+    pub reserved8: RESERVED8,
+    #[doc = "0x7c - Reserved"]
+    pub reserved9: RESERVED9,
+    #[doc = "0x80 - Reserved"]
+    pub reserved10: RESERVED10,
+    #[doc = "0x84 - DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4"]
+    pub dcoer_constk_rsel04: DCOER_CONSTK_RSEL04,
+    #[doc = "0x88 - DCO ER mode: DCO Constant (K) for DCORSEL 5"]
+    pub dcoer_constk_rsel5: DCOER_CONSTK_RSEL5,
+    #[doc = "0x8c - ADC14 Calibration Tag"]
+    pub adc14_cal_tag: ADC14_CAL_TAG,
+    #[doc = "0x90 - ADC14 Calibration Length"]
+    pub adc14_cal_len: ADC14_CAL_LEN,
+    #[doc = "0x94 - ADC Gain Factor"]
+    pub adc_gain_factor: ADC_GAIN_FACTOR,
+    #[doc = "0x98 - ADC Offset"]
+    pub adc_offset: ADC_OFFSET,
+    #[doc = "0x9c - Reserved"]
+    pub reserved11: RESERVED11,
+    #[doc = "0xa0 - Reserved"]
+    pub reserved12: RESERVED12,
+    #[doc = "0xa4 - Reserved"]
+    pub reserved13: RESERVED13,
+    #[doc = "0xa8 - Reserved"]
+    pub reserved14: RESERVED14,
+    #[doc = "0xac - Reserved"]
+    pub reserved15: RESERVED15,
+    #[doc = "0xb0 - Reserved"]
+    pub reserved16: RESERVED16,
+    #[doc = "0xb4 - Reserved"]
+    pub reserved17: RESERVED17,
+    #[doc = "0xb8 - Reserved"]
+    pub reserved18: RESERVED18,
+    #[doc = "0xbc - Reserved"]
+    pub reserved19: RESERVED19,
+    #[doc = "0xc0 - Reserved"]
+    pub reserved20: RESERVED20,
+    #[doc = "0xc4 - Reserved"]
+    pub reserved21: RESERVED21,
+    #[doc = "0xc8 - Reserved"]
+    pub reserved22: RESERVED22,
+    #[doc = "0xcc - Reserved"]
+    pub reserved23: RESERVED23,
+    #[doc = "0xd0 - Reserved"]
+    pub reserved24: RESERVED24,
+    #[doc = "0xd4 - Reserved"]
+    pub reserved25: RESERVED25,
+    #[doc = "0xd8 - Reserved"]
+    pub reserved26: RESERVED26,
+    #[doc = "0xdc - ADC14 1.2V Reference Temp. Sensor 30C"]
+    pub adc14_ref1p2v_ts30c: ADC14_REF1P2V_TS30C,
+    #[doc = "0xe0 - ADC14 1.2V Reference Temp. Sensor 85C"]
+    pub adc14_ref1p2v_ts85c: ADC14_REF1P2V_TS85C,
+    #[doc = "0xe4 - ADC14 1.45V Reference Temp. Sensor 30C"]
+    pub adc14_ref1p45v_ts30c: ADC14_REF1P45V_TS30C,
+    #[doc = "0xe8 - ADC14 1.45V Reference Temp. Sensor 85C"]
+    pub adc14_ref1p45v_ts85c: ADC14_REF1P45V_TS85C,
+    #[doc = "0xec - ADC14 2.5V Reference Temp. Sensor 30C"]
+    pub adc14_ref2p5v_ts30c: ADC14_REF2P5V_TS30C,
+    #[doc = "0xf0 - ADC14 2.5V Reference Temp. Sensor 85C"]
+    pub adc14_ref2p5v_ts85c: ADC14_REF2P5V_TS85C,
+    #[doc = "0xf4 - REF Calibration Tag"]
+    pub ref_cal_tag: REF_CAL_TAG,
+    #[doc = "0xf8 - REF Calibration Length"]
+    pub ref_cal_len: REF_CAL_LEN,
+    #[doc = "0xfc - REF 1.2V Reference"]
+    pub ref_1p2v: REF_1P2V,
+    #[doc = "0x100 - REF 1.45V Reference"]
+    pub ref_1p45v: REF_1P45V,
+    #[doc = "0x104 - REF 2.5V Reference"]
+    pub ref_2p5v: REF_2P5V,
+    #[doc = "0x108 - Flash Info Tag"]
+    pub flash_info_tag: FLASH_INFO_TAG,
+    #[doc = "0x10c - Flash Info Length"]
+    pub flash_info_len: FLASH_INFO_LEN,
+    #[doc = "0x110 - Flash Maximum Programming Pulses"]
+    pub flash_max_prog_pulses: FLASH_MAX_PROG_PULSES,
+    #[doc = "0x114 - Flash Maximum Erase Pulses"]
+    pub flash_max_erase_pulses: FLASH_MAX_ERASE_PULSES,
+    #[doc = "0x118 - 128-bit Random Number Tag"]
+    pub random_num_tag: RANDOM_NUM_TAG,
+    #[doc = "0x11c - 128-bit Random Number Length"]
+    pub random_num_len: RANDOM_NUM_LEN,
+    #[doc = "0x120 - 32-bit Random Number 1"]
+    pub random_num_1: RANDOM_NUM_1,
+    #[doc = "0x124 - 32-bit Random Number 2"]
+    pub random_num_2: RANDOM_NUM_2,
+    #[doc = "0x128 - 32-bit Random Number 3"]
+    pub random_num_3: RANDOM_NUM_3,
+    #[doc = "0x12c - 32-bit Random Number 4"]
+    pub random_num_4: RANDOM_NUM_4,
+    #[doc = "0x130 - BSL Configuration Tag"]
+    pub bsl_cfg_tag: BSL_CFG_TAG,
+    #[doc = "0x134 - BSL Configuration Length"]
+    pub bsl_cfg_len: BSL_CFG_LEN,
+    #[doc = "0x138 - BSL Peripheral Interface Selection"]
+    pub bsl_periphif_sel: BSL_PERIPHIF_SEL,
+    #[doc = "0x13c - BSL Port Interface Configuration for UART"]
+    pub bsl_portif_cfg_uart: BSL_PORTIF_CFG_UART,
+    #[doc = "0x140 - BSL Port Interface Configuration for SPI"]
+    pub bsl_portif_cfg_spi: BSL_PORTIF_CFG_SPI,
+    #[doc = "0x144 - BSL Port Interface Configuration for I2C"]
+    pub bsl_portif_cfg_i2c: BSL_PORTIF_CFG_I2C,
+    #[doc = "0x148 - TLV End Word"]
+    pub tlv_end: TLV_END,
+}
+#[doc = "TLV Checksum"]
+pub struct TLV_CHECKSUM {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "TLV Checksum"]
+pub mod tlv_checksum;
+#[doc = "Device Info Tag"]
+pub struct DEVICE_INFO_TAG {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Device Info Tag"]
+pub mod device_info_tag;
+#[doc = "Device Info Length"]
+pub struct DEVICE_INFO_LEN {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Device Info Length"]
+pub mod device_info_len;
+#[doc = "Device ID"]
+pub struct DEVICE_ID {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Device ID"]
+pub mod device_id;
+#[doc = "HW Revision"]
+pub struct HWREV {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "HW Revision"]
+pub mod hwrev;
+#[doc = "Boot Code Revision"]
+pub struct BCREV {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Boot Code Revision"]
+pub mod bcrev;
+#[doc = "ROM Driver Library Revision"]
+pub struct ROM_DRVLIB_REV {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ROM Driver Library Revision"]
+pub mod rom_drvlib_rev;
+#[doc = "Die Record Tag"]
+pub struct DIE_REC_TAG {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Die Record Tag"]
+pub mod die_rec_tag;
+#[doc = "Die Record Length"]
+pub struct DIE_REC_LEN {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Die Record Length"]
+pub mod die_rec_len;
+#[doc = "Die X-Position"]
+pub struct DIE_XPOS {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Die X-Position"]
+pub mod die_xpos;
+#[doc = "Die Y-Position"]
+pub struct DIE_YPOS {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Die Y-Position"]
+pub mod die_ypos;
+#[doc = "Wafer ID"]
+pub struct WAFER_ID {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Wafer ID"]
+pub mod wafer_id;
+#[doc = "Lot ID"]
+pub struct LOT_ID {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Lot ID"]
+pub mod lot_id;
+#[doc = "Reserved"]
+pub struct RESERVED0 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reserved"]
+pub mod reserved0;
+#[doc = "Reserved"]
+pub struct RESERVED1 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reserved"]
+pub mod reserved1;
+#[doc = "Reserved"]
+pub struct RESERVED2 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reserved"]
+pub mod reserved2;
+#[doc = "Test Results"]
+pub struct TEST_RESULTS {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Test Results"]
+pub mod test_results;
+#[doc = "Clock System Calibration Tag"]
+pub struct CS_CAL_TAG {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Clock System Calibration Tag"]
+pub mod cs_cal_tag;
+#[doc = "Clock System Calibration Length"]
+pub struct CS_CAL_LEN {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Clock System Calibration Length"]
+pub mod cs_cal_len;
+#[doc = "DCO IR mode: Frequency calibration for DCORSEL 0 to 4"]
+pub struct DCOIR_FCAL_RSEL04 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "DCO IR mode: Frequency calibration for DCORSEL 0 to 4"]
+pub mod dcoir_fcal_rsel04;
+#[doc = "DCO IR mode: Frequency calibration for DCORSEL 5"]
+pub struct DCOIR_FCAL_RSEL5 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "DCO IR mode: Frequency calibration for DCORSEL 5"]
+pub mod dcoir_fcal_rsel5;
+#[doc = "Reserved"]
+pub struct RESERVED3 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reserved"]
+pub mod reserved3;
+#[doc = "Reserved"]
+pub struct RESERVED4 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reserved"]
+pub mod reserved4;
+#[doc = "Reserved"]
+pub struct RESERVED5 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reserved"]
+pub mod reserved5;
+#[doc = "Reserved"]
+pub struct RESERVED6 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reserved"]
+pub mod reserved6;
+#[doc = "DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4"]
+pub struct DCOIR_CONSTK_RSEL04 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4"]
+pub mod dcoir_constk_rsel04;
+#[doc = "DCO IR mode: DCO Constant (K) for DCORSEL 5"]
+pub struct DCOIR_CONSTK_RSEL5 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "DCO IR mode: DCO Constant (K) for DCORSEL 5"]
+pub mod dcoir_constk_rsel5;
+#[doc = "DCO ER mode: Frequency calibration for DCORSEL 0 to 4"]
+pub struct DCOER_FCAL_RSEL04 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "DCO ER mode: Frequency calibration for DCORSEL 0 to 4"]
+pub mod dcoer_fcal_rsel04;
+#[doc = "DCO ER mode: Frequency calibration for DCORSEL 5"]
+pub struct DCOER_FCAL_RSEL5 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "DCO ER mode: Frequency calibration for DCORSEL 5"]
+pub mod dcoer_fcal_rsel5;
+#[doc = "Reserved"]
+pub struct RESERVED7 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reserved"]
+pub mod reserved7;
+#[doc = "Reserved"]
+pub struct RESERVED8 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reserved"]
+pub mod reserved8;
+#[doc = "Reserved"]
+pub struct RESERVED9 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reserved"]
+pub mod reserved9;
+#[doc = "Reserved"]
+pub struct RESERVED10 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reserved"]
+pub mod reserved10;
+#[doc = "DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4"]
+pub struct DCOER_CONSTK_RSEL04 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4"]
+pub mod dcoer_constk_rsel04;
+#[doc = "DCO ER mode: DCO Constant (K) for DCORSEL 5"]
+pub struct DCOER_CONSTK_RSEL5 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "DCO ER mode: DCO Constant (K) for DCORSEL 5"]
+pub mod dcoer_constk_rsel5;
+#[doc = "ADC14 Calibration Tag"]
+pub struct ADC14_CAL_TAG {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC14 Calibration Tag"]
+pub mod adc14_cal_tag;
+#[doc = "ADC14 Calibration Length"]
+pub struct ADC14_CAL_LEN {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC14 Calibration Length"]
+pub mod adc14_cal_len;
+#[doc = "ADC Gain Factor"]
+pub struct ADC_GAIN_FACTOR {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Gain Factor"]
+pub mod adc_gain_factor;
+#[doc = "ADC Offset"]
+pub struct ADC_OFFSET {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Offset"]
+pub mod adc_offset;
+#[doc = "Reserved"]
+pub struct RESERVED11 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reserved"]
+pub mod reserved11;
+#[doc = "Reserved"]
+pub struct RESERVED12 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reserved"]
+pub mod reserved12;
+#[doc = "Reserved"]
+pub struct RESERVED13 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reserved"]
+pub mod reserved13;
+#[doc = "Reserved"]
+pub struct RESERVED14 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reserved"]
+pub mod reserved14;
+#[doc = "Reserved"]
+pub struct RESERVED15 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reserved"]
+pub mod reserved15;
+#[doc = "Reserved"]
+pub struct RESERVED16 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reserved"]
+pub mod reserved16;
+#[doc = "Reserved"]
+pub struct RESERVED17 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reserved"]
+pub mod reserved17;
+#[doc = "Reserved"]
+pub struct RESERVED18 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reserved"]
+pub mod reserved18;
+#[doc = "Reserved"]
+pub struct RESERVED19 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reserved"]
+pub mod reserved19;
+#[doc = "Reserved"]
+pub struct RESERVED20 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reserved"]
+pub mod reserved20;
+#[doc = "Reserved"]
+pub struct RESERVED21 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reserved"]
+pub mod reserved21;
+#[doc = "Reserved"]
+pub struct RESERVED22 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reserved"]
+pub mod reserved22;
+#[doc = "Reserved"]
+pub struct RESERVED23 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reserved"]
+pub mod reserved23;
+#[doc = "Reserved"]
+pub struct RESERVED24 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reserved"]
+pub mod reserved24;
+#[doc = "Reserved"]
+pub struct RESERVED25 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reserved"]
+pub mod reserved25;
+#[doc = "Reserved"]
+pub struct RESERVED26 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Reserved"]
+pub mod reserved26;
+#[doc = "ADC14 1.2V Reference Temp. Sensor 30C"]
+pub struct ADC14_REF1P2V_TS30C {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC14 1.2V Reference Temp. Sensor 30C"]
+pub mod adc14_ref1p2v_ts30c;
+#[doc = "ADC14 1.2V Reference Temp. Sensor 85C"]
+pub struct ADC14_REF1P2V_TS85C {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC14 1.2V Reference Temp. Sensor 85C"]
+pub mod adc14_ref1p2v_ts85c;
+#[doc = "ADC14 1.45V Reference Temp. Sensor 30C"]
+pub struct ADC14_REF1P45V_TS30C {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC14 1.45V Reference Temp. Sensor 30C"]
+pub mod adc14_ref1p45v_ts30c;
+#[doc = "ADC14 1.45V Reference Temp. Sensor 85C"]
+pub struct ADC14_REF1P45V_TS85C {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC14 1.45V Reference Temp. Sensor 85C"]
+pub mod adc14_ref1p45v_ts85c;
+#[doc = "ADC14 2.5V Reference Temp. Sensor 30C"]
+pub struct ADC14_REF2P5V_TS30C {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC14 2.5V Reference Temp. Sensor 30C"]
+pub mod adc14_ref2p5v_ts30c;
+#[doc = "ADC14 2.5V Reference Temp. Sensor 85C"]
+pub struct ADC14_REF2P5V_TS85C {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC14 2.5V Reference Temp. Sensor 85C"]
+pub mod adc14_ref2p5v_ts85c;
+#[doc = "REF Calibration Tag"]
+pub struct REF_CAL_TAG {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "REF Calibration Tag"]
+pub mod ref_cal_tag;
+#[doc = "REF Calibration Length"]
+pub struct REF_CAL_LEN {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "REF Calibration Length"]
+pub mod ref_cal_len;
+#[doc = "REF 1.2V Reference"]
+pub struct REF_1P2V {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "REF 1.2V Reference"]
+pub mod ref_1p2v;
+#[doc = "REF 1.45V Reference"]
+pub struct REF_1P45V {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "REF 1.45V Reference"]
+pub mod ref_1p45v;
+#[doc = "REF 2.5V Reference"]
+pub struct REF_2P5V {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "REF 2.5V Reference"]
+pub mod ref_2p5v;
+#[doc = "Flash Info Tag"]
+pub struct FLASH_INFO_TAG {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Flash Info Tag"]
+pub mod flash_info_tag;
+#[doc = "Flash Info Length"]
+pub struct FLASH_INFO_LEN {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Flash Info Length"]
+pub mod flash_info_len;
+#[doc = "Flash Maximum Programming Pulses"]
+pub struct FLASH_MAX_PROG_PULSES {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Flash Maximum Programming Pulses"]
+pub mod flash_max_prog_pulses;
+#[doc = "Flash Maximum Erase Pulses"]
+pub struct FLASH_MAX_ERASE_PULSES {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Flash Maximum Erase Pulses"]
+pub mod flash_max_erase_pulses;
+#[doc = "128-bit Random Number Tag"]
+pub struct RANDOM_NUM_TAG {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "128-bit Random Number Tag"]
+pub mod random_num_tag;
+#[doc = "128-bit Random Number Length"]
+pub struct RANDOM_NUM_LEN {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "128-bit Random Number Length"]
+pub mod random_num_len;
+#[doc = "32-bit Random Number 1"]
+pub struct RANDOM_NUM_1 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "32-bit Random Number 1"]
+pub mod random_num_1;
+#[doc = "32-bit Random Number 2"]
+pub struct RANDOM_NUM_2 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "32-bit Random Number 2"]
+pub mod random_num_2;
+#[doc = "32-bit Random Number 3"]
+pub struct RANDOM_NUM_3 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "32-bit Random Number 3"]
+pub mod random_num_3;
+#[doc = "32-bit Random Number 4"]
+pub struct RANDOM_NUM_4 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "32-bit Random Number 4"]
+pub mod random_num_4;
+#[doc = "BSL Configuration Tag"]
+pub struct BSL_CFG_TAG {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "BSL Configuration Tag"]
+pub mod bsl_cfg_tag;
+#[doc = "BSL Configuration Length"]
+pub struct BSL_CFG_LEN {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "BSL Configuration Length"]
+pub mod bsl_cfg_len;
+#[doc = "BSL Peripheral Interface Selection"]
+pub struct BSL_PERIPHIF_SEL {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "BSL Peripheral Interface Selection"]
+pub mod bsl_periphif_sel;
+#[doc = "BSL Port Interface Configuration for UART"]
+pub struct BSL_PORTIF_CFG_UART {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "BSL Port Interface Configuration for UART"]
+pub mod bsl_portif_cfg_uart;
+#[doc = "BSL Port Interface Configuration for SPI"]
+pub struct BSL_PORTIF_CFG_SPI {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "BSL Port Interface Configuration for SPI"]
+pub mod bsl_portif_cfg_spi;
+#[doc = "BSL Port Interface Configuration for I2C"]
+pub struct BSL_PORTIF_CFG_I2C {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "BSL Port Interface Configuration for I2C"]
+pub mod bsl_portif_cfg_i2c;
+#[doc = "TLV End Word"]
+pub struct TLV_END {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "TLV End Word"]
+pub mod tlv_end;
diff --git a/example-source/msp432p401r/src/tlv/adc14_cal_len.rs b/example-source/msp432p401r/src/tlv/adc14_cal_len.rs
new file mode 100644
index 0000000..c8c3ef0
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/adc14_cal_len.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::ADC14_CAL_LEN {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/adc14_cal_tag.rs b/example-source/msp432p401r/src/tlv/adc14_cal_tag.rs
new file mode 100644
index 0000000..8497d1b
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/adc14_cal_tag.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::ADC14_CAL_TAG {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/adc14_ref1p2v_ts30c.rs b/example-source/msp432p401r/src/tlv/adc14_ref1p2v_ts30c.rs
new file mode 100644
index 0000000..9d334d2
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/adc14_ref1p2v_ts30c.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::ADC14_REF1P2V_TS30C {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/adc14_ref1p2v_ts85c.rs b/example-source/msp432p401r/src/tlv/adc14_ref1p2v_ts85c.rs
new file mode 100644
index 0000000..5a546cb
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/adc14_ref1p2v_ts85c.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::ADC14_REF1P2V_TS85C {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/adc14_ref1p45v_ts30c.rs b/example-source/msp432p401r/src/tlv/adc14_ref1p45v_ts30c.rs
new file mode 100644
index 0000000..835165b
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/adc14_ref1p45v_ts30c.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::ADC14_REF1P45V_TS30C {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/adc14_ref1p45v_ts85c.rs b/example-source/msp432p401r/src/tlv/adc14_ref1p45v_ts85c.rs
new file mode 100644
index 0000000..604e23f
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/adc14_ref1p45v_ts85c.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::ADC14_REF1P45V_TS85C {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/adc14_ref2p5v_ts30c.rs b/example-source/msp432p401r/src/tlv/adc14_ref2p5v_ts30c.rs
new file mode 100644
index 0000000..7cc847c
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/adc14_ref2p5v_ts30c.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::ADC14_REF2P5V_TS30C {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/adc14_ref2p5v_ts85c.rs b/example-source/msp432p401r/src/tlv/adc14_ref2p5v_ts85c.rs
new file mode 100644
index 0000000..4dc5ec8
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/adc14_ref2p5v_ts85c.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::ADC14_REF2P5V_TS85C {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/adc_gain_factor.rs b/example-source/msp432p401r/src/tlv/adc_gain_factor.rs
new file mode 100644
index 0000000..094376e
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/adc_gain_factor.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::ADC_GAIN_FACTOR {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/adc_offset.rs b/example-source/msp432p401r/src/tlv/adc_offset.rs
new file mode 100644
index 0000000..22ffb01
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/adc_offset.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::ADC_OFFSET {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/bcrev.rs b/example-source/msp432p401r/src/tlv/bcrev.rs
new file mode 100644
index 0000000..47eab18
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/bcrev.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::BCREV {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/bsl_cfg_len.rs b/example-source/msp432p401r/src/tlv/bsl_cfg_len.rs
new file mode 100644
index 0000000..2cc16ce
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/bsl_cfg_len.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::BSL_CFG_LEN {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/bsl_cfg_tag.rs b/example-source/msp432p401r/src/tlv/bsl_cfg_tag.rs
new file mode 100644
index 0000000..3cd459d
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/bsl_cfg_tag.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::BSL_CFG_TAG {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/bsl_periphif_sel.rs b/example-source/msp432p401r/src/tlv/bsl_periphif_sel.rs
new file mode 100644
index 0000000..a0e01b9
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/bsl_periphif_sel.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::BSL_PERIPHIF_SEL {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/bsl_portif_cfg_i2c.rs b/example-source/msp432p401r/src/tlv/bsl_portif_cfg_i2c.rs
new file mode 100644
index 0000000..d009f10
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/bsl_portif_cfg_i2c.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::BSL_PORTIF_CFG_I2C {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/bsl_portif_cfg_spi.rs b/example-source/msp432p401r/src/tlv/bsl_portif_cfg_spi.rs
new file mode 100644
index 0000000..c7e0ac1
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/bsl_portif_cfg_spi.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::BSL_PORTIF_CFG_SPI {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/bsl_portif_cfg_uart.rs b/example-source/msp432p401r/src/tlv/bsl_portif_cfg_uart.rs
new file mode 100644
index 0000000..2ac839a
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/bsl_portif_cfg_uart.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::BSL_PORTIF_CFG_UART {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/cs_cal_len.rs b/example-source/msp432p401r/src/tlv/cs_cal_len.rs
new file mode 100644
index 0000000..30e48c8
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/cs_cal_len.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::CS_CAL_LEN {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/cs_cal_tag.rs b/example-source/msp432p401r/src/tlv/cs_cal_tag.rs
new file mode 100644
index 0000000..e3eacd9
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/cs_cal_tag.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::CS_CAL_TAG {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/dcoer_constk_rsel04.rs b/example-source/msp432p401r/src/tlv/dcoer_constk_rsel04.rs
new file mode 100644
index 0000000..6d4e2d2
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/dcoer_constk_rsel04.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::DCOER_CONSTK_RSEL04 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/dcoer_constk_rsel5.rs b/example-source/msp432p401r/src/tlv/dcoer_constk_rsel5.rs
new file mode 100644
index 0000000..33dbef0
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/dcoer_constk_rsel5.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::DCOER_CONSTK_RSEL5 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/dcoer_fcal_rsel04.rs b/example-source/msp432p401r/src/tlv/dcoer_fcal_rsel04.rs
new file mode 100644
index 0000000..2f38e14
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/dcoer_fcal_rsel04.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::DCOER_FCAL_RSEL04 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/dcoer_fcal_rsel5.rs b/example-source/msp432p401r/src/tlv/dcoer_fcal_rsel5.rs
new file mode 100644
index 0000000..da77734
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/dcoer_fcal_rsel5.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::DCOER_FCAL_RSEL5 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/dcoir_constk_rsel04.rs b/example-source/msp432p401r/src/tlv/dcoir_constk_rsel04.rs
new file mode 100644
index 0000000..b90e84c
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/dcoir_constk_rsel04.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::DCOIR_CONSTK_RSEL04 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/dcoir_constk_rsel5.rs b/example-source/msp432p401r/src/tlv/dcoir_constk_rsel5.rs
new file mode 100644
index 0000000..2cf5cd3
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/dcoir_constk_rsel5.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::DCOIR_CONSTK_RSEL5 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/dcoir_fcal_rsel04.rs b/example-source/msp432p401r/src/tlv/dcoir_fcal_rsel04.rs
new file mode 100644
index 0000000..fc9dd06
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/dcoir_fcal_rsel04.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::DCOIR_FCAL_RSEL04 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/dcoir_fcal_rsel5.rs b/example-source/msp432p401r/src/tlv/dcoir_fcal_rsel5.rs
new file mode 100644
index 0000000..28f3c60
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/dcoir_fcal_rsel5.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::DCOIR_FCAL_RSEL5 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/device_id.rs b/example-source/msp432p401r/src/tlv/device_id.rs
new file mode 100644
index 0000000..55ba4b2
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/device_id.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::DEVICE_ID {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/device_info_len.rs b/example-source/msp432p401r/src/tlv/device_info_len.rs
new file mode 100644
index 0000000..4b14dfa
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/device_info_len.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::DEVICE_INFO_LEN {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/device_info_tag.rs b/example-source/msp432p401r/src/tlv/device_info_tag.rs
new file mode 100644
index 0000000..c049922
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/device_info_tag.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::DEVICE_INFO_TAG {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/die_rec_len.rs b/example-source/msp432p401r/src/tlv/die_rec_len.rs
new file mode 100644
index 0000000..c826ae7
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/die_rec_len.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::DIE_REC_LEN {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/die_rec_tag.rs b/example-source/msp432p401r/src/tlv/die_rec_tag.rs
new file mode 100644
index 0000000..9169b99
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/die_rec_tag.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::DIE_REC_TAG {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/die_xpos.rs b/example-source/msp432p401r/src/tlv/die_xpos.rs
new file mode 100644
index 0000000..b9bd8dd
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/die_xpos.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::DIE_XPOS {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/die_ypos.rs b/example-source/msp432p401r/src/tlv/die_ypos.rs
new file mode 100644
index 0000000..aa95fa5
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/die_ypos.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::DIE_YPOS {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/flash_info_len.rs b/example-source/msp432p401r/src/tlv/flash_info_len.rs
new file mode 100644
index 0000000..d58eceb
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/flash_info_len.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::FLASH_INFO_LEN {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/flash_info_tag.rs b/example-source/msp432p401r/src/tlv/flash_info_tag.rs
new file mode 100644
index 0000000..32da1f2
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/flash_info_tag.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::FLASH_INFO_TAG {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/flash_max_erase_pulses.rs b/example-source/msp432p401r/src/tlv/flash_max_erase_pulses.rs
new file mode 100644
index 0000000..62f22e2
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/flash_max_erase_pulses.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::FLASH_MAX_ERASE_PULSES {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/flash_max_prog_pulses.rs b/example-source/msp432p401r/src/tlv/flash_max_prog_pulses.rs
new file mode 100644
index 0000000..2f4c528
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/flash_max_prog_pulses.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::FLASH_MAX_PROG_PULSES {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/hwrev.rs b/example-source/msp432p401r/src/tlv/hwrev.rs
new file mode 100644
index 0000000..b64713f
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/hwrev.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::HWREV {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/lot_id.rs b/example-source/msp432p401r/src/tlv/lot_id.rs
new file mode 100644
index 0000000..2d655e5
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/lot_id.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::LOT_ID {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/random_num_1.rs b/example-source/msp432p401r/src/tlv/random_num_1.rs
new file mode 100644
index 0000000..b4c5724
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/random_num_1.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RANDOM_NUM_1 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/random_num_2.rs b/example-source/msp432p401r/src/tlv/random_num_2.rs
new file mode 100644
index 0000000..6ee8f4a
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/random_num_2.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RANDOM_NUM_2 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/random_num_3.rs b/example-source/msp432p401r/src/tlv/random_num_3.rs
new file mode 100644
index 0000000..384bbf9
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/random_num_3.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RANDOM_NUM_3 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/random_num_4.rs b/example-source/msp432p401r/src/tlv/random_num_4.rs
new file mode 100644
index 0000000..c29e701
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/random_num_4.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RANDOM_NUM_4 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/random_num_len.rs b/example-source/msp432p401r/src/tlv/random_num_len.rs
new file mode 100644
index 0000000..4a87534
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/random_num_len.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RANDOM_NUM_LEN {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/random_num_tag.rs b/example-source/msp432p401r/src/tlv/random_num_tag.rs
new file mode 100644
index 0000000..8d50b8a
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/random_num_tag.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RANDOM_NUM_TAG {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/ref_1p2v.rs b/example-source/msp432p401r/src/tlv/ref_1p2v.rs
new file mode 100644
index 0000000..a983b41
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/ref_1p2v.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::REF_1P2V {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/ref_1p45v.rs b/example-source/msp432p401r/src/tlv/ref_1p45v.rs
new file mode 100644
index 0000000..12919f5
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/ref_1p45v.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::REF_1P45V {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/ref_2p5v.rs b/example-source/msp432p401r/src/tlv/ref_2p5v.rs
new file mode 100644
index 0000000..ee1052f
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/ref_2p5v.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::REF_2P5V {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/ref_cal_len.rs b/example-source/msp432p401r/src/tlv/ref_cal_len.rs
new file mode 100644
index 0000000..f61b14a
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/ref_cal_len.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::REF_CAL_LEN {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/ref_cal_tag.rs b/example-source/msp432p401r/src/tlv/ref_cal_tag.rs
new file mode 100644
index 0000000..85cd50b
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/ref_cal_tag.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::REF_CAL_TAG {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/reserved0.rs b/example-source/msp432p401r/src/tlv/reserved0.rs
new file mode 100644
index 0000000..768156c
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/reserved0.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RESERVED0 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/reserved1.rs b/example-source/msp432p401r/src/tlv/reserved1.rs
new file mode 100644
index 0000000..e393097
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/reserved1.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RESERVED1 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/reserved10.rs b/example-source/msp432p401r/src/tlv/reserved10.rs
new file mode 100644
index 0000000..ab2c36c
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/reserved10.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RESERVED10 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/reserved11.rs b/example-source/msp432p401r/src/tlv/reserved11.rs
new file mode 100644
index 0000000..c4eb1e5
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/reserved11.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RESERVED11 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/reserved12.rs b/example-source/msp432p401r/src/tlv/reserved12.rs
new file mode 100644
index 0000000..049b9e7
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/reserved12.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RESERVED12 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/reserved13.rs b/example-source/msp432p401r/src/tlv/reserved13.rs
new file mode 100644
index 0000000..3ffe51a
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/reserved13.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RESERVED13 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/reserved14.rs b/example-source/msp432p401r/src/tlv/reserved14.rs
new file mode 100644
index 0000000..4b9052a
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/reserved14.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RESERVED14 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/reserved15.rs b/example-source/msp432p401r/src/tlv/reserved15.rs
new file mode 100644
index 0000000..1a25873
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/reserved15.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RESERVED15 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/reserved16.rs b/example-source/msp432p401r/src/tlv/reserved16.rs
new file mode 100644
index 0000000..73a9e47
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/reserved16.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RESERVED16 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/reserved17.rs b/example-source/msp432p401r/src/tlv/reserved17.rs
new file mode 100644
index 0000000..489b5e1
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/reserved17.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RESERVED17 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/reserved18.rs b/example-source/msp432p401r/src/tlv/reserved18.rs
new file mode 100644
index 0000000..1c3edfc
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/reserved18.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RESERVED18 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/reserved19.rs b/example-source/msp432p401r/src/tlv/reserved19.rs
new file mode 100644
index 0000000..511ac27
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/reserved19.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RESERVED19 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/reserved2.rs b/example-source/msp432p401r/src/tlv/reserved2.rs
new file mode 100644
index 0000000..f9fb14c
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/reserved2.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RESERVED2 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/reserved20.rs b/example-source/msp432p401r/src/tlv/reserved20.rs
new file mode 100644
index 0000000..4d3e501
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/reserved20.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RESERVED20 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/reserved21.rs b/example-source/msp432p401r/src/tlv/reserved21.rs
new file mode 100644
index 0000000..3954a8a
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/reserved21.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RESERVED21 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/reserved22.rs b/example-source/msp432p401r/src/tlv/reserved22.rs
new file mode 100644
index 0000000..075d29d
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/reserved22.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RESERVED22 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/reserved23.rs b/example-source/msp432p401r/src/tlv/reserved23.rs
new file mode 100644
index 0000000..fc3cdd3
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/reserved23.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RESERVED23 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/reserved24.rs b/example-source/msp432p401r/src/tlv/reserved24.rs
new file mode 100644
index 0000000..25efd61
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/reserved24.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RESERVED24 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/reserved25.rs b/example-source/msp432p401r/src/tlv/reserved25.rs
new file mode 100644
index 0000000..ff821b2
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/reserved25.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RESERVED25 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/reserved26.rs b/example-source/msp432p401r/src/tlv/reserved26.rs
new file mode 100644
index 0000000..2f04bb7
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/reserved26.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RESERVED26 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/reserved3.rs b/example-source/msp432p401r/src/tlv/reserved3.rs
new file mode 100644
index 0000000..8e77920
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/reserved3.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RESERVED3 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/reserved4.rs b/example-source/msp432p401r/src/tlv/reserved4.rs
new file mode 100644
index 0000000..46f3f8a
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/reserved4.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RESERVED4 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/reserved5.rs b/example-source/msp432p401r/src/tlv/reserved5.rs
new file mode 100644
index 0000000..936b7b7
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/reserved5.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RESERVED5 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/reserved6.rs b/example-source/msp432p401r/src/tlv/reserved6.rs
new file mode 100644
index 0000000..9769fe5
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/reserved6.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RESERVED6 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/reserved7.rs b/example-source/msp432p401r/src/tlv/reserved7.rs
new file mode 100644
index 0000000..b0466af
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/reserved7.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RESERVED7 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/reserved8.rs b/example-source/msp432p401r/src/tlv/reserved8.rs
new file mode 100644
index 0000000..dde9b49
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/reserved8.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RESERVED8 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/reserved9.rs b/example-source/msp432p401r/src/tlv/reserved9.rs
new file mode 100644
index 0000000..95a0579
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/reserved9.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::RESERVED9 {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/rom_drvlib_rev.rs b/example-source/msp432p401r/src/tlv/rom_drvlib_rev.rs
new file mode 100644
index 0000000..06ddf50
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/rom_drvlib_rev.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::ROM_DRVLIB_REV {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/test_results.rs b/example-source/msp432p401r/src/tlv/test_results.rs
new file mode 100644
index 0000000..ce675c6
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/test_results.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::TEST_RESULTS {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/tlv_checksum.rs b/example-source/msp432p401r/src/tlv/tlv_checksum.rs
new file mode 100644
index 0000000..17addf6
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/tlv_checksum.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::TLV_CHECKSUM {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/tlv_end.rs b/example-source/msp432p401r/src/tlv/tlv_end.rs
new file mode 100644
index 0000000..e6ef1f5
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/tlv_end.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::TLV_END {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/tlv/wafer_id.rs b/example-source/msp432p401r/src/tlv/wafer_id.rs
new file mode 100644
index 0000000..f2bd9b9
--- /dev/null
+++ b/example-source/msp432p401r/src/tlv/wafer_id.rs
@@ -0,0 +1,20 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::WAFER_ID {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
diff --git a/example-source/msp432p401r/src/wdt_a.rs b/example-source/msp432p401r/src/wdt_a.rs
new file mode 100644
index 0000000..f34295a
--- /dev/null
+++ b/example-source/msp432p401r/src/wdt_a.rs
@@ -0,0 +1,13 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    _reserved0: [u8; 12usize],
+    #[doc = "0x0c - Watchdog Timer Control Register"]
+    pub wdtctl: WDTCTL,
+}
+#[doc = "Watchdog Timer Control Register"]
+pub struct WDTCTL {
+    register: ::vcell::VolatileCell<u16>,
+}
+#[doc = "Watchdog Timer Control Register"]
+pub mod wdtctl;
diff --git a/example-source/msp432p401r/src/wdt_a/wdtctl.rs b/example-source/msp432p401r/src/wdt_a/wdtctl.rs
new file mode 100644
index 0000000..8035a0a
--- /dev/null
+++ b/example-source/msp432p401r/src/wdt_a/wdtctl.rs
@@ -0,0 +1,746 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u16,
+}
+impl super::WDTCTL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `WDTIS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WDTISR {
+    #[doc = "Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz)"]
+    WDTIS_0,
+    #[doc = "Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz)"]
+    WDTIS_1,
+    #[doc = "Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz)"]
+    WDTIS_2,
+    #[doc = "Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz)"]
+    WDTIS_3,
+    #[doc = "Watchdog clock source /(2^(15)) (1 s at 32.768 kHz)"]
+    WDTIS_4,
+    #[doc = "Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz)"]
+    WDTIS_5,
+    #[doc = "Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz)"]
+    WDTIS_6,
+    #[doc = "Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz)"]
+    WDTIS_7,
+}
+impl WDTISR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            WDTISR::WDTIS_0 => 0,
+            WDTISR::WDTIS_1 => 1,
+            WDTISR::WDTIS_2 => 2,
+            WDTISR::WDTIS_3 => 3,
+            WDTISR::WDTIS_4 => 4,
+            WDTISR::WDTIS_5 => 5,
+            WDTISR::WDTIS_6 => 6,
+            WDTISR::WDTIS_7 => 7,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> WDTISR {
+        match value {
+            0 => WDTISR::WDTIS_0,
+            1 => WDTISR::WDTIS_1,
+            2 => WDTISR::WDTIS_2,
+            3 => WDTISR::WDTIS_3,
+            4 => WDTISR::WDTIS_4,
+            5 => WDTISR::WDTIS_5,
+            6 => WDTISR::WDTIS_6,
+            7 => WDTISR::WDTIS_7,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `WDTIS_0`"]
+    #[inline]
+    pub fn is_wdtis_0(&self) -> bool {
+        *self == WDTISR::WDTIS_0
+    }
+    #[doc = "Checks if the value of the field is `WDTIS_1`"]
+    #[inline]
+    pub fn is_wdtis_1(&self) -> bool {
+        *self == WDTISR::WDTIS_1
+    }
+    #[doc = "Checks if the value of the field is `WDTIS_2`"]
+    #[inline]
+    pub fn is_wdtis_2(&self) -> bool {
+        *self == WDTISR::WDTIS_2
+    }
+    #[doc = "Checks if the value of the field is `WDTIS_3`"]
+    #[inline]
+    pub fn is_wdtis_3(&self) -> bool {
+        *self == WDTISR::WDTIS_3
+    }
+    #[doc = "Checks if the value of the field is `WDTIS_4`"]
+    #[inline]
+    pub fn is_wdtis_4(&self) -> bool {
+        *self == WDTISR::WDTIS_4
+    }
+    #[doc = "Checks if the value of the field is `WDTIS_5`"]
+    #[inline]
+    pub fn is_wdtis_5(&self) -> bool {
+        *self == WDTISR::WDTIS_5
+    }
+    #[doc = "Checks if the value of the field is `WDTIS_6`"]
+    #[inline]
+    pub fn is_wdtis_6(&self) -> bool {
+        *self == WDTISR::WDTIS_6
+    }
+    #[doc = "Checks if the value of the field is `WDTIS_7`"]
+    #[inline]
+    pub fn is_wdtis_7(&self) -> bool {
+        *self == WDTISR::WDTIS_7
+    }
+}
+#[doc = "Possible values of the field `WDTTMSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WDTTMSELR {
+    #[doc = "Watchdog mode"]
+    WDTTMSEL_0,
+    #[doc = "Interval timer mode"]
+    WDTTMSEL_1,
+}
+impl WDTTMSELR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            WDTTMSELR::WDTTMSEL_0 => false,
+            WDTTMSELR::WDTTMSEL_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> WDTTMSELR {
+        match value {
+            false => WDTTMSELR::WDTTMSEL_0,
+            true => WDTTMSELR::WDTTMSEL_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `WDTTMSEL_0`"]
+    #[inline]
+    pub fn is_wdttmsel_0(&self) -> bool {
+        *self == WDTTMSELR::WDTTMSEL_0
+    }
+    #[doc = "Checks if the value of the field is `WDTTMSEL_1`"]
+    #[inline]
+    pub fn is_wdttmsel_1(&self) -> bool {
+        *self == WDTTMSELR::WDTTMSEL_1
+    }
+}
+#[doc = "Possible values of the field `WDTSSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WDTSSELR {
+    #[doc = "SMCLK"]
+    WDTSSEL_0,
+    #[doc = "ACLK"]
+    WDTSSEL_1,
+    #[doc = "VLOCLK"]
+    WDTSSEL_2,
+    #[doc = "BCLK"]
+    WDTSSEL_3,
+}
+impl WDTSSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            WDTSSELR::WDTSSEL_0 => 0,
+            WDTSSELR::WDTSSEL_1 => 1,
+            WDTSSELR::WDTSSEL_2 => 2,
+            WDTSSELR::WDTSSEL_3 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> WDTSSELR {
+        match value {
+            0 => WDTSSELR::WDTSSEL_0,
+            1 => WDTSSELR::WDTSSEL_1,
+            2 => WDTSSELR::WDTSSEL_2,
+            3 => WDTSSELR::WDTSSEL_3,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `WDTSSEL_0`"]
+    #[inline]
+    pub fn is_wdtssel_0(&self) -> bool {
+        *self == WDTSSELR::WDTSSEL_0
+    }
+    #[doc = "Checks if the value of the field is `WDTSSEL_1`"]
+    #[inline]
+    pub fn is_wdtssel_1(&self) -> bool {
+        *self == WDTSSELR::WDTSSEL_1
+    }
+    #[doc = "Checks if the value of the field is `WDTSSEL_2`"]
+    #[inline]
+    pub fn is_wdtssel_2(&self) -> bool {
+        *self == WDTSSELR::WDTSSEL_2
+    }
+    #[doc = "Checks if the value of the field is `WDTSSEL_3`"]
+    #[inline]
+    pub fn is_wdtssel_3(&self) -> bool {
+        *self == WDTSSELR::WDTSSEL_3
+    }
+}
+#[doc = "Possible values of the field `WDTHOLD`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WDTHOLDR {
+    #[doc = "Watchdog timer is not stopped"]
+    WDTHOLD_0,
+    #[doc = "Watchdog timer is stopped"]
+    WDTHOLD_1,
+}
+impl WDTHOLDR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            WDTHOLDR::WDTHOLD_0 => false,
+            WDTHOLDR::WDTHOLD_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> WDTHOLDR {
+        match value {
+            false => WDTHOLDR::WDTHOLD_0,
+            true => WDTHOLDR::WDTHOLD_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `WDTHOLD_0`"]
+    #[inline]
+    pub fn is_wdthold_0(&self) -> bool {
+        *self == WDTHOLDR::WDTHOLD_0
+    }
+    #[doc = "Checks if the value of the field is `WDTHOLD_1`"]
+    #[inline]
+    pub fn is_wdthold_1(&self) -> bool {
+        *self == WDTHOLDR::WDTHOLD_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct WDTPWR {
+    bits: u8,
+}
+impl WDTPWR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Values that can be written to the field `WDTIS`"]
+pub enum WDTISW {
+    #[doc = "Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz)"]
+    WDTIS_0,
+    #[doc = "Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz)"]
+    WDTIS_1,
+    #[doc = "Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz)"]
+    WDTIS_2,
+    #[doc = "Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz)"]
+    WDTIS_3,
+    #[doc = "Watchdog clock source /(2^(15)) (1 s at 32.768 kHz)"]
+    WDTIS_4,
+    #[doc = "Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz)"]
+    WDTIS_5,
+    #[doc = "Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz)"]
+    WDTIS_6,
+    #[doc = "Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz)"]
+    WDTIS_7,
+}
+impl WDTISW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            WDTISW::WDTIS_0 => 0,
+            WDTISW::WDTIS_1 => 1,
+            WDTISW::WDTIS_2 => 2,
+            WDTISW::WDTIS_3 => 3,
+            WDTISW::WDTIS_4 => 4,
+            WDTISW::WDTIS_5 => 5,
+            WDTISW::WDTIS_6 => 6,
+            WDTISW::WDTIS_7 => 7,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _WDTISW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _WDTISW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: WDTISW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz)"]
+    #[inline]
+    pub fn wdtis_0(self) -> &'a mut W {
+        self.variant(WDTISW::WDTIS_0)
+    }
+    #[doc = "Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz)"]
+    #[inline]
+    pub fn wdtis_1(self) -> &'a mut W {
+        self.variant(WDTISW::WDTIS_1)
+    }
+    #[doc = "Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz)"]
+    #[inline]
+    pub fn wdtis_2(self) -> &'a mut W {
+        self.variant(WDTISW::WDTIS_2)
+    }
+    #[doc = "Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz)"]
+    #[inline]
+    pub fn wdtis_3(self) -> &'a mut W {
+        self.variant(WDTISW::WDTIS_3)
+    }
+    #[doc = "Watchdog clock source /(2^(15)) (1 s at 32.768 kHz)"]
+    #[inline]
+    pub fn wdtis_4(self) -> &'a mut W {
+        self.variant(WDTISW::WDTIS_4)
+    }
+    #[doc = "Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz)"]
+    #[inline]
+    pub fn wdtis_5(self) -> &'a mut W {
+        self.variant(WDTISW::WDTIS_5)
+    }
+    #[doc = "Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz)"]
+    #[inline]
+    pub fn wdtis_6(self) -> &'a mut W {
+        self.variant(WDTISW::WDTIS_6)
+    }
+    #[doc = "Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz)"]
+    #[inline]
+    pub fn wdtis_7(self) -> &'a mut W {
+        self.variant(WDTISW::WDTIS_7)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `WDTCNTCL`"]
+pub enum WDTCNTCLW {
+    #[doc = "No action"]
+    WDTCNTCL_0,
+    #[doc = "WDTCNT = 0000h"]
+    WDTCNTCL_1,
+}
+impl WDTCNTCLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            WDTCNTCLW::WDTCNTCL_0 => false,
+            WDTCNTCLW::WDTCNTCL_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _WDTCNTCLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _WDTCNTCLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: WDTCNTCLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No action"]
+    #[inline]
+    pub fn wdtcntcl_0(self) -> &'a mut W {
+        self.variant(WDTCNTCLW::WDTCNTCL_0)
+    }
+    #[doc = "WDTCNT = 0000h"]
+    #[inline]
+    pub fn wdtcntcl_1(self) -> &'a mut W {
+        self.variant(WDTCNTCLW::WDTCNTCL_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `WDTTMSEL`"]
+pub enum WDTTMSELW {
+    #[doc = "Watchdog mode"]
+    WDTTMSEL_0,
+    #[doc = "Interval timer mode"]
+    WDTTMSEL_1,
+}
+impl WDTTMSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            WDTTMSELW::WDTTMSEL_0 => false,
+            WDTTMSELW::WDTTMSEL_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _WDTTMSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _WDTTMSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: WDTTMSELW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Watchdog mode"]
+    #[inline]
+    pub fn wdttmsel_0(self) -> &'a mut W {
+        self.variant(WDTTMSELW::WDTTMSEL_0)
+    }
+    #[doc = "Interval timer mode"]
+    #[inline]
+    pub fn wdttmsel_1(self) -> &'a mut W {
+        self.variant(WDTTMSELW::WDTTMSEL_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `WDTSSEL`"]
+pub enum WDTSSELW {
+    #[doc = "SMCLK"]
+    WDTSSEL_0,
+    #[doc = "ACLK"]
+    WDTSSEL_1,
+    #[doc = "VLOCLK"]
+    WDTSSEL_2,
+    #[doc = "BCLK"]
+    WDTSSEL_3,
+}
+impl WDTSSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            WDTSSELW::WDTSSEL_0 => 0,
+            WDTSSELW::WDTSSEL_1 => 1,
+            WDTSSELW::WDTSSEL_2 => 2,
+            WDTSSELW::WDTSSEL_3 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _WDTSSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _WDTSSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: WDTSSELW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "SMCLK"]
+    #[inline]
+    pub fn wdtssel_0(self) -> &'a mut W {
+        self.variant(WDTSSELW::WDTSSEL_0)
+    }
+    #[doc = "ACLK"]
+    #[inline]
+    pub fn wdtssel_1(self) -> &'a mut W {
+        self.variant(WDTSSELW::WDTSSEL_1)
+    }
+    #[doc = "VLOCLK"]
+    #[inline]
+    pub fn wdtssel_2(self) -> &'a mut W {
+        self.variant(WDTSSELW::WDTSSEL_2)
+    }
+    #[doc = "BCLK"]
+    #[inline]
+    pub fn wdtssel_3(self) -> &'a mut W {
+        self.variant(WDTSSELW::WDTSSEL_3)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `WDTHOLD`"]
+pub enum WDTHOLDW {
+    #[doc = "Watchdog timer is not stopped"]
+    WDTHOLD_0,
+    #[doc = "Watchdog timer is stopped"]
+    WDTHOLD_1,
+}
+impl WDTHOLDW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            WDTHOLDW::WDTHOLD_0 => false,
+            WDTHOLDW::WDTHOLD_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _WDTHOLDW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _WDTHOLDW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: WDTHOLDW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Watchdog timer is not stopped"]
+    #[inline]
+    pub fn wdthold_0(self) -> &'a mut W {
+        self.variant(WDTHOLDW::WDTHOLD_0)
+    }
+    #[doc = "Watchdog timer is stopped"]
+    #[inline]
+    pub fn wdthold_1(self) -> &'a mut W {
+        self.variant(WDTHOLDW::WDTHOLD_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _WDTPWW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _WDTPWW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u16) << OFFSET);
+        self.w.bits |= ((value & MASK) as u16) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:2 - Watchdog timer interval select"]
+    #[inline]
+    pub fn wdtis(&self) -> WDTISR {
+        WDTISR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 4 - Watchdog timer mode select"]
+    #[inline]
+    pub fn wdttmsel(&self) -> WDTTMSELR {
+        WDTTMSELR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 5:6 - Watchdog timer clock source select"]
+    #[inline]
+    pub fn wdtssel(&self) -> WDTSSELR {
+        WDTSSELR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+    #[doc = "Bit 7 - Watchdog timer hold"]
+    #[inline]
+    pub fn wdthold(&self) -> WDTHOLDR {
+        WDTHOLDR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u16) != 0
+        })
+    }
+    #[doc = "Bits 8:15 - Watchdog timer password"]
+    #[inline]
+    pub fn wdtpw(&self) -> WDTPWR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        };
+        WDTPWR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 26884 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:2 - Watchdog timer interval select"]
+    #[inline]
+    pub fn wdtis(&mut self) -> _WDTISW {
+        _WDTISW { w: self }
+    }
+    #[doc = "Bit 3 - Watchdog timer counter clear"]
+    #[inline]
+    pub fn wdtcntcl(&mut self) -> _WDTCNTCLW {
+        _WDTCNTCLW { w: self }
+    }
+    #[doc = "Bit 4 - Watchdog timer mode select"]
+    #[inline]
+    pub fn wdttmsel(&mut self) -> _WDTTMSELW {
+        _WDTTMSELW { w: self }
+    }
+    #[doc = "Bits 5:6 - Watchdog timer clock source select"]
+    #[inline]
+    pub fn wdtssel(&mut self) -> _WDTSSELW {
+        _WDTSSELW { w: self }
+    }
+    #[doc = "Bit 7 - Watchdog timer hold"]
+    #[inline]
+    pub fn wdthold(&mut self) -> _WDTHOLDW {
+        _WDTHOLDW { w: self }
+    }
+    #[doc = "Bits 8:15 - Watchdog timer password"]
+    #[inline]
+    pub fn wdtpw(&mut self) -> _WDTPWW {
+        _WDTPWW { w: self }
+    }
+}