1290 lines
41 KiB
Rust
1290 lines
41 KiB
Rust
#[doc = r" Value read from the register"]
|
|
pub struct R {
|
|
bits: u32,
|
|
}
|
|
#[doc = r" Value to write to the register"]
|
|
pub struct W {
|
|
bits: u32,
|
|
}
|
|
impl super::ADC14MCTL {
|
|
#[doc = r" Modifies the contents of the register"]
|
|
#[inline]
|
|
pub fn modify<F>(&self, f: F)
|
|
where
|
|
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
|
{
|
|
let bits = self.register.get();
|
|
let r = R { bits: bits };
|
|
let mut w = W { bits: bits };
|
|
f(&r, &mut w);
|
|
self.register.set(w.bits);
|
|
}
|
|
#[doc = r" Reads the contents of the register"]
|
|
#[inline]
|
|
pub fn read(&self) -> R {
|
|
R {
|
|
bits: self.register.get(),
|
|
}
|
|
}
|
|
#[doc = r" Writes to the register"]
|
|
#[inline]
|
|
pub fn write<F>(&self, f: F)
|
|
where
|
|
F: FnOnce(&mut W) -> &mut W,
|
|
{
|
|
let mut w = W::reset_value();
|
|
f(&mut w);
|
|
self.register.set(w.bits);
|
|
}
|
|
#[doc = r" Writes the reset value to the register"]
|
|
#[inline]
|
|
pub fn reset(&self) {
|
|
self.write(|w| w)
|
|
}
|
|
}
|
|
#[doc = "Possible values of the field `ADC14INCH`"]
|
|
#[derive(Clone, Copy, Debug, PartialEq)]
|
|
pub enum ADC14INCHR {
|
|
#[doc = "If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1"]
|
|
ADC14INCH_0,
|
|
#[doc = "If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1"]
|
|
ADC14INCH_1,
|
|
#[doc = "If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3"]
|
|
ADC14INCH_2,
|
|
#[doc = "If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3"]
|
|
ADC14INCH_3,
|
|
#[doc = "If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5"]
|
|
ADC14INCH_4,
|
|
#[doc = "If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5"]
|
|
ADC14INCH_5,
|
|
#[doc = "If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7"]
|
|
ADC14INCH_6,
|
|
#[doc = "If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7"]
|
|
ADC14INCH_7,
|
|
#[doc = "If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9"]
|
|
ADC14INCH_8,
|
|
#[doc = "If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9"]
|
|
ADC14INCH_9,
|
|
#[doc = "If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11"]
|
|
ADC14INCH_10,
|
|
#[doc = "If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11"]
|
|
ADC14INCH_11,
|
|
#[doc = "If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13"]
|
|
ADC14INCH_12,
|
|
#[doc = "If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13"]
|
|
ADC14INCH_13,
|
|
#[doc = "If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15"]
|
|
ADC14INCH_14,
|
|
#[doc = "If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15"]
|
|
ADC14INCH_15,
|
|
#[doc = "If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17"]
|
|
ADC14INCH_16,
|
|
#[doc = "If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17"]
|
|
ADC14INCH_17,
|
|
#[doc = "If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19"]
|
|
ADC14INCH_18,
|
|
#[doc = "If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19"]
|
|
ADC14INCH_19,
|
|
#[doc = "If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21"]
|
|
ADC14INCH_20,
|
|
#[doc = "If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21"]
|
|
ADC14INCH_21,
|
|
#[doc = "If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23"]
|
|
ADC14INCH_22,
|
|
#[doc = "If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23"]
|
|
ADC14INCH_23,
|
|
#[doc = "If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25"]
|
|
ADC14INCH_24,
|
|
#[doc = "If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25"]
|
|
ADC14INCH_25,
|
|
#[doc = "If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27"]
|
|
ADC14INCH_26,
|
|
#[doc = "If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27"]
|
|
ADC14INCH_27,
|
|
#[doc = "If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29"]
|
|
ADC14INCH_28,
|
|
#[doc = "If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29"]
|
|
ADC14INCH_29,
|
|
#[doc = "If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31"]
|
|
ADC14INCH_30,
|
|
#[doc = "If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31"]
|
|
ADC14INCH_31,
|
|
}
|
|
impl ADC14INCHR {
|
|
#[doc = r" Value of the field as raw bits"]
|
|
#[inline]
|
|
pub fn bits(&self) -> u8 {
|
|
match *self {
|
|
ADC14INCHR::ADC14INCH_0 => 0,
|
|
ADC14INCHR::ADC14INCH_1 => 1,
|
|
ADC14INCHR::ADC14INCH_2 => 2,
|
|
ADC14INCHR::ADC14INCH_3 => 3,
|
|
ADC14INCHR::ADC14INCH_4 => 4,
|
|
ADC14INCHR::ADC14INCH_5 => 5,
|
|
ADC14INCHR::ADC14INCH_6 => 6,
|
|
ADC14INCHR::ADC14INCH_7 => 7,
|
|
ADC14INCHR::ADC14INCH_8 => 8,
|
|
ADC14INCHR::ADC14INCH_9 => 9,
|
|
ADC14INCHR::ADC14INCH_10 => 10,
|
|
ADC14INCHR::ADC14INCH_11 => 11,
|
|
ADC14INCHR::ADC14INCH_12 => 12,
|
|
ADC14INCHR::ADC14INCH_13 => 13,
|
|
ADC14INCHR::ADC14INCH_14 => 14,
|
|
ADC14INCHR::ADC14INCH_15 => 15,
|
|
ADC14INCHR::ADC14INCH_16 => 16,
|
|
ADC14INCHR::ADC14INCH_17 => 17,
|
|
ADC14INCHR::ADC14INCH_18 => 18,
|
|
ADC14INCHR::ADC14INCH_19 => 19,
|
|
ADC14INCHR::ADC14INCH_20 => 20,
|
|
ADC14INCHR::ADC14INCH_21 => 21,
|
|
ADC14INCHR::ADC14INCH_22 => 22,
|
|
ADC14INCHR::ADC14INCH_23 => 23,
|
|
ADC14INCHR::ADC14INCH_24 => 24,
|
|
ADC14INCHR::ADC14INCH_25 => 25,
|
|
ADC14INCHR::ADC14INCH_26 => 26,
|
|
ADC14INCHR::ADC14INCH_27 => 27,
|
|
ADC14INCHR::ADC14INCH_28 => 28,
|
|
ADC14INCHR::ADC14INCH_29 => 29,
|
|
ADC14INCHR::ADC14INCH_30 => 30,
|
|
ADC14INCHR::ADC14INCH_31 => 31,
|
|
}
|
|
}
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _from(value: u8) -> ADC14INCHR {
|
|
match value {
|
|
0 => ADC14INCHR::ADC14INCH_0,
|
|
1 => ADC14INCHR::ADC14INCH_1,
|
|
2 => ADC14INCHR::ADC14INCH_2,
|
|
3 => ADC14INCHR::ADC14INCH_3,
|
|
4 => ADC14INCHR::ADC14INCH_4,
|
|
5 => ADC14INCHR::ADC14INCH_5,
|
|
6 => ADC14INCHR::ADC14INCH_6,
|
|
7 => ADC14INCHR::ADC14INCH_7,
|
|
8 => ADC14INCHR::ADC14INCH_8,
|
|
9 => ADC14INCHR::ADC14INCH_9,
|
|
10 => ADC14INCHR::ADC14INCH_10,
|
|
11 => ADC14INCHR::ADC14INCH_11,
|
|
12 => ADC14INCHR::ADC14INCH_12,
|
|
13 => ADC14INCHR::ADC14INCH_13,
|
|
14 => ADC14INCHR::ADC14INCH_14,
|
|
15 => ADC14INCHR::ADC14INCH_15,
|
|
16 => ADC14INCHR::ADC14INCH_16,
|
|
17 => ADC14INCHR::ADC14INCH_17,
|
|
18 => ADC14INCHR::ADC14INCH_18,
|
|
19 => ADC14INCHR::ADC14INCH_19,
|
|
20 => ADC14INCHR::ADC14INCH_20,
|
|
21 => ADC14INCHR::ADC14INCH_21,
|
|
22 => ADC14INCHR::ADC14INCH_22,
|
|
23 => ADC14INCHR::ADC14INCH_23,
|
|
24 => ADC14INCHR::ADC14INCH_24,
|
|
25 => ADC14INCHR::ADC14INCH_25,
|
|
26 => ADC14INCHR::ADC14INCH_26,
|
|
27 => ADC14INCHR::ADC14INCH_27,
|
|
28 => ADC14INCHR::ADC14INCH_28,
|
|
29 => ADC14INCHR::ADC14INCH_29,
|
|
30 => ADC14INCHR::ADC14INCH_30,
|
|
31 => ADC14INCHR::ADC14INCH_31,
|
|
_ => unreachable!(),
|
|
}
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_0`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_0(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_0
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_1`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_1(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_1
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_2`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_2(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_2
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_3`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_3(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_3
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_4`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_4(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_4
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_5`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_5(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_5
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_6`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_6(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_6
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_7`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_7(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_7
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_8`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_8(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_8
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_9`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_9(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_9
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_10`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_10(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_10
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_11`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_11(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_11
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_12`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_12(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_12
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_13`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_13(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_13
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_14`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_14(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_14
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_15`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_15(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_15
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_16`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_16(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_16
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_17`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_17(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_17
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_18`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_18(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_18
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_19`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_19(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_19
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_20`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_20(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_20
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_21`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_21(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_21
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_22`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_22(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_22
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_23`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_23(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_23
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_24`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_24(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_24
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_25`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_25(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_25
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_26`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_26(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_26
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_27`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_27(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_27
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_28`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_28(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_28
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_29`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_29(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_29
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_30`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_30(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_30
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14INCH_31`"]
|
|
#[inline]
|
|
pub fn is_adc14inch_31(&self) -> bool {
|
|
*self == ADC14INCHR::ADC14INCH_31
|
|
}
|
|
}
|
|
#[doc = "Possible values of the field `ADC14EOS`"]
|
|
#[derive(Clone, Copy, Debug, PartialEq)]
|
|
pub enum ADC14EOSR {
|
|
#[doc = "Not end of sequence"]
|
|
ADC14EOS_0,
|
|
#[doc = "End of sequence"]
|
|
ADC14EOS_1,
|
|
}
|
|
impl ADC14EOSR {
|
|
#[doc = r" Returns `true` if the bit is clear (0)"]
|
|
#[inline]
|
|
pub fn bit_is_clear(&self) -> bool {
|
|
!self.bit()
|
|
}
|
|
#[doc = r" Returns `true` if the bit is set (1)"]
|
|
#[inline]
|
|
pub fn bit_is_set(&self) -> bool {
|
|
self.bit()
|
|
}
|
|
#[doc = r" Value of the field as raw bits"]
|
|
#[inline]
|
|
pub fn bit(&self) -> bool {
|
|
match *self {
|
|
ADC14EOSR::ADC14EOS_0 => false,
|
|
ADC14EOSR::ADC14EOS_1 => true,
|
|
}
|
|
}
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _from(value: bool) -> ADC14EOSR {
|
|
match value {
|
|
false => ADC14EOSR::ADC14EOS_0,
|
|
true => ADC14EOSR::ADC14EOS_1,
|
|
}
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14EOS_0`"]
|
|
#[inline]
|
|
pub fn is_adc14eos_0(&self) -> bool {
|
|
*self == ADC14EOSR::ADC14EOS_0
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14EOS_1`"]
|
|
#[inline]
|
|
pub fn is_adc14eos_1(&self) -> bool {
|
|
*self == ADC14EOSR::ADC14EOS_1
|
|
}
|
|
}
|
|
#[doc = "Possible values of the field `ADC14VRSEL`"]
|
|
#[derive(Clone, Copy, Debug, PartialEq)]
|
|
pub enum ADC14VRSELR {
|
|
#[doc = "V(R+) = AVCC, V(R-) = AVSS"]
|
|
ADC14VRSEL_0,
|
|
#[doc = "V(R+) = VREF buffered, V(R-) = AVSS"]
|
|
ADC14VRSEL_1,
|
|
#[doc = "V(R+) = VeREF+, V(R-) = VeREF-"]
|
|
ADC14VRSEL_14,
|
|
#[doc = "V(R+) = VeREF+ buffered, V(R-) = VeREF"]
|
|
ADC14VRSEL_15,
|
|
#[doc = r" Reserved"]
|
|
_Reserved(u8),
|
|
}
|
|
impl ADC14VRSELR {
|
|
#[doc = r" Value of the field as raw bits"]
|
|
#[inline]
|
|
pub fn bits(&self) -> u8 {
|
|
match *self {
|
|
ADC14VRSELR::ADC14VRSEL_0 => 0,
|
|
ADC14VRSELR::ADC14VRSEL_1 => 1,
|
|
ADC14VRSELR::ADC14VRSEL_14 => 14,
|
|
ADC14VRSELR::ADC14VRSEL_15 => 15,
|
|
ADC14VRSELR::_Reserved(bits) => bits,
|
|
}
|
|
}
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _from(value: u8) -> ADC14VRSELR {
|
|
match value {
|
|
0 => ADC14VRSELR::ADC14VRSEL_0,
|
|
1 => ADC14VRSELR::ADC14VRSEL_1,
|
|
14 => ADC14VRSELR::ADC14VRSEL_14,
|
|
15 => ADC14VRSELR::ADC14VRSEL_15,
|
|
i => ADC14VRSELR::_Reserved(i),
|
|
}
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14VRSEL_0`"]
|
|
#[inline]
|
|
pub fn is_adc14vrsel_0(&self) -> bool {
|
|
*self == ADC14VRSELR::ADC14VRSEL_0
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14VRSEL_1`"]
|
|
#[inline]
|
|
pub fn is_adc14vrsel_1(&self) -> bool {
|
|
*self == ADC14VRSELR::ADC14VRSEL_1
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14VRSEL_14`"]
|
|
#[inline]
|
|
pub fn is_adc14vrsel_14(&self) -> bool {
|
|
*self == ADC14VRSELR::ADC14VRSEL_14
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14VRSEL_15`"]
|
|
#[inline]
|
|
pub fn is_adc14vrsel_15(&self) -> bool {
|
|
*self == ADC14VRSELR::ADC14VRSEL_15
|
|
}
|
|
}
|
|
#[doc = "Possible values of the field `ADC14DIF`"]
|
|
#[derive(Clone, Copy, Debug, PartialEq)]
|
|
pub enum ADC14DIFR {
|
|
#[doc = "Single-ended mode enabled"]
|
|
ADC14DIF_0,
|
|
#[doc = "Differential mode enabled"]
|
|
ADC14DIF_1,
|
|
}
|
|
impl ADC14DIFR {
|
|
#[doc = r" Returns `true` if the bit is clear (0)"]
|
|
#[inline]
|
|
pub fn bit_is_clear(&self) -> bool {
|
|
!self.bit()
|
|
}
|
|
#[doc = r" Returns `true` if the bit is set (1)"]
|
|
#[inline]
|
|
pub fn bit_is_set(&self) -> bool {
|
|
self.bit()
|
|
}
|
|
#[doc = r" Value of the field as raw bits"]
|
|
#[inline]
|
|
pub fn bit(&self) -> bool {
|
|
match *self {
|
|
ADC14DIFR::ADC14DIF_0 => false,
|
|
ADC14DIFR::ADC14DIF_1 => true,
|
|
}
|
|
}
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _from(value: bool) -> ADC14DIFR {
|
|
match value {
|
|
false => ADC14DIFR::ADC14DIF_0,
|
|
true => ADC14DIFR::ADC14DIF_1,
|
|
}
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14DIF_0`"]
|
|
#[inline]
|
|
pub fn is_adc14dif_0(&self) -> bool {
|
|
*self == ADC14DIFR::ADC14DIF_0
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14DIF_1`"]
|
|
#[inline]
|
|
pub fn is_adc14dif_1(&self) -> bool {
|
|
*self == ADC14DIFR::ADC14DIF_1
|
|
}
|
|
}
|
|
#[doc = "Possible values of the field `ADC14WINC`"]
|
|
#[derive(Clone, Copy, Debug, PartialEq)]
|
|
pub enum ADC14WINCR {
|
|
#[doc = "Comparator window disabled"]
|
|
ADC14WINC_0,
|
|
#[doc = "Comparator window enabled"]
|
|
ADC14WINC_1,
|
|
}
|
|
impl ADC14WINCR {
|
|
#[doc = r" Returns `true` if the bit is clear (0)"]
|
|
#[inline]
|
|
pub fn bit_is_clear(&self) -> bool {
|
|
!self.bit()
|
|
}
|
|
#[doc = r" Returns `true` if the bit is set (1)"]
|
|
#[inline]
|
|
pub fn bit_is_set(&self) -> bool {
|
|
self.bit()
|
|
}
|
|
#[doc = r" Value of the field as raw bits"]
|
|
#[inline]
|
|
pub fn bit(&self) -> bool {
|
|
match *self {
|
|
ADC14WINCR::ADC14WINC_0 => false,
|
|
ADC14WINCR::ADC14WINC_1 => true,
|
|
}
|
|
}
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _from(value: bool) -> ADC14WINCR {
|
|
match value {
|
|
false => ADC14WINCR::ADC14WINC_0,
|
|
true => ADC14WINCR::ADC14WINC_1,
|
|
}
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14WINC_0`"]
|
|
#[inline]
|
|
pub fn is_adc14winc_0(&self) -> bool {
|
|
*self == ADC14WINCR::ADC14WINC_0
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14WINC_1`"]
|
|
#[inline]
|
|
pub fn is_adc14winc_1(&self) -> bool {
|
|
*self == ADC14WINCR::ADC14WINC_1
|
|
}
|
|
}
|
|
#[doc = "Possible values of the field `ADC14WINCTH`"]
|
|
#[derive(Clone, Copy, Debug, PartialEq)]
|
|
pub enum ADC14WINCTHR {
|
|
#[doc = "Use window comparator thresholds 0, ADC14LO0 and ADC14HI0"]
|
|
ADC14WINCTH_0,
|
|
#[doc = "Use window comparator thresholds 1, ADC14LO1 and ADC14HI1"]
|
|
ADC14WINCTH_1,
|
|
}
|
|
impl ADC14WINCTHR {
|
|
#[doc = r" Returns `true` if the bit is clear (0)"]
|
|
#[inline]
|
|
pub fn bit_is_clear(&self) -> bool {
|
|
!self.bit()
|
|
}
|
|
#[doc = r" Returns `true` if the bit is set (1)"]
|
|
#[inline]
|
|
pub fn bit_is_set(&self) -> bool {
|
|
self.bit()
|
|
}
|
|
#[doc = r" Value of the field as raw bits"]
|
|
#[inline]
|
|
pub fn bit(&self) -> bool {
|
|
match *self {
|
|
ADC14WINCTHR::ADC14WINCTH_0 => false,
|
|
ADC14WINCTHR::ADC14WINCTH_1 => true,
|
|
}
|
|
}
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _from(value: bool) -> ADC14WINCTHR {
|
|
match value {
|
|
false => ADC14WINCTHR::ADC14WINCTH_0,
|
|
true => ADC14WINCTHR::ADC14WINCTH_1,
|
|
}
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14WINCTH_0`"]
|
|
#[inline]
|
|
pub fn is_adc14wincth_0(&self) -> bool {
|
|
*self == ADC14WINCTHR::ADC14WINCTH_0
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14WINCTH_1`"]
|
|
#[inline]
|
|
pub fn is_adc14wincth_1(&self) -> bool {
|
|
*self == ADC14WINCTHR::ADC14WINCTH_1
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `ADC14INCH`"]
|
|
pub enum ADC14INCHW {
|
|
#[doc = "If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1"]
|
|
ADC14INCH_0,
|
|
#[doc = "If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1"]
|
|
ADC14INCH_1,
|
|
#[doc = "If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3"]
|
|
ADC14INCH_2,
|
|
#[doc = "If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3"]
|
|
ADC14INCH_3,
|
|
#[doc = "If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5"]
|
|
ADC14INCH_4,
|
|
#[doc = "If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5"]
|
|
ADC14INCH_5,
|
|
#[doc = "If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7"]
|
|
ADC14INCH_6,
|
|
#[doc = "If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7"]
|
|
ADC14INCH_7,
|
|
#[doc = "If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9"]
|
|
ADC14INCH_8,
|
|
#[doc = "If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9"]
|
|
ADC14INCH_9,
|
|
#[doc = "If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11"]
|
|
ADC14INCH_10,
|
|
#[doc = "If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11"]
|
|
ADC14INCH_11,
|
|
#[doc = "If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13"]
|
|
ADC14INCH_12,
|
|
#[doc = "If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13"]
|
|
ADC14INCH_13,
|
|
#[doc = "If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15"]
|
|
ADC14INCH_14,
|
|
#[doc = "If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15"]
|
|
ADC14INCH_15,
|
|
#[doc = "If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17"]
|
|
ADC14INCH_16,
|
|
#[doc = "If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17"]
|
|
ADC14INCH_17,
|
|
#[doc = "If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19"]
|
|
ADC14INCH_18,
|
|
#[doc = "If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19"]
|
|
ADC14INCH_19,
|
|
#[doc = "If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21"]
|
|
ADC14INCH_20,
|
|
#[doc = "If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21"]
|
|
ADC14INCH_21,
|
|
#[doc = "If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23"]
|
|
ADC14INCH_22,
|
|
#[doc = "If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23"]
|
|
ADC14INCH_23,
|
|
#[doc = "If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25"]
|
|
ADC14INCH_24,
|
|
#[doc = "If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25"]
|
|
ADC14INCH_25,
|
|
#[doc = "If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27"]
|
|
ADC14INCH_26,
|
|
#[doc = "If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27"]
|
|
ADC14INCH_27,
|
|
#[doc = "If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29"]
|
|
ADC14INCH_28,
|
|
#[doc = "If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29"]
|
|
ADC14INCH_29,
|
|
#[doc = "If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31"]
|
|
ADC14INCH_30,
|
|
#[doc = "If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31"]
|
|
ADC14INCH_31,
|
|
}
|
|
impl ADC14INCHW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> u8 {
|
|
match *self {
|
|
ADC14INCHW::ADC14INCH_0 => 0,
|
|
ADC14INCHW::ADC14INCH_1 => 1,
|
|
ADC14INCHW::ADC14INCH_2 => 2,
|
|
ADC14INCHW::ADC14INCH_3 => 3,
|
|
ADC14INCHW::ADC14INCH_4 => 4,
|
|
ADC14INCHW::ADC14INCH_5 => 5,
|
|
ADC14INCHW::ADC14INCH_6 => 6,
|
|
ADC14INCHW::ADC14INCH_7 => 7,
|
|
ADC14INCHW::ADC14INCH_8 => 8,
|
|
ADC14INCHW::ADC14INCH_9 => 9,
|
|
ADC14INCHW::ADC14INCH_10 => 10,
|
|
ADC14INCHW::ADC14INCH_11 => 11,
|
|
ADC14INCHW::ADC14INCH_12 => 12,
|
|
ADC14INCHW::ADC14INCH_13 => 13,
|
|
ADC14INCHW::ADC14INCH_14 => 14,
|
|
ADC14INCHW::ADC14INCH_15 => 15,
|
|
ADC14INCHW::ADC14INCH_16 => 16,
|
|
ADC14INCHW::ADC14INCH_17 => 17,
|
|
ADC14INCHW::ADC14INCH_18 => 18,
|
|
ADC14INCHW::ADC14INCH_19 => 19,
|
|
ADC14INCHW::ADC14INCH_20 => 20,
|
|
ADC14INCHW::ADC14INCH_21 => 21,
|
|
ADC14INCHW::ADC14INCH_22 => 22,
|
|
ADC14INCHW::ADC14INCH_23 => 23,
|
|
ADC14INCHW::ADC14INCH_24 => 24,
|
|
ADC14INCHW::ADC14INCH_25 => 25,
|
|
ADC14INCHW::ADC14INCH_26 => 26,
|
|
ADC14INCHW::ADC14INCH_27 => 27,
|
|
ADC14INCHW::ADC14INCH_28 => 28,
|
|
ADC14INCHW::ADC14INCH_29 => 29,
|
|
ADC14INCHW::ADC14INCH_30 => 30,
|
|
ADC14INCHW::ADC14INCH_31 => 31,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ADC14INCHW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ADC14INCHW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: ADC14INCHW) -> &'a mut W {
|
|
{
|
|
self.bits(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1"]
|
|
#[inline]
|
|
pub fn adc14inch_0(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_0)
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1"]
|
|
#[inline]
|
|
pub fn adc14inch_1(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_1)
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3"]
|
|
#[inline]
|
|
pub fn adc14inch_2(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_2)
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3"]
|
|
#[inline]
|
|
pub fn adc14inch_3(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_3)
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5"]
|
|
#[inline]
|
|
pub fn adc14inch_4(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_4)
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5"]
|
|
#[inline]
|
|
pub fn adc14inch_5(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_5)
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7"]
|
|
#[inline]
|
|
pub fn adc14inch_6(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_6)
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7"]
|
|
#[inline]
|
|
pub fn adc14inch_7(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_7)
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9"]
|
|
#[inline]
|
|
pub fn adc14inch_8(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_8)
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9"]
|
|
#[inline]
|
|
pub fn adc14inch_9(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_9)
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11"]
|
|
#[inline]
|
|
pub fn adc14inch_10(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_10)
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11"]
|
|
#[inline]
|
|
pub fn adc14inch_11(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_11)
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13"]
|
|
#[inline]
|
|
pub fn adc14inch_12(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_12)
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13"]
|
|
#[inline]
|
|
pub fn adc14inch_13(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_13)
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15"]
|
|
#[inline]
|
|
pub fn adc14inch_14(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_14)
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15"]
|
|
#[inline]
|
|
pub fn adc14inch_15(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_15)
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17"]
|
|
#[inline]
|
|
pub fn adc14inch_16(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_16)
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17"]
|
|
#[inline]
|
|
pub fn adc14inch_17(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_17)
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19"]
|
|
#[inline]
|
|
pub fn adc14inch_18(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_18)
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19"]
|
|
#[inline]
|
|
pub fn adc14inch_19(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_19)
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21"]
|
|
#[inline]
|
|
pub fn adc14inch_20(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_20)
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21"]
|
|
#[inline]
|
|
pub fn adc14inch_21(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_21)
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23"]
|
|
#[inline]
|
|
pub fn adc14inch_22(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_22)
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23"]
|
|
#[inline]
|
|
pub fn adc14inch_23(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_23)
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25"]
|
|
#[inline]
|
|
pub fn adc14inch_24(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_24)
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25"]
|
|
#[inline]
|
|
pub fn adc14inch_25(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_25)
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27"]
|
|
#[inline]
|
|
pub fn adc14inch_26(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_26)
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27"]
|
|
#[inline]
|
|
pub fn adc14inch_27(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_27)
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29"]
|
|
#[inline]
|
|
pub fn adc14inch_28(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_28)
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29"]
|
|
#[inline]
|
|
pub fn adc14inch_29(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_29)
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31"]
|
|
#[inline]
|
|
pub fn adc14inch_30(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_30)
|
|
}
|
|
#[doc = "If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31"]
|
|
#[inline]
|
|
pub fn adc14inch_31(self) -> &'a mut W {
|
|
self.variant(ADC14INCHW::ADC14INCH_31)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bits(self, value: u8) -> &'a mut W {
|
|
const MASK: u8 = 31;
|
|
const OFFSET: u8 = 0;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `ADC14EOS`"]
|
|
pub enum ADC14EOSW {
|
|
#[doc = "Not end of sequence"]
|
|
ADC14EOS_0,
|
|
#[doc = "End of sequence"]
|
|
ADC14EOS_1,
|
|
}
|
|
impl ADC14EOSW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> bool {
|
|
match *self {
|
|
ADC14EOSW::ADC14EOS_0 => false,
|
|
ADC14EOSW::ADC14EOS_1 => true,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ADC14EOSW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ADC14EOSW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: ADC14EOSW) -> &'a mut W {
|
|
{
|
|
self.bit(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "Not end of sequence"]
|
|
#[inline]
|
|
pub fn adc14eos_0(self) -> &'a mut W {
|
|
self.variant(ADC14EOSW::ADC14EOS_0)
|
|
}
|
|
#[doc = "End of sequence"]
|
|
#[inline]
|
|
pub fn adc14eos_1(self) -> &'a mut W {
|
|
self.variant(ADC14EOSW::ADC14EOS_1)
|
|
}
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
|
|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 7;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `ADC14VRSEL`"]
|
|
pub enum ADC14VRSELW {
|
|
#[doc = "V(R+) = AVCC, V(R-) = AVSS"]
|
|
ADC14VRSEL_0,
|
|
#[doc = "V(R+) = VREF buffered, V(R-) = AVSS"]
|
|
ADC14VRSEL_1,
|
|
#[doc = "V(R+) = VeREF+, V(R-) = VeREF-"]
|
|
ADC14VRSEL_14,
|
|
#[doc = "V(R+) = VeREF+ buffered, V(R-) = VeREF"]
|
|
ADC14VRSEL_15,
|
|
}
|
|
impl ADC14VRSELW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> u8 {
|
|
match *self {
|
|
ADC14VRSELW::ADC14VRSEL_0 => 0,
|
|
ADC14VRSELW::ADC14VRSEL_1 => 1,
|
|
ADC14VRSELW::ADC14VRSEL_14 => 14,
|
|
ADC14VRSELW::ADC14VRSEL_15 => 15,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ADC14VRSELW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ADC14VRSELW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: ADC14VRSELW) -> &'a mut W {
|
|
unsafe { self.bits(variant._bits()) }
|
|
}
|
|
#[doc = "V(R+) = AVCC, V(R-) = AVSS"]
|
|
#[inline]
|
|
pub fn adc14vrsel_0(self) -> &'a mut W {
|
|
self.variant(ADC14VRSELW::ADC14VRSEL_0)
|
|
}
|
|
#[doc = "V(R+) = VREF buffered, V(R-) = AVSS"]
|
|
#[inline]
|
|
pub fn adc14vrsel_1(self) -> &'a mut W {
|
|
self.variant(ADC14VRSELW::ADC14VRSEL_1)
|
|
}
|
|
#[doc = "V(R+) = VeREF+, V(R-) = VeREF-"]
|
|
#[inline]
|
|
pub fn adc14vrsel_14(self) -> &'a mut W {
|
|
self.variant(ADC14VRSELW::ADC14VRSEL_14)
|
|
}
|
|
#[doc = "V(R+) = VeREF+ buffered, V(R-) = VeREF"]
|
|
#[inline]
|
|
pub fn adc14vrsel_15(self) -> &'a mut W {
|
|
self.variant(ADC14VRSELW::ADC14VRSEL_15)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
|
const MASK: u8 = 15;
|
|
const OFFSET: u8 = 8;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `ADC14DIF`"]
|
|
pub enum ADC14DIFW {
|
|
#[doc = "Single-ended mode enabled"]
|
|
ADC14DIF_0,
|
|
#[doc = "Differential mode enabled"]
|
|
ADC14DIF_1,
|
|
}
|
|
impl ADC14DIFW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> bool {
|
|
match *self {
|
|
ADC14DIFW::ADC14DIF_0 => false,
|
|
ADC14DIFW::ADC14DIF_1 => true,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ADC14DIFW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ADC14DIFW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: ADC14DIFW) -> &'a mut W {
|
|
{
|
|
self.bit(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "Single-ended mode enabled"]
|
|
#[inline]
|
|
pub fn adc14dif_0(self) -> &'a mut W {
|
|
self.variant(ADC14DIFW::ADC14DIF_0)
|
|
}
|
|
#[doc = "Differential mode enabled"]
|
|
#[inline]
|
|
pub fn adc14dif_1(self) -> &'a mut W {
|
|
self.variant(ADC14DIFW::ADC14DIF_1)
|
|
}
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
|
|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 13;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `ADC14WINC`"]
|
|
pub enum ADC14WINCW {
|
|
#[doc = "Comparator window disabled"]
|
|
ADC14WINC_0,
|
|
#[doc = "Comparator window enabled"]
|
|
ADC14WINC_1,
|
|
}
|
|
impl ADC14WINCW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> bool {
|
|
match *self {
|
|
ADC14WINCW::ADC14WINC_0 => false,
|
|
ADC14WINCW::ADC14WINC_1 => true,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ADC14WINCW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ADC14WINCW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: ADC14WINCW) -> &'a mut W {
|
|
{
|
|
self.bit(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "Comparator window disabled"]
|
|
#[inline]
|
|
pub fn adc14winc_0(self) -> &'a mut W {
|
|
self.variant(ADC14WINCW::ADC14WINC_0)
|
|
}
|
|
#[doc = "Comparator window enabled"]
|
|
#[inline]
|
|
pub fn adc14winc_1(self) -> &'a mut W {
|
|
self.variant(ADC14WINCW::ADC14WINC_1)
|
|
}
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
|
|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 14;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `ADC14WINCTH`"]
|
|
pub enum ADC14WINCTHW {
|
|
#[doc = "Use window comparator thresholds 0, ADC14LO0 and ADC14HI0"]
|
|
ADC14WINCTH_0,
|
|
#[doc = "Use window comparator thresholds 1, ADC14LO1 and ADC14HI1"]
|
|
ADC14WINCTH_1,
|
|
}
|
|
impl ADC14WINCTHW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> bool {
|
|
match *self {
|
|
ADC14WINCTHW::ADC14WINCTH_0 => false,
|
|
ADC14WINCTHW::ADC14WINCTH_1 => true,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ADC14WINCTHW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ADC14WINCTHW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: ADC14WINCTHW) -> &'a mut W {
|
|
{
|
|
self.bit(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "Use window comparator thresholds 0, ADC14LO0 and ADC14HI0"]
|
|
#[inline]
|
|
pub fn adc14wincth_0(self) -> &'a mut W {
|
|
self.variant(ADC14WINCTHW::ADC14WINCTH_0)
|
|
}
|
|
#[doc = "Use window comparator thresholds 1, ADC14LO1 and ADC14HI1"]
|
|
#[inline]
|
|
pub fn adc14wincth_1(self) -> &'a mut W {
|
|
self.variant(ADC14WINCTHW::ADC14WINCTH_1)
|
|
}
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
|
|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 15;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
impl R {
|
|
#[doc = r" Value of the register as raw bits"]
|
|
#[inline]
|
|
pub fn bits(&self) -> u32 {
|
|
self.bits
|
|
}
|
|
#[doc = "Bits 0:4 - Input channel select"]
|
|
#[inline]
|
|
pub fn adc14inch(&self) -> ADC14INCHR {
|
|
ADC14INCHR::_from({
|
|
const MASK: u8 = 31;
|
|
const OFFSET: u8 = 0;
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
|
})
|
|
}
|
|
#[doc = "Bit 7 - End of sequence"]
|
|
#[inline]
|
|
pub fn adc14eos(&self) -> ADC14EOSR {
|
|
ADC14EOSR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 7;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
#[doc = "Bits 8:11 - Selects combinations of V(R+) and V(R-) sources"]
|
|
#[inline]
|
|
pub fn adc14vrsel(&self) -> ADC14VRSELR {
|
|
ADC14VRSELR::_from({
|
|
const MASK: u8 = 15;
|
|
const OFFSET: u8 = 8;
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
|
})
|
|
}
|
|
#[doc = "Bit 13 - Differential mode"]
|
|
#[inline]
|
|
pub fn adc14dif(&self) -> ADC14DIFR {
|
|
ADC14DIFR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 13;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
#[doc = "Bit 14 - Comparator window enable"]
|
|
#[inline]
|
|
pub fn adc14winc(&self) -> ADC14WINCR {
|
|
ADC14WINCR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 14;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
#[doc = "Bit 15 - Window comparator threshold register selection"]
|
|
#[inline]
|
|
pub fn adc14wincth(&self) -> ADC14WINCTHR {
|
|
ADC14WINCTHR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 15;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
}
|
|
impl W {
|
|
#[doc = r" Reset value of the register"]
|
|
#[inline]
|
|
pub fn reset_value() -> W {
|
|
W { bits: 0 }
|
|
}
|
|
#[doc = r" Writes raw bits to the register"]
|
|
#[inline]
|
|
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
|
self.bits = bits;
|
|
self
|
|
}
|
|
#[doc = "Bits 0:4 - Input channel select"]
|
|
#[inline]
|
|
pub fn adc14inch(&mut self) -> _ADC14INCHW {
|
|
_ADC14INCHW { w: self }
|
|
}
|
|
#[doc = "Bit 7 - End of sequence"]
|
|
#[inline]
|
|
pub fn adc14eos(&mut self) -> _ADC14EOSW {
|
|
_ADC14EOSW { w: self }
|
|
}
|
|
#[doc = "Bits 8:11 - Selects combinations of V(R+) and V(R-) sources"]
|
|
#[inline]
|
|
pub fn adc14vrsel(&mut self) -> _ADC14VRSELW {
|
|
_ADC14VRSELW { w: self }
|
|
}
|
|
#[doc = "Bit 13 - Differential mode"]
|
|
#[inline]
|
|
pub fn adc14dif(&mut self) -> _ADC14DIFW {
|
|
_ADC14DIFW { w: self }
|
|
}
|
|
#[doc = "Bit 14 - Comparator window enable"]
|
|
#[inline]
|
|
pub fn adc14winc(&mut self) -> _ADC14WINCW {
|
|
_ADC14WINCW { w: self }
|
|
}
|
|
#[doc = "Bit 15 - Window comparator threshold register selection"]
|
|
#[inline]
|
|
pub fn adc14wincth(&mut self) -> _ADC14WINCTHW {
|
|
_ADC14WINCTHW { w: self }
|
|
}
|
|
}
|