42238 lines
2.1 MiB
42238 lines
2.1 MiB
<?xml version="1.0" encoding="utf-8"?>
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<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
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<vendor>Texas Instruments</vendor>
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<vendorID>ti.com</vendorID>
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<name>MSP432P401R</name>
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<version>3.230</version>
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<description>ARM Cortex-M4 MSP432P4xx Device</description>
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<licenseText>
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\n
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Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/\n
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\n
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Redistribution and use in source and binary forms, with or without\n
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modification, are permitted provided that the following conditions\n
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are met:
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\n
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Redistributions of source code must retain the above copyright\n
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notice, this list of conditions and the following disclaimer.\n
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\n
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Redistributions in binary form must reproduce the above copyright\n
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notice, this list of conditions and the following disclaimer in the\n
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documentation and/or other materials provided with the\n
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distribution.\n
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\n
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Neither the name of Texas Instruments Incorporated nor the names of\n
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its contributors may be used to endorse or promote products derived\n
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from this software without specific prior written permission.\n
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\n
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n
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\n
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</licenseText>
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<!-- Bus Interface Properties -->
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<addressUnitBits>8</addressUnitBits>
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<width>32</width>
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<!-- -->
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<!-- Register Default Properties -->
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<size>32</size>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xffffffff</resetMask>
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<!-- -->
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<peripherals>
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<peripheral>
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<name>TLV</name>
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<version>356.0</version>
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<description>TLV</description>
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<baseAddress>0x201000</baseAddress>
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<addressBlock>
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<offset>0x0</offset>
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<size>0x15C</size>
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<usage>registers</usage>
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</addressBlock>
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<registers>
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<register>
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<name>TLV_CHECKSUM</name>
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<displayName>TLV_CHECKSUM</displayName>
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<description>TLV Checksum</description>
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<addressOffset>0x0</addressOffset>
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<size>32</size>
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<access>read-only</access>
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</register>
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<register>
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<name>DEVICE_INFO_TAG</name>
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<displayName>DEVICE_INFO_TAG</displayName>
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|
<description>Device Info Tag</description>
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<addressOffset>0x4</addressOffset>
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<size>32</size>
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<access>read-only</access>
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<resetValue>0x0000000b</resetValue>
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<resetMask>0xffffffff</resetMask>
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</register>
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<register>
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<name>DEVICE_INFO_LEN</name>
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<displayName>DEVICE_INFO_LEN</displayName>
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|
<description>Device Info Length</description>
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<addressOffset>0x8</addressOffset>
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<size>32</size>
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<access>read-only</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xffffffff</resetMask>
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</register>
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<register>
|
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<name>DEVICE_ID</name>
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<displayName>DEVICE_ID</displayName>
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<description>Device ID</description>
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<addressOffset>0xC</addressOffset>
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<size>32</size>
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<access>read-only</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xffffffff</resetMask>
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|
</register>
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|
<register>
|
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<name>HWREV</name>
|
|
<displayName>HWREV</displayName>
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<description>HW Revision</description>
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<addressOffset>0x10</addressOffset>
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<size>32</size>
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<access>read-only</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xffffffff</resetMask>
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</register>
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<register>
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<name>BCREV</name>
|
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<displayName>BCREV</displayName>
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<description>Boot Code Revision</description>
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<addressOffset>0x14</addressOffset>
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<size>32</size>
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<access>read-only</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xffffffff</resetMask>
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</register>
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<register>
|
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<name>ROM_DRVLIB_REV</name>
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<displayName>ROM_DRVLIB_REV</displayName>
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<description>ROM Driver Library Revision</description>
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<addressOffset>0x18</addressOffset>
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<size>32</size>
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<access>read-only</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xffffffff</resetMask>
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</register>
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<register>
|
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<name>DIE_REC_TAG</name>
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<displayName>DIE_REC_TAG</displayName>
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<description>Die Record Tag</description>
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<addressOffset>0x1C</addressOffset>
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<size>32</size>
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<access>read-only</access>
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<resetValue>0x0000000c</resetValue>
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<resetMask>0xffffffff</resetMask>
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</register>
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<register>
|
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<name>DIE_REC_LEN</name>
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<displayName>DIE_REC_LEN</displayName>
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|
<description>Die Record Length</description>
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<addressOffset>0x20</addressOffset>
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<size>32</size>
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<access>read-only</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xffffffff</resetMask>
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</register>
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<register>
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<name>DIE_XPOS</name>
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<displayName>DIE_XPOS</displayName>
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<description>Die X-Position</description>
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<addressOffset>0x24</addressOffset>
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<size>32</size>
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<access>read-only</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xffffffff</resetMask>
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</register>
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<register>
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<name>DIE_YPOS</name>
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<displayName>DIE_YPOS</displayName>
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<description>Die Y-Position</description>
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<addressOffset>0x28</addressOffset>
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<size>32</size>
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<access>read-only</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xffffffff</resetMask>
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</register>
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<register>
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<name>WAFER_ID</name>
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<displayName>WAFER_ID</displayName>
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<description>Wafer ID</description>
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<addressOffset>0x2C</addressOffset>
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<size>32</size>
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<access>read-only</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xffffffff</resetMask>
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</register>
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<register>
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<name>LOT_ID</name>
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<displayName>LOT_ID</displayName>
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<description>Lot ID</description>
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<addressOffset>0x30</addressOffset>
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<size>32</size>
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<access>read-only</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xffffffff</resetMask>
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</register>
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<register>
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<name>RESERVED0</name>
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<displayName>RESERVED0</displayName>
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<description>Reserved</description>
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<addressOffset>0x34</addressOffset>
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<size>32</size>
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<access>read-only</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xffffffff</resetMask>
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</register>
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<register>
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<name>RESERVED1</name>
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<displayName>RESERVED1</displayName>
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<description>Reserved</description>
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<addressOffset>0x38</addressOffset>
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<size>32</size>
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<access>read-only</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xffffffff</resetMask>
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</register>
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<register>
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<name>RESERVED2</name>
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<displayName>RESERVED2</displayName>
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<description>Reserved</description>
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<addressOffset>0x3C</addressOffset>
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<size>32</size>
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<access>read-only</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xffffffff</resetMask>
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</register>
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<register>
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<name>TEST_RESULTS</name>
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<displayName>TEST_RESULTS</displayName>
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<description>Test Results</description>
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<addressOffset>0x40</addressOffset>
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<size>32</size>
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<access>read-only</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xffffffff</resetMask>
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</register>
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<register>
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<name>CS_CAL_TAG</name>
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<displayName>CS_CAL_TAG</displayName>
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<description>Clock System Calibration Tag</description>
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<addressOffset>0x44</addressOffset>
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<size>32</size>
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<access>read-only</access>
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<resetValue>0x00000003</resetValue>
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<resetMask>0xffffffff</resetMask>
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</register>
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<register>
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<name>CS_CAL_LEN</name>
|
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<displayName>CS_CAL_LEN</displayName>
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<description>Clock System Calibration Length</description>
|
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<addressOffset>0x48</addressOffset>
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<size>32</size>
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<access>read-only</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xffffffff</resetMask>
|
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</register>
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<register>
|
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<name>DCOIR_FCAL_RSEL04</name>
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<displayName>DCOIR_FCAL_RSEL04</displayName>
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|
<description>DCO IR mode: Frequency calibration for DCORSEL 0 to 4</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
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<register>
|
|
<name>DCOIR_FCAL_RSEL5</name>
|
|
<displayName>DCOIR_FCAL_RSEL5</displayName>
|
|
<description>DCO IR mode: Frequency calibration for DCORSEL 5</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RESERVED3</name>
|
|
<displayName>RESERVED3</displayName>
|
|
<description>Reserved</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RESERVED4</name>
|
|
<displayName>RESERVED4</displayName>
|
|
<description>Reserved</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RESERVED5</name>
|
|
<displayName>RESERVED5</displayName>
|
|
<description>Reserved</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RESERVED6</name>
|
|
<displayName>RESERVED6</displayName>
|
|
<description>Reserved</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>DCOIR_CONSTK_RSEL04</name>
|
|
<displayName>DCOIR_CONSTK_RSEL04</displayName>
|
|
<description>DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>DCOIR_CONSTK_RSEL5</name>
|
|
<displayName>DCOIR_CONSTK_RSEL5</displayName>
|
|
<description>DCO IR mode: DCO Constant (K) for DCORSEL 5</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>DCOER_FCAL_RSEL04</name>
|
|
<displayName>DCOER_FCAL_RSEL04</displayName>
|
|
<description>DCO ER mode: Frequency calibration for DCORSEL 0 to 4</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>DCOER_FCAL_RSEL5</name>
|
|
<displayName>DCOER_FCAL_RSEL5</displayName>
|
|
<description>DCO ER mode: Frequency calibration for DCORSEL 5</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RESERVED7</name>
|
|
<displayName>RESERVED7</displayName>
|
|
<description>Reserved</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RESERVED8</name>
|
|
<displayName>RESERVED8</displayName>
|
|
<description>Reserved</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RESERVED9</name>
|
|
<displayName>RESERVED9</displayName>
|
|
<description>Reserved</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RESERVED10</name>
|
|
<displayName>RESERVED10</displayName>
|
|
<description>Reserved</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>DCOER_CONSTK_RSEL04</name>
|
|
<displayName>DCOER_CONSTK_RSEL04</displayName>
|
|
<description>DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>DCOER_CONSTK_RSEL5</name>
|
|
<displayName>DCOER_CONSTK_RSEL5</displayName>
|
|
<description>DCO ER mode: DCO Constant (K) for DCORSEL 5</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>ADC14_CAL_TAG</name>
|
|
<displayName>ADC14_CAL_TAG</displayName>
|
|
<description>ADC14 Calibration Tag</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000005</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>ADC14_CAL_LEN</name>
|
|
<displayName>ADC14_CAL_LEN</displayName>
|
|
<description>ADC14 Calibration Length</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>ADC_GAIN_FACTOR</name>
|
|
<displayName>ADC_GAIN_FACTOR</displayName>
|
|
<description>ADC Gain Factor</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>ADC_OFFSET</name>
|
|
<displayName>ADC_OFFSET</displayName>
|
|
<description>ADC Offset</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RESERVED11</name>
|
|
<displayName>RESERVED11</displayName>
|
|
<description>Reserved</description>
|
|
<addressOffset>0x9C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RESERVED12</name>
|
|
<displayName>RESERVED12</displayName>
|
|
<description>Reserved</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RESERVED13</name>
|
|
<displayName>RESERVED13</displayName>
|
|
<description>Reserved</description>
|
|
<addressOffset>0xA4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RESERVED14</name>
|
|
<displayName>RESERVED14</displayName>
|
|
<description>Reserved</description>
|
|
<addressOffset>0xA8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RESERVED15</name>
|
|
<displayName>RESERVED15</displayName>
|
|
<description>Reserved</description>
|
|
<addressOffset>0xAC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RESERVED16</name>
|
|
<displayName>RESERVED16</displayName>
|
|
<description>Reserved</description>
|
|
<addressOffset>0xB0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RESERVED17</name>
|
|
<displayName>RESERVED17</displayName>
|
|
<description>Reserved</description>
|
|
<addressOffset>0xB4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RESERVED18</name>
|
|
<displayName>RESERVED18</displayName>
|
|
<description>Reserved</description>
|
|
<addressOffset>0xB8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RESERVED19</name>
|
|
<displayName>RESERVED19</displayName>
|
|
<description>Reserved</description>
|
|
<addressOffset>0xBC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RESERVED20</name>
|
|
<displayName>RESERVED20</displayName>
|
|
<description>Reserved</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RESERVED21</name>
|
|
<displayName>RESERVED21</displayName>
|
|
<description>Reserved</description>
|
|
<addressOffset>0xC4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RESERVED22</name>
|
|
<displayName>RESERVED22</displayName>
|
|
<description>Reserved</description>
|
|
<addressOffset>0xC8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RESERVED23</name>
|
|
<displayName>RESERVED23</displayName>
|
|
<description>Reserved</description>
|
|
<addressOffset>0xCC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RESERVED24</name>
|
|
<displayName>RESERVED24</displayName>
|
|
<description>Reserved</description>
|
|
<addressOffset>0xD0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RESERVED25</name>
|
|
<displayName>RESERVED25</displayName>
|
|
<description>Reserved</description>
|
|
<addressOffset>0xD4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RESERVED26</name>
|
|
<displayName>RESERVED26</displayName>
|
|
<description>Reserved</description>
|
|
<addressOffset>0xD8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>ADC14_REF1P2V_TS30C</name>
|
|
<displayName>ADC14_REF1P2V_TS30C</displayName>
|
|
<description>ADC14 1.2V Reference Temp. Sensor 30C</description>
|
|
<addressOffset>0xDC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>ADC14_REF1P2V_TS85C</name>
|
|
<displayName>ADC14_REF1P2V_TS85C</displayName>
|
|
<description>ADC14 1.2V Reference Temp. Sensor 85C</description>
|
|
<addressOffset>0xE0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>ADC14_REF1P45V_TS30C</name>
|
|
<displayName>ADC14_REF1P45V_TS30C</displayName>
|
|
<description>ADC14 1.45V Reference Temp. Sensor 30C</description>
|
|
<addressOffset>0xE4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>ADC14_REF1P45V_TS85C</name>
|
|
<displayName>ADC14_REF1P45V_TS85C</displayName>
|
|
<description>ADC14 1.45V Reference Temp. Sensor 85C</description>
|
|
<addressOffset>0xE8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>ADC14_REF2P5V_TS30C</name>
|
|
<displayName>ADC14_REF2P5V_TS30C</displayName>
|
|
<description>ADC14 2.5V Reference Temp. Sensor 30C</description>
|
|
<addressOffset>0xEC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>ADC14_REF2P5V_TS85C</name>
|
|
<displayName>ADC14_REF2P5V_TS85C</displayName>
|
|
<description>ADC14 2.5V Reference Temp. Sensor 85C</description>
|
|
<addressOffset>0xF0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>REF_CAL_TAG</name>
|
|
<displayName>REF_CAL_TAG</displayName>
|
|
<description>REF Calibration Tag</description>
|
|
<addressOffset>0xF4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000008</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>REF_CAL_LEN</name>
|
|
<displayName>REF_CAL_LEN</displayName>
|
|
<description>REF Calibration Length</description>
|
|
<addressOffset>0xF8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>REF_1P2V</name>
|
|
<displayName>REF_1P2V</displayName>
|
|
<description>REF 1.2V Reference</description>
|
|
<addressOffset>0xFC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>REF_1P45V</name>
|
|
<displayName>REF_1P45V</displayName>
|
|
<description>REF 1.45V Reference</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>REF_2P5V</name>
|
|
<displayName>REF_2P5V</displayName>
|
|
<description>REF 2.5V Reference</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>FLASH_INFO_TAG</name>
|
|
<displayName>FLASH_INFO_TAG</displayName>
|
|
<description>Flash Info Tag</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000004</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>FLASH_INFO_LEN</name>
|
|
<displayName>FLASH_INFO_LEN</displayName>
|
|
<description>Flash Info Length</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>FLASH_MAX_PROG_PULSES</name>
|
|
<displayName>FLASH_MAX_PROG_PULSES</displayName>
|
|
<description>Flash Maximum Programming Pulses</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>FLASH_MAX_ERASE_PULSES</name>
|
|
<displayName>FLASH_MAX_ERASE_PULSES</displayName>
|
|
<description>Flash Maximum Erase Pulses</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RANDOM_NUM_TAG</name>
|
|
<displayName>RANDOM_NUM_TAG</displayName>
|
|
<description>128-bit Random Number Tag</description>
|
|
<addressOffset>0x118</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000000d</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RANDOM_NUM_LEN</name>
|
|
<displayName>RANDOM_NUM_LEN</displayName>
|
|
<description>128-bit Random Number Length</description>
|
|
<addressOffset>0x11C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RANDOM_NUM_1</name>
|
|
<displayName>RANDOM_NUM_1</displayName>
|
|
<description>32-bit Random Number 1</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RANDOM_NUM_2</name>
|
|
<displayName>RANDOM_NUM_2</displayName>
|
|
<description>32-bit Random Number 2</description>
|
|
<addressOffset>0x124</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RANDOM_NUM_3</name>
|
|
<displayName>RANDOM_NUM_3</displayName>
|
|
<description>32-bit Random Number 3</description>
|
|
<addressOffset>0x128</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RANDOM_NUM_4</name>
|
|
<displayName>RANDOM_NUM_4</displayName>
|
|
<description>32-bit Random Number 4</description>
|
|
<addressOffset>0x12C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>BSL_CFG_TAG</name>
|
|
<displayName>BSL_CFG_TAG</displayName>
|
|
<description>BSL Configuration Tag</description>
|
|
<addressOffset>0x130</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000000f</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>BSL_CFG_LEN</name>
|
|
<displayName>BSL_CFG_LEN</displayName>
|
|
<description>BSL Configuration Length</description>
|
|
<addressOffset>0x134</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>BSL_PERIPHIF_SEL</name>
|
|
<displayName>BSL_PERIPHIF_SEL</displayName>
|
|
<description>BSL Peripheral Interface Selection</description>
|
|
<addressOffset>0x138</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>BSL_PORTIF_CFG_UART</name>
|
|
<displayName>BSL_PORTIF_CFG_UART</displayName>
|
|
<description>BSL Port Interface Configuration for UART</description>
|
|
<addressOffset>0x13C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>BSL_PORTIF_CFG_SPI</name>
|
|
<displayName>BSL_PORTIF_CFG_SPI</displayName>
|
|
<description>BSL Port Interface Configuration for SPI</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>BSL_PORTIF_CFG_I2C</name>
|
|
<displayName>BSL_PORTIF_CFG_I2C</displayName>
|
|
<description>BSL Port Interface Configuration for I2C</description>
|
|
<addressOffset>0x144</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>TLV_END</name>
|
|
<displayName>TLV_END</displayName>
|
|
<description>TLV End Word</description>
|
|
<addressOffset>0x148</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0bd0e11d</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIMER_A0</name>
|
|
<version>356.0</version>
|
|
<description>TIMER_A0</description>
|
|
<baseAddress>0x40000000</baseAddress>
|
|
<interrupt>
|
|
<name>TA0_0_IRQ</name>
|
|
<description>TA0_0 Interrupt</description>
|
|
<value>8</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TA0_N_IRQ</name>
|
|
<description>TA0_N Interrupt</description>
|
|
<value>9</value>
|
|
</interrupt>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x30</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>TAxCTL</name>
|
|
<displayName>CTL</displayName>
|
|
<description>TimerAx Control Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TAIFG</name>
|
|
<description>TimerA interrupt flag</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TAIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAIE</name>
|
|
<description>TimerA interrupt enable</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TAIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TACLR</name>
|
|
<description>TimerA clear</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MC</name>
|
|
<description>Mode control</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MC_0</name>
|
|
<description>Stop mode: Timer is halted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MC_1</name>
|
|
<description>Up mode: Timer counts up to TAxCCR0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MC_2</name>
|
|
<description>Continuous mode: Timer counts up to 0FFFFh</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MC_3</name>
|
|
<description>Up/down mode: Timer counts up to TAxCCR0 then down to 0000h</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ID</name>
|
|
<description>Input divider</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ID_0</name>
|
|
<description>/1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ID_1</name>
|
|
<description>/2</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ID_2</name>
|
|
<description>/4</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ID_3</name>
|
|
<description>/8</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TASSEL</name>
|
|
<description>TimerA clock source select</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TASSEL_0</name>
|
|
<description>TAxCLK</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TASSEL_1</name>
|
|
<description>ACLK</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TASSEL_2</name>
|
|
<description>SMCLK</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TASSEL_3</name>
|
|
<description>INCLK</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>5</dim>
|
|
<dimIncrement>2</dimIncrement>
|
|
<dimIndex>0,1,2,3,4</dimIndex>
|
|
<name>TAxCCTL[%s]</name>
|
|
<displayName>CCTL[%s]</displayName>
|
|
<description>Timer_A Capture/Compare Control Register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000fff7</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCIFG</name>
|
|
<description>Capture/compare interrupt flag</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CCIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CCIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COV</name>
|
|
<description>Capture overflow</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COV_0</name>
|
|
<description>No capture overflow occurred</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COV_1</name>
|
|
<description>Capture overflow occurred</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUT</name>
|
|
<description>Output</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUT_0</name>
|
|
<description>Output low</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUT_1</name>
|
|
<description>Output high</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCI</name>
|
|
<description>Capture/compare input</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCIE</name>
|
|
<description>Capture/compare interrupt enable</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CCIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CCIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTMOD</name>
|
|
<description>Output mode</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_0</name>
|
|
<description>OUT bit value</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_1</name>
|
|
<description>Set</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_2</name>
|
|
<description>Toggle/reset</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_3</name>
|
|
<description>Set/reset</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_4</name>
|
|
<description>Toggle</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_5</name>
|
|
<description>Reset</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_6</name>
|
|
<description>Toggle/set</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_7</name>
|
|
<description>Reset/set</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP</name>
|
|
<description>Capture mode</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAP_0</name>
|
|
<description>Compare mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAP_1</name>
|
|
<description>Capture mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCCI</name>
|
|
<description>Synchronized capture/compare input</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCS</name>
|
|
<description>Synchronize capture source</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SCS_0</name>
|
|
<description>Asynchronous capture</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCS_1</name>
|
|
<description>Synchronous capture</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCIS</name>
|
|
<description>Capture/compare input select</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CCIS_0</name>
|
|
<description>CCIxA</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CCIS_1</name>
|
|
<description>CCIxB</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CCIS_2</name>
|
|
<description>GND</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CCIS_3</name>
|
|
<description>VCC</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CM</name>
|
|
<description>Capture mode</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CM_0</name>
|
|
<description>No capture</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM_1</name>
|
|
<description>Capture on rising edge</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM_2</name>
|
|
<description>Capture on falling edge</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM_3</name>
|
|
<description>Capture on both rising and falling edges</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAxR</name>
|
|
<displayName>R</displayName>
|
|
<description>TimerA register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<dim>5</dim>
|
|
<dimIncrement>2</dimIncrement>
|
|
<dimIndex>0,1,2,3,4</dimIndex>
|
|
<name>TAxCCR[%s]</name>
|
|
<displayName>CCR[%s]</displayName>
|
|
<description>Timer_A Capture/Compare Register</description>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TAxR</name>
|
|
<description>TimerA register</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAxEX0</name>
|
|
<displayName>EX0</displayName>
|
|
<description>TimerAx Expansion 0 Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TAIDEX</name>
|
|
<description>Input divider expansion</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_0</name>
|
|
<description>Divide by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_1</name>
|
|
<description>Divide by 2</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_2</name>
|
|
<description>Divide by 3</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_3</name>
|
|
<description>Divide by 4</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_4</name>
|
|
<description>Divide by 5</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_5</name>
|
|
<description>Divide by 6</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_6</name>
|
|
<description>Divide by 7</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_7</name>
|
|
<description>Divide by 8</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAxIV</name>
|
|
<displayName>IV</displayName>
|
|
<description>TimerAx Interrupt Vector Register</description>
|
|
<addressOffset>0x2E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TAIV</name>
|
|
<description>TimerA interrupt vector value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>TAIV_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>TAIV_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIV_2</name>
|
|
<description>Interrupt Source: Capture/compare 1; Interrupt Flag: TAxCCR1 CCIFG; Interrupt Priority: Highest</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIV_4</name>
|
|
<description>Interrupt Source: Capture/compare 2; Interrupt Flag: TAxCCR2 CCIFG</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIV_6</name>
|
|
<description>Interrupt Source: Capture/compare 3; Interrupt Flag: TAxCCR3 CCIFG</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIV_8</name>
|
|
<description>Interrupt Source: Capture/compare 4; Interrupt Flag: TAxCCR4 CCIFG</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIV_10</name>
|
|
<description>Interrupt Source: Capture/compare 5; Interrupt Flag: TAxCCR5 CCIFG</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIV_12</name>
|
|
<description>Interrupt Source: Capture/compare 6; Interrupt Flag: TAxCCR6 CCIFG</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIV_14</name>
|
|
<description>Interrupt Source: Timer overflow; Interrupt Flag: TAxCTL TAIFG; Interrupt Priority: Lowest</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIMER_A1</name>
|
|
<version>356.0</version>
|
|
<description>TIMER_A1</description>
|
|
<baseAddress>0x40000400</baseAddress>
|
|
<interrupt>
|
|
<name>TA1_0_IRQ</name>
|
|
<description>TA1_0 Interrupt</description>
|
|
<value>10</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TA1_N_IRQ</name>
|
|
<description>TA1_N Interrupt</description>
|
|
<value>11</value>
|
|
</interrupt>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x30</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>TAxCTL</name>
|
|
<displayName>CTL</displayName>
|
|
<description>TimerAx Control Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TAIFG</name>
|
|
<description>TimerA interrupt flag</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TAIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAIE</name>
|
|
<description>TimerA interrupt enable</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TAIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TACLR</name>
|
|
<description>TimerA clear</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MC</name>
|
|
<description>Mode control</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MC_0</name>
|
|
<description>Stop mode: Timer is halted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MC_1</name>
|
|
<description>Up mode: Timer counts up to TAxCCR0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MC_2</name>
|
|
<description>Continuous mode: Timer counts up to 0FFFFh</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MC_3</name>
|
|
<description>Up/down mode: Timer counts up to TAxCCR0 then down to 0000h</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ID</name>
|
|
<description>Input divider</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ID_0</name>
|
|
<description>/1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ID_1</name>
|
|
<description>/2</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ID_2</name>
|
|
<description>/4</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ID_3</name>
|
|
<description>/8</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TASSEL</name>
|
|
<description>TimerA clock source select</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TASSEL_0</name>
|
|
<description>TAxCLK</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TASSEL_1</name>
|
|
<description>ACLK</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TASSEL_2</name>
|
|
<description>SMCLK</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TASSEL_3</name>
|
|
<description>INCLK</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>5</dim>
|
|
<dimIncrement>2</dimIncrement>
|
|
<dimIndex>0,1,2,3,4</dimIndex>
|
|
<name>TAxCCTL[%s]</name>
|
|
<displayName>CCTL[%s]</displayName>
|
|
<description>Timer_A Capture/Compare Control Register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000fff7</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCIFG</name>
|
|
<description>Capture/compare interrupt flag</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CCIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CCIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COV</name>
|
|
<description>Capture overflow</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COV_0</name>
|
|
<description>No capture overflow occurred</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COV_1</name>
|
|
<description>Capture overflow occurred</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUT</name>
|
|
<description>Output</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUT_0</name>
|
|
<description>Output low</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUT_1</name>
|
|
<description>Output high</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCI</name>
|
|
<description>Capture/compare input</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCIE</name>
|
|
<description>Capture/compare interrupt enable</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CCIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CCIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTMOD</name>
|
|
<description>Output mode</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_0</name>
|
|
<description>OUT bit value</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_1</name>
|
|
<description>Set</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_2</name>
|
|
<description>Toggle/reset</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_3</name>
|
|
<description>Set/reset</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_4</name>
|
|
<description>Toggle</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_5</name>
|
|
<description>Reset</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_6</name>
|
|
<description>Toggle/set</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_7</name>
|
|
<description>Reset/set</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP</name>
|
|
<description>Capture mode</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAP_0</name>
|
|
<description>Compare mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAP_1</name>
|
|
<description>Capture mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCCI</name>
|
|
<description>Synchronized capture/compare input</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCS</name>
|
|
<description>Synchronize capture source</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SCS_0</name>
|
|
<description>Asynchronous capture</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCS_1</name>
|
|
<description>Synchronous capture</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCIS</name>
|
|
<description>Capture/compare input select</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CCIS_0</name>
|
|
<description>CCIxA</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CCIS_1</name>
|
|
<description>CCIxB</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CCIS_2</name>
|
|
<description>GND</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CCIS_3</name>
|
|
<description>VCC</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CM</name>
|
|
<description>Capture mode</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CM_0</name>
|
|
<description>No capture</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM_1</name>
|
|
<description>Capture on rising edge</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM_2</name>
|
|
<description>Capture on falling edge</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM_3</name>
|
|
<description>Capture on both rising and falling edges</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAxR</name>
|
|
<displayName>R</displayName>
|
|
<description>TimerA register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<dim>5</dim>
|
|
<dimIncrement>2</dimIncrement>
|
|
<dimIndex>0,1,2,3,4</dimIndex>
|
|
<name>TAxCCR[%s]</name>
|
|
<displayName>CCR[%s]</displayName>
|
|
<description>Timer_A Capture/Compare Register</description>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TAxR</name>
|
|
<description>TimerA register</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAxEX0</name>
|
|
<displayName>EX0</displayName>
|
|
<description>TimerAx Expansion 0 Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TAIDEX</name>
|
|
<description>Input divider expansion</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_0</name>
|
|
<description>Divide by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_1</name>
|
|
<description>Divide by 2</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_2</name>
|
|
<description>Divide by 3</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_3</name>
|
|
<description>Divide by 4</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_4</name>
|
|
<description>Divide by 5</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_5</name>
|
|
<description>Divide by 6</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_6</name>
|
|
<description>Divide by 7</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_7</name>
|
|
<description>Divide by 8</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAxIV</name>
|
|
<displayName>IV</displayName>
|
|
<description>TimerAx Interrupt Vector Register</description>
|
|
<addressOffset>0x2E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TAIV</name>
|
|
<description>TimerA interrupt vector value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>TAIV_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>TAIV_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIV_2</name>
|
|
<description>Interrupt Source: Capture/compare 1; Interrupt Flag: TAxCCR1 CCIFG; Interrupt Priority: Highest</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIV_4</name>
|
|
<description>Interrupt Source: Capture/compare 2; Interrupt Flag: TAxCCR2 CCIFG</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIV_6</name>
|
|
<description>Interrupt Source: Capture/compare 3; Interrupt Flag: TAxCCR3 CCIFG</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIV_8</name>
|
|
<description>Interrupt Source: Capture/compare 4; Interrupt Flag: TAxCCR4 CCIFG</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIV_10</name>
|
|
<description>Interrupt Source: Capture/compare 5; Interrupt Flag: TAxCCR5 CCIFG</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIV_12</name>
|
|
<description>Interrupt Source: Capture/compare 6; Interrupt Flag: TAxCCR6 CCIFG</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIV_14</name>
|
|
<description>Interrupt Source: Timer overflow; Interrupt Flag: TAxCTL TAIFG; Interrupt Priority: Lowest</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIMER_A2</name>
|
|
<version>356.0</version>
|
|
<description>TIMER_A2</description>
|
|
<baseAddress>0x40000800</baseAddress>
|
|
<interrupt>
|
|
<name>TA2_0_IRQ</name>
|
|
<description>TA2_0 Interrupt</description>
|
|
<value>12</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TA2_N_IRQ</name>
|
|
<description>TA2_N Interrupt</description>
|
|
<value>13</value>
|
|
</interrupt>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x30</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>TAxCTL</name>
|
|
<displayName>CTL</displayName>
|
|
<description>TimerAx Control Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TAIFG</name>
|
|
<description>TimerA interrupt flag</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TAIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAIE</name>
|
|
<description>TimerA interrupt enable</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TAIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TACLR</name>
|
|
<description>TimerA clear</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MC</name>
|
|
<description>Mode control</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MC_0</name>
|
|
<description>Stop mode: Timer is halted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MC_1</name>
|
|
<description>Up mode: Timer counts up to TAxCCR0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MC_2</name>
|
|
<description>Continuous mode: Timer counts up to 0FFFFh</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MC_3</name>
|
|
<description>Up/down mode: Timer counts up to TAxCCR0 then down to 0000h</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ID</name>
|
|
<description>Input divider</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ID_0</name>
|
|
<description>/1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ID_1</name>
|
|
<description>/2</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ID_2</name>
|
|
<description>/4</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ID_3</name>
|
|
<description>/8</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TASSEL</name>
|
|
<description>TimerA clock source select</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TASSEL_0</name>
|
|
<description>TAxCLK</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TASSEL_1</name>
|
|
<description>ACLK</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TASSEL_2</name>
|
|
<description>SMCLK</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TASSEL_3</name>
|
|
<description>INCLK</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>5</dim>
|
|
<dimIncrement>2</dimIncrement>
|
|
<dimIndex>0,1,2,3,4</dimIndex>
|
|
<name>TAxCCTL[%s]</name>
|
|
<displayName>CCTL[%s]</displayName>
|
|
<description>Timer_A Capture/Compare Control Register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000fff7</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCIFG</name>
|
|
<description>Capture/compare interrupt flag</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CCIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CCIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COV</name>
|
|
<description>Capture overflow</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COV_0</name>
|
|
<description>No capture overflow occurred</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COV_1</name>
|
|
<description>Capture overflow occurred</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUT</name>
|
|
<description>Output</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUT_0</name>
|
|
<description>Output low</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUT_1</name>
|
|
<description>Output high</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCI</name>
|
|
<description>Capture/compare input</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCIE</name>
|
|
<description>Capture/compare interrupt enable</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CCIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CCIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTMOD</name>
|
|
<description>Output mode</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_0</name>
|
|
<description>OUT bit value</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_1</name>
|
|
<description>Set</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_2</name>
|
|
<description>Toggle/reset</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_3</name>
|
|
<description>Set/reset</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_4</name>
|
|
<description>Toggle</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_5</name>
|
|
<description>Reset</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_6</name>
|
|
<description>Toggle/set</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_7</name>
|
|
<description>Reset/set</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP</name>
|
|
<description>Capture mode</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAP_0</name>
|
|
<description>Compare mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAP_1</name>
|
|
<description>Capture mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCCI</name>
|
|
<description>Synchronized capture/compare input</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCS</name>
|
|
<description>Synchronize capture source</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SCS_0</name>
|
|
<description>Asynchronous capture</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCS_1</name>
|
|
<description>Synchronous capture</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCIS</name>
|
|
<description>Capture/compare input select</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CCIS_0</name>
|
|
<description>CCIxA</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CCIS_1</name>
|
|
<description>CCIxB</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CCIS_2</name>
|
|
<description>GND</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CCIS_3</name>
|
|
<description>VCC</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CM</name>
|
|
<description>Capture mode</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CM_0</name>
|
|
<description>No capture</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM_1</name>
|
|
<description>Capture on rising edge</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM_2</name>
|
|
<description>Capture on falling edge</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM_3</name>
|
|
<description>Capture on both rising and falling edges</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAxR</name>
|
|
<displayName>R</displayName>
|
|
<description>TimerA register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<dim>5</dim>
|
|
<dimIncrement>2</dimIncrement>
|
|
<dimIndex>0,1,2,3,4</dimIndex>
|
|
<name>TAxCCR[%s]</name>
|
|
<displayName>CCR[%s]</displayName>
|
|
<description>Timer_A Capture/Compare Register</description>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TAxR</name>
|
|
<description>TimerA register</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAxEX0</name>
|
|
<displayName>EX0</displayName>
|
|
<description>TimerAx Expansion 0 Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TAIDEX</name>
|
|
<description>Input divider expansion</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_0</name>
|
|
<description>Divide by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_1</name>
|
|
<description>Divide by 2</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_2</name>
|
|
<description>Divide by 3</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_3</name>
|
|
<description>Divide by 4</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_4</name>
|
|
<description>Divide by 5</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_5</name>
|
|
<description>Divide by 6</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_6</name>
|
|
<description>Divide by 7</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_7</name>
|
|
<description>Divide by 8</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAxIV</name>
|
|
<displayName>IV</displayName>
|
|
<description>TimerAx Interrupt Vector Register</description>
|
|
<addressOffset>0x2E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TAIV</name>
|
|
<description>TimerA interrupt vector value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>TAIV_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>TAIV_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIV_2</name>
|
|
<description>Interrupt Source: Capture/compare 1; Interrupt Flag: TAxCCR1 CCIFG; Interrupt Priority: Highest</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIV_4</name>
|
|
<description>Interrupt Source: Capture/compare 2; Interrupt Flag: TAxCCR2 CCIFG</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIV_6</name>
|
|
<description>Interrupt Source: Capture/compare 3; Interrupt Flag: TAxCCR3 CCIFG</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIV_8</name>
|
|
<description>Interrupt Source: Capture/compare 4; Interrupt Flag: TAxCCR4 CCIFG</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIV_10</name>
|
|
<description>Interrupt Source: Capture/compare 5; Interrupt Flag: TAxCCR5 CCIFG</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIV_12</name>
|
|
<description>Interrupt Source: Capture/compare 6; Interrupt Flag: TAxCCR6 CCIFG</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIV_14</name>
|
|
<description>Interrupt Source: Timer overflow; Interrupt Flag: TAxCTL TAIFG; Interrupt Priority: Lowest</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIMER_A3</name>
|
|
<version>356.0</version>
|
|
<description>TIMER_A3</description>
|
|
<baseAddress>0x40000C00</baseAddress>
|
|
<interrupt>
|
|
<name>TA3_0_IRQ</name>
|
|
<description>TA3_0 Interrupt</description>
|
|
<value>14</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TA3_N_IRQ</name>
|
|
<description>TA3_N Interrupt</description>
|
|
<value>15</value>
|
|
</interrupt>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x30</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>TAxCTL</name>
|
|
<displayName>CTL</displayName>
|
|
<description>TimerAx Control Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TAIFG</name>
|
|
<description>TimerA interrupt flag</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TAIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAIE</name>
|
|
<description>TimerA interrupt enable</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TAIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TACLR</name>
|
|
<description>TimerA clear</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MC</name>
|
|
<description>Mode control</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MC_0</name>
|
|
<description>Stop mode: Timer is halted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MC_1</name>
|
|
<description>Up mode: Timer counts up to TAxCCR0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MC_2</name>
|
|
<description>Continuous mode: Timer counts up to 0FFFFh</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MC_3</name>
|
|
<description>Up/down mode: Timer counts up to TAxCCR0 then down to 0000h</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ID</name>
|
|
<description>Input divider</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ID_0</name>
|
|
<description>/1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ID_1</name>
|
|
<description>/2</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ID_2</name>
|
|
<description>/4</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ID_3</name>
|
|
<description>/8</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TASSEL</name>
|
|
<description>TimerA clock source select</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TASSEL_0</name>
|
|
<description>TAxCLK</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TASSEL_1</name>
|
|
<description>ACLK</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TASSEL_2</name>
|
|
<description>SMCLK</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TASSEL_3</name>
|
|
<description>INCLK</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>5</dim>
|
|
<dimIncrement>2</dimIncrement>
|
|
<dimIndex>0,1,2,3,4</dimIndex>
|
|
<name>TAxCCTL[%s]</name>
|
|
<displayName>CCTL[%s]</displayName>
|
|
<description>Timer_A Capture/Compare Control Register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000fff7</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCIFG</name>
|
|
<description>Capture/compare interrupt flag</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CCIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CCIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COV</name>
|
|
<description>Capture overflow</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COV_0</name>
|
|
<description>No capture overflow occurred</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COV_1</name>
|
|
<description>Capture overflow occurred</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUT</name>
|
|
<description>Output</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUT_0</name>
|
|
<description>Output low</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUT_1</name>
|
|
<description>Output high</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCI</name>
|
|
<description>Capture/compare input</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCIE</name>
|
|
<description>Capture/compare interrupt enable</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CCIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CCIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTMOD</name>
|
|
<description>Output mode</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_0</name>
|
|
<description>OUT bit value</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_1</name>
|
|
<description>Set</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_2</name>
|
|
<description>Toggle/reset</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_3</name>
|
|
<description>Set/reset</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_4</name>
|
|
<description>Toggle</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_5</name>
|
|
<description>Reset</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_6</name>
|
|
<description>Toggle/set</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTMOD_7</name>
|
|
<description>Reset/set</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP</name>
|
|
<description>Capture mode</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAP_0</name>
|
|
<description>Compare mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAP_1</name>
|
|
<description>Capture mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCCI</name>
|
|
<description>Synchronized capture/compare input</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCS</name>
|
|
<description>Synchronize capture source</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SCS_0</name>
|
|
<description>Asynchronous capture</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCS_1</name>
|
|
<description>Synchronous capture</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCIS</name>
|
|
<description>Capture/compare input select</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CCIS_0</name>
|
|
<description>CCIxA</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CCIS_1</name>
|
|
<description>CCIxB</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CCIS_2</name>
|
|
<description>GND</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CCIS_3</name>
|
|
<description>VCC</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CM</name>
|
|
<description>Capture mode</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CM_0</name>
|
|
<description>No capture</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM_1</name>
|
|
<description>Capture on rising edge</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM_2</name>
|
|
<description>Capture on falling edge</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM_3</name>
|
|
<description>Capture on both rising and falling edges</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAxR</name>
|
|
<displayName>R</displayName>
|
|
<description>TimerA register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<dim>5</dim>
|
|
<dimIncrement>2</dimIncrement>
|
|
<dimIndex>0,1,2,3,4</dimIndex>
|
|
<name>TAxCCR[%s]</name>
|
|
<displayName>CCR[%s]</displayName>
|
|
<description>Timer_A Capture/Compare Register</description>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TAxR</name>
|
|
<description>TimerA register</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAxEX0</name>
|
|
<displayName>EX0</displayName>
|
|
<description>TimerAx Expansion 0 Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TAIDEX</name>
|
|
<description>Input divider expansion</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_0</name>
|
|
<description>Divide by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_1</name>
|
|
<description>Divide by 2</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_2</name>
|
|
<description>Divide by 3</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_3</name>
|
|
<description>Divide by 4</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_4</name>
|
|
<description>Divide by 5</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_5</name>
|
|
<description>Divide by 6</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_6</name>
|
|
<description>Divide by 7</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIDEX_7</name>
|
|
<description>Divide by 8</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAxIV</name>
|
|
<displayName>IV</displayName>
|
|
<description>TimerAx Interrupt Vector Register</description>
|
|
<addressOffset>0x2E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TAIV</name>
|
|
<description>TimerA interrupt vector value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>TAIV_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>TAIV_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIV_2</name>
|
|
<description>Interrupt Source: Capture/compare 1; Interrupt Flag: TAxCCR1 CCIFG; Interrupt Priority: Highest</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIV_4</name>
|
|
<description>Interrupt Source: Capture/compare 2; Interrupt Flag: TAxCCR2 CCIFG</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIV_6</name>
|
|
<description>Interrupt Source: Capture/compare 3; Interrupt Flag: TAxCCR3 CCIFG</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIV_8</name>
|
|
<description>Interrupt Source: Capture/compare 4; Interrupt Flag: TAxCCR4 CCIFG</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIV_10</name>
|
|
<description>Interrupt Source: Capture/compare 5; Interrupt Flag: TAxCCR5 CCIFG</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIV_12</name>
|
|
<description>Interrupt Source: Capture/compare 6; Interrupt Flag: TAxCCR6 CCIFG</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIV_14</name>
|
|
<description>Interrupt Source: Timer overflow; Interrupt Flag: TAxCTL TAIFG; Interrupt Priority: Lowest</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EUSCI_A0</name>
|
|
<version>356.0</version>
|
|
<description>EUSCI_A0</description>
|
|
<baseAddress>0x40001000</baseAddress>
|
|
<interrupt>
|
|
<name>EUSCIA0_IRQ</name>
|
|
<description>EUSCIA0 Interrupt</description>
|
|
<value>16</value>
|
|
</interrupt>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>UCAxCTLW0</name>
|
|
<displayName>CTLW0</displayName>
|
|
<description>eUSCI_Ax Control Word Register 0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCSWRST</name>
|
|
<description>Software reset enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSWRST_0</name>
|
|
<description>Disabled. eUSCI_A reset released for operation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSWRST_1</name>
|
|
<description>Enabled. eUSCI_A logic held in reset state</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXBRK</name>
|
|
<description>Transmit break</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXBRK_0</name>
|
|
<description>Next frame transmitted is not a break</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXBRK_1</name>
|
|
<description>Next frame transmitted is a break or a break/synch</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXADDR</name>
|
|
<description>Transmit address</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXADDR_0</name>
|
|
<description>Next frame transmitted is data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXADDR_1</name>
|
|
<description>Next frame transmitted is an address</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCDORM</name>
|
|
<description>Dormant</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCDORM_0</name>
|
|
<description>Not dormant. All received characters set UCRXIFG.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCDORM_1</name>
|
|
<description>Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBRKIE</name>
|
|
<description>Receive break character interrupt enable</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCBRKIE_0</name>
|
|
<description>Received break characters do not set UCRXIFG</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBRKIE_1</name>
|
|
<description>Received break characters set UCRXIFG</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCRXEIE</name>
|
|
<description>Receive erroneous-character interrupt enable</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXEIE_0</name>
|
|
<description>Erroneous characters rejected and UCRXIFG is not set</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXEIE_1</name>
|
|
<description>Erroneous characters received set UCRXIFG</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSSEL</name>
|
|
<description>eUSCI_A clock source select</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSSEL_0</name>
|
|
<description>UCLK</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSSEL_1</name>
|
|
<description>ACLK</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSSEL_2</name>
|
|
<description>SMCLK</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSYNC</name>
|
|
<description>Synchronous mode enable</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSYNC_0</name>
|
|
<description>Asynchronous mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSYNC_1</name>
|
|
<description>Synchronous mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCMODE</name>
|
|
<description>eUSCI_A mode</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCMODE_0</name>
|
|
<description>UART mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMODE_1</name>
|
|
<description>Idle-line multiprocessor mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMODE_2</name>
|
|
<description>Address-bit multiprocessor mode</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMODE_3</name>
|
|
<description>UART mode with automatic baud-rate detection</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSPB</name>
|
|
<description>Stop bit select</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSPB_0</name>
|
|
<description>One stop bit</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSPB_1</name>
|
|
<description>Two stop bits</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UC7BIT</name>
|
|
<description>Character length</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UC7BIT_0</name>
|
|
<description>8-bit data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UC7BIT_1</name>
|
|
<description>7-bit data</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCMSB</name>
|
|
<description>MSB first select</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCMSB_0</name>
|
|
<description>LSB first</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMSB_1</name>
|
|
<description>MSB first</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCPAR</name>
|
|
<description>Parity select</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCPAR_0</name>
|
|
<description>Odd parity</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCPAR_1</name>
|
|
<description>Even parity</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCPEN</name>
|
|
<description>Parity enable</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCPEN_0</name>
|
|
<description>Parity disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCPEN_1</name>
|
|
<description>Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxCTLW1</name>
|
|
<displayName>CTLW1</displayName>
|
|
<description>eUSCI_Ax Control Word Register 1</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCGLIT</name>
|
|
<description>Deglitch time</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_0</name>
|
|
<description>Approximately 2 ns (equivalent of 1 delay element)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_1</name>
|
|
<description>Approximately 50 ns</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_2</name>
|
|
<description>Approximately 100 ns</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_3</name>
|
|
<description>Approximately 200 ns</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxBRW</name>
|
|
<displayName>BRW</displayName>
|
|
<description>eUSCI_Ax Baud Rate Control Word Register</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000ff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCBR</name>
|
|
<description>Clock prescaler setting of the Baud rate generator</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxMCTLW</name>
|
|
<displayName>MCTLW</displayName>
|
|
<description>eUSCI_Ax Modulation Control Word Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCOS16</name>
|
|
<description>Oversampling mode enabled</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCOS16_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCOS16_1</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBRF</name>
|
|
<description>First modulation stage select</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UCBRS</name>
|
|
<description>Second modulation stage select</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxSTATW</name>
|
|
<displayName>STATW</displayName>
|
|
<description>eUSCI_Ax Status Register</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCBUSY</name>
|
|
<description>eUSCI_A busy</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>UCBUSY_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>UCBUSY_0</name>
|
|
<description>eUSCI_A inactive</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBUSY_1</name>
|
|
<description>eUSCI_A transmitting or receiving</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCADDR_UCIDLE</name>
|
|
<description>Address received / Idle line detected</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UCRXERR</name>
|
|
<description>Receive error flag</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXERR_0</name>
|
|
<description>No receive errors detected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXERR_1</name>
|
|
<description>Receive error detected</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBRK</name>
|
|
<description>Break detect flag</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCBRK_0</name>
|
|
<description>No break condition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBRK_1</name>
|
|
<description>Break condition occurred</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCPE</name>
|
|
<description>Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read.</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCPE_0</name>
|
|
<description>No error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCPE_1</name>
|
|
<description>Character received with parity error</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCOE</name>
|
|
<description>Overrun error flag</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCOE_0</name>
|
|
<description>No error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCOE_1</name>
|
|
<description>Overrun error occurred</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCFE</name>
|
|
<description>Framing error flag</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCFE_0</name>
|
|
<description>No error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCFE_1</name>
|
|
<description>Character received with low stop bit</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCLISTEN</name>
|
|
<description>Listen enable</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCLISTEN_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCLISTEN_1</name>
|
|
<description>Enabled. UCAxTXD is internally fed back to the receiver</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxRXBUF</name>
|
|
<displayName>RXBUF</displayName>
|
|
<description>eUSCI_Ax Receive Buffer Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCRXBUF</name>
|
|
<description>Receive data buffer</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxTXBUF</name>
|
|
<displayName>TXBUF</displayName>
|
|
<description>eUSCI_Ax Transmit Buffer Register</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCTXBUF</name>
|
|
<description>Transmit data buffer</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxABCTL</name>
|
|
<displayName>ABCTL</displayName>
|
|
<description>eUSCI_Ax Auto Baud Rate Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCABDEN</name>
|
|
<description>Automatic baud-rate detect enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCABDEN_0</name>
|
|
<description>Baud-rate detection disabled. Length of break and synch field is not measured.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCABDEN_1</name>
|
|
<description>Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBTOE</name>
|
|
<description>Break time out error</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCBTOE_0</name>
|
|
<description>No error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBTOE_1</name>
|
|
<description>Length of break field exceeded 22 bit times</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTOE</name>
|
|
<description>Synch field time out error</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTOE_0</name>
|
|
<description>No error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTOE_1</name>
|
|
<description>Length of synch field exceeded measurable time</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCDELIM</name>
|
|
<description>Break/synch delimiter length</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCDELIM_0</name>
|
|
<description>1 bit time</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCDELIM_1</name>
|
|
<description>2 bit times</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCDELIM_2</name>
|
|
<description>3 bit times</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCDELIM_3</name>
|
|
<description>4 bit times</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxIRCTL</name>
|
|
<displayName>IRCTL</displayName>
|
|
<description>eUSCI_Ax IrDA Control Word Register</description>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCIREN</name>
|
|
<description>IrDA encoder/decoder enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCIREN_0</name>
|
|
<description>IrDA encoder/decoder disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIREN_1</name>
|
|
<description>IrDA encoder/decoder enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCIRTXCLK</name>
|
|
<description>IrDA transmit pulse clock select</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCIRTXCLK_0</name>
|
|
<description>BRCLK</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIRTXCLK_1</name>
|
|
<description>BITCLK16 when UCOS16 = 1. Otherwise, BRCLK.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCIRTXPL</name>
|
|
<description>Transmit pulse length</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UCIRRXFE</name>
|
|
<description>IrDA receive filter enabled</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCIRRXFE_0</name>
|
|
<description>Receive filter disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIRRXFE_1</name>
|
|
<description>Receive filter enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCIRRXPL</name>
|
|
<description>IrDA receive input UCAxRXD polarity</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCIRRXPL_0</name>
|
|
<description>IrDA transceiver delivers a high pulse when a light pulse is seen</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIRRXPL_1</name>
|
|
<description>IrDA transceiver delivers a low pulse when a light pulse is seen</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCIRRXFL</name>
|
|
<description>Receive filter length</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxIE</name>
|
|
<displayName>IE</displayName>
|
|
<description>eUSCI_Ax Interrupt Enable Register</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCRXIE</name>
|
|
<description>Receive interrupt enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIE</name>
|
|
<description>Transmit interrupt enable</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTTIE</name>
|
|
<description>Start bit interrupt enable</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTTIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTTIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXCPTIE</name>
|
|
<description>Transmit complete interrupt enable</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXCPTIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXCPTIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxIFG</name>
|
|
<displayName>IFG</displayName>
|
|
<description>eUSCI_Ax Interrupt Flag Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000002</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCRXIFG</name>
|
|
<description>Receive interrupt flag</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIFG</name>
|
|
<description>Transmit interrupt flag</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTTIFG</name>
|
|
<description>Start bit interrupt flag</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTTIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTTIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXCPTIFG</name>
|
|
<description>Transmit ready interrupt enable</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXCPTIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXCPTIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxIV</name>
|
|
<displayName>IV</displayName>
|
|
<description>eUSCI_Ax Interrupt Vector Register</description>
|
|
<addressOffset>0x1E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCIV</name>
|
|
<description>eUSCI_A interrupt vector value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>UCIV_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>UCIV_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_2</name>
|
|
<description>Interrupt Source: Receive buffer full; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_4</name>
|
|
<description>Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_6</name>
|
|
<description>Interrupt Source: Start bit received; Interrupt Flag: UCSTTIFG</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_8</name>
|
|
<description>Interrupt Source: Transmit complete; Interrupt Flag: UCTXCPTIFG; Interrupt Priority: Lowest</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EUSCI_A1</name>
|
|
<version>356.0</version>
|
|
<description>EUSCI_A1</description>
|
|
<baseAddress>0x40001400</baseAddress>
|
|
<interrupt>
|
|
<name>EUSCIA1_IRQ</name>
|
|
<description>EUSCIA1 Interrupt</description>
|
|
<value>17</value>
|
|
</interrupt>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>UCAxCTLW0</name>
|
|
<displayName>CTLW0</displayName>
|
|
<description>eUSCI_Ax Control Word Register 0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCSWRST</name>
|
|
<description>Software reset enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSWRST_0</name>
|
|
<description>Disabled. eUSCI_A reset released for operation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSWRST_1</name>
|
|
<description>Enabled. eUSCI_A logic held in reset state</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXBRK</name>
|
|
<description>Transmit break</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXBRK_0</name>
|
|
<description>Next frame transmitted is not a break</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXBRK_1</name>
|
|
<description>Next frame transmitted is a break or a break/synch</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXADDR</name>
|
|
<description>Transmit address</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXADDR_0</name>
|
|
<description>Next frame transmitted is data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXADDR_1</name>
|
|
<description>Next frame transmitted is an address</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCDORM</name>
|
|
<description>Dormant</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCDORM_0</name>
|
|
<description>Not dormant. All received characters set UCRXIFG.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCDORM_1</name>
|
|
<description>Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBRKIE</name>
|
|
<description>Receive break character interrupt enable</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCBRKIE_0</name>
|
|
<description>Received break characters do not set UCRXIFG</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBRKIE_1</name>
|
|
<description>Received break characters set UCRXIFG</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCRXEIE</name>
|
|
<description>Receive erroneous-character interrupt enable</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXEIE_0</name>
|
|
<description>Erroneous characters rejected and UCRXIFG is not set</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXEIE_1</name>
|
|
<description>Erroneous characters received set UCRXIFG</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSSEL</name>
|
|
<description>eUSCI_A clock source select</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSSEL_0</name>
|
|
<description>UCLK</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSSEL_1</name>
|
|
<description>ACLK</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSSEL_2</name>
|
|
<description>SMCLK</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSYNC</name>
|
|
<description>Synchronous mode enable</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSYNC_0</name>
|
|
<description>Asynchronous mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSYNC_1</name>
|
|
<description>Synchronous mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCMODE</name>
|
|
<description>eUSCI_A mode</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCMODE_0</name>
|
|
<description>UART mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMODE_1</name>
|
|
<description>Idle-line multiprocessor mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMODE_2</name>
|
|
<description>Address-bit multiprocessor mode</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMODE_3</name>
|
|
<description>UART mode with automatic baud-rate detection</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSPB</name>
|
|
<description>Stop bit select</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSPB_0</name>
|
|
<description>One stop bit</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSPB_1</name>
|
|
<description>Two stop bits</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UC7BIT</name>
|
|
<description>Character length</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UC7BIT_0</name>
|
|
<description>8-bit data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UC7BIT_1</name>
|
|
<description>7-bit data</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCMSB</name>
|
|
<description>MSB first select</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCMSB_0</name>
|
|
<description>LSB first</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMSB_1</name>
|
|
<description>MSB first</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCPAR</name>
|
|
<description>Parity select</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCPAR_0</name>
|
|
<description>Odd parity</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCPAR_1</name>
|
|
<description>Even parity</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCPEN</name>
|
|
<description>Parity enable</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCPEN_0</name>
|
|
<description>Parity disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCPEN_1</name>
|
|
<description>Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxCTLW1</name>
|
|
<displayName>CTLW1</displayName>
|
|
<description>eUSCI_Ax Control Word Register 1</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCGLIT</name>
|
|
<description>Deglitch time</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_0</name>
|
|
<description>Approximately 2 ns (equivalent of 1 delay element)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_1</name>
|
|
<description>Approximately 50 ns</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_2</name>
|
|
<description>Approximately 100 ns</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_3</name>
|
|
<description>Approximately 200 ns</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxBRW</name>
|
|
<displayName>BRW</displayName>
|
|
<description>eUSCI_Ax Baud Rate Control Word Register</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000ff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCBR</name>
|
|
<description>Clock prescaler setting of the Baud rate generator</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxMCTLW</name>
|
|
<displayName>MCTLW</displayName>
|
|
<description>eUSCI_Ax Modulation Control Word Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCOS16</name>
|
|
<description>Oversampling mode enabled</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCOS16_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCOS16_1</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBRF</name>
|
|
<description>First modulation stage select</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UCBRS</name>
|
|
<description>Second modulation stage select</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxSTATW</name>
|
|
<displayName>STATW</displayName>
|
|
<description>eUSCI_Ax Status Register</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCBUSY</name>
|
|
<description>eUSCI_A busy</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>UCBUSY_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>UCBUSY_0</name>
|
|
<description>eUSCI_A inactive</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBUSY_1</name>
|
|
<description>eUSCI_A transmitting or receiving</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCADDR_UCIDLE</name>
|
|
<description>Address received / Idle line detected</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UCRXERR</name>
|
|
<description>Receive error flag</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXERR_0</name>
|
|
<description>No receive errors detected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXERR_1</name>
|
|
<description>Receive error detected</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBRK</name>
|
|
<description>Break detect flag</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCBRK_0</name>
|
|
<description>No break condition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBRK_1</name>
|
|
<description>Break condition occurred</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCPE</name>
|
|
<description>Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read.</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCPE_0</name>
|
|
<description>No error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCPE_1</name>
|
|
<description>Character received with parity error</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCOE</name>
|
|
<description>Overrun error flag</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCOE_0</name>
|
|
<description>No error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCOE_1</name>
|
|
<description>Overrun error occurred</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCFE</name>
|
|
<description>Framing error flag</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCFE_0</name>
|
|
<description>No error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCFE_1</name>
|
|
<description>Character received with low stop bit</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCLISTEN</name>
|
|
<description>Listen enable</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCLISTEN_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCLISTEN_1</name>
|
|
<description>Enabled. UCAxTXD is internally fed back to the receiver</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxRXBUF</name>
|
|
<displayName>RXBUF</displayName>
|
|
<description>eUSCI_Ax Receive Buffer Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCRXBUF</name>
|
|
<description>Receive data buffer</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxTXBUF</name>
|
|
<displayName>TXBUF</displayName>
|
|
<description>eUSCI_Ax Transmit Buffer Register</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCTXBUF</name>
|
|
<description>Transmit data buffer</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxABCTL</name>
|
|
<displayName>ABCTL</displayName>
|
|
<description>eUSCI_Ax Auto Baud Rate Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCABDEN</name>
|
|
<description>Automatic baud-rate detect enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCABDEN_0</name>
|
|
<description>Baud-rate detection disabled. Length of break and synch field is not measured.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCABDEN_1</name>
|
|
<description>Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBTOE</name>
|
|
<description>Break time out error</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCBTOE_0</name>
|
|
<description>No error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBTOE_1</name>
|
|
<description>Length of break field exceeded 22 bit times</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTOE</name>
|
|
<description>Synch field time out error</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTOE_0</name>
|
|
<description>No error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTOE_1</name>
|
|
<description>Length of synch field exceeded measurable time</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCDELIM</name>
|
|
<description>Break/synch delimiter length</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCDELIM_0</name>
|
|
<description>1 bit time</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCDELIM_1</name>
|
|
<description>2 bit times</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCDELIM_2</name>
|
|
<description>3 bit times</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCDELIM_3</name>
|
|
<description>4 bit times</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxIRCTL</name>
|
|
<displayName>IRCTL</displayName>
|
|
<description>eUSCI_Ax IrDA Control Word Register</description>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCIREN</name>
|
|
<description>IrDA encoder/decoder enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCIREN_0</name>
|
|
<description>IrDA encoder/decoder disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIREN_1</name>
|
|
<description>IrDA encoder/decoder enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCIRTXCLK</name>
|
|
<description>IrDA transmit pulse clock select</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCIRTXCLK_0</name>
|
|
<description>BRCLK</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIRTXCLK_1</name>
|
|
<description>BITCLK16 when UCOS16 = 1. Otherwise, BRCLK.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCIRTXPL</name>
|
|
<description>Transmit pulse length</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UCIRRXFE</name>
|
|
<description>IrDA receive filter enabled</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCIRRXFE_0</name>
|
|
<description>Receive filter disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIRRXFE_1</name>
|
|
<description>Receive filter enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCIRRXPL</name>
|
|
<description>IrDA receive input UCAxRXD polarity</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCIRRXPL_0</name>
|
|
<description>IrDA transceiver delivers a high pulse when a light pulse is seen</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIRRXPL_1</name>
|
|
<description>IrDA transceiver delivers a low pulse when a light pulse is seen</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCIRRXFL</name>
|
|
<description>Receive filter length</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxIE</name>
|
|
<displayName>IE</displayName>
|
|
<description>eUSCI_Ax Interrupt Enable Register</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCRXIE</name>
|
|
<description>Receive interrupt enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIE</name>
|
|
<description>Transmit interrupt enable</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTTIE</name>
|
|
<description>Start bit interrupt enable</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTTIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTTIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXCPTIE</name>
|
|
<description>Transmit complete interrupt enable</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXCPTIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXCPTIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxIFG</name>
|
|
<displayName>IFG</displayName>
|
|
<description>eUSCI_Ax Interrupt Flag Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000002</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCRXIFG</name>
|
|
<description>Receive interrupt flag</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIFG</name>
|
|
<description>Transmit interrupt flag</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTTIFG</name>
|
|
<description>Start bit interrupt flag</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTTIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTTIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXCPTIFG</name>
|
|
<description>Transmit ready interrupt enable</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXCPTIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXCPTIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxIV</name>
|
|
<displayName>IV</displayName>
|
|
<description>eUSCI_Ax Interrupt Vector Register</description>
|
|
<addressOffset>0x1E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCIV</name>
|
|
<description>eUSCI_A interrupt vector value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>UCIV_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>UCIV_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_2</name>
|
|
<description>Interrupt Source: Receive buffer full; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_4</name>
|
|
<description>Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_6</name>
|
|
<description>Interrupt Source: Start bit received; Interrupt Flag: UCSTTIFG</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_8</name>
|
|
<description>Interrupt Source: Transmit complete; Interrupt Flag: UCTXCPTIFG; Interrupt Priority: Lowest</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EUSCI_A2</name>
|
|
<version>356.0</version>
|
|
<description>EUSCI_A2</description>
|
|
<baseAddress>0x40001800</baseAddress>
|
|
<interrupt>
|
|
<name>EUSCIA2_IRQ</name>
|
|
<description>EUSCIA2 Interrupt</description>
|
|
<value>18</value>
|
|
</interrupt>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>UCAxCTLW0</name>
|
|
<displayName>CTLW0</displayName>
|
|
<description>eUSCI_Ax Control Word Register 0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCSWRST</name>
|
|
<description>Software reset enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSWRST_0</name>
|
|
<description>Disabled. eUSCI_A reset released for operation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSWRST_1</name>
|
|
<description>Enabled. eUSCI_A logic held in reset state</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXBRK</name>
|
|
<description>Transmit break</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXBRK_0</name>
|
|
<description>Next frame transmitted is not a break</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXBRK_1</name>
|
|
<description>Next frame transmitted is a break or a break/synch</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXADDR</name>
|
|
<description>Transmit address</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXADDR_0</name>
|
|
<description>Next frame transmitted is data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXADDR_1</name>
|
|
<description>Next frame transmitted is an address</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCDORM</name>
|
|
<description>Dormant</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCDORM_0</name>
|
|
<description>Not dormant. All received characters set UCRXIFG.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCDORM_1</name>
|
|
<description>Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBRKIE</name>
|
|
<description>Receive break character interrupt enable</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCBRKIE_0</name>
|
|
<description>Received break characters do not set UCRXIFG</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBRKIE_1</name>
|
|
<description>Received break characters set UCRXIFG</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCRXEIE</name>
|
|
<description>Receive erroneous-character interrupt enable</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXEIE_0</name>
|
|
<description>Erroneous characters rejected and UCRXIFG is not set</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXEIE_1</name>
|
|
<description>Erroneous characters received set UCRXIFG</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSSEL</name>
|
|
<description>eUSCI_A clock source select</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSSEL_0</name>
|
|
<description>UCLK</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSSEL_1</name>
|
|
<description>ACLK</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSSEL_2</name>
|
|
<description>SMCLK</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSYNC</name>
|
|
<description>Synchronous mode enable</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSYNC_0</name>
|
|
<description>Asynchronous mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSYNC_1</name>
|
|
<description>Synchronous mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCMODE</name>
|
|
<description>eUSCI_A mode</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCMODE_0</name>
|
|
<description>UART mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMODE_1</name>
|
|
<description>Idle-line multiprocessor mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMODE_2</name>
|
|
<description>Address-bit multiprocessor mode</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMODE_3</name>
|
|
<description>UART mode with automatic baud-rate detection</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSPB</name>
|
|
<description>Stop bit select</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSPB_0</name>
|
|
<description>One stop bit</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSPB_1</name>
|
|
<description>Two stop bits</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UC7BIT</name>
|
|
<description>Character length</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UC7BIT_0</name>
|
|
<description>8-bit data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UC7BIT_1</name>
|
|
<description>7-bit data</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCMSB</name>
|
|
<description>MSB first select</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCMSB_0</name>
|
|
<description>LSB first</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMSB_1</name>
|
|
<description>MSB first</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCPAR</name>
|
|
<description>Parity select</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCPAR_0</name>
|
|
<description>Odd parity</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCPAR_1</name>
|
|
<description>Even parity</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCPEN</name>
|
|
<description>Parity enable</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCPEN_0</name>
|
|
<description>Parity disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCPEN_1</name>
|
|
<description>Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxCTLW1</name>
|
|
<displayName>CTLW1</displayName>
|
|
<description>eUSCI_Ax Control Word Register 1</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCGLIT</name>
|
|
<description>Deglitch time</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_0</name>
|
|
<description>Approximately 2 ns (equivalent of 1 delay element)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_1</name>
|
|
<description>Approximately 50 ns</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_2</name>
|
|
<description>Approximately 100 ns</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_3</name>
|
|
<description>Approximately 200 ns</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxBRW</name>
|
|
<displayName>BRW</displayName>
|
|
<description>eUSCI_Ax Baud Rate Control Word Register</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000ff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCBR</name>
|
|
<description>Clock prescaler setting of the Baud rate generator</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxMCTLW</name>
|
|
<displayName>MCTLW</displayName>
|
|
<description>eUSCI_Ax Modulation Control Word Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCOS16</name>
|
|
<description>Oversampling mode enabled</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCOS16_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCOS16_1</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBRF</name>
|
|
<description>First modulation stage select</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UCBRS</name>
|
|
<description>Second modulation stage select</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxSTATW</name>
|
|
<displayName>STATW</displayName>
|
|
<description>eUSCI_Ax Status Register</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCBUSY</name>
|
|
<description>eUSCI_A busy</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>UCBUSY_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>UCBUSY_0</name>
|
|
<description>eUSCI_A inactive</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBUSY_1</name>
|
|
<description>eUSCI_A transmitting or receiving</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCADDR_UCIDLE</name>
|
|
<description>Address received / Idle line detected</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UCRXERR</name>
|
|
<description>Receive error flag</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXERR_0</name>
|
|
<description>No receive errors detected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXERR_1</name>
|
|
<description>Receive error detected</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBRK</name>
|
|
<description>Break detect flag</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCBRK_0</name>
|
|
<description>No break condition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBRK_1</name>
|
|
<description>Break condition occurred</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCPE</name>
|
|
<description>Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read.</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCPE_0</name>
|
|
<description>No error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCPE_1</name>
|
|
<description>Character received with parity error</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCOE</name>
|
|
<description>Overrun error flag</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCOE_0</name>
|
|
<description>No error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCOE_1</name>
|
|
<description>Overrun error occurred</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCFE</name>
|
|
<description>Framing error flag</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCFE_0</name>
|
|
<description>No error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCFE_1</name>
|
|
<description>Character received with low stop bit</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCLISTEN</name>
|
|
<description>Listen enable</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCLISTEN_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCLISTEN_1</name>
|
|
<description>Enabled. UCAxTXD is internally fed back to the receiver</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxRXBUF</name>
|
|
<displayName>RXBUF</displayName>
|
|
<description>eUSCI_Ax Receive Buffer Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCRXBUF</name>
|
|
<description>Receive data buffer</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxTXBUF</name>
|
|
<displayName>TXBUF</displayName>
|
|
<description>eUSCI_Ax Transmit Buffer Register</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCTXBUF</name>
|
|
<description>Transmit data buffer</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxABCTL</name>
|
|
<displayName>ABCTL</displayName>
|
|
<description>eUSCI_Ax Auto Baud Rate Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCABDEN</name>
|
|
<description>Automatic baud-rate detect enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCABDEN_0</name>
|
|
<description>Baud-rate detection disabled. Length of break and synch field is not measured.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCABDEN_1</name>
|
|
<description>Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBTOE</name>
|
|
<description>Break time out error</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCBTOE_0</name>
|
|
<description>No error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBTOE_1</name>
|
|
<description>Length of break field exceeded 22 bit times</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTOE</name>
|
|
<description>Synch field time out error</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTOE_0</name>
|
|
<description>No error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTOE_1</name>
|
|
<description>Length of synch field exceeded measurable time</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCDELIM</name>
|
|
<description>Break/synch delimiter length</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCDELIM_0</name>
|
|
<description>1 bit time</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCDELIM_1</name>
|
|
<description>2 bit times</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCDELIM_2</name>
|
|
<description>3 bit times</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCDELIM_3</name>
|
|
<description>4 bit times</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxIRCTL</name>
|
|
<displayName>IRCTL</displayName>
|
|
<description>eUSCI_Ax IrDA Control Word Register</description>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCIREN</name>
|
|
<description>IrDA encoder/decoder enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCIREN_0</name>
|
|
<description>IrDA encoder/decoder disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIREN_1</name>
|
|
<description>IrDA encoder/decoder enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCIRTXCLK</name>
|
|
<description>IrDA transmit pulse clock select</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCIRTXCLK_0</name>
|
|
<description>BRCLK</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIRTXCLK_1</name>
|
|
<description>BITCLK16 when UCOS16 = 1. Otherwise, BRCLK.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCIRTXPL</name>
|
|
<description>Transmit pulse length</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UCIRRXFE</name>
|
|
<description>IrDA receive filter enabled</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCIRRXFE_0</name>
|
|
<description>Receive filter disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIRRXFE_1</name>
|
|
<description>Receive filter enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCIRRXPL</name>
|
|
<description>IrDA receive input UCAxRXD polarity</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCIRRXPL_0</name>
|
|
<description>IrDA transceiver delivers a high pulse when a light pulse is seen</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIRRXPL_1</name>
|
|
<description>IrDA transceiver delivers a low pulse when a light pulse is seen</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCIRRXFL</name>
|
|
<description>Receive filter length</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxIE</name>
|
|
<displayName>IE</displayName>
|
|
<description>eUSCI_Ax Interrupt Enable Register</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCRXIE</name>
|
|
<description>Receive interrupt enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIE</name>
|
|
<description>Transmit interrupt enable</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTTIE</name>
|
|
<description>Start bit interrupt enable</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTTIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTTIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXCPTIE</name>
|
|
<description>Transmit complete interrupt enable</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXCPTIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXCPTIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxIFG</name>
|
|
<displayName>IFG</displayName>
|
|
<description>eUSCI_Ax Interrupt Flag Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000002</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCRXIFG</name>
|
|
<description>Receive interrupt flag</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIFG</name>
|
|
<description>Transmit interrupt flag</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTTIFG</name>
|
|
<description>Start bit interrupt flag</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTTIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTTIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXCPTIFG</name>
|
|
<description>Transmit ready interrupt enable</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXCPTIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXCPTIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxIV</name>
|
|
<displayName>IV</displayName>
|
|
<description>eUSCI_Ax Interrupt Vector Register</description>
|
|
<addressOffset>0x1E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCIV</name>
|
|
<description>eUSCI_A interrupt vector value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>UCIV_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>UCIV_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_2</name>
|
|
<description>Interrupt Source: Receive buffer full; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_4</name>
|
|
<description>Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_6</name>
|
|
<description>Interrupt Source: Start bit received; Interrupt Flag: UCSTTIFG</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_8</name>
|
|
<description>Interrupt Source: Transmit complete; Interrupt Flag: UCTXCPTIFG; Interrupt Priority: Lowest</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EUSCI_A3</name>
|
|
<version>356.0</version>
|
|
<description>EUSCI_A3</description>
|
|
<baseAddress>0x40001C00</baseAddress>
|
|
<interrupt>
|
|
<name>EUSCIA3_IRQ</name>
|
|
<description>EUSCIA3 Interrupt</description>
|
|
<value>19</value>
|
|
</interrupt>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>UCAxCTLW0</name>
|
|
<displayName>CTLW0</displayName>
|
|
<description>eUSCI_Ax Control Word Register 0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCSWRST</name>
|
|
<description>Software reset enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSWRST_0</name>
|
|
<description>Disabled. eUSCI_A reset released for operation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSWRST_1</name>
|
|
<description>Enabled. eUSCI_A logic held in reset state</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXBRK</name>
|
|
<description>Transmit break</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXBRK_0</name>
|
|
<description>Next frame transmitted is not a break</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXBRK_1</name>
|
|
<description>Next frame transmitted is a break or a break/synch</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXADDR</name>
|
|
<description>Transmit address</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXADDR_0</name>
|
|
<description>Next frame transmitted is data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXADDR_1</name>
|
|
<description>Next frame transmitted is an address</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCDORM</name>
|
|
<description>Dormant</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCDORM_0</name>
|
|
<description>Not dormant. All received characters set UCRXIFG.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCDORM_1</name>
|
|
<description>Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBRKIE</name>
|
|
<description>Receive break character interrupt enable</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCBRKIE_0</name>
|
|
<description>Received break characters do not set UCRXIFG</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBRKIE_1</name>
|
|
<description>Received break characters set UCRXIFG</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCRXEIE</name>
|
|
<description>Receive erroneous-character interrupt enable</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXEIE_0</name>
|
|
<description>Erroneous characters rejected and UCRXIFG is not set</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXEIE_1</name>
|
|
<description>Erroneous characters received set UCRXIFG</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSSEL</name>
|
|
<description>eUSCI_A clock source select</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSSEL_0</name>
|
|
<description>UCLK</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSSEL_1</name>
|
|
<description>ACLK</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSSEL_2</name>
|
|
<description>SMCLK</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSYNC</name>
|
|
<description>Synchronous mode enable</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSYNC_0</name>
|
|
<description>Asynchronous mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSYNC_1</name>
|
|
<description>Synchronous mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCMODE</name>
|
|
<description>eUSCI_A mode</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCMODE_0</name>
|
|
<description>UART mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMODE_1</name>
|
|
<description>Idle-line multiprocessor mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMODE_2</name>
|
|
<description>Address-bit multiprocessor mode</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMODE_3</name>
|
|
<description>UART mode with automatic baud-rate detection</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSPB</name>
|
|
<description>Stop bit select</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSPB_0</name>
|
|
<description>One stop bit</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSPB_1</name>
|
|
<description>Two stop bits</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UC7BIT</name>
|
|
<description>Character length</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UC7BIT_0</name>
|
|
<description>8-bit data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UC7BIT_1</name>
|
|
<description>7-bit data</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCMSB</name>
|
|
<description>MSB first select</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCMSB_0</name>
|
|
<description>LSB first</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMSB_1</name>
|
|
<description>MSB first</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCPAR</name>
|
|
<description>Parity select</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCPAR_0</name>
|
|
<description>Odd parity</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCPAR_1</name>
|
|
<description>Even parity</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCPEN</name>
|
|
<description>Parity enable</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCPEN_0</name>
|
|
<description>Parity disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCPEN_1</name>
|
|
<description>Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxCTLW1</name>
|
|
<displayName>CTLW1</displayName>
|
|
<description>eUSCI_Ax Control Word Register 1</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCGLIT</name>
|
|
<description>Deglitch time</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_0</name>
|
|
<description>Approximately 2 ns (equivalent of 1 delay element)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_1</name>
|
|
<description>Approximately 50 ns</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_2</name>
|
|
<description>Approximately 100 ns</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_3</name>
|
|
<description>Approximately 200 ns</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxBRW</name>
|
|
<displayName>BRW</displayName>
|
|
<description>eUSCI_Ax Baud Rate Control Word Register</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000ff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCBR</name>
|
|
<description>Clock prescaler setting of the Baud rate generator</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxMCTLW</name>
|
|
<displayName>MCTLW</displayName>
|
|
<description>eUSCI_Ax Modulation Control Word Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCOS16</name>
|
|
<description>Oversampling mode enabled</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCOS16_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCOS16_1</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBRF</name>
|
|
<description>First modulation stage select</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UCBRS</name>
|
|
<description>Second modulation stage select</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxSTATW</name>
|
|
<displayName>STATW</displayName>
|
|
<description>eUSCI_Ax Status Register</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCBUSY</name>
|
|
<description>eUSCI_A busy</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>UCBUSY_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>UCBUSY_0</name>
|
|
<description>eUSCI_A inactive</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBUSY_1</name>
|
|
<description>eUSCI_A transmitting or receiving</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCADDR_UCIDLE</name>
|
|
<description>Address received / Idle line detected</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UCRXERR</name>
|
|
<description>Receive error flag</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXERR_0</name>
|
|
<description>No receive errors detected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXERR_1</name>
|
|
<description>Receive error detected</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBRK</name>
|
|
<description>Break detect flag</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCBRK_0</name>
|
|
<description>No break condition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBRK_1</name>
|
|
<description>Break condition occurred</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCPE</name>
|
|
<description>Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read.</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCPE_0</name>
|
|
<description>No error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCPE_1</name>
|
|
<description>Character received with parity error</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCOE</name>
|
|
<description>Overrun error flag</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCOE_0</name>
|
|
<description>No error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCOE_1</name>
|
|
<description>Overrun error occurred</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCFE</name>
|
|
<description>Framing error flag</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCFE_0</name>
|
|
<description>No error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCFE_1</name>
|
|
<description>Character received with low stop bit</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCLISTEN</name>
|
|
<description>Listen enable</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCLISTEN_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCLISTEN_1</name>
|
|
<description>Enabled. UCAxTXD is internally fed back to the receiver</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxRXBUF</name>
|
|
<displayName>RXBUF</displayName>
|
|
<description>eUSCI_Ax Receive Buffer Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCRXBUF</name>
|
|
<description>Receive data buffer</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxTXBUF</name>
|
|
<displayName>TXBUF</displayName>
|
|
<description>eUSCI_Ax Transmit Buffer Register</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCTXBUF</name>
|
|
<description>Transmit data buffer</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxABCTL</name>
|
|
<displayName>ABCTL</displayName>
|
|
<description>eUSCI_Ax Auto Baud Rate Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCABDEN</name>
|
|
<description>Automatic baud-rate detect enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCABDEN_0</name>
|
|
<description>Baud-rate detection disabled. Length of break and synch field is not measured.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCABDEN_1</name>
|
|
<description>Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBTOE</name>
|
|
<description>Break time out error</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCBTOE_0</name>
|
|
<description>No error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBTOE_1</name>
|
|
<description>Length of break field exceeded 22 bit times</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTOE</name>
|
|
<description>Synch field time out error</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTOE_0</name>
|
|
<description>No error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTOE_1</name>
|
|
<description>Length of synch field exceeded measurable time</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCDELIM</name>
|
|
<description>Break/synch delimiter length</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCDELIM_0</name>
|
|
<description>1 bit time</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCDELIM_1</name>
|
|
<description>2 bit times</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCDELIM_2</name>
|
|
<description>3 bit times</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCDELIM_3</name>
|
|
<description>4 bit times</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxIRCTL</name>
|
|
<displayName>IRCTL</displayName>
|
|
<description>eUSCI_Ax IrDA Control Word Register</description>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCIREN</name>
|
|
<description>IrDA encoder/decoder enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCIREN_0</name>
|
|
<description>IrDA encoder/decoder disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIREN_1</name>
|
|
<description>IrDA encoder/decoder enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCIRTXCLK</name>
|
|
<description>IrDA transmit pulse clock select</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCIRTXCLK_0</name>
|
|
<description>BRCLK</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIRTXCLK_1</name>
|
|
<description>BITCLK16 when UCOS16 = 1. Otherwise, BRCLK.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCIRTXPL</name>
|
|
<description>Transmit pulse length</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UCIRRXFE</name>
|
|
<description>IrDA receive filter enabled</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCIRRXFE_0</name>
|
|
<description>Receive filter disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIRRXFE_1</name>
|
|
<description>Receive filter enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCIRRXPL</name>
|
|
<description>IrDA receive input UCAxRXD polarity</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCIRRXPL_0</name>
|
|
<description>IrDA transceiver delivers a high pulse when a light pulse is seen</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIRRXPL_1</name>
|
|
<description>IrDA transceiver delivers a low pulse when a light pulse is seen</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCIRRXFL</name>
|
|
<description>Receive filter length</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxIE</name>
|
|
<displayName>IE</displayName>
|
|
<description>eUSCI_Ax Interrupt Enable Register</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCRXIE</name>
|
|
<description>Receive interrupt enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIE</name>
|
|
<description>Transmit interrupt enable</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTTIE</name>
|
|
<description>Start bit interrupt enable</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTTIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTTIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXCPTIE</name>
|
|
<description>Transmit complete interrupt enable</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXCPTIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXCPTIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxIFG</name>
|
|
<displayName>IFG</displayName>
|
|
<description>eUSCI_Ax Interrupt Flag Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000002</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCRXIFG</name>
|
|
<description>Receive interrupt flag</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIFG</name>
|
|
<description>Transmit interrupt flag</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTTIFG</name>
|
|
<description>Start bit interrupt flag</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTTIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTTIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXCPTIFG</name>
|
|
<description>Transmit ready interrupt enable</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXCPTIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXCPTIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCAxIV</name>
|
|
<displayName>IV</displayName>
|
|
<description>eUSCI_Ax Interrupt Vector Register</description>
|
|
<addressOffset>0x1E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCIV</name>
|
|
<description>eUSCI_A interrupt vector value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>UCIV_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>UCIV_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_2</name>
|
|
<description>Interrupt Source: Receive buffer full; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_4</name>
|
|
<description>Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_6</name>
|
|
<description>Interrupt Source: Start bit received; Interrupt Flag: UCSTTIFG</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_8</name>
|
|
<description>Interrupt Source: Transmit complete; Interrupt Flag: UCTXCPTIFG; Interrupt Priority: Lowest</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EUSCI_B0</name>
|
|
<version>356.0</version>
|
|
<description>EUSCI_B0</description>
|
|
<baseAddress>0x40002000</baseAddress>
|
|
<interrupt>
|
|
<name>EUSCIB0_IRQ</name>
|
|
<description>EUSCIB0 Interrupt</description>
|
|
<value>20</value>
|
|
</interrupt>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x30</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>UCBxCTLW0</name>
|
|
<displayName>CTLW0</displayName>
|
|
<description>eUSCI_Bx Control Word Register 0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000001c1</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCSWRST</name>
|
|
<description>Software reset enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSWRST_0</name>
|
|
<description>Disabled. eUSCI_B reset released for operation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSWRST_1</name>
|
|
<description>Enabled. eUSCI_B logic held in reset state</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXSTT</name>
|
|
<description>Transmit START condition in master mode</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXSTT_0</name>
|
|
<description>Do not generate START condition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXSTT_1</name>
|
|
<description>Generate START condition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXSTP</name>
|
|
<description>Transmit STOP condition in master mode</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXSTP_0</name>
|
|
<description>No STOP generated</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXSTP_1</name>
|
|
<description>Generate STOP</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXNACK</name>
|
|
<description>Transmit a NACK</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXNACK_0</name>
|
|
<description>Acknowledge normally</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXNACK_1</name>
|
|
<description>Generate NACK</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTR</name>
|
|
<description>Transmitter/receiver</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTR_0</name>
|
|
<description>Receiver</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTR_1</name>
|
|
<description>Transmitter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXACK</name>
|
|
<description>Transmit ACK condition in slave mode</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXACK_0</name>
|
|
<description>Do not acknowledge the slave address</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXACK_1</name>
|
|
<description>Acknowledge the slave address</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSSEL</name>
|
|
<description>eUSCI_B clock source select</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSSEL_0</name>
|
|
<description>UCLKI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSSEL_1</name>
|
|
<description>ACLK</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSSEL_2</name>
|
|
<description>SMCLK</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSSEL_3</name>
|
|
<description>SMCLK</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSYNC</name>
|
|
<description>Synchronous mode enable</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSYNC_0</name>
|
|
<description>Asynchronous mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSYNC_1</name>
|
|
<description>Synchronous mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCMODE</name>
|
|
<description>eUSCI_B mode</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCMODE_0</name>
|
|
<description>3-pin SPI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMODE_1</name>
|
|
<description>4-pin SPI (master or slave enabled if STE = 1)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMODE_2</name>
|
|
<description>4-pin SPI (master or slave enabled if STE = 0)</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMODE_3</name>
|
|
<description>I2C mode</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCMST</name>
|
|
<description>Master mode select</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCMST_0</name>
|
|
<description>Slave mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMST_1</name>
|
|
<description>Master mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCMM</name>
|
|
<description>Multi-master environment select</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCMM_0</name>
|
|
<description>Single master environment. There is no other master in the system. The address compare unit is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMM_1</name>
|
|
<description>Multi-master environment</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSLA10</name>
|
|
<description>Slave addressing mode select</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSLA10_0</name>
|
|
<description>Address slave with 7-bit address</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSLA10_1</name>
|
|
<description>Address slave with 10-bit address</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCA10</name>
|
|
<description>Own addressing mode select</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCA10_0</name>
|
|
<description>Own address is a 7-bit address</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCA10_1</name>
|
|
<description>Own address is a 10-bit address</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxCTLW1</name>
|
|
<displayName>CTLW1</displayName>
|
|
<description>eUSCI_Bx Control Word Register 1</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCGLIT</name>
|
|
<description>Deglitch time</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_0</name>
|
|
<description>50 ns</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_1</name>
|
|
<description>25 ns</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_2</name>
|
|
<description>12.5 ns</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_3</name>
|
|
<description>6.25 ns</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCASTP</name>
|
|
<description>Automatic STOP condition generation</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCASTP_0</name>
|
|
<description>No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCASTP_1</name>
|
|
<description>UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCASTP_2</name>
|
|
<description>A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSWACK</name>
|
|
<description>SW or HW ACK control</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSWACK_0</name>
|
|
<description>The address acknowledge of the slave is controlled by the eUSCI_B module</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSWACK_1</name>
|
|
<description>The user needs to trigger the sending of the address ACK by issuing UCTXACK</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTPNACK</name>
|
|
<description>ACK all master bytes</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTPNACK_0</name>
|
|
<description>Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTPNACK_1</name>
|
|
<description>All bytes are acknowledged by the eUSCI_B when configured as master receiver</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCCLTO</name>
|
|
<description>Clock low timeout select</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCCLTO_0</name>
|
|
<description>Disable clock low timeout counter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCCLTO_1</name>
|
|
<description>135 000 SYSCLK cycles (approximately 28 ms)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCCLTO_2</name>
|
|
<description>150 000 SYSCLK cycles (approximately 31 ms)</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCCLTO_3</name>
|
|
<description>165 000 SYSCLK cycles (approximately 34 ms)</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCETXINT</name>
|
|
<description>Early UCTXIFG0</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCETXINT_0</name>
|
|
<description>UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCETXINT_1</name>
|
|
<description>UCTXIFG0 is set for each START condition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxBRW</name>
|
|
<displayName>BRW</displayName>
|
|
<description>eUSCI_Bx Baud Rate Control Word Register</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCBR</name>
|
|
<description>Bit clock prescaler</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxSTATW</name>
|
|
<displayName>STATW</displayName>
|
|
<description>eUSCI_Bx Status Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCBBUSY</name>
|
|
<description>Bus busy</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>UCBBUSY_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>UCBBUSY_0</name>
|
|
<description>Bus inactive</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBBUSY_1</name>
|
|
<description>Bus busy</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCGC</name>
|
|
<description>General call address received</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>UCGC_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>UCGC_0</name>
|
|
<description>No general call address received</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGC_1</name>
|
|
<description>General call address received</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSCLLOW</name>
|
|
<description>SCL low</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>UCSCLLOW_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>UCSCLLOW_0</name>
|
|
<description>SCL is not held low</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSCLLOW_1</name>
|
|
<description>SCL is held low</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBCNT</name>
|
|
<description>Hardware byte counter value</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxTBCNT</name>
|
|
<displayName>TBCNT</displayName>
|
|
<description>eUSCI_Bx Byte Counter Threshold Register</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCTBCNT</name>
|
|
<description>Byte counter threshold value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxRXBUF</name>
|
|
<displayName>RXBUF</displayName>
|
|
<description>eUSCI_Bx Receive Buffer Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCRXBUF</name>
|
|
<description>Receive data buffer</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxTXBUF</name>
|
|
<displayName>TXBUF</displayName>
|
|
<description>eUSCI_Bx Transmit Buffer Register</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCTXBUF</name>
|
|
<description>Transmit data buffer</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxI2COA0</name>
|
|
<displayName>I2COA0</displayName>
|
|
<description>eUSCI_Bx I2C Own Address 0 Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>I2COA0</name>
|
|
<description>I2C own address</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0xA</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UCOAEN</name>
|
|
<description>Own Address enable register</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_0</name>
|
|
<description>The slave address defined in I2COA0 is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_1</name>
|
|
<description>The slave address defined in I2COA0 is enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCGCEN</name>
|
|
<description>General call response enable</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCGCEN_0</name>
|
|
<description>Do not respond to a general call</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGCEN_1</name>
|
|
<description>Respond to a general call</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxI2COA1</name>
|
|
<displayName>I2COA1</displayName>
|
|
<description>eUSCI_Bx I2C Own Address 1 Register</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>I2COA1</name>
|
|
<description>I2C own address</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0xA</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UCOAEN</name>
|
|
<description>Own Address enable register</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_0</name>
|
|
<description>The slave address defined in I2COA1 is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_1</name>
|
|
<description>The slave address defined in I2COA1 is enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxI2COA2</name>
|
|
<displayName>I2COA2</displayName>
|
|
<description>eUSCI_Bx I2C Own Address 2 Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>I2COA2</name>
|
|
<description>I2C own address</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0xA</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UCOAEN</name>
|
|
<description>Own Address enable register</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_0</name>
|
|
<description>The slave address defined in I2COA2 is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_1</name>
|
|
<description>The slave address defined in I2COA2 is enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxI2COA3</name>
|
|
<displayName>I2COA3</displayName>
|
|
<description>eUSCI_Bx I2C Own Address 3 Register</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>I2COA3</name>
|
|
<description>I2C own address</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0xA</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UCOAEN</name>
|
|
<description>Own Address enable register</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_0</name>
|
|
<description>The slave address defined in I2COA3 is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_1</name>
|
|
<description>The slave address defined in I2COA3 is enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxADDRX</name>
|
|
<displayName>ADDRX</displayName>
|
|
<description>eUSCI_Bx I2C Received Address Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDRX</name>
|
|
<description>Received Address Register</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0xA</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxADDMASK</name>
|
|
<displayName>ADDMASK</displayName>
|
|
<description>eUSCI_Bx I2C Address Mask Register</description>
|
|
<addressOffset>0x1E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000003ff</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDMASK</name>
|
|
<description>Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated.
|
|
Modify only when UCSWRST = 1.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0xA</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxI2CSA</name>
|
|
<displayName>I2CSA</displayName>
|
|
<description>eUSCI_Bx I2C Slave Address Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>I2CSA</name>
|
|
<description>I2C slave address</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0xA</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxIE</name>
|
|
<displayName>IE</displayName>
|
|
<description>eUSCI_Bx Interrupt Enable Register</description>
|
|
<addressOffset>0x2A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCRXIE0</name>
|
|
<description>Receive interrupt enable 0</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIE0_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIE0_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIE0</name>
|
|
<description>Transmit interrupt enable 0</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIE0_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIE0_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTTIE</name>
|
|
<description>START condition interrupt enable</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTTIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTTIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTPIE</name>
|
|
<description>STOP condition interrupt enable</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTPIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTPIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCALIE</name>
|
|
<description>Arbitration lost interrupt enable</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCALIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCALIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCNACKIE</name>
|
|
<description>Not-acknowledge interrupt enable</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCNACKIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCNACKIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBCNTIE</name>
|
|
<description>Byte counter interrupt enable</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCBCNTIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBCNTIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCCLTOIE</name>
|
|
<description>Clock low timeout interrupt enable</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCCLTOIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCCLTOIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCRXIE1</name>
|
|
<description>Receive interrupt enable 1</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIE1_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIE1_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIE1</name>
|
|
<description>Transmit interrupt enable 1</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIE1_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIE1_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCRXIE2</name>
|
|
<description>Receive interrupt enable 2</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIE2_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIE2_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIE2</name>
|
|
<description>Transmit interrupt enable 2</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIE2_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIE2_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCRXIE3</name>
|
|
<description>Receive interrupt enable 3</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIE3_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIE3_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIE3</name>
|
|
<description>Transmit interrupt enable 3</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIE3_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIE3_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBIT9IE</name>
|
|
<description>Bit position 9 interrupt enable</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCBIT9IE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBIT9IE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxIFG</name>
|
|
<displayName>IFG</displayName>
|
|
<description>eUSCI_Bx Interrupt Flag Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000002</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCRXIFG0</name>
|
|
<description>eUSCI_B receive interrupt flag 0</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG0_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG0_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIFG0</name>
|
|
<description>eUSCI_B transmit interrupt flag 0</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG0_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG0_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTTIFG</name>
|
|
<description>START condition interrupt flag</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTTIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTTIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTPIFG</name>
|
|
<description>STOP condition interrupt flag</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTPIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTPIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCALIFG</name>
|
|
<description>Arbitration lost interrupt flag</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCALIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCALIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCNACKIFG</name>
|
|
<description>Not-acknowledge received interrupt flag</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCNACKIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCNACKIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBCNTIFG</name>
|
|
<description>Byte counter interrupt flag</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCBCNTIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBCNTIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCCLTOIFG</name>
|
|
<description>Clock low timeout interrupt flag</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCCLTOIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCCLTOIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCRXIFG1</name>
|
|
<description>eUSCI_B receive interrupt flag 1</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG1_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG1_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIFG1</name>
|
|
<description>eUSCI_B transmit interrupt flag 1</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG1_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG1_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCRXIFG2</name>
|
|
<description>eUSCI_B receive interrupt flag 2</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG2_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG2_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIFG2</name>
|
|
<description>eUSCI_B transmit interrupt flag 2</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG2_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG2_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCRXIFG3</name>
|
|
<description>eUSCI_B receive interrupt flag 3</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG3_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG3_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIFG3</name>
|
|
<description>eUSCI_B transmit interrupt flag 3</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG3_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG3_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBIT9IFG</name>
|
|
<description>Bit position 9 interrupt flag</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCBIT9IFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBIT9IFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxIV</name>
|
|
<displayName>IV</displayName>
|
|
<description>eUSCI_Bx Interrupt Vector Register</description>
|
|
<addressOffset>0x2E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCIV</name>
|
|
<description>eUSCI_B interrupt vector value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>UCIV_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>UCIV_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_2</name>
|
|
<description>Interrupt Source: Arbitration lost; Interrupt Flag: UCALIFG; Interrupt Priority: Highest</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_4</name>
|
|
<description>Interrupt Source: Not acknowledgment; Interrupt Flag: UCNACKIFG</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_6</name>
|
|
<description>Interrupt Source: Start condition received; Interrupt Flag: UCSTTIFG</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_8</name>
|
|
<description>Interrupt Source: Stop condition received; Interrupt Flag: UCSTPIFG</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_10</name>
|
|
<description>Interrupt Source: Slave 3 Data received; Interrupt Flag: UCRXIFG3</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_12</name>
|
|
<description>Interrupt Source: Slave 3 Transmit buffer empty; Interrupt Flag: UCTXIFG3</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_14</name>
|
|
<description>Interrupt Source: Slave 2 Data received; Interrupt Flag: UCRXIFG2</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_16</name>
|
|
<description>Interrupt Source: Slave 2 Transmit buffer empty; Interrupt Flag: UCTXIFG2</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_18</name>
|
|
<description>Interrupt Source: Slave 1 Data received; Interrupt Flag: UCRXIFG1</description>
|
|
<value>18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_20</name>
|
|
<description>Interrupt Source: Slave 1 Transmit buffer empty; Interrupt Flag: UCTXIFG1</description>
|
|
<value>20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_22</name>
|
|
<description>Interrupt Source: Data received; Interrupt Flag: UCRXIFG0</description>
|
|
<value>22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_24</name>
|
|
<description>Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG0</description>
|
|
<value>24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_26</name>
|
|
<description>Interrupt Source: Byte counter zero; Interrupt Flag: UCBCNTIFG</description>
|
|
<value>26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_28</name>
|
|
<description>Interrupt Source: Clock low timeout; Interrupt Flag: UCCLTOIFG</description>
|
|
<value>28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_30</name>
|
|
<description>Interrupt Source: Nineth bit position; Interrupt Flag: UCBIT9IFG; Priority: Lowest</description>
|
|
<value>30</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EUSCI_B1</name>
|
|
<version>356.0</version>
|
|
<description>EUSCI_B1</description>
|
|
<baseAddress>0x40002400</baseAddress>
|
|
<interrupt>
|
|
<name>EUSCIB1_IRQ</name>
|
|
<description>EUSCIB1 Interrupt</description>
|
|
<value>21</value>
|
|
</interrupt>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x30</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>UCBxCTLW0</name>
|
|
<displayName>CTLW0</displayName>
|
|
<description>eUSCI_Bx Control Word Register 0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000001c1</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCSWRST</name>
|
|
<description>Software reset enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSWRST_0</name>
|
|
<description>Disabled. eUSCI_B reset released for operation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSWRST_1</name>
|
|
<description>Enabled. eUSCI_B logic held in reset state</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXSTT</name>
|
|
<description>Transmit START condition in master mode</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXSTT_0</name>
|
|
<description>Do not generate START condition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXSTT_1</name>
|
|
<description>Generate START condition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXSTP</name>
|
|
<description>Transmit STOP condition in master mode</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXSTP_0</name>
|
|
<description>No STOP generated</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXSTP_1</name>
|
|
<description>Generate STOP</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXNACK</name>
|
|
<description>Transmit a NACK</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXNACK_0</name>
|
|
<description>Acknowledge normally</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXNACK_1</name>
|
|
<description>Generate NACK</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTR</name>
|
|
<description>Transmitter/receiver</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTR_0</name>
|
|
<description>Receiver</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTR_1</name>
|
|
<description>Transmitter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXACK</name>
|
|
<description>Transmit ACK condition in slave mode</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXACK_0</name>
|
|
<description>Do not acknowledge the slave address</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXACK_1</name>
|
|
<description>Acknowledge the slave address</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSSEL</name>
|
|
<description>eUSCI_B clock source select</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSSEL_0</name>
|
|
<description>UCLKI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSSEL_1</name>
|
|
<description>ACLK</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSSEL_2</name>
|
|
<description>SMCLK</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSSEL_3</name>
|
|
<description>SMCLK</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSYNC</name>
|
|
<description>Synchronous mode enable</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSYNC_0</name>
|
|
<description>Asynchronous mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSYNC_1</name>
|
|
<description>Synchronous mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCMODE</name>
|
|
<description>eUSCI_B mode</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCMODE_0</name>
|
|
<description>3-pin SPI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMODE_1</name>
|
|
<description>4-pin SPI (master or slave enabled if STE = 1)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMODE_2</name>
|
|
<description>4-pin SPI (master or slave enabled if STE = 0)</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMODE_3</name>
|
|
<description>I2C mode</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCMST</name>
|
|
<description>Master mode select</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCMST_0</name>
|
|
<description>Slave mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMST_1</name>
|
|
<description>Master mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCMM</name>
|
|
<description>Multi-master environment select</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCMM_0</name>
|
|
<description>Single master environment. There is no other master in the system. The address compare unit is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMM_1</name>
|
|
<description>Multi-master environment</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSLA10</name>
|
|
<description>Slave addressing mode select</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSLA10_0</name>
|
|
<description>Address slave with 7-bit address</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSLA10_1</name>
|
|
<description>Address slave with 10-bit address</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCA10</name>
|
|
<description>Own addressing mode select</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCA10_0</name>
|
|
<description>Own address is a 7-bit address</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCA10_1</name>
|
|
<description>Own address is a 10-bit address</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxCTLW1</name>
|
|
<displayName>CTLW1</displayName>
|
|
<description>eUSCI_Bx Control Word Register 1</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCGLIT</name>
|
|
<description>Deglitch time</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_0</name>
|
|
<description>50 ns</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_1</name>
|
|
<description>25 ns</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_2</name>
|
|
<description>12.5 ns</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_3</name>
|
|
<description>6.25 ns</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCASTP</name>
|
|
<description>Automatic STOP condition generation</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCASTP_0</name>
|
|
<description>No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCASTP_1</name>
|
|
<description>UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCASTP_2</name>
|
|
<description>A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSWACK</name>
|
|
<description>SW or HW ACK control</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSWACK_0</name>
|
|
<description>The address acknowledge of the slave is controlled by the eUSCI_B module</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSWACK_1</name>
|
|
<description>The user needs to trigger the sending of the address ACK by issuing UCTXACK</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTPNACK</name>
|
|
<description>ACK all master bytes</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTPNACK_0</name>
|
|
<description>Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTPNACK_1</name>
|
|
<description>All bytes are acknowledged by the eUSCI_B when configured as master receiver</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCCLTO</name>
|
|
<description>Clock low timeout select</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCCLTO_0</name>
|
|
<description>Disable clock low timeout counter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCCLTO_1</name>
|
|
<description>135 000 SYSCLK cycles (approximately 28 ms)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCCLTO_2</name>
|
|
<description>150 000 SYSCLK cycles (approximately 31 ms)</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCCLTO_3</name>
|
|
<description>165 000 SYSCLK cycles (approximately 34 ms)</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCETXINT</name>
|
|
<description>Early UCTXIFG0</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCETXINT_0</name>
|
|
<description>UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCETXINT_1</name>
|
|
<description>UCTXIFG0 is set for each START condition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxBRW</name>
|
|
<displayName>BRW</displayName>
|
|
<description>eUSCI_Bx Baud Rate Control Word Register</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCBR</name>
|
|
<description>Bit clock prescaler</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxSTATW</name>
|
|
<displayName>STATW</displayName>
|
|
<description>eUSCI_Bx Status Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCBBUSY</name>
|
|
<description>Bus busy</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>UCBBUSY_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>UCBBUSY_0</name>
|
|
<description>Bus inactive</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBBUSY_1</name>
|
|
<description>Bus busy</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCGC</name>
|
|
<description>General call address received</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>UCGC_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>UCGC_0</name>
|
|
<description>No general call address received</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGC_1</name>
|
|
<description>General call address received</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSCLLOW</name>
|
|
<description>SCL low</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>UCSCLLOW_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>UCSCLLOW_0</name>
|
|
<description>SCL is not held low</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSCLLOW_1</name>
|
|
<description>SCL is held low</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBCNT</name>
|
|
<description>Hardware byte counter value</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxTBCNT</name>
|
|
<displayName>TBCNT</displayName>
|
|
<description>eUSCI_Bx Byte Counter Threshold Register</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCTBCNT</name>
|
|
<description>Byte counter threshold value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxRXBUF</name>
|
|
<displayName>RXBUF</displayName>
|
|
<description>eUSCI_Bx Receive Buffer Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCRXBUF</name>
|
|
<description>Receive data buffer</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxTXBUF</name>
|
|
<displayName>TXBUF</displayName>
|
|
<description>eUSCI_Bx Transmit Buffer Register</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCTXBUF</name>
|
|
<description>Transmit data buffer</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxI2COA0</name>
|
|
<displayName>I2COA0</displayName>
|
|
<description>eUSCI_Bx I2C Own Address 0 Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>I2COA0</name>
|
|
<description>I2C own address</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0xA</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UCOAEN</name>
|
|
<description>Own Address enable register</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_0</name>
|
|
<description>The slave address defined in I2COA0 is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_1</name>
|
|
<description>The slave address defined in I2COA0 is enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCGCEN</name>
|
|
<description>General call response enable</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCGCEN_0</name>
|
|
<description>Do not respond to a general call</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGCEN_1</name>
|
|
<description>Respond to a general call</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxI2COA1</name>
|
|
<displayName>I2COA1</displayName>
|
|
<description>eUSCI_Bx I2C Own Address 1 Register</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>I2COA1</name>
|
|
<description>I2C own address</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0xA</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UCOAEN</name>
|
|
<description>Own Address enable register</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_0</name>
|
|
<description>The slave address defined in I2COA1 is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_1</name>
|
|
<description>The slave address defined in I2COA1 is enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxI2COA2</name>
|
|
<displayName>I2COA2</displayName>
|
|
<description>eUSCI_Bx I2C Own Address 2 Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>I2COA2</name>
|
|
<description>I2C own address</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0xA</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UCOAEN</name>
|
|
<description>Own Address enable register</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_0</name>
|
|
<description>The slave address defined in I2COA2 is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_1</name>
|
|
<description>The slave address defined in I2COA2 is enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxI2COA3</name>
|
|
<displayName>I2COA3</displayName>
|
|
<description>eUSCI_Bx I2C Own Address 3 Register</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>I2COA3</name>
|
|
<description>I2C own address</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0xA</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UCOAEN</name>
|
|
<description>Own Address enable register</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_0</name>
|
|
<description>The slave address defined in I2COA3 is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_1</name>
|
|
<description>The slave address defined in I2COA3 is enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxADDRX</name>
|
|
<displayName>ADDRX</displayName>
|
|
<description>eUSCI_Bx I2C Received Address Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDRX</name>
|
|
<description>Received Address Register</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0xA</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxADDMASK</name>
|
|
<displayName>ADDMASK</displayName>
|
|
<description>eUSCI_Bx I2C Address Mask Register</description>
|
|
<addressOffset>0x1E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000003ff</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDMASK</name>
|
|
<description>Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated.
|
|
Modify only when UCSWRST = 1.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0xA</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxI2CSA</name>
|
|
<displayName>I2CSA</displayName>
|
|
<description>eUSCI_Bx I2C Slave Address Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>I2CSA</name>
|
|
<description>I2C slave address</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0xA</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxIE</name>
|
|
<displayName>IE</displayName>
|
|
<description>eUSCI_Bx Interrupt Enable Register</description>
|
|
<addressOffset>0x2A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCRXIE0</name>
|
|
<description>Receive interrupt enable 0</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIE0_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIE0_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIE0</name>
|
|
<description>Transmit interrupt enable 0</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIE0_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIE0_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTTIE</name>
|
|
<description>START condition interrupt enable</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTTIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTTIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTPIE</name>
|
|
<description>STOP condition interrupt enable</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTPIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTPIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCALIE</name>
|
|
<description>Arbitration lost interrupt enable</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCALIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCALIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCNACKIE</name>
|
|
<description>Not-acknowledge interrupt enable</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCNACKIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCNACKIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBCNTIE</name>
|
|
<description>Byte counter interrupt enable</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCBCNTIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBCNTIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCCLTOIE</name>
|
|
<description>Clock low timeout interrupt enable</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCCLTOIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCCLTOIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCRXIE1</name>
|
|
<description>Receive interrupt enable 1</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIE1_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIE1_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIE1</name>
|
|
<description>Transmit interrupt enable 1</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIE1_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIE1_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCRXIE2</name>
|
|
<description>Receive interrupt enable 2</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIE2_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIE2_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIE2</name>
|
|
<description>Transmit interrupt enable 2</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIE2_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIE2_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCRXIE3</name>
|
|
<description>Receive interrupt enable 3</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIE3_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIE3_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIE3</name>
|
|
<description>Transmit interrupt enable 3</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIE3_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIE3_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBIT9IE</name>
|
|
<description>Bit position 9 interrupt enable</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCBIT9IE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBIT9IE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxIFG</name>
|
|
<displayName>IFG</displayName>
|
|
<description>eUSCI_Bx Interrupt Flag Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000002</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCRXIFG0</name>
|
|
<description>eUSCI_B receive interrupt flag 0</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG0_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG0_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIFG0</name>
|
|
<description>eUSCI_B transmit interrupt flag 0</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG0_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG0_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTTIFG</name>
|
|
<description>START condition interrupt flag</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTTIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTTIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTPIFG</name>
|
|
<description>STOP condition interrupt flag</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTPIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTPIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCALIFG</name>
|
|
<description>Arbitration lost interrupt flag</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCALIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCALIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCNACKIFG</name>
|
|
<description>Not-acknowledge received interrupt flag</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCNACKIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCNACKIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBCNTIFG</name>
|
|
<description>Byte counter interrupt flag</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCBCNTIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBCNTIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCCLTOIFG</name>
|
|
<description>Clock low timeout interrupt flag</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCCLTOIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCCLTOIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCRXIFG1</name>
|
|
<description>eUSCI_B receive interrupt flag 1</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG1_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG1_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIFG1</name>
|
|
<description>eUSCI_B transmit interrupt flag 1</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG1_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG1_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCRXIFG2</name>
|
|
<description>eUSCI_B receive interrupt flag 2</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG2_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG2_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIFG2</name>
|
|
<description>eUSCI_B transmit interrupt flag 2</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG2_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG2_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCRXIFG3</name>
|
|
<description>eUSCI_B receive interrupt flag 3</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG3_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG3_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIFG3</name>
|
|
<description>eUSCI_B transmit interrupt flag 3</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG3_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG3_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBIT9IFG</name>
|
|
<description>Bit position 9 interrupt flag</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCBIT9IFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBIT9IFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxIV</name>
|
|
<displayName>IV</displayName>
|
|
<description>eUSCI_Bx Interrupt Vector Register</description>
|
|
<addressOffset>0x2E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCIV</name>
|
|
<description>eUSCI_B interrupt vector value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>UCIV_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>UCIV_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_2</name>
|
|
<description>Interrupt Source: Arbitration lost; Interrupt Flag: UCALIFG; Interrupt Priority: Highest</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_4</name>
|
|
<description>Interrupt Source: Not acknowledgment; Interrupt Flag: UCNACKIFG</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_6</name>
|
|
<description>Interrupt Source: Start condition received; Interrupt Flag: UCSTTIFG</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_8</name>
|
|
<description>Interrupt Source: Stop condition received; Interrupt Flag: UCSTPIFG</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_10</name>
|
|
<description>Interrupt Source: Slave 3 Data received; Interrupt Flag: UCRXIFG3</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_12</name>
|
|
<description>Interrupt Source: Slave 3 Transmit buffer empty; Interrupt Flag: UCTXIFG3</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_14</name>
|
|
<description>Interrupt Source: Slave 2 Data received; Interrupt Flag: UCRXIFG2</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_16</name>
|
|
<description>Interrupt Source: Slave 2 Transmit buffer empty; Interrupt Flag: UCTXIFG2</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_18</name>
|
|
<description>Interrupt Source: Slave 1 Data received; Interrupt Flag: UCRXIFG1</description>
|
|
<value>18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_20</name>
|
|
<description>Interrupt Source: Slave 1 Transmit buffer empty; Interrupt Flag: UCTXIFG1</description>
|
|
<value>20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_22</name>
|
|
<description>Interrupt Source: Data received; Interrupt Flag: UCRXIFG0</description>
|
|
<value>22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_24</name>
|
|
<description>Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG0</description>
|
|
<value>24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_26</name>
|
|
<description>Interrupt Source: Byte counter zero; Interrupt Flag: UCBCNTIFG</description>
|
|
<value>26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_28</name>
|
|
<description>Interrupt Source: Clock low timeout; Interrupt Flag: UCCLTOIFG</description>
|
|
<value>28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_30</name>
|
|
<description>Interrupt Source: Nineth bit position; Interrupt Flag: UCBIT9IFG; Priority: Lowest</description>
|
|
<value>30</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EUSCI_B2</name>
|
|
<version>356.0</version>
|
|
<description>EUSCI_B2</description>
|
|
<baseAddress>0x40002800</baseAddress>
|
|
<interrupt>
|
|
<name>EUSCIB2_IRQ</name>
|
|
<description>EUSCIB2 Interrupt</description>
|
|
<value>22</value>
|
|
</interrupt>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x30</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>UCBxCTLW0</name>
|
|
<displayName>CTLW0</displayName>
|
|
<description>eUSCI_Bx Control Word Register 0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000001c1</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCSWRST</name>
|
|
<description>Software reset enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSWRST_0</name>
|
|
<description>Disabled. eUSCI_B reset released for operation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSWRST_1</name>
|
|
<description>Enabled. eUSCI_B logic held in reset state</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXSTT</name>
|
|
<description>Transmit START condition in master mode</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXSTT_0</name>
|
|
<description>Do not generate START condition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXSTT_1</name>
|
|
<description>Generate START condition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXSTP</name>
|
|
<description>Transmit STOP condition in master mode</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXSTP_0</name>
|
|
<description>No STOP generated</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXSTP_1</name>
|
|
<description>Generate STOP</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXNACK</name>
|
|
<description>Transmit a NACK</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXNACK_0</name>
|
|
<description>Acknowledge normally</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXNACK_1</name>
|
|
<description>Generate NACK</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTR</name>
|
|
<description>Transmitter/receiver</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTR_0</name>
|
|
<description>Receiver</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTR_1</name>
|
|
<description>Transmitter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXACK</name>
|
|
<description>Transmit ACK condition in slave mode</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXACK_0</name>
|
|
<description>Do not acknowledge the slave address</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXACK_1</name>
|
|
<description>Acknowledge the slave address</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSSEL</name>
|
|
<description>eUSCI_B clock source select</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSSEL_0</name>
|
|
<description>UCLKI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSSEL_1</name>
|
|
<description>ACLK</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSSEL_2</name>
|
|
<description>SMCLK</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSSEL_3</name>
|
|
<description>SMCLK</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSYNC</name>
|
|
<description>Synchronous mode enable</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSYNC_0</name>
|
|
<description>Asynchronous mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSYNC_1</name>
|
|
<description>Synchronous mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCMODE</name>
|
|
<description>eUSCI_B mode</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCMODE_0</name>
|
|
<description>3-pin SPI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMODE_1</name>
|
|
<description>4-pin SPI (master or slave enabled if STE = 1)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMODE_2</name>
|
|
<description>4-pin SPI (master or slave enabled if STE = 0)</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMODE_3</name>
|
|
<description>I2C mode</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCMST</name>
|
|
<description>Master mode select</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCMST_0</name>
|
|
<description>Slave mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMST_1</name>
|
|
<description>Master mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCMM</name>
|
|
<description>Multi-master environment select</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCMM_0</name>
|
|
<description>Single master environment. There is no other master in the system. The address compare unit is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMM_1</name>
|
|
<description>Multi-master environment</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSLA10</name>
|
|
<description>Slave addressing mode select</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSLA10_0</name>
|
|
<description>Address slave with 7-bit address</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSLA10_1</name>
|
|
<description>Address slave with 10-bit address</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCA10</name>
|
|
<description>Own addressing mode select</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCA10_0</name>
|
|
<description>Own address is a 7-bit address</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCA10_1</name>
|
|
<description>Own address is a 10-bit address</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxCTLW1</name>
|
|
<displayName>CTLW1</displayName>
|
|
<description>eUSCI_Bx Control Word Register 1</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCGLIT</name>
|
|
<description>Deglitch time</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_0</name>
|
|
<description>50 ns</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_1</name>
|
|
<description>25 ns</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_2</name>
|
|
<description>12.5 ns</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_3</name>
|
|
<description>6.25 ns</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCASTP</name>
|
|
<description>Automatic STOP condition generation</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCASTP_0</name>
|
|
<description>No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCASTP_1</name>
|
|
<description>UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCASTP_2</name>
|
|
<description>A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSWACK</name>
|
|
<description>SW or HW ACK control</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSWACK_0</name>
|
|
<description>The address acknowledge of the slave is controlled by the eUSCI_B module</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSWACK_1</name>
|
|
<description>The user needs to trigger the sending of the address ACK by issuing UCTXACK</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTPNACK</name>
|
|
<description>ACK all master bytes</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTPNACK_0</name>
|
|
<description>Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTPNACK_1</name>
|
|
<description>All bytes are acknowledged by the eUSCI_B when configured as master receiver</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCCLTO</name>
|
|
<description>Clock low timeout select</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCCLTO_0</name>
|
|
<description>Disable clock low timeout counter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCCLTO_1</name>
|
|
<description>135 000 SYSCLK cycles (approximately 28 ms)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCCLTO_2</name>
|
|
<description>150 000 SYSCLK cycles (approximately 31 ms)</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCCLTO_3</name>
|
|
<description>165 000 SYSCLK cycles (approximately 34 ms)</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCETXINT</name>
|
|
<description>Early UCTXIFG0</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCETXINT_0</name>
|
|
<description>UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCETXINT_1</name>
|
|
<description>UCTXIFG0 is set for each START condition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxBRW</name>
|
|
<displayName>BRW</displayName>
|
|
<description>eUSCI_Bx Baud Rate Control Word Register</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCBR</name>
|
|
<description>Bit clock prescaler</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxSTATW</name>
|
|
<displayName>STATW</displayName>
|
|
<description>eUSCI_Bx Status Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCBBUSY</name>
|
|
<description>Bus busy</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>UCBBUSY_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>UCBBUSY_0</name>
|
|
<description>Bus inactive</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBBUSY_1</name>
|
|
<description>Bus busy</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCGC</name>
|
|
<description>General call address received</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>UCGC_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>UCGC_0</name>
|
|
<description>No general call address received</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGC_1</name>
|
|
<description>General call address received</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSCLLOW</name>
|
|
<description>SCL low</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>UCSCLLOW_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>UCSCLLOW_0</name>
|
|
<description>SCL is not held low</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSCLLOW_1</name>
|
|
<description>SCL is held low</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBCNT</name>
|
|
<description>Hardware byte counter value</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxTBCNT</name>
|
|
<displayName>TBCNT</displayName>
|
|
<description>eUSCI_Bx Byte Counter Threshold Register</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCTBCNT</name>
|
|
<description>Byte counter threshold value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxRXBUF</name>
|
|
<displayName>RXBUF</displayName>
|
|
<description>eUSCI_Bx Receive Buffer Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCRXBUF</name>
|
|
<description>Receive data buffer</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxTXBUF</name>
|
|
<displayName>TXBUF</displayName>
|
|
<description>eUSCI_Bx Transmit Buffer Register</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCTXBUF</name>
|
|
<description>Transmit data buffer</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxI2COA0</name>
|
|
<displayName>I2COA0</displayName>
|
|
<description>eUSCI_Bx I2C Own Address 0 Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>I2COA0</name>
|
|
<description>I2C own address</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0xA</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UCOAEN</name>
|
|
<description>Own Address enable register</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_0</name>
|
|
<description>The slave address defined in I2COA0 is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_1</name>
|
|
<description>The slave address defined in I2COA0 is enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCGCEN</name>
|
|
<description>General call response enable</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCGCEN_0</name>
|
|
<description>Do not respond to a general call</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGCEN_1</name>
|
|
<description>Respond to a general call</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxI2COA1</name>
|
|
<displayName>I2COA1</displayName>
|
|
<description>eUSCI_Bx I2C Own Address 1 Register</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>I2COA1</name>
|
|
<description>I2C own address</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0xA</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UCOAEN</name>
|
|
<description>Own Address enable register</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_0</name>
|
|
<description>The slave address defined in I2COA1 is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_1</name>
|
|
<description>The slave address defined in I2COA1 is enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxI2COA2</name>
|
|
<displayName>I2COA2</displayName>
|
|
<description>eUSCI_Bx I2C Own Address 2 Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>I2COA2</name>
|
|
<description>I2C own address</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0xA</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UCOAEN</name>
|
|
<description>Own Address enable register</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_0</name>
|
|
<description>The slave address defined in I2COA2 is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_1</name>
|
|
<description>The slave address defined in I2COA2 is enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxI2COA3</name>
|
|
<displayName>I2COA3</displayName>
|
|
<description>eUSCI_Bx I2C Own Address 3 Register</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>I2COA3</name>
|
|
<description>I2C own address</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0xA</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UCOAEN</name>
|
|
<description>Own Address enable register</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_0</name>
|
|
<description>The slave address defined in I2COA3 is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_1</name>
|
|
<description>The slave address defined in I2COA3 is enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxADDRX</name>
|
|
<displayName>ADDRX</displayName>
|
|
<description>eUSCI_Bx I2C Received Address Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDRX</name>
|
|
<description>Received Address Register</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0xA</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxADDMASK</name>
|
|
<displayName>ADDMASK</displayName>
|
|
<description>eUSCI_Bx I2C Address Mask Register</description>
|
|
<addressOffset>0x1E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000003ff</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDMASK</name>
|
|
<description>Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated.
|
|
Modify only when UCSWRST = 1.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0xA</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxI2CSA</name>
|
|
<displayName>I2CSA</displayName>
|
|
<description>eUSCI_Bx I2C Slave Address Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>I2CSA</name>
|
|
<description>I2C slave address</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0xA</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxIE</name>
|
|
<displayName>IE</displayName>
|
|
<description>eUSCI_Bx Interrupt Enable Register</description>
|
|
<addressOffset>0x2A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCRXIE0</name>
|
|
<description>Receive interrupt enable 0</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIE0_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIE0_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIE0</name>
|
|
<description>Transmit interrupt enable 0</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIE0_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIE0_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTTIE</name>
|
|
<description>START condition interrupt enable</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTTIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTTIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTPIE</name>
|
|
<description>STOP condition interrupt enable</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTPIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTPIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCALIE</name>
|
|
<description>Arbitration lost interrupt enable</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCALIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCALIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCNACKIE</name>
|
|
<description>Not-acknowledge interrupt enable</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCNACKIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCNACKIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBCNTIE</name>
|
|
<description>Byte counter interrupt enable</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCBCNTIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBCNTIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCCLTOIE</name>
|
|
<description>Clock low timeout interrupt enable</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCCLTOIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCCLTOIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCRXIE1</name>
|
|
<description>Receive interrupt enable 1</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIE1_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIE1_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIE1</name>
|
|
<description>Transmit interrupt enable 1</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIE1_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIE1_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCRXIE2</name>
|
|
<description>Receive interrupt enable 2</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIE2_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIE2_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIE2</name>
|
|
<description>Transmit interrupt enable 2</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIE2_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIE2_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCRXIE3</name>
|
|
<description>Receive interrupt enable 3</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIE3_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIE3_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIE3</name>
|
|
<description>Transmit interrupt enable 3</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIE3_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIE3_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBIT9IE</name>
|
|
<description>Bit position 9 interrupt enable</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCBIT9IE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBIT9IE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxIFG</name>
|
|
<displayName>IFG</displayName>
|
|
<description>eUSCI_Bx Interrupt Flag Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000002</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCRXIFG0</name>
|
|
<description>eUSCI_B receive interrupt flag 0</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG0_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG0_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIFG0</name>
|
|
<description>eUSCI_B transmit interrupt flag 0</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG0_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG0_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTTIFG</name>
|
|
<description>START condition interrupt flag</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTTIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTTIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTPIFG</name>
|
|
<description>STOP condition interrupt flag</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTPIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTPIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCALIFG</name>
|
|
<description>Arbitration lost interrupt flag</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCALIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCALIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCNACKIFG</name>
|
|
<description>Not-acknowledge received interrupt flag</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCNACKIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCNACKIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBCNTIFG</name>
|
|
<description>Byte counter interrupt flag</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCBCNTIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBCNTIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCCLTOIFG</name>
|
|
<description>Clock low timeout interrupt flag</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCCLTOIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCCLTOIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCRXIFG1</name>
|
|
<description>eUSCI_B receive interrupt flag 1</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG1_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG1_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIFG1</name>
|
|
<description>eUSCI_B transmit interrupt flag 1</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG1_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG1_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCRXIFG2</name>
|
|
<description>eUSCI_B receive interrupt flag 2</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG2_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG2_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIFG2</name>
|
|
<description>eUSCI_B transmit interrupt flag 2</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG2_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG2_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCRXIFG3</name>
|
|
<description>eUSCI_B receive interrupt flag 3</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG3_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG3_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIFG3</name>
|
|
<description>eUSCI_B transmit interrupt flag 3</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG3_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG3_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBIT9IFG</name>
|
|
<description>Bit position 9 interrupt flag</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCBIT9IFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBIT9IFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxIV</name>
|
|
<displayName>IV</displayName>
|
|
<description>eUSCI_Bx Interrupt Vector Register</description>
|
|
<addressOffset>0x2E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCIV</name>
|
|
<description>eUSCI_B interrupt vector value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>UCIV_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>UCIV_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_2</name>
|
|
<description>Interrupt Source: Arbitration lost; Interrupt Flag: UCALIFG; Interrupt Priority: Highest</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_4</name>
|
|
<description>Interrupt Source: Not acknowledgment; Interrupt Flag: UCNACKIFG</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_6</name>
|
|
<description>Interrupt Source: Start condition received; Interrupt Flag: UCSTTIFG</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_8</name>
|
|
<description>Interrupt Source: Stop condition received; Interrupt Flag: UCSTPIFG</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_10</name>
|
|
<description>Interrupt Source: Slave 3 Data received; Interrupt Flag: UCRXIFG3</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_12</name>
|
|
<description>Interrupt Source: Slave 3 Transmit buffer empty; Interrupt Flag: UCTXIFG3</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_14</name>
|
|
<description>Interrupt Source: Slave 2 Data received; Interrupt Flag: UCRXIFG2</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_16</name>
|
|
<description>Interrupt Source: Slave 2 Transmit buffer empty; Interrupt Flag: UCTXIFG2</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_18</name>
|
|
<description>Interrupt Source: Slave 1 Data received; Interrupt Flag: UCRXIFG1</description>
|
|
<value>18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_20</name>
|
|
<description>Interrupt Source: Slave 1 Transmit buffer empty; Interrupt Flag: UCTXIFG1</description>
|
|
<value>20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_22</name>
|
|
<description>Interrupt Source: Data received; Interrupt Flag: UCRXIFG0</description>
|
|
<value>22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_24</name>
|
|
<description>Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG0</description>
|
|
<value>24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_26</name>
|
|
<description>Interrupt Source: Byte counter zero; Interrupt Flag: UCBCNTIFG</description>
|
|
<value>26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_28</name>
|
|
<description>Interrupt Source: Clock low timeout; Interrupt Flag: UCCLTOIFG</description>
|
|
<value>28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_30</name>
|
|
<description>Interrupt Source: Nineth bit position; Interrupt Flag: UCBIT9IFG; Priority: Lowest</description>
|
|
<value>30</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EUSCI_B3</name>
|
|
<version>356.0</version>
|
|
<description>EUSCI_B3</description>
|
|
<baseAddress>0x40002C00</baseAddress>
|
|
<interrupt>
|
|
<name>EUSCIB3_IRQ</name>
|
|
<description>EUSCIB3 Interrupt</description>
|
|
<value>23</value>
|
|
</interrupt>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x30</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>UCBxCTLW0</name>
|
|
<displayName>CTLW0</displayName>
|
|
<description>eUSCI_Bx Control Word Register 0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000001c1</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCSWRST</name>
|
|
<description>Software reset enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSWRST_0</name>
|
|
<description>Disabled. eUSCI_B reset released for operation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSWRST_1</name>
|
|
<description>Enabled. eUSCI_B logic held in reset state</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXSTT</name>
|
|
<description>Transmit START condition in master mode</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXSTT_0</name>
|
|
<description>Do not generate START condition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXSTT_1</name>
|
|
<description>Generate START condition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXSTP</name>
|
|
<description>Transmit STOP condition in master mode</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXSTP_0</name>
|
|
<description>No STOP generated</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXSTP_1</name>
|
|
<description>Generate STOP</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXNACK</name>
|
|
<description>Transmit a NACK</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXNACK_0</name>
|
|
<description>Acknowledge normally</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXNACK_1</name>
|
|
<description>Generate NACK</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTR</name>
|
|
<description>Transmitter/receiver</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTR_0</name>
|
|
<description>Receiver</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTR_1</name>
|
|
<description>Transmitter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXACK</name>
|
|
<description>Transmit ACK condition in slave mode</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXACK_0</name>
|
|
<description>Do not acknowledge the slave address</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXACK_1</name>
|
|
<description>Acknowledge the slave address</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSSEL</name>
|
|
<description>eUSCI_B clock source select</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSSEL_0</name>
|
|
<description>UCLKI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSSEL_1</name>
|
|
<description>ACLK</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSSEL_2</name>
|
|
<description>SMCLK</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSSEL_3</name>
|
|
<description>SMCLK</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSYNC</name>
|
|
<description>Synchronous mode enable</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSYNC_0</name>
|
|
<description>Asynchronous mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSYNC_1</name>
|
|
<description>Synchronous mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCMODE</name>
|
|
<description>eUSCI_B mode</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCMODE_0</name>
|
|
<description>3-pin SPI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMODE_1</name>
|
|
<description>4-pin SPI (master or slave enabled if STE = 1)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMODE_2</name>
|
|
<description>4-pin SPI (master or slave enabled if STE = 0)</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMODE_3</name>
|
|
<description>I2C mode</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCMST</name>
|
|
<description>Master mode select</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCMST_0</name>
|
|
<description>Slave mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMST_1</name>
|
|
<description>Master mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCMM</name>
|
|
<description>Multi-master environment select</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCMM_0</name>
|
|
<description>Single master environment. There is no other master in the system. The address compare unit is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCMM_1</name>
|
|
<description>Multi-master environment</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSLA10</name>
|
|
<description>Slave addressing mode select</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSLA10_0</name>
|
|
<description>Address slave with 7-bit address</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSLA10_1</name>
|
|
<description>Address slave with 10-bit address</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCA10</name>
|
|
<description>Own addressing mode select</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCA10_0</name>
|
|
<description>Own address is a 7-bit address</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCA10_1</name>
|
|
<description>Own address is a 10-bit address</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxCTLW1</name>
|
|
<displayName>CTLW1</displayName>
|
|
<description>eUSCI_Bx Control Word Register 1</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCGLIT</name>
|
|
<description>Deglitch time</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_0</name>
|
|
<description>50 ns</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_1</name>
|
|
<description>25 ns</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_2</name>
|
|
<description>12.5 ns</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGLIT_3</name>
|
|
<description>6.25 ns</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCASTP</name>
|
|
<description>Automatic STOP condition generation</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCASTP_0</name>
|
|
<description>No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCASTP_1</name>
|
|
<description>UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCASTP_2</name>
|
|
<description>A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSWACK</name>
|
|
<description>SW or HW ACK control</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSWACK_0</name>
|
|
<description>The address acknowledge of the slave is controlled by the eUSCI_B module</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSWACK_1</name>
|
|
<description>The user needs to trigger the sending of the address ACK by issuing UCTXACK</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTPNACK</name>
|
|
<description>ACK all master bytes</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTPNACK_0</name>
|
|
<description>Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTPNACK_1</name>
|
|
<description>All bytes are acknowledged by the eUSCI_B when configured as master receiver</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCCLTO</name>
|
|
<description>Clock low timeout select</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCCLTO_0</name>
|
|
<description>Disable clock low timeout counter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCCLTO_1</name>
|
|
<description>135 000 SYSCLK cycles (approximately 28 ms)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCCLTO_2</name>
|
|
<description>150 000 SYSCLK cycles (approximately 31 ms)</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCCLTO_3</name>
|
|
<description>165 000 SYSCLK cycles (approximately 34 ms)</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCETXINT</name>
|
|
<description>Early UCTXIFG0</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCETXINT_0</name>
|
|
<description>UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCETXINT_1</name>
|
|
<description>UCTXIFG0 is set for each START condition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxBRW</name>
|
|
<displayName>BRW</displayName>
|
|
<description>eUSCI_Bx Baud Rate Control Word Register</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCBR</name>
|
|
<description>Bit clock prescaler</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxSTATW</name>
|
|
<displayName>STATW</displayName>
|
|
<description>eUSCI_Bx Status Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCBBUSY</name>
|
|
<description>Bus busy</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>UCBBUSY_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>UCBBUSY_0</name>
|
|
<description>Bus inactive</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBBUSY_1</name>
|
|
<description>Bus busy</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCGC</name>
|
|
<description>General call address received</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>UCGC_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>UCGC_0</name>
|
|
<description>No general call address received</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGC_1</name>
|
|
<description>General call address received</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSCLLOW</name>
|
|
<description>SCL low</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>UCSCLLOW_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>UCSCLLOW_0</name>
|
|
<description>SCL is not held low</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSCLLOW_1</name>
|
|
<description>SCL is held low</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBCNT</name>
|
|
<description>Hardware byte counter value</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxTBCNT</name>
|
|
<displayName>TBCNT</displayName>
|
|
<description>eUSCI_Bx Byte Counter Threshold Register</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCTBCNT</name>
|
|
<description>Byte counter threshold value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxRXBUF</name>
|
|
<displayName>RXBUF</displayName>
|
|
<description>eUSCI_Bx Receive Buffer Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCRXBUF</name>
|
|
<description>Receive data buffer</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxTXBUF</name>
|
|
<displayName>TXBUF</displayName>
|
|
<description>eUSCI_Bx Transmit Buffer Register</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCTXBUF</name>
|
|
<description>Transmit data buffer</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxI2COA0</name>
|
|
<displayName>I2COA0</displayName>
|
|
<description>eUSCI_Bx I2C Own Address 0 Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>I2COA0</name>
|
|
<description>I2C own address</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0xA</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UCOAEN</name>
|
|
<description>Own Address enable register</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_0</name>
|
|
<description>The slave address defined in I2COA0 is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_1</name>
|
|
<description>The slave address defined in I2COA0 is enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCGCEN</name>
|
|
<description>General call response enable</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCGCEN_0</name>
|
|
<description>Do not respond to a general call</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCGCEN_1</name>
|
|
<description>Respond to a general call</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxI2COA1</name>
|
|
<displayName>I2COA1</displayName>
|
|
<description>eUSCI_Bx I2C Own Address 1 Register</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>I2COA1</name>
|
|
<description>I2C own address</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0xA</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UCOAEN</name>
|
|
<description>Own Address enable register</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_0</name>
|
|
<description>The slave address defined in I2COA1 is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_1</name>
|
|
<description>The slave address defined in I2COA1 is enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxI2COA2</name>
|
|
<displayName>I2COA2</displayName>
|
|
<description>eUSCI_Bx I2C Own Address 2 Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>I2COA2</name>
|
|
<description>I2C own address</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0xA</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UCOAEN</name>
|
|
<description>Own Address enable register</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_0</name>
|
|
<description>The slave address defined in I2COA2 is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_1</name>
|
|
<description>The slave address defined in I2COA2 is enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxI2COA3</name>
|
|
<displayName>I2COA3</displayName>
|
|
<description>eUSCI_Bx I2C Own Address 3 Register</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>I2COA3</name>
|
|
<description>I2C own address</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0xA</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UCOAEN</name>
|
|
<description>Own Address enable register</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_0</name>
|
|
<description>The slave address defined in I2COA3 is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCOAEN_1</name>
|
|
<description>The slave address defined in I2COA3 is enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxADDRX</name>
|
|
<displayName>ADDRX</displayName>
|
|
<description>eUSCI_Bx I2C Received Address Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDRX</name>
|
|
<description>Received Address Register</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0xA</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxADDMASK</name>
|
|
<displayName>ADDMASK</displayName>
|
|
<description>eUSCI_Bx I2C Address Mask Register</description>
|
|
<addressOffset>0x1E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000003ff</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDMASK</name>
|
|
<description>Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated.
|
|
Modify only when UCSWRST = 1.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0xA</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxI2CSA</name>
|
|
<displayName>I2CSA</displayName>
|
|
<description>eUSCI_Bx I2C Slave Address Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>I2CSA</name>
|
|
<description>I2C slave address</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0xA</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxIE</name>
|
|
<displayName>IE</displayName>
|
|
<description>eUSCI_Bx Interrupt Enable Register</description>
|
|
<addressOffset>0x2A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCRXIE0</name>
|
|
<description>Receive interrupt enable 0</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIE0_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIE0_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIE0</name>
|
|
<description>Transmit interrupt enable 0</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIE0_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIE0_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTTIE</name>
|
|
<description>START condition interrupt enable</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTTIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTTIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTPIE</name>
|
|
<description>STOP condition interrupt enable</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTPIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTPIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCALIE</name>
|
|
<description>Arbitration lost interrupt enable</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCALIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCALIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCNACKIE</name>
|
|
<description>Not-acknowledge interrupt enable</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCNACKIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCNACKIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBCNTIE</name>
|
|
<description>Byte counter interrupt enable</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCBCNTIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBCNTIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCCLTOIE</name>
|
|
<description>Clock low timeout interrupt enable</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCCLTOIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCCLTOIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCRXIE1</name>
|
|
<description>Receive interrupt enable 1</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIE1_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIE1_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIE1</name>
|
|
<description>Transmit interrupt enable 1</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIE1_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIE1_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCRXIE2</name>
|
|
<description>Receive interrupt enable 2</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIE2_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIE2_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIE2</name>
|
|
<description>Transmit interrupt enable 2</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIE2_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIE2_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCRXIE3</name>
|
|
<description>Receive interrupt enable 3</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIE3_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIE3_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIE3</name>
|
|
<description>Transmit interrupt enable 3</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIE3_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIE3_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBIT9IE</name>
|
|
<description>Bit position 9 interrupt enable</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCBIT9IE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBIT9IE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxIFG</name>
|
|
<displayName>IFG</displayName>
|
|
<description>eUSCI_Bx Interrupt Flag Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000002</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCRXIFG0</name>
|
|
<description>eUSCI_B receive interrupt flag 0</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG0_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG0_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIFG0</name>
|
|
<description>eUSCI_B transmit interrupt flag 0</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG0_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG0_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTTIFG</name>
|
|
<description>START condition interrupt flag</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTTIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTTIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCSTPIFG</name>
|
|
<description>STOP condition interrupt flag</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCSTPIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCSTPIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCALIFG</name>
|
|
<description>Arbitration lost interrupt flag</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCALIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCALIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCNACKIFG</name>
|
|
<description>Not-acknowledge received interrupt flag</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCNACKIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCNACKIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBCNTIFG</name>
|
|
<description>Byte counter interrupt flag</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCBCNTIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBCNTIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCCLTOIFG</name>
|
|
<description>Clock low timeout interrupt flag</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCCLTOIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCCLTOIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCRXIFG1</name>
|
|
<description>eUSCI_B receive interrupt flag 1</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG1_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG1_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIFG1</name>
|
|
<description>eUSCI_B transmit interrupt flag 1</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG1_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG1_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCRXIFG2</name>
|
|
<description>eUSCI_B receive interrupt flag 2</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG2_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG2_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIFG2</name>
|
|
<description>eUSCI_B transmit interrupt flag 2</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG2_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG2_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCRXIFG3</name>
|
|
<description>eUSCI_B receive interrupt flag 3</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG3_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCRXIFG3_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCTXIFG3</name>
|
|
<description>eUSCI_B transmit interrupt flag 3</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG3_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCTXIFG3_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCBIT9IFG</name>
|
|
<description>Bit position 9 interrupt flag</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UCBIT9IFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCBIT9IFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UCBxIV</name>
|
|
<displayName>IV</displayName>
|
|
<description>eUSCI_Bx Interrupt Vector Register</description>
|
|
<addressOffset>0x2E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCIV</name>
|
|
<description>eUSCI_B interrupt vector value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>UCIV_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>UCIV_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_2</name>
|
|
<description>Interrupt Source: Arbitration lost; Interrupt Flag: UCALIFG; Interrupt Priority: Highest</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_4</name>
|
|
<description>Interrupt Source: Not acknowledgment; Interrupt Flag: UCNACKIFG</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_6</name>
|
|
<description>Interrupt Source: Start condition received; Interrupt Flag: UCSTTIFG</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_8</name>
|
|
<description>Interrupt Source: Stop condition received; Interrupt Flag: UCSTPIFG</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_10</name>
|
|
<description>Interrupt Source: Slave 3 Data received; Interrupt Flag: UCRXIFG3</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_12</name>
|
|
<description>Interrupt Source: Slave 3 Transmit buffer empty; Interrupt Flag: UCTXIFG3</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_14</name>
|
|
<description>Interrupt Source: Slave 2 Data received; Interrupt Flag: UCRXIFG2</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_16</name>
|
|
<description>Interrupt Source: Slave 2 Transmit buffer empty; Interrupt Flag: UCTXIFG2</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_18</name>
|
|
<description>Interrupt Source: Slave 1 Data received; Interrupt Flag: UCRXIFG1</description>
|
|
<value>18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_20</name>
|
|
<description>Interrupt Source: Slave 1 Transmit buffer empty; Interrupt Flag: UCTXIFG1</description>
|
|
<value>20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_22</name>
|
|
<description>Interrupt Source: Data received; Interrupt Flag: UCRXIFG0</description>
|
|
<value>22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_24</name>
|
|
<description>Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG0</description>
|
|
<value>24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_26</name>
|
|
<description>Interrupt Source: Byte counter zero; Interrupt Flag: UCBCNTIFG</description>
|
|
<value>26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_28</name>
|
|
<description>Interrupt Source: Clock low timeout; Interrupt Flag: UCCLTOIFG</description>
|
|
<value>28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UCIV_30</name>
|
|
<description>Interrupt Source: Nineth bit position; Interrupt Flag: UCBIT9IFG; Priority: Lowest</description>
|
|
<value>30</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>REF_A</name>
|
|
<version>356.0</version>
|
|
<description>REF_A</description>
|
|
<baseAddress>0x40003000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xC</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>REFCTL0</name>
|
|
<displayName>CTL0</displayName>
|
|
<description>REF Control Register 0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>REFON</name>
|
|
<description>Reference enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFON_0</name>
|
|
<description>Disables reference if no other reference requests are pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFON_1</name>
|
|
<description>Enables reference in static mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFOUT</name>
|
|
<description>Reference output buffer</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFOUT_0</name>
|
|
<description>Reference output not available externally</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFOUT_1</name>
|
|
<description>Reference output available externally. If ADC14REFBURST = 0, output is available continuously. If ADC14REFBURST = 1, output is available only during an ADC14 conversion.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFTCOFF</name>
|
|
<description>Temperature sensor disabled</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFTCOFF_0</name>
|
|
<description>Temperature sensor enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTCOFF_1</name>
|
|
<description>Temperature sensor disabled to save power</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFVSEL</name>
|
|
<description>Reference voltage level select</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFVSEL_0</name>
|
|
<description>1.2 V available when reference requested or REFON = 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFVSEL_1</name>
|
|
<description>1.45 V available when reference requested or REFON = 1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFVSEL_3</name>
|
|
<description>2.5 V available when reference requested or REFON = 1</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFGENOT</name>
|
|
<description>Reference generator one-time trigger</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFGENOT_0</name>
|
|
<description>No trigger</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFGENOT_1</name>
|
|
<description>Generation of the reference voltage is started by writing 1 or by a hardware trigger</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFBGOT</name>
|
|
<description>Bandgap and bandgap buffer one-time trigger</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFBGOT_0</name>
|
|
<description>No trigger</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFBGOT_1</name>
|
|
<description>Generation of the bandgap voltage is started by writing 1 or by a hardware trigger</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFGENACT</name>
|
|
<description>Reference generator active</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>REFGENACT_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>REFGENACT_0</name>
|
|
<description>Reference generator not active</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFGENACT_1</name>
|
|
<description>Reference generator active</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFBGACT</name>
|
|
<description>Reference bandgap active</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>REFBGACT_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>REFBGACT_0</name>
|
|
<description>Reference bandgap buffer not active</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFBGACT_1</name>
|
|
<description>Reference bandgap buffer active</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFGENBUSY</name>
|
|
<description>Reference generator busy</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>REFGENBUSY_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>REFGENBUSY_0</name>
|
|
<description>Reference generator not busy</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFGENBUSY_1</name>
|
|
<description>Reference generator busy</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BGMODE</name>
|
|
<description>Bandgap mode</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>BGMODE_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>BGMODE_0</name>
|
|
<description>Static mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BGMODE_1</name>
|
|
<description>Sampled mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFGENRDY</name>
|
|
<description>Variable reference voltage ready status</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>REFGENRDY_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>REFGENRDY_0</name>
|
|
<description>Reference voltage output is not ready to be used</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFGENRDY_1</name>
|
|
<description>Reference voltage output is ready to be used</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFBGRDY</name>
|
|
<description>Buffered bandgap voltage ready status</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>REFBGRDY_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>REFBGRDY_0</name>
|
|
<description>Buffered bandgap voltage is not ready to be used</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFBGRDY_1</name>
|
|
<description>Buffered bandgap voltage is ready to be used</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>COMP_E0</name>
|
|
<version>356.0</version>
|
|
<description>COMP_E0</description>
|
|
<baseAddress>0x40003400</baseAddress>
|
|
<interrupt>
|
|
<name>COMP_E0_IRQ</name>
|
|
<description>COMP_E0 Interrupt</description>
|
|
<value>6</value>
|
|
</interrupt>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CExCTL0</name>
|
|
<displayName>CTL0</displayName>
|
|
<description>Comparator Control Register 0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEIPSEL</name>
|
|
<description>Channel input selected for the V+ terminal</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_0</name>
|
|
<description>Channel 0 selected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_1</name>
|
|
<description>Channel 1 selected</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_2</name>
|
|
<description>Channel 2 selected</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_3</name>
|
|
<description>Channel 3 selected</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_4</name>
|
|
<description>Channel 4 selected</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_5</name>
|
|
<description>Channel 5 selected</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_6</name>
|
|
<description>Channel 6 selected</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_7</name>
|
|
<description>Channel 7 selected</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_8</name>
|
|
<description>Channel 8 selected</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_9</name>
|
|
<description>Channel 9 selected</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_10</name>
|
|
<description>Channel 10 selected</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_11</name>
|
|
<description>Channel 11 selected</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_12</name>
|
|
<description>Channel 12 selected</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_13</name>
|
|
<description>Channel 13 selected</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_14</name>
|
|
<description>Channel 14 selected</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_15</name>
|
|
<description>Channel 15 selected</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEIPEN</name>
|
|
<description>Channel input enable for the V+ terminal</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEIPEN_0</name>
|
|
<description>Selected analog input channel for V+ terminal is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPEN_1</name>
|
|
<description>Selected analog input channel for V+ terminal is enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEIMSEL</name>
|
|
<description>Channel input selected for the - terminal</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_0</name>
|
|
<description>Channel 0 selected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_1</name>
|
|
<description>Channel 1 selected</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_2</name>
|
|
<description>Channel 2 selected</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_3</name>
|
|
<description>Channel 3 selected</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_4</name>
|
|
<description>Channel 4 selected</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_5</name>
|
|
<description>Channel 5 selected</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_6</name>
|
|
<description>Channel 6 selected</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_7</name>
|
|
<description>Channel 7 selected</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_8</name>
|
|
<description>Channel 8 selected</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_9</name>
|
|
<description>Channel 9 selected</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_10</name>
|
|
<description>Channel 10 selected</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_11</name>
|
|
<description>Channel 11 selected</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_12</name>
|
|
<description>Channel 12 selected</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_13</name>
|
|
<description>Channel 13 selected</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_14</name>
|
|
<description>Channel 14 selected</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_15</name>
|
|
<description>Channel 15 selected</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEIMEN</name>
|
|
<description>Channel input enable for the - terminal</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEIMEN_0</name>
|
|
<description>Selected analog input channel for V- terminal is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMEN_1</name>
|
|
<description>Selected analog input channel for V- terminal is enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CExCTL1</name>
|
|
<displayName>CTL1</displayName>
|
|
<description>Comparator Control Register 1</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEOUT</name>
|
|
<description>Comparator output value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CEOUTPOL</name>
|
|
<description>Comparator output polarity</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEOUTPOL_0</name>
|
|
<description>Noninverted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEOUTPOL_1</name>
|
|
<description>Inverted</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEF</name>
|
|
<description>Comparator output filter</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEF_0</name>
|
|
<description>Comparator output is not filtered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEF_1</name>
|
|
<description>Comparator output is filtered</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEIES</name>
|
|
<description>Interrupt edge select for CEIIFG and CEIFG</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEIES_0</name>
|
|
<description>Rising edge for CEIFG, falling edge for CEIIFG</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIES_1</name>
|
|
<description>Falling edge for CEIFG, rising edge for CEIIFG</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CESHORT</name>
|
|
<description>Input short</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CESHORT_0</name>
|
|
<description>Inputs not shorted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CESHORT_1</name>
|
|
<description>Inputs shorted</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEEX</name>
|
|
<description>Exchange</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CEFDLY</name>
|
|
<description>Filter delay</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEFDLY_0</name>
|
|
<description>Typical filter delay of TBD (450) ns</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEFDLY_1</name>
|
|
<description>Typical filter delay of TBD (900) ns</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEFDLY_2</name>
|
|
<description>Typical filter delay of TBD (1800) ns</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEFDLY_3</name>
|
|
<description>Typical filter delay of TBD (3600) ns</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPWRMD</name>
|
|
<description>Power Mode</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPWRMD_0</name>
|
|
<description>High-speed mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPWRMD_1</name>
|
|
<description>Normal mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPWRMD_2</name>
|
|
<description>Ultra-low power mode</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEON</name>
|
|
<description>Comparator On</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEON_0</name>
|
|
<description>Off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEON_1</name>
|
|
<description>On</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEMRVL</name>
|
|
<description>This bit is valid of CEMRVS is set to 1</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEMRVL_0</name>
|
|
<description>VREF0 is selected if CERS = 00, 01, or 10</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEMRVL_1</name>
|
|
<description>VREF1 is selected if CERS = 00, 01, or 10</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEMRVS</name>
|
|
<description>This bit defines if the comparator output selects between VREF0 or VREF1 if CERS = 00, 01, or 10.</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEMRVS_0</name>
|
|
<description>Comparator output state selects between VREF0 or VREF1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEMRVS_1</name>
|
|
<description>CEMRVL selects between VREF0 or VREF1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CExCTL2</name>
|
|
<displayName>CTL2</displayName>
|
|
<description>Comparator Control Register 2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEREF0</name>
|
|
<description>Reference resistor tap 0</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEREF0_0</name>
|
|
<description>Reference resistor tap for setting 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_1</name>
|
|
<description>Reference resistor tap for setting 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_2</name>
|
|
<description>Reference resistor tap for setting 2.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_3</name>
|
|
<description>Reference resistor tap for setting 3.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_4</name>
|
|
<description>Reference resistor tap for setting 4.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_5</name>
|
|
<description>Reference resistor tap for setting 5.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_6</name>
|
|
<description>Reference resistor tap for setting 6.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_7</name>
|
|
<description>Reference resistor tap for setting 7.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_8</name>
|
|
<description>Reference resistor tap for setting 8.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_9</name>
|
|
<description>Reference resistor tap for setting 9.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_10</name>
|
|
<description>Reference resistor tap for setting 10.</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_11</name>
|
|
<description>Reference resistor tap for setting 11.</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_12</name>
|
|
<description>Reference resistor tap for setting 12.</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_13</name>
|
|
<description>Reference resistor tap for setting 13.</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_14</name>
|
|
<description>Reference resistor tap for setting 14.</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_15</name>
|
|
<description>Reference resistor tap for setting 15.</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_16</name>
|
|
<description>Reference resistor tap for setting 16.</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_17</name>
|
|
<description>Reference resistor tap for setting 17.</description>
|
|
<value>17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_18</name>
|
|
<description>Reference resistor tap for setting 18.</description>
|
|
<value>18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_19</name>
|
|
<description>Reference resistor tap for setting 19.</description>
|
|
<value>19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_20</name>
|
|
<description>Reference resistor tap for setting 20.</description>
|
|
<value>20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_21</name>
|
|
<description>Reference resistor tap for setting 21.</description>
|
|
<value>21</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_22</name>
|
|
<description>Reference resistor tap for setting 22.</description>
|
|
<value>22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_23</name>
|
|
<description>Reference resistor tap for setting 23.</description>
|
|
<value>23</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_24</name>
|
|
<description>Reference resistor tap for setting 24.</description>
|
|
<value>24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_25</name>
|
|
<description>Reference resistor tap for setting 25.</description>
|
|
<value>25</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_26</name>
|
|
<description>Reference resistor tap for setting 26.</description>
|
|
<value>26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_27</name>
|
|
<description>Reference resistor tap for setting 27.</description>
|
|
<value>27</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_28</name>
|
|
<description>Reference resistor tap for setting 28.</description>
|
|
<value>28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_29</name>
|
|
<description>Reference resistor tap for setting 29.</description>
|
|
<value>29</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_30</name>
|
|
<description>Reference resistor tap for setting 30.</description>
|
|
<value>30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_31</name>
|
|
<description>Reference resistor tap for setting 31.</description>
|
|
<value>31</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CERSEL</name>
|
|
<description>Reference select</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CERSEL_0</name>
|
|
<description>When CEEX = 0, VREF is applied to the V+ terminal; When CEEX = 1, VREF is applied to the V- terminal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CERSEL_1</name>
|
|
<description>When CEEX = 0, VREF is applied to the V- terminal; When CEEX = 1, VREF is applied to the V+ terminal</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CERS</name>
|
|
<description>Reference source</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CERS_0</name>
|
|
<description>No current is drawn by the reference circuitry</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CERS_1</name>
|
|
<description>VCC applied to the resistor ladder</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CERS_2</name>
|
|
<description>Shared reference voltage applied to the resistor ladder</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CERS_3</name>
|
|
<description>Shared reference voltage supplied to V(CREF). Resistor ladder is off</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEREF1</name>
|
|
<description>Reference resistor tap 1</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEREF1_0</name>
|
|
<description>Reference resistor tap for setting 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_1</name>
|
|
<description>Reference resistor tap for setting 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_2</name>
|
|
<description>Reference resistor tap for setting 2.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_3</name>
|
|
<description>Reference resistor tap for setting 3.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_4</name>
|
|
<description>Reference resistor tap for setting 4.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_5</name>
|
|
<description>Reference resistor tap for setting 5.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_6</name>
|
|
<description>Reference resistor tap for setting 6.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_7</name>
|
|
<description>Reference resistor tap for setting 7.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_8</name>
|
|
<description>Reference resistor tap for setting 8.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_9</name>
|
|
<description>Reference resistor tap for setting 9.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_10</name>
|
|
<description>Reference resistor tap for setting 10.</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_11</name>
|
|
<description>Reference resistor tap for setting 11.</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_12</name>
|
|
<description>Reference resistor tap for setting 12.</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_13</name>
|
|
<description>Reference resistor tap for setting 13.</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_14</name>
|
|
<description>Reference resistor tap for setting 14.</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_15</name>
|
|
<description>Reference resistor tap for setting 15.</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_16</name>
|
|
<description>Reference resistor tap for setting 16.</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_17</name>
|
|
<description>Reference resistor tap for setting 17.</description>
|
|
<value>17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_18</name>
|
|
<description>Reference resistor tap for setting 18.</description>
|
|
<value>18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_19</name>
|
|
<description>Reference resistor tap for setting 19.</description>
|
|
<value>19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_20</name>
|
|
<description>Reference resistor tap for setting 20.</description>
|
|
<value>20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_21</name>
|
|
<description>Reference resistor tap for setting 21.</description>
|
|
<value>21</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_22</name>
|
|
<description>Reference resistor tap for setting 22.</description>
|
|
<value>22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_23</name>
|
|
<description>Reference resistor tap for setting 23.</description>
|
|
<value>23</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_24</name>
|
|
<description>Reference resistor tap for setting 24.</description>
|
|
<value>24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_25</name>
|
|
<description>Reference resistor tap for setting 25.</description>
|
|
<value>25</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_26</name>
|
|
<description>Reference resistor tap for setting 26.</description>
|
|
<value>26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_27</name>
|
|
<description>Reference resistor tap for setting 27.</description>
|
|
<value>27</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_28</name>
|
|
<description>Reference resistor tap for setting 28.</description>
|
|
<value>28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_29</name>
|
|
<description>Reference resistor tap for setting 29.</description>
|
|
<value>29</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_30</name>
|
|
<description>Reference resistor tap for setting 30.</description>
|
|
<value>30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_31</name>
|
|
<description>Reference resistor tap for setting 31.</description>
|
|
<value>31</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEREFL</name>
|
|
<description>Reference voltage level</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEREFL_0</name>
|
|
<description>Reference amplifier is disabled. No reference voltage is requested</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREFL_1</name>
|
|
<description>1.2 V is selected as shared reference voltage input</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREFL_2</name>
|
|
<description>2.0 V is selected as shared reference voltage input</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREFL_3</name>
|
|
<description>2.5 V is selected as shared reference voltage input</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEREFACC</name>
|
|
<description>Reference accuracy</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEREFACC_0</name>
|
|
<description>Static mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREFACC_1</name>
|
|
<description>Clocked (low power, low accuracy) mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CExCTL3</name>
|
|
<displayName>CTL3</displayName>
|
|
<description>Comparator Control Register 3</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEPD0</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD0_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD0_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPD1</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD1_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD1_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPD2</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD2_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD2_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPD3</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD3_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD3_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPD4</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD4_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD4_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPD5</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD5_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD5_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPD6</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD6_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD6_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPD7</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD7_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD7_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPD8</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD8_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD8_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPD9</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD9_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD9_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPD10</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD10_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD10_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPD11</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD11_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD11_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPD12</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD12_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD12_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPD13</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD13_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD13_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPD14</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD14_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD14_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPD15</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD15_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD15_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CExINT</name>
|
|
<displayName>INT</displayName>
|
|
<description>Comparator Interrupt Control Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEIFG</name>
|
|
<description>Comparator output interrupt flag</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEIIFG</name>
|
|
<description>Comparator output inverted interrupt flag</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEIIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CERDYIFG</name>
|
|
<description>Comparator ready interrupt flag</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CERDYIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CERDYIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEIE</name>
|
|
<description>Comparator output interrupt enable</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEIIE</name>
|
|
<description>Comparator output interrupt enable inverted polarity</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEIIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CERDYIE</name>
|
|
<description>Comparator ready interrupt enable</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CERDYIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CERDYIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CExIV</name>
|
|
<displayName>IV</displayName>
|
|
<description>Comparator Interrupt Vector Word Register</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEIV</name>
|
|
<description>Comparator interrupt vector word register</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>CEIV_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>CEIV_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIV_2</name>
|
|
<description>Interrupt Source: CEOUT interrupt; Interrupt Flag: CEIFG; Interrupt Priority: Highest</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIV_4</name>
|
|
<description>Interrupt Source: CEOUT interrupt inverted polarity; Interrupt Flag: CEIIFG</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIV_10</name>
|
|
<description>Interrupt Source: Comparator ready interrupt; Interrupt Flag: CERDYIFG; Interrupt Priority: Lowest</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>COMP_E1</name>
|
|
<version>356.0</version>
|
|
<description>COMP_E1</description>
|
|
<baseAddress>0x40003800</baseAddress>
|
|
<interrupt>
|
|
<name>COMP_E1_IRQ</name>
|
|
<description>COMP_E1 Interrupt</description>
|
|
<value>7</value>
|
|
</interrupt>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CExCTL0</name>
|
|
<displayName>CTL0</displayName>
|
|
<description>Comparator Control Register 0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEIPSEL</name>
|
|
<description>Channel input selected for the V+ terminal</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_0</name>
|
|
<description>Channel 0 selected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_1</name>
|
|
<description>Channel 1 selected</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_2</name>
|
|
<description>Channel 2 selected</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_3</name>
|
|
<description>Channel 3 selected</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_4</name>
|
|
<description>Channel 4 selected</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_5</name>
|
|
<description>Channel 5 selected</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_6</name>
|
|
<description>Channel 6 selected</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_7</name>
|
|
<description>Channel 7 selected</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_8</name>
|
|
<description>Channel 8 selected</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_9</name>
|
|
<description>Channel 9 selected</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_10</name>
|
|
<description>Channel 10 selected</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_11</name>
|
|
<description>Channel 11 selected</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_12</name>
|
|
<description>Channel 12 selected</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_13</name>
|
|
<description>Channel 13 selected</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_14</name>
|
|
<description>Channel 14 selected</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPSEL_15</name>
|
|
<description>Channel 15 selected</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEIPEN</name>
|
|
<description>Channel input enable for the V+ terminal</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEIPEN_0</name>
|
|
<description>Selected analog input channel for V+ terminal is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIPEN_1</name>
|
|
<description>Selected analog input channel for V+ terminal is enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEIMSEL</name>
|
|
<description>Channel input selected for the - terminal</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_0</name>
|
|
<description>Channel 0 selected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_1</name>
|
|
<description>Channel 1 selected</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_2</name>
|
|
<description>Channel 2 selected</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_3</name>
|
|
<description>Channel 3 selected</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_4</name>
|
|
<description>Channel 4 selected</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_5</name>
|
|
<description>Channel 5 selected</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_6</name>
|
|
<description>Channel 6 selected</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_7</name>
|
|
<description>Channel 7 selected</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_8</name>
|
|
<description>Channel 8 selected</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_9</name>
|
|
<description>Channel 9 selected</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_10</name>
|
|
<description>Channel 10 selected</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_11</name>
|
|
<description>Channel 11 selected</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_12</name>
|
|
<description>Channel 12 selected</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_13</name>
|
|
<description>Channel 13 selected</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_14</name>
|
|
<description>Channel 14 selected</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMSEL_15</name>
|
|
<description>Channel 15 selected</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEIMEN</name>
|
|
<description>Channel input enable for the - terminal</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEIMEN_0</name>
|
|
<description>Selected analog input channel for V- terminal is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIMEN_1</name>
|
|
<description>Selected analog input channel for V- terminal is enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CExCTL1</name>
|
|
<displayName>CTL1</displayName>
|
|
<description>Comparator Control Register 1</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEOUT</name>
|
|
<description>Comparator output value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CEOUTPOL</name>
|
|
<description>Comparator output polarity</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEOUTPOL_0</name>
|
|
<description>Noninverted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEOUTPOL_1</name>
|
|
<description>Inverted</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEF</name>
|
|
<description>Comparator output filter</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEF_0</name>
|
|
<description>Comparator output is not filtered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEF_1</name>
|
|
<description>Comparator output is filtered</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEIES</name>
|
|
<description>Interrupt edge select for CEIIFG and CEIFG</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEIES_0</name>
|
|
<description>Rising edge for CEIFG, falling edge for CEIIFG</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIES_1</name>
|
|
<description>Falling edge for CEIFG, rising edge for CEIIFG</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CESHORT</name>
|
|
<description>Input short</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CESHORT_0</name>
|
|
<description>Inputs not shorted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CESHORT_1</name>
|
|
<description>Inputs shorted</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEEX</name>
|
|
<description>Exchange</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CEFDLY</name>
|
|
<description>Filter delay</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEFDLY_0</name>
|
|
<description>Typical filter delay of TBD (450) ns</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEFDLY_1</name>
|
|
<description>Typical filter delay of TBD (900) ns</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEFDLY_2</name>
|
|
<description>Typical filter delay of TBD (1800) ns</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEFDLY_3</name>
|
|
<description>Typical filter delay of TBD (3600) ns</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPWRMD</name>
|
|
<description>Power Mode</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPWRMD_0</name>
|
|
<description>High-speed mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPWRMD_1</name>
|
|
<description>Normal mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPWRMD_2</name>
|
|
<description>Ultra-low power mode</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEON</name>
|
|
<description>Comparator On</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEON_0</name>
|
|
<description>Off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEON_1</name>
|
|
<description>On</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEMRVL</name>
|
|
<description>This bit is valid of CEMRVS is set to 1</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEMRVL_0</name>
|
|
<description>VREF0 is selected if CERS = 00, 01, or 10</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEMRVL_1</name>
|
|
<description>VREF1 is selected if CERS = 00, 01, or 10</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEMRVS</name>
|
|
<description>This bit defines if the comparator output selects between VREF0 or VREF1 if CERS = 00, 01, or 10.</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEMRVS_0</name>
|
|
<description>Comparator output state selects between VREF0 or VREF1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEMRVS_1</name>
|
|
<description>CEMRVL selects between VREF0 or VREF1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CExCTL2</name>
|
|
<displayName>CTL2</displayName>
|
|
<description>Comparator Control Register 2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEREF0</name>
|
|
<description>Reference resistor tap 0</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEREF0_0</name>
|
|
<description>Reference resistor tap for setting 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_1</name>
|
|
<description>Reference resistor tap for setting 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_2</name>
|
|
<description>Reference resistor tap for setting 2.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_3</name>
|
|
<description>Reference resistor tap for setting 3.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_4</name>
|
|
<description>Reference resistor tap for setting 4.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_5</name>
|
|
<description>Reference resistor tap for setting 5.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_6</name>
|
|
<description>Reference resistor tap for setting 6.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_7</name>
|
|
<description>Reference resistor tap for setting 7.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_8</name>
|
|
<description>Reference resistor tap for setting 8.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_9</name>
|
|
<description>Reference resistor tap for setting 9.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_10</name>
|
|
<description>Reference resistor tap for setting 10.</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_11</name>
|
|
<description>Reference resistor tap for setting 11.</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_12</name>
|
|
<description>Reference resistor tap for setting 12.</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_13</name>
|
|
<description>Reference resistor tap for setting 13.</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_14</name>
|
|
<description>Reference resistor tap for setting 14.</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_15</name>
|
|
<description>Reference resistor tap for setting 15.</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_16</name>
|
|
<description>Reference resistor tap for setting 16.</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_17</name>
|
|
<description>Reference resistor tap for setting 17.</description>
|
|
<value>17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_18</name>
|
|
<description>Reference resistor tap for setting 18.</description>
|
|
<value>18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_19</name>
|
|
<description>Reference resistor tap for setting 19.</description>
|
|
<value>19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_20</name>
|
|
<description>Reference resistor tap for setting 20.</description>
|
|
<value>20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_21</name>
|
|
<description>Reference resistor tap for setting 21.</description>
|
|
<value>21</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_22</name>
|
|
<description>Reference resistor tap for setting 22.</description>
|
|
<value>22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_23</name>
|
|
<description>Reference resistor tap for setting 23.</description>
|
|
<value>23</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_24</name>
|
|
<description>Reference resistor tap for setting 24.</description>
|
|
<value>24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_25</name>
|
|
<description>Reference resistor tap for setting 25.</description>
|
|
<value>25</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_26</name>
|
|
<description>Reference resistor tap for setting 26.</description>
|
|
<value>26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_27</name>
|
|
<description>Reference resistor tap for setting 27.</description>
|
|
<value>27</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_28</name>
|
|
<description>Reference resistor tap for setting 28.</description>
|
|
<value>28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_29</name>
|
|
<description>Reference resistor tap for setting 29.</description>
|
|
<value>29</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_30</name>
|
|
<description>Reference resistor tap for setting 30.</description>
|
|
<value>30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF0_31</name>
|
|
<description>Reference resistor tap for setting 31.</description>
|
|
<value>31</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CERSEL</name>
|
|
<description>Reference select</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CERSEL_0</name>
|
|
<description>When CEEX = 0, VREF is applied to the V+ terminal; When CEEX = 1, VREF is applied to the V- terminal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CERSEL_1</name>
|
|
<description>When CEEX = 0, VREF is applied to the V- terminal; When CEEX = 1, VREF is applied to the V+ terminal</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CERS</name>
|
|
<description>Reference source</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CERS_0</name>
|
|
<description>No current is drawn by the reference circuitry</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CERS_1</name>
|
|
<description>VCC applied to the resistor ladder</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CERS_2</name>
|
|
<description>Shared reference voltage applied to the resistor ladder</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CERS_3</name>
|
|
<description>Shared reference voltage supplied to V(CREF). Resistor ladder is off</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEREF1</name>
|
|
<description>Reference resistor tap 1</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEREF1_0</name>
|
|
<description>Reference resistor tap for setting 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_1</name>
|
|
<description>Reference resistor tap for setting 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_2</name>
|
|
<description>Reference resistor tap for setting 2.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_3</name>
|
|
<description>Reference resistor tap for setting 3.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_4</name>
|
|
<description>Reference resistor tap for setting 4.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_5</name>
|
|
<description>Reference resistor tap for setting 5.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_6</name>
|
|
<description>Reference resistor tap for setting 6.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_7</name>
|
|
<description>Reference resistor tap for setting 7.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_8</name>
|
|
<description>Reference resistor tap for setting 8.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_9</name>
|
|
<description>Reference resistor tap for setting 9.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_10</name>
|
|
<description>Reference resistor tap for setting 10.</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_11</name>
|
|
<description>Reference resistor tap for setting 11.</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_12</name>
|
|
<description>Reference resistor tap for setting 12.</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_13</name>
|
|
<description>Reference resistor tap for setting 13.</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_14</name>
|
|
<description>Reference resistor tap for setting 14.</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_15</name>
|
|
<description>Reference resistor tap for setting 15.</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_16</name>
|
|
<description>Reference resistor tap for setting 16.</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_17</name>
|
|
<description>Reference resistor tap for setting 17.</description>
|
|
<value>17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_18</name>
|
|
<description>Reference resistor tap for setting 18.</description>
|
|
<value>18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_19</name>
|
|
<description>Reference resistor tap for setting 19.</description>
|
|
<value>19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_20</name>
|
|
<description>Reference resistor tap for setting 20.</description>
|
|
<value>20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_21</name>
|
|
<description>Reference resistor tap for setting 21.</description>
|
|
<value>21</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_22</name>
|
|
<description>Reference resistor tap for setting 22.</description>
|
|
<value>22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_23</name>
|
|
<description>Reference resistor tap for setting 23.</description>
|
|
<value>23</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_24</name>
|
|
<description>Reference resistor tap for setting 24.</description>
|
|
<value>24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_25</name>
|
|
<description>Reference resistor tap for setting 25.</description>
|
|
<value>25</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_26</name>
|
|
<description>Reference resistor tap for setting 26.</description>
|
|
<value>26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_27</name>
|
|
<description>Reference resistor tap for setting 27.</description>
|
|
<value>27</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_28</name>
|
|
<description>Reference resistor tap for setting 28.</description>
|
|
<value>28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_29</name>
|
|
<description>Reference resistor tap for setting 29.</description>
|
|
<value>29</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_30</name>
|
|
<description>Reference resistor tap for setting 30.</description>
|
|
<value>30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREF1_31</name>
|
|
<description>Reference resistor tap for setting 31.</description>
|
|
<value>31</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEREFL</name>
|
|
<description>Reference voltage level</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEREFL_0</name>
|
|
<description>Reference amplifier is disabled. No reference voltage is requested</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREFL_1</name>
|
|
<description>1.2 V is selected as shared reference voltage input</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREFL_2</name>
|
|
<description>2.0 V is selected as shared reference voltage input</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREFL_3</name>
|
|
<description>2.5 V is selected as shared reference voltage input</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEREFACC</name>
|
|
<description>Reference accuracy</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEREFACC_0</name>
|
|
<description>Static mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEREFACC_1</name>
|
|
<description>Clocked (low power, low accuracy) mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CExCTL3</name>
|
|
<displayName>CTL3</displayName>
|
|
<description>Comparator Control Register 3</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEPD0</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD0_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD0_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPD1</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD1_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD1_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPD2</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD2_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD2_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPD3</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD3_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD3_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPD4</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD4_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD4_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPD5</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD5_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD5_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPD6</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD6_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD6_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPD7</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD7_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD7_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPD8</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD8_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD8_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPD9</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD9_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD9_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPD10</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD10_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD10_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPD11</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD11_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD11_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPD12</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD12_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD12_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPD13</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD13_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD13_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPD14</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD14_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD14_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEPD15</name>
|
|
<description>Port disable</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEPD15_0</name>
|
|
<description>The input buffer is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEPD15_1</name>
|
|
<description>The input buffer is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CExINT</name>
|
|
<displayName>INT</displayName>
|
|
<description>Comparator Interrupt Control Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEIFG</name>
|
|
<description>Comparator output interrupt flag</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEIIFG</name>
|
|
<description>Comparator output inverted interrupt flag</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEIIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CERDYIFG</name>
|
|
<description>Comparator ready interrupt flag</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CERDYIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CERDYIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEIE</name>
|
|
<description>Comparator output interrupt enable</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEIIE</name>
|
|
<description>Comparator output interrupt enable inverted polarity</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CEIIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CERDYIE</name>
|
|
<description>Comparator ready interrupt enable</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CERDYIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CERDYIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CExIV</name>
|
|
<displayName>IV</displayName>
|
|
<description>Comparator Interrupt Vector Word Register</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEIV</name>
|
|
<description>Comparator interrupt vector word register</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>CEIV_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>CEIV_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIV_2</name>
|
|
<description>Interrupt Source: CEOUT interrupt; Interrupt Flag: CEIFG; Interrupt Priority: Highest</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIV_4</name>
|
|
<description>Interrupt Source: CEOUT interrupt inverted polarity; Interrupt Flag: CEIIFG</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEIV_10</name>
|
|
<description>Interrupt Source: Comparator ready interrupt; Interrupt Flag: CERDYIFG; Interrupt Priority: Lowest</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>AES256</name>
|
|
<version>356.0</version>
|
|
<description>AES256</description>
|
|
<baseAddress>0x40003C00</baseAddress>
|
|
<interrupt>
|
|
<name>AES256_IRQ</name>
|
|
<description>AES256 Interrupt</description>
|
|
<value>28</value>
|
|
</interrupt>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>AESACTL0</name>
|
|
<displayName>CTL0</displayName>
|
|
<description>AES Accelerator Control Register 0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AESOPx</name>
|
|
<description>AES operation</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AESOPx_0</name>
|
|
<description>Encryption</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AESOPx_1</name>
|
|
<description>Decryption. The provided key is the same key used for encryption</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AESOPx_2</name>
|
|
<description>Generate first round key required for decryption</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AESOPx_3</name>
|
|
<description>Decryption. The provided key is the first round key required for decryption</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AESKLx</name>
|
|
<description>AES key length</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AESKLx_0</name>
|
|
<description>AES128. The key size is 128 bit</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AESKLx_1</name>
|
|
<description>AES192. The key size is 192 bit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AESKLx_2</name>
|
|
<description>AES256. The key size is 256 bit</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AESCMx</name>
|
|
<description>AES cipher mode select</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AESCMx_0</name>
|
|
<description>ECB</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AESCMx_1</name>
|
|
<description>CBC</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AESCMx_2</name>
|
|
<description>OFB</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AESCMx_3</name>
|
|
<description>CFB</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AESSWRST</name>
|
|
<description>AES software reset</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AESSWRST_0</name>
|
|
<description>No reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AESSWRST_1</name>
|
|
<description>Reset AES accelerator module</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AESRDYIFG</name>
|
|
<description>AES ready interrupt flag</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AESRDYIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AESRDYIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AESERRFG</name>
|
|
<description>AES error flag</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AESERRFG_0</name>
|
|
<description>No error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AESERRFG_1</name>
|
|
<description>Error occurred</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AESRDYIE</name>
|
|
<description>AES ready interrupt enable</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AESRDYIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AESRDYIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AESCMEN</name>
|
|
<description>AES cipher mode enable</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AESCMEN_0</name>
|
|
<description>No DMA triggers are generated</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AESCMEN_1</name>
|
|
<description>DMA ciphermode support operation is enabled and the corresponding DMA triggers are generated</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AESACTL1</name>
|
|
<displayName>CTL1</displayName>
|
|
<description>AES Accelerator Control Register 1</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AESBLKCNTx</name>
|
|
<description>Cipher Block Counter</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AESASTAT</name>
|
|
<displayName>STAT</displayName>
|
|
<description>AES Accelerator Status Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AESBUSY</name>
|
|
<description>AES accelerator module busy</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AESBUSY_0</name>
|
|
<description>Not busy</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AESBUSY_1</name>
|
|
<description>Busy</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AESKEYWR</name>
|
|
<description>All 16 bytes written to AESAKEY</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AESKEYWR_0</name>
|
|
<description>Not all bytes written</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AESKEYWR_1</name>
|
|
<description>All bytes written</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AESDINWR</name>
|
|
<description>All 16 bytes written to AESADIN, AESAXDIN or AESAXIN</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AESDINWR_0</name>
|
|
<description>Not all bytes written</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AESDINWR_1</name>
|
|
<description>All bytes written</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AESDOUTRD</name>
|
|
<description>All 16 bytes read from AESADOUT</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>AESDOUTRD_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>AESDOUTRD_0</name>
|
|
<description>Not all bytes read</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AESDOUTRD_1</name>
|
|
<description>All bytes read</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AESKEYCNTx</name>
|
|
<description>Bytes written via AESAKEY for AESKLx=00, half-words written via AESAKEY</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AESDINCNTx</name>
|
|
<description>Bytes written via AESADIN, AESAXDIN or AESAXIN</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AESDOUTCNTx</name>
|
|
<description>Bytes read via AESADOUT</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AESAKEY</name>
|
|
<displayName>KEY</displayName>
|
|
<description>AES Accelerator Key Register</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AESKEY0x</name>
|
|
<description>AES key byte n when AESAKEY is written as half-word</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AESKEY1x</name>
|
|
<description>AES key byte n+1 when AESAKEY is written as half-word</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AESADIN</name>
|
|
<displayName>DIN</displayName>
|
|
<description>AES Accelerator Data In Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AESDIN0x</name>
|
|
<description>AES data in byte n when AESADIN is written as half-word</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AESDIN1x</name>
|
|
<description>AES data in byte n+1 when AESADIN is written as half-word</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AESADOUT</name>
|
|
<displayName>DOUT</displayName>
|
|
<description>AES Accelerator Data Out Register</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>16</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AESDOUT0x</name>
|
|
<description>AES data out byte n when AESADOUT is read as half-word</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AESDOUT1x</name>
|
|
<description>AES data out byte n+1 when AESADOUT is read as half-word</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AESAXDIN</name>
|
|
<displayName>XDIN</displayName>
|
|
<description>AES Accelerator XORed Data In Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AESXDIN0x</name>
|
|
<description>AES data in byte n when AESAXDIN is written as half-word</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AESXDIN1x</name>
|
|
<description>AES data in byte n+1 when AESAXDIN is written as half-word</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AESAXIN</name>
|
|
<displayName>XIN</displayName>
|
|
<description>AES Accelerator XORed Data In Register</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>16</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AESXIN0x</name>
|
|
<description>AES data in byte n when AESAXIN is written as half-word</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AESXIN1x</name>
|
|
<description>AES data in byte n+1 when AESAXIN is written as half-word</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CRC32</name>
|
|
<version>356.0</version>
|
|
<description>CRC32</description>
|
|
<baseAddress>0x40004000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CRC32DI</name>
|
|
<displayName>CRC32DI</displayName>
|
|
<description>Data Input for CRC32 Signature Computation</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRC32DI</name>
|
|
<description>Data input register</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRC32DIRB</name>
|
|
<displayName>CRC32DIRB</displayName>
|
|
<description>Data In Reverse for CRC32 Computation</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRC32DIRB</name>
|
|
<description>Data input register reversed</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRC32INIRES_LO</name>
|
|
<displayName>CRC32INIRES_LO</displayName>
|
|
<description>CRC32 Initialization and Result, lower 16 bits</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRC32INIRES_LO</name>
|
|
<description>CRC32 initialization and result, lower 16 bits</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRC32INIRES_HI</name>
|
|
<displayName>CRC32INIRES_HI</displayName>
|
|
<description>CRC32 Initialization and Result, upper 16 bits</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRC32INIRES_HI</name>
|
|
<description>CRC32 initialization and result, upper 16 bits</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRC32RESR_LO</name>
|
|
<displayName>CRC32RESR_LO</displayName>
|
|
<description>CRC32 Result Reverse, lower 16 bits</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000ffff</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRC32RESR_LO</name>
|
|
<description>CRC32 reverse result, lower 16 bits</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRC32RESR_HI</name>
|
|
<displayName>CRC32RESR_HI</displayName>
|
|
<description>CRC32 Result Reverse, Upper 16 bits</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000ffff</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRC32RESR_HI</name>
|
|
<description>CRC32 reverse result, upper 16 bits</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRC16DI</name>
|
|
<displayName>CRC16DI</displayName>
|
|
<description>Data Input for CRC16 computation</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRC16DI</name>
|
|
<description>CRC16 data in</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRC16DIRB</name>
|
|
<displayName>CRC16DIRB</displayName>
|
|
<description>CRC16 Data In Reverse</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRC16DIRB</name>
|
|
<description>CRC16 data in reverse byte</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRC16INIRES</name>
|
|
<displayName>CRC16INIRES</displayName>
|
|
<description>CRC16 Initialization and Result register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000ffff</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRC16INIRES</name>
|
|
<description>CRC16 initialization and result</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRC16RESR</name>
|
|
<displayName>CRC16RESR</displayName>
|
|
<description>CRC16 Result Reverse</description>
|
|
<addressOffset>0x1E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000ffff</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRC16RESR</name>
|
|
<description>CRC16 reverse result</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RTC_C</name>
|
|
<version>356.0</version>
|
|
<description>RTC_C</description>
|
|
<baseAddress>0x40004400</baseAddress>
|
|
<interrupt>
|
|
<name>RTC_C_IRQ</name>
|
|
<description>RTC_C Interrupt</description>
|
|
<value>29</value>
|
|
</interrupt>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>RTCCTL0</name>
|
|
<displayName>CTL0</displayName>
|
|
<description>RTCCTL0 Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00009608</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RTCRDYIFG</name>
|
|
<description>Real-time clock ready interrupt flag</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTCRDYIFG_0</name>
|
|
<description>RTC cannot be read safely</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTCRDYIFG_1</name>
|
|
<description>RTC can be read safely</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTCAIFG</name>
|
|
<description>Real-time clock alarm interrupt flag</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTCAIFG_0</name>
|
|
<description>No time event occurred</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTCAIFG_1</name>
|
|
<description>Time event occurred</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTCTEVIFG</name>
|
|
<description>Real-time clock time event interrupt flag</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTCTEVIFG_0</name>
|
|
<description>No time event occurred</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTCTEVIFG_1</name>
|
|
<description>Time event occurred</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTCOFIFG</name>
|
|
<description>32-kHz crystal oscillator fault interrupt flag</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTCOFIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTCOFIFG_1</name>
|
|
<description>Interrupt pending. A 32-kHz crystal oscillator fault occurred after last reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTCRDYIE</name>
|
|
<description>Real-time clock ready interrupt enable</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTCRDYIE_0</name>
|
|
<description>Interrupt not enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTCRDYIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTCAIE</name>
|
|
<description>Real-time clock alarm interrupt enable</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTCAIE_0</name>
|
|
<description>Interrupt not enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTCAIE_1</name>
|
|
<description>Interrupt enabled (LPM3/LPM3.5 wake-up enabled)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTCTEVIE</name>
|
|
<description>Real-time clock time event interrupt enable</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTCTEVIE_0</name>
|
|
<description>Interrupt not enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTCTEVIE_1</name>
|
|
<description>Interrupt enabled (LPM3/LPM3.5 wake-up enabled)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTCOFIE</name>
|
|
<description>32-kHz crystal oscillator fault interrupt enable</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTCOFIE_0</name>
|
|
<description>Interrupt not enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTCOFIE_1</name>
|
|
<description>Interrupt enabled (LPM3/LPM3.5 wake-up enabled)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTCKEY</name>
|
|
<description>Real-time clock key</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTCCTL13</name>
|
|
<displayName>CTL13</displayName>
|
|
<description>RTCCTL13 Register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000070</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RTCTEV</name>
|
|
<description>Real-time clock time event</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTCTEV_0</name>
|
|
<description>Minute changed</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTCTEV_1</name>
|
|
<description>Hour changed</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTCTEV_2</name>
|
|
<description>Every day at midnight (00:00)</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTCTEV_3</name>
|
|
<description>Every day at noon (12:00)</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTCSSEL</name>
|
|
<description>Real-time clock source select</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTCSSEL_0</name>
|
|
<description>BCLK</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTCRDY</name>
|
|
<description>Real-time clock ready</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>RTCRDY_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>RTCRDY_0</name>
|
|
<description>RTC time values in transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTCRDY_1</name>
|
|
<description>RTC time values safe for reading. This bit indicates when the real-time clock time values are safe for reading.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTCMODE</name>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>RTCMODE_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>RTCMODE_1</name>
|
|
<description>Calendar mode. Always reads a value of 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTCHOLD</name>
|
|
<description>Real-time clock hold</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTCHOLD_0</name>
|
|
<description>Real-time clock is operational</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTCHOLD_1</name>
|
|
<description>When set, the calendar is stopped as well as the prescale counters, RT0PS and RT1PS are don't care</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTCBCD</name>
|
|
<description>Real-time clock BCD select</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTCBCD_0</name>
|
|
<description>Binary (hexadecimal) code selected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTCBCD_1</name>
|
|
<description>Binary coded decimal (BCD) code selected</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTCCALF</name>
|
|
<description>Real-time clock calibration frequency</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTCCALF_0</name>
|
|
<description>No frequency output to RTCCLK pin</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTCCALF_1</name>
|
|
<description>512 Hz</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTCCALF_2</name>
|
|
<description>256 Hz</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTCCALF_3</name>
|
|
<description>1 Hz</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTCOCAL</name>
|
|
<displayName>OCAL</displayName>
|
|
<description>RTCOCAL Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RTCOCAL</name>
|
|
<description>Real-time clock offset error calibration</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RTCOCALS</name>
|
|
<description>Real-time clock offset error calibration sign</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTCOCALS_0</name>
|
|
<description>Down calibration. Frequency adjusted down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTCOCALS_1</name>
|
|
<description>Up calibration. Frequency adjusted up.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTCTCMP</name>
|
|
<displayName>TCMP</displayName>
|
|
<description>RTCTCMP Register</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00004000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RTCTCMP</name>
|
|
<description>Real-time clock temperature compensation</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RTCTCOK</name>
|
|
<description>Real-time clock temperature compensation write OK</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>RTCTCOK_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>RTCTCOK_0</name>
|
|
<description>Write to RTCTCMPx is unsuccessful</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTCTCOK_1</name>
|
|
<description>Write to RTCTCMPx is successful</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTCTCRDY</name>
|
|
<description>Real-time clock temperature compensation ready</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RTCTCMPS</name>
|
|
<description>Real-time clock temperature compensation sign</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTCTCMPS_0</name>
|
|
<description>Down calibration. Frequency adjusted down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTCTCMPS_1</name>
|
|
<description>Up calibration. Frequency adjusted up</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTCPS0CTL</name>
|
|
<displayName>PS0CTL</displayName>
|
|
<description>Real-Time Clock Prescale Timer 0 Control Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RT0PSIFG</name>
|
|
<description>Prescale timer 0 interrupt flag</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RT0PSIFG_0</name>
|
|
<description>No time event occurred</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RT0PSIFG_1</name>
|
|
<description>Time event occurred</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RT0PSIE</name>
|
|
<description>Prescale timer 0 interrupt enable</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RT0PSIE_0</name>
|
|
<description>Interrupt not enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RT0PSIE_1</name>
|
|
<description>Interrupt enabled (LPM3/LPM3.5 wake-up enabled)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RT0IP</name>
|
|
<description>Prescale timer 0 interrupt interval</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RT0IP_0</name>
|
|
<description>Divide by 2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RT0IP_1</name>
|
|
<description>Divide by 4</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RT0IP_2</name>
|
|
<description>Divide by 8</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RT0IP_3</name>
|
|
<description>Divide by 16</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RT0IP_4</name>
|
|
<description>Divide by 32</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RT0IP_5</name>
|
|
<description>Divide by 64</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RT0IP_6</name>
|
|
<description>Divide by 128</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RT0IP_7</name>
|
|
<description>Divide by 256</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTCPS1CTL</name>
|
|
<displayName>PS1CTL</displayName>
|
|
<description>Real-Time Clock Prescale Timer 1 Control Register</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RT1PSIFG</name>
|
|
<description>Prescale timer 1 interrupt flag</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RT1PSIFG_0</name>
|
|
<description>No time event occurred</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RT1PSIFG_1</name>
|
|
<description>Time event occurred</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RT1PSIE</name>
|
|
<description>Prescale timer 1 interrupt enable</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RT1PSIE_0</name>
|
|
<description>Interrupt not enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RT1PSIE_1</name>
|
|
<description>Interrupt enabled (LPM3/LPM3.5 wake-up enabled)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RT1IP</name>
|
|
<description>Prescale timer 1 interrupt interval</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RT1IP_0</name>
|
|
<description>Divide by 2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RT1IP_1</name>
|
|
<description>Divide by 4</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RT1IP_2</name>
|
|
<description>Divide by 8</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RT1IP_3</name>
|
|
<description>Divide by 16</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RT1IP_4</name>
|
|
<description>Divide by 32</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RT1IP_5</name>
|
|
<description>Divide by 64</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RT1IP_6</name>
|
|
<description>Divide by 128</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RT1IP_7</name>
|
|
<description>Divide by 256</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTCPS</name>
|
|
<displayName>PS</displayName>
|
|
<description>Real-Time Clock Prescale Timer Counter Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RT0PS</name>
|
|
<description>Prescale timer 0 counter value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RT1PS</name>
|
|
<description>Prescale timer 1 counter value</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTCIV</name>
|
|
<displayName>IV</displayName>
|
|
<description>Real-Time Clock Interrupt Vector Register</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RTCIV</name>
|
|
<description>Real-time clock interrupt vector value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>RTCIV_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>RTCIV_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTCIV_2</name>
|
|
<description>Interrupt Source: RTC oscillator failure; Interrupt Flag: RTCOFIFG; Interrupt Priority: Highest</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTCIV_4</name>
|
|
<description>Interrupt Source: RTC ready; Interrupt Flag: RTCRDYIFG</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTCIV_6</name>
|
|
<description>Interrupt Source: RTC interval timer; Interrupt Flag: RTCTEVIFG</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTCIV_8</name>
|
|
<description>Interrupt Source: RTC user alarm; Interrupt Flag: RTCAIFG</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTCIV_10</name>
|
|
<description>Interrupt Source: RTC prescaler 0; Interrupt Flag: RT0PSIFG</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTCIV_12</name>
|
|
<description>Interrupt Source: RTC prescaler 1; Interrupt Flag: RT1PSIFG</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTCTIM0</name>
|
|
<displayName>TIM0</displayName>
|
|
<description>RTCTIM0 Register Hexadecimal Format</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000c0c0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Seconds</name>
|
|
<description>Seconds (0 to 59)</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>Minutes</name>
|
|
<description>Minutes (0 to 59)</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTCTIM1</name>
|
|
<displayName>TIM1</displayName>
|
|
<description>Real-Time Clock Hour, Day of Week</description>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000f8e0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Hours</name>
|
|
<description>Hours (0 to 23)</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DayofWeek</name>
|
|
<description>Day of week (0 to 6)</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTCDATE</name>
|
|
<displayName>DATE</displayName>
|
|
<description>RTCDATE - Hexadecimal Format</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000f0e0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Day</name>
|
|
<description>Day of month (1 to 28, 29, 30, 31)</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>Month</name>
|
|
<description>Month (1 to 12)</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTCYEAR</name>
|
|
<displayName>YEAR</displayName>
|
|
<description>RTCYEAR Register Hexadecimal Format</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000f000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>YearLowByte</name>
|
|
<description>Year low byte. Valid values for Year are 0 to 4095.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>YearHighByte</name>
|
|
<description>Year high byte. Valid values for Year are 0 to 4095.</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTCAMINHR</name>
|
|
<displayName>AMINHR</displayName>
|
|
<description>RTCMINHR - Hexadecimal Format</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00006040</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Minutes</name>
|
|
<description>Minutes (0 to 59)</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MINAE</name>
|
|
<description>Alarm enable</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>Hours</name>
|
|
<description>Hours (0 to 23)</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HOURAE</name>
|
|
<description>Alarm enable</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTCADOWDAY</name>
|
|
<displayName>ADOWDAY</displayName>
|
|
<description>RTCADOWDAY - Hexadecimal Format</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00006078</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DayofWeek</name>
|
|
<description>Day of week (0 to 6)</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DOWAE</name>
|
|
<description>Alarm enable</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DayofMonth</name>
|
|
<description>Day of month (1 to 28, 29, 30, 31)</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DAYAE</name>
|
|
<description>Alarm enable</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTCBIN2BCD</name>
|
|
<displayName>BIN2BCD</displayName>
|
|
<description>Binary-to-BCD Conversion Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BIN2BCD</name>
|
|
<description>bin to bcd conversion</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTCBCD2BIN</name>
|
|
<displayName>BCD2BIN</displayName>
|
|
<description>BCD-to-Binary Conversion Register</description>
|
|
<addressOffset>0x1E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BCD2BIN</name>
|
|
<description>bcd to bin conversion</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>WDT_A</name>
|
|
<version>356.0</version>
|
|
<description>WDT_A</description>
|
|
<baseAddress>0x40004800</baseAddress>
|
|
<interrupt>
|
|
<name>WDT_A_IRQ</name>
|
|
<description>WDT_A Interrupt</description>
|
|
<value>3</value>
|
|
</interrupt>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xE</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>WDTCTL</name>
|
|
<displayName>CTL</displayName>
|
|
<description>Watchdog Timer Control Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00006904</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WDTIS</name>
|
|
<description>Watchdog timer interval select</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WDTIS_0</name>
|
|
<description>Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WDTIS_1</name>
|
|
<description>Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WDTIS_2</name>
|
|
<description>Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz)</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WDTIS_3</name>
|
|
<description>Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz)</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WDTIS_4</name>
|
|
<description>Watchdog clock source /(2^(15)) (1 s at 32.768 kHz)</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WDTIS_5</name>
|
|
<description>Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz)</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WDTIS_6</name>
|
|
<description>Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz)</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WDTIS_7</name>
|
|
<description>Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz)</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDTCNTCL</name>
|
|
<description>Watchdog timer counter clear</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>WDTCNTCL_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>WDTCNTCL_0</name>
|
|
<description>No action</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WDTCNTCL_1</name>
|
|
<description>WDTCNT = 0000h</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDTTMSEL</name>
|
|
<description>Watchdog timer mode select</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WDTTMSEL_0</name>
|
|
<description>Watchdog mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WDTTMSEL_1</name>
|
|
<description>Interval timer mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDTSSEL</name>
|
|
<description>Watchdog timer clock source select</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WDTSSEL_0</name>
|
|
<description>SMCLK</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WDTSSEL_1</name>
|
|
<description>ACLK</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WDTSSEL_2</name>
|
|
<description>VLOCLK</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WDTSSEL_3</name>
|
|
<description>BCLK</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDTHOLD</name>
|
|
<description>Watchdog timer hold</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WDTHOLD_0</name>
|
|
<description>Watchdog timer is not stopped</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WDTHOLD_1</name>
|
|
<description>Watchdog timer is stopped</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDTPW</name>
|
|
<description>Watchdog timer password</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DIO</name>
|
|
<version>356.0</version>
|
|
<description>DIO</description>
|
|
<baseAddress>0x40004C00</baseAddress>
|
|
<interrupt>
|
|
<name>PORT1_IRQ</name>
|
|
<description>Port1 Interrupt</description>
|
|
<value>35</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORT2_IRQ</name>
|
|
<description>Port2 Interrupt</description>
|
|
<value>36</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORT3_IRQ</name>
|
|
<description>Port3 Interrupt</description>
|
|
<value>37</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORT4_IRQ</name>
|
|
<description>Port4 Interrupt</description>
|
|
<value>38</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORT5_IRQ</name>
|
|
<description>Port5 Interrupt</description>
|
|
<value>39</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORT6_IRQ</name>
|
|
<description>Port6 Interrupt</description>
|
|
<value>40</value>
|
|
</interrupt>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x138</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PAIN</name>
|
|
<displayName>PAIN</displayName>
|
|
<description>Port A Input</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P1IN</name>
|
|
<description>Port 1 Input</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2IN</name>
|
|
<description>Port 2 Input</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PAOUT</name>
|
|
<displayName>PAOUT</displayName>
|
|
<description>Port A Output</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P2OUT</name>
|
|
<description>Port 2 Output</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P1OUT</name>
|
|
<description>Port 1 Output</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PADIR</name>
|
|
<displayName>PADIR</displayName>
|
|
<description>Port A Direction</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P1DIR</name>
|
|
<description>Port 1 Direction</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P2DIR</name>
|
|
<description>Port 2 Direction</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PAREN</name>
|
|
<displayName>PAREN</displayName>
|
|
<description>Port A Resistor Enable</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P1REN</name>
|
|
<description>Port 1 Resistor Enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P2REN</name>
|
|
<description>Port 2 Resistor Enable</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PADS</name>
|
|
<displayName>PADS</displayName>
|
|
<description>Port A Drive Strength</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>P1DS</name>
|
|
<description>Port 1 Drive Strength</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P2DS</name>
|
|
<description>Port 2 Drive Strength</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PASEL0</name>
|
|
<displayName>PASEL0</displayName>
|
|
<description>Port A Select 0</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P1SEL0</name>
|
|
<description>Port 1 Select 0</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P2SEL0</name>
|
|
<description>Port 2 Select 0</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PASEL1</name>
|
|
<displayName>PASEL1</displayName>
|
|
<description>Port A Select 1</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P1SEL1</name>
|
|
<description>Port 1 Select 1</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P2SEL1</name>
|
|
<description>Port 2 Select 1</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1IV</name>
|
|
<displayName>P1IV</displayName>
|
|
<description>Port 1 Interrupt Vector Register</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P1IV</name>
|
|
<description>Port 1 interrupt vector value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x5</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>P1IV_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>P1IV_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P1IV_2</name>
|
|
<description>Interrupt Source: Port 1.0 interrupt; Interrupt Flag: P1IFG0; Interrupt Priority: Highest</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P1IV_4</name>
|
|
<description>Interrupt Source: Port 1.1 interrupt; Interrupt Flag: P1IFG1</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P1IV_6</name>
|
|
<description>Interrupt Source: Port 1.2 interrupt; Interrupt Flag: P1IFG2</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P1IV_8</name>
|
|
<description>Interrupt Source: Port 1.3 interrupt; Interrupt Flag: P1IFG3</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P1IV_10</name>
|
|
<description>Interrupt Source: Port 1.4 interrupt; Interrupt Flag: P1IFG4</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P1IV_12</name>
|
|
<description>Interrupt Source: Port 1.5 interrupt; Interrupt Flag: P1IFG5</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P1IV_14</name>
|
|
<description>Interrupt Source: Port 1.6 interrupt; Interrupt Flag: P1IFG6</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P1IV_16</name>
|
|
<description>Interrupt Source: Port 1.7 interrupt; Interrupt Flag: P1IFG7; Interrupt Priority: Lowest</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PASELC</name>
|
|
<displayName>PASELC</displayName>
|
|
<description>Port A Complement Select</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P1SELC</name>
|
|
<description>Port 1 Complement Select</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P2SELC</name>
|
|
<description>Port 2 Complement Select</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PAIES</name>
|
|
<displayName>PAIES</displayName>
|
|
<description>Port A Interrupt Edge Select</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P1IES</name>
|
|
<description>Port 1 Interrupt Edge Select</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P2IES</name>
|
|
<description>Port 2 Interrupt Edge Select</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PAIE</name>
|
|
<displayName>PAIE</displayName>
|
|
<description>Port A Interrupt Enable</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P1IE</name>
|
|
<description>Port 1 Interrupt Enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P2IE</name>
|
|
<description>Port 2 Interrupt Enable</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PAIFG</name>
|
|
<displayName>PAIFG</displayName>
|
|
<description>Port A Interrupt Flag</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P1IFG</name>
|
|
<description>Port 1 Interrupt Flag</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P2IFG</name>
|
|
<description>Port 2 Interrupt Flag</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2IV</name>
|
|
<displayName>P2IV</displayName>
|
|
<description>Port 2 Interrupt Vector Register</description>
|
|
<addressOffset>0x1E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P2IV</name>
|
|
<description>Port 2 interrupt vector value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x5</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>P2IV_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>P2IV_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P2IV_2</name>
|
|
<description>Interrupt Source: Port 2.0 interrupt; Interrupt Flag: P2IFG0; Interrupt Priority: Highest</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P2IV_4</name>
|
|
<description>Interrupt Source: Port 2.1 interrupt; Interrupt Flag: P2IFG1</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P2IV_6</name>
|
|
<description>Interrupt Source: Port 2.2 interrupt; Interrupt Flag: P2IFG2</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P2IV_8</name>
|
|
<description>Interrupt Source: Port 2.3 interrupt; Interrupt Flag: P2IFG3</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P2IV_10</name>
|
|
<description>Interrupt Source: Port 2.4 interrupt; Interrupt Flag: P2IFG4</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P2IV_12</name>
|
|
<description>Interrupt Source: Port 2.5 interrupt; Interrupt Flag: P2IFG5</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P2IV_14</name>
|
|
<description>Interrupt Source: Port 2.6 interrupt; Interrupt Flag: P2IFG6</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P2IV_16</name>
|
|
<description>Interrupt Source: Port 2.7 interrupt; Interrupt Flag: P2IFG7; Interrupt Priority: Lowest</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBIN</name>
|
|
<displayName>PBIN</displayName>
|
|
<description>Port B Input</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P3IN</name>
|
|
<description>Port 3 Input</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4IN</name>
|
|
<description>Port 4 Input</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBOUT</name>
|
|
<displayName>PBOUT</displayName>
|
|
<description>Port B Output</description>
|
|
<addressOffset>0x22</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P3OUT</name>
|
|
<description>Port 3 Output</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P4OUT</name>
|
|
<description>Port 4 Output</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBDIR</name>
|
|
<displayName>PBDIR</displayName>
|
|
<description>Port B Direction</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P3DIR</name>
|
|
<description>Port 3 Direction</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P4DIR</name>
|
|
<description>Port 4 Direction</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBREN</name>
|
|
<displayName>PBREN</displayName>
|
|
<description>Port B Resistor Enable</description>
|
|
<addressOffset>0x26</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P3REN</name>
|
|
<description>Port 3 Resistor Enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P4REN</name>
|
|
<description>Port 4 Resistor Enable</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBDS</name>
|
|
<displayName>PBDS</displayName>
|
|
<description>Port B Drive Strength</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>P3DS</name>
|
|
<description>Port 3 Drive Strength</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P4DS</name>
|
|
<description>Port 4 Drive Strength</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBSEL0</name>
|
|
<displayName>PBSEL0</displayName>
|
|
<description>Port B Select 0</description>
|
|
<addressOffset>0x2A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P4SEL0</name>
|
|
<description>Port 4 Select 0</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P3SEL0</name>
|
|
<description>Port 3 Select 0</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBSEL1</name>
|
|
<displayName>PBSEL1</displayName>
|
|
<description>Port B Select 1</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P3SEL1</name>
|
|
<description>Port 3 Select 1</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P4SEL1</name>
|
|
<description>Port 4 Select 1</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3IV</name>
|
|
<displayName>P3IV</displayName>
|
|
<description>Port 3 Interrupt Vector Register</description>
|
|
<addressOffset>0x2E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P3IV</name>
|
|
<description>Port 3 interrupt vector value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x5</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>P3IV_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>P3IV_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P3IV_2</name>
|
|
<description>Interrupt Source: Port 3.0 interrupt; Interrupt Flag: P3IFG0; Interrupt Priority: Highest</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P3IV_4</name>
|
|
<description>Interrupt Source: Port 3.1 interrupt; Interrupt Flag: P3IFG1</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P3IV_6</name>
|
|
<description>Interrupt Source: Port 3.2 interrupt; Interrupt Flag: P3IFG2</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P3IV_8</name>
|
|
<description>Interrupt Source: Port 3.3 interrupt; Interrupt Flag: P3IFG3</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P3IV_10</name>
|
|
<description>Interrupt Source: Port 3.4 interrupt; Interrupt Flag: P3IFG4</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P3IV_12</name>
|
|
<description>Interrupt Source: Port 3.5 interrupt; Interrupt Flag: P3IFG5</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P3IV_14</name>
|
|
<description>Interrupt Source: Port 3.6 interrupt; Interrupt Flag: P3IFG6</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P3IV_16</name>
|
|
<description>Interrupt Source: Port 3.7 interrupt; Interrupt Flag: P3IFG7; Interrupt Priority: Lowest</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBSELC</name>
|
|
<displayName>PBSELC</displayName>
|
|
<description>Port B Complement Select</description>
|
|
<addressOffset>0x36</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P3SELC</name>
|
|
<description>Port 3 Complement Select</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P4SELC</name>
|
|
<description>Port 4 Complement Select</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBIES</name>
|
|
<displayName>PBIES</displayName>
|
|
<description>Port B Interrupt Edge Select</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P3IES</name>
|
|
<description>Port 3 Interrupt Edge Select</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P4IES</name>
|
|
<description>Port 4 Interrupt Edge Select</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBIE</name>
|
|
<displayName>PBIE</displayName>
|
|
<description>Port B Interrupt Enable</description>
|
|
<addressOffset>0x3A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P3IE</name>
|
|
<description>Port 3 Interrupt Enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P4IE</name>
|
|
<description>Port 4 Interrupt Enable</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBIFG</name>
|
|
<displayName>PBIFG</displayName>
|
|
<description>Port B Interrupt Flag</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P3IFG</name>
|
|
<description>Port 3 Interrupt Flag</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P4IFG</name>
|
|
<description>Port 4 Interrupt Flag</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4IV</name>
|
|
<displayName>P4IV</displayName>
|
|
<description>Port 4 Interrupt Vector Register</description>
|
|
<addressOffset>0x3E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P4IV</name>
|
|
<description>Port 4 interrupt vector value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x5</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>P4IV_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>P4IV_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P4IV_2</name>
|
|
<description>Interrupt Source: Port 4.0 interrupt; Interrupt Flag: P4IFG0; Interrupt Priority: Highest</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P4IV_4</name>
|
|
<description>Interrupt Source: Port 4.1 interrupt; Interrupt Flag: P4IFG1</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P4IV_6</name>
|
|
<description>Interrupt Source: Port 4.2 interrupt; Interrupt Flag: P4IFG2</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P4IV_8</name>
|
|
<description>Interrupt Source: Port 4.3 interrupt; Interrupt Flag: P4IFG3</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P4IV_10</name>
|
|
<description>Interrupt Source: Port 4.4 interrupt; Interrupt Flag: P4IFG4</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P4IV_12</name>
|
|
<description>Interrupt Source: Port 4.5 interrupt; Interrupt Flag: P4IFG5</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P4IV_14</name>
|
|
<description>Interrupt Source: Port 4.6 interrupt; Interrupt Flag: P4IFG6</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P4IV_16</name>
|
|
<description>Interrupt Source: Port 4.7 interrupt; Interrupt Flag: P4IFG7; Interrupt Priority: Lowest</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCIN</name>
|
|
<displayName>PCIN</displayName>
|
|
<description>Port C Input</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P5IN</name>
|
|
<description>Port 5 Input</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6IN</name>
|
|
<description>Port 6 Input</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCOUT</name>
|
|
<displayName>PCOUT</displayName>
|
|
<description>Port C Output</description>
|
|
<addressOffset>0x42</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P5OUT</name>
|
|
<description>Port 5 Output</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P6OUT</name>
|
|
<description>Port 6 Output</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCDIR</name>
|
|
<displayName>PCDIR</displayName>
|
|
<description>Port C Direction</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P5DIR</name>
|
|
<description>Port 5 Direction</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P6DIR</name>
|
|
<description>Port 6 Direction</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCREN</name>
|
|
<displayName>PCREN</displayName>
|
|
<description>Port C Resistor Enable</description>
|
|
<addressOffset>0x46</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P5REN</name>
|
|
<description>Port 5 Resistor Enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P6REN</name>
|
|
<description>Port 6 Resistor Enable</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCDS</name>
|
|
<displayName>PCDS</displayName>
|
|
<description>Port C Drive Strength</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>P5DS</name>
|
|
<description>Port 5 Drive Strength</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P6DS</name>
|
|
<description>Port 6 Drive Strength</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCSEL0</name>
|
|
<displayName>PCSEL0</displayName>
|
|
<description>Port C Select 0</description>
|
|
<addressOffset>0x4A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P5SEL0</name>
|
|
<description>Port 5 Select 0</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P6SEL0</name>
|
|
<description>Port 6 Select 0</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCSEL1</name>
|
|
<displayName>PCSEL1</displayName>
|
|
<description>Port C Select 1</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P5SEL1</name>
|
|
<description>Port 5 Select 1</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P6SEL1</name>
|
|
<description>Port 6 Select 1</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P5IV</name>
|
|
<displayName>P5IV</displayName>
|
|
<description>Port 5 Interrupt Vector Register</description>
|
|
<addressOffset>0x4E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P5IV</name>
|
|
<description>Port 5 interrupt vector value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x5</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>P5IV_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>P5IV_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P5IV_2</name>
|
|
<description>Interrupt Source: Port 5.0 interrupt; Interrupt Flag: P5IFG0; Interrupt Priority: Highest</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P5IV_4</name>
|
|
<description>Interrupt Source: Port 5.1 interrupt; Interrupt Flag: P5IFG1</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P5IV_6</name>
|
|
<description>Interrupt Source: Port 5.2 interrupt; Interrupt Flag: P5IFG2</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P5IV_8</name>
|
|
<description>Interrupt Source: Port 5.3 interrupt; Interrupt Flag: P5IFG3</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P5IV_10</name>
|
|
<description>Interrupt Source: Port 5.4 interrupt; Interrupt Flag: P5IFG4</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P5IV_12</name>
|
|
<description>Interrupt Source: Port 5.5 interrupt; Interrupt Flag: P5IFG5</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P5IV_14</name>
|
|
<description>Interrupt Source: Port 5.6 interrupt; Interrupt Flag: P5IFG6</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P5IV_16</name>
|
|
<description>Interrupt Source: Port 5.7 interrupt; Interrupt Flag: P5IFG7; Interrupt Priority: Lowest</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCSELC</name>
|
|
<displayName>PCSELC</displayName>
|
|
<description>Port C Complement Select</description>
|
|
<addressOffset>0x56</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P5SELC</name>
|
|
<description>Port 5 Complement Select</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P6SELC</name>
|
|
<description>Port 6 Complement Select</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCIES</name>
|
|
<displayName>PCIES</displayName>
|
|
<description>Port C Interrupt Edge Select</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P5IES</name>
|
|
<description>Port 5 Interrupt Edge Select</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P6IES</name>
|
|
<description>Port 6 Interrupt Edge Select</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCIE</name>
|
|
<displayName>PCIE</displayName>
|
|
<description>Port C Interrupt Enable</description>
|
|
<addressOffset>0x5A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P5IE</name>
|
|
<description>Port 5 Interrupt Enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P6IE</name>
|
|
<description>Port 6 Interrupt Enable</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCIFG</name>
|
|
<displayName>PCIFG</displayName>
|
|
<description>Port C Interrupt Flag</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P5IFG</name>
|
|
<description>Port 5 Interrupt Flag</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P6IFG</name>
|
|
<description>Port 6 Interrupt Flag</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P6IV</name>
|
|
<displayName>P6IV</displayName>
|
|
<description>Port 6 Interrupt Vector Register</description>
|
|
<addressOffset>0x5E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P6IV</name>
|
|
<description>Port 6 interrupt vector value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x5</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>P6IV_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>P6IV_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P6IV_2</name>
|
|
<description>Interrupt Source: Port 6.0 interrupt; Interrupt Flag: P6IFG0; Interrupt Priority: Highest</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P6IV_4</name>
|
|
<description>Interrupt Source: Port 6.1 interrupt; Interrupt Flag: P6IFG1</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P6IV_6</name>
|
|
<description>Interrupt Source: Port 6.2 interrupt; Interrupt Flag: P6IFG2</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P6IV_8</name>
|
|
<description>Interrupt Source: Port 6.3 interrupt; Interrupt Flag: P6IFG3</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P6IV_10</name>
|
|
<description>Interrupt Source: Port 6.4 interrupt; Interrupt Flag: P6IFG4</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P6IV_12</name>
|
|
<description>Interrupt Source: Port 6.5 interrupt; Interrupt Flag: P6IFG5</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P6IV_14</name>
|
|
<description>Interrupt Source: Port 6.6 interrupt; Interrupt Flag: P6IFG6</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P6IV_16</name>
|
|
<description>Interrupt Source: Port 6.7 interrupt; Interrupt Flag: P6IFG7; Interrupt Priority: Lowest</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDIN</name>
|
|
<displayName>PDIN</displayName>
|
|
<description>Port D Input</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P7IN</name>
|
|
<description>Port 7 Input</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8IN</name>
|
|
<description>Port 8 Input</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDOUT</name>
|
|
<displayName>PDOUT</displayName>
|
|
<description>Port D Output</description>
|
|
<addressOffset>0x62</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P7OUT</name>
|
|
<description>Port 7 Output</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P8OUT</name>
|
|
<description>Port 8 Output</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDDIR</name>
|
|
<displayName>PDDIR</displayName>
|
|
<description>Port D Direction</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P7DIR</name>
|
|
<description>Port 7 Direction</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P8DIR</name>
|
|
<description>Port 8 Direction</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDREN</name>
|
|
<displayName>PDREN</displayName>
|
|
<description>Port D Resistor Enable</description>
|
|
<addressOffset>0x66</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P7REN</name>
|
|
<description>Port 7 Resistor Enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P8REN</name>
|
|
<description>Port 8 Resistor Enable</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDDS</name>
|
|
<displayName>PDDS</displayName>
|
|
<description>Port D Drive Strength</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>P7DS</name>
|
|
<description>Port 7 Drive Strength</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P8DS</name>
|
|
<description>Port 8 Drive Strength</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDSEL0</name>
|
|
<displayName>PDSEL0</displayName>
|
|
<description>Port D Select 0</description>
|
|
<addressOffset>0x6A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P7SEL0</name>
|
|
<description>Port 7 Select 0</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P8SEL0</name>
|
|
<description>Port 8 Select 0</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDSEL1</name>
|
|
<displayName>PDSEL1</displayName>
|
|
<description>Port D Select 1</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P7SEL1</name>
|
|
<description>Port 7 Select 1</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P8SEL1</name>
|
|
<description>Port 8 Select 1</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P7IV</name>
|
|
<displayName>P7IV</displayName>
|
|
<description>Port 7 Interrupt Vector Register</description>
|
|
<addressOffset>0x6E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P7IV</name>
|
|
<description>Port 7 interrupt vector value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x5</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>P7IV_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>P7IV_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P7IV_2</name>
|
|
<description>Interrupt Source: Port 7.0 interrupt; Interrupt Flag: P7IFG0; Interrupt Priority: Highest</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P7IV_4</name>
|
|
<description>Interrupt Source: Port 7.1 interrupt; Interrupt Flag: P7IFG1</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P7IV_6</name>
|
|
<description>Interrupt Source: Port 7.2 interrupt; Interrupt Flag: P7IFG2</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P7IV_8</name>
|
|
<description>Interrupt Source: Port 7.3 interrupt; Interrupt Flag: P7IFG3</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P7IV_10</name>
|
|
<description>Interrupt Source: Port 7.4 interrupt; Interrupt Flag: P7IFG4</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P7IV_12</name>
|
|
<description>Interrupt Source: Port 7.5 interrupt; Interrupt Flag: P7IFG5</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P7IV_14</name>
|
|
<description>Interrupt Source: Port 7.6 interrupt; Interrupt Flag: P7IFG6</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P7IV_16</name>
|
|
<description>Interrupt Source: Port 7.7 interrupt; Interrupt Flag: P7IFG7; Interrupt Priority: Lowest</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDSELC</name>
|
|
<displayName>PDSELC</displayName>
|
|
<description>Port D Complement Select</description>
|
|
<addressOffset>0x76</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P7SELC</name>
|
|
<description>Port 7 Complement Select</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P8SELC</name>
|
|
<description>Port 8 Complement Select</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDIES</name>
|
|
<displayName>PDIES</displayName>
|
|
<description>Port D Interrupt Edge Select</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P7IES</name>
|
|
<description>Port 7 Interrupt Edge Select</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P8IES</name>
|
|
<description>Port 8 Interrupt Edge Select</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDIE</name>
|
|
<displayName>PDIE</displayName>
|
|
<description>Port D Interrupt Enable</description>
|
|
<addressOffset>0x7A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P7IE</name>
|
|
<description>Port 7 Interrupt Enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P8IE</name>
|
|
<description>Port 8 Interrupt Enable</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDIFG</name>
|
|
<displayName>PDIFG</displayName>
|
|
<description>Port D Interrupt Flag</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P7IFG</name>
|
|
<description>Port 7 Interrupt Flag</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P8IFG</name>
|
|
<description>Port 8 Interrupt Flag</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P8IV</name>
|
|
<displayName>P8IV</displayName>
|
|
<description>Port 8 Interrupt Vector Register</description>
|
|
<addressOffset>0x7E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P8IV</name>
|
|
<description>Port 8 interrupt vector value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x5</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>P8IV_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>P8IV_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P8IV_2</name>
|
|
<description>Interrupt Source: Port 8.0 interrupt; Interrupt Flag: P8IFG0; Interrupt Priority: Highest</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P8IV_4</name>
|
|
<description>Interrupt Source: Port 8.1 interrupt; Interrupt Flag: P8IFG1</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P8IV_6</name>
|
|
<description>Interrupt Source: Port 8.2 interrupt; Interrupt Flag: P8IFG2</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P8IV_8</name>
|
|
<description>Interrupt Source: Port 8.3 interrupt; Interrupt Flag: P8IFG3</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P8IV_10</name>
|
|
<description>Interrupt Source: Port 8.4 interrupt; Interrupt Flag: P8IFG4</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P8IV_12</name>
|
|
<description>Interrupt Source: Port 8.5 interrupt; Interrupt Flag: P8IFG5</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P8IV_14</name>
|
|
<description>Interrupt Source: Port 8.6 interrupt; Interrupt Flag: P8IFG6</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P8IV_16</name>
|
|
<description>Interrupt Source: Port 8.7 interrupt; Interrupt Flag: P8IFG7; Interrupt Priority: Lowest</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PEIN</name>
|
|
<displayName>PEIN</displayName>
|
|
<description>Port E Input</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P9IN</name>
|
|
<description>Port 9 Input</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10IN</name>
|
|
<description>Port 10 Input</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PEOUT</name>
|
|
<displayName>PEOUT</displayName>
|
|
<description>Port E Output</description>
|
|
<addressOffset>0x82</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P9OUT</name>
|
|
<description>Port 9 Output</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P10OUT</name>
|
|
<description>Port 10 Output</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PEDIR</name>
|
|
<displayName>PEDIR</displayName>
|
|
<description>Port E Direction</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P9DIR</name>
|
|
<description>Port 9 Direction</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P10DIR</name>
|
|
<description>Port 10 Direction</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PEREN</name>
|
|
<displayName>PEREN</displayName>
|
|
<description>Port E Resistor Enable</description>
|
|
<addressOffset>0x86</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P9REN</name>
|
|
<description>Port 9 Resistor Enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P10REN</name>
|
|
<description>Port 10 Resistor Enable</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PEDS</name>
|
|
<displayName>PEDS</displayName>
|
|
<description>Port E Drive Strength</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>P9DS</name>
|
|
<description>Port 9 Drive Strength</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P10DS</name>
|
|
<description>Port 10 Drive Strength</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PESEL0</name>
|
|
<displayName>PESEL0</displayName>
|
|
<description>Port E Select 0</description>
|
|
<addressOffset>0x8A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P9SEL0</name>
|
|
<description>Port 9 Select 0</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P10SEL0</name>
|
|
<description>Port 10 Select 0</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PESEL1</name>
|
|
<displayName>PESEL1</displayName>
|
|
<description>Port E Select 1</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P9SEL1</name>
|
|
<description>Port 9 Select 1</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P10SEL1</name>
|
|
<description>Port 10 Select 1</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P9IV</name>
|
|
<displayName>P9IV</displayName>
|
|
<description>Port 9 Interrupt Vector Register</description>
|
|
<addressOffset>0x8E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P9IV</name>
|
|
<description>Port 9 interrupt vector value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x5</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>P9IV_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>P9IV_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P9IV_2</name>
|
|
<description>Interrupt Source: Port 9.0 interrupt; Interrupt Flag: P9IFG0; Interrupt Priority: Highest</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P9IV_4</name>
|
|
<description>Interrupt Source: Port 9.1 interrupt; Interrupt Flag: P9IFG1</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P9IV_6</name>
|
|
<description>Interrupt Source: Port 9.2 interrupt; Interrupt Flag: P9IFG2</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P9IV_8</name>
|
|
<description>Interrupt Source: Port 9.3 interrupt; Interrupt Flag: P9IFG3</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P9IV_10</name>
|
|
<description>Interrupt Source: Port 9.4 interrupt; Interrupt Flag: P9IFG4</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P9IV_12</name>
|
|
<description>Interrupt Source: Port 9.5 interrupt; Interrupt Flag: P9IFG5</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P9IV_14</name>
|
|
<description>Interrupt Source: Port 9.6 interrupt; Interrupt Flag: P9IFG6</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P9IV_16</name>
|
|
<description>Interrupt Source: Port 9.7 interrupt; Interrupt Flag: P9IFG7; Interrupt Priority: Lowest</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PESELC</name>
|
|
<displayName>PESELC</displayName>
|
|
<description>Port E Complement Select</description>
|
|
<addressOffset>0x96</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P9SELC</name>
|
|
<description>Port 9 Complement Select</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P10SELC</name>
|
|
<description>Port 10 Complement Select</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PEIES</name>
|
|
<displayName>PEIES</displayName>
|
|
<description>Port E Interrupt Edge Select</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P9IES</name>
|
|
<description>Port 9 Interrupt Edge Select</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P10IES</name>
|
|
<description>Port 10 Interrupt Edge Select</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PEIE</name>
|
|
<displayName>PEIE</displayName>
|
|
<description>Port E Interrupt Enable</description>
|
|
<addressOffset>0x9A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P9IE</name>
|
|
<description>Port 9 Interrupt Enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P10IE</name>
|
|
<description>Port 10 Interrupt Enable</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PEIFG</name>
|
|
<displayName>PEIFG</displayName>
|
|
<description>Port E Interrupt Flag</description>
|
|
<addressOffset>0x9C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P9IFG</name>
|
|
<description>Port 9 Interrupt Flag</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P10IFG</name>
|
|
<description>Port 10 Interrupt Flag</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P10IV</name>
|
|
<displayName>P10IV</displayName>
|
|
<description>Port 10 Interrupt Vector Register</description>
|
|
<addressOffset>0x9E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P10IV</name>
|
|
<description>Port 10 interrupt vector value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x5</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>P10IV_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>P10IV_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P10IV_2</name>
|
|
<description>Interrupt Source: Port 10.0 interrupt; Interrupt Flag: P10IFG0; Interrupt Priority: Highest</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P10IV_4</name>
|
|
<description>Interrupt Source: Port 10.1 interrupt; Interrupt Flag: P10IFG1</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P10IV_6</name>
|
|
<description>Interrupt Source: Port 10.2 interrupt; Interrupt Flag: P10IFG2</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P10IV_8</name>
|
|
<description>Interrupt Source: Port 10.3 interrupt; Interrupt Flag: P10IFG3</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P10IV_10</name>
|
|
<description>Interrupt Source: Port 10.4 interrupt; Interrupt Flag: P10IFG4</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P10IV_12</name>
|
|
<description>Interrupt Source: Port 10.5 interrupt; Interrupt Flag: P10IFG5</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P10IV_14</name>
|
|
<description>Interrupt Source: Port 10.6 interrupt; Interrupt Flag: P10IFG6</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P10IV_16</name>
|
|
<description>Interrupt Source: Port 10.7 interrupt; Interrupt Flag: P10IFG7; Interrupt Priority: Lowest</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PJIN</name>
|
|
<displayName>PJIN</displayName>
|
|
<description>Port J Input</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PJIN</name>
|
|
<description>Port J Input</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PJOUT</name>
|
|
<displayName>PJOUT</displayName>
|
|
<description>Port J Output</description>
|
|
<addressOffset>0x122</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PJOUT</name>
|
|
<description>Port J Output</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PJDIR</name>
|
|
<displayName>PJDIR</displayName>
|
|
<description>Port J Direction</description>
|
|
<addressOffset>0x124</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PJDIR</name>
|
|
<description>Port J Direction</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PJREN</name>
|
|
<displayName>PJREN</displayName>
|
|
<description>Port J Resistor Enable</description>
|
|
<addressOffset>0x126</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PJREN</name>
|
|
<description>Port J Resistor Enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PJDS</name>
|
|
<displayName>PJDS</displayName>
|
|
<description>Port J Drive Strength</description>
|
|
<addressOffset>0x128</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>PJDS</name>
|
|
<description>Port J Drive Strength</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PJSEL0</name>
|
|
<displayName>PJSEL0</displayName>
|
|
<description>Port J Select 0</description>
|
|
<addressOffset>0x12A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PJSEL0</name>
|
|
<description>Port J Select 0</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PJSEL1</name>
|
|
<displayName>PJSEL1</displayName>
|
|
<description>Port J Select 1</description>
|
|
<addressOffset>0x12C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PJSEL1</name>
|
|
<description>Port J Select 1</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PJSELC</name>
|
|
<displayName>PJSELC</displayName>
|
|
<description>Port J Complement Select</description>
|
|
<addressOffset>0x136</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PJSELC</name>
|
|
<description>Port J Complement Select</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PMAP</name>
|
|
<version>356.0</version>
|
|
<description>PMAP</description>
|
|
<baseAddress>0x40005000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x40</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PMAPKEYID</name>
|
|
<displayName>KEYID</displayName>
|
|
<description>Port Mapping Key Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000096a5</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PMAPKEY</name>
|
|
<description>Port mapping controller write access key</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMAPCTL</name>
|
|
<displayName>CTL</displayName>
|
|
<description>Port Mapping Control Register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PMAPLOCKED</name>
|
|
<description>Port mapping lock bit</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>PMAPLOCKED_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>PMAPLOCKED_0</name>
|
|
<description>Access to mapping registers is granted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PMAPLOCKED_1</name>
|
|
<description>Access to mapping registers is locked</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PMAPRECFG</name>
|
|
<description>Port mapping reconfiguration control bit</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PMAPRECFG_0</name>
|
|
<description>Configuration allowed only once</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PMAPRECFG_1</name>
|
|
<description>Allow reconfiguration of port mapping</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1MAP01</name>
|
|
<displayName>P1MAP01</displayName>
|
|
<description>Port mapping register, P1.0 and P1.1</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>PMAPx</name>
|
|
<description>Selects secondary port function</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1MAP23</name>
|
|
<displayName>P1MAP23</displayName>
|
|
<description>Port mapping register, P1.2 and P1.3</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>PMAPx</name>
|
|
<description>Selects secondary port function</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1MAP45</name>
|
|
<displayName>P1MAP45</displayName>
|
|
<description>Port mapping register, P1.4 and P1.5</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>PMAPx</name>
|
|
<description>Selects secondary port function</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1MAP67</name>
|
|
<displayName>P1MAP67</displayName>
|
|
<description>Port mapping register, P1.6 and P1.7</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>PMAPx</name>
|
|
<description>Selects secondary port function</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2MAP01</name>
|
|
<displayName>P2MAP01</displayName>
|
|
<description>Port mapping register, P2.0 and P2.1</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>PMAPx</name>
|
|
<description>Selects secondary port function</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2MAP23</name>
|
|
<displayName>P2MAP23</displayName>
|
|
<description>Port mapping register, P2.2 and P2.3</description>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>PMAPx</name>
|
|
<description>Selects secondary port function</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2MAP45</name>
|
|
<displayName>P2MAP45</displayName>
|
|
<description>Port mapping register, P2.4 and P2.5</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>PMAPx</name>
|
|
<description>Selects secondary port function</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2MAP67</name>
|
|
<displayName>P2MAP67</displayName>
|
|
<description>Port mapping register, P2.6 and P2.7</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>PMAPx</name>
|
|
<description>Selects secondary port function</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3MAP01</name>
|
|
<displayName>P3MAP01</displayName>
|
|
<description>Port mapping register, P3.0 and P3.1</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>PMAPx</name>
|
|
<description>Selects secondary port function</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3MAP23</name>
|
|
<displayName>P3MAP23</displayName>
|
|
<description>Port mapping register, P3.2 and P3.3</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>PMAPx</name>
|
|
<description>Selects secondary port function</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3MAP45</name>
|
|
<displayName>P3MAP45</displayName>
|
|
<description>Port mapping register, P3.4 and P3.5</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>PMAPx</name>
|
|
<description>Selects secondary port function</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3MAP67</name>
|
|
<displayName>P3MAP67</displayName>
|
|
<description>Port mapping register, P3.6 and P3.7</description>
|
|
<addressOffset>0x1E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>PMAPx</name>
|
|
<description>Selects secondary port function</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4MAP01</name>
|
|
<displayName>P4MAP01</displayName>
|
|
<description>Port mapping register, P4.0 and P4.1</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>PMAPx</name>
|
|
<description>Selects secondary port function</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4MAP23</name>
|
|
<displayName>P4MAP23</displayName>
|
|
<description>Port mapping register, P4.2 and P4.3</description>
|
|
<addressOffset>0x22</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>PMAPx</name>
|
|
<description>Selects secondary port function</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4MAP45</name>
|
|
<displayName>P4MAP45</displayName>
|
|
<description>Port mapping register, P4.4 and P4.5</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>PMAPx</name>
|
|
<description>Selects secondary port function</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4MAP67</name>
|
|
<displayName>P4MAP67</displayName>
|
|
<description>Port mapping register, P4.6 and P4.7</description>
|
|
<addressOffset>0x26</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>PMAPx</name>
|
|
<description>Selects secondary port function</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P5MAP01</name>
|
|
<displayName>P5MAP01</displayName>
|
|
<description>Port mapping register, P5.0 and P5.1</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>PMAPx</name>
|
|
<description>Selects secondary port function</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P5MAP23</name>
|
|
<displayName>P5MAP23</displayName>
|
|
<description>Port mapping register, P5.2 and P5.3</description>
|
|
<addressOffset>0x2A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>PMAPx</name>
|
|
<description>Selects secondary port function</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P5MAP45</name>
|
|
<displayName>P5MAP45</displayName>
|
|
<description>Port mapping register, P5.4 and P5.5</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>PMAPx</name>
|
|
<description>Selects secondary port function</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P5MAP67</name>
|
|
<displayName>P5MAP67</displayName>
|
|
<description>Port mapping register, P5.6 and P5.7</description>
|
|
<addressOffset>0x2E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>PMAPx</name>
|
|
<description>Selects secondary port function</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P6MAP01</name>
|
|
<displayName>P6MAP01</displayName>
|
|
<description>Port mapping register, P6.0 and P6.1</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>PMAPx</name>
|
|
<description>Selects secondary port function</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P6MAP23</name>
|
|
<displayName>P6MAP23</displayName>
|
|
<description>Port mapping register, P6.2 and P6.3</description>
|
|
<addressOffset>0x32</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>PMAPx</name>
|
|
<description>Selects secondary port function</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P6MAP45</name>
|
|
<displayName>P6MAP45</displayName>
|
|
<description>Port mapping register, P6.4 and P6.5</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>PMAPx</name>
|
|
<description>Selects secondary port function</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P6MAP67</name>
|
|
<displayName>P6MAP67</displayName>
|
|
<description>Port mapping register, P6.6 and P6.7</description>
|
|
<addressOffset>0x36</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>PMAPx</name>
|
|
<description>Selects secondary port function</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P7MAP01</name>
|
|
<displayName>P7MAP01</displayName>
|
|
<description>Port mapping register, P7.0 and P7.1</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>PMAPx</name>
|
|
<description>Selects secondary port function</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P7MAP23</name>
|
|
<displayName>P7MAP23</displayName>
|
|
<description>Port mapping register, P7.2 and P7.3</description>
|
|
<addressOffset>0x3A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>PMAPx</name>
|
|
<description>Selects secondary port function</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P7MAP45</name>
|
|
<displayName>P7MAP45</displayName>
|
|
<description>Port mapping register, P7.4 and P7.5</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>PMAPx</name>
|
|
<description>Selects secondary port function</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P7MAP67</name>
|
|
<displayName>P7MAP67</displayName>
|
|
<description>Port mapping register, P7.6 and P7.7</description>
|
|
<addressOffset>0x3E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>PMAPx</name>
|
|
<description>Selects secondary port function</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CAPTIO0</name>
|
|
<version>356.0</version>
|
|
<description>CAPTIO0</description>
|
|
<baseAddress>0x40005400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CAPTIOxCTL</name>
|
|
<displayName>CTL</displayName>
|
|
<description>Capacitive Touch IO x Control Register</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPTIOPISELx</name>
|
|
<description>Capacitive Touch IO pin select</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPISELx_0</name>
|
|
<description>Px.0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPISELx_1</name>
|
|
<description>Px.1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPISELx_2</name>
|
|
<description>Px.2</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPISELx_3</name>
|
|
<description>Px.3</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPISELx_4</name>
|
|
<description>Px.4</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPISELx_5</name>
|
|
<description>Px.5</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPISELx_6</name>
|
|
<description>Px.6</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPISELx_7</name>
|
|
<description>Px.7</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTIOPOSELx</name>
|
|
<description>Capacitive Touch IO port select</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_0</name>
|
|
<description>Px = PJ</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_1</name>
|
|
<description>Px = P1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_2</name>
|
|
<description>Px = P2</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_3</name>
|
|
<description>Px = P3</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_4</name>
|
|
<description>Px = P4</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_5</name>
|
|
<description>Px = P5</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_6</name>
|
|
<description>Px = P6</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_7</name>
|
|
<description>Px = P7</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_8</name>
|
|
<description>Px = P8</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_9</name>
|
|
<description>Px = P9</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_10</name>
|
|
<description>Px = P10</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_11</name>
|
|
<description>Px = P11</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_12</name>
|
|
<description>Px = P12</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_13</name>
|
|
<description>Px = P13</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_14</name>
|
|
<description>Px = P14</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_15</name>
|
|
<description>Px = P15</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTIOEN</name>
|
|
<description>Capacitive Touch IO enable</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAPTIOEN_0</name>
|
|
<description>All Capacitive Touch IOs are disabled. Signal towards timers is 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOEN_1</name>
|
|
<description>Selected Capacitive Touch IO is enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTIOSTATE</name>
|
|
<description>Capacitive Touch IO state</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>CAPTIOSTATE_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>CAPTIOSTATE_0</name>
|
|
<description>Curent state 0 or Capacitive Touch IO is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOSTATE_1</name>
|
|
<description>Current state 1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CAPTIO1</name>
|
|
<version>356.0</version>
|
|
<description>CAPTIO1</description>
|
|
<baseAddress>0x40005800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CAPTIOxCTL</name>
|
|
<displayName>CTL</displayName>
|
|
<description>Capacitive Touch IO x Control Register</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPTIOPISELx</name>
|
|
<description>Capacitive Touch IO pin select</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPISELx_0</name>
|
|
<description>Px.0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPISELx_1</name>
|
|
<description>Px.1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPISELx_2</name>
|
|
<description>Px.2</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPISELx_3</name>
|
|
<description>Px.3</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPISELx_4</name>
|
|
<description>Px.4</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPISELx_5</name>
|
|
<description>Px.5</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPISELx_6</name>
|
|
<description>Px.6</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPISELx_7</name>
|
|
<description>Px.7</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTIOPOSELx</name>
|
|
<description>Capacitive Touch IO port select</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_0</name>
|
|
<description>Px = PJ</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_1</name>
|
|
<description>Px = P1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_2</name>
|
|
<description>Px = P2</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_3</name>
|
|
<description>Px = P3</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_4</name>
|
|
<description>Px = P4</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_5</name>
|
|
<description>Px = P5</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_6</name>
|
|
<description>Px = P6</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_7</name>
|
|
<description>Px = P7</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_8</name>
|
|
<description>Px = P8</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_9</name>
|
|
<description>Px = P9</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_10</name>
|
|
<description>Px = P10</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_11</name>
|
|
<description>Px = P11</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_12</name>
|
|
<description>Px = P12</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_13</name>
|
|
<description>Px = P13</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_14</name>
|
|
<description>Px = P14</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOPOSELx_15</name>
|
|
<description>Px = P15</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTIOEN</name>
|
|
<description>Capacitive Touch IO enable</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAPTIOEN_0</name>
|
|
<description>All Capacitive Touch IOs are disabled. Signal towards timers is 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOEN_1</name>
|
|
<description>Selected Capacitive Touch IO is enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTIOSTATE</name>
|
|
<description>Capacitive Touch IO state</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>CAPTIOSTATE_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>CAPTIOSTATE_0</name>
|
|
<description>Curent state 0 or Capacitive Touch IO is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTIOSTATE_1</name>
|
|
<description>Current state 1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIMER32</name>
|
|
<version>356.0</version>
|
|
<description>TIMER32</description>
|
|
<baseAddress>0x4000C000</baseAddress>
|
|
<interrupt>
|
|
<name>T32_INT1_IRQ</name>
|
|
<description>T32_INT1 Interrupt</description>
|
|
<value>25</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>T32_INT2_IRQ</name>
|
|
<description>T32_INT2 Interrupt</description>
|
|
<value>26</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>T32_INTC_IRQ</name>
|
|
<description>T32_INTC Interrupt</description>
|
|
<value>27</value>
|
|
</interrupt>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xF0C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>T32LOAD1</name>
|
|
<displayName>LOAD1</displayName>
|
|
<description>Timer 1 Load Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOAD</name>
|
|
<description>The value from which the Timer 1 counter decrements</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>T32VALUE1</name>
|
|
<displayName>VALUE1</displayName>
|
|
<description>Timer 1 Current Value Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xffffffff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Current value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>T32CONTROL1</name>
|
|
<displayName>CONTROL1</displayName>
|
|
<description>Timer 1 Timer Control Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000020</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ONESHOT</name>
|
|
<description>Selects one-shot or wrapping counter mode</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONESHOT_0</name>
|
|
<description>wrapping mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONESHOT_1</name>
|
|
<description>one-shot mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SIZE</name>
|
|
<description>Selects 16 or 32 bit counter operation</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SIZE_0</name>
|
|
<description>16-bit counter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SIZE_1</name>
|
|
<description>32-bit counter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESCALE</name>
|
|
<description>Prescale bits</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRESCALE_0</name>
|
|
<description>0 stages of prescale, clock is divided by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESCALE_1</name>
|
|
<description>4 stages of prescale, clock is divided by 16</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESCALE_2</name>
|
|
<description>8 stages of prescale, clock is divided by 256</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IE</name>
|
|
<description>Interrupt enable bit</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IE_0</name>
|
|
<description>Timer interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IE_1</name>
|
|
<description>Timer interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Mode bit</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MODE_0</name>
|
|
<description>Timer is in free-running mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE_1</name>
|
|
<description>Timer is in periodic mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable bit</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLE_0</name>
|
|
<description>Timer disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_1</name>
|
|
<description>Timer enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>T32INTCLR1</name>
|
|
<displayName>INTCLR1</displayName>
|
|
<description>Timer 1 Interrupt Clear Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTCLR</name>
|
|
<description>Write clears interrupt output</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>T32RIS1</name>
|
|
<displayName>RIS1</displayName>
|
|
<description>Timer 1 Raw Interrupt Status Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RAW_IFG</name>
|
|
<description>Raw interrupt status</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>T32MIS1</name>
|
|
<displayName>MIS1</displayName>
|
|
<description>Timer 1 Interrupt Status Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IFG</name>
|
|
<description>Enabled interrupt status</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>T32BGLOAD1</name>
|
|
<displayName>BGLOAD1</displayName>
|
|
<description>Timer 1 Background Load Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BGLOAD</name>
|
|
<description>Value from which the counter decrements</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>T32LOAD2</name>
|
|
<displayName>LOAD2</displayName>
|
|
<description>Timer 2 Load Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOAD</name>
|
|
<description>The value from which the Timer 2 counter decrements</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>T32VALUE2</name>
|
|
<displayName>VALUE2</displayName>
|
|
<description>Timer 2 Current Value Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xffffffff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Current value of the decrementing counter</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>T32CONTROL2</name>
|
|
<displayName>CONTROL2</displayName>
|
|
<description>Timer 2 Timer Control Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000020</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ONESHOT</name>
|
|
<description>Selects one-shot or wrapping counter mode</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONESHOT_0</name>
|
|
<description>wrapping mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONESHOT_1</name>
|
|
<description>one-shot mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SIZE</name>
|
|
<description>Selects 16 or 32 bit counter operation</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SIZE_0</name>
|
|
<description>16-bit counter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SIZE_1</name>
|
|
<description>32-bit counter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESCALE</name>
|
|
<description>Prescale bits</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRESCALE_0</name>
|
|
<description>0 stages of prescale, clock is divided by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESCALE_1</name>
|
|
<description>4 stages of prescale, clock is divided by 16</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESCALE_2</name>
|
|
<description>8 stages of prescale, clock is divided by 256</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IE</name>
|
|
<description>Interrupt enable bit</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IE_0</name>
|
|
<description>Timer interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IE_1</name>
|
|
<description>Timer interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Mode bit</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MODE_0</name>
|
|
<description>Timer is in free-running mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE_1</name>
|
|
<description>Timer is in periodic mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable bit</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLE_0</name>
|
|
<description>Timer disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_1</name>
|
|
<description>Timer enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>T32INTCLR2</name>
|
|
<displayName>INTCLR2</displayName>
|
|
<description>Timer 2 Interrupt Clear Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTCLR</name>
|
|
<description>Write clears the interrupt output</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>T32RIS2</name>
|
|
<displayName>RIS2</displayName>
|
|
<description>Timer 2 Raw Interrupt Status Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RAW_IFG</name>
|
|
<description>Raw interrupt status</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>T32MIS2</name>
|
|
<displayName>MIS2</displayName>
|
|
<description>Timer 2 Interrupt Status Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IFG</name>
|
|
<description>Enabled interrupt status</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>T32BGLOAD2</name>
|
|
<displayName>BGLOAD2</displayName>
|
|
<description>Timer 2 Background Load Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BGLOAD</name>
|
|
<description>Value from which the counter decrements</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DMA</name>
|
|
<version>356.0</version>
|
|
<description>DMA</description>
|
|
<baseAddress>0x4000E000</baseAddress>
|
|
<interrupt>
|
|
<name>DMA_ERR_IRQ</name>
|
|
<description>DMA_ERR Interrupt</description>
|
|
<value>30</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA_INT3_IRQ</name>
|
|
<description>DMA_INT3 Interrupt</description>
|
|
<value>31</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA_INT2_IRQ</name>
|
|
<description>DMA_INT2 Interrupt</description>
|
|
<value>32</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA_INT1_IRQ</name>
|
|
<description>DMA_INT1 Interrupt</description>
|
|
<value>33</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA_INT0_IRQ</name>
|
|
<description>DMA_INT0 Interrupt</description>
|
|
<value>34</value>
|
|
</interrupt>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1050</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DMA_DEVICE_CFG</name>
|
|
<displayName>DEVICE_CFG</displayName>
|
|
<description>Device Configuration Status</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffff0000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NUM_DMA_CHANNELS</name>
|
|
<description>Number of DMA channels available</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NUM_SRC_PER_CHANNEL</name>
|
|
<description>Number of DMA sources per channel</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_SW_CHTRIG</name>
|
|
<displayName>SW_CHTRIG</displayName>
|
|
<description>Software Channel Trigger Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Write 1, triggers DMA_CHANNEL0</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Write 1, triggers DMA_CHANNEL1</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>Write 1, triggers DMA_CHANNEL2</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>Write 1, triggers DMA_CHANNEL3</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4</name>
|
|
<description>Write 1, triggers DMA_CHANNEL4</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5</name>
|
|
<description>Write 1, triggers DMA_CHANNEL5</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6</name>
|
|
<description>Write 1, triggers DMA_CHANNEL6</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7</name>
|
|
<description>Write 1, triggers DMA_CHANNEL7</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH8</name>
|
|
<description>Write 1, triggers DMA_CHANNEL8</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH9</name>
|
|
<description>Write 1, triggers DMA_CHANNEL9</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH10</name>
|
|
<description>Write 1, triggers DMA_CHANNEL10</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH11</name>
|
|
<description>Write 1, triggers DMA_CHANNEL11</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH12</name>
|
|
<description>Write 1, triggers DMA_CHANNEL12</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH13</name>
|
|
<description>Write 1, triggers DMA_CHANNEL13</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH14</name>
|
|
<description>Write 1, triggers DMA_CHANNEL14</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH15</name>
|
|
<description>Write 1, triggers DMA_CHANNEL15</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH16</name>
|
|
<description>Write 1, triggers DMA_CHANNEL16</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH17</name>
|
|
<description>Write 1, triggers DMA_CHANNEL17</description>
|
|
<bitOffset>0x11</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH18</name>
|
|
<description>Write 1, triggers DMA_CHANNEL18</description>
|
|
<bitOffset>0x12</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH19</name>
|
|
<description>Write 1, triggers DMA_CHANNEL19</description>
|
|
<bitOffset>0x13</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH20</name>
|
|
<description>Write 1, triggers DMA_CHANNEL20</description>
|
|
<bitOffset>0x14</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH21</name>
|
|
<description>Write 1, triggers DMA_CHANNEL21</description>
|
|
<bitOffset>0x15</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH22</name>
|
|
<description>Write 1, triggers DMA_CHANNEL22</description>
|
|
<bitOffset>0x16</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH23</name>
|
|
<description>Write 1, triggers DMA_CHANNEL23</description>
|
|
<bitOffset>0x17</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH24</name>
|
|
<description>Write 1, triggers DMA_CHANNEL24</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH25</name>
|
|
<description>Write 1, triggers DMA_CHANNEL25</description>
|
|
<bitOffset>0x19</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH26</name>
|
|
<description>Write 1, triggers DMA_CHANNEL26</description>
|
|
<bitOffset>0x1A</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH27</name>
|
|
<description>Write 1, triggers DMA_CHANNEL27</description>
|
|
<bitOffset>0x1B</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH28</name>
|
|
<description>Write 1, triggers DMA_CHANNEL28</description>
|
|
<bitOffset>0x1C</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH29</name>
|
|
<description>Write 1, triggers DMA_CHANNEL29</description>
|
|
<bitOffset>0x1D</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH30</name>
|
|
<description>Write 1, triggers DMA_CHANNEL30</description>
|
|
<bitOffset>0x1E</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH31</name>
|
|
<description>Write 1, triggers DMA_CHANNEL31</description>
|
|
<bitOffset>0x1F</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31</dimIndex>
|
|
<name>DMA_CH_SRCCFG[%s]</name>
|
|
<displayName>CH_SRCCFG[%s]</displayName>
|
|
<description>Channel n Source Configuration Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMA_SRC</name>
|
|
<description>Device level DMA source mapping to channel input</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_INT1_SRCCFG</name>
|
|
<displayName>INT1_SRCCFG</displayName>
|
|
<description>Interrupt 1 Source Channel Configuration</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INT_SRC</name>
|
|
<description>Controls which channel's completion event is mapped as a source of this Interrupt</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Enables DMA_INT1 mapping</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_INT2_SRCCFG</name>
|
|
<displayName>INT2_SRCCFG</displayName>
|
|
<description>Interrupt 2 Source Channel Configuration Register</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INT_SRC</name>
|
|
<description>Controls which channel's completion event is mapped as a source of this Interrupt</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Enables DMA_INT2 mapping</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_INT3_SRCCFG</name>
|
|
<displayName>INT3_SRCCFG</displayName>
|
|
<description>Interrupt 3 Source Channel Configuration Register</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INT_SRC</name>
|
|
<description>Controls which channel's completion event is mapped as a source of this Interrupt</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Enables DMA_INT3 mapping</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_INT0_SRCFLG</name>
|
|
<displayName>INT0_SRCFLG</displayName>
|
|
<description>Interrupt 0 Source Channel Flag Register</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel 0 was the source of DMA_INT0</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel 1 was the source of DMA_INT0</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>Channel 2 was the source of DMA_INT0</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>Channel 3 was the source of DMA_INT0</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4</name>
|
|
<description>Channel 4 was the source of DMA_INT0</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5</name>
|
|
<description>Channel 5 was the source of DMA_INT0</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6</name>
|
|
<description>Channel 6 was the source of DMA_INT0</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7</name>
|
|
<description>Channel 7 was the source of DMA_INT0</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH8</name>
|
|
<description>Channel 8 was the source of DMA_INT0</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH9</name>
|
|
<description>Channel 9 was the source of DMA_INT0</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH10</name>
|
|
<description>Channel 10 was the source of DMA_INT0</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH11</name>
|
|
<description>Channel 11 was the source of DMA_INT0</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH12</name>
|
|
<description>Channel 12 was the source of DMA_INT0</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH13</name>
|
|
<description>Channel 13 was the source of DMA_INT0</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH14</name>
|
|
<description>Channel 14 was the source of DMA_INT0</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH15</name>
|
|
<description>Channel 15 was the source of DMA_INT0</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH16</name>
|
|
<description>Channel 16 was the source of DMA_INT0</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH17</name>
|
|
<description>Channel 17 was the source of DMA_INT0</description>
|
|
<bitOffset>0x11</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH18</name>
|
|
<description>Channel 18 was the source of DMA_INT0</description>
|
|
<bitOffset>0x12</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH19</name>
|
|
<description>Channel 19 was the source of DMA_INT0</description>
|
|
<bitOffset>0x13</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH20</name>
|
|
<description>Channel 20 was the source of DMA_INT0</description>
|
|
<bitOffset>0x14</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH21</name>
|
|
<description>Channel 21 was the source of DMA_INT0</description>
|
|
<bitOffset>0x15</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH22</name>
|
|
<description>Channel 22 was the source of DMA_INT0</description>
|
|
<bitOffset>0x16</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH23</name>
|
|
<description>Channel 23 was the source of DMA_INT0</description>
|
|
<bitOffset>0x17</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH24</name>
|
|
<description>Channel 24 was the source of DMA_INT0</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH25</name>
|
|
<description>Channel 25 was the source of DMA_INT0</description>
|
|
<bitOffset>0x19</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH26</name>
|
|
<description>Channel 26 was the source of DMA_INT0</description>
|
|
<bitOffset>0x1A</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH27</name>
|
|
<description>Channel 27 was the source of DMA_INT0</description>
|
|
<bitOffset>0x1B</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH28</name>
|
|
<description>Channel 28 was the source of DMA_INT0</description>
|
|
<bitOffset>0x1C</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH29</name>
|
|
<description>Channel 29 was the source of DMA_INT0</description>
|
|
<bitOffset>0x1D</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH30</name>
|
|
<description>Channel 30 was the source of DMA_INT0</description>
|
|
<bitOffset>0x1E</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH31</name>
|
|
<description>Channel 31 was the source of DMA_INT0</description>
|
|
<bitOffset>0x1F</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_INT0_CLRFLG</name>
|
|
<displayName>INT0_CLRFLG</displayName>
|
|
<description>Interrupt 0 Source Channel Clear Flag Register</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH8</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH9</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH10</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH11</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH12</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH13</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH14</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH15</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH16</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH17</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0x11</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH18</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0x12</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH19</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0x13</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH20</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0x14</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH21</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0x15</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH22</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0x16</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH23</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0x17</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH24</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH25</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0x19</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH26</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0x1A</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH27</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0x1B</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH28</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0x1C</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH29</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0x1D</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH30</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0x1E</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH31</name>
|
|
<description>Clear corresponding DMA_INT0_SRCFLG_REG</description>
|
|
<bitOffset>0x1F</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_STAT</name>
|
|
<displayName>STAT</displayName>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x1000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0f00ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MASTEN</name>
|
|
<description>Enable status of the controller</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>MASTEN_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>MASTEN_0</name>
|
|
<description>Controller disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MASTEN_1</name>
|
|
<description>Controller enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STATE</name>
|
|
<description>Current state of the control state machine.
|
|
State can be one of the following:</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>STATE_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>STATE_0</name>
|
|
<description>idle</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATE_1</name>
|
|
<description>reading channel controller data</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATE_2</name>
|
|
<description>reading source data end pointer</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATE_3</name>
|
|
<description>reading destination data end pointer</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATE_4</name>
|
|
<description>reading source data</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATE_5</name>
|
|
<description>writing destination data</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATE_6</name>
|
|
<description>waiting for DMA request to clear</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATE_7</name>
|
|
<description>writing channel controller data</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATE_8</name>
|
|
<description>stalled</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATE_9</name>
|
|
<description>done</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATE_10</name>
|
|
<description>peripheral scatter-gather transition</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMACHANS</name>
|
|
<description>Number of available DMA channels minus one.</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x5</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>DMACHANS_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>DMACHANS_0</name>
|
|
<description>Controller configured to use 1 DMA channel</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMACHANS_1</name>
|
|
<description>Controller configured to use 2 DMA channels</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMACHANS_30</name>
|
|
<description>Controller configured to use 31 DMA channels</description>
|
|
<value>30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMACHANS_31</name>
|
|
<description>Controller configured to use 32 DMA channels</description>
|
|
<value>31</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TESTSTAT</name>
|
|
<description>To reduce the gate count the controller can be configured to exclude the integration test logic.
|
|
The values 2h to Fh are Reserved.</description>
|
|
<bitOffset>0x1C</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>TESTSTAT_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>TESTSTAT_0</name>
|
|
<description>Controller does not include the integration test logic</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TESTSTAT_1</name>
|
|
<description>Controller includes the integration test logic</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_CFG</name>
|
|
<displayName>CFG</displayName>
|
|
<description>Configuration Register</description>
|
|
<addressOffset>0x1004</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MASTEN</name>
|
|
<description>Enable status of the controller</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>MASTEN_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>MASTEN_0</name>
|
|
<description>Controller disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MASTEN_1</name>
|
|
<description>Controller enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHPROTCTRL</name>
|
|
<description>Sets the AHB-Lite protection by controlling the HPROT[3:1] signal
|
|
levels as follows:
|
|
Bit [7] Controls HPROT[3] to indicate if a cacheable access is occurring.
|
|
Bit [6] Controls HPROT[2] to indicate if a bufferable access is occurring.
|
|
Bit [5] Controls HPROT[1] to indicate if a privileged access is occurring.
|
|
Note: When bit [n] = 1 then the corresponding HPROT is HIGH.
|
|
When bit [n] = 0 then the corresponding HPROT is LOW.</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_CTLBASE</name>
|
|
<displayName>CTLBASE</displayName>
|
|
<description>Channel Control Data Base Pointer Register</description>
|
|
<addressOffset>0x1008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Pointer to the base address of the primary data structure.</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1B</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_ALTBASE</name>
|
|
<displayName>ALTBASE</displayName>
|
|
<description>Channel Alternate Control Data Base Pointer Register</description>
|
|
<addressOffset>0x100C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffff00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Base address of the alternate data structure</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_WAITSTAT</name>
|
|
<displayName>WAITSTAT</displayName>
|
|
<description>Channel Wait on Request Status Register</description>
|
|
<addressOffset>0x1010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WAITREQ</name>
|
|
<description>Channel wait on request status.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>WAITREQ_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>WAITREQ_0</name>
|
|
<description>dma_waitonreq[C] is LOW.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAITREQ_1</name>
|
|
<description>dma_waitonreq[C] is HIGH.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_SWREQ</name>
|
|
<displayName>SWREQ</displayName>
|
|
<description>Channel Software Request Register</description>
|
|
<addressOffset>0x1014</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHNL_SW_REQ</name>
|
|
<description>Set the appropriate bit to generate a software DMA request on the
|
|
corresponding DMA channel.
|
|
Writing to a bit where a DMA channel is not implemented does not
|
|
create a DMA request for that channel.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CHNL_SW_REQ_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CHNL_SW_REQ_0</name>
|
|
<description>Does not create a DMA request for the channel</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CHNL_SW_REQ_1</name>
|
|
<description>Creates a DMA request for the channel</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_USEBURSTSET</name>
|
|
<displayName>USEBURSTSET</displayName>
|
|
<description>Channel Useburst Set Register</description>
|
|
<addressOffset>0x1018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SET</name>
|
|
<description>Returns the useburst status, or disables dma_sreq from generating DMA requests.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<name>SET_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>SET_0_READ</name>
|
|
<description>DMA channel C responds to requests that it receives on dma_req[C] or dma_sreq[C].
|
|
The controller performs 2R, or single, bus transfers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_1_READ</name>
|
|
<description>DMA channel C does not respond to requests that it receives on dma_sreq[C].
|
|
The controller only responds to dma_req[C] requests and performs 2R transfers.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
<enumeratedValues>
|
|
<name>SET_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>SET_0_WRITE</name>
|
|
<description>No effect. Use the DMA_USEBURST_CLR Register to set bit [C] to 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_1_WRITE</name>
|
|
<description>Disables dma_sreq[C] from generating DMA requests.
|
|
The controller performs 2R transfers.
|
|
Writing to a bit where a DMA channel is not implemented has no effect.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_USEBURSTCLR</name>
|
|
<displayName>USEBURSTCLR</displayName>
|
|
<description>Channel Useburst Clear Register</description>
|
|
<addressOffset>0x101C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLR</name>
|
|
<description>Set the appropriate bit to enable dma_sreq to generate requests.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLR_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLR_0</name>
|
|
<description>No effect.
|
|
Use the DMA_USEBURST_SET Register to disable dma_sreq from generating requests.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLR_1</name>
|
|
<description>Enables dma_sreq[C] to generate DMA requests.
|
|
Writing to a bit where a DMA channel is not implemented has no effect.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_REQMASKSET</name>
|
|
<displayName>REQMASKSET</displayName>
|
|
<description>Channel Request Mask Set Register</description>
|
|
<addressOffset>0x1020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SET</name>
|
|
<description>Returns the request mask status of dma_req and dma_sreq, or
|
|
disables the corresponding channel from generating DMA requests.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<name>SET_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>SET_0_READ</name>
|
|
<description>External requests are enabled for channel C.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_1_READ</name>
|
|
<description>External requests are disabled for channel C.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
<enumeratedValues>
|
|
<name>SET_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>SET_0_WRITE</name>
|
|
<description>No effect.
|
|
Use the DMA_REQMASKCLR Register to enable DMA requests.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_1_WRITE</name>
|
|
<description>Disables dma_req[C] and dma_sreq[C] from generating DMA requests.
|
|
Writing to a bit where a DMA channel is not implemented has no effect.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_REQMASKCLR</name>
|
|
<displayName>REQMASKCLR</displayName>
|
|
<description>Channel Request Mask Clear Register</description>
|
|
<addressOffset>0x1024</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLR</name>
|
|
<description>Set the appropriate bit to enable DMA requests for the channel
|
|
corresponding to dma_req and dma_sreq.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLR_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLR_0</name>
|
|
<description>No effect.
|
|
Use the DMA_REQMASKSET Register to disable dma_req and
|
|
dma_sreq from generating requests.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLR_1</name>
|
|
<description>Enables dma_req[C] or dma_sreq[C] to generate DMA requests.
|
|
Writing to a bit where a DMA channel is not implemented has no effect.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_ENASET</name>
|
|
<displayName>ENASET</displayName>
|
|
<description>Channel Enable Set Register</description>
|
|
<addressOffset>0x1028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SET</name>
|
|
<description>Returns the enable status of the channels, or enables the
|
|
corresponding channels.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<name>SET_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>SET_0_READ</name>
|
|
<description>Channel C is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_1_READ</name>
|
|
<description>Channel C is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
<enumeratedValues>
|
|
<name>SET_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>SET_0_WRITE</name>
|
|
<description>No effect.
|
|
Use the DMA_ENACLR Register to disable a channel.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_1_WRITE</name>
|
|
<description>Enables channel C.
|
|
Writing to a bit where a DMA channel is not implemented has no effect.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_ENACLR</name>
|
|
<displayName>ENACLR</displayName>
|
|
<description>Channel Enable Clear Register</description>
|
|
<addressOffset>0x102C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLR</name>
|
|
<description>Set the appropriate bit to disable the corresponding DMA channel.
|
|
Note: The controller disables a channel, by setting the appropriate
|
|
bit, when:
|
|
a) it completes the DMA cycle
|
|
b) it reads a channel_cfg memory location which has cycle_ctrl =
|
|
b000
|
|
c) an ERROR occurs on the AHB-Lite bus.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLR_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLR_0</name>
|
|
<description>No effect.
|
|
Use the DMA_ENASET Register to enable DMA channels.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLR_1</name>
|
|
<description>Disables channel C.
|
|
Writing to a bit where a DMA channel is not implemented has no effect.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_ALTSET</name>
|
|
<displayName>ALTSET</displayName>
|
|
<description>Channel Primary-Alternate Set Register</description>
|
|
<addressOffset>0x1030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SET</name>
|
|
<description>Channel Primary-Alternate Set Register</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<name>SET_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>SET_0_READ</name>
|
|
<description>DMA channel C is using the primary data structure.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_1_READ</name>
|
|
<description>DMA channel C is using the alternate data structure.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
<enumeratedValues>
|
|
<name>SET_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>SEL_0_WRITE</name>
|
|
<description>No effect.
|
|
Use the DMA_ALTCLR Register to set bit [C] to 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEL_1_WRITE</name>
|
|
<description>Selects the alternate data structure for channel C.
|
|
Writing to a bit where a DMA channel is not implemented has no effect.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_ALTCLR</name>
|
|
<displayName>ALTCLR</displayName>
|
|
<description>Channel Primary-Alternate Clear Register</description>
|
|
<addressOffset>0x1034</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLR</name>
|
|
<description>Channel Primary-Alternate Clear Register</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLR_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLR_0</name>
|
|
<description>No effect.
|
|
Use the DMA_ALTSET Register to select the alternate data structure.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLR_1</name>
|
|
<description>Selects the primary data structure for channel C.
|
|
Writing to a bit where a DMA channel is not implemented has no effect.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_PRIOSET</name>
|
|
<displayName>PRIOSET</displayName>
|
|
<description>Channel Priority Set Register</description>
|
|
<addressOffset>0x1038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SET</name>
|
|
<description>Returns the channel priority mask status, or sets the channel priority
|
|
to high.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<name>SET_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>SET_0_READ</name>
|
|
<description>DMA channel C is using the default priority level.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_1_READ</name>
|
|
<description>DMA channel C is using a high priority level.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
<enumeratedValues>
|
|
<name>SET_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>SET_0_WRITE</name>
|
|
<description>No effect.
|
|
Use the DMA_PRIOCLR Register to set channel C to the default priority level.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_1_WRITE</name>
|
|
<description>Channel C uses the high priority level.
|
|
Writing to a bit where a DMA channel is not implemented has no effect.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_PRIOCLR</name>
|
|
<displayName>PRIOCLR</displayName>
|
|
<description>Channel Priority Clear Register</description>
|
|
<addressOffset>0x103C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLR</name>
|
|
<description>Set the appropriate bit to select the default priority level for the
|
|
specified DMA channel.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLR_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLR_0</name>
|
|
<description>No effect.
|
|
Use the DMA_PRIOSET Register to set channel C to the high priority level.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLR_1</name>
|
|
<description>Channel C uses the default priority level.
|
|
Writing to a bit where a DMA channel is not implemented has no effect.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_ERRCLR</name>
|
|
<displayName>ERRCLR</displayName>
|
|
<description>Bus Error Clear Register</description>
|
|
<addressOffset>0x104C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ERRCLR</name>
|
|
<description>Returns the status of dma_err, or sets the signal LOW.
|
|
|
|
For test purposes, use the ERRSET register to set dma_err HIGH.
|
|
Note: If you deassert dma_err at the same time as an ERROR
|
|
occurs on the AHB-Lite bus, then the ERROR condition takes
|
|
precedence and dma_err remains asserted.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<name>ERRCLR_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ERRCLR_0_READ</name>
|
|
<description>dma_err is LOW</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERRCLR_1_READ</name>
|
|
<description>dma_err is HIGH.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
<enumeratedValues>
|
|
<name>ERRCLR_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>ERRCLR_0_WRITE</name>
|
|
<description>No effect, status of dma_err is unchanged.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERRCLR_1_WRITE</name>
|
|
<description>Sets dma_err LOW.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PCM</name>
|
|
<version>356.0</version>
|
|
<description>PCM</description>
|
|
<baseAddress>0x40010000</baseAddress>
|
|
<interrupt>
|
|
<name>PCM_IRQ</name>
|
|
<description>PCM Interrupt</description>
|
|
<value>2</value>
|
|
</interrupt>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x14</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PCMCTL0</name>
|
|
<displayName>CTL0</displayName>
|
|
<description>Control 0 Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xa5960000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AMR</name>
|
|
<description>Active Mode Request</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AMR_0</name>
|
|
<description>LDO based Active Mode at Core voltage setting 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AMR_1</name>
|
|
<description>LDO based Active Mode at Core voltage setting 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AMR_4</name>
|
|
<description>DC-DC based Active Mode at Core voltage setting 0.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AMR_5</name>
|
|
<description>DC-DC based Active Mode at Core voltage setting 1.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AMR_8</name>
|
|
<description>Low-Frequency Active Mode at Core voltage setting 0.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AMR_9</name>
|
|
<description>Low-Frequency Active Mode at Core voltage setting 1.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPMR</name>
|
|
<description>Low Power Mode Request</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPMR_0</name>
|
|
<description>LPM3. Core voltage setting is similar to the mode from which LPM3 is entered.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPMR_10</name>
|
|
<description>LPM3.5. Core voltage setting 0.</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPMR_12</name>
|
|
<description>LPM4.5</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPM</name>
|
|
<description>Current Power Mode</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x6</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>CPM_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>CPM_0</name>
|
|
<description>LDO based Active Mode at Core voltage setting 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CPM_1</name>
|
|
<description>LDO based Active Mode at Core voltage setting 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CPM_4</name>
|
|
<description>DC-DC based Active Mode at Core voltage setting 0.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CPM_5</name>
|
|
<description>DC-DC based Active Mode at Core voltage setting 1.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CPM_8</name>
|
|
<description>Low-Frequency Active Mode at Core voltage setting 0.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CPM_9</name>
|
|
<description>Low-Frequency Active Mode at Core voltage setting 1.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CPM_16</name>
|
|
<description>LDO based LPM0 at Core voltage setting 0.</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CPM_17</name>
|
|
<description>LDO based LPM0 at Core voltage setting 1.</description>
|
|
<value>17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CPM_20</name>
|
|
<description>DC-DC based LPM0 at Core voltage setting 0.</description>
|
|
<value>20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CPM_21</name>
|
|
<description>DC-DC based LPM0 at Core voltage setting 1.</description>
|
|
<value>21</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CPM_24</name>
|
|
<description>Low-Frequency LPM0 at Core voltage setting 0.</description>
|
|
<value>24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CPM_25</name>
|
|
<description>Low-Frequency LPM0 at Core voltage setting 1.</description>
|
|
<value>25</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CPM_32</name>
|
|
<description>LPM3</description>
|
|
<value>32</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCMKEY</name>
|
|
<description>PCM key</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCMCTL1</name>
|
|
<displayName>CTL1</displayName>
|
|
<description>Control 1 Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xa5960000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCKLPM5</name>
|
|
<description>Lock LPM5</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOCKLPM5_0</name>
|
|
<description>LPMx.5 configuration defaults to reset condition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKLPM5_1</name>
|
|
<description>LPMx.5 configuration remains locked during LPMx.5 entry and exit</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOCKBKUP</name>
|
|
<description>Lock Backup</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOCKBKUP_0</name>
|
|
<description>Backup domain configuration defaults to reset condition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKBKUP_1</name>
|
|
<description>Backup domain configuration remains locked during LPM3.5 entry and exit</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FORCE_LPM_ENTRY</name>
|
|
<description>Force LPM entry</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FORCE_LPM_ENTRY_0</name>
|
|
<description>PCM aborts LPM3/LPMx.5 transition if the active clock configuration does not meet the LPM3/LPMx.5 entry criteria. PCM generates the LPM_INVALID_CLK flag on abort to LPM3/LPMx.5 entry.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_LPM_ENTRY_1</name>
|
|
<description>PCM enters LPM3/LPMx.5 after shuting off the clocks forcefully. Application needs to ensure RTC and WDT are clocked using BCLK tree to keep these modules alive in LPM3/LPM3.5. In LPM4.5 all clocks are forcefully shutoff and the core voltage is turned off.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PMR_BUSY</name>
|
|
<description>Power mode request busy flag</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PCMKEY</name>
|
|
<description>PCM key</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCMIE</name>
|
|
<displayName>IE</displayName>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LPM_INVALID_TR_IE</name>
|
|
<description>LPM invalid transition interrupt enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPM_INVALID_TR_IE_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPM_INVALID_TR_IE_1</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPM_INVALID_CLK_IE</name>
|
|
<description>LPM invalid clock interrupt enable</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPM_INVALID_CLK_IE_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPM_INVALID_CLK_IE_1</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AM_INVALID_TR_IE</name>
|
|
<description>Active mode invalid transition interrupt enable</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AM_INVALID_TR_IE_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AM_INVALID_TR_IE_1</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCDC_ERROR_IE</name>
|
|
<description>DC-DC error interrupt enable</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DCDC_ERROR_IE_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DCDC_ERROR_IE_1</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCMIFG</name>
|
|
<displayName>IFG</displayName>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LPM_INVALID_TR_IFG</name>
|
|
<description>LPM invalid transition flag</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LPM_INVALID_CLK_IFG</name>
|
|
<description>LPM invalid clock flag</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AM_INVALID_TR_IFG</name>
|
|
<description>Active mode invalid transition flag</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DCDC_ERROR_IFG</name>
|
|
<description>DC-DC error flag</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCMCLRIFG</name>
|
|
<displayName>CLRIFG</displayName>
|
|
<description>Clear Interrupt Flag Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLR_LPM_INVALID_TR_IFG</name>
|
|
<description>Clear LPM invalid transition flag</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLR_LPM_INVALID_CLK_IFG</name>
|
|
<description>Clear LPM invalid clock flag</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLR_AM_INVALID_TR_IFG</name>
|
|
<description>Clear active mode invalid transition flag</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLR_DCDC_ERROR_IFG</name>
|
|
<description>Clear DC-DC error flag</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CS</name>
|
|
<version>356.0</version>
|
|
<description>CS</description>
|
|
<baseAddress>0x40010400</baseAddress>
|
|
<interrupt>
|
|
<name>CS_IRQ</name>
|
|
<description>CS Interrupt</description>
|
|
<value>1</value>
|
|
</interrupt>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x68</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CSKEY</name>
|
|
<displayName>KEY</displayName>
|
|
<description>Key Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000a596</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CSKEY</name>
|
|
<description>Write xxxx_695Ah to unlock</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSCTL0</name>
|
|
<displayName>CTL0</displayName>
|
|
<description>Control 0 Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00010000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DCOTUNE</name>
|
|
<description>DCO frequency tuning select</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0xA</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DCORSEL</name>
|
|
<description>DCO frequency range select</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DCORSEL_0</name>
|
|
<description>Nominal DCO Frequency Range (MHz): 1 to 2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DCORSEL_1</name>
|
|
<description>Nominal DCO Frequency Range (MHz): 2 to 4</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DCORSEL_2</name>
|
|
<description>Nominal DCO Frequency Range (MHz): 4 to 8</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DCORSEL_3</name>
|
|
<description>Nominal DCO Frequency Range (MHz): 8 to 16</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DCORSEL_4</name>
|
|
<description>Nominal DCO Frequency Range (MHz): 16 to 32</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DCORSEL_5</name>
|
|
<description>Nominal DCO Frequency Range (MHz): 32 to 64</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCORES</name>
|
|
<description>Enables the DCO external resistor mode</description>
|
|
<bitOffset>0x16</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DCORES_0</name>
|
|
<description>Internal resistor mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DCORES_1</name>
|
|
<description>External resistor mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCOEN</name>
|
|
<description>Enables the DCO oscillator</description>
|
|
<bitOffset>0x17</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DCOEN_0</name>
|
|
<description>DCO is on if it is used as a source for MCLK, HSMCLK , or SMCLK and clock is requested, otherwise it is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DCOEN_1</name>
|
|
<description>DCO is on</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSCTL1</name>
|
|
<displayName>CTL1</displayName>
|
|
<description>Control 1 Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000033</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SELM</name>
|
|
<description>Selects the MCLK source</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SELM_0</name>
|
|
<description>when LFXT available, otherwise REFOCLK</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELM_1</name>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELM_2</name>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELM_3</name>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELM_4</name>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELM_5</name>
|
|
<description>when HFXT available, otherwise DCOCLK</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELM_6</name>
|
|
<description>when HFXT2 available, otherwise DCOCLK</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELM_7</name>
|
|
<description>for future use. Defaults to DCOCLK. Not recommended for use
|
|
to ensure future compatibilities.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELS</name>
|
|
<description>Selects the SMCLK and HSMCLK source</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SELS_0</name>
|
|
<description>when LFXT available, otherwise REFOCLK</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELS_1</name>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELS_2</name>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELS_3</name>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELS_4</name>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELS_5</name>
|
|
<description>when HFXT available, otherwise DCOCLK</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELS_6</name>
|
|
<description>when HFXT2 available, otherwise DCOCLK</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELS_7</name>
|
|
<description>for furture use. Defaults to DCOCLK. Do not use to ensure future compatibilities.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELA</name>
|
|
<description>Selects the ACLK source</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SELA_0</name>
|
|
<description>when LFXT available, otherwise REFOCLK</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELA_1</name>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELA_2</name>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELA_3</name>
|
|
<description>for future use. Defaults to REFOCLK. Not recommended
|
|
for use to ensure future compatibilities.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELA_4</name>
|
|
<description>for future use. Defaults to REFOCLK. Not recommended
|
|
for use to ensure future compatibilities.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELA_5</name>
|
|
<description>for future use. Defaults to REFOCLK. Not recommended
|
|
for use to ensure future compatibilities.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELA_6</name>
|
|
<description>for future use. Defaults to REFOCLK. Not recommended
|
|
for use to ensure future compatibilities.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELA_7</name>
|
|
<description>for future use. Defaults to REFOCLK. Not recommended
|
|
for use to ensure future compatibilities.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELB</name>
|
|
<description>Selects the BCLK source</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SELB_0</name>
|
|
<description>LFXTCLK</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELB_1</name>
|
|
<description>REFOCLK</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIVM</name>
|
|
<description>MCLK source divider</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIVM_0</name>
|
|
<description>f(MCLK)/1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVM_1</name>
|
|
<description>f(MCLK)/2</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVM_2</name>
|
|
<description>f(MCLK)/4</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVM_3</name>
|
|
<description>f(MCLK)/8</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVM_4</name>
|
|
<description>f(MCLK)/16</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVM_5</name>
|
|
<description>f(MCLK)/32</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVM_6</name>
|
|
<description>f(MCLK)/64</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVM_7</name>
|
|
<description>f(MCLK)/128</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIVHS</name>
|
|
<description>HSMCLK source divider</description>
|
|
<bitOffset>0x14</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIVHS_0</name>
|
|
<description>f(HSMCLK)/1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVHS_1</name>
|
|
<description>f(HSMCLK)/2</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVHS_2</name>
|
|
<description>f(HSMCLK)/4</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVHS_3</name>
|
|
<description>f(HSMCLK)/8</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVHS_4</name>
|
|
<description>f(HSMCLK)/16</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVHS_5</name>
|
|
<description>f(HSMCLK)/32</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVHS_6</name>
|
|
<description>f(HSMCLK)/64</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVHS_7</name>
|
|
<description>f(HSMCLK)/128</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIVA</name>
|
|
<description>ACLK source divider</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIVA_0</name>
|
|
<description>f(ACLK)/1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVA_1</name>
|
|
<description>f(ACLK)/2</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVA_2</name>
|
|
<description>f(ACLK)/4</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVA_3</name>
|
|
<description>f(ACLK)/8</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVA_4</name>
|
|
<description>f(ACLK)/16</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVA_5</name>
|
|
<description>f(ACLK)/32</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVA_6</name>
|
|
<description>f(ACLK)/64</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVA_7</name>
|
|
<description>f(ACLK)/128</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIVS</name>
|
|
<description>SMCLK source divider</description>
|
|
<bitOffset>0x1C</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIVS_0</name>
|
|
<description>f(SMCLK)/1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVS_1</name>
|
|
<description>f(SMCLK)/2</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVS_2</name>
|
|
<description>f(SMCLK)/4</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVS_3</name>
|
|
<description>f(SMCLK)/8</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVS_4</name>
|
|
<description>f(SMCLK)/16</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVS_5</name>
|
|
<description>f(SMCLK)/32</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVS_6</name>
|
|
<description>f(SMCLK)/64</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVS_7</name>
|
|
<description>f(SMCLK)/128</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSCTL2</name>
|
|
<displayName>CTL2</displayName>
|
|
<description>Control 2 Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00010003</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LFXTDRIVE</name>
|
|
<description>LFXT oscillator current can be adjusted to its drive needs</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LFXTDRIVE_0</name>
|
|
<description>Lowest drive strength and current consumption LFXT oscillator.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFXTDRIVE_1</name>
|
|
<description>Increased drive strength LFXT oscillator.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFXTDRIVE_2</name>
|
|
<description>Increased drive strength LFXT oscillator.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFXTDRIVE_3</name>
|
|
<description>Maximum drive strength and maximum current consumption LFXT oscillator.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LFXTAGCOFF</name>
|
|
<description>Disables the automatic gain control of the LFXT crystal</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LFXTAGCOFF_0</name>
|
|
<description>AGC enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFXTAGCOFF_1</name>
|
|
<description>AGC disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LFXT_EN</name>
|
|
<description>Turns on the LFXT oscillator regardless if used as a clock resource</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LFXT_EN_0</name>
|
|
<description>LFXT is on if it is used as a source for ACLK, MCLK, HSMCLK , or SMCLK
|
|
and is selected via the port selection and not in bypass mode of operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFXT_EN_1</name>
|
|
<description>LFXT is on if LFXT is selected via the port selection and LFXT is not in
|
|
bypass mode of operation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LFXTBYPASS</name>
|
|
<description>LFXT bypass select</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LFXTBYPASS_0</name>
|
|
<description>LFXT sourced by external crystal.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFXTBYPASS_1</name>
|
|
<description>LFXT sourced by external square wave.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HFXTDRIVE</name>
|
|
<description>HFXT oscillator drive selection</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HFXTDRIVE_0</name>
|
|
<description>To be used for HFXTFREQ setting 000b</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFXTDRIVE_1</name>
|
|
<description>To be used for HFXTFREQ settings 001b to 110b</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HFXTFREQ</name>
|
|
<description>HFXT frequency selection</description>
|
|
<bitOffset>0x14</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HFXTFREQ_0</name>
|
|
<description>1 MHz to 4 MHz</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFXTFREQ_1</name>
|
|
<description>>4 MHz to 8 MHz</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFXTFREQ_2</name>
|
|
<description>>8 MHz to 16 MHz</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFXTFREQ_3</name>
|
|
<description>>16 MHz to 24 MHz</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFXTFREQ_4</name>
|
|
<description>>24 MHz to 32 MHz</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFXTFREQ_5</name>
|
|
<description>>32 MHz to 40 MHz</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFXTFREQ_6</name>
|
|
<description>>40 MHz to 48 MHz</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HFXT_EN</name>
|
|
<description>Turns on the HFXT oscillator regardless if used as a clock resource</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HFXT_EN_0</name>
|
|
<description>HFXT is on if it is used as a source for MCLK, HSMCLK , or SMCLK and is selected via the port selection and not in bypass mode of operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFXT_EN_1</name>
|
|
<description>HFXT is on if HFXT is selected via the port selection and HFXT is not in bypass mode of operation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HFXTBYPASS</name>
|
|
<description>HFXT bypass select</description>
|
|
<bitOffset>0x19</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HFXTBYPASS_0</name>
|
|
<description>HFXT sourced by external crystal.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFXTBYPASS_1</name>
|
|
<description>HFXT sourced by external square wave.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSCTL3</name>
|
|
<displayName>CTL3</displayName>
|
|
<description>Control 3 Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000bbb</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FCNTLF</name>
|
|
<description>Start flag counter for LFXT</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FCNTLF_0</name>
|
|
<description>4096 cycles</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FCNTLF_1</name>
|
|
<description>8192 cycles</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FCNTLF_2</name>
|
|
<description>16384 cycles</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FCNTLF_3</name>
|
|
<description>32768 cycles</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFCNTLF</name>
|
|
<description>Reset start fault counter for LFXT</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>RFCNTLF_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>RFCNTLF_0</name>
|
|
<description>Not applicable. Always reads as zero due to self clearing.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RFCNTLF_1</name>
|
|
<description>Restarts the counter immediately.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FCNTLF_EN</name>
|
|
<description>Enable start fault counter for LFXT</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FCNTLF_EN_0</name>
|
|
<description>Startup fault counter disabled. Counter is cleared.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FCNTLF_EN_1</name>
|
|
<description>Startup fault counter enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FCNTHF</name>
|
|
<description>Start flag counter for HFXT</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FCNTHF_0</name>
|
|
<description>2048 cycles</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FCNTHF_1</name>
|
|
<description>4096 cycles</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FCNTHF_2</name>
|
|
<description>8192 cycles</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FCNTHF_3</name>
|
|
<description>16384 cycles</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFCNTHF</name>
|
|
<description>Reset start fault counter for HFXT</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>RFCNTHF_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>RFCNTHF_0</name>
|
|
<description>Not applicable. Always reads as zero due to self clearing.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RFCNTHF_1</name>
|
|
<description>Restarts the counter immediately.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FCNTHF_EN</name>
|
|
<description>Enable start fault counter for HFXT</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FCNTHF_EN_0</name>
|
|
<description>Startup fault counter disabled. Counter is cleared.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FCNTHF_EN_1</name>
|
|
<description>Startup fault counter enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FCNTHF2</name>
|
|
<description>Start flag counter for HFXT2</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FCNTHF2_0</name>
|
|
<description>2048 cycles</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FCNTHF2_1</name>
|
|
<description>4096 cycles</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FCNTHF2_2</name>
|
|
<description>8192 cycles</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FCNTHF2_3</name>
|
|
<description>16384 cycles</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFCNTHF2</name>
|
|
<description>Reset start fault counter for HFXT2</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>RFCNTHF2_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>RFCNTHF2_0</name>
|
|
<description>Not applicable. Always reads as zero due to self clearing.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RFCNTHF2_1</name>
|
|
<description>Restarts the counter immediately.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FCNTHF2_EN</name>
|
|
<description>Enable start fault counter for HFXT2</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FCNTHF2_EN_0</name>
|
|
<description>Startup fault counter disabled. Counter is cleared.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FCNTHF2_EN_1</name>
|
|
<description>Startup fault counter enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSCLKEN</name>
|
|
<displayName>CLKEN</displayName>
|
|
<description>Clock Enable Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000000f</resetValue>
|
|
<resetMask>0xffff847f</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACLK_EN</name>
|
|
<description>ACLK system clock conditional request enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ACLK_EN_0</name>
|
|
<description>ACLK disabled regardless of conditional clock requests</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACLK_EN_1</name>
|
|
<description>ACLK enabled based on any conditional clock requests</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MCLK_EN</name>
|
|
<description>MCLK system clock conditional request enable</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MCLK_EN_0</name>
|
|
<description>MCLK disabled regardless of conditional clock requests</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCLK_EN_1</name>
|
|
<description>MCLK enabled based on any conditional clock requests</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HSMCLK_EN</name>
|
|
<description>HSMCLK system clock conditional request enable</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HSMCLK_EN_0</name>
|
|
<description>HSMCLK disabled regardless of conditional clock requests</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HSMCLK_EN_1</name>
|
|
<description>HSMCLK enabled based on any conditional clock requests</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMCLK_EN</name>
|
|
<description>SMCLK system clock conditional request enable</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMCLK_EN_0</name>
|
|
<description>SMCLK disabled regardless of conditional clock requests.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMCLK_EN_1</name>
|
|
<description>SMCLK enabled based on any conditional clock requests</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VLO_EN</name>
|
|
<description>Turns on the VLO oscillator</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>VLO_EN_0</name>
|
|
<description>VLO is on only if it is used as a source for ACLK, MCLK, HSMCLK or SMCLK.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VLO_EN_1</name>
|
|
<description>VLO is on</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFO_EN</name>
|
|
<description>Turns on the REFO oscillator</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFO_EN_0</name>
|
|
<description>REFO is on only if it is used as a source for ACLK, MCLK, HSMCLK or SMCLK</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFO_EN_1</name>
|
|
<description>REFO is on</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODOSC_EN</name>
|
|
<description>Turns on the MODOSC oscillator</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MODOSC_EN_0</name>
|
|
<description>MODOSC is on only if it is used as a source for ACLK, MCLK, HSMCLK or SMCLK</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODOSC_EN_1</name>
|
|
<description>MODOSC is on</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFOFSEL</name>
|
|
<description>Selects REFO nominal frequency</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFOFSEL_0</name>
|
|
<description>32 kHz</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFOFSEL_1</name>
|
|
<description>128 kHz</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSSTAT</name>
|
|
<displayName>STAT</displayName>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<resetMask>0xffff01ff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DCO_ON</name>
|
|
<description>DCO status</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>DCO_ON_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>DCO_ON_0</name>
|
|
<description>Inactive</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DCO_ON_1</name>
|
|
<description>Active</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCOBIAS_ON</name>
|
|
<description>DCO bias status</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>DCOBIAS_ON_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>DCOBIAS_ON_0</name>
|
|
<description>Inactive</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DCOBIAS_ON_1</name>
|
|
<description>Active</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HFXT_ON</name>
|
|
<description>HFXT status</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>HFXT_ON_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>HFXT_ON_0</name>
|
|
<description>Inactive</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFXT_ON_1</name>
|
|
<description>Active</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HFXT2_ON</name>
|
|
<description>HFXT2 status</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>HFXT2_ON_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>HFXT2_ON_0</name>
|
|
<description>Inactive</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFXT2_ON_1</name>
|
|
<description>Active</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODOSC_ON</name>
|
|
<description>MODOSC status</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>MODOSC_ON_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>MODOSC_ON_0</name>
|
|
<description>Inactive</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODOSC_ON_1</name>
|
|
<description>Active</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VLO_ON</name>
|
|
<description>VLO status</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>VLO_ON_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>VLO_ON_0</name>
|
|
<description>Inactive</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VLO_ON_1</name>
|
|
<description>Active</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LFXT_ON</name>
|
|
<description>LFXT status</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>LFXT_ON_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>LFXT_ON_0</name>
|
|
<description>Inactive</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFXT_ON_1</name>
|
|
<description>Active</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFO_ON</name>
|
|
<description>REFO status</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>REFO_ON_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>REFO_ON_0</name>
|
|
<description>Inactive</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFO_ON_1</name>
|
|
<description>Active</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACLK_ON</name>
|
|
<description>ACLK system clock status</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ACLK_ON_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ACLK_ON_0</name>
|
|
<description>Inactive</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACLK_ON_1</name>
|
|
<description>Active</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MCLK_ON</name>
|
|
<description>MCLK system clock status</description>
|
|
<bitOffset>0x11</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>MCLK_ON_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>MCLK_ON_0</name>
|
|
<description>Inactive</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCLK_ON_1</name>
|
|
<description>Active</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HSMCLK_ON</name>
|
|
<description>HSMCLK system clock status</description>
|
|
<bitOffset>0x12</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>HSMCLK_ON_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>HSMCLK_ON_0</name>
|
|
<description>Inactive</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HSMCLK_ON_1</name>
|
|
<description>Active</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMCLK_ON</name>
|
|
<description>SMCLK system clock status</description>
|
|
<bitOffset>0x13</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>SMCLK_ON_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>SMCLK_ON_0</name>
|
|
<description>Inactive</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMCLK_ON_1</name>
|
|
<description>Active</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODCLK_ON</name>
|
|
<description>MODCLK system clock status</description>
|
|
<bitOffset>0x14</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>MODCLK_ON_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>MODCLK_ON_0</name>
|
|
<description>Inactive</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODCLK_ON_1</name>
|
|
<description>Active</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VLOCLK_ON</name>
|
|
<description>VLOCLK system clock status</description>
|
|
<bitOffset>0x15</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>VLOCLK_ON_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>VLOCLK_ON_0</name>
|
|
<description>Inactive</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VLOCLK_ON_1</name>
|
|
<description>Active</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LFXTCLK_ON</name>
|
|
<description>LFXTCLK system clock status</description>
|
|
<bitOffset>0x16</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>LFXTCLK_ON_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>LFXTCLK_ON_0</name>
|
|
<description>Inactive</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFXTCLK_ON_1</name>
|
|
<description>Active</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFOCLK_ON</name>
|
|
<description>REFOCLK system clock status</description>
|
|
<bitOffset>0x17</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>REFOCLK_ON_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>REFOCLK_ON_0</name>
|
|
<description>Inactive</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFOCLK_ON_1</name>
|
|
<description>Active</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACLK_READY</name>
|
|
<description>ACLK Ready status</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ACLK_READY_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ACLK_READY_0</name>
|
|
<description>Not ready</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACLK_READY_1</name>
|
|
<description>Ready</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MCLK_READY</name>
|
|
<description>MCLK Ready status</description>
|
|
<bitOffset>0x19</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>MCLK_READY_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>MCLK_READY_0</name>
|
|
<description>Not ready</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCLK_READY_1</name>
|
|
<description>Ready</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HSMCLK_READY</name>
|
|
<description>HSMCLK Ready status</description>
|
|
<bitOffset>0x1A</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>HSMCLK_READY_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>HSMCLK_READY_0</name>
|
|
<description>Not ready</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HSMCLK_READY_1</name>
|
|
<description>Ready</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMCLK_READY</name>
|
|
<description>SMCLK Ready status</description>
|
|
<bitOffset>0x1B</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>SMCLK_READY_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>SMCLK_READY_0</name>
|
|
<description>Not ready</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMCLK_READY_1</name>
|
|
<description>Ready</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCLK_READY</name>
|
|
<description>BCLK Ready status</description>
|
|
<bitOffset>0x1C</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>BCLK_READY_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>BCLK_READY_0</name>
|
|
<description>Not ready</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BCLK_READY_1</name>
|
|
<description>Ready</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSIE</name>
|
|
<displayName>IE</displayName>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LFXTIE</name>
|
|
<description>LFXT oscillator fault flag interrupt enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LFXTIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFXTIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HFXTIE</name>
|
|
<description>HFXT oscillator fault flag interrupt enable</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HFXTIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFXTIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HFXT2IE</name>
|
|
<description>HFXT2 oscillator fault flag interrupt enable</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HFXT2IE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFXT2IE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCOR_OPNIE</name>
|
|
<description>DCO external resistor open circuit fault flag interrupt enable.</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DCOR_OPNIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DCOR_OPNIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FCNTLFIE</name>
|
|
<description>Start fault counter interrupt enable LFXT</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FCNTLFIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FCNTLFIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FCNTHFIE</name>
|
|
<description>Start fault counter interrupt enable HFXT</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FCNTHFIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FCNTHFIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FCNTHF2IE</name>
|
|
<description>Start fault counter interrupt enable HFXT2</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FCNTHF2IE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FCNTHF2IE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PLLOOLIE</name>
|
|
<description>PLL out-of-lock interrupt enable</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PLLOOLIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLLOOLIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PLLLOSIE</name>
|
|
<description>PLL loss-of-signal interrupt enable</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PLLLOSIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLLLOSIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PLLOORIE</name>
|
|
<description>PLL out-of-range interrupt enable</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PLLOORIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLLOORIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CALIE</name>
|
|
<description>REFCNT period counter interrupt enable</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CALIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CALIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSIFG</name>
|
|
<displayName>IFG</displayName>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LFXTIFG</name>
|
|
<description>LFXT oscillator fault flag</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>LFXTIFG_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>LFXTIFG_0</name>
|
|
<description>No fault condition occurred after the last reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFXTIFG_1</name>
|
|
<description>LFXT fault. A LFXT fault occurred after the last reset</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HFXTIFG</name>
|
|
<description>HFXT oscillator fault flag</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>HFXTIFG_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>HFXTIFG_0</name>
|
|
<description>No fault condition occurred after the last reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFXTIFG_1</name>
|
|
<description>HFXT fault. A HFXT fault occurred after the last reset</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HFXT2IFG</name>
|
|
<description>HFXT2 oscillator fault flag</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>HFXT2IFG_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>HFXT2IFG_0</name>
|
|
<description>No fault condition occurred after the last reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFXT2IFG_1</name>
|
|
<description>HFXT2 fault. A HFXT2 fault occurred after the last reset</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCOR_SHTIFG</name>
|
|
<description>DCO external resistor short circuit fault flag.</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>DCOR_SHTIFG_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>DCOR_SHTIFG_0</name>
|
|
<description>DCO external resistor present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DCOR_SHTIFG_1</name>
|
|
<description>DCO external resistor short circuit fault</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCOR_OPNIFG</name>
|
|
<description>DCO external resistor open circuit fault flag.</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>DCOR_OPNIFG_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>DCOR_OPNIFG_0</name>
|
|
<description>DCO external resistor present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DCOR_OPNIFG_1</name>
|
|
<description>DCO external resistor open circuit fault</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FCNTLFIFG</name>
|
|
<description>Start fault counter interrupt flag LFXT</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>FCNTLFIFG_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>FCNTLFIFG_0</name>
|
|
<description>Start counter not expired</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FCNTLFIFG_1</name>
|
|
<description>Start counter expired</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FCNTHFIFG</name>
|
|
<description>Start fault counter interrupt flag HFXT</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>FCNTHFIFG_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>FCNTHFIFG_0</name>
|
|
<description>Start counter not expired</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FCNTHFIFG_1</name>
|
|
<description>Start counter expired</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FCNTHF2IFG</name>
|
|
<description>Start fault counter interrupt flag HFXT2</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>FCNTHF2IFG_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>FCNTHF2IFG_0</name>
|
|
<description>Start counter not expired</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FCNTHF2IFG_1</name>
|
|
<description>Start counter expired</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PLLOOLIFG</name>
|
|
<description>PLL out-of-lock interrupt flag</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>PLLOOLIFG_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>PLLOOLIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLLOOLIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PLLLOSIFG</name>
|
|
<description>PLL loss-of-signal interrupt flag</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>PLLLOSIFG_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>PLLLOSIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLLLOSIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PLLOORIFG</name>
|
|
<description>PLL out-of-range interrupt flag</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>PLLOORIFG_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>PLLOORIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLLOORIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CALIFG</name>
|
|
<description>REFCNT period counter expired</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>CALIFG_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>CALIFG_0</name>
|
|
<description>REFCNT period counter not expired</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CALIFG_1</name>
|
|
<description>REFCNT period counter expired</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSCLRIFG</name>
|
|
<displayName>CLRIFG</displayName>
|
|
<description>Clear Interrupt Flag Register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLR_LFXTIFG</name>
|
|
<description>Clear LFXT oscillator fault interrupt flag</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLR_LFXTIFG_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLR_LFXTIFG_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLR_LFXTIFG_1</name>
|
|
<description>Clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLR_HFXTIFG</name>
|
|
<description>Clear HFXT oscillator fault interrupt flag</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLR_HFXTIFG_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLR_HFXTIFG_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLR_HFXTIFG_1</name>
|
|
<description>Clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLR_HFXT2IFG</name>
|
|
<description>Clear HFXT2 oscillator fault interrupt flag</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLR_HFXT2IFG_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLR_HFXT2IFG_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLR_HFXT2IFG_1</name>
|
|
<description>Clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLR_DCOR_OPNIFG</name>
|
|
<description>Clear DCO external resistor open circuit fault interrupt flag.</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLR_DCOR_OPNIFG_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLR_DCOR_OPNIFG_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLR_DCOR_OPNIFG_1</name>
|
|
<description>Clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLR_CALIFG</name>
|
|
<description>REFCNT period counter clear interrupt flag</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLR_CALIFG_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLR_CALIFG_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLR_CALIFG_1</name>
|
|
<description>Clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLR_FCNTLFIFG</name>
|
|
<description>Start fault counter clear interrupt flag LFXT</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLR_FCNTLFIFG_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLR_FCNTLFIFG_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLR_FCNTLFIFG_1</name>
|
|
<description>Clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLR_FCNTHFIFG</name>
|
|
<description>Start fault counter clear interrupt flag HFXT</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLR_FCNTHFIFG_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLR_FCNTHFIFG_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLR_FCNTHFIFG_1</name>
|
|
<description>Clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLR_FCNTHF2IFG</name>
|
|
<description>Start fault counter clear interrupt flag HFXT2</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLR_FCNTHF2IFG_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLR_FCNTHF2IFG_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLR_FCNTHF2IFG_1</name>
|
|
<description>Clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLR_PLLOOLIFG</name>
|
|
<description>PLL out-of-lock clear interrupt flag</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLR_PLLOOLIFG_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLR_PLLOOLIFG_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLR_PLLOOLIFG_1</name>
|
|
<description>Clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLR_PLLLOSIFG</name>
|
|
<description>PLL loss-of-signal clear interrupt flag</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLR_PLLLOSIFG_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLR_PLLLOSIFG_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLR_PLLLOSIFG_1</name>
|
|
<description>Clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLR_PLLOORIFG</name>
|
|
<description>PLL out-of-range clear interrupt flag</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLR_PLLOORIFG_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLR_PLLOORIFG_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLR_PLLOORIFG_1</name>
|
|
<description>Clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSSETIFG</name>
|
|
<displayName>SETIFG</displayName>
|
|
<description>Set Interrupt Flag Register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SET_LFXTIFG</name>
|
|
<description>Set LFXT oscillator fault interrupt flag</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>SET_LFXTIFG_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>SET_LFXTIFG_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_LFXTIFG_1</name>
|
|
<description>Set pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SET_HFXTIFG</name>
|
|
<description>Set HFXT oscillator fault interrupt flag</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>SET_HFXTIFG_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>SET_HFXTIFG_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_HFXTIFG_1</name>
|
|
<description>Set pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SET_HFXT2IFG</name>
|
|
<description>Set HFXT2 oscillator fault interrupt flag</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>SET_HFXT2IFG_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>SET_HFXT2IFG_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_HFXT2IFG_1</name>
|
|
<description>Set pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SET_DCOR_OPNIFG</name>
|
|
<description>Set DCO external resistor open circuit fault interrupt flag.</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>SET_DCOR_OPNIFG_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>SET_DCOR_OPNIFG_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_DCOR_OPNIFG_1</name>
|
|
<description>Set pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SET_CALIFG</name>
|
|
<description>REFCNT period counter set interrupt flag</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>SET_CALIFG_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>SET_CALIFG_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_CALIFG_1</name>
|
|
<description>Set pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SET_FCNTHFIFG</name>
|
|
<description>Start fault counter set interrupt flag HFXT</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>SET_FCNTHFIFG_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>SET_FCNTHFIFG_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_FCNTHFIFG_1</name>
|
|
<description>Set pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SET_FCNTHF2IFG</name>
|
|
<description>Start fault counter set interrupt flag HFXT2</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>SET_FCNTHF2IFG_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>SET_FCNTHF2IFG_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_FCNTHF2IFG_1</name>
|
|
<description>Set pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SET_FCNTLFIFG</name>
|
|
<description>Start fault counter set interrupt flag LFXT</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>SET_FCNTLFIFG_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>SET_FCNTLFIFG_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_FCNTLFIFG_1</name>
|
|
<description>Set pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SET_PLLOOLIFG</name>
|
|
<description>PLL out-of-lock set interrupt flag</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>SET_PLLOOLIFG_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>SET_PLLOOLIFG_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_PLLOOLIFG_1</name>
|
|
<description>Set pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SET_PLLLOSIFG</name>
|
|
<description>PLL loss-of-signal set interrupt flag</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>SET_PLLLOSIFG_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>SET_PLLLOSIFG_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_PLLLOSIFG_1</name>
|
|
<description>Set pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SET_PLLOORIFG</name>
|
|
<description>PLL out-of-range set interrupt flag</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>SET_PLLOORIFG_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>SET_PLLOORIFG_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_PLLOORIFG_1</name>
|
|
<description>Set pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSDCOERCAL0</name>
|
|
<displayName>DCOERCAL0</displayName>
|
|
<description>DCO External Resistor Cailbration 0 Register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x01000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DCO_TCCAL</name>
|
|
<description>DCO Temperature compensation calibration</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DCO_FCAL_RSEL04</name>
|
|
<description>DCO frequency calibration for DCO frequency range (DCORSEL) 0 to 4.</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0xA</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSDCOERCAL1</name>
|
|
<displayName>DCOERCAL1</displayName>
|
|
<description>DCO External Resistor Calibration 1 Register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000100</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DCO_FCAL_RSEL5</name>
|
|
<description>DCO frequency calibration for DCO frequency range (DCORSEL) 5.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0xA</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PSS</name>
|
|
<version>356.0</version>
|
|
<description>PSS</description>
|
|
<baseAddress>0x40010800</baseAddress>
|
|
<interrupt>
|
|
<name>PSS_IRQ</name>
|
|
<description>PSS Interrupt</description>
|
|
<value>0</value>
|
|
</interrupt>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x40</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PSSKEY</name>
|
|
<displayName>KEY</displayName>
|
|
<description>Key Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000a596</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PSSKEY</name>
|
|
<description>PSS control key</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSSCTL0</name>
|
|
<displayName>CTL0</displayName>
|
|
<description>Control 0 Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00002000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SVSMHOFF</name>
|
|
<description>SVSM high-side off</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SVSMHOFF_0</name>
|
|
<description>The SVSMH is on</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SVSMHOFF_1</name>
|
|
<description>The SVSMH is off</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SVSMHLP</name>
|
|
<description>SVSM high-side low power normal performance mode</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SVSMHLP_0</name>
|
|
<description>Full performance mode. See the device-specific data sheet for response times.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SVSMHLP_1</name>
|
|
<description>Low power normal performance mode in LPM3, LPM4, and LPMx.5, full performance in all other modes. See the device-specific data sheet for response times.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SVSMHS</name>
|
|
<description>Supply supervisor or monitor selection for the high-side</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SVSMHS_0</name>
|
|
<description>Configure as SVSH</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SVSMHS_1</name>
|
|
<description>Configure as SVMH</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SVSMHTH</name>
|
|
<description>SVSM high-side reset voltage level</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SVMHOE</name>
|
|
<description>SVSM high-side output enable</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SVMHOE_0</name>
|
|
<description>SVSMHIFG bit is not output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SVMHOE_1</name>
|
|
<description>SVSMHIFG bit is output to the device SVMHOUT pin. The device-specific port logic must be configured accordingly</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SVMHOUTPOLAL</name>
|
|
<description>SVMHOUT pin polarity active low</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SVMHOUTPOLAL_0</name>
|
|
<description>SVMHOUT is active high. An error condition is signaled by a 1 at the SVMHOUT pin</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SVMHOUTPOLAL_1</name>
|
|
<description>SVMHOUT is active low. An error condition is signaled by a 0 at the SVMHOUT pin</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCDC_FORCE</name>
|
|
<description>Force DC-DC regulator operation</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DCDC_FORCE_0</name>
|
|
<description>DC-DC regulator operation not forced. Automatic fail-safe mechanism switches the core voltage regulator from DC-DC to LDO when the supply voltage falls below the minimum supply voltage necessary for DC-DC operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DCDC_FORCE_1</name>
|
|
<description>DC-DC regulator operation forced. Automatic fail-safe mechanism is disabled and device continues to operate out of DC-DC regulator.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VCORETRAN</name>
|
|
<description>Controls core voltage level transition time</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>VCORETRAN_0</name>
|
|
<description>32 s / 100 mV</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VCORETRAN_1</name>
|
|
<description>64 s / 100 mV</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VCORETRAN_2</name>
|
|
<description>128 s / 100 mV (default)</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VCORETRAN_3</name>
|
|
<description>256 s / 100 mV</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSSIE</name>
|
|
<displayName>IE</displayName>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SVSMHIE</name>
|
|
<description>High-side SVSM interrupt enable</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SVSMHIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SVSMHIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSSIFG</name>
|
|
<displayName>IFG</displayName>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SVSMHIFG</name>
|
|
<description>High-side SVSM interrupt flag</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>SVSMHIFG_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>SVSMHIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SVSMHIFG_1</name>
|
|
<description>Interrupt due to SVSMH</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSSCLRIFG</name>
|
|
<displayName>CLRIFG</displayName>
|
|
<description>Clear Interrupt Flag Register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLRSVSMHIFG</name>
|
|
<description>SVSMH clear interrupt flag</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRSVSMHIFG_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRSVSMHIFG_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRSVSMHIFG_1</name>
|
|
<description>Clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FLCTL</name>
|
|
<version>356.0</version>
|
|
<description>FLCTL</description>
|
|
<baseAddress>0x40011000</baseAddress>
|
|
<interrupt>
|
|
<name>FLCTL_IRQ</name>
|
|
<description>Flash Controller Interrupt</description>
|
|
<value>5</value>
|
|
</interrupt>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x124</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>FLCTL_POWER_STAT</name>
|
|
<displayName>POWER_STAT</displayName>
|
|
<description>Power Status Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000080</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PSTAT</name>
|
|
<description>Flash power status</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PSTAT_0</name>
|
|
<description>Flash IP in power-down mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PSTAT_1</name>
|
|
<description>Flash IP Vdd domain power-up in progress</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PSTAT_2</name>
|
|
<description>PSS LDO_GOOD, IREF_OK and VREF_OK check in progress</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PSTAT_3</name>
|
|
<description>Flash IP SAFE_LV check in progress</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PSTAT_4</name>
|
|
<description>Flash IP Active</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PSTAT_5</name>
|
|
<description>Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PSTAT_6</name>
|
|
<description>Flash IP in Standby mode</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PSTAT_7</name>
|
|
<description>Flash IP in Current mirror boost state</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LDOSTAT</name>
|
|
<description>PSS FLDO GOOD status</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LDOSTAT_0</name>
|
|
<description>FLDO not GOOD</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDOSTAT_1</name>
|
|
<description>FLDO GOOD</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VREFSTAT</name>
|
|
<description>PSS VREF stable status</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>VREFSTAT_0</name>
|
|
<description>Flash LDO not stable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VREFSTAT_1</name>
|
|
<description>Flash LDO stable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IREFSTAT</name>
|
|
<description>PSS IREF stable status</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IREFSTAT_0</name>
|
|
<description>IREF not stable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IREFSTAT_1</name>
|
|
<description>IREF stable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIMSTAT</name>
|
|
<description>PSS trim done status</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TRIMSTAT_0</name>
|
|
<description>PSS trim not complete</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRIMSTAT_1</name>
|
|
<description>PSS trim complete</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RD_2T</name>
|
|
<description>Indicates if Flash is being accessed in 2T mode</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RD_2T_0</name>
|
|
<description>Flash reads are in 1T mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RD_2T_1</name>
|
|
<description>Flash reads are in 2T mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_BANK0_RDCTL</name>
|
|
<displayName>BANK0_RDCTL</displayName>
|
|
<description>Bank0 Read Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RD_MODE</name>
|
|
<description>Flash read mode control setting for Bank 0</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_0</name>
|
|
<description>Normal read mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_1</name>
|
|
<description>Read Margin 0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_2</name>
|
|
<description>Read Margin 1</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_3</name>
|
|
<description>Program Verify</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_4</name>
|
|
<description>Erase Verify</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_5</name>
|
|
<description>Leakage Verify</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_9</name>
|
|
<description>Read Margin 0B</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_10</name>
|
|
<description>Read Margin 1B</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUFI</name>
|
|
<description>Enables read buffering feature for instruction fetches to this Bank</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BUFD</name>
|
|
<description>Enables read buffering feature for data reads to this Bank</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WAIT</name>
|
|
<description>Number of wait states for read</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WAIT_0</name>
|
|
<description>0 wait states</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT_1</name>
|
|
<description>1 wait states</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT_2</name>
|
|
<description>2 wait states</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT_3</name>
|
|
<description>3 wait states</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT_4</name>
|
|
<description>4 wait states</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT_5</name>
|
|
<description>5 wait states</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT_6</name>
|
|
<description>6 wait states</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT_7</name>
|
|
<description>7 wait states</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT_8</name>
|
|
<description>8 wait states</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT_9</name>
|
|
<description>9 wait states</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT_10</name>
|
|
<description>10 wait states</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT_11</name>
|
|
<description>11 wait states</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT_12</name>
|
|
<description>12 wait states</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT_13</name>
|
|
<description>13 wait states</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT_14</name>
|
|
<description>14 wait states</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT_15</name>
|
|
<description>15 wait states</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RD_MODE_STATUS</name>
|
|
<description>Read mode</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_STATUS_0</name>
|
|
<description>Normal read mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_STATUS_1</name>
|
|
<description>Read Margin 0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_STATUS_2</name>
|
|
<description>Read Margin 1</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_STATUS_3</name>
|
|
<description>Program Verify</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_STATUS_4</name>
|
|
<description>Erase Verify</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_STATUS_5</name>
|
|
<description>Leakage Verify</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_STATUS_9</name>
|
|
<description>Read Margin 0B</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_STATUS_10</name>
|
|
<description>Read Margin 1B</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_BANK1_RDCTL</name>
|
|
<displayName>BANK1_RDCTL</displayName>
|
|
<description>Bank1 Read Control Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RD_MODE</name>
|
|
<description>Flash read mode control setting for Bank 0</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_0</name>
|
|
<description>Normal read mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_1</name>
|
|
<description>Read Margin 0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_2</name>
|
|
<description>Read Margin 1</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_3</name>
|
|
<description>Program Verify</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_4</name>
|
|
<description>Erase Verify</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_5</name>
|
|
<description>Leakage Verify</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_9</name>
|
|
<description>Read Margin 0B</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_10</name>
|
|
<description>Read Margin 1B</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUFI</name>
|
|
<description>Enables read buffering feature for instruction fetches to this Bank</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BUFD</name>
|
|
<description>Enables read buffering feature for data reads to this Bank</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RD_MODE_STATUS</name>
|
|
<description>Read mode</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_STATUS_0</name>
|
|
<description>Normal read mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_STATUS_1</name>
|
|
<description>Read Margin 0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_STATUS_2</name>
|
|
<description>Read Margin 1</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_STATUS_3</name>
|
|
<description>Program Verify</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_STATUS_4</name>
|
|
<description>Erase Verify</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_STATUS_5</name>
|
|
<description>Leakage Verify</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_STATUS_9</name>
|
|
<description>Read Margin 0B</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RD_MODE_STATUS_10</name>
|
|
<description>Read Margin 1B</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAIT</name>
|
|
<description>Number of wait states for read</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WAIT_0</name>
|
|
<description>0 wait states</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT_1</name>
|
|
<description>1 wait states</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT_2</name>
|
|
<description>2 wait states</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT_3</name>
|
|
<description>3 wait states</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT_4</name>
|
|
<description>4 wait states</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT_5</name>
|
|
<description>5 wait states</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT_6</name>
|
|
<description>6 wait states</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT_7</name>
|
|
<description>7 wait states</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT_8</name>
|
|
<description>8 wait states</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT_9</name>
|
|
<description>9 wait states</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT_10</name>
|
|
<description>10 wait states</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT_11</name>
|
|
<description>11 wait states</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT_12</name>
|
|
<description>12 wait states</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT_13</name>
|
|
<description>13 wait states</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT_14</name>
|
|
<description>14 wait states</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT_15</name>
|
|
<description>15 wait states</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_RDBRST_CTLSTAT</name>
|
|
<displayName>RDBRST_CTLSTAT</displayName>
|
|
<description>Read Burst/Compare Control and Status Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start of burst/compare operation</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MEM_TYPE</name>
|
|
<description>Type of memory that burst is carried out on</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MEM_TYPE_0</name>
|
|
<description>Main Memory</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MEM_TYPE_1</name>
|
|
<description>Information Memory</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MEM_TYPE_3</name>
|
|
<description>Engineering Memory</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STOP_FAIL</name>
|
|
<description>Terminate burst/compare operation</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATA_CMP</name>
|
|
<description>Data pattern used for comparison against memory read data</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DATA_CMP_0</name>
|
|
<description>0000_0000_0000_0000_0000_0000_0000_0000</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA_CMP_1</name>
|
|
<description>FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEST_EN</name>
|
|
<description>Enable comparison against test data compare registers</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BRST_STAT</name>
|
|
<description>Status of Burst/Compare operation</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BRST_STAT_0</name>
|
|
<description>Idle</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BRST_STAT_1</name>
|
|
<description>Burst/Compare START bit written, but operation pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BRST_STAT_2</name>
|
|
<description>Burst/Compare in progress</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BRST_STAT_3</name>
|
|
<description>Burst complete (status of completed burst remains in this state unless explicitly cleared by SW)</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP_ERR</name>
|
|
<description>Burst/Compare Operation encountered atleast one data</description>
|
|
<bitOffset>0x12</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADDR_ERR</name>
|
|
<description>Burst/Compare Operation was terminated due to access to</description>
|
|
<bitOffset>0x13</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLR_STAT</name>
|
|
<description>Clear status bits 19-16 of this register</description>
|
|
<bitOffset>0x17</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_RDBRST_STARTADDR</name>
|
|
<displayName>RDBRST_STARTADDR</displayName>
|
|
<description>Read Burst/Compare Start Address Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START_ADDRESS</name>
|
|
<description>Start Address of Burst Operation</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_RDBRST_LEN</name>
|
|
<displayName>RDBRST_LEN</displayName>
|
|
<description>Read Burst/Compare Length Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BURST_LENGTH</name>
|
|
<description>Length of Burst Operation</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_RDBRST_FAILADDR</name>
|
|
<displayName>RDBRST_FAILADDR</displayName>
|
|
<description>Read Burst/Compare Fail Address Register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FAIL_ADDRESS</name>
|
|
<description>Reflects address of last failed compare</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_RDBRST_FAILCNT</name>
|
|
<displayName>RDBRST_FAILCNT</displayName>
|
|
<description>Read Burst/Compare Fail Count Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FAIL_COUNT</name>
|
|
<description>Number of failures encountered in burst operation</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_PRG_CTLSTAT</name>
|
|
<displayName>PRG_CTLSTAT</displayName>
|
|
<description>Program Control and Status Register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x0000000c</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Master control for all word program operations</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLE_0</name>
|
|
<description>Word program operation disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_1</name>
|
|
<description>Word program operation enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Write mode</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MODE_0</name>
|
|
<description>Write immediate mode. Starts program operation immediately on each write to the Flash</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE_1</name>
|
|
<description>Full word write mode. Flash controller collates data over multiple writes to compose the full 128bit word before initiating the program operation</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VER_PRE</name>
|
|
<description>Controls automatic pre program verify operations</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>VER_PRE_0</name>
|
|
<description>No pre program verification</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VER_PRE_1</name>
|
|
<description>Pre verify feature automatically invoked for each write operation (irrespective of the mode)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VER_PST</name>
|
|
<description>Controls automatic post program verify operations</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>VER_PST_0</name>
|
|
<description>No post program verification</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VER_PST_1</name>
|
|
<description>Post verify feature automatically invoked for each write operation (irrespective of the mode)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STATUS</name>
|
|
<description>Status of program operations in the Flash memory</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STATUS_0</name>
|
|
<description>Idle (no program operation currently active)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATUS_1</name>
|
|
<description>Single word program operation triggered, but pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATUS_2</name>
|
|
<description>Single word program in progress</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BNK_ACT</name>
|
|
<description>Bank active</description>
|
|
<bitOffset>0x12</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BNK_ACT_0</name>
|
|
<description>Word in Bank0 being programmed</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BNK_ACT_1</name>
|
|
<description>Word in Bank1 being programmed</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_PRGBRST_CTLSTAT</name>
|
|
<displayName>PRGBRST_CTLSTAT</displayName>
|
|
<description>Program Burst Control and Status Register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x000000c0</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Trigger start of burst program operation</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TYPE</name>
|
|
<description>Type of memory that burst program is carried out on</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TYPE_0</name>
|
|
<description>Main Memory</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TYPE_1</name>
|
|
<description>Information Memory</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TYPE_3</name>
|
|
<description>Engineering Memory</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LEN</name>
|
|
<description>Length of burst</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LEN_0</name>
|
|
<description>No burst operation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEN_1</name>
|
|
<description>1 word burst of 128 bits, starting with address in the FLCTL_PRGBRST_STARTADDR Register</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEN_2</name>
|
|
<description>2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEN_3</name>
|
|
<description>3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEN_4</name>
|
|
<description>4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO_PRE</name>
|
|
<description>Auto-Verify operation before the Burst Program</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AUTO_PRE_0</name>
|
|
<description>No program verify operations carried out</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUTO_PRE_1</name>
|
|
<description>Causes an automatic Burst Program Verify after the Burst Program Operation</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO_PST</name>
|
|
<description>Auto-Verify operation after the Burst Program</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AUTO_PST_0</name>
|
|
<description>No program verify operations carried out</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUTO_PST_1</name>
|
|
<description>Causes an automatic Burst Program Verify before the Burst Program Operation</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BURST_STATUS</name>
|
|
<description>Status of a Burst Operation</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BURST_STATUS_0</name>
|
|
<description>Idle (Burst not active)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BURST_STATUS_1</name>
|
|
<description>Burst program started but pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BURST_STATUS_2</name>
|
|
<description>Burst active, with 1st 128 bit word being written into Flash</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BURST_STATUS_3</name>
|
|
<description>Burst active, with 2nd 128 bit word being written into Flash</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BURST_STATUS_4</name>
|
|
<description>Burst active, with 3rd 128 bit word being written into Flash</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BURST_STATUS_5</name>
|
|
<description>Burst active, with 4th 128 bit word being written into Flash</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BURST_STATUS_7</name>
|
|
<description>Burst Complete (status of completed burst remains in this state unless explicitly cleared by SW)</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRE_ERR</name>
|
|
<description>Burst Operation encountered preprogram auto-verify errors</description>
|
|
<bitOffset>0x13</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PST_ERR</name>
|
|
<description>Burst Operation encountered postprogram auto-verify errors</description>
|
|
<bitOffset>0x14</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADDR_ERR</name>
|
|
<description>Burst Operation was terminated due to attempted program of reserved memory</description>
|
|
<bitOffset>0x15</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLR_STAT</name>
|
|
<description>Clear status bits 21-16 of this register</description>
|
|
<bitOffset>0x17</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_PRGBRST_STARTADDR</name>
|
|
<displayName>PRGBRST_STARTADDR</displayName>
|
|
<description>Program Burst Start Address Register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START_ADDRESS</name>
|
|
<description>Start Address of Program Burst Operation</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_PRGBRST_DATA0_0</name>
|
|
<displayName>PRGBRST_DATA0_0</displayName>
|
|
<description>Program Burst Data0 Register0</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0xffffffff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATAIN</name>
|
|
<description>Program Burst 128 bit Data Word 0</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_PRGBRST_DATA0_1</name>
|
|
<displayName>PRGBRST_DATA0_1</displayName>
|
|
<description>Program Burst Data0 Register1</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0xffffffff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATAIN</name>
|
|
<description>Program Burst 128 bit Data Word 0</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_PRGBRST_DATA0_2</name>
|
|
<displayName>PRGBRST_DATA0_2</displayName>
|
|
<description>Program Burst Data0 Register2</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0xffffffff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATAIN</name>
|
|
<description>Program Burst 128 bit Data Word 0</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_PRGBRST_DATA0_3</name>
|
|
<displayName>PRGBRST_DATA0_3</displayName>
|
|
<description>Program Burst Data0 Register3</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0xffffffff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATAIN</name>
|
|
<description>Program Burst 128 bit Data Word 0</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_PRGBRST_DATA1_0</name>
|
|
<displayName>PRGBRST_DATA1_0</displayName>
|
|
<description>Program Burst Data1 Register0</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0xffffffff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATAIN</name>
|
|
<description>Program Burst 128 bit Data Word 1</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_PRGBRST_DATA1_1</name>
|
|
<displayName>PRGBRST_DATA1_1</displayName>
|
|
<description>Program Burst Data1 Register1</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0xffffffff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATAIN</name>
|
|
<description>Program Burst 128 bit Data Word 1</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_PRGBRST_DATA1_2</name>
|
|
<displayName>PRGBRST_DATA1_2</displayName>
|
|
<description>Program Burst Data1 Register2</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0xffffffff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATAIN</name>
|
|
<description>Program Burst 128 bit Data Word 1</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_PRGBRST_DATA1_3</name>
|
|
<displayName>PRGBRST_DATA1_3</displayName>
|
|
<description>Program Burst Data1 Register3</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0xffffffff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATAIN</name>
|
|
<description>Program Burst 128 bit Data Word 1</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_PRGBRST_DATA2_0</name>
|
|
<displayName>PRGBRST_DATA2_0</displayName>
|
|
<description>Program Burst Data2 Register0</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0xffffffff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATAIN</name>
|
|
<description>Program Burst 128 bit Data Word 2</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_PRGBRST_DATA2_1</name>
|
|
<displayName>PRGBRST_DATA2_1</displayName>
|
|
<description>Program Burst Data2 Register1</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0xffffffff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATAIN</name>
|
|
<description>Program Burst 128 bit Data Word 2</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_PRGBRST_DATA2_2</name>
|
|
<displayName>PRGBRST_DATA2_2</displayName>
|
|
<description>Program Burst Data2 Register2</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0xffffffff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATAIN</name>
|
|
<description>Program Burst 128 bit Data Word 2</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_PRGBRST_DATA2_3</name>
|
|
<displayName>PRGBRST_DATA2_3</displayName>
|
|
<description>Program Burst Data2 Register3</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0xffffffff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATAIN</name>
|
|
<description>Program Burst 128 bit Data Word 2</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_PRGBRST_DATA3_0</name>
|
|
<displayName>PRGBRST_DATA3_0</displayName>
|
|
<description>Program Burst Data3 Register0</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0xffffffff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATAIN</name>
|
|
<description>Program Burst 128 bit Data Word 3</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_PRGBRST_DATA3_1</name>
|
|
<displayName>PRGBRST_DATA3_1</displayName>
|
|
<description>Program Burst Data3 Register1</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0xffffffff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATAIN</name>
|
|
<description>Program Burst 128 bit Data Word 3</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_PRGBRST_DATA3_2</name>
|
|
<displayName>PRGBRST_DATA3_2</displayName>
|
|
<description>Program Burst Data3 Register2</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0xffffffff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATAIN</name>
|
|
<description>Program Burst 128 bit Data Word 3</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_PRGBRST_DATA3_3</name>
|
|
<displayName>PRGBRST_DATA3_3</displayName>
|
|
<description>Program Burst Data3 Register3</description>
|
|
<addressOffset>0x9C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0xffffffff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATAIN</name>
|
|
<description>Program Burst 128 bit Data Word 3</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_ERASE_CTLSTAT</name>
|
|
<displayName>ERASE_CTLSTAT</displayName>
|
|
<description>Erase Control and Status Register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start of Erase operation</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Erase mode selected by application</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MODE_0</name>
|
|
<description>Sector Erase (controlled by FLTCTL_ERASE_SECTADDR)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE_1</name>
|
|
<description>Mass Erase (includes all Main and Information memory sectors that don't have corresponding WE bits set)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TYPE</name>
|
|
<description>Type of memory that erase operation is carried out on</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TYPE_0</name>
|
|
<description>Main Memory</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TYPE_1</name>
|
|
<description>Information Memory</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TYPE_3</name>
|
|
<description>Engineering Memory</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STATUS</name>
|
|
<description>Status of erase operations in the Flash memory</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STATUS_0</name>
|
|
<description>Idle (no program operation currently active)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATUS_1</name>
|
|
<description>Erase operation triggered to START but pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATUS_2</name>
|
|
<description>Erase operation in progress</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATUS_3</name>
|
|
<description>Erase operation completed (status of completed erase remains in this state unless explicitly cleared by SW)</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADDR_ERR</name>
|
|
<description>Erase Operation was terminated due to attempted erase of reserved memory address</description>
|
|
<bitOffset>0x12</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLR_STAT</name>
|
|
<description>Clear status bits 18-16 of this register</description>
|
|
<bitOffset>0x13</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_ERASE_SECTADDR</name>
|
|
<displayName>ERASE_SECTADDR</displayName>
|
|
<description>Erase Sector Address Register</description>
|
|
<addressOffset>0xA4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SECT_ADDRESS</name>
|
|
<description>Address of Sector being Erased</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_BANK0_INFO_WEPROT</name>
|
|
<displayName>BANK0_INFO_WEPROT</displayName>
|
|
<description>Information Memory Bank0 Write/Erase Protection Register</description>
|
|
<addressOffset>0xB0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000003</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PROT0</name>
|
|
<description>Protects Sector 0 from program or erase</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT1</name>
|
|
<description>Protects Sector 1 from program or erase</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_BANK0_MAIN_WEPROT</name>
|
|
<displayName>BANK0_MAIN_WEPROT</displayName>
|
|
<description>Main Memory Bank0 Write/Erase Protection Register</description>
|
|
<addressOffset>0xB4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0xffffffff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PROT0</name>
|
|
<description>Protects Sector 0 from program or erase</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT1</name>
|
|
<description>Protects Sector 1 from program or erase</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT2</name>
|
|
<description>Protects Sector 2 from program or erase</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT3</name>
|
|
<description>Protects Sector 3 from program or erase</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT4</name>
|
|
<description>Protects Sector 4 from program or erase</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT5</name>
|
|
<description>Protects Sector 5 from program or erase</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT6</name>
|
|
<description>Protects Sector 6 from program or erase</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT7</name>
|
|
<description>Protects Sector 7 from program or erase</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT8</name>
|
|
<description>Protects Sector 8 from program or erase</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT9</name>
|
|
<description>Protects Sector 9 from program or erase</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT10</name>
|
|
<description>Protects Sector 10 from program or erase</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT11</name>
|
|
<description>Protects Sector 11 from program or erase</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT12</name>
|
|
<description>Protects Sector 12 from program or erase</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT13</name>
|
|
<description>Protects Sector 13 from program or erase</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT14</name>
|
|
<description>Protects Sector 14 from program or erase</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT15</name>
|
|
<description>Protects Sector 15 from program or erase</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT16</name>
|
|
<description>Protects Sector 16 from program or erase</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT17</name>
|
|
<description>Protects Sector 17 from program or erase</description>
|
|
<bitOffset>0x11</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT18</name>
|
|
<description>Protects Sector 18 from program or erase</description>
|
|
<bitOffset>0x12</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT19</name>
|
|
<description>Protects Sector 19 from program or erase</description>
|
|
<bitOffset>0x13</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT20</name>
|
|
<description>Protects Sector 20 from program or erase</description>
|
|
<bitOffset>0x14</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT21</name>
|
|
<description>Protects Sector 21 from program or erase</description>
|
|
<bitOffset>0x15</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT22</name>
|
|
<description>Protects Sector 22 from program or erase</description>
|
|
<bitOffset>0x16</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT23</name>
|
|
<description>Protects Sector 23 from program or erase</description>
|
|
<bitOffset>0x17</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT24</name>
|
|
<description>Protects Sector 24 from program or erase</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT25</name>
|
|
<description>Protects Sector 25 from program or erase</description>
|
|
<bitOffset>0x19</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT26</name>
|
|
<description>Protects Sector 26 from program or erase</description>
|
|
<bitOffset>0x1A</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT27</name>
|
|
<description>Protects Sector 27 from program or erase</description>
|
|
<bitOffset>0x1B</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT28</name>
|
|
<description>Protects Sector 28 from program or erase</description>
|
|
<bitOffset>0x1C</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT29</name>
|
|
<description>Protects Sector 29 from program or erase</description>
|
|
<bitOffset>0x1D</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT30</name>
|
|
<description>Protects Sector 30 from program or erase</description>
|
|
<bitOffset>0x1E</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT31</name>
|
|
<description>Protects Sector 31 from program or erase</description>
|
|
<bitOffset>0x1F</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_BANK1_INFO_WEPROT</name>
|
|
<displayName>BANK1_INFO_WEPROT</displayName>
|
|
<description>Information Memory Bank1 Write/Erase Protection Register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000003</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PROT0</name>
|
|
<description>Protects Sector 0 from program or erase operations</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT1</name>
|
|
<description>Protects Sector 1 from program or erase operations</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_BANK1_MAIN_WEPROT</name>
|
|
<displayName>BANK1_MAIN_WEPROT</displayName>
|
|
<description>Main Memory Bank1 Write/Erase Protection Register</description>
|
|
<addressOffset>0xC4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0xffffffff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PROT0</name>
|
|
<description>Protects Sector 0 from program or erase operations</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT1</name>
|
|
<description>Protects Sector 1 from program or erase operations</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT2</name>
|
|
<description>Protects Sector 2 from program or erase operations</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT3</name>
|
|
<description>Protects Sector 3 from program or erase operations</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT4</name>
|
|
<description>Protects Sector 4 from program or erase operations</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT5</name>
|
|
<description>Protects Sector 5 from program or erase operations</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT6</name>
|
|
<description>Protects Sector 6 from program or erase operations</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT7</name>
|
|
<description>Protects Sector 7 from program or erase operations</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT8</name>
|
|
<description>Protects Sector 8 from program or erase operations</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT9</name>
|
|
<description>Protects Sector 9 from program or erase operations</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT10</name>
|
|
<description>Protects Sector 10 from program or erase operations</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT11</name>
|
|
<description>Protects Sector 11 from program or erase operations</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT12</name>
|
|
<description>Protects Sector 12 from program or erase operations</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT13</name>
|
|
<description>Protects Sector 13 from program or erase operations</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT14</name>
|
|
<description>Protects Sector 14 from program or erase operations</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT15</name>
|
|
<description>Protects Sector 15 from program or erase operations</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT16</name>
|
|
<description>Protects Sector 16 from program or erase operations</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT17</name>
|
|
<description>Protects Sector 17 from program or erase operations</description>
|
|
<bitOffset>0x11</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT18</name>
|
|
<description>Protects Sector 18 from program or erase operations</description>
|
|
<bitOffset>0x12</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT19</name>
|
|
<description>Protects Sector 19 from program or erase operations</description>
|
|
<bitOffset>0x13</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT20</name>
|
|
<description>Protects Sector 20 from program or erase operations</description>
|
|
<bitOffset>0x14</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT21</name>
|
|
<description>Protects Sector 21 from program or erase operations</description>
|
|
<bitOffset>0x15</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT22</name>
|
|
<description>Protects Sector 22 from program or erase operations</description>
|
|
<bitOffset>0x16</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT23</name>
|
|
<description>Protects Sector 23 from program or erase operations</description>
|
|
<bitOffset>0x17</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT24</name>
|
|
<description>Protects Sector 24 from program or erase operations</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT25</name>
|
|
<description>Protects Sector 25 from program or erase operations</description>
|
|
<bitOffset>0x19</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT26</name>
|
|
<description>Protects Sector 26 from program or erase operations</description>
|
|
<bitOffset>0x1A</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT27</name>
|
|
<description>Protects Sector 27 from program or erase operations</description>
|
|
<bitOffset>0x1B</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT28</name>
|
|
<description>Protects Sector 28 from program or erase operations</description>
|
|
<bitOffset>0x1C</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT29</name>
|
|
<description>Protects Sector 29 from program or erase operations</description>
|
|
<bitOffset>0x1D</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT30</name>
|
|
<description>Protects Sector 30 from program or erase operations</description>
|
|
<bitOffset>0x1E</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROT31</name>
|
|
<description>Protects Sector 31 from program or erase operations</description>
|
|
<bitOffset>0x1F</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_BMRK_CTLSTAT</name>
|
|
<displayName>BMRK_CTLSTAT</displayName>
|
|
<description>Benchmark Control and Status Register</description>
|
|
<addressOffset>0xD0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>I_BMRK</name>
|
|
<description>When 1, increments the Instruction Benchmark count register on each instruction fetch to the Flash</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>D_BMRK</name>
|
|
<description>When 1, increments the Data Benchmark count register on each data read access to the Flash</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMP_EN</name>
|
|
<description>When 1, enables comparison of the Instruction or Data Benchmark Registers against the threshold value</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMP_SEL</name>
|
|
<description>Selects which benchmark register should be compared against the threshold</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_1_0x0</name>
|
|
<description>Compares the Instruction Benchmark Register against the threshold value</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_2_0x1</name>
|
|
<description>Compares the Data Benchmark Register against the threshold value</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_BMRK_IFETCH</name>
|
|
<displayName>BMRK_IFETCH</displayName>
|
|
<description>Benchmark Instruction Fetch Count Register</description>
|
|
<addressOffset>0xD4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Reflects the number of Instruction Fetches to the Flash (increments by one on each fetch)</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_BMRK_DREAD</name>
|
|
<displayName>BMRK_DREAD</displayName>
|
|
<description>Benchmark Data Read Count Register</description>
|
|
<addressOffset>0xD8</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Reflects the number of Data Read operations to the Flash (increments by one on each read)</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_BMRK_CMP</name>
|
|
<displayName>BMRK_CMP</displayName>
|
|
<description>Benchmark Count Compare Register</description>
|
|
<addressOffset>0xDC</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00010000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Reflects the threshold value that is compared against either the IFETCH or DREAD Benchmark Counters</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_IFG</name>
|
|
<displayName>IFG</displayName>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0xF0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RDBRST</name>
|
|
<description>If set to 1, indicates that the Read Burst/Compare operation is complete</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AVPRE</name>
|
|
<description>If set to 1, indicates that the pre-program verify operation has detected an error</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AVPST</name>
|
|
<description>If set to 1, indicates that the post-program verify operation has failed comparison</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PRG</name>
|
|
<description>If set to 1, indicates that a word Program operation is complete</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PRGB</name>
|
|
<description>If set to 1, indicates that the configured Burst Program operation is complete</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ERASE</name>
|
|
<description>If set to 1, indicates that the Erase operation is complete</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BMRK</name>
|
|
<description>If set to 1, indicates that a Benchmark Compare match occurred</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PRG_ERR</name>
|
|
<description>If set to 1, indicates a word composition error in full word write mode (possible data loss due to writes crossing over to a new 128bit boundary before full word has been composed)</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_IE</name>
|
|
<displayName>IE</displayName>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0xF4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RDBRST</name>
|
|
<description>If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AVPRE</name>
|
|
<description>If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AVPST</name>
|
|
<description>If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRG</name>
|
|
<description>If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRGB</name>
|
|
<description>If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERASE</name>
|
|
<description>If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BMRK</name>
|
|
<description>If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRG_ERR</name>
|
|
<description>If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_CLRIFG</name>
|
|
<displayName>CLRIFG</displayName>
|
|
<description>Clear Interrupt Flag Register</description>
|
|
<addressOffset>0xF8</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RDBRST</name>
|
|
<description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AVPRE</name>
|
|
<description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AVPST</name>
|
|
<description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PRG</name>
|
|
<description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PRGB</name>
|
|
<description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ERASE</name>
|
|
<description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BMRK</name>
|
|
<description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PRG_ERR</name>
|
|
<description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_SETIFG</name>
|
|
<displayName>SETIFG</displayName>
|
|
<description>Set Interrupt Flag Register</description>
|
|
<addressOffset>0xFC</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RDBRST</name>
|
|
<description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AVPRE</name>
|
|
<description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AVPST</name>
|
|
<description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PRG</name>
|
|
<description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PRGB</name>
|
|
<description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ERASE</name>
|
|
<description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BMRK</name>
|
|
<description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PRG_ERR</name>
|
|
<description>Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_READ_TIMCTL</name>
|
|
<displayName>READ_TIMCTL</displayName>
|
|
<description>Read Timing Control Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>SETUP</name>
|
|
<description>Configures the length of the Setup phase for this operation</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IREF_BOOST1</name>
|
|
<description>Length of the IREF_BOOST1 signal of the IP</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SETUP_LONG</name>
|
|
<description>Length of the Setup time into read mode when the device is recovering from one of the following conditions: Moving from Power-down or Standby back to Active and device is not trimmed. Moving from standby to active state in low-frequency active mode. Recovering from the LDO Boost operation after a Mass Erase.</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_READMARGIN_TIMCTL</name>
|
|
<displayName>READMARGIN_TIMCTL</displayName>
|
|
<description>Read Margin Timing Control Register</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>SETUP</name>
|
|
<description>Length of the Setup phase for this operation</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_PRGVER_TIMCTL</name>
|
|
<displayName>PRGVER_TIMCTL</displayName>
|
|
<description>Program Verify Timing Control Register</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>SETUP</name>
|
|
<description>Length of the Setup phase for this operation</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Length of the Active phase for this operation</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HOLD</name>
|
|
<description>Length of the Hold phase for this operation</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_ERSVER_TIMCTL</name>
|
|
<displayName>ERSVER_TIMCTL</displayName>
|
|
<description>Erase Verify Timing Control Register</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>SETUP</name>
|
|
<description>Length of the Setup phase for this operation</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_LKGVER_TIMCTL</name>
|
|
<displayName>LKGVER_TIMCTL</displayName>
|
|
<description>Leakage Verify Timing Control Register</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>SETUP</name>
|
|
<description>Length of the Setup phase for this operation</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_PROGRAM_TIMCTL</name>
|
|
<displayName>PROGRAM_TIMCTL</displayName>
|
|
<description>Program Timing Control Register</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>SETUP</name>
|
|
<description>Length of the Setup phase for this operation</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Length of the Active phase for this operation</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x14</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HOLD</name>
|
|
<description>Length of the Hold phase for this operation</description>
|
|
<bitOffset>0x1C</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_ERASE_TIMCTL</name>
|
|
<displayName>ERASE_TIMCTL</displayName>
|
|
<description>Erase Timing Control Register</description>
|
|
<addressOffset>0x118</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>SETUP</name>
|
|
<description>Length of the Setup phase for this operation</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Length of the Active phase for this operation</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x14</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HOLD</name>
|
|
<description>Length of the Hold phase for this operation</description>
|
|
<bitOffset>0x1C</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_MASSERASE_TIMCTL</name>
|
|
<displayName>MASSERASE_TIMCTL</displayName>
|
|
<description>Mass Erase Timing Control Register</description>
|
|
<addressOffset>0x11C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>BOOST_ACTIVE</name>
|
|
<description>Length of the time for which LDO Boost Signal is kept active</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BOOST_HOLD</name>
|
|
<description>Length for which Flash deactivates the LDO Boost signal before processing any new commands</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCTL_BURSTPRG_TIMCTL</name>
|
|
<displayName>BURSTPRG_TIMCTL</displayName>
|
|
<description>Burst Program Timing Control Register</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Length of the Active phase for this operation</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x14</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ADC14</name>
|
|
<version>356.0</version>
|
|
<description>ADC14</description>
|
|
<baseAddress>0x40012000</baseAddress>
|
|
<interrupt>
|
|
<name>ADC14_IRQ</name>
|
|
<description>ADC14 Interrupt</description>
|
|
<value>24</value>
|
|
</interrupt>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x158</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>ADC14CTL0</name>
|
|
<displayName>CTL0</displayName>
|
|
<description>Control 0 Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADC14SC</name>
|
|
<description>ADC14 start conversion</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14SC_0</name>
|
|
<description>No sample-and-conversion-start</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14SC_1</name>
|
|
<description>Start sample-and-conversion</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14ENC</name>
|
|
<description>ADC14 enable conversion</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14ENC_0</name>
|
|
<description>ADC14 disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14ENC_1</name>
|
|
<description>ADC14 enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14ON</name>
|
|
<description>ADC14 on</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14ON_0</name>
|
|
<description>ADC14 off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14ON_1</name>
|
|
<description>ADC14 on. ADC core is ready to power up when a valid conversion is triggered.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14MSC</name>
|
|
<description>ADC14 multiple sample and conversion</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14MSC_0</name>
|
|
<description>The sampling timer requires a rising edge of the SHI signal to trigger each sample-and-convert</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14MSC_1</name>
|
|
<description>The first rising edge of the SHI signal triggers the sampling timer, but further sample-and-conversions are performed automatically as soon as the prior conversion is completed</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14SHT0</name>
|
|
<description>ADC14 sample-and-hold time</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14SHT0_0</name>
|
|
<description>4</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14SHT0_1</name>
|
|
<description>8</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14SHT0_2</name>
|
|
<description>16</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14SHT0_3</name>
|
|
<description>32</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14SHT0_4</name>
|
|
<description>64</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14SHT0_5</name>
|
|
<description>96</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14SHT0_6</name>
|
|
<description>128</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14SHT0_7</name>
|
|
<description>192</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14SHT1</name>
|
|
<description>ADC14 sample-and-hold time</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14SHT1_0</name>
|
|
<description>4</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14SHT1_1</name>
|
|
<description>8</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14SHT1_2</name>
|
|
<description>16</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14SHT1_3</name>
|
|
<description>32</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14SHT1_4</name>
|
|
<description>64</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14SHT1_5</name>
|
|
<description>96</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14SHT1_6</name>
|
|
<description>128</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14SHT1_7</name>
|
|
<description>192</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14BUSY</name>
|
|
<description>ADC14 busy</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14BUSY_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14BUSY_0</name>
|
|
<description>No operation is active</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14BUSY_1</name>
|
|
<description>A sequence, sample, or conversion is active</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14CONSEQ</name>
|
|
<description>ADC14 conversion sequence mode select</description>
|
|
<bitOffset>0x11</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14CONSEQ_0</name>
|
|
<description>Single-channel, single-conversion</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14CONSEQ_1</name>
|
|
<description>Sequence-of-channels</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14CONSEQ_2</name>
|
|
<description>Repeat-single-channel</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14CONSEQ_3</name>
|
|
<description>Repeat-sequence-of-channels</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14SSEL</name>
|
|
<description>ADC14 clock source select</description>
|
|
<bitOffset>0x13</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14SSEL_0</name>
|
|
<description>MODCLK</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14SSEL_1</name>
|
|
<description>SYSCLK</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14SSEL_2</name>
|
|
<description>ACLK</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14SSEL_3</name>
|
|
<description>MCLK</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14SSEL_4</name>
|
|
<description>SMCLK</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14SSEL_5</name>
|
|
<description>HSMCLK</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14DIV</name>
|
|
<description>ADC14 clock divider</description>
|
|
<bitOffset>0x16</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14DIV_0</name>
|
|
<description>/1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14DIV_1</name>
|
|
<description>/2</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14DIV_2</name>
|
|
<description>/3</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14DIV_3</name>
|
|
<description>/4</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14DIV_4</name>
|
|
<description>/5</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14DIV_5</name>
|
|
<description>/6</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14DIV_6</name>
|
|
<description>/7</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14DIV_7</name>
|
|
<description>/8</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14ISSH</name>
|
|
<description>ADC14 invert signal sample-and-hold</description>
|
|
<bitOffset>0x19</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14ISSH_0</name>
|
|
<description>The sample-input signal is not inverted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14ISSH_1</name>
|
|
<description>The sample-input signal is inverted</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14SHP</name>
|
|
<description>ADC14 sample-and-hold pulse-mode select</description>
|
|
<bitOffset>0x1A</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14SHP_0</name>
|
|
<description>SAMPCON signal is sourced from the sample-input signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14SHP_1</name>
|
|
<description>SAMPCON signal is sourced from the sampling timer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14SHS</name>
|
|
<description>ADC14 sample-and-hold source select</description>
|
|
<bitOffset>0x1B</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14SHS_0</name>
|
|
<description>ADC14SC bit</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14SHS_1</name>
|
|
<description>See device-specific data sheet for source</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14SHS_2</name>
|
|
<description>See device-specific data sheet for source</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14SHS_3</name>
|
|
<description>See device-specific data sheet for source</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14SHS_4</name>
|
|
<description>See device-specific data sheet for source</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14SHS_5</name>
|
|
<description>See device-specific data sheet for source</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14SHS_6</name>
|
|
<description>See device-specific data sheet for source</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14SHS_7</name>
|
|
<description>See device-specific data sheet for source</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14PDIV</name>
|
|
<description>ADC14 predivider</description>
|
|
<bitOffset>0x1E</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14PDIV_0</name>
|
|
<description>Predivide by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14PDIV_1</name>
|
|
<description>Predivide by 4</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14PDIV_2</name>
|
|
<description>Predivide by 32</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14PDIV_3</name>
|
|
<description>Predivide by 64</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADC14CTL1</name>
|
|
<displayName>CTL1</displayName>
|
|
<description>Control 1 Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADC14PWRMD</name>
|
|
<description>ADC14 power modes</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14PWRMD_0</name>
|
|
<description>Regular power mode for use with any resolution setting. Sample rate can be up to 1 Msps.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14PWRMD_2</name>
|
|
<description>Low-power mode for 12-bit, 10-bit, and 8-bit resolution settings. Sample rate must not exceed 200 ksps.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14REFBURST</name>
|
|
<description>ADC14 reference buffer burst</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14REFBURST_0</name>
|
|
<description>ADC reference buffer on continuously</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14REFBURST_1</name>
|
|
<description>ADC reference buffer on only during sample-and-conversion</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14DF</name>
|
|
<description>ADC14 data read-back format</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14DF_0</name>
|
|
<description>Binary unsigned. Theoretically, for ADC14DIF = 0 and 14-bit mode, the analog input voltage - V(REF) results in 0000h, and the analog input voltage + V(REF) results in 3FFFh</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14DF_1</name>
|
|
<description>Signed binary (2s complement), left aligned. Theoretically, for ADC14DIF = 0 and 14-bit mode, the analog input voltage - V(REF) results in 8000h, and the analog input voltage + V(REF) results in 7FFCh</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14RES</name>
|
|
<description>ADC14 resolution</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14RES_0</name>
|
|
<description>8 bit (9 clock cycle conversion time)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14RES_1</name>
|
|
<description>10 bit (11 clock cycle conversion time)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14RES_2</name>
|
|
<description>12 bit (14 clock cycle conversion time)</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14RES_3</name>
|
|
<description>14 bit (16 clock cycle conversion time)</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14CSTARTADD</name>
|
|
<description>ADC14 conversion start address</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ADC14BATMAP</name>
|
|
<description>Controls 1/2 AVCC ADC input channel selection</description>
|
|
<bitOffset>0x16</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14BATMAP_0</name>
|
|
<description>ADC internal 1/2 x AVCC channel is not selected for ADC</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14BATMAP_1</name>
|
|
<description>ADC internal 1/2 x AVCC channel is selected for ADC input channel MAX</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14TCMAP</name>
|
|
<description>Controls temperature sensor ADC input channel selection</description>
|
|
<bitOffset>0x17</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14TCMAP_0</name>
|
|
<description>ADC internal temperature sensor channel is not selected for ADC</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14TCMAP_1</name>
|
|
<description>ADC internal temperature sensor channel is selected for ADC input channel MAX-1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14CH0MAP</name>
|
|
<description>Controls internal channel 0 selection to ADC input channel MAX-2</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14CH0MAP_0</name>
|
|
<description>ADC input channel internal 0 is not selected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14CH0MAP_1</name>
|
|
<description>ADC input channel internal 0 is selected for ADC input channel MAX-2</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14CH1MAP</name>
|
|
<description>Controls internal channel 1 selection to ADC input channel MAX-3</description>
|
|
<bitOffset>0x19</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14CH1MAP_0</name>
|
|
<description>ADC input channel internal 1 is not selected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14CH1MAP_1</name>
|
|
<description>ADC input channel internal 1 is selected for ADC input channel MAX-3</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14CH2MAP</name>
|
|
<description>Controls internal channel 2 selection to ADC input channel MAX-4</description>
|
|
<bitOffset>0x1A</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14CH2MAP_0</name>
|
|
<description>ADC input channel internal 2 is not selected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14CH2MAP_1</name>
|
|
<description>ADC input channel internal 2 is selected for ADC input channel MAX-4</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14CH3MAP</name>
|
|
<description>Controls internal channel 3 selection to ADC input channel MAX-5</description>
|
|
<bitOffset>0x1B</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14CH3MAP_0</name>
|
|
<description>ADC input channel internal 3 is not selected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14CH3MAP_1</name>
|
|
<description>ADC input channel internal 3 is selected for ADC input channel MAX-5</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADC14LO0</name>
|
|
<displayName>LO0</displayName>
|
|
<description>Window Comparator Low Threshold 0 Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADC14LO0</name>
|
|
<description>Low threshold 0</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADC14HI0</name>
|
|
<displayName>HI0</displayName>
|
|
<description>Window Comparator High Threshold 0 Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00003fff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADC14HI0</name>
|
|
<description>High threshold 0</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADC14LO1</name>
|
|
<displayName>LO1</displayName>
|
|
<description>Window Comparator Low Threshold 1 Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADC14LO1</name>
|
|
<description>Low threshold 1</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADC14HI1</name>
|
|
<displayName>HI1</displayName>
|
|
<description>Window Comparator High Threshold 1 Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00003fff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADC14HI1</name>
|
|
<description>High threshold 1</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31</dimIndex>
|
|
<name>ADC14MCTL[%s]</name>
|
|
<displayName>MCTL[%s]</displayName>
|
|
<description>Conversion Memory Control Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADC14INCH</name>
|
|
<description>Input channel select</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_0</name>
|
|
<description>If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_1</name>
|
|
<description>If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_2</name>
|
|
<description>If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_3</name>
|
|
<description>If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_4</name>
|
|
<description>If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_5</name>
|
|
<description>If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_6</name>
|
|
<description>If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_7</name>
|
|
<description>If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_8</name>
|
|
<description>If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_9</name>
|
|
<description>If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_10</name>
|
|
<description>If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_11</name>
|
|
<description>If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_12</name>
|
|
<description>If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_13</name>
|
|
<description>If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_14</name>
|
|
<description>If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_15</name>
|
|
<description>If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_16</name>
|
|
<description>If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_17</name>
|
|
<description>If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17</description>
|
|
<value>17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_18</name>
|
|
<description>If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19</description>
|
|
<value>18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_19</name>
|
|
<description>If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19</description>
|
|
<value>19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_20</name>
|
|
<description>If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21</description>
|
|
<value>20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_21</name>
|
|
<description>If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21</description>
|
|
<value>21</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_22</name>
|
|
<description>If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23</description>
|
|
<value>22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_23</name>
|
|
<description>If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23</description>
|
|
<value>23</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_24</name>
|
|
<description>If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25</description>
|
|
<value>24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_25</name>
|
|
<description>If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25</description>
|
|
<value>25</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_26</name>
|
|
<description>If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27</description>
|
|
<value>26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_27</name>
|
|
<description>If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27</description>
|
|
<value>27</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_28</name>
|
|
<description>If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29</description>
|
|
<value>28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_29</name>
|
|
<description>If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29</description>
|
|
<value>29</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_30</name>
|
|
<description>If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31</description>
|
|
<value>30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INCH_31</name>
|
|
<description>If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31</description>
|
|
<value>31</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14EOS</name>
|
|
<description>End of sequence</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14EOS_0</name>
|
|
<description>Not end of sequence</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14EOS_1</name>
|
|
<description>End of sequence</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14VRSEL</name>
|
|
<description>Selects combinations of V(R+) and V(R-) sources</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14VRSEL_0</name>
|
|
<description>V(R+) = AVCC, V(R-) = AVSS</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14VRSEL_1</name>
|
|
<description>V(R+) = VREF buffered, V(R-) = AVSS</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14VRSEL_14</name>
|
|
<description>V(R+) = VeREF+, V(R-) = VeREF-</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14VRSEL_15</name>
|
|
<description>V(R+) = VeREF+ buffered, V(R-) = VeREF</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14DIF</name>
|
|
<description>Differential mode</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14DIF_0</name>
|
|
<description>Single-ended mode enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14DIF_1</name>
|
|
<description>Differential mode enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14WINC</name>
|
|
<description>Comparator window enable</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14WINC_0</name>
|
|
<description>Comparator window disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14WINC_1</name>
|
|
<description>Comparator window enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14WINCTH</name>
|
|
<description>Window comparator threshold register selection</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14WINCTH_0</name>
|
|
<description>Use window comparator thresholds 0, ADC14LO0 and ADC14HI0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14WINCTH_1</name>
|
|
<description>Use window comparator thresholds 1, ADC14LO1 and ADC14HI1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31</dimIndex>
|
|
<name>ADC14MEM[%s]</name>
|
|
<displayName>MEM[%s]</displayName>
|
|
<description>Conversion Memory Register</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Conversion_Results</name>
|
|
<description>Conversion Result</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADC14IER0</name>
|
|
<displayName>IER0</displayName>
|
|
<description>Interrupt Enable 0 Register</description>
|
|
<addressOffset>0x13C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADC14IE0</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE0_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE0_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IE1</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE1_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE1_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IE2</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE2_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE2_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IE3</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE3_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE3_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IE4</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE4_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE4_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IE5</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE5_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE5_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IE6</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE6_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE6_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IE7</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE7_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE7_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IE8</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE8_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE8_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IE9</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE9_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE9_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IE10</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE10_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE10_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IE11</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE11_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE11_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IE12</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE12_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE12_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IE13</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE13_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE13_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IE14</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE14_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE14_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IE15</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE15_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE15_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IE16</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE16_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE16_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IE17</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0x11</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE17_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE17_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IE19</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0x13</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE19_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE19_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IE18</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0x12</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE18_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE18_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IE20</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0x14</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE20_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE20_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IE21</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0x15</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE21_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE21_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IE22</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0x16</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE22_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE22_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IE23</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0x17</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE23_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE23_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IE24</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE24_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE24_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IE25</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0x19</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE25_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE25_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IE26</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0x1A</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE26_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE26_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IE27</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0x1B</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE27_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE27_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IE28</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0x1C</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE28_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE28_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IE29</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0x1D</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE29_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE29_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IE30</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0x1E</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE30_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE30_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IE31</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>0x1F</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IE31_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IE31_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADC14IER1</name>
|
|
<displayName>IER1</displayName>
|
|
<description>Interrupt Enable 1 Register</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADC14INIE</name>
|
|
<description>Interrupt enable for ADC14MEMx within comparator window</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14INIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14LOIE</name>
|
|
<description>Interrupt enable for ADC14MEMx below comparator window</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14LOIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14LOIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14HIIE</name>
|
|
<description>Interrupt enable for ADC14MEMx above comparator window</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14HIIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14HIIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14OVIE</name>
|
|
<description>ADC14MEMx overflow-interrupt enable</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14OVIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14OVIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14TOVIE</name>
|
|
<description>ADC14 conversion-time-overflow interrupt enable</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14TOVIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14TOVIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14RDYIE</name>
|
|
<description>ADC14 local buffered reference ready interrupt enable</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14RDYIE_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14RDYIE_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADC14IFGR0</name>
|
|
<displayName>IFGR0</displayName>
|
|
<description>Interrupt Flag 0 Register</description>
|
|
<addressOffset>0x144</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADC14IFG0</name>
|
|
<description>ADC14MEM0 interrupt flag</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG0_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG0_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG0_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IFG1</name>
|
|
<description>ADC14MEM1 interrupt flag</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG1_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG1_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG1_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IFG2</name>
|
|
<description>ADC14MEM2 interrupt flag</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG2_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG2_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG2_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IFG3</name>
|
|
<description>ADC14MEM3 interrupt flag</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG3_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG3_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG3_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IFG4</name>
|
|
<description>ADC14MEM4 interrupt flag</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG4_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG4_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG4_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IFG5</name>
|
|
<description>ADC14MEM5 interrupt flag</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG5_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG5_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG5_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IFG6</name>
|
|
<description>ADC14MEM6 interrupt flag</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG6_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG6_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG6_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IFG7</name>
|
|
<description>ADC14MEM7 interrupt flag</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG7_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG7_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG7_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IFG8</name>
|
|
<description>ADC14MEM8 interrupt flag</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG8_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG8_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG8_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IFG9</name>
|
|
<description>ADC14MEM9 interrupt flag</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG9_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG9_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG9_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IFG10</name>
|
|
<description>ADC14MEM10 interrupt flag</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG10_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG10_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG10_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IFG11</name>
|
|
<description>ADC14MEM11 interrupt flag</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG11_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG11_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG11_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IFG12</name>
|
|
<description>ADC14MEM12 interrupt flag</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG12_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG12_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG12_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IFG13</name>
|
|
<description>ADC14MEM13 interrupt flag</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG13_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG13_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG13_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IFG14</name>
|
|
<description>ADC14MEM14 interrupt flag</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG14_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG14_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG14_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IFG15</name>
|
|
<description>ADC14MEM15 interrupt flag</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG15_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG15_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG15_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IFG16</name>
|
|
<description>ADC14MEM16 interrupt flag</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG16_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG16_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG16_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IFG17</name>
|
|
<description>ADC14MEM17 interrupt flag</description>
|
|
<bitOffset>0x11</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG17_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG17_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG17_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IFG18</name>
|
|
<description>ADC14MEM18 interrupt flag</description>
|
|
<bitOffset>0x12</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG18_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG18_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG18_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IFG19</name>
|
|
<description>ADC14MEM19 interrupt flag</description>
|
|
<bitOffset>0x13</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG19_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG19_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG19_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IFG20</name>
|
|
<description>ADC14MEM20 interrupt flag</description>
|
|
<bitOffset>0x14</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG20_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG20_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG20_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IFG21</name>
|
|
<description>ADC14MEM21 interrupt flag</description>
|
|
<bitOffset>0x15</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG21_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG21_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG21_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IFG22</name>
|
|
<description>ADC14MEM22 interrupt flag</description>
|
|
<bitOffset>0x16</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG22_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG22_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG22_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IFG23</name>
|
|
<description>ADC14MEM23 interrupt flag</description>
|
|
<bitOffset>0x17</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG23_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG23_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG23_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IFG24</name>
|
|
<description>ADC14MEM24 interrupt flag</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG24_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG24_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG24_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IFG25</name>
|
|
<description>ADC14MEM25 interrupt flag</description>
|
|
<bitOffset>0x19</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG25_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG25_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG25_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IFG26</name>
|
|
<description>ADC14MEM26 interrupt flag</description>
|
|
<bitOffset>0x1A</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG26_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG26_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG26_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IFG27</name>
|
|
<description>ADC14MEM27 interrupt flag</description>
|
|
<bitOffset>0x1B</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG27_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG27_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG27_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IFG28</name>
|
|
<description>ADC14MEM28 interrupt flag</description>
|
|
<bitOffset>0x1C</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG28_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG28_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG28_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IFG29</name>
|
|
<description>ADC14MEM29 interrupt flag</description>
|
|
<bitOffset>0x1D</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG29_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG29_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG29_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IFG30</name>
|
|
<description>ADC14MEM30 interrupt flag</description>
|
|
<bitOffset>0x1E</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG30_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG30_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG30_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14IFG31</name>
|
|
<description>ADC14MEM31 interrupt flag</description>
|
|
<bitOffset>0x1F</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14IFG31_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG31_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IFG31_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADC14IFGR1</name>
|
|
<displayName>IFGR1</displayName>
|
|
<description>Interrupt Flag 1 Register</description>
|
|
<addressOffset>0x148</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADC14INIFG</name>
|
|
<description>Interrupt flag for ADC14MEMx within comparator window</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14INIFG_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14INIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14INIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14LOIFG</name>
|
|
<description>Interrupt flag for ADC14MEMx below comparator window</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14LOIFG_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14LOIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14LOIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14HIIFG</name>
|
|
<description>Interrupt flag for ADC14MEMx above comparator window</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14HIIFG_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14HIIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14HIIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14OVIFG</name>
|
|
<description>ADC14MEMx overflow interrupt flag</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14OVIFG_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14OVIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14OVIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14TOVIFG</name>
|
|
<description>ADC14 conversion time overflow interrupt flag</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14TOVIFG_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14TOVIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14TOVIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC14RDYIFG</name>
|
|
<description>ADC14 local buffered reference ready interrupt flag</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>ADC14RDYIFG_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>ADC14RDYIFG_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14RDYIFG_1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADC14CLRIFGR0</name>
|
|
<displayName>CLRIFGR0</displayName>
|
|
<description>Clear Interrupt Flag 0 Register</description>
|
|
<addressOffset>0x14C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLRADC14IFG0</name>
|
|
<description>clear ADC14IFG0</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG0_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG0_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG0_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14IFG1</name>
|
|
<description>clear ADC14IFG1</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG1_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG1_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG1_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14IFG2</name>
|
|
<description>clear ADC14IFG2</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG2_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG2_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG2_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14IFG3</name>
|
|
<description>clear ADC14IFG3</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG3_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG3_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG3_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14IFG4</name>
|
|
<description>clear ADC14IFG4</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG4_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG4_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG4_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14IFG5</name>
|
|
<description>clear ADC14IFG5</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG5_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG5_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG5_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14IFG6</name>
|
|
<description>clear ADC14IFG6</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG6_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG6_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG6_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14IFG7</name>
|
|
<description>clear ADC14IFG7</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG7_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG7_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG7_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14IFG8</name>
|
|
<description>clear ADC14IFG8</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG8_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG8_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG8_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14IFG9</name>
|
|
<description>clear ADC14IFG9</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG9_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG9_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG9_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14IFG10</name>
|
|
<description>clear ADC14IFG10</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG10_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG10_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG10_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14IFG11</name>
|
|
<description>clear ADC14IFG11</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG11_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG11_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG11_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14IFG12</name>
|
|
<description>clear ADC14IFG12</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG12_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG12_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG12_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14IFG13</name>
|
|
<description>clear ADC14IFG13</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG13_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG13_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG13_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14IFG14</name>
|
|
<description>clear ADC14IFG14</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG14_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG14_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG14_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14IFG15</name>
|
|
<description>clear ADC14IFG15</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG15_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG15_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG15_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14IFG16</name>
|
|
<description>clear ADC14IFG16</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG16_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG16_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG16_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14IFG17</name>
|
|
<description>clear ADC14IFG17</description>
|
|
<bitOffset>0x11</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG17_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG17_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG17_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14IFG18</name>
|
|
<description>clear ADC14IFG18</description>
|
|
<bitOffset>0x12</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG18_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG18_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG18_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14IFG19</name>
|
|
<description>clear ADC14IFG19</description>
|
|
<bitOffset>0x13</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG19_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG19_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG19_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14IFG20</name>
|
|
<description>clear ADC14IFG20</description>
|
|
<bitOffset>0x14</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG20_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG20_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG20_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14IFG21</name>
|
|
<description>clear ADC14IFG21</description>
|
|
<bitOffset>0x15</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG21_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG21_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG21_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14IFG22</name>
|
|
<description>clear ADC14IFG22</description>
|
|
<bitOffset>0x16</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG22_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG22_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG22_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14IFG23</name>
|
|
<description>clear ADC14IFG23</description>
|
|
<bitOffset>0x17</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG23_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG23_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG23_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14IFG24</name>
|
|
<description>clear ADC14IFG24</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG24_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG24_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG24_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14IFG25</name>
|
|
<description>clear ADC14IFG25</description>
|
|
<bitOffset>0x19</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG25_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG25_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG25_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14IFG26</name>
|
|
<description>clear ADC14IFG26</description>
|
|
<bitOffset>0x1A</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG26_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG26_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG26_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14IFG27</name>
|
|
<description>clear ADC14IFG27</description>
|
|
<bitOffset>0x1B</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG27_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG27_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG27_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14IFG28</name>
|
|
<description>clear ADC14IFG28</description>
|
|
<bitOffset>0x1C</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG28_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG28_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG28_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14IFG29</name>
|
|
<description>clear ADC14IFG29</description>
|
|
<bitOffset>0x1D</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG29_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG29_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG29_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14IFG30</name>
|
|
<description>clear ADC14IFG30</description>
|
|
<bitOffset>0x1E</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG30_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG30_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG30_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14IFG31</name>
|
|
<description>clear ADC14IFG31</description>
|
|
<bitOffset>0x1F</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14IFG31_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG31_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14IFG31_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADC14CLRIFGR1</name>
|
|
<displayName>CLRIFGR1</displayName>
|
|
<description>Clear Interrupt Flag 1 Register</description>
|
|
<addressOffset>0x150</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLRADC14INIFG</name>
|
|
<description>clear ADC14INIFG</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14INIFG_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14INIFG_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14INIFG_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14LOIFG</name>
|
|
<description>clear ADC14LOIFG</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14LOIFG_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14LOIFG_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14LOIFG_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14HIIFG</name>
|
|
<description>clear ADC14HIIFG</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14HIIFG_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14HIIFG_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14HIIFG_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14OVIFG</name>
|
|
<description>clear ADC14OVIFG</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14OVIFG_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14OVIFG_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14OVIFG_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14TOVIFG</name>
|
|
<description>clear ADC14TOVIFG</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14TOVIFG_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14TOVIFG_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14TOVIFG_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRADC14RDYIFG</name>
|
|
<description>clear ADC14RDYIFG</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<name>CLRADC14RDYIFG_enum_write</name>
|
|
<usage>write</usage>
|
|
<enumeratedValue>
|
|
<name>CLRADC14RDYIFG_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRADC14RDYIFG_1</name>
|
|
<description>clear pending interrupt flag</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADC14IV</name>
|
|
<displayName>IV</displayName>
|
|
<description>Interrupt Vector Register</description>
|
|
<addressOffset>0x154</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADC14IV</name>
|
|
<description>ADC14 interrupt vector value</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_2</name>
|
|
<description>Interrupt Source: ADC14MEMx overflow; Interrupt Flag: ADC14OVIFG; Interrupt Priority: Highest</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_4</name>
|
|
<description>Interrupt Source: Conversion time overflow; Interrupt Flag: ADC14TOVIFG</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_6</name>
|
|
<description>Interrupt Source: ADC14 window high interrupt flag; Interrupt Flag: ADC14HIIFG</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_8</name>
|
|
<description>Interrupt Source: ADC14 window low interrupt flag; Interrupt Flag: ADC14LOIFG</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_10</name>
|
|
<description>Interrupt Source: ADC14 in-window interrupt flag; Interrupt Flag: ADC14INIFG</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_12</name>
|
|
<description>Interrupt Source: ADC14MEM0 interrupt flag; Interrupt Flag: ADC14IFG0</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_14</name>
|
|
<description>Interrupt Source: ADC14MEM1 interrupt flag; Interrupt Flag: ADC14IFG1</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_16</name>
|
|
<description>Interrupt Source: ADC14MEM2 interrupt flag; Interrupt Flag: ADC14IFG2</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_18</name>
|
|
<description>Interrupt Source: ADC14MEM3 interrupt flag; Interrupt Flag: ADC14IFG3</description>
|
|
<value>18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_20</name>
|
|
<description>Interrupt Source: ADC14MEM4 interrupt flag; Interrupt Flag: ADC14IFG4</description>
|
|
<value>20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_22</name>
|
|
<description>Interrupt Source: ADC14MEM5 interrupt flag; Interrupt Flag: ADC14IFG5</description>
|
|
<value>22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_24</name>
|
|
<description>Interrupt Source: ADC14MEM6 interrupt flag; Interrupt Flag: ADC14IFG6</description>
|
|
<value>24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_26</name>
|
|
<description>Interrupt Source: ADC14MEM7 interrupt flag; Interrupt Flag: ADC14IFG7</description>
|
|
<value>26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_28</name>
|
|
<description>Interrupt Source: ADC14MEM8 interrupt flag; Interrupt Flag: ADC14IFG8</description>
|
|
<value>28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_30</name>
|
|
<description>Interrupt Source: ADC14MEM9 interrupt flag; Interrupt Flag: ADC14IFG9</description>
|
|
<value>30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_32</name>
|
|
<description>Interrupt Source: ADC14MEM10 interrupt flag; Interrupt Flag: ADC14IFG10</description>
|
|
<value>32</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_34</name>
|
|
<description>Interrupt Source: ADC14MEM11 interrupt flag; Interrupt Flag: ADC14IFG11</description>
|
|
<value>34</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_36</name>
|
|
<description>Interrupt Source: ADC14MEM12 interrupt flag; Interrupt Flag: ADC14IFG12</description>
|
|
<value>36</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_38</name>
|
|
<description>Interrupt Source: ADC14MEM13 interrupt flag; Interrupt Flag: ADC14IFG13</description>
|
|
<value>38</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_40</name>
|
|
<description>Interrupt Source: ADC14MEM14 interrupt flag; Interrupt Flag: ADC14IFG14</description>
|
|
<value>40</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_42</name>
|
|
<description>Interrupt Source: ADC14MEM15 interrupt flag; Interrupt Flag: ADC14IFG15</description>
|
|
<value>42</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_44</name>
|
|
<description>Interrupt Source: ADC14MEM16 interrupt flag; Interrupt Flag: ADC14IFG16</description>
|
|
<value>44</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_46</name>
|
|
<description>Interrupt Source: ADC14MEM17 interrupt flag; Interrupt Flag: ADC14IFG17</description>
|
|
<value>46</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_48</name>
|
|
<description>Interrupt Source: ADC14MEM18 interrupt flag; Interrupt Flag: ADC14IFG18</description>
|
|
<value>48</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_50</name>
|
|
<description>Interrupt Source: ADC14MEM19 interrupt flag; Interrupt Flag: ADC14IFG19</description>
|
|
<value>50</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_52</name>
|
|
<description>Interrupt Source: ADC14MEM20 interrupt flag; Interrupt Flag: ADC14IFG20</description>
|
|
<value>52</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_54</name>
|
|
<description>Interrupt Source: ADC14MEM22 interrupt flag; Interrupt Flag: ADC14IFG22</description>
|
|
<value>54</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_56</name>
|
|
<description>Interrupt Source: ADC14MEM22 interrupt flag; Interrupt Flag: ADC14IFG22</description>
|
|
<value>56</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_58</name>
|
|
<description>Interrupt Source: ADC14MEM23 interrupt flag; Interrupt Flag: ADC14IFG23</description>
|
|
<value>58</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_60</name>
|
|
<description>Interrupt Source: ADC14MEM24 interrupt flag; Interrupt Flag: ADC14IFG24</description>
|
|
<value>60</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_62</name>
|
|
<description>Interrupt Source: ADC14MEM25 interrupt flag; Interrupt Flag: ADC14IFG25</description>
|
|
<value>62</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_64</name>
|
|
<description>Interrupt Source: ADC14MEM26 interrupt flag; Interrupt Flag: ADC14IFG26</description>
|
|
<value>64</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_66</name>
|
|
<description>Interrupt Source: ADC14MEM27 interrupt flag; Interrupt Flag: ADC14IFG27</description>
|
|
<value>66</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_68</name>
|
|
<description>Interrupt Source: ADC14MEM28 interrupt flag; Interrupt Flag: ADC14IFG28</description>
|
|
<value>68</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_70</name>
|
|
<description>Interrupt Source: ADC14MEM29 interrupt flag; Interrupt Flag: ADC14IFG29</description>
|
|
<value>70</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_72</name>
|
|
<description>Interrupt Source: ADC14MEM30 interrupt flag; Interrupt Flag: ADC14IFG30</description>
|
|
<value>72</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_74</name>
|
|
<description>Interrupt Source: ADC14MEM31 interrupt flag; Interrupt Flag: ADC14IFG31</description>
|
|
<value>74</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC14IV_76</name>
|
|
<description>Interrupt Source: ADC14RDYIFG interrupt flag; Interrupt Flag: ADC14RDYIFG; Interrupt Priority: Lowest</description>
|
|
<value>76</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ITM</name>
|
|
<version>356.0</version>
|
|
<description>ITM</description>
|
|
<baseAddress>0xE0000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>ITM_STIM0</name>
|
|
<displayName>STIM0</displayName>
|
|
<description>ITM Stimulus Port 0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_STIM1</name>
|
|
<displayName>STIM1</displayName>
|
|
<description>ITM Stimulus Port 1</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_STIM2</name>
|
|
<displayName>STIM2</displayName>
|
|
<description>ITM Stimulus Port 2</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_STIM3</name>
|
|
<displayName>STIM3</displayName>
|
|
<description>ITM Stimulus Port 3</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_STIM4</name>
|
|
<displayName>STIM4</displayName>
|
|
<description>ITM Stimulus Port 4</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_STIM5</name>
|
|
<displayName>STIM5</displayName>
|
|
<description>ITM Stimulus Port 5</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_STIM6</name>
|
|
<displayName>STIM6</displayName>
|
|
<description>ITM Stimulus Port 6</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_STIM7</name>
|
|
<displayName>STIM7</displayName>
|
|
<description>ITM Stimulus Port 7</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_STIM8</name>
|
|
<displayName>STIM8</displayName>
|
|
<description>ITM Stimulus Port 8</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_STIM9</name>
|
|
<displayName>STIM9</displayName>
|
|
<description>ITM Stimulus Port 9</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_STIM10</name>
|
|
<displayName>STIM10</displayName>
|
|
<description>ITM Stimulus Port 10</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_STIM11</name>
|
|
<displayName>STIM11</displayName>
|
|
<description>ITM Stimulus Port 11</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_STIM12</name>
|
|
<displayName>STIM12</displayName>
|
|
<description>ITM Stimulus Port 12</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_STIM13</name>
|
|
<displayName>STIM13</displayName>
|
|
<description>ITM Stimulus Port 13</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_STIM14</name>
|
|
<displayName>STIM14</displayName>
|
|
<description>ITM Stimulus Port 14</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_STIM15</name>
|
|
<displayName>STIM15</displayName>
|
|
<description>ITM Stimulus Port 15</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_STIM16</name>
|
|
<displayName>STIM16</displayName>
|
|
<description>ITM Stimulus Port 16</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_STIM17</name>
|
|
<displayName>STIM17</displayName>
|
|
<description>ITM Stimulus Port 17</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_STIM18</name>
|
|
<displayName>STIM18</displayName>
|
|
<description>ITM Stimulus Port 18</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_STIM19</name>
|
|
<displayName>STIM19</displayName>
|
|
<description>ITM Stimulus Port 19</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_STIM20</name>
|
|
<displayName>STIM20</displayName>
|
|
<description>ITM Stimulus Port 20</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_STIM21</name>
|
|
<displayName>STIM21</displayName>
|
|
<description>ITM Stimulus Port 21</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_STIM22</name>
|
|
<displayName>STIM22</displayName>
|
|
<description>ITM Stimulus Port 22</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_STIM23</name>
|
|
<displayName>STIM23</displayName>
|
|
<description>ITM Stimulus Port 23</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_STIM24</name>
|
|
<displayName>STIM24</displayName>
|
|
<description>ITM Stimulus Port 24</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_STIM25</name>
|
|
<displayName>STIM25</displayName>
|
|
<description>ITM Stimulus Port 25</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_STIM26</name>
|
|
<displayName>STIM26</displayName>
|
|
<description>ITM Stimulus Port 26</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_STIM27</name>
|
|
<displayName>STIM27</displayName>
|
|
<description>ITM Stimulus Port 27</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_STIM28</name>
|
|
<displayName>STIM28</displayName>
|
|
<description>ITM Stimulus Port 28</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_STIM29</name>
|
|
<displayName>STIM29</displayName>
|
|
<description>ITM Stimulus Port 29</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_STIM30</name>
|
|
<displayName>STIM30</displayName>
|
|
<description>ITM Stimulus Port 30</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_STIM31</name>
|
|
<displayName>STIM31</displayName>
|
|
<description>ITM Stimulus Port 31</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>ITM_TER</name>
|
|
<displayName>TER</displayName>
|
|
<description>ITM Trace Enable Register</description>
|
|
<addressOffset>0xE00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STIMENA</name>
|
|
<description>Bit mask to enable tracing on ITM stimulus ports. One bit per stimulus port.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ITM_TPR</name>
|
|
<displayName>TPR</displayName>
|
|
<description>ITM Trace Privilege Register</description>
|
|
<addressOffset>0xE40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRIVMASK</name>
|
|
<description>Bit mask to enable tracing on ITM stimulus ports: bit [0] = stimulus ports [7:0], bit [1] = stimulus ports [15:8], bit [2] = stimulus ports [23:16], bit [3] = stimulus ports [31:24].</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ITM_TCR</name>
|
|
<displayName>TCR</displayName>
|
|
<description>ITM Trace Control Register</description>
|
|
<addressOffset>0xE80</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ITMENA</name>
|
|
<description>Enable ITM. This is the master enable, and must be set before ITM Stimulus and Trace Enable registers can be written.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TSENA</name>
|
|
<description>Enables differential timestamps. Differential timestamps are emitted when a packet is written to the FIFO with a non-zero timestamp counter, and when the timestamp counter overflows. Timestamps are emitted during idle times after a fixed number of two million cycles. This provides a time reference for packets and inter-packet gaps. If SWOENA (bit [4]) is set, timestamps are triggered by activity on the internal trace bus only. In this case there is no regular timestamp output when the ITM is idle.</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SYNCENA</name>
|
|
<description>Enables sync packets for TPIU.</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DWTENA</name>
|
|
<description>Enables the DWT stimulus.</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SWOENA</name>
|
|
<description>Enables asynchronous clocking of the timestamp counter.</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TSPRESCALE</name>
|
|
<description>TSPrescale Timestamp prescaler.</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b00</name>
|
|
<description>no prescaling</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b01</name>
|
|
<description>divide by 4</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b10</name>
|
|
<description>divide by 16</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b11</name>
|
|
<description>divide by 64</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ATBID</name>
|
|
<description>ATB ID for CoreSight system.</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>Set when ITM events present and being drained.</description>
|
|
<bitOffset>0x17</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ITM_IWR</name>
|
|
<displayName>IWR</displayName>
|
|
<description>ITM Integration Write Register</description>
|
|
<addressOffset>0xEF8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ATVALIDM</name>
|
|
<description>When the integration mode is set: 0 = ATVALIDM clear. 1 = ATVALIDM set.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>ATVALIDM clear</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>ATVALIDM set</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ITM_IMCR</name>
|
|
<displayName>IMCR</displayName>
|
|
<description>ITM Integration Mode Control Register</description>
|
|
<addressOffset>0xF00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>INTEGRATION</name>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>ATVALIDM normal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>ATVALIDM driven from Integration Write Register</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ITM_LAR</name>
|
|
<displayName>LAR</displayName>
|
|
<description>ITM Lock Access Register</description>
|
|
<addressOffset>0xFB0</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LOCK_ACCESS</name>
|
|
<description>A privileged write of 0xC5ACCE55 enables more write access to Control Register 0xE00::0xFFC. An invalid write removes write access.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ITM_LSR</name>
|
|
<displayName>LSR</displayName>
|
|
<description>ITM Lock Status Register</description>
|
|
<addressOffset>0xFB4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRESENT</name>
|
|
<description>Indicates that a lock mechanism exists for this component.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ACCESS</name>
|
|
<description>Write access to component is blocked. All writes are ignored, reads are permitted.</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BYTEACC</name>
|
|
<description>You cannot implement 8-bit lock accesses.</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DWT</name>
|
|
<version>356.0</version>
|
|
<description>DWT</description>
|
|
<baseAddress>0xE0001000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DWT_CTRL</name>
|
|
<displayName>CTRL</displayName>
|
|
<description>DWT Control Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x40000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CYCCNTENA</name>
|
|
<description>Enable the CYCCNT counter. If not enabled, the counter does not count and no event is generated for PS sampling or CYCCNTENA. In normal use, the debugger must initialize the CYCCNT counter to 0.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>POSTPRESET</name>
|
|
<description>Reload value for POSTCNT, bits [8:5], post-scalar counter. If this value is 0, events are triggered on each tap change (a power of 2). If this field has a non-0 value, this forms a count-down value, to be reloaded into POSTCNT each time it reaches 0. For example, a value 1 in this register means an event is formed every other tap change.</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>POSTCNT</name>
|
|
<description>Post-scalar counter for CYCTAP. When the selected tapped bit changes from 0 to 1 or 1 to 0, the post scalar counter is down-counted when not 0. If 0, it triggers an event for PCSAMPLENA or CYCEVTENA use. It also reloads with the value from POSTPRESET (bits [4:1]).</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CYCTAP</name>
|
|
<description>Selects a tap on the DWT_CYCCNT register. These are spaced at bits [6] and [10]. When the selected bit in the CYCCNT register changes from 0 to 1 or 1 to 0, it emits into the POSTCNT, bits [8:5], post-scalar counter. That counter then counts down. On a bit change when post-scalar is 0, it triggers an event for PC sampling or CYCEVTCNT.</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>selects bit [6] to tap</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>selects bit [10] to tap.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCTAP</name>
|
|
<description>Feeds a synchronization pulse to the ITM SYNCENA control. The value selected here picks the rate (approximately 1/second or less) by selecting a tap on the DWT_CYCCNT register. To use synchronization (heartbeat and hot-connect synchronization), CYCCNTENA must be set to 1, SYNCTAP must be set to one of its values, and SYNCENA must be set to 1.</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b00</name>
|
|
<description>Disabled. No synch counting.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b01</name>
|
|
<description>Tap at CYCCNT bit 24.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b10</name>
|
|
<description>Tap at CYCCNT bit 26.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b11</name>
|
|
<description>Tap at CYCCNT bit 28.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCSAMPLEENA</name>
|
|
<description>Enables PC Sampling event. A PC sample event is emitted when the POSTCNT counter triggers it. See CYCTAP, bit [9], and POSTPRESET, bits [4:1], for details. Enabling this bit overrides CYCEVTENA (bit [20]). Reset clears the PCSAMPLENA bit.</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>PC Sampling event disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>Sampling event enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXCTRCENA</name>
|
|
<description>Enables Interrupt event tracing. Reset clears the EXCEVTENA bit.</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>interrupt event trace disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>interrupt event trace enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPIEVTENA</name>
|
|
<description>Enables CPI count event. Emits an event when DWT_CPICNT overflows (every 256 cycles of multi-cycle instructions). Reset clears the CPIEVTENA bit.</description>
|
|
<bitOffset>0x11</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>CPI counter events disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>CPI counter events enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXCEVTENA</name>
|
|
<description>Enables Interrupt overhead event. Emits an event when DWT_EXCCNT overflows (every 256 cycles of interrupt overhead). Reset clears the EXCEVTENA bit.</description>
|
|
<bitOffset>0x12</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>Interrupt overhead event disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>Interrupt overhead event enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLEEPEVTENA</name>
|
|
<description>Enables Sleep count event. Emits an event when DWT_SLEEPCNT overflows (every 256 cycles that the processor is sleeping). Reset clears the SLEEPEVTENA bit.</description>
|
|
<bitOffset>0x13</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>Sleep count events disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>Sleep count events enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LSUEVTENA</name>
|
|
<description>Enables LSU count event. Emits an event when DWT_LSUCNT overflows (every 256 cycles of LSU operation). LSU counts include all LSU costs after the initial cycle for the instruction. Reset clears the LSUEVTENA bit.</description>
|
|
<bitOffset>0x14</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>LSU count events disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>LSU count events enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FOLDEVTENA</name>
|
|
<description>Enables Folded instruction count event. Emits an event when DWT_FOLDCNT overflows (every 256 cycles of folded instructions). A folded instruction is one that does not incur even one cycle to execute. For example, an IT instruction is folded away and so does not use up one cycle. Reset clears the FOLDEVTENA bit.</description>
|
|
<bitOffset>0x15</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>Folded instruction count events disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>Folded instruction count events enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CYCEVTENA</name>
|
|
<description>Enables Cycle count event. Emits an event when the POSTCNT counter triggers it. See CYCTAP (bit [9]) and POSTPRESET, bits [4:1], for details. This event is only emitted if PCSAMPLENA, bit [12], is disabled. PCSAMPLENA overrides the setting of this bit. Reset clears the CYCEVTENA bit.</description>
|
|
<bitOffset>0x16</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>Cycle count events disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>Cycle count events enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOPRFCNT</name>
|
|
<description>When set, DWT_FOLDCNT, DWT_LSUCNT, DWT_SLEEPCNT, DWT_EXCCNT, and DWT_CPICNT are not supported.</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NOCYCCNT</name>
|
|
<description>When set, DWT_CYCCNT is not supported.</description>
|
|
<bitOffset>0x19</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_CYCCNT</name>
|
|
<displayName>CYCCNT</displayName>
|
|
<description>DWT Current PC Sampler Cycle Count Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CYCCNT</name>
|
|
<description>Current PC Sampler Cycle Counter count value. When enabled, this counter counts the number of core cycles, except when the core is halted. CYCCNT is a free running counter, counting upwards. It wraps around to 0 on overflow. The debugger must initialize this to 0 when first enabling.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_CPICNT</name>
|
|
<displayName>CPICNT</displayName>
|
|
<description>DWT CPI Count Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>CPICNT</name>
|
|
<description>Current CPI counter value. Increments on the additional cycles (the first cycle is not counted) required to execute all instructions except those recorded by DWT_LSUCNT. This counter also increments on all instruction fetch stalls. If CPIEVTENA is set, an event is emitted when the counter overflows. Clears to 0 on enabling.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_EXCCNT</name>
|
|
<displayName>EXCCNT</displayName>
|
|
<description>DWT Exception Overhead Count Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>EXCCNT</name>
|
|
<description>Current interrupt overhead counter value. Counts the total cycles spent in interrupt processing (for example entry stacking, return unstacking, pre-emption). An event is emitted on counter overflow (every 256 cycles). This counter initializes to 0 when enabled. Clears to 0 on enabling.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_SLEEPCNT</name>
|
|
<displayName>SLEEPCNT</displayName>
|
|
<description>DWT Sleep Count Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>SLEEPCNT</name>
|
|
<description>Sleep counter. Counts the number of cycles during which the processor is sleeping. An event is emitted on counter overflow (every 256 cycles). This counter initializes to 0 when enabled. Note that SLEEPCNT is clocked using FCLK. It is possible that the frequency of FCLK might be reduced while the processor is sleeping to minimize power consumption. This means that sleep duration must be calculated with the frequency of FCLK during sleep.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_LSUCNT</name>
|
|
<displayName>LSUCNT</displayName>
|
|
<description>DWT LSU Count Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>LSUCNT</name>
|
|
<description>LSU counter. This counts the total number of cycles that the processor is processing an LSU operation. The initial execution cost of the instruction is not counted. For example, an LDR that takes two cycles to complete increments this counter one cycle. Equivalently, an LDR that stalls for two cycles (and so takes four cycles), increments this counter three times. An event is emitted on counter overflow (every 256 cycles). Clears to 0 on enabling.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_FOLDCNT</name>
|
|
<displayName>FOLDCNT</displayName>
|
|
<description>DWT Fold Count Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>FOLDCNT</name>
|
|
<description>This counts the total number folded instructions. This counter initializes to 0 when enabled.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_PCSR</name>
|
|
<displayName>PCSR</displayName>
|
|
<description>DWT Program Counter Sample Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>EIASAMPLE</name>
|
|
<description>Execution instruction address sample, or 0xFFFFFFFF if the core is halted.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_COMP0</name>
|
|
<displayName>COMP0</displayName>
|
|
<description>DWT Comparator Register 0</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Data value to compare against PC and the data address as given by DWT_FUNCTION0. DWT_COMP0 can also compare against the value of the PC Sampler Counter (DWT_CYCCNT).</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_MASK0</name>
|
|
<displayName>MASK0</displayName>
|
|
<description>DWT Mask Register 0</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Mask on data address when matching against COMP. This is the size of the ignore mask. hat is, DWT matching is performed as:(ADDR ANDed with (~0 left bit-shifted by MASK)) == COMP. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP is 3, this matches a word access of 0, because 3 would be within the word.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_FUNCTION0</name>
|
|
<displayName>FUNCTION0</displayName>
|
|
<description>DWT Function Register 0</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FUNCTION</name>
|
|
<description>Function settings. Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0010</name>
|
|
<description>EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0011</name>
|
|
<description>EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0100</name>
|
|
<description>Watchpoint on PC match.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0101</name>
|
|
<description>Watchpoint on read.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0110</name>
|
|
<description>Watchpoint on write.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0111</name>
|
|
<description>Watchpoint on read or write.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1000</name>
|
|
<description>ETM trigger on PC match</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1001</name>
|
|
<description>ETM trigger on read</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1010</name>
|
|
<description>ETM trigger on write</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1011</name>
|
|
<description>ETM trigger on read or write</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1100</name>
|
|
<description>EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1101</name>
|
|
<description>EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1110</name>
|
|
<description>EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1111</name>
|
|
<description>EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMITRANGE</name>
|
|
<description>Emit range field. Reserved to permit emitting offset when range match occurs. Reset clears the EMITRANGE bit. PC sampling is not supported when EMITRANGE is enabled. EMITRANGE only applies for: FUNCTION = b0001, b0010, b0011, b1100, b1101, b1110, and b1111.</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATAVMATCH</name>
|
|
<description>This bit is only available in comparator 1. When DATAVMATCH is set, this comparator performs data value compares. The comparators given by DATAVADDR0 and DATAVADDR1provide the address for the data comparison. If DATAVMATCH is set in DWT_FUNCTION1, the FUNCTION setting for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and those comparators only provide the address match for the data comparison.</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LNK1ENA</name>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>DATAVADDR1 not supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>DATAVADDR1 supported (enabled).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATAVSIZE</name>
|
|
<description>Defines the size of the data in the COMP register that is to be matched:</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b00</name>
|
|
<description>byte</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b01</name>
|
|
<description>halfword</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b10</name>
|
|
<description>word</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b11</name>
|
|
<description>Unpredictable.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATAVADDR0</name>
|
|
<description>Identity of a linked address comparator for data value matching when DATAVMATCH == 1.</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATAVADDR1</name>
|
|
<description>Identity of a second linked address comparator for data value matching when DATAVMATCH == 1 and LNK1ENA == 1.</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MATCHED</name>
|
|
<description>This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read.</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_COMP1</name>
|
|
<displayName>COMP1</displayName>
|
|
<description>DWT Comparator Register 1</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Data value to compare against PC and the data address as given by DWT_FUNCTION1.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_MASK1</name>
|
|
<displayName>MASK1</displayName>
|
|
<description>DWT Mask Register 1</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Mask on data address when matching against COMP. This is the size of the ignore mask. hat is, DWT matching is performed as:(ADDR ANDed with (~0 left bit-shifted by MASK)) == COMP. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP is 3, this matches a word access of 0, because 3 would be within the word.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_FUNCTION1</name>
|
|
<displayName>FUNCTION1</displayName>
|
|
<description>DWT Function Register 1</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FUNCTION</name>
|
|
<description>Function settings. Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: FUNCTION is overridden for comparators given by DATAVADDR0 and DATAVADDR1 in DWT_FUNCTION1if DATAVMATCH is also set in DWT_FUNCTION1. The comparators given by DATAVADDR0 and DATAVADDR1 can then only perform address comparator matches for comparator 1 data matches. Note 4: If the data matching functionality is not included during implementation it is not possible to set DATAVADDR0, DATAVADDR1, or DATAVMATCH in DWT_FUNCTION1. This means that the data matching functionality is not available in the implementation. Test the availability of data matching by writing and reading the DATAVMATCH bit in DWT_FUNCTION1. If it is not settable then data matching is unavailable. Note 5: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0010</name>
|
|
<description>EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0011</name>
|
|
<description>EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0100</name>
|
|
<description>Watchpoint on PC match.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0101</name>
|
|
<description>Watchpoint on read.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0110</name>
|
|
<description>Watchpoint on write.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0111</name>
|
|
<description>Watchpoint on read or write.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1000</name>
|
|
<description>ETM trigger on PC match</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1001</name>
|
|
<description>ETM trigger on read</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1010</name>
|
|
<description>ETM trigger on write</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1011</name>
|
|
<description>ETM trigger on read or write</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1100</name>
|
|
<description>EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1101</name>
|
|
<description>EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1110</name>
|
|
<description>EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1111</name>
|
|
<description>EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMITRANGE</name>
|
|
<description>Emit range field. Reserved to permit emitting offset when range match occurs. Reset clears the EMITRANGE bit. PC sampling is not supported when EMITRANGE is enabled. EMITRANGE only applies for: FUNCTION = b0001, b0010, b0011, b1100, b1101, b1110, and b1111.</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CYCMATCH</name>
|
|
<description>Only available in comparator 0. When set, this comparator compares against the clock cycle counter.</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATAVMATCH</name>
|
|
<description>This bit is only available in comparator 1. When DATAVMATCH is set, this comparator performs data value compares. The comparators given by DATAVADDR0 and DATAVADDR1provide the address for the data comparison. If DATAVMATCH is set in DWT_FUNCTION1, the FUNCTION setting for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and those comparators only provide the address match for the data comparison.</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LNK1ENA</name>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>DATAVADDR1 not supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>DATAVADDR1 supported (enabled).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATAVSIZE</name>
|
|
<description>Defines the size of the data in the COMP register that is to be matched:</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b00</name>
|
|
<description>byte</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b01</name>
|
|
<description>halfword</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b10</name>
|
|
<description>word</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b11</name>
|
|
<description>Unpredictable.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATAVADDR0</name>
|
|
<description>Identity of a linked address comparator for data value matching when DATAVMATCH == 1.</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATAVADDR1</name>
|
|
<description>Identity of a second linked address comparator for data value matching when DATAVMATCH == 1 and LNK1ENA == 1.</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MATCHED</name>
|
|
<description>This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read.</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_COMP2</name>
|
|
<displayName>COMP2</displayName>
|
|
<description>DWT Comparator Register 2</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Data value to compare against PC and the data address as given by DWT_FUNCTION2.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_MASK2</name>
|
|
<displayName>MASK2</displayName>
|
|
<description>DWT Mask Register 2</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Mask on data address when matching against COMP. This is the size of the ignore mask. hat is, DWT matching is performed as:(ADDR ANDed with (~0 left bit-shifted by MASK)) == COMP. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP is 3, this matches a word access of 0, because 3 would be within the word.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_FUNCTION2</name>
|
|
<displayName>FUNCTION2</displayName>
|
|
<description>DWT Function Register 2</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FUNCTION</name>
|
|
<description>Function settings. Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0010</name>
|
|
<description>EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0011</name>
|
|
<description>EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0100</name>
|
|
<description>Watchpoint on PC match.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0101</name>
|
|
<description>Watchpoint on read.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0110</name>
|
|
<description>Watchpoint on write.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0111</name>
|
|
<description>Watchpoint on read or write.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1000</name>
|
|
<description>ETM trigger on PC match</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1001</name>
|
|
<description>ETM trigger on read</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1010</name>
|
|
<description>ETM trigger on write</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1011</name>
|
|
<description>ETM trigger on read or write</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1100</name>
|
|
<description>EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1101</name>
|
|
<description>EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1110</name>
|
|
<description>EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1111</name>
|
|
<description>EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMITRANGE</name>
|
|
<description>Emit range field. Reserved to permit emitting offset when range match occurs. Reset clears the EMITRANGE bit. PC sampling is not supported when EMITRANGE is enabled. EMITRANGE only applies for: FUNCTION = b0001, b0010, b0011, b1100, b1101, b1110, and b1111.</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATAVMATCH</name>
|
|
<description>This bit is only available in comparator 1. When DATAVMATCH is set, this comparator performs data value compares. The comparators given by DATAVADDR0 and DATAVADDR1provide the address for the data comparison. If DATAVMATCH is set in DWT_FUNCTION1, the FUNCTION setting for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and those comparators only provide the address match for the data comparison.</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LNK1ENA</name>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>DATAVADDR1 not supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>DATAVADDR1 supported (enabled).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATAVSIZE</name>
|
|
<description>Defines the size of the data in the COMP register that is to be matched:</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b00</name>
|
|
<description>byte</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b01</name>
|
|
<description>halfword</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b10</name>
|
|
<description>word</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b11</name>
|
|
<description>Unpredictable.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATAVADDR0</name>
|
|
<description>Identity of a linked address comparator for data value matching when DATAVMATCH == 1.</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATAVADDR1</name>
|
|
<description>Identity of a second linked address comparator for data value matching when DATAVMATCH == 1 and LNK1ENA == 1.</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MATCHED</name>
|
|
<description>This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read.</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_COMP3</name>
|
|
<displayName>COMP3</displayName>
|
|
<description>DWT Comparator Register 3</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Data value to compare against PC and the data address as given by DWT_FUNCTION3.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_MASK3</name>
|
|
<displayName>MASK3</displayName>
|
|
<description>DWT Mask Register 3</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Mask on data address when matching against COMP. This is the size of the ignore mask. hat is, DWT matching is performed as:(ADDR ANDed with (~0 left bit-shifted by MASK)) == COMP. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP is 3, this matches a word access of 0, because 3 would be within the word.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_FUNCTION3</name>
|
|
<displayName>FUNCTION3</displayName>
|
|
<description>DWT Function Register 3</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FUNCTION</name>
|
|
<description>Function settings. Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0010</name>
|
|
<description>EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0011</name>
|
|
<description>EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0100</name>
|
|
<description>Watchpoint on PC match.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0101</name>
|
|
<description>Watchpoint on read.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0110</name>
|
|
<description>Watchpoint on write.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0111</name>
|
|
<description>Watchpoint on read or write.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1000</name>
|
|
<description>ETM trigger on PC match</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1001</name>
|
|
<description>ETM trigger on read</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1010</name>
|
|
<description>ETM trigger on write</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1011</name>
|
|
<description>ETM trigger on read or write</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1100</name>
|
|
<description>EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1101</name>
|
|
<description>EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1110</name>
|
|
<description>EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1111</name>
|
|
<description>EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMITRANGE</name>
|
|
<description>Emit range field. Reserved to permit emitting offset when range match occurs. Reset clears the EMITRANGE bit. PC sampling is not supported when EMITRANGE is enabled. EMITRANGE only applies for: FUNCTION = b0001, b0010, b0011, b1100, b1101, b1110, and b1111.</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATAVMATCH</name>
|
|
<description>This bit is only available in comparator 1. When DATAVMATCH is set, this comparator performs data value compares. The comparators given by DATAVADDR0 and DATAVADDR1provide the address for the data comparison. If DATAVMATCH is set in DWT_FUNCTION1, the FUNCTION setting for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and those comparators only provide the address match for the data comparison.</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LNK1ENA</name>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>DATAVADDR1 not supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>DATAVADDR1 supported (enabled).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATAVSIZE</name>
|
|
<description>Defines the size of the data in the COMP register that is to be matched:</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b00</name>
|
|
<description>byte</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b01</name>
|
|
<description>halfword</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b10</name>
|
|
<description>word</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b11</name>
|
|
<description>Unpredictable.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATAVADDR0</name>
|
|
<description>Identity of a linked address comparator for data value matching when DATAVMATCH == 1.</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATAVADDR1</name>
|
|
<description>Identity of a second linked address comparator for data value matching when DATAVMATCH == 1 and LNK1ENA == 1.</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MATCHED</name>
|
|
<description>This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read.</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FPB</name>
|
|
<version>356.0</version>
|
|
<description>FPB</description>
|
|
<baseAddress>0xE0002000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>FP_CTRL</name>
|
|
<displayName>FP_CTRL</displayName>
|
|
<description>Flash Patch Control Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000130</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Flash patch unit enable bit</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>flash patch unit disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>flash patch unit enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Key field. To write to the Flash Patch Control Register, you must write a 1 to this write-only bit.</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NUM_CODE1</name>
|
|
<description>Number of code slots field.</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>no code slots</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0010</name>
|
|
<description>two code slots</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0110</name>
|
|
<description>six code slots</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NUM_LIT</name>
|
|
<description>Number of literal slots field.</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>no literal slots</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0010</name>
|
|
<description>two literal slots</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NUM_CODE2</name>
|
|
<description>Number of full banks of code comparators, sixteen comparators per bank. Where less than sixteen code comparators are provided, the bank count is zero, and the number present indicated by NUM_CODE. This read only field contains 3'b000 to indicate 0 banks for Cortex-M4 processor.</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FP_REMAP</name>
|
|
<displayName>FP_REMAP</displayName>
|
|
<description>Flash Patch Remap Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>REMAP</name>
|
|
<description>Remap base address field.</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x18</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FP_COMP0</name>
|
|
<displayName>FP_COMP0</displayName>
|
|
<description>Flash Patch Comparator Registers</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Compare and remap enable for Flash Patch Comparator Register 0. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>Flash Patch Comparator Register 0 compare and remap disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>Flash Patch Comparator Register 0 compare and remap enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Comparison address.</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1B</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REPLACE</name>
|
|
<description>This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting.</description>
|
|
<bitOffset>0x1E</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b00</name>
|
|
<description>remap to remap address. See FP_REMAP</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b01</name>
|
|
<description>set BKPT on lower halfword, upper is unaffected</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b10</name>
|
|
<description>set BKPT on upper halfword, lower is unaffected</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b11</name>
|
|
<description>set BKPT on both lower and upper halfwords.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FP_COMP1</name>
|
|
<displayName>FP_COMP1</displayName>
|
|
<description>Flash Patch Comparator Registers</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Compare and remap enable for Flash Patch Comparator Register 1. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>Flash Patch Comparator Register 1 compare and remap disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>Flash Patch Comparator Register 1 compare and remap enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Comparison address.</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1B</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REPLACE</name>
|
|
<description>This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting.</description>
|
|
<bitOffset>0x1E</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b00</name>
|
|
<description>remap to remap address. See FP_REMAP</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b01</name>
|
|
<description>set BKPT on lower halfword, upper is unaffected</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b10</name>
|
|
<description>set BKPT on upper halfword, lower is unaffected</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b11</name>
|
|
<description>set BKPT on both lower and upper halfwords.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FP_COMP2</name>
|
|
<displayName>FP_COMP2</displayName>
|
|
<description>Flash Patch Comparator Registers</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Compare and remap enable for Flash Patch Comparator Register 2. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>Flash Patch Comparator Register 2 compare and remap disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>Flash Patch Comparator Register 2 compare and remap enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Comparison address.</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1B</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REPLACE</name>
|
|
<description>This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting.</description>
|
|
<bitOffset>0x1E</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b00</name>
|
|
<description>remap to remap address. See FP_REMAP</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b01</name>
|
|
<description>set BKPT on lower halfword, upper is unaffected</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b10</name>
|
|
<description>set BKPT on upper halfword, lower is unaffected</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b11</name>
|
|
<description>set BKPT on both lower and upper halfwords.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FP_COMP3</name>
|
|
<displayName>FP_COMP3</displayName>
|
|
<description>Flash Patch Comparator Registers</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Compare and remap enable for Flash Patch Comparator Register 3. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>Flash Patch Comparator Register 3 compare and remap disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>Flash Patch Comparator Register 3 compare and remap enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Comparison address.</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1B</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REPLACE</name>
|
|
<description>This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting.</description>
|
|
<bitOffset>0x1E</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b00</name>
|
|
<description>remap to remap address. See FP_REMAP</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b01</name>
|
|
<description>set BKPT on lower halfword, upper is unaffected</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b10</name>
|
|
<description>set BKPT on upper halfword, lower is unaffected</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b11</name>
|
|
<description>set BKPT on both lower and upper halfwords.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FP_COMP4</name>
|
|
<displayName>FP_COMP4</displayName>
|
|
<description>Flash Patch Comparator Registers</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Compare and remap enable for Flash Patch Comparator Register 4. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>Flash Patch Comparator Register 4 compare and remap disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>Flash Patch Comparator Register 4 compare and remap enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Comparison address.</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1B</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REPLACE</name>
|
|
<description>This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting.</description>
|
|
<bitOffset>0x1E</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b00</name>
|
|
<description>remap to remap address. See FP_REMAP</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b01</name>
|
|
<description>set BKPT on lower halfword, upper is unaffected</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b10</name>
|
|
<description>set BKPT on upper halfword, lower is unaffected</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b11</name>
|
|
<description>set BKPT on both lower and upper halfwords.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FP_COMP5</name>
|
|
<displayName>FP_COMP5</displayName>
|
|
<description>Flash Patch Comparator Registers</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Compare and remap enable for Flash Patch Comparator Register 5. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>Flash Patch Comparator Register 5 compare and remap disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>Flash Patch Comparator Register 5 compare and remap enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Comparison address.</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1B</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REPLACE</name>
|
|
<description>This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting.</description>
|
|
<bitOffset>0x1E</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b00</name>
|
|
<description>remap to remap address. See FP_REMAP</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b01</name>
|
|
<description>set BKPT on lower halfword, upper is unaffected</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b10</name>
|
|
<description>set BKPT on upper halfword, lower is unaffected</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b11</name>
|
|
<description>set BKPT on both lower and upper halfwords.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FP_COMP6</name>
|
|
<displayName>FP_COMP6</displayName>
|
|
<description>Flash Patch Comparator Registers</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Compare and remap enable for Flash Patch Comparator Register 6. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>Flash Patch Comparator Register 6 compare and remap disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>Flash Patch Comparator Register 6 compare and remap enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Comparison address.</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1B</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REPLACE</name>
|
|
<description>This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting.</description>
|
|
<bitOffset>0x1E</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b00</name>
|
|
<description>remap to remap address. See FP_REMAP</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b01</name>
|
|
<description>set BKPT on lower halfword, upper is unaffected</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b10</name>
|
|
<description>set BKPT on upper halfword, lower is unaffected</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b11</name>
|
|
<description>set BKPT on both lower and upper halfwords.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FP_COMP7</name>
|
|
<displayName>FP_COMP7</displayName>
|
|
<description>Flash Patch Comparator Registers</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Compare and remap enable for Flash Patch Comparator Register 7. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>Flash Patch Comparator Register 7 compare and remap disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>Flash Patch Comparator Register 7 compare and remap enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Comparison address.</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1B</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REPLACE</name>
|
|
<description>This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting.</description>
|
|
<bitOffset>0x1E</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b00</name>
|
|
<description>remap to remap address. See FP_REMAP</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b01</name>
|
|
<description>set BKPT on lower halfword, upper is unaffected</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b10</name>
|
|
<description>set BKPT on upper halfword, lower is unaffected</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b11</name>
|
|
<description>set BKPT on both lower and upper halfwords.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SystemControlSpace</name>
|
|
<version>356.0</version>
|
|
<description>System Control Space for ARM core: SCnSCB, SCB, SysTick, NVIC, CoreDebug, MPU, FPU</description>
|
|
<baseAddress>0xE000E000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>ICTR</name>
|
|
<displayName>ICTR</displayName>
|
|
<description>Interrupt Control Type Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>INTLINESNUM</name>
|
|
<description>Total number of interrupt lines in groups of 32.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x5</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACTLR</name>
|
|
<displayName>ACTLR</displayName>
|
|
<description>Auxiliary Control Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DISMCYCINT</name>
|
|
<description>Disables interruption of multi-cycle instructions. This increases the interrupt latency of the processor becuase LDM/STM completes before interrupt stacking occurs.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISDEFWBUF</name>
|
|
<description>Disables write buffer us during default memorty map accesses. This causes all bus faults to be precise bus faults but decreases the performance of the processor because the stores to memory have to complete before the next instruction can be executed.</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISFOLD</name>
|
|
<description>Disables IT folding.</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISFPCA</name>
|
|
<description>Disable automatic update of CONTROL.FPCA</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISOOFP</name>
|
|
<description>Disables floating point instructions completing out of order with respect to integer
|
|
instructions.</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>ISER0</name>
|
|
<displayName>ISER0</displayName>
|
|
<description>Irq 0 to 31 Set Enable Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SETENA</name>
|
|
<description>Writing 0 to a SETENA bit has no effect, writing 1 to a bit enables the corresponding interrupt. Reading the bit returns its current enable state. Reset clears the SETENA fields.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISER1</name>
|
|
<displayName>ISER1</displayName>
|
|
<description>Irq 32 to 63 Set Enable Register</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SETENA</name>
|
|
<description>Writing 0 to a SETENA bit has no effect, writing 1 to a bit enables the corresponding interrupt. Reading the bit returns its current enable state. Reset clears the SETENA fields.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICER0</name>
|
|
<displayName>ICER0</displayName>
|
|
<description>Irq 0 to 31 Clear Enable Register</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CLRENA</name>
|
|
<description>Writing 0 to a CLRENA bit has no effect, writing 1 to a bit disables the corresponding interrupt. Reading the bit returns its current enable state. Reset clears the CLRENA field.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICER1</name>
|
|
<displayName>ICER1</displayName>
|
|
<description>Irq 32 to 63 Clear Enable Register</description>
|
|
<addressOffset>0x184</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CLRENA</name>
|
|
<description>Writing 0 to a CLRENA bit has no effect, writing 1 to a bit disables the corresponding interrupt. Reading the bit returns its current enable state. Reset clears the CLRENA field.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISPR0</name>
|
|
<displayName>ISPR0</displayName>
|
|
<description>Irq 0 to 31 Set Pending Register</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SETPEND</name>
|
|
<description>Writing 0 to a SETPEND bit has no effect, writing 1 to a bit pends the corresponding interrupt. Reading the bit returns its current state.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISPR1</name>
|
|
<displayName>ISPR1</displayName>
|
|
<description>Irq 32 to 63 Set Pending Register</description>
|
|
<addressOffset>0x204</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SETPEND</name>
|
|
<description>Writing 0 to a SETPEND bit has no effect, writing 1 to a bit pends the corresponding interrupt. Reading the bit returns its current state.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICPR0</name>
|
|
<displayName>ICPR0</displayName>
|
|
<description>Irq 0 to 31 Clear Pending Register</description>
|
|
<addressOffset>0x280</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CLRPEND</name>
|
|
<description>Writing 0 to a CLRPEND bit has no effect, writing 1 to a bit clears the corresponding pending interrupt. Reading the bit returns its current state.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICPR1</name>
|
|
<displayName>ICPR1</displayName>
|
|
<description>Irq 32 to 63 Clear Pending Register</description>
|
|
<addressOffset>0x284</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CLRPEND</name>
|
|
<description>Writing 0 to a CLRPEND bit has no effect, writing 1 to a bit clears the corresponding pending interrupt. Reading the bit returns its current state.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IABR0</name>
|
|
<displayName>IABR0</displayName>
|
|
<description>Irq 0 to 31 Active Bit Register</description>
|
|
<addressOffset>0x300</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Interrupt active flags. Reading 0 implies the interrupt is not active or stacked. Reading 1 implies the interrupt is active or pre-empted and stacked.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IABR1</name>
|
|
<displayName>IABR1</displayName>
|
|
<description>Irq 32 to 63 Active Bit Register</description>
|
|
<addressOffset>0x304</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Interrupt active flags. Reading 0 implies the interrupt is not active or stacked. Reading 1 implies the interrupt is active or pre-empted and stacked.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR0</name>
|
|
<displayName>IPR0</displayName>
|
|
<description>Irq 0 to 3 Priority Register</description>
|
|
<addressOffset>0x400</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_0</name>
|
|
<description>Priority of interrupt 0</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_1</name>
|
|
<description>Priority of interrupt 1</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_2</name>
|
|
<description>Priority of interrupt 2</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_3</name>
|
|
<description>Priority of interrupt 3</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR1</name>
|
|
<displayName>IPR1</displayName>
|
|
<description>Irq 4 to 7 Priority Register</description>
|
|
<addressOffset>0x404</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_4</name>
|
|
<description>Priority of interrupt 4</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_5</name>
|
|
<description>Priority of interrupt 5</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_6</name>
|
|
<description>Priority of interrupt 6</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_7</name>
|
|
<description>Priority of interrupt 7</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR2</name>
|
|
<displayName>IPR2</displayName>
|
|
<description>Irq 8 to 11 Priority Register</description>
|
|
<addressOffset>0x408</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_8</name>
|
|
<description>Priority of interrupt 8</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_9</name>
|
|
<description>Priority of interrupt 9</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_10</name>
|
|
<description>Priority of interrupt 10</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_11</name>
|
|
<description>Priority of interrupt 11</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR3</name>
|
|
<displayName>IPR3</displayName>
|
|
<description>Irq 12 to 15 Priority Register</description>
|
|
<addressOffset>0x40C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_12</name>
|
|
<description>Priority of interrupt 12</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_13</name>
|
|
<description>Priority of interrupt 13</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_14</name>
|
|
<description>Priority of interrupt 14</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_15</name>
|
|
<description>Priority of interrupt 15</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR4</name>
|
|
<displayName>IPR4</displayName>
|
|
<description>Irq 16 to 19 Priority Register</description>
|
|
<addressOffset>0x410</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_16</name>
|
|
<description>Priority of interrupt 16</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_17</name>
|
|
<description>Priority of interrupt 17</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_18</name>
|
|
<description>Priority of interrupt 18</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_19</name>
|
|
<description>Priority of interrupt 19</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR5</name>
|
|
<displayName>IPR5</displayName>
|
|
<description>Irq 20 to 23 Priority Register</description>
|
|
<addressOffset>0x414</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_20</name>
|
|
<description>Priority of interrupt 20</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_21</name>
|
|
<description>Priority of interrupt 21</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_22</name>
|
|
<description>Priority of interrupt 22</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_23</name>
|
|
<description>Priority of interrupt 23</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR6</name>
|
|
<displayName>IPR6</displayName>
|
|
<description>Irq 24 to 27 Priority Register</description>
|
|
<addressOffset>0x418</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_24</name>
|
|
<description>Priority of interrupt 24</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_25</name>
|
|
<description>Priority of interrupt 25</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_26</name>
|
|
<description>Priority of interrupt 26</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_27</name>
|
|
<description>Priority of interrupt 27</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR7</name>
|
|
<displayName>IPR7</displayName>
|
|
<description>Irq 28 to 31 Priority Register</description>
|
|
<addressOffset>0x41C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_28</name>
|
|
<description>Priority of interrupt 28</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_29</name>
|
|
<description>Priority of interrupt 29</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_30</name>
|
|
<description>Priority of interrupt 30</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_31</name>
|
|
<description>Priority of interrupt 31</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR8</name>
|
|
<displayName>IPR8</displayName>
|
|
<description>Irq 32 to 35 Priority Register</description>
|
|
<addressOffset>0x420</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_32</name>
|
|
<description>Priority of interrupt 32</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_33</name>
|
|
<description>Priority of interrupt 33</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_34</name>
|
|
<description>Priority of interrupt 34</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_35</name>
|
|
<description>Priority of interrupt 35</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR9</name>
|
|
<displayName>IPR9</displayName>
|
|
<description>Irq 36 to 39 Priority Register</description>
|
|
<addressOffset>0x424</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_36</name>
|
|
<description>Priority of interrupt 36</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_37</name>
|
|
<description>Priority of interrupt 37</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_38</name>
|
|
<description>Priority of interrupt 38</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_39</name>
|
|
<description>Priority of interrupt 39</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR10</name>
|
|
<displayName>IPR10</displayName>
|
|
<description>Irq 40 to 43 Priority Register</description>
|
|
<addressOffset>0x428</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_40</name>
|
|
<description>Priority of interrupt 40</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_41</name>
|
|
<description>Priority of interrupt 41</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_42</name>
|
|
<description>Priority of interrupt 42</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_43</name>
|
|
<description>Priority of interrupt 43</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR11</name>
|
|
<displayName>IPR11</displayName>
|
|
<description>Irq 44 to 47 Priority Register</description>
|
|
<addressOffset>0x42C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_44</name>
|
|
<description>Priority of interrupt 44</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_45</name>
|
|
<description>Priority of interrupt 45</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_46</name>
|
|
<description>Priority of interrupt 46</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_47</name>
|
|
<description>Priority of interrupt 47</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR12</name>
|
|
<displayName>IPR12</displayName>
|
|
<description>Irq 48 to 51 Priority Register</description>
|
|
<addressOffset>0x430</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_48</name>
|
|
<description>Priority of interrupt 48</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_49</name>
|
|
<description>Priority of interrupt 49</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_50</name>
|
|
<description>Priority of interrupt 50</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_51</name>
|
|
<description>Priority of interrupt 51</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR13</name>
|
|
<displayName>IPR13</displayName>
|
|
<description>Irq 52 to 55 Priority Register</description>
|
|
<addressOffset>0x434</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_52</name>
|
|
<description>Priority of interrupt 52</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_53</name>
|
|
<description>Priority of interrupt 53</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_54</name>
|
|
<description>Priority of interrupt 54</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_55</name>
|
|
<description>Priority of interrupt 55</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR14</name>
|
|
<displayName>IPR14</displayName>
|
|
<description>Irq 56 to 59 Priority Register</description>
|
|
<addressOffset>0x438</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_56</name>
|
|
<description>Priority of interrupt 56</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_57</name>
|
|
<description>Priority of interrupt 57</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_58</name>
|
|
<description>Priority of interrupt 58</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_59</name>
|
|
<description>Priority of interrupt 59</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR15</name>
|
|
<displayName>IPR15</displayName>
|
|
<description>Irq 60 to 63 Priority Register</description>
|
|
<addressOffset>0x43C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_60</name>
|
|
<description>Priority of interrupt 60</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_61</name>
|
|
<description>Priority of interrupt 61</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_62</name>
|
|
<description>Priority of interrupt 62</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_63</name>
|
|
<description>Priority of interrupt 63</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STIR</name>
|
|
<displayName>STIR</displayName>
|
|
<description>Software Trigger Interrupt Register</description>
|
|
<addressOffset>0xF00</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>INTID</name>
|
|
<description>Interrupt ID field. Writing a value to the INTID field is the same as manually pending an interrupt by setting the corresponding interrupt bit in an Interrupt Set Pending Register.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x9</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>STCSR</name>
|
|
<displayName>STCSR</displayName>
|
|
<description>SysTick Control and Status Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000004</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable SysTick counter</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>First</name>
|
|
<description>Counter disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TICKINT</name>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>VAL_0</name>
|
|
<description>Counting down to zero does not pend the SysTick handler. Software can use COUNTFLAG to determine if the SysTick handler has ever counted to zero.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VAL_1</name>
|
|
<description>Counting down to zero pends the SysTick handler.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKSOURCE</name>
|
|
<description>Clock source.</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>CLKSOURCE_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>VAL_0</name>
|
|
<description>Not applicable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VAL_1</name>
|
|
<description>Core clock</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COUNTFLAG</name>
|
|
<description>Returns 1 if timer counted to 0 since last time this was read. Clears on read by application of any part of the SysTick Control and Status Register. If read by the debugger using the DAP, this bit is cleared on read-only if the MasterType bit in the AHB-AP Control Register is set to 0. Otherwise, the COUNTFLAG bit is not changed by the debugger read.</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STRVR</name>
|
|
<displayName>STRVR</displayName>
|
|
<description>SysTick Reload Value Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>RELOAD</name>
|
|
<description>Value to load into the SysTick Current Value Register when the counter reaches 0.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x18</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STCVR</name>
|
|
<displayName>STCVR</displayName>
|
|
<description>SysTick Current Value Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>CURRENT</name>
|
|
<description>Current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x18</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STCR</name>
|
|
<displayName>STCR</displayName>
|
|
<description>SysTick Calibration Value Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>TENMS</name>
|
|
<description>Reads as zero. Indicates calibration value is not known.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x18</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SKEW</name>
|
|
<description>Reads as one. The calibration value is not exactly 10ms because of clock frequency. This could affect its suitability as a software real time clock.</description>
|
|
<bitOffset>0x1E</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NOREF</name>
|
|
<description>Reads as one. Indicates that no separate reference clock is provided.</description>
|
|
<bitOffset>0x1F</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CPUID</name>
|
|
<displayName>CPUID</displayName>
|
|
<description>CPUID Base Register</description>
|
|
<addressOffset>0xD00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x410fc241</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REVISION</name>
|
|
<description>Implementation defined revision number.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PARTNO</name>
|
|
<description>Number of processor within family.</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0xC</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CONSTANT</name>
|
|
<description>Reads as 0xC</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>VARIANT</name>
|
|
<description>Implementation defined variant number.</description>
|
|
<bitOffset>0x14</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IMPLEMENTER</name>
|
|
<description>Implementor code.</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICSR</name>
|
|
<displayName>ICSR</displayName>
|
|
<description>Interrupt Control State Register</description>
|
|
<addressOffset>0xD04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VECTACTIVE</name>
|
|
<description>Active ISR number field. Reset clears the VECTACTIVE field.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RETTOBASE</name>
|
|
<description>This bit is 1 when the set of all active exceptions minus the IPSR_current_exception yields the empty set.</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>VECTPENDING</name>
|
|
<description>Pending ISR number field. VECTPENDING contains the interrupt number of the highest priority pending ISR.</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x6</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ISRPENDING</name>
|
|
<description>Interrupt pending flag. Excludes NMI and faults.</description>
|
|
<bitOffset>0x16</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>interrupt not pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>interrupt pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISRPREEMPT</name>
|
|
<description>You must only use this at debug time. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced.</description>
|
|
<bitOffset>0x17</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>a pending exception is not serviced.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>a pending exception is serviced on exit from the debug halt state</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PENDSTCLR</name>
|
|
<description>Clear pending SysTick bit</description>
|
|
<bitOffset>0x19</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>do not clear pending SysTick</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>clear pending SysTick</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PENDSTSET</name>
|
|
<description>Set a pending SysTick bit.</description>
|
|
<bitOffset>0x1A</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>do not set pending SysTick</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>set pending SysTick</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PENDSVCLR</name>
|
|
<description>Clear pending pendSV bit</description>
|
|
<bitOffset>0x1B</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>do not clear pending pendSV</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>clear pending pendSV</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PENDSVSET</name>
|
|
<description>Set pending pendSV bit.</description>
|
|
<bitOffset>0x1C</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>do not set pending pendSV</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>set pending PendSV</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NMIPENDSET</name>
|
|
<description>Set pending NMI bit. NMIPENDSET pends and activates an NMI. Because NMI is the highest-priority interrupt, it takes effect as soon as it registers.</description>
|
|
<bitOffset>0x1F</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>do not set pending NMI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>set pending NMI</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VTOR</name>
|
|
<displayName>VTOR</displayName>
|
|
<description>Vector Table Offset Register</description>
|
|
<addressOffset>0xD08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TBLOFF</name>
|
|
<description>Vector table base offset field. Contains the offset of the table base from the bottom of the SRAM or CODE space.</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TBLBASE</name>
|
|
<description>Table base is in Code (0) or RAM (1).</description>
|
|
<bitOffset>0x1D</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AIRCR</name>
|
|
<displayName>AIRCR</displayName>
|
|
<description>Application Interrupt/Reset Control Register</description>
|
|
<addressOffset>0xD0C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xfa050000</resetValue>
|
|
<resetMask>0xffff7fff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VECTRESET</name>
|
|
<description>System Reset bit. Resets the system, with the exception of debug components. The VECTRESET bit self-clears. Reset clears the VECTRESET bit. For debugging, only write this bit when the core is halted.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>VECTCLRACTIVE</name>
|
|
<description>Clears all active state information for active NMI, fault, and interrupts. It is the responsibility of the application to reinitialize the stack. The VECTCLRACTIVE bit is for returning to a known state during debug. The VECTCLRACTIVE bit self-clears. IPSR is not cleared by this operation. So, if used by an application, it must only be used at the base level of activation, or within a system handler whose active bit can be set.</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SYSRESETREQ</name>
|
|
<description>Causes a signal to be asserted to the outer system that indicates a reset is requested. Intended to force a large system reset of all major components except for debug. Setting this bit does not prevent Halting Debug from running.</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PRIGROUP</name>
|
|
<description>Interrupt priority grouping field. The PRIGROUP field is a binary point position indicator for creating subpriorities for exceptions that share the same pre-emption level. It divides the PRI_n field in the Interrupt Priority Register into a pre-emption level and a subpriority level. The binary point is a left-of value. This means that the PRIGROUP value represents a point starting at the left of the Least Significant Bit (LSB). This is bit [0] of 7:0. The lowest value might not be 0 depending on the number of bits allocated for priorities, and implementation choices</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDIANESS</name>
|
|
<description>Data endianness bit. ENDIANNESS is sampled from the BIGEND input port during reset. You cannot change ENDIANNESS outside of reset.</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>little endian</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>big endian</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VECTKEY</name>
|
|
<description>Register key. Writing to this register requires 0x5FA in the VECTKEY field. Otherwise the write value is ignored.</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR</name>
|
|
<displayName>SCR</displayName>
|
|
<description>System Control Register</description>
|
|
<addressOffset>0xD10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SLEEPONEXIT</name>
|
|
<description>Sleep on exit when returning from Handler mode to Thread mode. Enables interrupt driven applications to avoid returning to empty main application.</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>do not sleep when returning to thread mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>sleep on ISR exit</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLEEPDEEP</name>
|
|
<description>Sleep deep bit.</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>not OK to turn off system clock</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>indicates to the system that Cortex-M4 clock can be stopped. Setting this bit causes the SLEEPDEEP port to be asserted when the processor can be stopped.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEVONPEND</name>
|
|
<description>When enabled, this causes WFE to wake up when an interrupt moves from inactive to pended. Otherwise, WFE only wakes up from an event signal, external and SEV instruction generated. The event input, RXEV, is registered even when not waiting for an event, and so effects the next WFE.</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR</name>
|
|
<displayName>CCR</displayName>
|
|
<description>Configuration Control Register</description>
|
|
<addressOffset>0xD14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000200</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NONBASETHREDENA</name>
|
|
<description>When 0, default, It is only possible to enter Thread mode when returning from the last exception. When set to 1, Thread mode can be entered from any level in Handler mode by controlled return value.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USERSETMPEND</name>
|
|
<description>If written as 1, enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception, which is one associated with the Main stack pointer.</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UNALIGN_TRP</name>
|
|
<description>Trap for unaligned access. This enables faulting/halting on any unaligned half or full word access. Unaligned load-store multiples always fault. The relevant Usage Fault Status Register bit is UNALIGNED.</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIV_0_TRP</name>
|
|
<description>Trap on Divide by 0. This enables faulting/halting when an attempt is made to divide by 0. The relevant Usage Fault Status Register bit is DIVBYZERO.</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BFHFNMIGN</name>
|
|
<description>When enabled, this causes handlers running at priority -1 and -2 (Hard Fault, NMI, and FAULTMASK escalated handlers) to ignore Data Bus faults caused by load and store instructions. When disabled, these bus faults cause a lock-up. You must only use this enable with extreme caution. All data bus faults are ignored therefore you must only use it when the handler and its data are in absolutely safe memory. Its normal use is to probe system devices and bridges to detect control path problems and fix them.</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STKALIGN</name>
|
|
<description>Stack alignment bit.</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>Only 4-byte alignment is guaranteed for the SP used prior to the exception on exception entry.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned and the context to restore it is saved. The SP is restored on the associated exception return.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHPR1</name>
|
|
<displayName>SHPR1</displayName>
|
|
<description>System Handlers 4-7 Priority Register</description>
|
|
<addressOffset>0xD18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_4</name>
|
|
<description>Priority of system handler 4.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_5</name>
|
|
<description>Priority of system handler 5.</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_6</name>
|
|
<description>Priority of system handler 6.</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_7</name>
|
|
<description>Priority of system handler 7.</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHPR2</name>
|
|
<displayName>SHPR2</displayName>
|
|
<description>System Handlers 8-11 Priority Register</description>
|
|
<addressOffset>0xD1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_8</name>
|
|
<description>Priority of system handler 8.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_9</name>
|
|
<description>Priority of system handler 9.</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_10</name>
|
|
<description>Priority of system handler 10.</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_11</name>
|
|
<description>Priority of system handler 11.</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHPR3</name>
|
|
<displayName>SHPR3</displayName>
|
|
<description>System Handlers 12-15 Priority Register</description>
|
|
<addressOffset>0xD20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_12</name>
|
|
<description>Priority of system handler 12.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_13</name>
|
|
<description>Priority of system handler 13.</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_14</name>
|
|
<description>Priority of system handler 14.</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_15</name>
|
|
<description>Priority of system handler 15.</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHCSR</name>
|
|
<displayName>SHCSR</displayName>
|
|
<description>System Handler Control and State Register</description>
|
|
<addressOffset>0xD24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MEMFAULTACT</name>
|
|
<description>MemManage active flag.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>not active</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>active</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSFAULTACT</name>
|
|
<description>BusFault active flag.</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>not active</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>active</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USGFAULTACT</name>
|
|
<description>UsageFault active flag.</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>not active</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>active</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SVCALLACT</name>
|
|
<description>SVCall active flag.</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>not active</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>active</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MONITORACT</name>
|
|
<description>the Monitor active flag.</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>not active</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>active</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PENDSVACT</name>
|
|
<description>PendSV active flag.</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>not active</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>active</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSTICKACT</name>
|
|
<description>SysTick active flag.</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>not active</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>active</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USGFAULTPENDED</name>
|
|
<description>usage fault pended flag.</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>not pended</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>pended</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MEMFAULTPENDED</name>
|
|
<description>MemManage pended flag.</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>not pended</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>pended</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSFAULTPENDED</name>
|
|
<description>BusFault pended flag.</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>not pended</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>pended</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SVCALLPENDED</name>
|
|
<description>SVCall pended flag.</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>not pended</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>pended</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MEMFAULTENA</name>
|
|
<description>MemManage fault system handler enable</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSFAULTENA</name>
|
|
<description>Bus fault system handler enable</description>
|
|
<bitOffset>0x11</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USGFAULTENA</name>
|
|
<description>Usage fault system handler enable</description>
|
|
<bitOffset>0x12</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFSR</name>
|
|
<displayName>CFSR</displayName>
|
|
<description>Configurable Fault Status Registers</description>
|
|
<addressOffset>0xD28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IACCVIOL</name>
|
|
<description>Instruction access violation flag. Attempting to fetch an instruction from a location that does not permit execution sets the IACCVIOL flag. This occurs on any access to an XN region, even when the MPU is disabled or not present. The return PC points to the faulting instruction. The MMAR is not written.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DACCVIOL</name>
|
|
<description>Data access violation flag. Attempting to load or store at a location that does not permit the operation sets the DACCVIOL flag. The return PC points to the faulting instruction. This error loads MMAR with the address of the attempted access.</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MUNSTKERR</name>
|
|
<description>Unstack from exception return has caused one or more access violations. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. The MMAR is not written.</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSTKERR</name>
|
|
<description>Stacking from exception has caused one or more access violations. The SP is still adjusted and the values in the context area on the stack might be incorrect. The MMAR is not written.</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MMARVALID</name>
|
|
<description>Memory Manage Address Register (MMAR) address valid flag. A later-arriving fault, such as a bus fault, can clear a memory manage fault.. If a MemManage fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems on return to a stacked active MemManage handler whose MMAR value has been overwritten.</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IBUSERR</name>
|
|
<description>Instruction bus error flag. The IBUSERR flag is set by a prefetch error. The fault stops on the instruction, so if the error occurs under a branch shadow, no fault occurs. The BFAR is not written.</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRECISERR</name>
|
|
<description>Precise data bus error return.</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IMPRECISERR</name>
|
|
<description>Imprecise data bus error. It is a BusFault, but the Return PC is not related to the causing instruction. This is not a synchronous fault. So, if detected when the priority of the current activation is higher than the Bus Fault, it only pends. Bus fault activates when returning to a lower priority activation. If a precise fault occurs before returning to a lower priority exception, the handler detects both IMPRECISERR set and one of the precise fault status bits set at the same time. The BFAR is not written.</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UNSTKERR</name>
|
|
<description>Unstack from exception return has caused one or more bus faults. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. The BFAR is not written.</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STKERR</name>
|
|
<description>Stacking from exception has caused one or more bus faults. The SP is still adjusted and the values in the context area on the stack might be incorrect. The BFAR is not written.</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BFARVALID</name>
|
|
<description>This bit is set if the Bus Fault Address Register (BFAR) contains a valid address. This is true after a bus fault where the address is known. Other faults can clear this bit, such as a Mem Manage fault occurring later. If a Bus fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems if returning to a stacked active Bus fault handler whose BFAR value has been overwritten.</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UNDEFINSTR</name>
|
|
<description>The UNDEFINSTR flag is set when the processor attempts to execute an undefined instruction. This is an instruction that the processor cannot decode. The return PC points to the undefined instruction.</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INVSTATE</name>
|
|
<description>Invalid combination of EPSR and instruction, for reasons other than UNDEFINED instruction. Return PC points to faulting instruction, with the invalid state.</description>
|
|
<bitOffset>0x11</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INVPC</name>
|
|
<description>Attempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid context, invalid value. The return PC points to the instruction that tried to set the PC.</description>
|
|
<bitOffset>0x12</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NOCP</name>
|
|
<description>Attempt to use a coprocessor instruction. The processor does not support coprocessor instructions.</description>
|
|
<bitOffset>0x13</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UNALIGNED</name>
|
|
<description>When UNALIGN_TRP is enabled (see Configuration Control Register on page 8-26), and there is an attempt to make an unaligned memory access, then this fault occurs. Unaligned LDM/STM/LDRD/STRD instructions always fault irrespective of the setting of UNALIGN_TRP.</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIVBYZERO</name>
|
|
<description>When DIV_0_TRP (see Configuration Control Register on page 8-26) is enabled and an SDIV or UDIV instruction is used with a divisor of 0, this fault occurs The instruction is executed and the return PC points to it. If DIV_0_TRP is not set, then the divide returns a quotient of 0.</description>
|
|
<bitOffset>0x19</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MLSPERR</name>
|
|
<description>Indicates if MemManage fault occurred during FP lazy state preservation.</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSPERR</name>
|
|
<description>Indicates if bus fault occurred during FP lazy state preservation.</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HFSR</name>
|
|
<displayName>HFSR</displayName>
|
|
<description>Hard Fault Status Register</description>
|
|
<addressOffset>0xD2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VECTTBL</name>
|
|
<description>This bit is set if there is a fault because of vector table read on exception processing (Bus Fault). This case is always a Hard Fault. The return PC points to the pre-empted instruction.</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FORCED</name>
|
|
<description>Hard Fault activated because a Configurable Fault was received and cannot activate because of priority or because the Configurable Fault is disabled. The Hard Fault handler then has to read the other fault status registers to determine cause.</description>
|
|
<bitOffset>0x1E</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEBUGEVT</name>
|
|
<description>This bit is set if there is a fault related to debug. This is only possible when halting debug is not enabled. For monitor enabled debug, it only happens for BKPT when the current priority is higher than the monitor. When both halting and monitor debug are disabled, it only happens for debug events that are not ignored (minimally, BKPT). The Debug Fault Status Register is updated.</description>
|
|
<bitOffset>0x1F</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFSR</name>
|
|
<displayName>DFSR</displayName>
|
|
<description>Debug Fault Status Register</description>
|
|
<addressOffset>0xD30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HALTED</name>
|
|
<description>Halt request flag. The processor is halted on the next instruction.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>no halt request</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>halt requested by NVIC, including step</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BKPT</name>
|
|
<description>BKPT flag. The BKPT flag is set by a BKPT instruction in flash patch code, and also by normal code. Return PC points to breakpoint containing instruction.</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>no BKPT instruction execution</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>BKPT instruction execution</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DWTTRAP</name>
|
|
<description>Data Watchpoint and Trace (DWT) flag. The processor stops at the current instruction or at the next instruction.</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>no DWT match</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>DWT match</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VCATCH</name>
|
|
<description>Vector catch flag. When the VCATCH flag is set, a flag in one of the local fault status registers is also set to indicate the type of fault.</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>no vector catch occurred</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>vector catch occurred</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTERNAL</name>
|
|
<description>External debug request flag. The processor stops on next instruction boundary.</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>EDBGRQ signal not asserted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>EDBGRQ signal asserted</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MMFAR</name>
|
|
<displayName>MMFAR</displayName>
|
|
<description>Mem Manage Fault Address Register</description>
|
|
<addressOffset>0xD34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>ADDRESS</name>
|
|
<description>Mem Manage fault address field. ADDRESS is the data address of a faulted load or store attempt. When an unaligned access faults, the address is the actual address that faulted. Because an access can be split into multiple parts, each aligned, this address can be any offset in the range of the requested size. Flags in the Memory Manage Fault Status Register indicate the cause of the fault</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BFAR</name>
|
|
<displayName>BFAR</displayName>
|
|
<description>Bus Fault Address Register</description>
|
|
<addressOffset>0xD38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>ADDRESS</name>
|
|
<description>Bus fault address field. ADDRESS is the data address of a faulted load or store attempt. When an unaligned access faults, the address is the address requested by the instruction, even if that is not the address that faulted. Flags in the Bus Fault Status Register indicate the cause of the fault</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AFSR</name>
|
|
<displayName>AFSR</displayName>
|
|
<description>Auxiliary Fault Status Register</description>
|
|
<addressOffset>0xD3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IMPDEF</name>
|
|
<description>Implementation defined. The bits map directly onto the signal assignment to the AUXFAULT inputs.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PFR0</name>
|
|
<displayName>PFR0</displayName>
|
|
<description>Processor Feature register0</description>
|
|
<addressOffset>0xD40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STATE0</name>
|
|
<description>State0 (T-bit == 0)</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>no ARM encoding</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>N/A</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STATE1</name>
|
|
<description>State1 (T-bit == 1)</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>N/A</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>N/A</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0010</name>
|
|
<description>Thumb-2 encoding with the 16-bit basic instructions plus 32-bit Buncond/BL but no other 32-bit basic instructions (Note non-basic 32-bit instructions can be added using the appropriate instruction attribute, but other 32-bit basic instructions cannot.)</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0011</name>
|
|
<description>Thumb-2 encoding with all Thumb-2 basic instructions</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PFR1</name>
|
|
<displayName>PFR1</displayName>
|
|
<description>Processor Feature register1</description>
|
|
<addressOffset>0xD44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000200</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MICROCONTROLLER_PROGRAMMERS_MODEL</name>
|
|
<description>Microcontroller programmer's model</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>not supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0010</name>
|
|
<description>two-stack support</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFR0</name>
|
|
<displayName>DFR0</displayName>
|
|
<description>Debug Feature register0</description>
|
|
<addressOffset>0xD48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00100000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MICROCONTROLLER_DEBUG_MODEL</name>
|
|
<description>Microcontroller Debug Model - memory mapped</description>
|
|
<bitOffset>0x14</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>not supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>Microcontroller debug v1 (ITMv1, DWTv1, optional ETM)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AFR0</name>
|
|
<displayName>AFR0</displayName>
|
|
<description>Auxiliary Feature register0</description>
|
|
<addressOffset>0xD4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>MMFR0</name>
|
|
<displayName>MMFR0</displayName>
|
|
<description>Memory Model Feature register0</description>
|
|
<addressOffset>0xD50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00100030</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PMSA_SUPPORT</name>
|
|
<description>PMSA support</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>not supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>IMPLEMENTATION DEFINED (N/A)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0010</name>
|
|
<description>PMSA base (features as defined for ARMv6) (N/A)</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0011</name>
|
|
<description>PMSAv7 (base plus subregion support)</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CACHE_COHERENCE_SUPPORT</name>
|
|
<description>Cache coherence support</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>no shared support</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>partial-inner-shared coherency (coherency amongst some - but not all - of the entities within an inner-coherent domain)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0010</name>
|
|
<description>full-inner-shared coherency (coherency amongst all of the entities within an inner-coherent domain)</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0011</name>
|
|
<description>full coherency (coherency amongst all of the entities)</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTER_NON_SHARABLE_SUPPORT</name>
|
|
<description>Outer non-sharable support</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>Outer non-sharable not supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>Outer sharable supported</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUXILIARY_REGISTER_SUPPORT</name>
|
|
<description>Auxiliary register support</description>
|
|
<bitOffset>0x14</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>not supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>Auxiliary control register</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MMFR1</name>
|
|
<displayName>MMFR1</displayName>
|
|
<description>Memory Model Feature register1</description>
|
|
<addressOffset>0xD54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>MMFR2</name>
|
|
<displayName>MMFR2</displayName>
|
|
<description>Memory Model Feature register2</description>
|
|
<addressOffset>0xD58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WAIT_FOR_INTERRUPT_STALLING</name>
|
|
<description>wait for interrupt stalling</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>not supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>wait for interrupt supported</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MMFR3</name>
|
|
<displayName>MMFR3</displayName>
|
|
<description>Memory Model Feature register3</description>
|
|
<addressOffset>0xD5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>ISAR0</name>
|
|
<displayName>ISAR0</displayName>
|
|
<description>ISA Feature register0</description>
|
|
<addressOffset>0xD60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x01141110</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BITCOUNT_INSTRS</name>
|
|
<description>BitCount instructions</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>no bit-counting instructions present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>adds CLZ</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BITFIELD_INSTRS</name>
|
|
<description>BitField instructions</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>no bitfield instructions present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>adds BFC, BFI, SBFX, UBFX</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPBRANCH_INSTRS</name>
|
|
<description>CmpBranch instructions</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>no combined compare-and-branch instructions present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>adds CB{N}Z</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COPROC_INSTRS</name>
|
|
<description>Coprocessor instructions</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>no coprocessor support, other than for separately attributed architectures such as CP15 or VFP</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>adds generic CDP, LDC, MCR, MRC, STC</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0010</name>
|
|
<description>adds generic CDP2, LDC2, MCR2, MRC2, STC2</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0011</name>
|
|
<description>adds generic MCRR, MRRC</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0100</name>
|
|
<description>adds generic MCRR2, MRRC2</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DEBUG_INSTRS</name>
|
|
<description>Debug instructions</description>
|
|
<bitOffset>0x14</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>no debug instructions present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>adds BKPT</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIVIDE_INSTRS</name>
|
|
<description>Divide instructions</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>no divide instructions present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>adds SDIV, UDIV (v1 quotient only result)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISAR1</name>
|
|
<displayName>ISAR1</displayName>
|
|
<description>ISA Feature register1</description>
|
|
<addressOffset>0xD64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x02112000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EXTEND_INSRS</name>
|
|
<description>Extend instructions. Note that the shift options on these instructions are also controlled by the WithShifts_instrs attribute.</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>no scalar (i.e. non-SIMD) sign/zero-extend instructions present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>adds SXTB, SXTH, UXTB, UXTH</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0010</name>
|
|
<description>N/A</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IFTHEN_INSTRS</name>
|
|
<description>IfThen instructions</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>IT instructions not present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>adds IT instructions (and IT bits in PSRs)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IMMEDIATE_INSTRS</name>
|
|
<description>Immediate instructions</description>
|
|
<bitOffset>0x14</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>no special immediate-generating instructions present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>adds ADDW, MOVW, MOVT, SUBW</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTERWORK_INSTRS</name>
|
|
<description>Interwork instructions</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>no interworking instructions supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>adds BX (and T bit in PSRs)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0010</name>
|
|
<description>adds BLX, and PC loads have BX-like behavior</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0011</name>
|
|
<description>N/A</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISAR2</name>
|
|
<displayName>ISAR2</displayName>
|
|
<description>ISA Feature register2</description>
|
|
<addressOffset>0xD68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x21232231</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LOADSTORE_INSTRS</name>
|
|
<description>LoadStore instructions</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>no additional normal load/store instructions present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>adds LDRD/STRD</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MEMHINT_INSTRS</name>
|
|
<description>MemoryHint instructions</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>no memory hint instructions presen</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>adds PLD</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0010</name>
|
|
<description>adds PLD (ie a repeat on value 1)</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0011</name>
|
|
<description>adds PLI</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MULTIACCESSINT_INSTRS</name>
|
|
<description>Multi-Access interruptible instructions</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>the (LDM/STM) instructions are non-interruptible</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>the (LDM/STM) instructions are restartable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0010</name>
|
|
<description>the (LDM/STM) instructions are continuable</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MULT_INSTRS</name>
|
|
<description>Multiply instructions</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>only MUL present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>adds MLA</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0010</name>
|
|
<description>adds MLS</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MULTS_INSTRS</name>
|
|
<description>Multiply instructions (advanced, signed)</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>no signed multiply instructions present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>adds SMULL, SMLAL</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0010</name>
|
|
<description>N/A</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0011</name>
|
|
<description>N/A</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MULTU_INSTRS</name>
|
|
<description>Multiply instructions (advanced, unsigned)</description>
|
|
<bitOffset>0x14</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>no unsigned multiply instructions present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>adds UMULL, UMLAL</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0010</name>
|
|
<description>N/A</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REVERSAL_INSTRS</name>
|
|
<description>Reversal instructions</description>
|
|
<bitOffset>0x1C</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>no reversal instructions present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>adds REV, REV16, REVSH</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0010</name>
|
|
<description>adds RBIT</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISAR3</name>
|
|
<displayName>ISAR3</displayName>
|
|
<description>ISA Feature register3</description>
|
|
<addressOffset>0xD6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x01111131</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SATRUATE_INSTRS</name>
|
|
<description>Saturate instructions</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>no non-SIMD saturate instructions present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>N/A</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SIMD_INSTRS</name>
|
|
<description>SIMD instructions</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>no SIMD instructions present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>adds SSAT, USAT (and the Q flag in the PSRs)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0011</name>
|
|
<description>N/A</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SVC_INSTRS</name>
|
|
<description>SVC instructions</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>no SVC (SWI) instructions present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>adds SVC (SWI)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCPRIM_INSTRS</name>
|
|
<description>SyncPrim instructions. Note there are no LDREXD or STREXD in ARMv7-M. This attribute is used in conjunction with the SyncPrim_instrs_frac attribute in ID_ISAR4[23:20].</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>no synchronization primitives present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>adds LDREX, STREX</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0010</name>
|
|
<description>adds LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, CLREX(N/A)</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TABBRANCH_INSTRS</name>
|
|
<description>TableBranch instructions</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>no table-branch instructions present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>adds TBB, TBH</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>THUMBCOPY_INSTRS</name>
|
|
<description>ThumbCopy instructions</description>
|
|
<bitOffset>0x14</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>Thumb MOV(register) instruction does not allow low reg -> low reg</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>adds Thumb MOV(register) low reg -> low reg and the CPY alias</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRUENOP_INSTRS</name>
|
|
<description>TrueNOP instructions</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>true NOP instructions not present - that is, NOP instructions with no register dependencies</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>adds "true NOP", and the capability of additional "NOP compatible hints"</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISAR4</name>
|
|
<displayName>ISAR4</displayName>
|
|
<description>ISA Feature register4</description>
|
|
<addressOffset>0xD70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x01310102</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UNPRIV_INSTRS</name>
|
|
<description>Unprivileged instructions</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>no "T variant" instructions exist</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>adds LDRBT, LDRT, STRBT, STRT</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0010</name>
|
|
<description>adds LDRHT, LDRSBT, LDRSHT, STRHT</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WITHSHIFTS_INSTRS</name>
|
|
<description>WithShift instructions. Note that all additions only apply in cases where the encoding supports them - e.g. there is no difference between levels 3 and 4 in the Thumb-2 instruction set. Also note that MOV instructions with shift options should instead be treated as ASR, LSL, LSR, ROR or RRX instructions.</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>non-zero shifts only support MOV and shift instructions (see notes)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>shifts of loads/stores over the range LSL 0-3</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0010</name>
|
|
<description>adds other constant shift options.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0100</name>
|
|
<description>adds register-controlled shift options.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WRITEBACK_INSTRS</name>
|
|
<description>Writeback instructions</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>only non-writeback addressing modes present, except that LDMIA/STMDB/PUSH/POP instructions support writeback addressing.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>adds all currently-defined writeback addressing modes (ARMv7, Thumb-2)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BARRIER_INSTRS</name>
|
|
<description>Barrier instructions</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>no barrier instructions supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>adds DMB, DSB, ISB barrier instructions</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCPRIM_INSTRS_FRAC</name>
|
|
<description>SyncPrim_instrs_frac</description>
|
|
<bitOffset>0x14</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>no additional support</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0011</name>
|
|
<description>adds CLREX, LDREXB, STREXB, LDREXH, STREXH</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSR_M_INSTRS</name>
|
|
<description>PSR_M_instrs</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0000</name>
|
|
<description>instructions not present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b0001</name>
|
|
<description>adds CPS, MRS, and MSR instructions (M-profile forms)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPACR</name>
|
|
<displayName>CPACR</displayName>
|
|
<description>Coprocessor Access Control Register</description>
|
|
<addressOffset>0xD88</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>CP11</name>
|
|
<description>Access privileges for coprocessor 11. The possible values of each field are: 0b00 = Access denied. Any attempted access generates a NOCP UsageFault. 0b01 = Privileged access only. An unprivileged access generates a NOCP UsageFault. 0b10 = Reserved. 0b11 = Full access. Used in conjunction with the control for CP10, this controls access to the Floating Point Coprocessor.</description>
|
|
<bitOffset>0x16</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CP10</name>
|
|
<description>Access privileges for coprocessor 10. The possible values of each field are: 0b00 = Access denied. Any attempted access generates a NOCP UsageFault. 0b01 = Privileged access only. An unprivileged access generates a NOCP UsageFault. 0b10 = Reserved. 0b11 = Full access. Used in conjunction with the control for CP11, this controls access to the Floating Point Coprocessor.</description>
|
|
<bitOffset>0x14</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>FPCCR</name>
|
|
<displayName>FPCCR</displayName>
|
|
<description>Floating Point Context Control Register</description>
|
|
<addressOffset>0xF34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xc0000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ASPEN</name>
|
|
<description>Automatic State Preservation ENable. When this bit is set is will cause bit [2] of the Special CONTROL register to be set (FPCA) on execution of a floating point instruction which results in the floating point state automatically being preserved on exception entry.</description>
|
|
<bitOffset>0x1F</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSPEN</name>
|
|
<description>Lazy State Preservation ENable. When the processor performs a context save, space on the stack is reserved for the floating point state but it is not stacked until the new context performs a floating point operation.</description>
|
|
<bitOffset>0x1E</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MONRDY</name>
|
|
<description>Indicates whether the the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending.</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BFRDY</name>
|
|
<description>Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending.</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MMRDY</name>
|
|
<description>Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending.</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HFRDY</name>
|
|
<description>Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending.</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>THREAD</name>
|
|
<description>Indicates the processor mode was Thread when it allocated the FP stack frame.</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USER</name>
|
|
<description>Indicates the privilege level of the software executing was User (Unpriviledged) when the processor allocated the FP stack frame.</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSPACT</name>
|
|
<description>Indicates whether Lazy preservation of the FP state is active.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FPCAR</name>
|
|
<displayName>FPCAR</displayName>
|
|
<description>Floating-Point Context Address Register</description>
|
|
<addressOffset>0xF38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDRESS</name>
|
|
<description>Holds the (double-word-aligned) location of the unpopulated floating-point register space allocated on an exception stack frame.</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1D</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FPDSCR</name>
|
|
<displayName>FPDSCR</displayName>
|
|
<description>Floating Point Default Status Control Register</description>
|
|
<addressOffset>0xF3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AHP</name>
|
|
<description>Default value for Alternative Half Precision bit. (If this bit is set to 1 then Alternative half-precision format is selected).</description>
|
|
<bitOffset>0x1A</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DN</name>
|
|
<description>Default value for Default NaN mode bit. (If this bit is set to 1 then any operation involving one or more NaNs returns the Default NaN).</description>
|
|
<bitOffset>0x19</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FZ</name>
|
|
<description>Default value for Flush-to-Zero mode bit. (If this bit is set to 1 then Flush-to-zero mode is enabled).</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RMODE</name>
|
|
<description>Default value for Rounding Mode control field. (The encoding for this field is: 0b00 Round to Nearest (RN) mode, 0b01 Round towards Plus Infinity (RP) mode, 0b10 Round towards Minus Infinity (RM) mode, 0b11 Round towards Zero (RZ) mode. The specified rounding mode is used by almost all floating-point instructions).</description>
|
|
<bitOffset>0x16</bitOffset>
|
|
<bitWidth>0x2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MVFR0</name>
|
|
<displayName>MVFR0</displayName>
|
|
<description>Media and FP Feature Register 0 (MVFR0)</description>
|
|
<addressOffset>0xF40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x10110021</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FP_ROUNDING_MODES</name>
|
|
<description>Indicates the rounding modes supported by the FP floating-point hardware. The value of this field is: 0b0001 - all rounding modes supported.</description>
|
|
<bitOffset>0x1C</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SHORT_VECTORS</name>
|
|
<description>Indicates the hardware support for FP short vectors. The value of this field is: 0b0000 - not supported in ARMv7-M.</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SQUARE_ROOT</name>
|
|
<description>Indicates the hardware support for FP square root operations. The value of this field is: 0b0001 - supported.</description>
|
|
<bitOffset>0x14</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DIVIDE</name>
|
|
<description>Indicates the hardware support for FP divide operations. The value of this field is: 0b0001 - supported.</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FP_EXCEPTION_TRAPPING</name>
|
|
<description>Indicates whether the FP hardware implementation supports exception trapping. The value of this field is: 0b0000 - not supported in ARMv7-M.</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DOUBLE_PRECISION</name>
|
|
<description>Indicates the hardware support for FP double-precision operations. The value of this field is: 0b0000 - not supported in ARMv7-M.</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SINGLE_PRECISION</name>
|
|
<description>Indicates the hardware support for FP single-precision operations. The value of this field is: 0b0010 - supported.</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>A_SIMD_REGISTERS</name>
|
|
<description>Indicates the size of the FP register bank. The value of this field is: 0b0001 - supported, 16 x 64-bit registers.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MVFR1</name>
|
|
<displayName>MVFR1</displayName>
|
|
<description>Media and FP Feature Register 1 (MVFR1)</description>
|
|
<addressOffset>0xF44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x11000011</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FP_FUSED_MAC</name>
|
|
<description>Indicates whether the FP supports fused multiply accumulate operations. The value of this field is: 0b0001 - supported.</description>
|
|
<bitOffset>0x1C</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FP_HPFP</name>
|
|
<description>Indicates whether the FP supports half-precision floating-point conversion operations. The value of this field is: 0b0001 - supported.</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>D_NAN_MODE</name>
|
|
<description>Indicates whether the FP hardware implementation supports only the Default NaN mode. The value of this field is: 0b0001 - hardware supports propagation of NaN values.</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FTZ_MODE</name>
|
|
<description>Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation. The value of this field is: 0b0001 - hardware supports full denormalized number arithmetic.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>MPU_TYPE</name>
|
|
<displayName>TYPE</displayName>
|
|
<description>MPU Type Register</description>
|
|
<addressOffset>0xD90</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000800</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SEPARATE</name>
|
|
<description>Because the processor core uses only a unified MPU, SEPARATE is always 0.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DREGION</name>
|
|
<description>Number of supported MPU regions field. DREGION contains 0x08 if the implementation contains an MPU indicating eight MPU regions, otherwise it contains 0x00.</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IREGION</name>
|
|
<description>Because the processor core uses only a unified MPU, IREGION always contains 0x00.</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MPU_CTRL</name>
|
|
<displayName>CTRL</displayName>
|
|
<description>MPU Control Register</description>
|
|
<addressOffset>0xD94</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>MPU enable bit. Reset clears the ENABLE bit.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>disable MPU</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>enable MPU</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HFNMIENA</name>
|
|
<description>This bit enables the MPU when in Hard Fault, NMI, and FAULTMASK escalated handlers. If this bit = 1 and the ENABLE bit = 1, the MPU is enabled when in these handlers. If this bit = 0, the MPU is disabled when in these handlers, regardless of the value of ENABLE. If this bit =1 and ENABLE = 0, behavior is Unpredictable. Reset clears the HFNMIENA bit.</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRIVDEFENA</name>
|
|
<description>This bit enables the default memory map for privileged access, as a background region, when the MPU is enabled. The background region acts as if it was region number 1 before any settable regions. Any region that is set up overlays this default map, and overrides it. If this bit = 0, the default memory map is disabled, and memory not covered by a region faults. This applies to memory type, Execute Never (XN), cache and shareable rules. However, this only applies to privileged mode (fetch and data access). User mode code faults unless a region has been set up for its code and data. When the MPU is disabled, the default map acts on both privileged and user mode code. XN and SO rules always apply to the System partition whether this enable is set or not. If the MPU is disabled, this bit is ignored. Reset clears the PRIVDEFENA bit.</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MPU_RNR</name>
|
|
<displayName>RNR</displayName>
|
|
<description>MPU Region Number Register</description>
|
|
<addressOffset>0xD98</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>REGION</name>
|
|
<description>Region select field. Selects the region to operate on when using the Region Attribute and Size Register and the Region Base Address Register. It must be written first except when the address VALID + REGION fields are written, which overwrites this.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MPU_RBAR</name>
|
|
<displayName>RBAR</displayName>
|
|
<description>MPU Region Base Address Register</description>
|
|
<addressOffset>0xD9C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REGION</name>
|
|
<description>MPU region override field.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VALID</name>
|
|
<description>MPU Region Number valid bit.</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>MPU Region Number Register remains unchanged and is interpreted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>MPU Region Number Register is overwritten by bits 3:0 (the REGION value).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Region base address field. The position of the LSB depends on the region size, so that the base address is aligned according to an even multiple of size. The power of 2 size specified by the SZENABLE field of the MPU Region Attribute and Size Register defines how many bits of base address are used.</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1B</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MPU_RASR</name>
|
|
<displayName>RASR</displayName>
|
|
<description>MPU Region Attribute and Size Register</description>
|
|
<addressOffset>0xDA0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Region enable bit.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SIZE</name>
|
|
<description>MPU Protection Region Size Field.</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b00100</name>
|
|
<description>32B</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b00101</name>
|
|
<description>64B</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b00110</name>
|
|
<description>128B</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b00111</name>
|
|
<description>256B</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b01000</name>
|
|
<description>512B</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b01001</name>
|
|
<description>1KB</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b01010</name>
|
|
<description>2KB</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b01011</name>
|
|
<description>4KB</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b01100</name>
|
|
<description>8KB</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b01101</name>
|
|
<description>16KB</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b01110</name>
|
|
<description>32KB</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b01111</name>
|
|
<description>64KB</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b10000</name>
|
|
<description>128KB</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b10001</name>
|
|
<description>256KB</description>
|
|
<value>17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b10010</name>
|
|
<description>512KB</description>
|
|
<value>18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b10011</name>
|
|
<description>1MB</description>
|
|
<value>19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b10100</name>
|
|
<description>2MB</description>
|
|
<value>20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b10101</name>
|
|
<description>4MB</description>
|
|
<value>21</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b10110</name>
|
|
<description>8MB</description>
|
|
<value>22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b10111</name>
|
|
<description>16MB</description>
|
|
<value>23</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b11000</name>
|
|
<description>32MB</description>
|
|
<value>24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b11001</name>
|
|
<description>64MB</description>
|
|
<value>25</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b11010</name>
|
|
<description>128MB</description>
|
|
<value>26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b11011</name>
|
|
<description>256MB</description>
|
|
<value>27</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b11100</name>
|
|
<description>512MB</description>
|
|
<value>28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b11101</name>
|
|
<description>1GB</description>
|
|
<value>29</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b11110</name>
|
|
<description>2GB</description>
|
|
<value>30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b11111</name>
|
|
<description>4GB</description>
|
|
<value>31</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRD</name>
|
|
<description>Sub-Region Disable (SRD) field. Setting an SRD bit disables the corresponding sub-region. Regions are split into eight equal-sized sub-regions. Sub-regions are not supported for region sizes of 128 bytes and less.</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B</name>
|
|
<description>Bufferable bit</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>not bufferable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>bufferable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>C</name>
|
|
<description>Cacheable bit</description>
|
|
<bitOffset>0x11</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>not cacheable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>cacheable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>S</name>
|
|
<description>Shareable bit</description>
|
|
<bitOffset>0x12</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>not shareable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>shareable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEX</name>
|
|
<description>Type extension field</description>
|
|
<bitOffset>0x13</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AP</name>
|
|
<description>Data access permission field</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b000</name>
|
|
<description>Priviliged permissions: No access. User permissions: No access.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b001</name>
|
|
<description>Priviliged permissions: Read-write. User permissions: No access.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b010</name>
|
|
<description>Priviliged permissions: Read-write. User permissions: Read-only.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b011</name>
|
|
<description>Priviliged permissions: Read-write. User permissions: Read-write.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b101</name>
|
|
<description>Priviliged permissions: Read-only. User permissions: No access.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b110</name>
|
|
<description>Priviliged permissions: Read-only. User permissions: Read-only.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b111</name>
|
|
<description>Priviliged permissions: Read-only. User permissions: Read-only.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XN</name>
|
|
<description>Instruction access disable bit</description>
|
|
<bitOffset>0x1C</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>enable instruction fetches</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>disable instruction fetches</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MPU_RBAR_A1</name>
|
|
<displayName>RBAR_A1</displayName>
|
|
<description>MPU Alias 1 Region Base Address register</description>
|
|
<addressOffset>0xDA4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>MPU_RASR_A1</name>
|
|
<displayName>RASR_A1</displayName>
|
|
<description>MPU Alias 1 Region Attribute and Size register</description>
|
|
<addressOffset>0xDA8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>MPU_RBAR_A2</name>
|
|
<displayName>RBAR_A2</displayName>
|
|
<description>MPU Alias 2 Region Base Address register</description>
|
|
<addressOffset>0xDAC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>MPU_RASR_A2</name>
|
|
<displayName>RASR_A2</displayName>
|
|
<description>MPU Alias 2 Region Attribute and Size register</description>
|
|
<addressOffset>0xDB0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>MPU_RBAR_A3</name>
|
|
<displayName>RBAR_A3</displayName>
|
|
<description>MPU Alias 3 Region Base Address register</description>
|
|
<addressOffset>0xDB4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>MPU_RASR_A3</name>
|
|
<displayName>RASR_A3</displayName>
|
|
<description>MPU Alias 3 Region Attribute and Size register</description>
|
|
<addressOffset>0xDB8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
</registers>
|
|
<interrupt>
|
|
<name>FPU_IRQ</name>
|
|
<description>FPU Interrupt</description>
|
|
<value>4</value>
|
|
</interrupt>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DHCSR</name>
|
|
<displayName>DHCSR</displayName>
|
|
<description>Debug Halting Control and Status Register</description>
|
|
<addressOffset>0xDF0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xfffeffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>C_DEBUGEN</name>
|
|
<description>Enables debug. This can only be written by AHB-AP and not by the core. It is ignored when written by the core, which cannot set or clear it. The core must write a 1 to it when writing C_HALT to halt itself.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>C_HALT</name>
|
|
<description>Halts the core. This bit is set automatically when the core Halts. For example Breakpoint. This bit clears on core reset. This bit can only be written if C_DEBUGEN is 1, otherwise it is ignored. When setting this bit to 1, C_DEBUGEN must also be written to 1 in the same value (value[1:0] is 2'b11). The core can halt itself, but only if C_DEBUGEN is already 1 and only if it writes with b11).</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>C_STEP</name>
|
|
<description>Steps the core in halted debug. When C_DEBUGEN = 0, this bit has no effect. Must only be modified when the processor is halted (S_HALT == 1).</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>C_MASKINTS</name>
|
|
<description>Mask interrupts when stepping or running in halted debug. Does not affect NMI, which is not maskable. Must only be modified when the processor is halted (S_HALT == 1). Also does not affect fault exceptions and SVC caused by execution of the instructions. CMASKINTS must be set or cleared before halt is released. This means that the writes to set or clear C_MASKINTS and to set or clear C_HALT must be separate.</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>C_SNAPSTALL</name>
|
|
<description>If the core is stalled on a load/store operation the stall ceases and the instruction is forced to complete. This enables Halting debug to gain control of the core. It can only be set if: C_DEBUGEN = 1 and C_HALT = 1. The core reads S_RETIRE_ST as 0. This indicates that no instruction has advanced. This prevents misuse. The bus state is Unpredictable when this is used. S_RETIRE can detect core stalls on load/store operations.</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>S_REGRDY</name>
|
|
<description>Register Read/Write on the Debug Core Register Selector register is available. Last transfer is complete.</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>S_HALT</name>
|
|
<description>The core is in debug state when S_HALT is set.</description>
|
|
<bitOffset>0x11</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>S_SLEEP</name>
|
|
<description>Indicates that the core is sleeping (WFI, WFE, or SLEEP-ON-EXIT). Must use C_HALT to gain control or wait for interrupt to wake-up.</description>
|
|
<bitOffset>0x12</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>S_LOCKUP</name>
|
|
<description>Reads as one if the core is running (not halted) and a lockup condition is present.</description>
|
|
<bitOffset>0x13</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>S_RETIRE_ST</name>
|
|
<description>Indicates that an instruction has completed since last read. This is a sticky bit that clears on read. This determines if the core is stalled on a load/store or fetch.</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>S_RESET_ST</name>
|
|
<description>Indicates that the core has been reset, or is now being reset, since the last time this bit was read. This a sticky bit that clears on read. So, reading twice and getting 1 then 0 means it was reset in the past. Reading twice and getting 1 both times means that it is being reset now (held in reset still).</description>
|
|
<bitOffset>0x19</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCRSR</name>
|
|
<displayName>DCRSR</displayName>
|
|
<description>Deubg Core Register Selector Register</description>
|
|
<addressOffset>0xDF4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>REGSEL</name>
|
|
<description>Register select</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x5</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b00000</name>
|
|
<description>R0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b00001</name>
|
|
<description>R1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b00010</name>
|
|
<description>R2</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b00011</name>
|
|
<description>R3</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b00100</name>
|
|
<description>R4</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b00101</name>
|
|
<description>R5</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b00110</name>
|
|
<description>R6</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b00111</name>
|
|
<description>R7</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b01000</name>
|
|
<description>R8</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b01001</name>
|
|
<description>R9</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b01010</name>
|
|
<description>R10</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b01011</name>
|
|
<description>R11</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b01100</name>
|
|
<description>R12</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b01101</name>
|
|
<description>Current SP</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b01110</name>
|
|
<description>LR</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b01111</name>
|
|
<description>DebugReturnAddress</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b10000</name>
|
|
<description>xPSR/flags, execution state information, and exception number</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b10001</name>
|
|
<description>MSP (Main SP)</description>
|
|
<value>17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b10010</name>
|
|
<description>PSP (Process SP)</description>
|
|
<value>18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b10100</name>
|
|
<description>CONTROL bits [31:24], FAULTMASK bits [23:16], BASEPRI bits [15:8], PRIMASK bits [7:0]</description>
|
|
<value>20</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REGWNR</name>
|
|
<description>Write = 1, Read = 0</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCRDR</name>
|
|
<displayName>DCRDR</displayName>
|
|
<description>Debug Core Register Data Register</description>
|
|
<addressOffset>0xDF8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
</register>
|
|
<register>
|
|
<name>DEMCR</name>
|
|
<displayName>DEMCR</displayName>
|
|
<description>Debug Exception and Monitor Control Register</description>
|
|
<addressOffset>0xDFC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VC_CORERESET</name>
|
|
<description>Reset Vector Catch. Halt running system if Core reset occurs.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VC_MMERR</name>
|
|
<description>Debug trap on Memory Management faults.</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VC_NOCPERR</name>
|
|
<description>Debug trap on Usage Fault access to Coprocessor that is not present or marked as not present in CAR register.</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VC_CHKERR</name>
|
|
<description>Debug trap on Usage Fault enabled checking errors.</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VC_STATERR</name>
|
|
<description>Debug trap on Usage Fault state errors.</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VC_BUSERR</name>
|
|
<description>Debug Trap on normal Bus error.</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VC_INTERR</name>
|
|
<description>Debug Trap on interrupt/exception service errors. These are a subset of other faults and catches before BUSERR or HARDERR.</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VC_HARDERR</name>
|
|
<description>Debug trap on Hard Fault.</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MON_EN</name>
|
|
<description>Enable the debug monitor. When enabled, the System handler priority register controls its priority level. If disabled, then all debug events go to Hard fault. C_DEBUGEN in the Debug Halting Control and Statue register overrides this bit. Vector catching is semi-synchronous. When a matching event is seen, a Halt is requested. Because the processor can only halt on an instruction boundary, it must wait until the next instruction boundary. As a result, it stops on the first instruction of the exception handler. However, two special cases exist when a vector catch has triggered: 1. If a fault is taken during vectoring, vector read or stack push error, the halt occurs on the corresponding fault handler, for the vector error or stack push. 2. If a late arriving interrupt comes in during vectoring, it is not taken. That is, an implementation that supports the late arrival optimization must suppress it in this case.</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MON_PEND</name>
|
|
<description>Pend the monitor to activate when priority permits. This can wake up the monitor through the AHB-AP port. It is the equivalent to C_HALT for Monitor debug. This register does not reset on a system reset. It is only reset by a POR reset. Software in the reset handler or later, or by the DAP must enable the debug monitor.</description>
|
|
<bitOffset>0x11</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MON_STEP</name>
|
|
<description>When MON_EN = 1, this steps the core. When MON_EN = 0, this bit is ignored. This is the equivalent to C_STEP. Interrupts are only stepped according to the priority of the monitor and settings of PRIMASK, FAULTMASK, or BASEPRI.</description>
|
|
<bitOffset>0x12</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MON_REQ</name>
|
|
<description>This enables the monitor to identify how it wakes up. This bit clears on a Core Reset.</description>
|
|
<bitOffset>0x13</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>en_0b0</name>
|
|
<description>woken up by debug exception.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>en_0b1</name>
|
|
<description>woken up by MON_PEND</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRCENA</name>
|
|
<description>This bit must be set to 1 to enable use of the trace and debug blocks: Data Watchpoint and Trace (DWT), Instrumentation Trace Macrocell (ITM), Embedded Trace Macrocell (ETM), Trace Port Interface Unit (TPIU). This enables control of power usage unless tracing is required. The application can enable this, for ITM use, or use by a debugger. Note that if no debug or trace components are present in the implementation then it is not possible to set TRCENA.</description>
|
|
<bitOffset>0x18</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RSTCTL</name>
|
|
<version>356.0</version>
|
|
<description>RSTCTL</description>
|
|
<baseAddress>0xE0042000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x128</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>RSTCTL_RESET_REQ</name>
|
|
<displayName>RESET_REQ</displayName>
|
|
<description>Reset Request Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffff00fc</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOFT_REQ</name>
|
|
<description>Soft Reset request</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HARD_REQ</name>
|
|
<description>Hard Reset request</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTKEY</name>
|
|
<description>Write key to unlock reset request bits</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTCTL_HARDRESET_STAT</name>
|
|
<displayName>HARDRESET_STAT</displayName>
|
|
<description>Hard Reset Status Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRC0</name>
|
|
<description>Indicates that SRC0 was the source of the Hard Reset</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC1</name>
|
|
<description>Indicates that SRC1 was the source of the Hard Reset</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC2</name>
|
|
<description>Indicates that SRC2 was the source of the Hard Reset</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC3</name>
|
|
<description>Indicates that SRC3 was the source of the Hard Reset</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC4</name>
|
|
<description>Indicates that SRC4 was the source of the Hard Reset</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC5</name>
|
|
<description>Indicates that SRC5 was the source of the Hard Reset</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC6</name>
|
|
<description>Indicates that SRC6 was the source of the Hard Reset</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC7</name>
|
|
<description>Indicates that SRC7 was the source of the Hard Reset</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC8</name>
|
|
<description>Indicates that SRC8 was the source of the Hard Reset</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC9</name>
|
|
<description>Indicates that SRC9 was the source of the Hard Reset</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC10</name>
|
|
<description>Indicates that SRC10 was the source of the Hard Reset</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC11</name>
|
|
<description>Indicates that SRC11 was the source of the Hard Reset</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC12</name>
|
|
<description>Indicates that SRC12 was the source of the Hard Reset</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC13</name>
|
|
<description>Indicates that SRC13 was the source of the Hard Reset</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC14</name>
|
|
<description>Indicates that SRC14 was the source of the Hard Reset</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC15</name>
|
|
<description>Indicates that SRC15 was the source of the Hard Reset</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTCTL_HARDRESET_CLR</name>
|
|
<displayName>HARDRESET_CLR</displayName>
|
|
<description>Hard Reset Status Clear Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffff0000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRC0</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC1</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC2</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC3</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC4</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC5</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC6</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC7</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC8</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC9</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC10</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC11</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC12</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC13</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC14</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC15</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_HRDRESETSTAT_REG</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTCTL_HARDRESET_SET</name>
|
|
<displayName>HARDRESET_SET</displayName>
|
|
<description>Hard Reset Status Set Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRC0</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC1</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC2</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC3</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC4</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC5</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC6</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC7</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC8</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC9</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC10</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC11</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC12</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC13</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC14</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC15</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset)</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTCTL_SOFTRESET_STAT</name>
|
|
<displayName>SOFTRESET_STAT</displayName>
|
|
<description>Soft Reset Status Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRC0</name>
|
|
<description>If 1, indicates that SRC0 was the source of the Soft Reset</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC1</name>
|
|
<description>If 1, indicates that SRC1 was the source of the Soft Reset</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC2</name>
|
|
<description>If 1, indicates that SRC2 was the source of the Soft Reset</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC3</name>
|
|
<description>If 1, indicates that SRC3 was the source of the Soft Reset</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC4</name>
|
|
<description>If 1, indicates that SRC4 was the source of the Soft Reset</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC5</name>
|
|
<description>If 1, indicates that SRC5 was the source of the Soft Reset</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC6</name>
|
|
<description>If 1, indicates that SRC6 was the source of the Soft Reset</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC7</name>
|
|
<description>If 1, indicates that SRC7 was the source of the Soft Reset</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC8</name>
|
|
<description>If 1, indicates that SRC8 was the source of the Soft Reset</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC9</name>
|
|
<description>If 1, indicates that SRC9 was the source of the Soft Reset</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC10</name>
|
|
<description>If 1, indicates that SRC10 was the source of the Soft Reset</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC11</name>
|
|
<description>If 1, indicates that SRC11 was the source of the Soft Reset</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC12</name>
|
|
<description>If 1, indicates that SRC12 was the source of the Soft Reset</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC13</name>
|
|
<description>If 1, indicates that SRC13 was the source of the Soft Reset</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC14</name>
|
|
<description>If 1, indicates that SRC14 was the source of the Soft Reset</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC15</name>
|
|
<description>If 1, indicates that SRC15 was the source of the Soft Reset</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTCTL_SOFTRESET_CLR</name>
|
|
<displayName>SOFTRESET_CLR</displayName>
|
|
<description>Soft Reset Status Clear Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRC0</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC1</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC2</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC3</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC4</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC5</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC6</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC7</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC8</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC9</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC10</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC11</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC12</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC13</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC14</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC15</name>
|
|
<description>Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTCTL_SOFTRESET_SET</name>
|
|
<displayName>SOFTRESET_SET</displayName>
|
|
<description>Soft Reset Status Set Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRC0</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC1</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC2</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC3</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC4</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC5</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC6</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC7</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC8</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC9</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC10</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC11</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC12</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC13</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC14</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRC15</name>
|
|
<description>Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset)</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTCTL_PSSRESET_STAT</name>
|
|
<displayName>PSSRESET_STAT</displayName>
|
|
<description>PSS Reset Status Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000000f</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SVSMH</name>
|
|
<description>Indicates if POR was caused by an SVSMH trip condition int the PSS</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BGREF</name>
|
|
<description>Indicates if POR was caused by a BGREF not okay condition in the PSS</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>VCCDET</name>
|
|
<description>Indicates if POR was caused by a VCCDET trip condition in the PSS</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SVSL</name>
|
|
<description>Indicates if POR was caused by an SVSL trip condition in the PSS</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTCTL_PSSRESET_CLR</name>
|
|
<displayName>PSSRESET_CLR</displayName>
|
|
<description>PSS Reset Status Clear Register</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLR</name>
|
|
<description>Write 1 clears all PSS Reset Flags in the RSTCTL_PSSRESET_STAT</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTCTL_PCMRESET_STAT</name>
|
|
<displayName>PCMRESET_STAT</displayName>
|
|
<description>PCM Reset Status Register</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LPM35</name>
|
|
<description>Indicates if POR was caused by PCM due to an exit from LPM3.5</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LPM45</name>
|
|
<description>Indicates if POR was caused by PCM due to an exit from LPM4.5</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTCTL_PCMRESET_CLR</name>
|
|
<displayName>PCMRESET_CLR</displayName>
|
|
<description>PCM Reset Status Clear Register</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLR</name>
|
|
<description>Write 1 clears all PCM Reset Flags in the RSTCTL_PCMRESET_STAT</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTCTL_PINRESET_STAT</name>
|
|
<displayName>PINRESET_STAT</displayName>
|
|
<description>Pin Reset Status Register</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RSTNMI</name>
|
|
<description>POR was caused by RSTn/NMI pin based reset event</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTCTL_PINRESET_CLR</name>
|
|
<displayName>PINRESET_CLR</displayName>
|
|
<description>Pin Reset Status Clear Register</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLR</name>
|
|
<description>Write 1 clears the RSTn/NMI Pin Reset Flag in RSTCTL_PINRESET_STAT</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTCTL_REBOOTRESET_STAT</name>
|
|
<displayName>REBOOTRESET_STAT</displayName>
|
|
<description>Reboot Reset Status Register</description>
|
|
<addressOffset>0x118</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REBOOT</name>
|
|
<description>Indicates if Reboot reset was caused by the SYSCTL module.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTCTL_REBOOTRESET_CLR</name>
|
|
<displayName>REBOOTRESET_CLR</displayName>
|
|
<description>Reboot Reset Status Clear Register</description>
|
|
<addressOffset>0x11C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLR</name>
|
|
<description>Write 1 clears the Reboot Reset Flag in RSTCTL_REBOOTRESET_STAT</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTCTL_CSRESET_STAT</name>
|
|
<displayName>CSRESET_STAT</displayName>
|
|
<description>CS Reset Status Register</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DCOR_SHT</name>
|
|
<description>Indicates if POR was caused by DCO short circuit fault in the external resistor mode</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTCTL_CSRESET_CLR</name>
|
|
<displayName>CSRESET_CLR</displayName>
|
|
<description>CS Reset Status Clear Register</description>
|
|
<addressOffset>0x124</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLR</name>
|
|
<description>Write 1 clears the DCOR_SHT Flag in RSTCTL_CSRESET_STAT as well as DCOR_SHTIFG flag in CSIFG register of clock system</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SYSCTL</name>
|
|
<version>356.0</version>
|
|
<description>SYSCTL</description>
|
|
<baseAddress>0xE0043000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1028</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>SYS_REBOOT_CTL</name>
|
|
<displayName>REBOOT_CTL</displayName>
|
|
<description>Reboot Control Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000000fe</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REBOOT</name>
|
|
<description>Write 1 initiates a Reboot of the device</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WKEY</name>
|
|
<description>Key to enable writes to bit 0</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYS_NMI_CTLSTAT</name>
|
|
<displayName>NMI_CTLSTAT</displayName>
|
|
<description>NMI Control and Status Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000007</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CS_SRC</name>
|
|
<description>CS interrupt as a source of NMI</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CS_SRC_0</name>
|
|
<description>Disables CS interrupt as a source of NMI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CS_SRC_1</name>
|
|
<description>Enables CS interrupt as a source of NMI</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSS_SRC</name>
|
|
<description>PSS interrupt as a source of NMI</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PSS_SRC_0</name>
|
|
<description>Disables the PSS interrupt as a source of NMI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PSS_SRC_1</name>
|
|
<description>Enables the PSS interrupt as a source of NMI</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCM_SRC</name>
|
|
<description>PCM interrupt as a source of NMI</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PCM_SRC_0</name>
|
|
<description>Disbles the PCM interrupt as a source of NMI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PCM_SRC_1</name>
|
|
<description>Enables the PCM interrupt as a source of NMI</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIN_SRC</name>
|
|
<description>RSTn/NMI pin configuration
|
|
Note: When the device enters LPM3/LPM4 modes of operation, the functionality selected by this bit is retained. If selected as an NMI, activity on this pin in
|
|
LPM3/LPM4 wakes the device and processes the interrupt, without causing a POR. If selected as a Reset, activity on this pin in LPM3/LPM4 causes a device-level POR
|
|
When the device enters LPM3.5/LPM4.5 modes of operation, this bit is always cleared to 0. In other words, the RSTn/NMI pin always assumes a reset functionality in LPM3.5/LPM4.5 modes.</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PIN_SRC_0</name>
|
|
<description>Configures the RSTn_NMI pin as a source of POR Class Reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIN_SRC_1</name>
|
|
<description>Configures the RSTn_NMI pin as a source of NMI</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CS_FLG</name>
|
|
<description>CS interrupt was the source of NMI</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>CS_FLG_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>CS_FLG_0</name>
|
|
<description>indicates CS interrupt was not the source of NMI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CS_FLG_1</name>
|
|
<description>indicates CS interrupt was the source of NMI</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSS_FLG</name>
|
|
<description>PSS interrupt was the source of NMI</description>
|
|
<bitOffset>0x11</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>PSS_FLG_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>PSS_FLG_0</name>
|
|
<description>indicates the PSS interrupt was not the source of NMI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PSS_FLG_1</name>
|
|
<description>indicates the PSS interrupt was the source of NMI</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCM_FLG</name>
|
|
<description>PCM interrupt was the source of NMI</description>
|
|
<bitOffset>0x12</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>PCM_FLG_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>PCM_FLG_0</name>
|
|
<description>indicates the PCM interrupt was not the source of NMI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PCM_FLG_1</name>
|
|
<description>indicates the PCM interrupt was the source of NMI</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIN_FLG</name>
|
|
<description>RSTn/NMI pin was the source of NMI</description>
|
|
<bitOffset>0x13</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PIN_FLG_0</name>
|
|
<description>Indicates the RSTn_NMI pin was not the source of NMI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIN_FLG_1</name>
|
|
<description>Indicates the RSTn_NMI pin was the source of NMI</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYS_WDTRESET_CTL</name>
|
|
<displayName>WDTRESET_CTL</displayName>
|
|
<description>Watchdog Reset Control Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TIMEOUT</name>
|
|
<description>WDT timeout reset type</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMEOUT_0</name>
|
|
<description>WDT timeout event generates Soft reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMEOUT_1</name>
|
|
<description>WDT timeout event generates Hard reset</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VIOLATION</name>
|
|
<description>WDT password violation reset type</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>VIOLATION_0</name>
|
|
<description>WDT password violation event generates Soft reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VIOLATION_1</name>
|
|
<description>WDT password violation event generates Hard reset</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYS_PERIHALT_CTL</name>
|
|
<displayName>PERIHALT_CTL</displayName>
|
|
<description>Peripheral Halt Control Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00004000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HALT_T16_0</name>
|
|
<description>Freezes IP operation when CPU is halted</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HALT_T16_0_0</name>
|
|
<description>IP operation unaffected when CPU is halted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT_T16_0_1</name>
|
|
<description>freezes IP operation when CPU is halted</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HALT_T16_1</name>
|
|
<description>Freezes IP operation when CPU is halted</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HALT_T16_1_0</name>
|
|
<description>IP operation unaffected when CPU is halted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT_T16_1_1</name>
|
|
<description>freezes IP operation when CPU is halted</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HALT_T16_2</name>
|
|
<description>Freezes IP operation when CPU is halted</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HALT_T16_2_0</name>
|
|
<description>IP operation unaffected when CPU is halted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT_T16_2_1</name>
|
|
<description>freezes IP operation when CPU is halted</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HALT_T16_3</name>
|
|
<description>Freezes IP operation when CPU is halted</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HALT_T16_3_0</name>
|
|
<description>IP operation unaffected when CPU is halted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT_T16_3_1</name>
|
|
<description>freezes IP operation when CPU is halted</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HALT_T32_0</name>
|
|
<description>Freezes IP operation when CPU is halted</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HALT_T32_0_0</name>
|
|
<description>IP operation unaffected when CPU is halted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT_T32_0_1</name>
|
|
<description>freezes IP operation when CPU is halted</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HALT_eUA0</name>
|
|
<description>Freezes IP operation when CPU is halted</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HALT_eUA0_0</name>
|
|
<description>IP operation unaffected when CPU is halted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT_eUA0_1</name>
|
|
<description>freezes IP operation when CPU is halted</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HALT_eUA1</name>
|
|
<description>Freezes IP operation when CPU is halted</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HALT_eUA1_0</name>
|
|
<description>IP operation unaffected when CPU is halted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT_eUA1_1</name>
|
|
<description>freezes IP operation when CPU is halted</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HALT_eUA2</name>
|
|
<description>Freezes IP operation when CPU is halted</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HALT_eUA2_0</name>
|
|
<description>IP operation unaffected when CPU is halted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT_eUA2_1</name>
|
|
<description>freezes IP operation when CPU is halted</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HALT_eUA3</name>
|
|
<description>Freezes IP operation when CPU is halted</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HALT_eUA3_0</name>
|
|
<description>IP operation unaffected when CPU is halted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT_eUA3_1</name>
|
|
<description>freezes IP operation when CPU is halted</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HALT_eUB0</name>
|
|
<description>Freezes IP operation when CPU is halted</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HALT_eUB0_0</name>
|
|
<description>IP operation unaffected when CPU is halted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT_eUB0_1</name>
|
|
<description>freezes IP operation when CPU is halted</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HALT_eUB1</name>
|
|
<description>Freezes IP operation when CPU is halted</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HALT_eUB1_0</name>
|
|
<description>IP operation unaffected when CPU is halted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT_eUB1_1</name>
|
|
<description>freezes IP operation when CPU is halted</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HALT_eUB2</name>
|
|
<description>Freezes IP operation when CPU is halted</description>
|
|
<bitOffset>0xB</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HALT_eUB2_0</name>
|
|
<description>IP operation unaffected when CPU is halted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT_eUB2_1</name>
|
|
<description>freezes IP operation when CPU is halted</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HALT_eUB3</name>
|
|
<description>Freezes IP operation when CPU is halted</description>
|
|
<bitOffset>0xC</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HALT_eUB3_0</name>
|
|
<description>IP operation unaffected when CPU is halted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT_eUB3_1</name>
|
|
<description>freezes IP operation when CPU is halted</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HALT_ADC</name>
|
|
<description>Freezes IP operation when CPU is halted</description>
|
|
<bitOffset>0xD</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HALT_ADC_0</name>
|
|
<description>IP operation unaffected when CPU is halted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT_ADC_1</name>
|
|
<description>freezes IP operation when CPU is halted</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HALT_WDT</name>
|
|
<description>Freezes IP operation when CPU is halted</description>
|
|
<bitOffset>0xE</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HALT_WDT_0</name>
|
|
<description>IP operation unaffected when CPU is halted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT_WDT_1</name>
|
|
<description>freezes IP operation when CPU is halted</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HALT_DMA</name>
|
|
<description>Freezes IP operation when CPU is halted</description>
|
|
<bitOffset>0xF</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HALT_DMA_0</name>
|
|
<description>IP operation unaffected when CPU is halted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT_DMA_1</name>
|
|
<description>freezes IP operation when CPU is halted</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYS_SRAM_SIZE</name>
|
|
<displayName>SRAM_SIZE</displayName>
|
|
<description>SRAM Size Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>SIZE</name>
|
|
<description>Indicates the size of SRAM on the device</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYS_SRAM_BANKEN</name>
|
|
<displayName>SRAM_BANKEN</displayName>
|
|
<description>SRAM Bank Enable Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000000ff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BNK0_EN</name>
|
|
<description>SRAM Bank0 enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BNK1_EN</name>
|
|
<description>SRAM Bank1 enable</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BNK1_EN_0</name>
|
|
<description>Disables Bank1 of the SRAM</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BNK1_EN_1</name>
|
|
<description>Enables Bank1 of the SRAM</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BNK2_EN</name>
|
|
<description>SRAM Bank1 enable</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BNK2_EN_0</name>
|
|
<description>Disables Bank2 of the SRAM</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BNK2_EN_1</name>
|
|
<description>Enables Bank2 of the SRAM</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BNK3_EN</name>
|
|
<description>SRAM Bank1 enable</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BNK3_EN_0</name>
|
|
<description>Disables Bank3 of the SRAM</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BNK3_EN_1</name>
|
|
<description>Enables Bank3 of the SRAM</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BNK4_EN</name>
|
|
<description>SRAM Bank1 enable</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BNK4_EN_0</name>
|
|
<description>Disables Bank4 of the SRAM</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BNK4_EN_1</name>
|
|
<description>Enables Bank4 of the SRAM</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BNK5_EN</name>
|
|
<description>SRAM Bank1 enable</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BNK5_EN_0</name>
|
|
<description>Disables Bank5 of the SRAM</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BNK5_EN_1</name>
|
|
<description>Enables Bank5 of the SRAM</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BNK6_EN</name>
|
|
<description>SRAM Bank1 enable</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BNK6_EN_0</name>
|
|
<description>Disables Bank6 of the SRAM</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BNK6_EN_1</name>
|
|
<description>Enables Bank6 of the SRAM</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BNK7_EN</name>
|
|
<description>SRAM Bank1 enable</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BNK7_EN_0</name>
|
|
<description>Disables Bank7 of the SRAM</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BNK7_EN_1</name>
|
|
<description>Enables Bank7 of the SRAM</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRAM_RDY</name>
|
|
<description>SRAM ready</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>SRAM_RDY_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>SRAM_RDY_0</name>
|
|
<description>SRAM is not ready for accesses. Banks are undergoing an enable or disable sequence, and reads or writes to SRAM are stalled until the banks are ready</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRAM_RDY_1</name>
|
|
<description>SRAM is ready for accesses. All SRAM banks are enabled/disabled according to values of bits 7:0 of this register</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYS_SRAM_BANKRET</name>
|
|
<displayName>SRAM_BANKRET</displayName>
|
|
<description>SRAM Bank Retention Control Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000000ff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BNK0_RET</name>
|
|
<description>Bank0 retention</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BNK1_RET</name>
|
|
<description>Bank1 retention</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BNK1_RET_0</name>
|
|
<description>Bank1 of the SRAM is not retained in LPM3 or LPM4</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BNK1_RET_1</name>
|
|
<description>Bank1 of the SRAM is retained in LPM3 and LPM4</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BNK2_RET</name>
|
|
<description>Bank2 retention</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BNK2_RET_0</name>
|
|
<description>Bank2 of the SRAM is not retained in LPM3 or LPM4</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BNK2_RET_1</name>
|
|
<description>Bank2 of the SRAM is retained in LPM3 and LPM4</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BNK3_RET</name>
|
|
<description>Bank3 retention</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BNK3_RET_0</name>
|
|
<description>Bank3 of the SRAM is not retained in LPM3 or LPM4</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BNK3_RET_1</name>
|
|
<description>Bank3 of the SRAM is retained in LPM3 and LPM4</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BNK4_RET</name>
|
|
<description>Bank4 retention</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BNK4_RET_0</name>
|
|
<description>Bank4 of the SRAM is not retained in LPM3 or LPM4</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BNK4_RET_1</name>
|
|
<description>Bank4 of the SRAM is retained in LPM3 and LPM4</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BNK5_RET</name>
|
|
<description>Bank5 retention</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BNK5_RET_0</name>
|
|
<description>Bank5 of the SRAM is not retained in LPM3 or LPM4</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BNK5_RET_1</name>
|
|
<description>Bank5 of the SRAM is retained in LPM3 and LPM4</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BNK6_RET</name>
|
|
<description>Bank6 retention</description>
|
|
<bitOffset>0x6</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BNK6_RET_0</name>
|
|
<description>Bank6 of the SRAM is not retained in LPM3 or LPM4</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BNK6_RET_1</name>
|
|
<description>Bank6 of the SRAM is retained in LPM3 and LPM4</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BNK7_RET</name>
|
|
<description>Bank7 retention</description>
|
|
<bitOffset>0x7</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BNK7_RET_0</name>
|
|
<description>Bank7 of the SRAM is not retained in LPM3 or LPM4</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BNK7_RET_1</name>
|
|
<description>Bank7 of the SRAM is retained in LPM3 and LPM4</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRAM_RDY</name>
|
|
<description>SRAM ready</description>
|
|
<bitOffset>0x10</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<name>SRAM_RDY_enum_read</name>
|
|
<usage>read</usage>
|
|
<enumeratedValue>
|
|
<name>SRAM_RDY_0</name>
|
|
<description>SRAM banks are being set up for retention. Entry into LPM3, LPM4 should not be attempted until this bit is set to 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRAM_RDY_1</name>
|
|
<description>SRAM is ready for accesses. All SRAM banks are enabled/disabled for retention according to values of bits 7:0 of this register</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYS_FLASH_SIZE</name>
|
|
<displayName>FLASH_SIZE</displayName>
|
|
<description>Flash Size Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>SIZE</name>
|
|
<description>Flash User Region size</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYS_DIO_GLTFLT_CTL</name>
|
|
<displayName>DIO_GLTFLT_CTL</displayName>
|
|
<description>Digital I/O Glitch Filter Control Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GLTCH_EN</name>
|
|
<description>Glitch filter enable</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GLTCH_EN_0</name>
|
|
<description>Disables glitch filter on the digital I/Os</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GLTCH_EN_1</name>
|
|
<description>Enables glitch filter on the digital I/Os</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYS_SECDATA_UNLOCK</name>
|
|
<displayName>SECDATA_UNLOCK</displayName>
|
|
<description>IP Protected Secure Zone Data Access Unlock Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UNLKEY</name>
|
|
<description>Unlock key</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYS_MASTER_UNLOCK</name>
|
|
<displayName>MASTER_UNLOCK</displayName>
|
|
<description>Master Unlock Register</description>
|
|
<addressOffset>0x1000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UNLKEY</name>
|
|
<description>Unlock Key</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>SYS_BOOTOVER_REQ[%s]</name>
|
|
<displayName>BOOTOVER_REQ[%s]</displayName>
|
|
<description>Boot Override Request Register</description>
|
|
<addressOffset>0x1004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REGVAL</name>
|
|
<description>Value set by debugger, read and clear by the CPU</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYS_BOOTOVER_ACK</name>
|
|
<displayName>BOOTOVER_ACK</displayName>
|
|
<description>Boot Override Acknowledge Register</description>
|
|
<addressOffset>0x100C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REGVAL</name>
|
|
<description>Value set by CPU, read/clear by the debugger</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYS_RESET_REQ</name>
|
|
<displayName>RESET_REQ</displayName>
|
|
<description>Reset Request Register</description>
|
|
<addressOffset>0x1010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>POR</name>
|
|
<description>Generate POR</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>REBOOT</name>
|
|
<description>Generate Reboot_Reset</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WKEY</name>
|
|
<description>Write key</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYS_RESET_STATOVER</name>
|
|
<displayName>RESET_STATOVER</displayName>
|
|
<description>Reset Status and Override Register</description>
|
|
<addressOffset>0x1014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000700</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOFT</name>
|
|
<description>Indicates if SOFT Reset is active</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HARD</name>
|
|
<description>Indicates if HARD Reset is active</description>
|
|
<bitOffset>0x1</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>REBOOT</name>
|
|
<description>Indicates if Reboot Reset is active</description>
|
|
<bitOffset>0x2</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SOFT_OVER</name>
|
|
<description>SOFT_Reset overwrite request</description>
|
|
<bitOffset>0x8</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HARD_OVER</name>
|
|
<description>HARD_Reset overwrite request</description>
|
|
<bitOffset>0x9</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RBT_OVER</name>
|
|
<description>Reboot Reset overwrite request</description>
|
|
<bitOffset>0xA</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYS_SYSTEM_STAT</name>
|
|
<displayName>SYSTEM_STAT</displayName>
|
|
<description>System Status Register</description>
|
|
<addressOffset>0x1020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>DBG_SEC_ACT</name>
|
|
<description>Debug Security active</description>
|
|
<bitOffset>0x3</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>JTAG_SWD_LOCK_ACT</name>
|
|
<description>Indicates if JTAG and SWD Lock is active</description>
|
|
<bitOffset>0x4</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IP_PROT_ACT</name>
|
|
<description>Indicates if IP protection is active</description>
|
|
<bitOffset>0x5</bitOffset>
|
|
<bitWidth>0x1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
</peripherals>
|
|
</device>
|
|
|
|
|