2096 lines
58 KiB
Rust
2096 lines
58 KiB
Rust
#[doc = r" Value read from the register"]
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pub struct R {
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bits: u32,
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}
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#[doc = r" Value to write to the register"]
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pub struct W {
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bits: u32,
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}
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impl super::ADC14CTL0 {
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#[doc = r" Modifies the contents of the register"]
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#[inline]
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pub fn modify<F>(&self, f: F)
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where
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for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
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{
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let bits = self.register.get();
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let r = R { bits: bits };
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let mut w = W { bits: bits };
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f(&r, &mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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pub fn write<F>(&self, f: F)
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where
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F: FnOnce(&mut W) -> &mut W,
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{
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let mut w = W::reset_value();
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f(&mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Writes the reset value to the register"]
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#[inline]
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pub fn reset(&self) {
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self.write(|w| w)
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}
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}
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#[doc = "Possible values of the field `ADC14SC`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum ADC14SCR {
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#[doc = "No sample-and-conversion-start"]
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ADC14SC_0,
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#[doc = "Start sample-and-conversion"]
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ADC14SC_1,
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}
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impl ADC14SCR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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ADC14SCR::ADC14SC_0 => false,
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ADC14SCR::ADC14SC_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> ADC14SCR {
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match value {
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false => ADC14SCR::ADC14SC_0,
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true => ADC14SCR::ADC14SC_1,
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}
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}
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#[doc = "Checks if the value of the field is `ADC14SC_0`"]
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#[inline]
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pub fn is_adc14sc_0(&self) -> bool {
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*self == ADC14SCR::ADC14SC_0
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}
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#[doc = "Checks if the value of the field is `ADC14SC_1`"]
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#[inline]
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pub fn is_adc14sc_1(&self) -> bool {
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*self == ADC14SCR::ADC14SC_1
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}
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}
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#[doc = "Possible values of the field `ADC14ENC`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum ADC14ENCR {
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#[doc = "ADC14 disabled"]
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ADC14ENC_0,
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#[doc = "ADC14 enabled"]
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ADC14ENC_1,
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}
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impl ADC14ENCR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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ADC14ENCR::ADC14ENC_0 => false,
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ADC14ENCR::ADC14ENC_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> ADC14ENCR {
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match value {
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false => ADC14ENCR::ADC14ENC_0,
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true => ADC14ENCR::ADC14ENC_1,
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}
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}
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#[doc = "Checks if the value of the field is `ADC14ENC_0`"]
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#[inline]
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pub fn is_adc14enc_0(&self) -> bool {
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*self == ADC14ENCR::ADC14ENC_0
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}
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#[doc = "Checks if the value of the field is `ADC14ENC_1`"]
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#[inline]
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pub fn is_adc14enc_1(&self) -> bool {
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*self == ADC14ENCR::ADC14ENC_1
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}
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}
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#[doc = "Possible values of the field `ADC14ON`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum ADC14ONR {
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#[doc = "ADC14 off"]
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ADC14ON_0,
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#[doc = "ADC14 on. ADC core is ready to power up when a valid conversion is triggered."]
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ADC14ON_1,
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}
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impl ADC14ONR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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ADC14ONR::ADC14ON_0 => false,
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ADC14ONR::ADC14ON_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> ADC14ONR {
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match value {
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false => ADC14ONR::ADC14ON_0,
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true => ADC14ONR::ADC14ON_1,
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}
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}
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#[doc = "Checks if the value of the field is `ADC14ON_0`"]
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#[inline]
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pub fn is_adc14on_0(&self) -> bool {
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*self == ADC14ONR::ADC14ON_0
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}
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#[doc = "Checks if the value of the field is `ADC14ON_1`"]
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#[inline]
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pub fn is_adc14on_1(&self) -> bool {
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*self == ADC14ONR::ADC14ON_1
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}
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}
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#[doc = "Possible values of the field `ADC14MSC`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum ADC14MSCR {
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#[doc = "The sampling timer requires a rising edge of the SHI signal to trigger each sample-and-convert"]
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ADC14MSC_0,
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#[doc = "The first rising edge of the SHI signal triggers the sampling timer, but further sample-and-conversions are performed automatically as soon as the prior conversion is completed"]
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ADC14MSC_1,
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}
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impl ADC14MSCR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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ADC14MSCR::ADC14MSC_0 => false,
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ADC14MSCR::ADC14MSC_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> ADC14MSCR {
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match value {
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false => ADC14MSCR::ADC14MSC_0,
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true => ADC14MSCR::ADC14MSC_1,
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}
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}
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#[doc = "Checks if the value of the field is `ADC14MSC_0`"]
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#[inline]
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pub fn is_adc14msc_0(&self) -> bool {
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*self == ADC14MSCR::ADC14MSC_0
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}
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#[doc = "Checks if the value of the field is `ADC14MSC_1`"]
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#[inline]
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pub fn is_adc14msc_1(&self) -> bool {
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*self == ADC14MSCR::ADC14MSC_1
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}
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}
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#[doc = "Possible values of the field `ADC14SHT0`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum ADC14SHT0R {
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#[doc = "4"]
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ADC14SHT0_0,
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#[doc = "8"]
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ADC14SHT0_1,
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#[doc = "16"]
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ADC14SHT0_2,
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#[doc = "32"]
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ADC14SHT0_3,
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#[doc = "64"]
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ADC14SHT0_4,
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#[doc = "96"]
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ADC14SHT0_5,
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#[doc = "128"]
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ADC14SHT0_6,
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#[doc = "192"]
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ADC14SHT0_7,
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#[doc = r" Reserved"]
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_Reserved(u8),
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}
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impl ADC14SHT0R {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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match *self {
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ADC14SHT0R::ADC14SHT0_0 => 0,
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ADC14SHT0R::ADC14SHT0_1 => 1,
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ADC14SHT0R::ADC14SHT0_2 => 2,
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ADC14SHT0R::ADC14SHT0_3 => 3,
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ADC14SHT0R::ADC14SHT0_4 => 4,
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ADC14SHT0R::ADC14SHT0_5 => 5,
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ADC14SHT0R::ADC14SHT0_6 => 6,
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ADC14SHT0R::ADC14SHT0_7 => 7,
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ADC14SHT0R::_Reserved(bits) => bits,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: u8) -> ADC14SHT0R {
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match value {
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0 => ADC14SHT0R::ADC14SHT0_0,
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1 => ADC14SHT0R::ADC14SHT0_1,
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2 => ADC14SHT0R::ADC14SHT0_2,
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3 => ADC14SHT0R::ADC14SHT0_3,
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4 => ADC14SHT0R::ADC14SHT0_4,
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5 => ADC14SHT0R::ADC14SHT0_5,
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6 => ADC14SHT0R::ADC14SHT0_6,
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7 => ADC14SHT0R::ADC14SHT0_7,
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i => ADC14SHT0R::_Reserved(i),
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}
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}
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#[doc = "Checks if the value of the field is `ADC14SHT0_0`"]
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#[inline]
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pub fn is_adc14sht0_0(&self) -> bool {
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*self == ADC14SHT0R::ADC14SHT0_0
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}
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#[doc = "Checks if the value of the field is `ADC14SHT0_1`"]
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#[inline]
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pub fn is_adc14sht0_1(&self) -> bool {
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*self == ADC14SHT0R::ADC14SHT0_1
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}
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#[doc = "Checks if the value of the field is `ADC14SHT0_2`"]
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#[inline]
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pub fn is_adc14sht0_2(&self) -> bool {
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*self == ADC14SHT0R::ADC14SHT0_2
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}
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#[doc = "Checks if the value of the field is `ADC14SHT0_3`"]
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#[inline]
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pub fn is_adc14sht0_3(&self) -> bool {
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*self == ADC14SHT0R::ADC14SHT0_3
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}
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#[doc = "Checks if the value of the field is `ADC14SHT0_4`"]
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#[inline]
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pub fn is_adc14sht0_4(&self) -> bool {
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*self == ADC14SHT0R::ADC14SHT0_4
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}
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#[doc = "Checks if the value of the field is `ADC14SHT0_5`"]
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#[inline]
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pub fn is_adc14sht0_5(&self) -> bool {
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*self == ADC14SHT0R::ADC14SHT0_5
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}
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#[doc = "Checks if the value of the field is `ADC14SHT0_6`"]
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#[inline]
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pub fn is_adc14sht0_6(&self) -> bool {
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*self == ADC14SHT0R::ADC14SHT0_6
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}
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#[doc = "Checks if the value of the field is `ADC14SHT0_7`"]
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#[inline]
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pub fn is_adc14sht0_7(&self) -> bool {
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*self == ADC14SHT0R::ADC14SHT0_7
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}
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}
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#[doc = "Possible values of the field `ADC14SHT1`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum ADC14SHT1R {
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#[doc = "4"]
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ADC14SHT1_0,
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#[doc = "8"]
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ADC14SHT1_1,
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#[doc = "16"]
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ADC14SHT1_2,
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#[doc = "32"]
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ADC14SHT1_3,
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#[doc = "64"]
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ADC14SHT1_4,
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#[doc = "96"]
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ADC14SHT1_5,
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#[doc = "128"]
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ADC14SHT1_6,
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#[doc = "192"]
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ADC14SHT1_7,
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#[doc = r" Reserved"]
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_Reserved(u8),
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}
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impl ADC14SHT1R {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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match *self {
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ADC14SHT1R::ADC14SHT1_0 => 0,
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ADC14SHT1R::ADC14SHT1_1 => 1,
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ADC14SHT1R::ADC14SHT1_2 => 2,
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ADC14SHT1R::ADC14SHT1_3 => 3,
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ADC14SHT1R::ADC14SHT1_4 => 4,
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ADC14SHT1R::ADC14SHT1_5 => 5,
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ADC14SHT1R::ADC14SHT1_6 => 6,
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ADC14SHT1R::ADC14SHT1_7 => 7,
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ADC14SHT1R::_Reserved(bits) => bits,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: u8) -> ADC14SHT1R {
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match value {
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0 => ADC14SHT1R::ADC14SHT1_0,
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1 => ADC14SHT1R::ADC14SHT1_1,
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2 => ADC14SHT1R::ADC14SHT1_2,
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3 => ADC14SHT1R::ADC14SHT1_3,
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4 => ADC14SHT1R::ADC14SHT1_4,
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5 => ADC14SHT1R::ADC14SHT1_5,
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6 => ADC14SHT1R::ADC14SHT1_6,
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7 => ADC14SHT1R::ADC14SHT1_7,
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i => ADC14SHT1R::_Reserved(i),
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}
|
|
}
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#[doc = "Checks if the value of the field is `ADC14SHT1_0`"]
|
|
#[inline]
|
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pub fn is_adc14sht1_0(&self) -> bool {
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|
*self == ADC14SHT1R::ADC14SHT1_0
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|
}
|
|
#[doc = "Checks if the value of the field is `ADC14SHT1_1`"]
|
|
#[inline]
|
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pub fn is_adc14sht1_1(&self) -> bool {
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*self == ADC14SHT1R::ADC14SHT1_1
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|
}
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#[doc = "Checks if the value of the field is `ADC14SHT1_2`"]
|
|
#[inline]
|
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pub fn is_adc14sht1_2(&self) -> bool {
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*self == ADC14SHT1R::ADC14SHT1_2
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|
}
|
|
#[doc = "Checks if the value of the field is `ADC14SHT1_3`"]
|
|
#[inline]
|
|
pub fn is_adc14sht1_3(&self) -> bool {
|
|
*self == ADC14SHT1R::ADC14SHT1_3
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14SHT1_4`"]
|
|
#[inline]
|
|
pub fn is_adc14sht1_4(&self) -> bool {
|
|
*self == ADC14SHT1R::ADC14SHT1_4
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14SHT1_5`"]
|
|
#[inline]
|
|
pub fn is_adc14sht1_5(&self) -> bool {
|
|
*self == ADC14SHT1R::ADC14SHT1_5
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14SHT1_6`"]
|
|
#[inline]
|
|
pub fn is_adc14sht1_6(&self) -> bool {
|
|
*self == ADC14SHT1R::ADC14SHT1_6
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14SHT1_7`"]
|
|
#[inline]
|
|
pub fn is_adc14sht1_7(&self) -> bool {
|
|
*self == ADC14SHT1R::ADC14SHT1_7
|
|
}
|
|
}
|
|
#[doc = "Possible values of the field `ADC14BUSY`"]
|
|
#[derive(Clone, Copy, Debug, PartialEq)]
|
|
pub enum ADC14BUSYR {
|
|
#[doc = "No operation is active"]
|
|
ADC14BUSY_0,
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|
#[doc = "A sequence, sample, or conversion is active"]
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|
ADC14BUSY_1,
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|
}
|
|
impl ADC14BUSYR {
|
|
#[doc = r" Returns `true` if the bit is clear (0)"]
|
|
#[inline]
|
|
pub fn bit_is_clear(&self) -> bool {
|
|
!self.bit()
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|
}
|
|
#[doc = r" Returns `true` if the bit is set (1)"]
|
|
#[inline]
|
|
pub fn bit_is_set(&self) -> bool {
|
|
self.bit()
|
|
}
|
|
#[doc = r" Value of the field as raw bits"]
|
|
#[inline]
|
|
pub fn bit(&self) -> bool {
|
|
match *self {
|
|
ADC14BUSYR::ADC14BUSY_0 => false,
|
|
ADC14BUSYR::ADC14BUSY_1 => true,
|
|
}
|
|
}
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _from(value: bool) -> ADC14BUSYR {
|
|
match value {
|
|
false => ADC14BUSYR::ADC14BUSY_0,
|
|
true => ADC14BUSYR::ADC14BUSY_1,
|
|
}
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14BUSY_0`"]
|
|
#[inline]
|
|
pub fn is_adc14busy_0(&self) -> bool {
|
|
*self == ADC14BUSYR::ADC14BUSY_0
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14BUSY_1`"]
|
|
#[inline]
|
|
pub fn is_adc14busy_1(&self) -> bool {
|
|
*self == ADC14BUSYR::ADC14BUSY_1
|
|
}
|
|
}
|
|
#[doc = "Possible values of the field `ADC14CONSEQ`"]
|
|
#[derive(Clone, Copy, Debug, PartialEq)]
|
|
pub enum ADC14CONSEQR {
|
|
#[doc = "Single-channel, single-conversion"]
|
|
ADC14CONSEQ_0,
|
|
#[doc = "Sequence-of-channels"]
|
|
ADC14CONSEQ_1,
|
|
#[doc = "Repeat-single-channel"]
|
|
ADC14CONSEQ_2,
|
|
#[doc = "Repeat-sequence-of-channels"]
|
|
ADC14CONSEQ_3,
|
|
}
|
|
impl ADC14CONSEQR {
|
|
#[doc = r" Value of the field as raw bits"]
|
|
#[inline]
|
|
pub fn bits(&self) -> u8 {
|
|
match *self {
|
|
ADC14CONSEQR::ADC14CONSEQ_0 => 0,
|
|
ADC14CONSEQR::ADC14CONSEQ_1 => 1,
|
|
ADC14CONSEQR::ADC14CONSEQ_2 => 2,
|
|
ADC14CONSEQR::ADC14CONSEQ_3 => 3,
|
|
}
|
|
}
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _from(value: u8) -> ADC14CONSEQR {
|
|
match value {
|
|
0 => ADC14CONSEQR::ADC14CONSEQ_0,
|
|
1 => ADC14CONSEQR::ADC14CONSEQ_1,
|
|
2 => ADC14CONSEQR::ADC14CONSEQ_2,
|
|
3 => ADC14CONSEQR::ADC14CONSEQ_3,
|
|
_ => unreachable!(),
|
|
}
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14CONSEQ_0`"]
|
|
#[inline]
|
|
pub fn is_adc14conseq_0(&self) -> bool {
|
|
*self == ADC14CONSEQR::ADC14CONSEQ_0
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14CONSEQ_1`"]
|
|
#[inline]
|
|
pub fn is_adc14conseq_1(&self) -> bool {
|
|
*self == ADC14CONSEQR::ADC14CONSEQ_1
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14CONSEQ_2`"]
|
|
#[inline]
|
|
pub fn is_adc14conseq_2(&self) -> bool {
|
|
*self == ADC14CONSEQR::ADC14CONSEQ_2
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14CONSEQ_3`"]
|
|
#[inline]
|
|
pub fn is_adc14conseq_3(&self) -> bool {
|
|
*self == ADC14CONSEQR::ADC14CONSEQ_3
|
|
}
|
|
}
|
|
#[doc = "Possible values of the field `ADC14SSEL`"]
|
|
#[derive(Clone, Copy, Debug, PartialEq)]
|
|
pub enum ADC14SSELR {
|
|
#[doc = "MODCLK"]
|
|
ADC14SSEL_0,
|
|
#[doc = "SYSCLK"]
|
|
ADC14SSEL_1,
|
|
#[doc = "ACLK"]
|
|
ADC14SSEL_2,
|
|
#[doc = "MCLK"]
|
|
ADC14SSEL_3,
|
|
#[doc = "SMCLK"]
|
|
ADC14SSEL_4,
|
|
#[doc = "HSMCLK"]
|
|
ADC14SSEL_5,
|
|
#[doc = r" Reserved"]
|
|
_Reserved(u8),
|
|
}
|
|
impl ADC14SSELR {
|
|
#[doc = r" Value of the field as raw bits"]
|
|
#[inline]
|
|
pub fn bits(&self) -> u8 {
|
|
match *self {
|
|
ADC14SSELR::ADC14SSEL_0 => 0,
|
|
ADC14SSELR::ADC14SSEL_1 => 1,
|
|
ADC14SSELR::ADC14SSEL_2 => 2,
|
|
ADC14SSELR::ADC14SSEL_3 => 3,
|
|
ADC14SSELR::ADC14SSEL_4 => 4,
|
|
ADC14SSELR::ADC14SSEL_5 => 5,
|
|
ADC14SSELR::_Reserved(bits) => bits,
|
|
}
|
|
}
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _from(value: u8) -> ADC14SSELR {
|
|
match value {
|
|
0 => ADC14SSELR::ADC14SSEL_0,
|
|
1 => ADC14SSELR::ADC14SSEL_1,
|
|
2 => ADC14SSELR::ADC14SSEL_2,
|
|
3 => ADC14SSELR::ADC14SSEL_3,
|
|
4 => ADC14SSELR::ADC14SSEL_4,
|
|
5 => ADC14SSELR::ADC14SSEL_5,
|
|
i => ADC14SSELR::_Reserved(i),
|
|
}
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14SSEL_0`"]
|
|
#[inline]
|
|
pub fn is_adc14ssel_0(&self) -> bool {
|
|
*self == ADC14SSELR::ADC14SSEL_0
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14SSEL_1`"]
|
|
#[inline]
|
|
pub fn is_adc14ssel_1(&self) -> bool {
|
|
*self == ADC14SSELR::ADC14SSEL_1
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14SSEL_2`"]
|
|
#[inline]
|
|
pub fn is_adc14ssel_2(&self) -> bool {
|
|
*self == ADC14SSELR::ADC14SSEL_2
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14SSEL_3`"]
|
|
#[inline]
|
|
pub fn is_adc14ssel_3(&self) -> bool {
|
|
*self == ADC14SSELR::ADC14SSEL_3
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14SSEL_4`"]
|
|
#[inline]
|
|
pub fn is_adc14ssel_4(&self) -> bool {
|
|
*self == ADC14SSELR::ADC14SSEL_4
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14SSEL_5`"]
|
|
#[inline]
|
|
pub fn is_adc14ssel_5(&self) -> bool {
|
|
*self == ADC14SSELR::ADC14SSEL_5
|
|
}
|
|
}
|
|
#[doc = "Possible values of the field `ADC14DIV`"]
|
|
#[derive(Clone, Copy, Debug, PartialEq)]
|
|
pub enum ADC14DIVR {
|
|
#[doc = "/1"]
|
|
ADC14DIV_0,
|
|
#[doc = "/2"]
|
|
ADC14DIV_1,
|
|
#[doc = "/3"]
|
|
ADC14DIV_2,
|
|
#[doc = "/4"]
|
|
ADC14DIV_3,
|
|
#[doc = "/5"]
|
|
ADC14DIV_4,
|
|
#[doc = "/6"]
|
|
ADC14DIV_5,
|
|
#[doc = "/7"]
|
|
ADC14DIV_6,
|
|
#[doc = "/8"]
|
|
ADC14DIV_7,
|
|
}
|
|
impl ADC14DIVR {
|
|
#[doc = r" Value of the field as raw bits"]
|
|
#[inline]
|
|
pub fn bits(&self) -> u8 {
|
|
match *self {
|
|
ADC14DIVR::ADC14DIV_0 => 0,
|
|
ADC14DIVR::ADC14DIV_1 => 1,
|
|
ADC14DIVR::ADC14DIV_2 => 2,
|
|
ADC14DIVR::ADC14DIV_3 => 3,
|
|
ADC14DIVR::ADC14DIV_4 => 4,
|
|
ADC14DIVR::ADC14DIV_5 => 5,
|
|
ADC14DIVR::ADC14DIV_6 => 6,
|
|
ADC14DIVR::ADC14DIV_7 => 7,
|
|
}
|
|
}
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _from(value: u8) -> ADC14DIVR {
|
|
match value {
|
|
0 => ADC14DIVR::ADC14DIV_0,
|
|
1 => ADC14DIVR::ADC14DIV_1,
|
|
2 => ADC14DIVR::ADC14DIV_2,
|
|
3 => ADC14DIVR::ADC14DIV_3,
|
|
4 => ADC14DIVR::ADC14DIV_4,
|
|
5 => ADC14DIVR::ADC14DIV_5,
|
|
6 => ADC14DIVR::ADC14DIV_6,
|
|
7 => ADC14DIVR::ADC14DIV_7,
|
|
_ => unreachable!(),
|
|
}
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14DIV_0`"]
|
|
#[inline]
|
|
pub fn is_adc14div_0(&self) -> bool {
|
|
*self == ADC14DIVR::ADC14DIV_0
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14DIV_1`"]
|
|
#[inline]
|
|
pub fn is_adc14div_1(&self) -> bool {
|
|
*self == ADC14DIVR::ADC14DIV_1
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14DIV_2`"]
|
|
#[inline]
|
|
pub fn is_adc14div_2(&self) -> bool {
|
|
*self == ADC14DIVR::ADC14DIV_2
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14DIV_3`"]
|
|
#[inline]
|
|
pub fn is_adc14div_3(&self) -> bool {
|
|
*self == ADC14DIVR::ADC14DIV_3
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14DIV_4`"]
|
|
#[inline]
|
|
pub fn is_adc14div_4(&self) -> bool {
|
|
*self == ADC14DIVR::ADC14DIV_4
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14DIV_5`"]
|
|
#[inline]
|
|
pub fn is_adc14div_5(&self) -> bool {
|
|
*self == ADC14DIVR::ADC14DIV_5
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14DIV_6`"]
|
|
#[inline]
|
|
pub fn is_adc14div_6(&self) -> bool {
|
|
*self == ADC14DIVR::ADC14DIV_6
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14DIV_7`"]
|
|
#[inline]
|
|
pub fn is_adc14div_7(&self) -> bool {
|
|
*self == ADC14DIVR::ADC14DIV_7
|
|
}
|
|
}
|
|
#[doc = "Possible values of the field `ADC14ISSH`"]
|
|
#[derive(Clone, Copy, Debug, PartialEq)]
|
|
pub enum ADC14ISSHR {
|
|
#[doc = "The sample-input signal is not inverted"]
|
|
ADC14ISSH_0,
|
|
#[doc = "The sample-input signal is inverted"]
|
|
ADC14ISSH_1,
|
|
}
|
|
impl ADC14ISSHR {
|
|
#[doc = r" Returns `true` if the bit is clear (0)"]
|
|
#[inline]
|
|
pub fn bit_is_clear(&self) -> bool {
|
|
!self.bit()
|
|
}
|
|
#[doc = r" Returns `true` if the bit is set (1)"]
|
|
#[inline]
|
|
pub fn bit_is_set(&self) -> bool {
|
|
self.bit()
|
|
}
|
|
#[doc = r" Value of the field as raw bits"]
|
|
#[inline]
|
|
pub fn bit(&self) -> bool {
|
|
match *self {
|
|
ADC14ISSHR::ADC14ISSH_0 => false,
|
|
ADC14ISSHR::ADC14ISSH_1 => true,
|
|
}
|
|
}
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _from(value: bool) -> ADC14ISSHR {
|
|
match value {
|
|
false => ADC14ISSHR::ADC14ISSH_0,
|
|
true => ADC14ISSHR::ADC14ISSH_1,
|
|
}
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14ISSH_0`"]
|
|
#[inline]
|
|
pub fn is_adc14issh_0(&self) -> bool {
|
|
*self == ADC14ISSHR::ADC14ISSH_0
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14ISSH_1`"]
|
|
#[inline]
|
|
pub fn is_adc14issh_1(&self) -> bool {
|
|
*self == ADC14ISSHR::ADC14ISSH_1
|
|
}
|
|
}
|
|
#[doc = "Possible values of the field `ADC14SHP`"]
|
|
#[derive(Clone, Copy, Debug, PartialEq)]
|
|
pub enum ADC14SHPR {
|
|
#[doc = "SAMPCON signal is sourced from the sample-input signal"]
|
|
ADC14SHP_0,
|
|
#[doc = "SAMPCON signal is sourced from the sampling timer"]
|
|
ADC14SHP_1,
|
|
}
|
|
impl ADC14SHPR {
|
|
#[doc = r" Returns `true` if the bit is clear (0)"]
|
|
#[inline]
|
|
pub fn bit_is_clear(&self) -> bool {
|
|
!self.bit()
|
|
}
|
|
#[doc = r" Returns `true` if the bit is set (1)"]
|
|
#[inline]
|
|
pub fn bit_is_set(&self) -> bool {
|
|
self.bit()
|
|
}
|
|
#[doc = r" Value of the field as raw bits"]
|
|
#[inline]
|
|
pub fn bit(&self) -> bool {
|
|
match *self {
|
|
ADC14SHPR::ADC14SHP_0 => false,
|
|
ADC14SHPR::ADC14SHP_1 => true,
|
|
}
|
|
}
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _from(value: bool) -> ADC14SHPR {
|
|
match value {
|
|
false => ADC14SHPR::ADC14SHP_0,
|
|
true => ADC14SHPR::ADC14SHP_1,
|
|
}
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14SHP_0`"]
|
|
#[inline]
|
|
pub fn is_adc14shp_0(&self) -> bool {
|
|
*self == ADC14SHPR::ADC14SHP_0
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14SHP_1`"]
|
|
#[inline]
|
|
pub fn is_adc14shp_1(&self) -> bool {
|
|
*self == ADC14SHPR::ADC14SHP_1
|
|
}
|
|
}
|
|
#[doc = "Possible values of the field `ADC14SHS`"]
|
|
#[derive(Clone, Copy, Debug, PartialEq)]
|
|
pub enum ADC14SHSR {
|
|
#[doc = "ADC14SC bit"]
|
|
ADC14SHS_0,
|
|
#[doc = "See device-specific data sheet for source"]
|
|
ADC14SHS_1,
|
|
#[doc = "See device-specific data sheet for source"]
|
|
ADC14SHS_2,
|
|
#[doc = "See device-specific data sheet for source"]
|
|
ADC14SHS_3,
|
|
#[doc = "See device-specific data sheet for source"]
|
|
ADC14SHS_4,
|
|
#[doc = "See device-specific data sheet for source"]
|
|
ADC14SHS_5,
|
|
#[doc = "See device-specific data sheet for source"]
|
|
ADC14SHS_6,
|
|
#[doc = "See device-specific data sheet for source"]
|
|
ADC14SHS_7,
|
|
}
|
|
impl ADC14SHSR {
|
|
#[doc = r" Value of the field as raw bits"]
|
|
#[inline]
|
|
pub fn bits(&self) -> u8 {
|
|
match *self {
|
|
ADC14SHSR::ADC14SHS_0 => 0,
|
|
ADC14SHSR::ADC14SHS_1 => 1,
|
|
ADC14SHSR::ADC14SHS_2 => 2,
|
|
ADC14SHSR::ADC14SHS_3 => 3,
|
|
ADC14SHSR::ADC14SHS_4 => 4,
|
|
ADC14SHSR::ADC14SHS_5 => 5,
|
|
ADC14SHSR::ADC14SHS_6 => 6,
|
|
ADC14SHSR::ADC14SHS_7 => 7,
|
|
}
|
|
}
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _from(value: u8) -> ADC14SHSR {
|
|
match value {
|
|
0 => ADC14SHSR::ADC14SHS_0,
|
|
1 => ADC14SHSR::ADC14SHS_1,
|
|
2 => ADC14SHSR::ADC14SHS_2,
|
|
3 => ADC14SHSR::ADC14SHS_3,
|
|
4 => ADC14SHSR::ADC14SHS_4,
|
|
5 => ADC14SHSR::ADC14SHS_5,
|
|
6 => ADC14SHSR::ADC14SHS_6,
|
|
7 => ADC14SHSR::ADC14SHS_7,
|
|
_ => unreachable!(),
|
|
}
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14SHS_0`"]
|
|
#[inline]
|
|
pub fn is_adc14shs_0(&self) -> bool {
|
|
*self == ADC14SHSR::ADC14SHS_0
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14SHS_1`"]
|
|
#[inline]
|
|
pub fn is_adc14shs_1(&self) -> bool {
|
|
*self == ADC14SHSR::ADC14SHS_1
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14SHS_2`"]
|
|
#[inline]
|
|
pub fn is_adc14shs_2(&self) -> bool {
|
|
*self == ADC14SHSR::ADC14SHS_2
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14SHS_3`"]
|
|
#[inline]
|
|
pub fn is_adc14shs_3(&self) -> bool {
|
|
*self == ADC14SHSR::ADC14SHS_3
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14SHS_4`"]
|
|
#[inline]
|
|
pub fn is_adc14shs_4(&self) -> bool {
|
|
*self == ADC14SHSR::ADC14SHS_4
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14SHS_5`"]
|
|
#[inline]
|
|
pub fn is_adc14shs_5(&self) -> bool {
|
|
*self == ADC14SHSR::ADC14SHS_5
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14SHS_6`"]
|
|
#[inline]
|
|
pub fn is_adc14shs_6(&self) -> bool {
|
|
*self == ADC14SHSR::ADC14SHS_6
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14SHS_7`"]
|
|
#[inline]
|
|
pub fn is_adc14shs_7(&self) -> bool {
|
|
*self == ADC14SHSR::ADC14SHS_7
|
|
}
|
|
}
|
|
#[doc = "Possible values of the field `ADC14PDIV`"]
|
|
#[derive(Clone, Copy, Debug, PartialEq)]
|
|
pub enum ADC14PDIVR {
|
|
#[doc = "Predivide by 1"]
|
|
ADC14PDIV_0,
|
|
#[doc = "Predivide by 4"]
|
|
ADC14PDIV_1,
|
|
#[doc = "Predivide by 32"]
|
|
ADC14PDIV_2,
|
|
#[doc = "Predivide by 64"]
|
|
ADC14PDIV_3,
|
|
}
|
|
impl ADC14PDIVR {
|
|
#[doc = r" Value of the field as raw bits"]
|
|
#[inline]
|
|
pub fn bits(&self) -> u8 {
|
|
match *self {
|
|
ADC14PDIVR::ADC14PDIV_0 => 0,
|
|
ADC14PDIVR::ADC14PDIV_1 => 1,
|
|
ADC14PDIVR::ADC14PDIV_2 => 2,
|
|
ADC14PDIVR::ADC14PDIV_3 => 3,
|
|
}
|
|
}
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _from(value: u8) -> ADC14PDIVR {
|
|
match value {
|
|
0 => ADC14PDIVR::ADC14PDIV_0,
|
|
1 => ADC14PDIVR::ADC14PDIV_1,
|
|
2 => ADC14PDIVR::ADC14PDIV_2,
|
|
3 => ADC14PDIVR::ADC14PDIV_3,
|
|
_ => unreachable!(),
|
|
}
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14PDIV_0`"]
|
|
#[inline]
|
|
pub fn is_adc14pdiv_0(&self) -> bool {
|
|
*self == ADC14PDIVR::ADC14PDIV_0
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14PDIV_1`"]
|
|
#[inline]
|
|
pub fn is_adc14pdiv_1(&self) -> bool {
|
|
*self == ADC14PDIVR::ADC14PDIV_1
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14PDIV_2`"]
|
|
#[inline]
|
|
pub fn is_adc14pdiv_2(&self) -> bool {
|
|
*self == ADC14PDIVR::ADC14PDIV_2
|
|
}
|
|
#[doc = "Checks if the value of the field is `ADC14PDIV_3`"]
|
|
#[inline]
|
|
pub fn is_adc14pdiv_3(&self) -> bool {
|
|
*self == ADC14PDIVR::ADC14PDIV_3
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `ADC14SC`"]
|
|
pub enum ADC14SCW {
|
|
#[doc = "No sample-and-conversion-start"]
|
|
ADC14SC_0,
|
|
#[doc = "Start sample-and-conversion"]
|
|
ADC14SC_1,
|
|
}
|
|
impl ADC14SCW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> bool {
|
|
match *self {
|
|
ADC14SCW::ADC14SC_0 => false,
|
|
ADC14SCW::ADC14SC_1 => true,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ADC14SCW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ADC14SCW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: ADC14SCW) -> &'a mut W {
|
|
{
|
|
self.bit(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "No sample-and-conversion-start"]
|
|
#[inline]
|
|
pub fn adc14sc_0(self) -> &'a mut W {
|
|
self.variant(ADC14SCW::ADC14SC_0)
|
|
}
|
|
#[doc = "Start sample-and-conversion"]
|
|
#[inline]
|
|
pub fn adc14sc_1(self) -> &'a mut W {
|
|
self.variant(ADC14SCW::ADC14SC_1)
|
|
}
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
|
|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 0;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `ADC14ENC`"]
|
|
pub enum ADC14ENCW {
|
|
#[doc = "ADC14 disabled"]
|
|
ADC14ENC_0,
|
|
#[doc = "ADC14 enabled"]
|
|
ADC14ENC_1,
|
|
}
|
|
impl ADC14ENCW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> bool {
|
|
match *self {
|
|
ADC14ENCW::ADC14ENC_0 => false,
|
|
ADC14ENCW::ADC14ENC_1 => true,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ADC14ENCW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ADC14ENCW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: ADC14ENCW) -> &'a mut W {
|
|
{
|
|
self.bit(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "ADC14 disabled"]
|
|
#[inline]
|
|
pub fn adc14enc_0(self) -> &'a mut W {
|
|
self.variant(ADC14ENCW::ADC14ENC_0)
|
|
}
|
|
#[doc = "ADC14 enabled"]
|
|
#[inline]
|
|
pub fn adc14enc_1(self) -> &'a mut W {
|
|
self.variant(ADC14ENCW::ADC14ENC_1)
|
|
}
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
|
|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 1;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `ADC14ON`"]
|
|
pub enum ADC14ONW {
|
|
#[doc = "ADC14 off"]
|
|
ADC14ON_0,
|
|
#[doc = "ADC14 on. ADC core is ready to power up when a valid conversion is triggered."]
|
|
ADC14ON_1,
|
|
}
|
|
impl ADC14ONW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> bool {
|
|
match *self {
|
|
ADC14ONW::ADC14ON_0 => false,
|
|
ADC14ONW::ADC14ON_1 => true,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ADC14ONW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ADC14ONW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: ADC14ONW) -> &'a mut W {
|
|
{
|
|
self.bit(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "ADC14 off"]
|
|
#[inline]
|
|
pub fn adc14on_0(self) -> &'a mut W {
|
|
self.variant(ADC14ONW::ADC14ON_0)
|
|
}
|
|
#[doc = "ADC14 on. ADC core is ready to power up when a valid conversion is triggered."]
|
|
#[inline]
|
|
pub fn adc14on_1(self) -> &'a mut W {
|
|
self.variant(ADC14ONW::ADC14ON_1)
|
|
}
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
|
|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 4;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `ADC14MSC`"]
|
|
pub enum ADC14MSCW {
|
|
#[doc = "The sampling timer requires a rising edge of the SHI signal to trigger each sample-and-convert"]
|
|
ADC14MSC_0,
|
|
#[doc = "The first rising edge of the SHI signal triggers the sampling timer, but further sample-and-conversions are performed automatically as soon as the prior conversion is completed"]
|
|
ADC14MSC_1,
|
|
}
|
|
impl ADC14MSCW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> bool {
|
|
match *self {
|
|
ADC14MSCW::ADC14MSC_0 => false,
|
|
ADC14MSCW::ADC14MSC_1 => true,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ADC14MSCW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ADC14MSCW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: ADC14MSCW) -> &'a mut W {
|
|
{
|
|
self.bit(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "The sampling timer requires a rising edge of the SHI signal to trigger each sample-and-convert"]
|
|
#[inline]
|
|
pub fn adc14msc_0(self) -> &'a mut W {
|
|
self.variant(ADC14MSCW::ADC14MSC_0)
|
|
}
|
|
#[doc = "The first rising edge of the SHI signal triggers the sampling timer, but further sample-and-conversions are performed automatically as soon as the prior conversion is completed"]
|
|
#[inline]
|
|
pub fn adc14msc_1(self) -> &'a mut W {
|
|
self.variant(ADC14MSCW::ADC14MSC_1)
|
|
}
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
|
|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 7;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `ADC14SHT0`"]
|
|
pub enum ADC14SHT0W {
|
|
#[doc = "4"]
|
|
ADC14SHT0_0,
|
|
#[doc = "8"]
|
|
ADC14SHT0_1,
|
|
#[doc = "16"]
|
|
ADC14SHT0_2,
|
|
#[doc = "32"]
|
|
ADC14SHT0_3,
|
|
#[doc = "64"]
|
|
ADC14SHT0_4,
|
|
#[doc = "96"]
|
|
ADC14SHT0_5,
|
|
#[doc = "128"]
|
|
ADC14SHT0_6,
|
|
#[doc = "192"]
|
|
ADC14SHT0_7,
|
|
}
|
|
impl ADC14SHT0W {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> u8 {
|
|
match *self {
|
|
ADC14SHT0W::ADC14SHT0_0 => 0,
|
|
ADC14SHT0W::ADC14SHT0_1 => 1,
|
|
ADC14SHT0W::ADC14SHT0_2 => 2,
|
|
ADC14SHT0W::ADC14SHT0_3 => 3,
|
|
ADC14SHT0W::ADC14SHT0_4 => 4,
|
|
ADC14SHT0W::ADC14SHT0_5 => 5,
|
|
ADC14SHT0W::ADC14SHT0_6 => 6,
|
|
ADC14SHT0W::ADC14SHT0_7 => 7,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ADC14SHT0W<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ADC14SHT0W<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: ADC14SHT0W) -> &'a mut W {
|
|
unsafe { self.bits(variant._bits()) }
|
|
}
|
|
#[doc = "4"]
|
|
#[inline]
|
|
pub fn adc14sht0_0(self) -> &'a mut W {
|
|
self.variant(ADC14SHT0W::ADC14SHT0_0)
|
|
}
|
|
#[doc = "8"]
|
|
#[inline]
|
|
pub fn adc14sht0_1(self) -> &'a mut W {
|
|
self.variant(ADC14SHT0W::ADC14SHT0_1)
|
|
}
|
|
#[doc = "16"]
|
|
#[inline]
|
|
pub fn adc14sht0_2(self) -> &'a mut W {
|
|
self.variant(ADC14SHT0W::ADC14SHT0_2)
|
|
}
|
|
#[doc = "32"]
|
|
#[inline]
|
|
pub fn adc14sht0_3(self) -> &'a mut W {
|
|
self.variant(ADC14SHT0W::ADC14SHT0_3)
|
|
}
|
|
#[doc = "64"]
|
|
#[inline]
|
|
pub fn adc14sht0_4(self) -> &'a mut W {
|
|
self.variant(ADC14SHT0W::ADC14SHT0_4)
|
|
}
|
|
#[doc = "96"]
|
|
#[inline]
|
|
pub fn adc14sht0_5(self) -> &'a mut W {
|
|
self.variant(ADC14SHT0W::ADC14SHT0_5)
|
|
}
|
|
#[doc = "128"]
|
|
#[inline]
|
|
pub fn adc14sht0_6(self) -> &'a mut W {
|
|
self.variant(ADC14SHT0W::ADC14SHT0_6)
|
|
}
|
|
#[doc = "192"]
|
|
#[inline]
|
|
pub fn adc14sht0_7(self) -> &'a mut W {
|
|
self.variant(ADC14SHT0W::ADC14SHT0_7)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
|
const MASK: u8 = 15;
|
|
const OFFSET: u8 = 8;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `ADC14SHT1`"]
|
|
pub enum ADC14SHT1W {
|
|
#[doc = "4"]
|
|
ADC14SHT1_0,
|
|
#[doc = "8"]
|
|
ADC14SHT1_1,
|
|
#[doc = "16"]
|
|
ADC14SHT1_2,
|
|
#[doc = "32"]
|
|
ADC14SHT1_3,
|
|
#[doc = "64"]
|
|
ADC14SHT1_4,
|
|
#[doc = "96"]
|
|
ADC14SHT1_5,
|
|
#[doc = "128"]
|
|
ADC14SHT1_6,
|
|
#[doc = "192"]
|
|
ADC14SHT1_7,
|
|
}
|
|
impl ADC14SHT1W {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> u8 {
|
|
match *self {
|
|
ADC14SHT1W::ADC14SHT1_0 => 0,
|
|
ADC14SHT1W::ADC14SHT1_1 => 1,
|
|
ADC14SHT1W::ADC14SHT1_2 => 2,
|
|
ADC14SHT1W::ADC14SHT1_3 => 3,
|
|
ADC14SHT1W::ADC14SHT1_4 => 4,
|
|
ADC14SHT1W::ADC14SHT1_5 => 5,
|
|
ADC14SHT1W::ADC14SHT1_6 => 6,
|
|
ADC14SHT1W::ADC14SHT1_7 => 7,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ADC14SHT1W<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ADC14SHT1W<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: ADC14SHT1W) -> &'a mut W {
|
|
unsafe { self.bits(variant._bits()) }
|
|
}
|
|
#[doc = "4"]
|
|
#[inline]
|
|
pub fn adc14sht1_0(self) -> &'a mut W {
|
|
self.variant(ADC14SHT1W::ADC14SHT1_0)
|
|
}
|
|
#[doc = "8"]
|
|
#[inline]
|
|
pub fn adc14sht1_1(self) -> &'a mut W {
|
|
self.variant(ADC14SHT1W::ADC14SHT1_1)
|
|
}
|
|
#[doc = "16"]
|
|
#[inline]
|
|
pub fn adc14sht1_2(self) -> &'a mut W {
|
|
self.variant(ADC14SHT1W::ADC14SHT1_2)
|
|
}
|
|
#[doc = "32"]
|
|
#[inline]
|
|
pub fn adc14sht1_3(self) -> &'a mut W {
|
|
self.variant(ADC14SHT1W::ADC14SHT1_3)
|
|
}
|
|
#[doc = "64"]
|
|
#[inline]
|
|
pub fn adc14sht1_4(self) -> &'a mut W {
|
|
self.variant(ADC14SHT1W::ADC14SHT1_4)
|
|
}
|
|
#[doc = "96"]
|
|
#[inline]
|
|
pub fn adc14sht1_5(self) -> &'a mut W {
|
|
self.variant(ADC14SHT1W::ADC14SHT1_5)
|
|
}
|
|
#[doc = "128"]
|
|
#[inline]
|
|
pub fn adc14sht1_6(self) -> &'a mut W {
|
|
self.variant(ADC14SHT1W::ADC14SHT1_6)
|
|
}
|
|
#[doc = "192"]
|
|
#[inline]
|
|
pub fn adc14sht1_7(self) -> &'a mut W {
|
|
self.variant(ADC14SHT1W::ADC14SHT1_7)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
|
const MASK: u8 = 15;
|
|
const OFFSET: u8 = 12;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `ADC14CONSEQ`"]
|
|
pub enum ADC14CONSEQW {
|
|
#[doc = "Single-channel, single-conversion"]
|
|
ADC14CONSEQ_0,
|
|
#[doc = "Sequence-of-channels"]
|
|
ADC14CONSEQ_1,
|
|
#[doc = "Repeat-single-channel"]
|
|
ADC14CONSEQ_2,
|
|
#[doc = "Repeat-sequence-of-channels"]
|
|
ADC14CONSEQ_3,
|
|
}
|
|
impl ADC14CONSEQW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> u8 {
|
|
match *self {
|
|
ADC14CONSEQW::ADC14CONSEQ_0 => 0,
|
|
ADC14CONSEQW::ADC14CONSEQ_1 => 1,
|
|
ADC14CONSEQW::ADC14CONSEQ_2 => 2,
|
|
ADC14CONSEQW::ADC14CONSEQ_3 => 3,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ADC14CONSEQW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ADC14CONSEQW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: ADC14CONSEQW) -> &'a mut W {
|
|
{
|
|
self.bits(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "Single-channel, single-conversion"]
|
|
#[inline]
|
|
pub fn adc14conseq_0(self) -> &'a mut W {
|
|
self.variant(ADC14CONSEQW::ADC14CONSEQ_0)
|
|
}
|
|
#[doc = "Sequence-of-channels"]
|
|
#[inline]
|
|
pub fn adc14conseq_1(self) -> &'a mut W {
|
|
self.variant(ADC14CONSEQW::ADC14CONSEQ_1)
|
|
}
|
|
#[doc = "Repeat-single-channel"]
|
|
#[inline]
|
|
pub fn adc14conseq_2(self) -> &'a mut W {
|
|
self.variant(ADC14CONSEQW::ADC14CONSEQ_2)
|
|
}
|
|
#[doc = "Repeat-sequence-of-channels"]
|
|
#[inline]
|
|
pub fn adc14conseq_3(self) -> &'a mut W {
|
|
self.variant(ADC14CONSEQW::ADC14CONSEQ_3)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bits(self, value: u8) -> &'a mut W {
|
|
const MASK: u8 = 3;
|
|
const OFFSET: u8 = 17;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `ADC14SSEL`"]
|
|
pub enum ADC14SSELW {
|
|
#[doc = "MODCLK"]
|
|
ADC14SSEL_0,
|
|
#[doc = "SYSCLK"]
|
|
ADC14SSEL_1,
|
|
#[doc = "ACLK"]
|
|
ADC14SSEL_2,
|
|
#[doc = "MCLK"]
|
|
ADC14SSEL_3,
|
|
#[doc = "SMCLK"]
|
|
ADC14SSEL_4,
|
|
#[doc = "HSMCLK"]
|
|
ADC14SSEL_5,
|
|
}
|
|
impl ADC14SSELW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> u8 {
|
|
match *self {
|
|
ADC14SSELW::ADC14SSEL_0 => 0,
|
|
ADC14SSELW::ADC14SSEL_1 => 1,
|
|
ADC14SSELW::ADC14SSEL_2 => 2,
|
|
ADC14SSELW::ADC14SSEL_3 => 3,
|
|
ADC14SSELW::ADC14SSEL_4 => 4,
|
|
ADC14SSELW::ADC14SSEL_5 => 5,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ADC14SSELW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ADC14SSELW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: ADC14SSELW) -> &'a mut W {
|
|
unsafe { self.bits(variant._bits()) }
|
|
}
|
|
#[doc = "MODCLK"]
|
|
#[inline]
|
|
pub fn adc14ssel_0(self) -> &'a mut W {
|
|
self.variant(ADC14SSELW::ADC14SSEL_0)
|
|
}
|
|
#[doc = "SYSCLK"]
|
|
#[inline]
|
|
pub fn adc14ssel_1(self) -> &'a mut W {
|
|
self.variant(ADC14SSELW::ADC14SSEL_1)
|
|
}
|
|
#[doc = "ACLK"]
|
|
#[inline]
|
|
pub fn adc14ssel_2(self) -> &'a mut W {
|
|
self.variant(ADC14SSELW::ADC14SSEL_2)
|
|
}
|
|
#[doc = "MCLK"]
|
|
#[inline]
|
|
pub fn adc14ssel_3(self) -> &'a mut W {
|
|
self.variant(ADC14SSELW::ADC14SSEL_3)
|
|
}
|
|
#[doc = "SMCLK"]
|
|
#[inline]
|
|
pub fn adc14ssel_4(self) -> &'a mut W {
|
|
self.variant(ADC14SSELW::ADC14SSEL_4)
|
|
}
|
|
#[doc = "HSMCLK"]
|
|
#[inline]
|
|
pub fn adc14ssel_5(self) -> &'a mut W {
|
|
self.variant(ADC14SSELW::ADC14SSEL_5)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
|
const MASK: u8 = 7;
|
|
const OFFSET: u8 = 19;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `ADC14DIV`"]
|
|
pub enum ADC14DIVW {
|
|
#[doc = "/1"]
|
|
ADC14DIV_0,
|
|
#[doc = "/2"]
|
|
ADC14DIV_1,
|
|
#[doc = "/3"]
|
|
ADC14DIV_2,
|
|
#[doc = "/4"]
|
|
ADC14DIV_3,
|
|
#[doc = "/5"]
|
|
ADC14DIV_4,
|
|
#[doc = "/6"]
|
|
ADC14DIV_5,
|
|
#[doc = "/7"]
|
|
ADC14DIV_6,
|
|
#[doc = "/8"]
|
|
ADC14DIV_7,
|
|
}
|
|
impl ADC14DIVW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> u8 {
|
|
match *self {
|
|
ADC14DIVW::ADC14DIV_0 => 0,
|
|
ADC14DIVW::ADC14DIV_1 => 1,
|
|
ADC14DIVW::ADC14DIV_2 => 2,
|
|
ADC14DIVW::ADC14DIV_3 => 3,
|
|
ADC14DIVW::ADC14DIV_4 => 4,
|
|
ADC14DIVW::ADC14DIV_5 => 5,
|
|
ADC14DIVW::ADC14DIV_6 => 6,
|
|
ADC14DIVW::ADC14DIV_7 => 7,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ADC14DIVW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ADC14DIVW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: ADC14DIVW) -> &'a mut W {
|
|
{
|
|
self.bits(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "/1"]
|
|
#[inline]
|
|
pub fn adc14div_0(self) -> &'a mut W {
|
|
self.variant(ADC14DIVW::ADC14DIV_0)
|
|
}
|
|
#[doc = "/2"]
|
|
#[inline]
|
|
pub fn adc14div_1(self) -> &'a mut W {
|
|
self.variant(ADC14DIVW::ADC14DIV_1)
|
|
}
|
|
#[doc = "/3"]
|
|
#[inline]
|
|
pub fn adc14div_2(self) -> &'a mut W {
|
|
self.variant(ADC14DIVW::ADC14DIV_2)
|
|
}
|
|
#[doc = "/4"]
|
|
#[inline]
|
|
pub fn adc14div_3(self) -> &'a mut W {
|
|
self.variant(ADC14DIVW::ADC14DIV_3)
|
|
}
|
|
#[doc = "/5"]
|
|
#[inline]
|
|
pub fn adc14div_4(self) -> &'a mut W {
|
|
self.variant(ADC14DIVW::ADC14DIV_4)
|
|
}
|
|
#[doc = "/6"]
|
|
#[inline]
|
|
pub fn adc14div_5(self) -> &'a mut W {
|
|
self.variant(ADC14DIVW::ADC14DIV_5)
|
|
}
|
|
#[doc = "/7"]
|
|
#[inline]
|
|
pub fn adc14div_6(self) -> &'a mut W {
|
|
self.variant(ADC14DIVW::ADC14DIV_6)
|
|
}
|
|
#[doc = "/8"]
|
|
#[inline]
|
|
pub fn adc14div_7(self) -> &'a mut W {
|
|
self.variant(ADC14DIVW::ADC14DIV_7)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bits(self, value: u8) -> &'a mut W {
|
|
const MASK: u8 = 7;
|
|
const OFFSET: u8 = 22;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `ADC14ISSH`"]
|
|
pub enum ADC14ISSHW {
|
|
#[doc = "The sample-input signal is not inverted"]
|
|
ADC14ISSH_0,
|
|
#[doc = "The sample-input signal is inverted"]
|
|
ADC14ISSH_1,
|
|
}
|
|
impl ADC14ISSHW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> bool {
|
|
match *self {
|
|
ADC14ISSHW::ADC14ISSH_0 => false,
|
|
ADC14ISSHW::ADC14ISSH_1 => true,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ADC14ISSHW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ADC14ISSHW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: ADC14ISSHW) -> &'a mut W {
|
|
{
|
|
self.bit(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "The sample-input signal is not inverted"]
|
|
#[inline]
|
|
pub fn adc14issh_0(self) -> &'a mut W {
|
|
self.variant(ADC14ISSHW::ADC14ISSH_0)
|
|
}
|
|
#[doc = "The sample-input signal is inverted"]
|
|
#[inline]
|
|
pub fn adc14issh_1(self) -> &'a mut W {
|
|
self.variant(ADC14ISSHW::ADC14ISSH_1)
|
|
}
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
|
|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 25;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `ADC14SHP`"]
|
|
pub enum ADC14SHPW {
|
|
#[doc = "SAMPCON signal is sourced from the sample-input signal"]
|
|
ADC14SHP_0,
|
|
#[doc = "SAMPCON signal is sourced from the sampling timer"]
|
|
ADC14SHP_1,
|
|
}
|
|
impl ADC14SHPW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> bool {
|
|
match *self {
|
|
ADC14SHPW::ADC14SHP_0 => false,
|
|
ADC14SHPW::ADC14SHP_1 => true,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ADC14SHPW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ADC14SHPW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: ADC14SHPW) -> &'a mut W {
|
|
{
|
|
self.bit(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "SAMPCON signal is sourced from the sample-input signal"]
|
|
#[inline]
|
|
pub fn adc14shp_0(self) -> &'a mut W {
|
|
self.variant(ADC14SHPW::ADC14SHP_0)
|
|
}
|
|
#[doc = "SAMPCON signal is sourced from the sampling timer"]
|
|
#[inline]
|
|
pub fn adc14shp_1(self) -> &'a mut W {
|
|
self.variant(ADC14SHPW::ADC14SHP_1)
|
|
}
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
|
|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 26;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `ADC14SHS`"]
|
|
pub enum ADC14SHSW {
|
|
#[doc = "ADC14SC bit"]
|
|
ADC14SHS_0,
|
|
#[doc = "See device-specific data sheet for source"]
|
|
ADC14SHS_1,
|
|
#[doc = "See device-specific data sheet for source"]
|
|
ADC14SHS_2,
|
|
#[doc = "See device-specific data sheet for source"]
|
|
ADC14SHS_3,
|
|
#[doc = "See device-specific data sheet for source"]
|
|
ADC14SHS_4,
|
|
#[doc = "See device-specific data sheet for source"]
|
|
ADC14SHS_5,
|
|
#[doc = "See device-specific data sheet for source"]
|
|
ADC14SHS_6,
|
|
#[doc = "See device-specific data sheet for source"]
|
|
ADC14SHS_7,
|
|
}
|
|
impl ADC14SHSW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> u8 {
|
|
match *self {
|
|
ADC14SHSW::ADC14SHS_0 => 0,
|
|
ADC14SHSW::ADC14SHS_1 => 1,
|
|
ADC14SHSW::ADC14SHS_2 => 2,
|
|
ADC14SHSW::ADC14SHS_3 => 3,
|
|
ADC14SHSW::ADC14SHS_4 => 4,
|
|
ADC14SHSW::ADC14SHS_5 => 5,
|
|
ADC14SHSW::ADC14SHS_6 => 6,
|
|
ADC14SHSW::ADC14SHS_7 => 7,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ADC14SHSW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ADC14SHSW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: ADC14SHSW) -> &'a mut W {
|
|
{
|
|
self.bits(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "ADC14SC bit"]
|
|
#[inline]
|
|
pub fn adc14shs_0(self) -> &'a mut W {
|
|
self.variant(ADC14SHSW::ADC14SHS_0)
|
|
}
|
|
#[doc = "See device-specific data sheet for source"]
|
|
#[inline]
|
|
pub fn adc14shs_1(self) -> &'a mut W {
|
|
self.variant(ADC14SHSW::ADC14SHS_1)
|
|
}
|
|
#[doc = "See device-specific data sheet for source"]
|
|
#[inline]
|
|
pub fn adc14shs_2(self) -> &'a mut W {
|
|
self.variant(ADC14SHSW::ADC14SHS_2)
|
|
}
|
|
#[doc = "See device-specific data sheet for source"]
|
|
#[inline]
|
|
pub fn adc14shs_3(self) -> &'a mut W {
|
|
self.variant(ADC14SHSW::ADC14SHS_3)
|
|
}
|
|
#[doc = "See device-specific data sheet for source"]
|
|
#[inline]
|
|
pub fn adc14shs_4(self) -> &'a mut W {
|
|
self.variant(ADC14SHSW::ADC14SHS_4)
|
|
}
|
|
#[doc = "See device-specific data sheet for source"]
|
|
#[inline]
|
|
pub fn adc14shs_5(self) -> &'a mut W {
|
|
self.variant(ADC14SHSW::ADC14SHS_5)
|
|
}
|
|
#[doc = "See device-specific data sheet for source"]
|
|
#[inline]
|
|
pub fn adc14shs_6(self) -> &'a mut W {
|
|
self.variant(ADC14SHSW::ADC14SHS_6)
|
|
}
|
|
#[doc = "See device-specific data sheet for source"]
|
|
#[inline]
|
|
pub fn adc14shs_7(self) -> &'a mut W {
|
|
self.variant(ADC14SHSW::ADC14SHS_7)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bits(self, value: u8) -> &'a mut W {
|
|
const MASK: u8 = 7;
|
|
const OFFSET: u8 = 27;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `ADC14PDIV`"]
|
|
pub enum ADC14PDIVW {
|
|
#[doc = "Predivide by 1"]
|
|
ADC14PDIV_0,
|
|
#[doc = "Predivide by 4"]
|
|
ADC14PDIV_1,
|
|
#[doc = "Predivide by 32"]
|
|
ADC14PDIV_2,
|
|
#[doc = "Predivide by 64"]
|
|
ADC14PDIV_3,
|
|
}
|
|
impl ADC14PDIVW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> u8 {
|
|
match *self {
|
|
ADC14PDIVW::ADC14PDIV_0 => 0,
|
|
ADC14PDIVW::ADC14PDIV_1 => 1,
|
|
ADC14PDIVW::ADC14PDIV_2 => 2,
|
|
ADC14PDIVW::ADC14PDIV_3 => 3,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ADC14PDIVW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ADC14PDIVW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: ADC14PDIVW) -> &'a mut W {
|
|
{
|
|
self.bits(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "Predivide by 1"]
|
|
#[inline]
|
|
pub fn adc14pdiv_0(self) -> &'a mut W {
|
|
self.variant(ADC14PDIVW::ADC14PDIV_0)
|
|
}
|
|
#[doc = "Predivide by 4"]
|
|
#[inline]
|
|
pub fn adc14pdiv_1(self) -> &'a mut W {
|
|
self.variant(ADC14PDIVW::ADC14PDIV_1)
|
|
}
|
|
#[doc = "Predivide by 32"]
|
|
#[inline]
|
|
pub fn adc14pdiv_2(self) -> &'a mut W {
|
|
self.variant(ADC14PDIVW::ADC14PDIV_2)
|
|
}
|
|
#[doc = "Predivide by 64"]
|
|
#[inline]
|
|
pub fn adc14pdiv_3(self) -> &'a mut W {
|
|
self.variant(ADC14PDIVW::ADC14PDIV_3)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bits(self, value: u8) -> &'a mut W {
|
|
const MASK: u8 = 3;
|
|
const OFFSET: u8 = 30;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
impl R {
|
|
#[doc = r" Value of the register as raw bits"]
|
|
#[inline]
|
|
pub fn bits(&self) -> u32 {
|
|
self.bits
|
|
}
|
|
#[doc = "Bit 0 - ADC14 start conversion"]
|
|
#[inline]
|
|
pub fn adc14sc(&self) -> ADC14SCR {
|
|
ADC14SCR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 0;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
#[doc = "Bit 1 - ADC14 enable conversion"]
|
|
#[inline]
|
|
pub fn adc14enc(&self) -> ADC14ENCR {
|
|
ADC14ENCR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 1;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
#[doc = "Bit 4 - ADC14 on"]
|
|
#[inline]
|
|
pub fn adc14on(&self) -> ADC14ONR {
|
|
ADC14ONR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 4;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
#[doc = "Bit 7 - ADC14 multiple sample and conversion"]
|
|
#[inline]
|
|
pub fn adc14msc(&self) -> ADC14MSCR {
|
|
ADC14MSCR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 7;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
#[doc = "Bits 8:11 - ADC14 sample-and-hold time"]
|
|
#[inline]
|
|
pub fn adc14sht0(&self) -> ADC14SHT0R {
|
|
ADC14SHT0R::_from({
|
|
const MASK: u8 = 15;
|
|
const OFFSET: u8 = 8;
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
|
})
|
|
}
|
|
#[doc = "Bits 12:15 - ADC14 sample-and-hold time"]
|
|
#[inline]
|
|
pub fn adc14sht1(&self) -> ADC14SHT1R {
|
|
ADC14SHT1R::_from({
|
|
const MASK: u8 = 15;
|
|
const OFFSET: u8 = 12;
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
|
})
|
|
}
|
|
#[doc = "Bit 16 - ADC14 busy"]
|
|
#[inline]
|
|
pub fn adc14busy(&self) -> ADC14BUSYR {
|
|
ADC14BUSYR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 16;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
#[doc = "Bits 17:18 - ADC14 conversion sequence mode select"]
|
|
#[inline]
|
|
pub fn adc14conseq(&self) -> ADC14CONSEQR {
|
|
ADC14CONSEQR::_from({
|
|
const MASK: u8 = 3;
|
|
const OFFSET: u8 = 17;
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
|
})
|
|
}
|
|
#[doc = "Bits 19:21 - ADC14 clock source select"]
|
|
#[inline]
|
|
pub fn adc14ssel(&self) -> ADC14SSELR {
|
|
ADC14SSELR::_from({
|
|
const MASK: u8 = 7;
|
|
const OFFSET: u8 = 19;
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
|
})
|
|
}
|
|
#[doc = "Bits 22:24 - ADC14 clock divider"]
|
|
#[inline]
|
|
pub fn adc14div(&self) -> ADC14DIVR {
|
|
ADC14DIVR::_from({
|
|
const MASK: u8 = 7;
|
|
const OFFSET: u8 = 22;
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
|
})
|
|
}
|
|
#[doc = "Bit 25 - ADC14 invert signal sample-and-hold"]
|
|
#[inline]
|
|
pub fn adc14issh(&self) -> ADC14ISSHR {
|
|
ADC14ISSHR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 25;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
#[doc = "Bit 26 - ADC14 sample-and-hold pulse-mode select"]
|
|
#[inline]
|
|
pub fn adc14shp(&self) -> ADC14SHPR {
|
|
ADC14SHPR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 26;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
#[doc = "Bits 27:29 - ADC14 sample-and-hold source select"]
|
|
#[inline]
|
|
pub fn adc14shs(&self) -> ADC14SHSR {
|
|
ADC14SHSR::_from({
|
|
const MASK: u8 = 7;
|
|
const OFFSET: u8 = 27;
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
|
})
|
|
}
|
|
#[doc = "Bits 30:31 - ADC14 predivider"]
|
|
#[inline]
|
|
pub fn adc14pdiv(&self) -> ADC14PDIVR {
|
|
ADC14PDIVR::_from({
|
|
const MASK: u8 = 3;
|
|
const OFFSET: u8 = 30;
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
|
})
|
|
}
|
|
}
|
|
impl W {
|
|
#[doc = r" Reset value of the register"]
|
|
#[inline]
|
|
pub fn reset_value() -> W {
|
|
W { bits: 0 }
|
|
}
|
|
#[doc = r" Writes raw bits to the register"]
|
|
#[inline]
|
|
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
|
self.bits = bits;
|
|
self
|
|
}
|
|
#[doc = "Bit 0 - ADC14 start conversion"]
|
|
#[inline]
|
|
pub fn adc14sc(&mut self) -> _ADC14SCW {
|
|
_ADC14SCW { w: self }
|
|
}
|
|
#[doc = "Bit 1 - ADC14 enable conversion"]
|
|
#[inline]
|
|
pub fn adc14enc(&mut self) -> _ADC14ENCW {
|
|
_ADC14ENCW { w: self }
|
|
}
|
|
#[doc = "Bit 4 - ADC14 on"]
|
|
#[inline]
|
|
pub fn adc14on(&mut self) -> _ADC14ONW {
|
|
_ADC14ONW { w: self }
|
|
}
|
|
#[doc = "Bit 7 - ADC14 multiple sample and conversion"]
|
|
#[inline]
|
|
pub fn adc14msc(&mut self) -> _ADC14MSCW {
|
|
_ADC14MSCW { w: self }
|
|
}
|
|
#[doc = "Bits 8:11 - ADC14 sample-and-hold time"]
|
|
#[inline]
|
|
pub fn adc14sht0(&mut self) -> _ADC14SHT0W {
|
|
_ADC14SHT0W { w: self }
|
|
}
|
|
#[doc = "Bits 12:15 - ADC14 sample-and-hold time"]
|
|
#[inline]
|
|
pub fn adc14sht1(&mut self) -> _ADC14SHT1W {
|
|
_ADC14SHT1W { w: self }
|
|
}
|
|
#[doc = "Bits 17:18 - ADC14 conversion sequence mode select"]
|
|
#[inline]
|
|
pub fn adc14conseq(&mut self) -> _ADC14CONSEQW {
|
|
_ADC14CONSEQW { w: self }
|
|
}
|
|
#[doc = "Bits 19:21 - ADC14 clock source select"]
|
|
#[inline]
|
|
pub fn adc14ssel(&mut self) -> _ADC14SSELW {
|
|
_ADC14SSELW { w: self }
|
|
}
|
|
#[doc = "Bits 22:24 - ADC14 clock divider"]
|
|
#[inline]
|
|
pub fn adc14div(&mut self) -> _ADC14DIVW {
|
|
_ADC14DIVW { w: self }
|
|
}
|
|
#[doc = "Bit 25 - ADC14 invert signal sample-and-hold"]
|
|
#[inline]
|
|
pub fn adc14issh(&mut self) -> _ADC14ISSHW {
|
|
_ADC14ISSHW { w: self }
|
|
}
|
|
#[doc = "Bit 26 - ADC14 sample-and-hold pulse-mode select"]
|
|
#[inline]
|
|
pub fn adc14shp(&mut self) -> _ADC14SHPW {
|
|
_ADC14SHPW { w: self }
|
|
}
|
|
#[doc = "Bits 27:29 - ADC14 sample-and-hold source select"]
|
|
#[inline]
|
|
pub fn adc14shs(&mut self) -> _ADC14SHSW {
|
|
_ADC14SHSW { w: self }
|
|
}
|
|
#[doc = "Bits 30:31 - ADC14 predivider"]
|
|
#[inline]
|
|
pub fn adc14pdiv(&mut self) -> _ADC14PDIVW {
|
|
_ADC14PDIVW { w: self }
|
|
}
|
|
}
|