1799 lines
54 KiB
Rust
1799 lines
54 KiB
Rust
#[doc = r" Value read from the register"]
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pub struct R {
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bits: u16,
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}
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#[doc = r" Value to write to the register"]
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pub struct W {
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bits: u16,
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}
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impl super::CEXCTL2 {
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#[doc = r" Modifies the contents of the register"]
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#[inline]
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pub fn modify<F>(&self, f: F)
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where
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for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
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{
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let bits = self.register.get();
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let r = R { bits: bits };
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let mut w = W { bits: bits };
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f(&r, &mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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pub fn write<F>(&self, f: F)
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where
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F: FnOnce(&mut W) -> &mut W,
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{
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let mut w = W::reset_value();
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f(&mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Writes the reset value to the register"]
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#[inline]
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pub fn reset(&self) {
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self.write(|w| w)
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}
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}
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#[doc = "Possible values of the field `CEREF0`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum CEREF0R {
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#[doc = "Reference resistor tap for setting 0."]
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CEREF0_0,
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#[doc = "Reference resistor tap for setting 1."]
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CEREF0_1,
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#[doc = "Reference resistor tap for setting 2."]
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CEREF0_2,
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#[doc = "Reference resistor tap for setting 3."]
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CEREF0_3,
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#[doc = "Reference resistor tap for setting 4."]
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CEREF0_4,
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#[doc = "Reference resistor tap for setting 5."]
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CEREF0_5,
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#[doc = "Reference resistor tap for setting 6."]
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CEREF0_6,
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#[doc = "Reference resistor tap for setting 7."]
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CEREF0_7,
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#[doc = "Reference resistor tap for setting 8."]
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CEREF0_8,
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#[doc = "Reference resistor tap for setting 9."]
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CEREF0_9,
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#[doc = "Reference resistor tap for setting 10."]
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CEREF0_10,
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#[doc = "Reference resistor tap for setting 11."]
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CEREF0_11,
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#[doc = "Reference resistor tap for setting 12."]
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CEREF0_12,
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#[doc = "Reference resistor tap for setting 13."]
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CEREF0_13,
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#[doc = "Reference resistor tap for setting 14."]
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CEREF0_14,
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#[doc = "Reference resistor tap for setting 15."]
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CEREF0_15,
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#[doc = "Reference resistor tap for setting 16."]
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CEREF0_16,
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#[doc = "Reference resistor tap for setting 17."]
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CEREF0_17,
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#[doc = "Reference resistor tap for setting 18."]
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CEREF0_18,
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#[doc = "Reference resistor tap for setting 19."]
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CEREF0_19,
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#[doc = "Reference resistor tap for setting 20."]
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CEREF0_20,
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#[doc = "Reference resistor tap for setting 21."]
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CEREF0_21,
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#[doc = "Reference resistor tap for setting 22."]
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CEREF0_22,
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#[doc = "Reference resistor tap for setting 23."]
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CEREF0_23,
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#[doc = "Reference resistor tap for setting 24."]
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CEREF0_24,
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#[doc = "Reference resistor tap for setting 25."]
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CEREF0_25,
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#[doc = "Reference resistor tap for setting 26."]
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CEREF0_26,
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#[doc = "Reference resistor tap for setting 27."]
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CEREF0_27,
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#[doc = "Reference resistor tap for setting 28."]
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CEREF0_28,
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#[doc = "Reference resistor tap for setting 29."]
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CEREF0_29,
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#[doc = "Reference resistor tap for setting 30."]
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CEREF0_30,
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#[doc = "Reference resistor tap for setting 31."]
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CEREF0_31,
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}
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impl CEREF0R {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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match *self {
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CEREF0R::CEREF0_0 => 0,
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CEREF0R::CEREF0_1 => 1,
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CEREF0R::CEREF0_2 => 2,
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CEREF0R::CEREF0_3 => 3,
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CEREF0R::CEREF0_4 => 4,
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CEREF0R::CEREF0_5 => 5,
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CEREF0R::CEREF0_6 => 6,
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CEREF0R::CEREF0_7 => 7,
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CEREF0R::CEREF0_8 => 8,
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CEREF0R::CEREF0_9 => 9,
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CEREF0R::CEREF0_10 => 10,
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CEREF0R::CEREF0_11 => 11,
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CEREF0R::CEREF0_12 => 12,
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CEREF0R::CEREF0_13 => 13,
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CEREF0R::CEREF0_14 => 14,
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CEREF0R::CEREF0_15 => 15,
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CEREF0R::CEREF0_16 => 16,
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CEREF0R::CEREF0_17 => 17,
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CEREF0R::CEREF0_18 => 18,
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CEREF0R::CEREF0_19 => 19,
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CEREF0R::CEREF0_20 => 20,
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CEREF0R::CEREF0_21 => 21,
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CEREF0R::CEREF0_22 => 22,
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CEREF0R::CEREF0_23 => 23,
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CEREF0R::CEREF0_24 => 24,
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CEREF0R::CEREF0_25 => 25,
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CEREF0R::CEREF0_26 => 26,
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CEREF0R::CEREF0_27 => 27,
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CEREF0R::CEREF0_28 => 28,
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CEREF0R::CEREF0_29 => 29,
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CEREF0R::CEREF0_30 => 30,
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CEREF0R::CEREF0_31 => 31,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: u8) -> CEREF0R {
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match value {
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0 => CEREF0R::CEREF0_0,
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1 => CEREF0R::CEREF0_1,
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2 => CEREF0R::CEREF0_2,
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3 => CEREF0R::CEREF0_3,
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4 => CEREF0R::CEREF0_4,
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5 => CEREF0R::CEREF0_5,
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6 => CEREF0R::CEREF0_6,
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7 => CEREF0R::CEREF0_7,
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8 => CEREF0R::CEREF0_8,
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9 => CEREF0R::CEREF0_9,
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10 => CEREF0R::CEREF0_10,
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11 => CEREF0R::CEREF0_11,
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12 => CEREF0R::CEREF0_12,
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13 => CEREF0R::CEREF0_13,
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14 => CEREF0R::CEREF0_14,
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15 => CEREF0R::CEREF0_15,
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16 => CEREF0R::CEREF0_16,
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17 => CEREF0R::CEREF0_17,
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18 => CEREF0R::CEREF0_18,
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19 => CEREF0R::CEREF0_19,
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20 => CEREF0R::CEREF0_20,
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21 => CEREF0R::CEREF0_21,
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22 => CEREF0R::CEREF0_22,
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23 => CEREF0R::CEREF0_23,
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24 => CEREF0R::CEREF0_24,
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25 => CEREF0R::CEREF0_25,
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26 => CEREF0R::CEREF0_26,
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27 => CEREF0R::CEREF0_27,
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28 => CEREF0R::CEREF0_28,
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29 => CEREF0R::CEREF0_29,
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30 => CEREF0R::CEREF0_30,
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31 => CEREF0R::CEREF0_31,
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_ => unreachable!(),
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}
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}
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#[doc = "Checks if the value of the field is `CEREF0_0`"]
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#[inline]
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pub fn is_ceref0_0(&self) -> bool {
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*self == CEREF0R::CEREF0_0
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}
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#[doc = "Checks if the value of the field is `CEREF0_1`"]
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#[inline]
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pub fn is_ceref0_1(&self) -> bool {
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*self == CEREF0R::CEREF0_1
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}
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#[doc = "Checks if the value of the field is `CEREF0_2`"]
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#[inline]
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pub fn is_ceref0_2(&self) -> bool {
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*self == CEREF0R::CEREF0_2
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}
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#[doc = "Checks if the value of the field is `CEREF0_3`"]
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#[inline]
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pub fn is_ceref0_3(&self) -> bool {
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*self == CEREF0R::CEREF0_3
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}
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#[doc = "Checks if the value of the field is `CEREF0_4`"]
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#[inline]
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pub fn is_ceref0_4(&self) -> bool {
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*self == CEREF0R::CEREF0_4
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}
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#[doc = "Checks if the value of the field is `CEREF0_5`"]
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#[inline]
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pub fn is_ceref0_5(&self) -> bool {
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*self == CEREF0R::CEREF0_5
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}
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#[doc = "Checks if the value of the field is `CEREF0_6`"]
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#[inline]
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pub fn is_ceref0_6(&self) -> bool {
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*self == CEREF0R::CEREF0_6
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}
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#[doc = "Checks if the value of the field is `CEREF0_7`"]
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#[inline]
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pub fn is_ceref0_7(&self) -> bool {
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*self == CEREF0R::CEREF0_7
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}
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#[doc = "Checks if the value of the field is `CEREF0_8`"]
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#[inline]
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pub fn is_ceref0_8(&self) -> bool {
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*self == CEREF0R::CEREF0_8
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}
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#[doc = "Checks if the value of the field is `CEREF0_9`"]
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#[inline]
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pub fn is_ceref0_9(&self) -> bool {
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*self == CEREF0R::CEREF0_9
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}
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#[doc = "Checks if the value of the field is `CEREF0_10`"]
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#[inline]
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pub fn is_ceref0_10(&self) -> bool {
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*self == CEREF0R::CEREF0_10
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}
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#[doc = "Checks if the value of the field is `CEREF0_11`"]
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#[inline]
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pub fn is_ceref0_11(&self) -> bool {
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*self == CEREF0R::CEREF0_11
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}
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#[doc = "Checks if the value of the field is `CEREF0_12`"]
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#[inline]
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pub fn is_ceref0_12(&self) -> bool {
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*self == CEREF0R::CEREF0_12
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}
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#[doc = "Checks if the value of the field is `CEREF0_13`"]
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#[inline]
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pub fn is_ceref0_13(&self) -> bool {
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*self == CEREF0R::CEREF0_13
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}
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#[doc = "Checks if the value of the field is `CEREF0_14`"]
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#[inline]
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pub fn is_ceref0_14(&self) -> bool {
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*self == CEREF0R::CEREF0_14
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}
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#[doc = "Checks if the value of the field is `CEREF0_15`"]
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#[inline]
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pub fn is_ceref0_15(&self) -> bool {
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*self == CEREF0R::CEREF0_15
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}
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#[doc = "Checks if the value of the field is `CEREF0_16`"]
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#[inline]
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pub fn is_ceref0_16(&self) -> bool {
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*self == CEREF0R::CEREF0_16
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}
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#[doc = "Checks if the value of the field is `CEREF0_17`"]
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#[inline]
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pub fn is_ceref0_17(&self) -> bool {
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*self == CEREF0R::CEREF0_17
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}
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#[doc = "Checks if the value of the field is `CEREF0_18`"]
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#[inline]
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pub fn is_ceref0_18(&self) -> bool {
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*self == CEREF0R::CEREF0_18
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}
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#[doc = "Checks if the value of the field is `CEREF0_19`"]
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#[inline]
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pub fn is_ceref0_19(&self) -> bool {
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*self == CEREF0R::CEREF0_19
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}
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#[doc = "Checks if the value of the field is `CEREF0_20`"]
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#[inline]
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pub fn is_ceref0_20(&self) -> bool {
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*self == CEREF0R::CEREF0_20
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}
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#[doc = "Checks if the value of the field is `CEREF0_21`"]
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#[inline]
|
|
pub fn is_ceref0_21(&self) -> bool {
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*self == CEREF0R::CEREF0_21
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}
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#[doc = "Checks if the value of the field is `CEREF0_22`"]
|
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#[inline]
|
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pub fn is_ceref0_22(&self) -> bool {
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*self == CEREF0R::CEREF0_22
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}
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#[doc = "Checks if the value of the field is `CEREF0_23`"]
|
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#[inline]
|
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pub fn is_ceref0_23(&self) -> bool {
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*self == CEREF0R::CEREF0_23
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}
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#[doc = "Checks if the value of the field is `CEREF0_24`"]
|
|
#[inline]
|
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pub fn is_ceref0_24(&self) -> bool {
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*self == CEREF0R::CEREF0_24
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}
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#[doc = "Checks if the value of the field is `CEREF0_25`"]
|
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#[inline]
|
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pub fn is_ceref0_25(&self) -> bool {
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*self == CEREF0R::CEREF0_25
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}
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#[doc = "Checks if the value of the field is `CEREF0_26`"]
|
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#[inline]
|
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pub fn is_ceref0_26(&self) -> bool {
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*self == CEREF0R::CEREF0_26
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}
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#[doc = "Checks if the value of the field is `CEREF0_27`"]
|
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#[inline]
|
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pub fn is_ceref0_27(&self) -> bool {
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*self == CEREF0R::CEREF0_27
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}
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#[doc = "Checks if the value of the field is `CEREF0_28`"]
|
|
#[inline]
|
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pub fn is_ceref0_28(&self) -> bool {
|
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*self == CEREF0R::CEREF0_28
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}
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#[doc = "Checks if the value of the field is `CEREF0_29`"]
|
|
#[inline]
|
|
pub fn is_ceref0_29(&self) -> bool {
|
|
*self == CEREF0R::CEREF0_29
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF0_30`"]
|
|
#[inline]
|
|
pub fn is_ceref0_30(&self) -> bool {
|
|
*self == CEREF0R::CEREF0_30
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF0_31`"]
|
|
#[inline]
|
|
pub fn is_ceref0_31(&self) -> bool {
|
|
*self == CEREF0R::CEREF0_31
|
|
}
|
|
}
|
|
#[doc = "Possible values of the field `CERSEL`"]
|
|
#[derive(Clone, Copy, Debug, PartialEq)]
|
|
pub enum CERSELR {
|
|
#[doc = "When CEEX = 0, VREF is applied to the V+ terminal; When CEEX = 1, VREF is applied to the V- terminal"]
|
|
CERSEL_0,
|
|
#[doc = "When CEEX = 0, VREF is applied to the V- terminal; When CEEX = 1, VREF is applied to the V+ terminal"]
|
|
CERSEL_1,
|
|
}
|
|
impl CERSELR {
|
|
#[doc = r" Returns `true` if the bit is clear (0)"]
|
|
#[inline]
|
|
pub fn bit_is_clear(&self) -> bool {
|
|
!self.bit()
|
|
}
|
|
#[doc = r" Returns `true` if the bit is set (1)"]
|
|
#[inline]
|
|
pub fn bit_is_set(&self) -> bool {
|
|
self.bit()
|
|
}
|
|
#[doc = r" Value of the field as raw bits"]
|
|
#[inline]
|
|
pub fn bit(&self) -> bool {
|
|
match *self {
|
|
CERSELR::CERSEL_0 => false,
|
|
CERSELR::CERSEL_1 => true,
|
|
}
|
|
}
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _from(value: bool) -> CERSELR {
|
|
match value {
|
|
false => CERSELR::CERSEL_0,
|
|
true => CERSELR::CERSEL_1,
|
|
}
|
|
}
|
|
#[doc = "Checks if the value of the field is `CERSEL_0`"]
|
|
#[inline]
|
|
pub fn is_cersel_0(&self) -> bool {
|
|
*self == CERSELR::CERSEL_0
|
|
}
|
|
#[doc = "Checks if the value of the field is `CERSEL_1`"]
|
|
#[inline]
|
|
pub fn is_cersel_1(&self) -> bool {
|
|
*self == CERSELR::CERSEL_1
|
|
}
|
|
}
|
|
#[doc = "Possible values of the field `CERS`"]
|
|
#[derive(Clone, Copy, Debug, PartialEq)]
|
|
pub enum CERSR {
|
|
#[doc = "No current is drawn by the reference circuitry"]
|
|
CERS_0,
|
|
#[doc = "VCC applied to the resistor ladder"]
|
|
CERS_1,
|
|
#[doc = "Shared reference voltage applied to the resistor ladder"]
|
|
CERS_2,
|
|
#[doc = "Shared reference voltage supplied to V(CREF). Resistor ladder is off"]
|
|
CERS_3,
|
|
}
|
|
impl CERSR {
|
|
#[doc = r" Value of the field as raw bits"]
|
|
#[inline]
|
|
pub fn bits(&self) -> u8 {
|
|
match *self {
|
|
CERSR::CERS_0 => 0,
|
|
CERSR::CERS_1 => 1,
|
|
CERSR::CERS_2 => 2,
|
|
CERSR::CERS_3 => 3,
|
|
}
|
|
}
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _from(value: u8) -> CERSR {
|
|
match value {
|
|
0 => CERSR::CERS_0,
|
|
1 => CERSR::CERS_1,
|
|
2 => CERSR::CERS_2,
|
|
3 => CERSR::CERS_3,
|
|
_ => unreachable!(),
|
|
}
|
|
}
|
|
#[doc = "Checks if the value of the field is `CERS_0`"]
|
|
#[inline]
|
|
pub fn is_cers_0(&self) -> bool {
|
|
*self == CERSR::CERS_0
|
|
}
|
|
#[doc = "Checks if the value of the field is `CERS_1`"]
|
|
#[inline]
|
|
pub fn is_cers_1(&self) -> bool {
|
|
*self == CERSR::CERS_1
|
|
}
|
|
#[doc = "Checks if the value of the field is `CERS_2`"]
|
|
#[inline]
|
|
pub fn is_cers_2(&self) -> bool {
|
|
*self == CERSR::CERS_2
|
|
}
|
|
#[doc = "Checks if the value of the field is `CERS_3`"]
|
|
#[inline]
|
|
pub fn is_cers_3(&self) -> bool {
|
|
*self == CERSR::CERS_3
|
|
}
|
|
}
|
|
#[doc = "Possible values of the field `CEREF1`"]
|
|
#[derive(Clone, Copy, Debug, PartialEq)]
|
|
pub enum CEREF1R {
|
|
#[doc = "Reference resistor tap for setting 0."]
|
|
CEREF1_0,
|
|
#[doc = "Reference resistor tap for setting 1."]
|
|
CEREF1_1,
|
|
#[doc = "Reference resistor tap for setting 2."]
|
|
CEREF1_2,
|
|
#[doc = "Reference resistor tap for setting 3."]
|
|
CEREF1_3,
|
|
#[doc = "Reference resistor tap for setting 4."]
|
|
CEREF1_4,
|
|
#[doc = "Reference resistor tap for setting 5."]
|
|
CEREF1_5,
|
|
#[doc = "Reference resistor tap for setting 6."]
|
|
CEREF1_6,
|
|
#[doc = "Reference resistor tap for setting 7."]
|
|
CEREF1_7,
|
|
#[doc = "Reference resistor tap for setting 8."]
|
|
CEREF1_8,
|
|
#[doc = "Reference resistor tap for setting 9."]
|
|
CEREF1_9,
|
|
#[doc = "Reference resistor tap for setting 10."]
|
|
CEREF1_10,
|
|
#[doc = "Reference resistor tap for setting 11."]
|
|
CEREF1_11,
|
|
#[doc = "Reference resistor tap for setting 12."]
|
|
CEREF1_12,
|
|
#[doc = "Reference resistor tap for setting 13."]
|
|
CEREF1_13,
|
|
#[doc = "Reference resistor tap for setting 14."]
|
|
CEREF1_14,
|
|
#[doc = "Reference resistor tap for setting 15."]
|
|
CEREF1_15,
|
|
#[doc = "Reference resistor tap for setting 16."]
|
|
CEREF1_16,
|
|
#[doc = "Reference resistor tap for setting 17."]
|
|
CEREF1_17,
|
|
#[doc = "Reference resistor tap for setting 18."]
|
|
CEREF1_18,
|
|
#[doc = "Reference resistor tap for setting 19."]
|
|
CEREF1_19,
|
|
#[doc = "Reference resistor tap for setting 20."]
|
|
CEREF1_20,
|
|
#[doc = "Reference resistor tap for setting 21."]
|
|
CEREF1_21,
|
|
#[doc = "Reference resistor tap for setting 22."]
|
|
CEREF1_22,
|
|
#[doc = "Reference resistor tap for setting 23."]
|
|
CEREF1_23,
|
|
#[doc = "Reference resistor tap for setting 24."]
|
|
CEREF1_24,
|
|
#[doc = "Reference resistor tap for setting 25."]
|
|
CEREF1_25,
|
|
#[doc = "Reference resistor tap for setting 26."]
|
|
CEREF1_26,
|
|
#[doc = "Reference resistor tap for setting 27."]
|
|
CEREF1_27,
|
|
#[doc = "Reference resistor tap for setting 28."]
|
|
CEREF1_28,
|
|
#[doc = "Reference resistor tap for setting 29."]
|
|
CEREF1_29,
|
|
#[doc = "Reference resistor tap for setting 30."]
|
|
CEREF1_30,
|
|
#[doc = "Reference resistor tap for setting 31."]
|
|
CEREF1_31,
|
|
}
|
|
impl CEREF1R {
|
|
#[doc = r" Value of the field as raw bits"]
|
|
#[inline]
|
|
pub fn bits(&self) -> u8 {
|
|
match *self {
|
|
CEREF1R::CEREF1_0 => 0,
|
|
CEREF1R::CEREF1_1 => 1,
|
|
CEREF1R::CEREF1_2 => 2,
|
|
CEREF1R::CEREF1_3 => 3,
|
|
CEREF1R::CEREF1_4 => 4,
|
|
CEREF1R::CEREF1_5 => 5,
|
|
CEREF1R::CEREF1_6 => 6,
|
|
CEREF1R::CEREF1_7 => 7,
|
|
CEREF1R::CEREF1_8 => 8,
|
|
CEREF1R::CEREF1_9 => 9,
|
|
CEREF1R::CEREF1_10 => 10,
|
|
CEREF1R::CEREF1_11 => 11,
|
|
CEREF1R::CEREF1_12 => 12,
|
|
CEREF1R::CEREF1_13 => 13,
|
|
CEREF1R::CEREF1_14 => 14,
|
|
CEREF1R::CEREF1_15 => 15,
|
|
CEREF1R::CEREF1_16 => 16,
|
|
CEREF1R::CEREF1_17 => 17,
|
|
CEREF1R::CEREF1_18 => 18,
|
|
CEREF1R::CEREF1_19 => 19,
|
|
CEREF1R::CEREF1_20 => 20,
|
|
CEREF1R::CEREF1_21 => 21,
|
|
CEREF1R::CEREF1_22 => 22,
|
|
CEREF1R::CEREF1_23 => 23,
|
|
CEREF1R::CEREF1_24 => 24,
|
|
CEREF1R::CEREF1_25 => 25,
|
|
CEREF1R::CEREF1_26 => 26,
|
|
CEREF1R::CEREF1_27 => 27,
|
|
CEREF1R::CEREF1_28 => 28,
|
|
CEREF1R::CEREF1_29 => 29,
|
|
CEREF1R::CEREF1_30 => 30,
|
|
CEREF1R::CEREF1_31 => 31,
|
|
}
|
|
}
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _from(value: u8) -> CEREF1R {
|
|
match value {
|
|
0 => CEREF1R::CEREF1_0,
|
|
1 => CEREF1R::CEREF1_1,
|
|
2 => CEREF1R::CEREF1_2,
|
|
3 => CEREF1R::CEREF1_3,
|
|
4 => CEREF1R::CEREF1_4,
|
|
5 => CEREF1R::CEREF1_5,
|
|
6 => CEREF1R::CEREF1_6,
|
|
7 => CEREF1R::CEREF1_7,
|
|
8 => CEREF1R::CEREF1_8,
|
|
9 => CEREF1R::CEREF1_9,
|
|
10 => CEREF1R::CEREF1_10,
|
|
11 => CEREF1R::CEREF1_11,
|
|
12 => CEREF1R::CEREF1_12,
|
|
13 => CEREF1R::CEREF1_13,
|
|
14 => CEREF1R::CEREF1_14,
|
|
15 => CEREF1R::CEREF1_15,
|
|
16 => CEREF1R::CEREF1_16,
|
|
17 => CEREF1R::CEREF1_17,
|
|
18 => CEREF1R::CEREF1_18,
|
|
19 => CEREF1R::CEREF1_19,
|
|
20 => CEREF1R::CEREF1_20,
|
|
21 => CEREF1R::CEREF1_21,
|
|
22 => CEREF1R::CEREF1_22,
|
|
23 => CEREF1R::CEREF1_23,
|
|
24 => CEREF1R::CEREF1_24,
|
|
25 => CEREF1R::CEREF1_25,
|
|
26 => CEREF1R::CEREF1_26,
|
|
27 => CEREF1R::CEREF1_27,
|
|
28 => CEREF1R::CEREF1_28,
|
|
29 => CEREF1R::CEREF1_29,
|
|
30 => CEREF1R::CEREF1_30,
|
|
31 => CEREF1R::CEREF1_31,
|
|
_ => unreachable!(),
|
|
}
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_0`"]
|
|
#[inline]
|
|
pub fn is_ceref1_0(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_0
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_1`"]
|
|
#[inline]
|
|
pub fn is_ceref1_1(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_1
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_2`"]
|
|
#[inline]
|
|
pub fn is_ceref1_2(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_2
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_3`"]
|
|
#[inline]
|
|
pub fn is_ceref1_3(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_3
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_4`"]
|
|
#[inline]
|
|
pub fn is_ceref1_4(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_4
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_5`"]
|
|
#[inline]
|
|
pub fn is_ceref1_5(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_5
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_6`"]
|
|
#[inline]
|
|
pub fn is_ceref1_6(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_6
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_7`"]
|
|
#[inline]
|
|
pub fn is_ceref1_7(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_7
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_8`"]
|
|
#[inline]
|
|
pub fn is_ceref1_8(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_8
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_9`"]
|
|
#[inline]
|
|
pub fn is_ceref1_9(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_9
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_10`"]
|
|
#[inline]
|
|
pub fn is_ceref1_10(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_10
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_11`"]
|
|
#[inline]
|
|
pub fn is_ceref1_11(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_11
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_12`"]
|
|
#[inline]
|
|
pub fn is_ceref1_12(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_12
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_13`"]
|
|
#[inline]
|
|
pub fn is_ceref1_13(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_13
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_14`"]
|
|
#[inline]
|
|
pub fn is_ceref1_14(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_14
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_15`"]
|
|
#[inline]
|
|
pub fn is_ceref1_15(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_15
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_16`"]
|
|
#[inline]
|
|
pub fn is_ceref1_16(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_16
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_17`"]
|
|
#[inline]
|
|
pub fn is_ceref1_17(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_17
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_18`"]
|
|
#[inline]
|
|
pub fn is_ceref1_18(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_18
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_19`"]
|
|
#[inline]
|
|
pub fn is_ceref1_19(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_19
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_20`"]
|
|
#[inline]
|
|
pub fn is_ceref1_20(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_20
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_21`"]
|
|
#[inline]
|
|
pub fn is_ceref1_21(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_21
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_22`"]
|
|
#[inline]
|
|
pub fn is_ceref1_22(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_22
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_23`"]
|
|
#[inline]
|
|
pub fn is_ceref1_23(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_23
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_24`"]
|
|
#[inline]
|
|
pub fn is_ceref1_24(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_24
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_25`"]
|
|
#[inline]
|
|
pub fn is_ceref1_25(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_25
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_26`"]
|
|
#[inline]
|
|
pub fn is_ceref1_26(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_26
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_27`"]
|
|
#[inline]
|
|
pub fn is_ceref1_27(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_27
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_28`"]
|
|
#[inline]
|
|
pub fn is_ceref1_28(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_28
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_29`"]
|
|
#[inline]
|
|
pub fn is_ceref1_29(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_29
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_30`"]
|
|
#[inline]
|
|
pub fn is_ceref1_30(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_30
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREF1_31`"]
|
|
#[inline]
|
|
pub fn is_ceref1_31(&self) -> bool {
|
|
*self == CEREF1R::CEREF1_31
|
|
}
|
|
}
|
|
#[doc = "Possible values of the field `CEREFL`"]
|
|
#[derive(Clone, Copy, Debug, PartialEq)]
|
|
pub enum CEREFLR {
|
|
#[doc = "Reference amplifier is disabled. No reference voltage is requested"]
|
|
CEREFL_0,
|
|
#[doc = "1.2 V is selected as shared reference voltage input"]
|
|
CEREFL_1,
|
|
#[doc = "2.0 V is selected as shared reference voltage input"]
|
|
CEREFL_2,
|
|
#[doc = "2.5 V is selected as shared reference voltage input"]
|
|
CEREFL_3,
|
|
}
|
|
impl CEREFLR {
|
|
#[doc = r" Value of the field as raw bits"]
|
|
#[inline]
|
|
pub fn bits(&self) -> u8 {
|
|
match *self {
|
|
CEREFLR::CEREFL_0 => 0,
|
|
CEREFLR::CEREFL_1 => 1,
|
|
CEREFLR::CEREFL_2 => 2,
|
|
CEREFLR::CEREFL_3 => 3,
|
|
}
|
|
}
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _from(value: u8) -> CEREFLR {
|
|
match value {
|
|
0 => CEREFLR::CEREFL_0,
|
|
1 => CEREFLR::CEREFL_1,
|
|
2 => CEREFLR::CEREFL_2,
|
|
3 => CEREFLR::CEREFL_3,
|
|
_ => unreachable!(),
|
|
}
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREFL_0`"]
|
|
#[inline]
|
|
pub fn is_cerefl_0(&self) -> bool {
|
|
*self == CEREFLR::CEREFL_0
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREFL_1`"]
|
|
#[inline]
|
|
pub fn is_cerefl_1(&self) -> bool {
|
|
*self == CEREFLR::CEREFL_1
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREFL_2`"]
|
|
#[inline]
|
|
pub fn is_cerefl_2(&self) -> bool {
|
|
*self == CEREFLR::CEREFL_2
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREFL_3`"]
|
|
#[inline]
|
|
pub fn is_cerefl_3(&self) -> bool {
|
|
*self == CEREFLR::CEREFL_3
|
|
}
|
|
}
|
|
#[doc = "Possible values of the field `CEREFACC`"]
|
|
#[derive(Clone, Copy, Debug, PartialEq)]
|
|
pub enum CEREFACCR {
|
|
#[doc = "Static mode"]
|
|
CEREFACC_0,
|
|
#[doc = "Clocked (low power, low accuracy) mode"]
|
|
CEREFACC_1,
|
|
}
|
|
impl CEREFACCR {
|
|
#[doc = r" Returns `true` if the bit is clear (0)"]
|
|
#[inline]
|
|
pub fn bit_is_clear(&self) -> bool {
|
|
!self.bit()
|
|
}
|
|
#[doc = r" Returns `true` if the bit is set (1)"]
|
|
#[inline]
|
|
pub fn bit_is_set(&self) -> bool {
|
|
self.bit()
|
|
}
|
|
#[doc = r" Value of the field as raw bits"]
|
|
#[inline]
|
|
pub fn bit(&self) -> bool {
|
|
match *self {
|
|
CEREFACCR::CEREFACC_0 => false,
|
|
CEREFACCR::CEREFACC_1 => true,
|
|
}
|
|
}
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _from(value: bool) -> CEREFACCR {
|
|
match value {
|
|
false => CEREFACCR::CEREFACC_0,
|
|
true => CEREFACCR::CEREFACC_1,
|
|
}
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREFACC_0`"]
|
|
#[inline]
|
|
pub fn is_cerefacc_0(&self) -> bool {
|
|
*self == CEREFACCR::CEREFACC_0
|
|
}
|
|
#[doc = "Checks if the value of the field is `CEREFACC_1`"]
|
|
#[inline]
|
|
pub fn is_cerefacc_1(&self) -> bool {
|
|
*self == CEREFACCR::CEREFACC_1
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `CEREF0`"]
|
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pub enum CEREF0W {
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#[doc = "Reference resistor tap for setting 0."]
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CEREF0_0,
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#[doc = "Reference resistor tap for setting 1."]
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CEREF0_1,
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#[doc = "Reference resistor tap for setting 2."]
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CEREF0_2,
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#[doc = "Reference resistor tap for setting 3."]
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CEREF0_3,
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#[doc = "Reference resistor tap for setting 4."]
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CEREF0_4,
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#[doc = "Reference resistor tap for setting 5."]
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CEREF0_5,
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#[doc = "Reference resistor tap for setting 6."]
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CEREF0_6,
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#[doc = "Reference resistor tap for setting 7."]
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CEREF0_7,
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#[doc = "Reference resistor tap for setting 8."]
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CEREF0_8,
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#[doc = "Reference resistor tap for setting 9."]
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CEREF0_9,
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#[doc = "Reference resistor tap for setting 10."]
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CEREF0_10,
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#[doc = "Reference resistor tap for setting 11."]
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CEREF0_11,
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#[doc = "Reference resistor tap for setting 12."]
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CEREF0_12,
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#[doc = "Reference resistor tap for setting 13."]
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CEREF0_13,
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#[doc = "Reference resistor tap for setting 14."]
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CEREF0_14,
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#[doc = "Reference resistor tap for setting 15."]
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CEREF0_15,
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#[doc = "Reference resistor tap for setting 16."]
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CEREF0_16,
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#[doc = "Reference resistor tap for setting 17."]
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CEREF0_17,
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#[doc = "Reference resistor tap for setting 18."]
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CEREF0_18,
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#[doc = "Reference resistor tap for setting 19."]
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CEREF0_19,
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#[doc = "Reference resistor tap for setting 20."]
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CEREF0_20,
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#[doc = "Reference resistor tap for setting 21."]
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CEREF0_21,
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#[doc = "Reference resistor tap for setting 22."]
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CEREF0_22,
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#[doc = "Reference resistor tap for setting 23."]
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CEREF0_23,
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#[doc = "Reference resistor tap for setting 24."]
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CEREF0_24,
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#[doc = "Reference resistor tap for setting 25."]
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CEREF0_25,
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#[doc = "Reference resistor tap for setting 26."]
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CEREF0_26,
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#[doc = "Reference resistor tap for setting 27."]
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CEREF0_27,
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#[doc = "Reference resistor tap for setting 28."]
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CEREF0_28,
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#[doc = "Reference resistor tap for setting 29."]
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CEREF0_29,
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#[doc = "Reference resistor tap for setting 30."]
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CEREF0_30,
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#[doc = "Reference resistor tap for setting 31."]
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CEREF0_31,
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}
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impl CEREF0W {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> u8 {
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match *self {
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CEREF0W::CEREF0_0 => 0,
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CEREF0W::CEREF0_1 => 1,
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CEREF0W::CEREF0_2 => 2,
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CEREF0W::CEREF0_3 => 3,
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CEREF0W::CEREF0_4 => 4,
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CEREF0W::CEREF0_5 => 5,
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CEREF0W::CEREF0_6 => 6,
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CEREF0W::CEREF0_7 => 7,
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CEREF0W::CEREF0_8 => 8,
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CEREF0W::CEREF0_9 => 9,
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CEREF0W::CEREF0_10 => 10,
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CEREF0W::CEREF0_11 => 11,
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CEREF0W::CEREF0_12 => 12,
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CEREF0W::CEREF0_13 => 13,
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CEREF0W::CEREF0_14 => 14,
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CEREF0W::CEREF0_15 => 15,
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CEREF0W::CEREF0_16 => 16,
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CEREF0W::CEREF0_17 => 17,
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CEREF0W::CEREF0_18 => 18,
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CEREF0W::CEREF0_19 => 19,
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CEREF0W::CEREF0_20 => 20,
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CEREF0W::CEREF0_21 => 21,
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CEREF0W::CEREF0_22 => 22,
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CEREF0W::CEREF0_23 => 23,
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CEREF0W::CEREF0_24 => 24,
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CEREF0W::CEREF0_25 => 25,
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CEREF0W::CEREF0_26 => 26,
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CEREF0W::CEREF0_27 => 27,
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CEREF0W::CEREF0_28 => 28,
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CEREF0W::CEREF0_29 => 29,
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CEREF0W::CEREF0_30 => 30,
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CEREF0W::CEREF0_31 => 31,
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}
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}
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}
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#[doc = r" Proxy"]
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pub struct _CEREF0W<'a> {
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w: &'a mut W,
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}
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impl<'a> _CEREF0W<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: CEREF0W) -> &'a mut W {
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{
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self.bits(variant._bits())
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}
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}
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#[doc = "Reference resistor tap for setting 0."]
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#[inline]
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pub fn ceref0_0(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_0)
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}
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#[doc = "Reference resistor tap for setting 1."]
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#[inline]
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pub fn ceref0_1(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_1)
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}
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#[doc = "Reference resistor tap for setting 2."]
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#[inline]
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pub fn ceref0_2(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_2)
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}
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#[doc = "Reference resistor tap for setting 3."]
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#[inline]
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pub fn ceref0_3(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_3)
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}
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#[doc = "Reference resistor tap for setting 4."]
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#[inline]
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pub fn ceref0_4(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_4)
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}
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#[doc = "Reference resistor tap for setting 5."]
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#[inline]
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pub fn ceref0_5(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_5)
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}
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#[doc = "Reference resistor tap for setting 6."]
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#[inline]
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pub fn ceref0_6(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_6)
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}
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#[doc = "Reference resistor tap for setting 7."]
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#[inline]
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pub fn ceref0_7(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_7)
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}
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#[doc = "Reference resistor tap for setting 8."]
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#[inline]
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pub fn ceref0_8(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_8)
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}
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#[doc = "Reference resistor tap for setting 9."]
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#[inline]
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pub fn ceref0_9(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_9)
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}
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#[doc = "Reference resistor tap for setting 10."]
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#[inline]
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pub fn ceref0_10(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_10)
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}
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#[doc = "Reference resistor tap for setting 11."]
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#[inline]
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pub fn ceref0_11(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_11)
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}
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#[doc = "Reference resistor tap for setting 12."]
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#[inline]
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pub fn ceref0_12(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_12)
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}
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#[doc = "Reference resistor tap for setting 13."]
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#[inline]
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pub fn ceref0_13(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_13)
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}
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#[doc = "Reference resistor tap for setting 14."]
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#[inline]
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pub fn ceref0_14(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_14)
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}
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#[doc = "Reference resistor tap for setting 15."]
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#[inline]
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pub fn ceref0_15(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_15)
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}
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#[doc = "Reference resistor tap for setting 16."]
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#[inline]
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pub fn ceref0_16(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_16)
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}
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#[doc = "Reference resistor tap for setting 17."]
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#[inline]
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pub fn ceref0_17(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_17)
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}
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#[doc = "Reference resistor tap for setting 18."]
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#[inline]
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pub fn ceref0_18(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_18)
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}
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#[doc = "Reference resistor tap for setting 19."]
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#[inline]
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pub fn ceref0_19(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_19)
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}
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#[doc = "Reference resistor tap for setting 20."]
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#[inline]
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pub fn ceref0_20(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_20)
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}
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#[doc = "Reference resistor tap for setting 21."]
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#[inline]
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pub fn ceref0_21(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_21)
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}
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#[doc = "Reference resistor tap for setting 22."]
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#[inline]
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pub fn ceref0_22(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_22)
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}
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#[doc = "Reference resistor tap for setting 23."]
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#[inline]
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pub fn ceref0_23(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_23)
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}
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#[doc = "Reference resistor tap for setting 24."]
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#[inline]
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pub fn ceref0_24(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_24)
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}
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#[doc = "Reference resistor tap for setting 25."]
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#[inline]
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pub fn ceref0_25(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_25)
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}
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#[doc = "Reference resistor tap for setting 26."]
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#[inline]
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pub fn ceref0_26(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_26)
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}
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#[doc = "Reference resistor tap for setting 27."]
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#[inline]
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pub fn ceref0_27(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_27)
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}
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#[doc = "Reference resistor tap for setting 28."]
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#[inline]
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pub fn ceref0_28(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_28)
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}
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#[doc = "Reference resistor tap for setting 29."]
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#[inline]
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pub fn ceref0_29(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_29)
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}
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#[doc = "Reference resistor tap for setting 30."]
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#[inline]
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pub fn ceref0_30(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_30)
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}
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#[doc = "Reference resistor tap for setting 31."]
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#[inline]
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pub fn ceref0_31(self) -> &'a mut W {
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self.variant(CEREF0W::CEREF0_31)
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}
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub fn bits(self, value: u8) -> &'a mut W {
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const MASK: u8 = 31;
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const OFFSET: u8 = 0;
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self.w.bits &= !((MASK as u16) << OFFSET);
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self.w.bits |= ((value & MASK) as u16) << OFFSET;
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self.w
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}
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}
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#[doc = "Values that can be written to the field `CERSEL`"]
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pub enum CERSELW {
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#[doc = "When CEEX = 0, VREF is applied to the V+ terminal; When CEEX = 1, VREF is applied to the V- terminal"]
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CERSEL_0,
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#[doc = "When CEEX = 0, VREF is applied to the V- terminal; When CEEX = 1, VREF is applied to the V+ terminal"]
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CERSEL_1,
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}
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impl CERSELW {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> bool {
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match *self {
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CERSELW::CERSEL_0 => false,
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CERSELW::CERSEL_1 => true,
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}
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}
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}
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#[doc = r" Proxy"]
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pub struct _CERSELW<'a> {
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w: &'a mut W,
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}
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impl<'a> _CERSELW<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: CERSELW) -> &'a mut W {
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{
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self.bit(variant._bits())
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}
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}
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#[doc = "When CEEX = 0, VREF is applied to the V+ terminal; When CEEX = 1, VREF is applied to the V- terminal"]
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#[inline]
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pub fn cersel_0(self) -> &'a mut W {
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self.variant(CERSELW::CERSEL_0)
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}
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#[doc = "When CEEX = 0, VREF is applied to the V- terminal; When CEEX = 1, VREF is applied to the V+ terminal"]
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#[inline]
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pub fn cersel_1(self) -> &'a mut W {
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self.variant(CERSELW::CERSEL_1)
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}
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#[doc = r" Sets the field bit"]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r" Clears the field bit"]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r" Writes raw bits to the field"]
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#[inline]
|
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pub fn bit(self, value: bool) -> &'a mut W {
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const MASK: bool = true;
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const OFFSET: u8 = 5;
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self.w.bits &= !((MASK as u16) << OFFSET);
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self.w.bits |= ((value & MASK) as u16) << OFFSET;
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self.w
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}
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}
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#[doc = "Values that can be written to the field `CERS`"]
|
|
pub enum CERSW {
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#[doc = "No current is drawn by the reference circuitry"]
|
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CERS_0,
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#[doc = "VCC applied to the resistor ladder"]
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|
CERS_1,
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#[doc = "Shared reference voltage applied to the resistor ladder"]
|
|
CERS_2,
|
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#[doc = "Shared reference voltage supplied to V(CREF). Resistor ladder is off"]
|
|
CERS_3,
|
|
}
|
|
impl CERSW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> u8 {
|
|
match *self {
|
|
CERSW::CERS_0 => 0,
|
|
CERSW::CERS_1 => 1,
|
|
CERSW::CERS_2 => 2,
|
|
CERSW::CERS_3 => 3,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _CERSW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _CERSW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: CERSW) -> &'a mut W {
|
|
{
|
|
self.bits(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "No current is drawn by the reference circuitry"]
|
|
#[inline]
|
|
pub fn cers_0(self) -> &'a mut W {
|
|
self.variant(CERSW::CERS_0)
|
|
}
|
|
#[doc = "VCC applied to the resistor ladder"]
|
|
#[inline]
|
|
pub fn cers_1(self) -> &'a mut W {
|
|
self.variant(CERSW::CERS_1)
|
|
}
|
|
#[doc = "Shared reference voltage applied to the resistor ladder"]
|
|
#[inline]
|
|
pub fn cers_2(self) -> &'a mut W {
|
|
self.variant(CERSW::CERS_2)
|
|
}
|
|
#[doc = "Shared reference voltage supplied to V(CREF). Resistor ladder is off"]
|
|
#[inline]
|
|
pub fn cers_3(self) -> &'a mut W {
|
|
self.variant(CERSW::CERS_3)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bits(self, value: u8) -> &'a mut W {
|
|
const MASK: u8 = 3;
|
|
const OFFSET: u8 = 6;
|
|
self.w.bits &= !((MASK as u16) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u16) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `CEREF1`"]
|
|
pub enum CEREF1W {
|
|
#[doc = "Reference resistor tap for setting 0."]
|
|
CEREF1_0,
|
|
#[doc = "Reference resistor tap for setting 1."]
|
|
CEREF1_1,
|
|
#[doc = "Reference resistor tap for setting 2."]
|
|
CEREF1_2,
|
|
#[doc = "Reference resistor tap for setting 3."]
|
|
CEREF1_3,
|
|
#[doc = "Reference resistor tap for setting 4."]
|
|
CEREF1_4,
|
|
#[doc = "Reference resistor tap for setting 5."]
|
|
CEREF1_5,
|
|
#[doc = "Reference resistor tap for setting 6."]
|
|
CEREF1_6,
|
|
#[doc = "Reference resistor tap for setting 7."]
|
|
CEREF1_7,
|
|
#[doc = "Reference resistor tap for setting 8."]
|
|
CEREF1_8,
|
|
#[doc = "Reference resistor tap for setting 9."]
|
|
CEREF1_9,
|
|
#[doc = "Reference resistor tap for setting 10."]
|
|
CEREF1_10,
|
|
#[doc = "Reference resistor tap for setting 11."]
|
|
CEREF1_11,
|
|
#[doc = "Reference resistor tap for setting 12."]
|
|
CEREF1_12,
|
|
#[doc = "Reference resistor tap for setting 13."]
|
|
CEREF1_13,
|
|
#[doc = "Reference resistor tap for setting 14."]
|
|
CEREF1_14,
|
|
#[doc = "Reference resistor tap for setting 15."]
|
|
CEREF1_15,
|
|
#[doc = "Reference resistor tap for setting 16."]
|
|
CEREF1_16,
|
|
#[doc = "Reference resistor tap for setting 17."]
|
|
CEREF1_17,
|
|
#[doc = "Reference resistor tap for setting 18."]
|
|
CEREF1_18,
|
|
#[doc = "Reference resistor tap for setting 19."]
|
|
CEREF1_19,
|
|
#[doc = "Reference resistor tap for setting 20."]
|
|
CEREF1_20,
|
|
#[doc = "Reference resistor tap for setting 21."]
|
|
CEREF1_21,
|
|
#[doc = "Reference resistor tap for setting 22."]
|
|
CEREF1_22,
|
|
#[doc = "Reference resistor tap for setting 23."]
|
|
CEREF1_23,
|
|
#[doc = "Reference resistor tap for setting 24."]
|
|
CEREF1_24,
|
|
#[doc = "Reference resistor tap for setting 25."]
|
|
CEREF1_25,
|
|
#[doc = "Reference resistor tap for setting 26."]
|
|
CEREF1_26,
|
|
#[doc = "Reference resistor tap for setting 27."]
|
|
CEREF1_27,
|
|
#[doc = "Reference resistor tap for setting 28."]
|
|
CEREF1_28,
|
|
#[doc = "Reference resistor tap for setting 29."]
|
|
CEREF1_29,
|
|
#[doc = "Reference resistor tap for setting 30."]
|
|
CEREF1_30,
|
|
#[doc = "Reference resistor tap for setting 31."]
|
|
CEREF1_31,
|
|
}
|
|
impl CEREF1W {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> u8 {
|
|
match *self {
|
|
CEREF1W::CEREF1_0 => 0,
|
|
CEREF1W::CEREF1_1 => 1,
|
|
CEREF1W::CEREF1_2 => 2,
|
|
CEREF1W::CEREF1_3 => 3,
|
|
CEREF1W::CEREF1_4 => 4,
|
|
CEREF1W::CEREF1_5 => 5,
|
|
CEREF1W::CEREF1_6 => 6,
|
|
CEREF1W::CEREF1_7 => 7,
|
|
CEREF1W::CEREF1_8 => 8,
|
|
CEREF1W::CEREF1_9 => 9,
|
|
CEREF1W::CEREF1_10 => 10,
|
|
CEREF1W::CEREF1_11 => 11,
|
|
CEREF1W::CEREF1_12 => 12,
|
|
CEREF1W::CEREF1_13 => 13,
|
|
CEREF1W::CEREF1_14 => 14,
|
|
CEREF1W::CEREF1_15 => 15,
|
|
CEREF1W::CEREF1_16 => 16,
|
|
CEREF1W::CEREF1_17 => 17,
|
|
CEREF1W::CEREF1_18 => 18,
|
|
CEREF1W::CEREF1_19 => 19,
|
|
CEREF1W::CEREF1_20 => 20,
|
|
CEREF1W::CEREF1_21 => 21,
|
|
CEREF1W::CEREF1_22 => 22,
|
|
CEREF1W::CEREF1_23 => 23,
|
|
CEREF1W::CEREF1_24 => 24,
|
|
CEREF1W::CEREF1_25 => 25,
|
|
CEREF1W::CEREF1_26 => 26,
|
|
CEREF1W::CEREF1_27 => 27,
|
|
CEREF1W::CEREF1_28 => 28,
|
|
CEREF1W::CEREF1_29 => 29,
|
|
CEREF1W::CEREF1_30 => 30,
|
|
CEREF1W::CEREF1_31 => 31,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _CEREF1W<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _CEREF1W<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: CEREF1W) -> &'a mut W {
|
|
{
|
|
self.bits(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "Reference resistor tap for setting 0."]
|
|
#[inline]
|
|
pub fn ceref1_0(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_0)
|
|
}
|
|
#[doc = "Reference resistor tap for setting 1."]
|
|
#[inline]
|
|
pub fn ceref1_1(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_1)
|
|
}
|
|
#[doc = "Reference resistor tap for setting 2."]
|
|
#[inline]
|
|
pub fn ceref1_2(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_2)
|
|
}
|
|
#[doc = "Reference resistor tap for setting 3."]
|
|
#[inline]
|
|
pub fn ceref1_3(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_3)
|
|
}
|
|
#[doc = "Reference resistor tap for setting 4."]
|
|
#[inline]
|
|
pub fn ceref1_4(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_4)
|
|
}
|
|
#[doc = "Reference resistor tap for setting 5."]
|
|
#[inline]
|
|
pub fn ceref1_5(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_5)
|
|
}
|
|
#[doc = "Reference resistor tap for setting 6."]
|
|
#[inline]
|
|
pub fn ceref1_6(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_6)
|
|
}
|
|
#[doc = "Reference resistor tap for setting 7."]
|
|
#[inline]
|
|
pub fn ceref1_7(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_7)
|
|
}
|
|
#[doc = "Reference resistor tap for setting 8."]
|
|
#[inline]
|
|
pub fn ceref1_8(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_8)
|
|
}
|
|
#[doc = "Reference resistor tap for setting 9."]
|
|
#[inline]
|
|
pub fn ceref1_9(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_9)
|
|
}
|
|
#[doc = "Reference resistor tap for setting 10."]
|
|
#[inline]
|
|
pub fn ceref1_10(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_10)
|
|
}
|
|
#[doc = "Reference resistor tap for setting 11."]
|
|
#[inline]
|
|
pub fn ceref1_11(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_11)
|
|
}
|
|
#[doc = "Reference resistor tap for setting 12."]
|
|
#[inline]
|
|
pub fn ceref1_12(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_12)
|
|
}
|
|
#[doc = "Reference resistor tap for setting 13."]
|
|
#[inline]
|
|
pub fn ceref1_13(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_13)
|
|
}
|
|
#[doc = "Reference resistor tap for setting 14."]
|
|
#[inline]
|
|
pub fn ceref1_14(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_14)
|
|
}
|
|
#[doc = "Reference resistor tap for setting 15."]
|
|
#[inline]
|
|
pub fn ceref1_15(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_15)
|
|
}
|
|
#[doc = "Reference resistor tap for setting 16."]
|
|
#[inline]
|
|
pub fn ceref1_16(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_16)
|
|
}
|
|
#[doc = "Reference resistor tap for setting 17."]
|
|
#[inline]
|
|
pub fn ceref1_17(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_17)
|
|
}
|
|
#[doc = "Reference resistor tap for setting 18."]
|
|
#[inline]
|
|
pub fn ceref1_18(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_18)
|
|
}
|
|
#[doc = "Reference resistor tap for setting 19."]
|
|
#[inline]
|
|
pub fn ceref1_19(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_19)
|
|
}
|
|
#[doc = "Reference resistor tap for setting 20."]
|
|
#[inline]
|
|
pub fn ceref1_20(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_20)
|
|
}
|
|
#[doc = "Reference resistor tap for setting 21."]
|
|
#[inline]
|
|
pub fn ceref1_21(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_21)
|
|
}
|
|
#[doc = "Reference resistor tap for setting 22."]
|
|
#[inline]
|
|
pub fn ceref1_22(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_22)
|
|
}
|
|
#[doc = "Reference resistor tap for setting 23."]
|
|
#[inline]
|
|
pub fn ceref1_23(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_23)
|
|
}
|
|
#[doc = "Reference resistor tap for setting 24."]
|
|
#[inline]
|
|
pub fn ceref1_24(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_24)
|
|
}
|
|
#[doc = "Reference resistor tap for setting 25."]
|
|
#[inline]
|
|
pub fn ceref1_25(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_25)
|
|
}
|
|
#[doc = "Reference resistor tap for setting 26."]
|
|
#[inline]
|
|
pub fn ceref1_26(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_26)
|
|
}
|
|
#[doc = "Reference resistor tap for setting 27."]
|
|
#[inline]
|
|
pub fn ceref1_27(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_27)
|
|
}
|
|
#[doc = "Reference resistor tap for setting 28."]
|
|
#[inline]
|
|
pub fn ceref1_28(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_28)
|
|
}
|
|
#[doc = "Reference resistor tap for setting 29."]
|
|
#[inline]
|
|
pub fn ceref1_29(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_29)
|
|
}
|
|
#[doc = "Reference resistor tap for setting 30."]
|
|
#[inline]
|
|
pub fn ceref1_30(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_30)
|
|
}
|
|
#[doc = "Reference resistor tap for setting 31."]
|
|
#[inline]
|
|
pub fn ceref1_31(self) -> &'a mut W {
|
|
self.variant(CEREF1W::CEREF1_31)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bits(self, value: u8) -> &'a mut W {
|
|
const MASK: u8 = 31;
|
|
const OFFSET: u8 = 8;
|
|
self.w.bits &= !((MASK as u16) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u16) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `CEREFL`"]
|
|
pub enum CEREFLW {
|
|
#[doc = "Reference amplifier is disabled. No reference voltage is requested"]
|
|
CEREFL_0,
|
|
#[doc = "1.2 V is selected as shared reference voltage input"]
|
|
CEREFL_1,
|
|
#[doc = "2.0 V is selected as shared reference voltage input"]
|
|
CEREFL_2,
|
|
#[doc = "2.5 V is selected as shared reference voltage input"]
|
|
CEREFL_3,
|
|
}
|
|
impl CEREFLW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> u8 {
|
|
match *self {
|
|
CEREFLW::CEREFL_0 => 0,
|
|
CEREFLW::CEREFL_1 => 1,
|
|
CEREFLW::CEREFL_2 => 2,
|
|
CEREFLW::CEREFL_3 => 3,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _CEREFLW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _CEREFLW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: CEREFLW) -> &'a mut W {
|
|
{
|
|
self.bits(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "Reference amplifier is disabled. No reference voltage is requested"]
|
|
#[inline]
|
|
pub fn cerefl_0(self) -> &'a mut W {
|
|
self.variant(CEREFLW::CEREFL_0)
|
|
}
|
|
#[doc = "1.2 V is selected as shared reference voltage input"]
|
|
#[inline]
|
|
pub fn cerefl_1(self) -> &'a mut W {
|
|
self.variant(CEREFLW::CEREFL_1)
|
|
}
|
|
#[doc = "2.0 V is selected as shared reference voltage input"]
|
|
#[inline]
|
|
pub fn cerefl_2(self) -> &'a mut W {
|
|
self.variant(CEREFLW::CEREFL_2)
|
|
}
|
|
#[doc = "2.5 V is selected as shared reference voltage input"]
|
|
#[inline]
|
|
pub fn cerefl_3(self) -> &'a mut W {
|
|
self.variant(CEREFLW::CEREFL_3)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bits(self, value: u8) -> &'a mut W {
|
|
const MASK: u8 = 3;
|
|
const OFFSET: u8 = 13;
|
|
self.w.bits &= !((MASK as u16) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u16) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `CEREFACC`"]
|
|
pub enum CEREFACCW {
|
|
#[doc = "Static mode"]
|
|
CEREFACC_0,
|
|
#[doc = "Clocked (low power, low accuracy) mode"]
|
|
CEREFACC_1,
|
|
}
|
|
impl CEREFACCW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> bool {
|
|
match *self {
|
|
CEREFACCW::CEREFACC_0 => false,
|
|
CEREFACCW::CEREFACC_1 => true,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _CEREFACCW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _CEREFACCW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: CEREFACCW) -> &'a mut W {
|
|
{
|
|
self.bit(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "Static mode"]
|
|
#[inline]
|
|
pub fn cerefacc_0(self) -> &'a mut W {
|
|
self.variant(CEREFACCW::CEREFACC_0)
|
|
}
|
|
#[doc = "Clocked (low power, low accuracy) mode"]
|
|
#[inline]
|
|
pub fn cerefacc_1(self) -> &'a mut W {
|
|
self.variant(CEREFACCW::CEREFACC_1)
|
|
}
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
|
|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 15;
|
|
self.w.bits &= !((MASK as u16) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u16) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
impl R {
|
|
#[doc = r" Value of the register as raw bits"]
|
|
#[inline]
|
|
pub fn bits(&self) -> u16 {
|
|
self.bits
|
|
}
|
|
#[doc = "Bits 0:4 - Reference resistor tap 0"]
|
|
#[inline]
|
|
pub fn ceref0(&self) -> CEREF0R {
|
|
CEREF0R::_from({
|
|
const MASK: u8 = 31;
|
|
const OFFSET: u8 = 0;
|
|
((self.bits >> OFFSET) & MASK as u16) as u8
|
|
})
|
|
}
|
|
#[doc = "Bit 5 - Reference select"]
|
|
#[inline]
|
|
pub fn cersel(&self) -> CERSELR {
|
|
CERSELR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 5;
|
|
((self.bits >> OFFSET) & MASK as u16) != 0
|
|
})
|
|
}
|
|
#[doc = "Bits 6:7 - Reference source"]
|
|
#[inline]
|
|
pub fn cers(&self) -> CERSR {
|
|
CERSR::_from({
|
|
const MASK: u8 = 3;
|
|
const OFFSET: u8 = 6;
|
|
((self.bits >> OFFSET) & MASK as u16) as u8
|
|
})
|
|
}
|
|
#[doc = "Bits 8:12 - Reference resistor tap 1"]
|
|
#[inline]
|
|
pub fn ceref1(&self) -> CEREF1R {
|
|
CEREF1R::_from({
|
|
const MASK: u8 = 31;
|
|
const OFFSET: u8 = 8;
|
|
((self.bits >> OFFSET) & MASK as u16) as u8
|
|
})
|
|
}
|
|
#[doc = "Bits 13:14 - Reference voltage level"]
|
|
#[inline]
|
|
pub fn cerefl(&self) -> CEREFLR {
|
|
CEREFLR::_from({
|
|
const MASK: u8 = 3;
|
|
const OFFSET: u8 = 13;
|
|
((self.bits >> OFFSET) & MASK as u16) as u8
|
|
})
|
|
}
|
|
#[doc = "Bit 15 - Reference accuracy"]
|
|
#[inline]
|
|
pub fn cerefacc(&self) -> CEREFACCR {
|
|
CEREFACCR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 15;
|
|
((self.bits >> OFFSET) & MASK as u16) != 0
|
|
})
|
|
}
|
|
}
|
|
impl W {
|
|
#[doc = r" Reset value of the register"]
|
|
#[inline]
|
|
pub fn reset_value() -> W {
|
|
W { bits: 0 }
|
|
}
|
|
#[doc = r" Writes raw bits to the register"]
|
|
#[inline]
|
|
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
|
|
self.bits = bits;
|
|
self
|
|
}
|
|
#[doc = "Bits 0:4 - Reference resistor tap 0"]
|
|
#[inline]
|
|
pub fn ceref0(&mut self) -> _CEREF0W {
|
|
_CEREF0W { w: self }
|
|
}
|
|
#[doc = "Bit 5 - Reference select"]
|
|
#[inline]
|
|
pub fn cersel(&mut self) -> _CERSELW {
|
|
_CERSELW { w: self }
|
|
}
|
|
#[doc = "Bits 6:7 - Reference source"]
|
|
#[inline]
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pub fn cers(&mut self) -> _CERSW {
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_CERSW { w: self }
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}
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#[doc = "Bits 8:12 - Reference resistor tap 1"]
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#[inline]
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pub fn ceref1(&mut self) -> _CEREF1W {
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_CEREF1W { w: self }
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}
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#[doc = "Bits 13:14 - Reference voltage level"]
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#[inline]
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pub fn cerefl(&mut self) -> _CEREFLW {
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_CEREFLW { w: self }
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}
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#[doc = "Bit 15 - Reference accuracy"]
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#[inline]
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pub fn cerefacc(&mut self) -> _CEREFACCW {
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_CEREFACCW { w: self }
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}
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}
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