Update hal to 0.9.0
parent
a77f5bba05
commit
3df764e74c
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@ -10,7 +10,7 @@ edition = "2021"
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cortex-m = "0.7.4"
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cortex-m-rt = "0.7.1"
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embedded-hal = "0.2.3"
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stm32f1xx-hal = { version = "0.8.0", features = ["rt", "stm32f103", "medium"] }
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stm32f1xx-hal = { version = "0.9.0", features = ["rt", "stm32f103", "medium"] }
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rtt-target = { version = "0.3.1", features = ["cortex-m"] }
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panic-rtt-target = { version = "0.1.0", features = ["cortex-m"] }
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switch-hal = "0.4.0"
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17
src/main.rs
17
src/main.rs
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@ -10,7 +10,6 @@ use cortex_m::interrupt::Mutex;
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use stm32f1xx_hal::{
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afio,
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delay::Delay,
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device::{EXTI, NVIC},
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gpio::{
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gpioa::{PA8, PA9},
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@ -64,17 +63,17 @@ fn main() -> ! {
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// we configure the clock and "freeze" the configuration so we can pass it
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let clocks = rcc
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.cfgr
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.use_hse(8.mhz()) // Use High Speed External 8Mhz crystal oscillator
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.sysclk(72.mhz()) // Use the PLL to multiply SYSCLK to 72MHz
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.hclk(72.mhz()) // Leave AHB prescaler at /1
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.pclk1(36.mhz()) // Use the APB1 prescaler to divide the clock to 36MHz (max supported)
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.pclk2(72.mhz()) // Leave the APB2 prescaler at /1
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.adcclk(12.mhz()) // ADC prescaler of /6 (max speed of 14MHz, but /4 gives 18MHz)
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.use_hse(8.MHz()) // Use High Speed External 8Mhz crystal oscillator
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.sysclk(72.MHz()) // Use the PLL to multiply SYSCLK to 72MHz
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.hclk(72.MHz()) // Leave AHB prescaler at /1
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.pclk1(36.MHz()) // Use the APB1 prescaler to divide the clock to 36MHz (max supported)
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.pclk2(72.MHz()) // Leave the APB2 prescaler at /1
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.adcclk(12.MHz()) // ADC prescaler of /6 (max speed of 14MHz, but /4 gives 18MHz)
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.freeze(&mut flash.acr);
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// In order to have precisely-timed delays, we can use the core SysTick clock as a
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// delay provider
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let mut delay = Delay::new(core_periph.SYST, clocks);
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let mut delay = core_periph.SYST.delay(&clocks);
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// Acquire the necessary gpio peripherals
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let mut gpioa = dev_periph.GPIOA.split();
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@ -111,7 +110,7 @@ fn main() -> ! {
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dev_periph.I2C2,
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(scl, sda),
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Mode::Fast {
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frequency: 400_000.hz(),
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frequency: 400_000.Hz(),
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duty_cycle: DutyCycle::Ratio2to1,
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},
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clocks,
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