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Update hal to 0.9.0

master
Levi Pearson 2022-03-09 03:40:15 -07:00
parent a77f5bba05
commit 3df764e74c
2 changed files with 9 additions and 10 deletions
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2
Cargo.toml
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@ -10,7 +10,7 @@ edition = "2021"
cortex-m = "0.7.4" cortex-m = "0.7.4"
cortex-m-rt = "0.7.1" cortex-m-rt = "0.7.1"
embedded-hal = "0.2.3" embedded-hal = "0.2.3"
stm32f1xx-hal = { version = "0.8.0", features = ["rt", "stm32f103", "medium"] } stm32f1xx-hal = { version = "0.9.0", features = ["rt", "stm32f103", "medium"] }
rtt-target = { version = "0.3.1", features = ["cortex-m"] } rtt-target = { version = "0.3.1", features = ["cortex-m"] }
panic-rtt-target = { version = "0.1.0", features = ["cortex-m"] } panic-rtt-target = { version = "0.1.0", features = ["cortex-m"] }
switch-hal = "0.4.0" switch-hal = "0.4.0"

17
src/main.rs
View File

@ -10,7 +10,6 @@ use cortex_m::interrupt::Mutex;
use stm32f1xx_hal::{ use stm32f1xx_hal::{
afio, afio,
delay::Delay,
device::{EXTI, NVIC}, device::{EXTI, NVIC},
gpio::{ gpio::{
gpioa::{PA8, PA9}, gpioa::{PA8, PA9},
@ -64,17 +63,17 @@ fn main() -> ! {
// we configure the clock and "freeze" the configuration so we can pass it // we configure the clock and "freeze" the configuration so we can pass it
let clocks = rcc let clocks = rcc
.cfgr .cfgr
.use_hse(8.mhz()) // Use High Speed External 8Mhz crystal oscillator .use_hse(8.MHz()) // Use High Speed External 8Mhz crystal oscillator
.sysclk(72.mhz()) // Use the PLL to multiply SYSCLK to 72MHz .sysclk(72.MHz()) // Use the PLL to multiply SYSCLK to 72MHz
.hclk(72.mhz()) // Leave AHB prescaler at /1 .hclk(72.MHz()) // Leave AHB prescaler at /1
.pclk1(36.mhz()) // Use the APB1 prescaler to divide the clock to 36MHz (max supported) .pclk1(36.MHz()) // Use the APB1 prescaler to divide the clock to 36MHz (max supported)
.pclk2(72.mhz()) // Leave the APB2 prescaler at /1 .pclk2(72.MHz()) // Leave the APB2 prescaler at /1
.adcclk(12.mhz()) // ADC prescaler of /6 (max speed of 14MHz, but /4 gives 18MHz) .adcclk(12.MHz()) // ADC prescaler of /6 (max speed of 14MHz, but /4 gives 18MHz)
.freeze(&mut flash.acr); .freeze(&mut flash.acr);
// In order to have precisely-timed delays, we can use the core SysTick clock as a // In order to have precisely-timed delays, we can use the core SysTick clock as a
// delay provider // delay provider
let mut delay = Delay::new(core_periph.SYST, clocks); let mut delay = core_periph.SYST.delay(&clocks);
// Acquire the necessary gpio peripherals // Acquire the necessary gpio peripherals
let mut gpioa = dev_periph.GPIOA.split(); let mut gpioa = dev_periph.GPIOA.split();
@ -111,7 +110,7 @@ fn main() -> ! {
dev_periph.I2C2, dev_periph.I2C2,
(scl, sda), (scl, sda),
Mode::Fast { Mode::Fast {
frequency: 400_000.hz(), frequency: 400_000.Hz(),
duty_cycle: DutyCycle::Ratio2to1, duty_cycle: DutyCycle::Ratio2to1,
}, },
clocks, clocks,