Talk as presented plus example source for MSP432 blinky light demo

example-source/msp432p401r/src/dio/p2iv.rs

@@ -0,0 +1,133 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u16,
+}
+impl super::P2IV {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+}
+#[doc = "Possible values of the field `P2IV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum P2IVR {
+    #[doc = "No interrupt pending"]
+    P2IV_0,
+    #[doc = "Interrupt Source: Port 2.0 interrupt; Interrupt Flag: P2IFG0; Interrupt Priority: Highest"]
+    P2IV_2,
+    #[doc = "Interrupt Source: Port 2.1 interrupt; Interrupt Flag: P2IFG1"]
+    P2IV_4,
+    #[doc = "Interrupt Source: Port 2.2 interrupt; Interrupt Flag: P2IFG2"]
+    P2IV_6,
+    #[doc = "Interrupt Source: Port 2.3 interrupt; Interrupt Flag: P2IFG3"]
+    P2IV_8,
+    #[doc = "Interrupt Source: Port 2.4 interrupt; Interrupt Flag: P2IFG4"]
+    P2IV_10,
+    #[doc = "Interrupt Source: Port 2.5 interrupt; Interrupt Flag: P2IFG5"]
+    P2IV_12,
+    #[doc = "Interrupt Source: Port 2.6 interrupt; Interrupt Flag: P2IFG6"]
+    P2IV_14,
+    #[doc = "Interrupt Source: Port 2.7 interrupt; Interrupt Flag: P2IFG7; Interrupt Priority: Lowest"]
+    P2IV_16,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl P2IVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            P2IVR::P2IV_0 => 0,
+            P2IVR::P2IV_2 => 2,
+            P2IVR::P2IV_4 => 4,
+            P2IVR::P2IV_6 => 6,
+            P2IVR::P2IV_8 => 8,
+            P2IVR::P2IV_10 => 10,
+            P2IVR::P2IV_12 => 12,
+            P2IVR::P2IV_14 => 14,
+            P2IVR::P2IV_16 => 16,
+            P2IVR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> P2IVR {
+        match value {
+            0 => P2IVR::P2IV_0,
+            2 => P2IVR::P2IV_2,
+            4 => P2IVR::P2IV_4,
+            6 => P2IVR::P2IV_6,
+            8 => P2IVR::P2IV_8,
+            10 => P2IVR::P2IV_10,
+            12 => P2IVR::P2IV_12,
+            14 => P2IVR::P2IV_14,
+            16 => P2IVR::P2IV_16,
+            i => P2IVR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `P2IV_0`"]
+    #[inline]
+    pub fn is_p2iv_0(&self) -> bool {
+        *self == P2IVR::P2IV_0
+    }
+    #[doc = "Checks if the value of the field is `P2IV_2`"]
+    #[inline]
+    pub fn is_p2iv_2(&self) -> bool {
+        *self == P2IVR::P2IV_2
+    }
+    #[doc = "Checks if the value of the field is `P2IV_4`"]
+    #[inline]
+    pub fn is_p2iv_4(&self) -> bool {
+        *self == P2IVR::P2IV_4
+    }
+    #[doc = "Checks if the value of the field is `P2IV_6`"]
+    #[inline]
+    pub fn is_p2iv_6(&self) -> bool {
+        *self == P2IVR::P2IV_6
+    }
+    #[doc = "Checks if the value of the field is `P2IV_8`"]
+    #[inline]
+    pub fn is_p2iv_8(&self) -> bool {
+        *self == P2IVR::P2IV_8
+    }
+    #[doc = "Checks if the value of the field is `P2IV_10`"]
+    #[inline]
+    pub fn is_p2iv_10(&self) -> bool {
+        *self == P2IVR::P2IV_10
+    }
+    #[doc = "Checks if the value of the field is `P2IV_12`"]
+    #[inline]
+    pub fn is_p2iv_12(&self) -> bool {
+        *self == P2IVR::P2IV_12
+    }
+    #[doc = "Checks if the value of the field is `P2IV_14`"]
+    #[inline]
+    pub fn is_p2iv_14(&self) -> bool {
+        *self == P2IVR::P2IV_14
+    }
+    #[doc = "Checks if the value of the field is `P2IV_16`"]
+    #[inline]
+    pub fn is_p2iv_16(&self) -> bool {
+        *self == P2IVR::P2IV_16
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+    #[doc = "Bits 0:4 - Port 2 interrupt vector value"]
+    #[inline]
+    pub fn p2iv(&self) -> P2IVR {
+        P2IVR::_from({
+            const MASK: u8 = 31;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u16) as u8
+        })
+    }
+}