414 lines
15 KiB
Rust
414 lines
15 KiB
Rust
#[doc = r" Register block"]
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#[repr(C)]
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pub struct RegisterBlock {
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#[doc = "0x00 - Power Status Register"]
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pub flctl_power_stat: FLCTL_POWER_STAT,
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_reserved0: [u8; 12usize],
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#[doc = "0x10 - Bank0 Read Control Register"]
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pub flctl_bank0_rdctl: FLCTL_BANK0_RDCTL,
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#[doc = "0x14 - Bank1 Read Control Register"]
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pub flctl_bank1_rdctl: FLCTL_BANK1_RDCTL,
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_reserved1: [u8; 8usize],
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#[doc = "0x20 - Read Burst/Compare Control and Status Register"]
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pub flctl_rdbrst_ctlstat: FLCTL_RDBRST_CTLSTAT,
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#[doc = "0x24 - Read Burst/Compare Start Address Register"]
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pub flctl_rdbrst_startaddr: FLCTL_RDBRST_STARTADDR,
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#[doc = "0x28 - Read Burst/Compare Length Register"]
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pub flctl_rdbrst_len: FLCTL_RDBRST_LEN,
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_reserved2: [u8; 16usize],
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#[doc = "0x3c - Read Burst/Compare Fail Address Register"]
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pub flctl_rdbrst_failaddr: FLCTL_RDBRST_FAILADDR,
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#[doc = "0x40 - Read Burst/Compare Fail Count Register"]
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pub flctl_rdbrst_failcnt: FLCTL_RDBRST_FAILCNT,
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_reserved3: [u8; 12usize],
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#[doc = "0x50 - Program Control and Status Register"]
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pub flctl_prg_ctlstat: FLCTL_PRG_CTLSTAT,
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#[doc = "0x54 - Program Burst Control and Status Register"]
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pub flctl_prgbrst_ctlstat: FLCTL_PRGBRST_CTLSTAT,
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#[doc = "0x58 - Program Burst Start Address Register"]
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pub flctl_prgbrst_startaddr: FLCTL_PRGBRST_STARTADDR,
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_reserved4: [u8; 4usize],
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#[doc = "0x60 - Program Burst Data0 Register0"]
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pub flctl_prgbrst_data0_0: FLCTL_PRGBRST_DATA0_0,
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#[doc = "0x64 - Program Burst Data0 Register1"]
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pub flctl_prgbrst_data0_1: FLCTL_PRGBRST_DATA0_1,
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#[doc = "0x68 - Program Burst Data0 Register2"]
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pub flctl_prgbrst_data0_2: FLCTL_PRGBRST_DATA0_2,
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#[doc = "0x6c - Program Burst Data0 Register3"]
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pub flctl_prgbrst_data0_3: FLCTL_PRGBRST_DATA0_3,
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#[doc = "0x70 - Program Burst Data1 Register0"]
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pub flctl_prgbrst_data1_0: FLCTL_PRGBRST_DATA1_0,
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#[doc = "0x74 - Program Burst Data1 Register1"]
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pub flctl_prgbrst_data1_1: FLCTL_PRGBRST_DATA1_1,
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#[doc = "0x78 - Program Burst Data1 Register2"]
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pub flctl_prgbrst_data1_2: FLCTL_PRGBRST_DATA1_2,
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#[doc = "0x7c - Program Burst Data1 Register3"]
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pub flctl_prgbrst_data1_3: FLCTL_PRGBRST_DATA1_3,
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#[doc = "0x80 - Program Burst Data2 Register0"]
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pub flctl_prgbrst_data2_0: FLCTL_PRGBRST_DATA2_0,
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#[doc = "0x84 - Program Burst Data2 Register1"]
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pub flctl_prgbrst_data2_1: FLCTL_PRGBRST_DATA2_1,
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#[doc = "0x88 - Program Burst Data2 Register2"]
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pub flctl_prgbrst_data2_2: FLCTL_PRGBRST_DATA2_2,
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#[doc = "0x8c - Program Burst Data2 Register3"]
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pub flctl_prgbrst_data2_3: FLCTL_PRGBRST_DATA2_3,
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#[doc = "0x90 - Program Burst Data3 Register0"]
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pub flctl_prgbrst_data3_0: FLCTL_PRGBRST_DATA3_0,
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#[doc = "0x94 - Program Burst Data3 Register1"]
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pub flctl_prgbrst_data3_1: FLCTL_PRGBRST_DATA3_1,
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#[doc = "0x98 - Program Burst Data3 Register2"]
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pub flctl_prgbrst_data3_2: FLCTL_PRGBRST_DATA3_2,
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#[doc = "0x9c - Program Burst Data3 Register3"]
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pub flctl_prgbrst_data3_3: FLCTL_PRGBRST_DATA3_3,
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#[doc = "0xa0 - Erase Control and Status Register"]
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pub flctl_erase_ctlstat: FLCTL_ERASE_CTLSTAT,
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#[doc = "0xa4 - Erase Sector Address Register"]
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pub flctl_erase_sectaddr: FLCTL_ERASE_SECTADDR,
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_reserved5: [u8; 8usize],
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#[doc = "0xb0 - Information Memory Bank0 Write/Erase Protection Register"]
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pub flctl_bank0_info_weprot: FLCTL_BANK0_INFO_WEPROT,
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#[doc = "0xb4 - Main Memory Bank0 Write/Erase Protection Register"]
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pub flctl_bank0_main_weprot: FLCTL_BANK0_MAIN_WEPROT,
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_reserved6: [u8; 8usize],
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#[doc = "0xc0 - Information Memory Bank1 Write/Erase Protection Register"]
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pub flctl_bank1_info_weprot: FLCTL_BANK1_INFO_WEPROT,
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#[doc = "0xc4 - Main Memory Bank1 Write/Erase Protection Register"]
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pub flctl_bank1_main_weprot: FLCTL_BANK1_MAIN_WEPROT,
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_reserved7: [u8; 8usize],
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#[doc = "0xd0 - Benchmark Control and Status Register"]
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pub flctl_bmrk_ctlstat: FLCTL_BMRK_CTLSTAT,
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#[doc = "0xd4 - Benchmark Instruction Fetch Count Register"]
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pub flctl_bmrk_ifetch: FLCTL_BMRK_IFETCH,
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#[doc = "0xd8 - Benchmark Data Read Count Register"]
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pub flctl_bmrk_dread: FLCTL_BMRK_DREAD,
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#[doc = "0xdc - Benchmark Count Compare Register"]
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pub flctl_bmrk_cmp: FLCTL_BMRK_CMP,
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_reserved8: [u8; 16usize],
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#[doc = "0xf0 - Interrupt Flag Register"]
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pub flctl_ifg: FLCTL_IFG,
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#[doc = "0xf4 - Interrupt Enable Register"]
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pub flctl_ie: FLCTL_IE,
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#[doc = "0xf8 - Clear Interrupt Flag Register"]
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pub flctl_clrifg: FLCTL_CLRIFG,
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#[doc = "0xfc - Set Interrupt Flag Register"]
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pub flctl_setifg: FLCTL_SETIFG,
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#[doc = "0x100 - Read Timing Control Register"]
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pub flctl_read_timctl: FLCTL_READ_TIMCTL,
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#[doc = "0x104 - Read Margin Timing Control Register"]
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pub flctl_readmargin_timctl: FLCTL_READMARGIN_TIMCTL,
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#[doc = "0x108 - Program Verify Timing Control Register"]
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pub flctl_prgver_timctl: FLCTL_PRGVER_TIMCTL,
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#[doc = "0x10c - Erase Verify Timing Control Register"]
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pub flctl_ersver_timctl: FLCTL_ERSVER_TIMCTL,
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#[doc = "0x110 - Leakage Verify Timing Control Register"]
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pub flctl_lkgver_timctl: FLCTL_LKGVER_TIMCTL,
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#[doc = "0x114 - Program Timing Control Register"]
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pub flctl_program_timctl: FLCTL_PROGRAM_TIMCTL,
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#[doc = "0x118 - Erase Timing Control Register"]
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pub flctl_erase_timctl: FLCTL_ERASE_TIMCTL,
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#[doc = "0x11c - Mass Erase Timing Control Register"]
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pub flctl_masserase_timctl: FLCTL_MASSERASE_TIMCTL,
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#[doc = "0x120 - Burst Program Timing Control Register"]
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pub flctl_burstprg_timctl: FLCTL_BURSTPRG_TIMCTL,
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}
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#[doc = "Power Status Register"]
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pub struct FLCTL_POWER_STAT {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Power Status Register"]
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pub mod flctl_power_stat;
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#[doc = "Bank0 Read Control Register"]
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pub struct FLCTL_BANK0_RDCTL {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Bank0 Read Control Register"]
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pub mod flctl_bank0_rdctl;
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#[doc = "Bank1 Read Control Register"]
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pub struct FLCTL_BANK1_RDCTL {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Bank1 Read Control Register"]
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pub mod flctl_bank1_rdctl;
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#[doc = "Read Burst/Compare Control and Status Register"]
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pub struct FLCTL_RDBRST_CTLSTAT {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Read Burst/Compare Control and Status Register"]
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pub mod flctl_rdbrst_ctlstat;
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#[doc = "Read Burst/Compare Start Address Register"]
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pub struct FLCTL_RDBRST_STARTADDR {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Read Burst/Compare Start Address Register"]
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pub mod flctl_rdbrst_startaddr;
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#[doc = "Read Burst/Compare Length Register"]
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pub struct FLCTL_RDBRST_LEN {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Read Burst/Compare Length Register"]
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pub mod flctl_rdbrst_len;
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#[doc = "Read Burst/Compare Fail Address Register"]
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pub struct FLCTL_RDBRST_FAILADDR {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Read Burst/Compare Fail Address Register"]
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pub mod flctl_rdbrst_failaddr;
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#[doc = "Read Burst/Compare Fail Count Register"]
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pub struct FLCTL_RDBRST_FAILCNT {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Read Burst/Compare Fail Count Register"]
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pub mod flctl_rdbrst_failcnt;
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#[doc = "Program Control and Status Register"]
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pub struct FLCTL_PRG_CTLSTAT {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Program Control and Status Register"]
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pub mod flctl_prg_ctlstat;
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#[doc = "Program Burst Control and Status Register"]
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pub struct FLCTL_PRGBRST_CTLSTAT {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Program Burst Control and Status Register"]
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pub mod flctl_prgbrst_ctlstat;
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#[doc = "Program Burst Start Address Register"]
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pub struct FLCTL_PRGBRST_STARTADDR {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Program Burst Start Address Register"]
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pub mod flctl_prgbrst_startaddr;
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#[doc = "Program Burst Data0 Register0"]
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pub struct FLCTL_PRGBRST_DATA0_0 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Program Burst Data0 Register0"]
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pub mod flctl_prgbrst_data0_0;
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#[doc = "Program Burst Data0 Register1"]
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pub struct FLCTL_PRGBRST_DATA0_1 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Program Burst Data0 Register1"]
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pub mod flctl_prgbrst_data0_1;
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#[doc = "Program Burst Data0 Register2"]
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pub struct FLCTL_PRGBRST_DATA0_2 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Program Burst Data0 Register2"]
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pub mod flctl_prgbrst_data0_2;
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#[doc = "Program Burst Data0 Register3"]
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pub struct FLCTL_PRGBRST_DATA0_3 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Program Burst Data0 Register3"]
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pub mod flctl_prgbrst_data0_3;
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#[doc = "Program Burst Data1 Register0"]
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pub struct FLCTL_PRGBRST_DATA1_0 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Program Burst Data1 Register0"]
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pub mod flctl_prgbrst_data1_0;
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#[doc = "Program Burst Data1 Register1"]
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pub struct FLCTL_PRGBRST_DATA1_1 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Program Burst Data1 Register1"]
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pub mod flctl_prgbrst_data1_1;
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#[doc = "Program Burst Data1 Register2"]
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pub struct FLCTL_PRGBRST_DATA1_2 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Program Burst Data1 Register2"]
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pub mod flctl_prgbrst_data1_2;
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#[doc = "Program Burst Data1 Register3"]
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pub struct FLCTL_PRGBRST_DATA1_3 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Program Burst Data1 Register3"]
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pub mod flctl_prgbrst_data1_3;
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#[doc = "Program Burst Data2 Register0"]
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pub struct FLCTL_PRGBRST_DATA2_0 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Program Burst Data2 Register0"]
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pub mod flctl_prgbrst_data2_0;
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#[doc = "Program Burst Data2 Register1"]
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pub struct FLCTL_PRGBRST_DATA2_1 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Program Burst Data2 Register1"]
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pub mod flctl_prgbrst_data2_1;
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#[doc = "Program Burst Data2 Register2"]
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pub struct FLCTL_PRGBRST_DATA2_2 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Program Burst Data2 Register2"]
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pub mod flctl_prgbrst_data2_2;
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#[doc = "Program Burst Data2 Register3"]
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pub struct FLCTL_PRGBRST_DATA2_3 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Program Burst Data2 Register3"]
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pub mod flctl_prgbrst_data2_3;
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#[doc = "Program Burst Data3 Register0"]
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pub struct FLCTL_PRGBRST_DATA3_0 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Program Burst Data3 Register0"]
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pub mod flctl_prgbrst_data3_0;
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#[doc = "Program Burst Data3 Register1"]
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pub struct FLCTL_PRGBRST_DATA3_1 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Program Burst Data3 Register1"]
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pub mod flctl_prgbrst_data3_1;
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#[doc = "Program Burst Data3 Register2"]
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pub struct FLCTL_PRGBRST_DATA3_2 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Program Burst Data3 Register2"]
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pub mod flctl_prgbrst_data3_2;
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#[doc = "Program Burst Data3 Register3"]
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pub struct FLCTL_PRGBRST_DATA3_3 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Program Burst Data3 Register3"]
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pub mod flctl_prgbrst_data3_3;
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#[doc = "Erase Control and Status Register"]
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pub struct FLCTL_ERASE_CTLSTAT {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Erase Control and Status Register"]
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pub mod flctl_erase_ctlstat;
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#[doc = "Erase Sector Address Register"]
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pub struct FLCTL_ERASE_SECTADDR {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Erase Sector Address Register"]
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pub mod flctl_erase_sectaddr;
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#[doc = "Information Memory Bank0 Write/Erase Protection Register"]
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pub struct FLCTL_BANK0_INFO_WEPROT {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Information Memory Bank0 Write/Erase Protection Register"]
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pub mod flctl_bank0_info_weprot;
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#[doc = "Main Memory Bank0 Write/Erase Protection Register"]
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pub struct FLCTL_BANK0_MAIN_WEPROT {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Main Memory Bank0 Write/Erase Protection Register"]
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pub mod flctl_bank0_main_weprot;
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#[doc = "Information Memory Bank1 Write/Erase Protection Register"]
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pub struct FLCTL_BANK1_INFO_WEPROT {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Information Memory Bank1 Write/Erase Protection Register"]
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pub mod flctl_bank1_info_weprot;
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#[doc = "Main Memory Bank1 Write/Erase Protection Register"]
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pub struct FLCTL_BANK1_MAIN_WEPROT {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Main Memory Bank1 Write/Erase Protection Register"]
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pub mod flctl_bank1_main_weprot;
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#[doc = "Benchmark Control and Status Register"]
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pub struct FLCTL_BMRK_CTLSTAT {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Benchmark Control and Status Register"]
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pub mod flctl_bmrk_ctlstat;
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#[doc = "Benchmark Instruction Fetch Count Register"]
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pub struct FLCTL_BMRK_IFETCH {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Benchmark Instruction Fetch Count Register"]
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pub mod flctl_bmrk_ifetch;
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#[doc = "Benchmark Data Read Count Register"]
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pub struct FLCTL_BMRK_DREAD {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Benchmark Data Read Count Register"]
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pub mod flctl_bmrk_dread;
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#[doc = "Benchmark Count Compare Register"]
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pub struct FLCTL_BMRK_CMP {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Benchmark Count Compare Register"]
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pub mod flctl_bmrk_cmp;
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#[doc = "Interrupt Flag Register"]
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pub struct FLCTL_IFG {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Interrupt Flag Register"]
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pub mod flctl_ifg;
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#[doc = "Interrupt Enable Register"]
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pub struct FLCTL_IE {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Interrupt Enable Register"]
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pub mod flctl_ie;
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#[doc = "Clear Interrupt Flag Register"]
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pub struct FLCTL_CLRIFG {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Clear Interrupt Flag Register"]
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pub mod flctl_clrifg;
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#[doc = "Set Interrupt Flag Register"]
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pub struct FLCTL_SETIFG {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Set Interrupt Flag Register"]
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pub mod flctl_setifg;
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#[doc = "Read Timing Control Register"]
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pub struct FLCTL_READ_TIMCTL {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Read Timing Control Register"]
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pub mod flctl_read_timctl;
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#[doc = "Read Margin Timing Control Register"]
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pub struct FLCTL_READMARGIN_TIMCTL {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Read Margin Timing Control Register"]
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pub mod flctl_readmargin_timctl;
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#[doc = "Program Verify Timing Control Register"]
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pub struct FLCTL_PRGVER_TIMCTL {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Program Verify Timing Control Register"]
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pub mod flctl_prgver_timctl;
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#[doc = "Erase Verify Timing Control Register"]
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pub struct FLCTL_ERSVER_TIMCTL {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Erase Verify Timing Control Register"]
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pub mod flctl_ersver_timctl;
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#[doc = "Leakage Verify Timing Control Register"]
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pub struct FLCTL_LKGVER_TIMCTL {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Leakage Verify Timing Control Register"]
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pub mod flctl_lkgver_timctl;
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#[doc = "Program Timing Control Register"]
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pub struct FLCTL_PROGRAM_TIMCTL {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Program Timing Control Register"]
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pub mod flctl_program_timctl;
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#[doc = "Erase Timing Control Register"]
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pub struct FLCTL_ERASE_TIMCTL {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Erase Timing Control Register"]
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pub mod flctl_erase_timctl;
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#[doc = "Mass Erase Timing Control Register"]
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pub struct FLCTL_MASSERASE_TIMCTL {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Mass Erase Timing Control Register"]
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pub mod flctl_masserase_timctl;
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#[doc = "Burst Program Timing Control Register"]
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pub struct FLCTL_BURSTPRG_TIMCTL {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Burst Program Timing Control Register"]
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pub mod flctl_burstprg_timctl;
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