210 lines
7.1 KiB
Rust
210 lines
7.1 KiB
Rust
#[doc = r" Register block"]
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#[repr(C)]
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pub struct RegisterBlock {
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#[doc = "0x00 - Device Configuration Status"]
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pub dma_device_cfg: DMA_DEVICE_CFG,
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#[doc = "0x04 - Software Channel Trigger Register"]
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pub dma_sw_chtrig: DMA_SW_CHTRIG,
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_reserved0: [u8; 8usize],
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#[doc = "0x10 - Channel n Source Configuration Register"]
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pub dma_ch_srccfg: [DMA_CH_SRCCFG; 32],
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_reserved1: [u8; 112usize],
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#[doc = "0x100 - Interrupt 1 Source Channel Configuration"]
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pub dma_int1_srccfg: DMA_INT1_SRCCFG,
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#[doc = "0x104 - Interrupt 2 Source Channel Configuration Register"]
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pub dma_int2_srccfg: DMA_INT2_SRCCFG,
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#[doc = "0x108 - Interrupt 3 Source Channel Configuration Register"]
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pub dma_int3_srccfg: DMA_INT3_SRCCFG,
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_reserved2: [u8; 4usize],
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#[doc = "0x110 - Interrupt 0 Source Channel Flag Register"]
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pub dma_int0_srcflg: DMA_INT0_SRCFLG,
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#[doc = "0x114 - Interrupt 0 Source Channel Clear Flag Register"]
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pub dma_int0_clrflg: DMA_INT0_CLRFLG,
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_reserved3: [u8; 3816usize],
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#[doc = "0x1000 - Status Register"]
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pub dma_stat: DMA_STAT,
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#[doc = "0x1004 - Configuration Register"]
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pub dma_cfg: DMA_CFG,
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#[doc = "0x1008 - Channel Control Data Base Pointer Register"]
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pub dma_ctlbase: DMA_CTLBASE,
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#[doc = "0x100c - Channel Alternate Control Data Base Pointer Register"]
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pub dma_altbase: DMA_ALTBASE,
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#[doc = "0x1010 - Channel Wait on Request Status Register"]
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pub dma_waitstat: DMA_WAITSTAT,
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#[doc = "0x1014 - Channel Software Request Register"]
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pub dma_swreq: DMA_SWREQ,
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#[doc = "0x1018 - Channel Useburst Set Register"]
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pub dma_useburstset: DMA_USEBURSTSET,
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#[doc = "0x101c - Channel Useburst Clear Register"]
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pub dma_useburstclr: DMA_USEBURSTCLR,
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#[doc = "0x1020 - Channel Request Mask Set Register"]
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pub dma_reqmaskset: DMA_REQMASKSET,
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#[doc = "0x1024 - Channel Request Mask Clear Register"]
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pub dma_reqmaskclr: DMA_REQMASKCLR,
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#[doc = "0x1028 - Channel Enable Set Register"]
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pub dma_enaset: DMA_ENASET,
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#[doc = "0x102c - Channel Enable Clear Register"]
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pub dma_enaclr: DMA_ENACLR,
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#[doc = "0x1030 - Channel Primary-Alternate Set Register"]
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pub dma_altset: DMA_ALTSET,
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#[doc = "0x1034 - Channel Primary-Alternate Clear Register"]
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pub dma_altclr: DMA_ALTCLR,
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#[doc = "0x1038 - Channel Priority Set Register"]
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pub dma_prioset: DMA_PRIOSET,
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#[doc = "0x103c - Channel Priority Clear Register"]
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pub dma_prioclr: DMA_PRIOCLR,
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_reserved4: [u8; 12usize],
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#[doc = "0x104c - Bus Error Clear Register"]
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pub dma_errclr: DMA_ERRCLR,
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}
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#[doc = "Device Configuration Status"]
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pub struct DMA_DEVICE_CFG {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Device Configuration Status"]
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pub mod dma_device_cfg;
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#[doc = "Software Channel Trigger Register"]
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pub struct DMA_SW_CHTRIG {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Software Channel Trigger Register"]
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pub mod dma_sw_chtrig;
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#[doc = "Channel n Source Configuration Register"]
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pub struct DMA_CH_SRCCFG {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Channel n Source Configuration Register"]
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pub mod dma_ch_srccfg;
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#[doc = "Interrupt 1 Source Channel Configuration"]
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pub struct DMA_INT1_SRCCFG {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Interrupt 1 Source Channel Configuration"]
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pub mod dma_int1_srccfg;
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#[doc = "Interrupt 2 Source Channel Configuration Register"]
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pub struct DMA_INT2_SRCCFG {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Interrupt 2 Source Channel Configuration Register"]
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pub mod dma_int2_srccfg;
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#[doc = "Interrupt 3 Source Channel Configuration Register"]
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pub struct DMA_INT3_SRCCFG {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Interrupt 3 Source Channel Configuration Register"]
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pub mod dma_int3_srccfg;
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#[doc = "Interrupt 0 Source Channel Flag Register"]
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pub struct DMA_INT0_SRCFLG {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Interrupt 0 Source Channel Flag Register"]
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pub mod dma_int0_srcflg;
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#[doc = "Interrupt 0 Source Channel Clear Flag Register"]
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pub struct DMA_INT0_CLRFLG {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Interrupt 0 Source Channel Clear Flag Register"]
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pub mod dma_int0_clrflg;
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#[doc = "Status Register"]
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pub struct DMA_STAT {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Status Register"]
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pub mod dma_stat;
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#[doc = "Configuration Register"]
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pub struct DMA_CFG {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Configuration Register"]
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pub mod dma_cfg;
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#[doc = "Channel Control Data Base Pointer Register"]
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pub struct DMA_CTLBASE {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Channel Control Data Base Pointer Register"]
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pub mod dma_ctlbase;
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#[doc = "Channel Alternate Control Data Base Pointer Register"]
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pub struct DMA_ALTBASE {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Channel Alternate Control Data Base Pointer Register"]
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pub mod dma_altbase;
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#[doc = "Channel Wait on Request Status Register"]
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pub struct DMA_WAITSTAT {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Channel Wait on Request Status Register"]
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pub mod dma_waitstat;
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#[doc = "Channel Software Request Register"]
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pub struct DMA_SWREQ {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Channel Software Request Register"]
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pub mod dma_swreq;
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#[doc = "Channel Useburst Set Register"]
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pub struct DMA_USEBURSTSET {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Channel Useburst Set Register"]
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pub mod dma_useburstset;
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#[doc = "Channel Useburst Clear Register"]
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pub struct DMA_USEBURSTCLR {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Channel Useburst Clear Register"]
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pub mod dma_useburstclr;
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#[doc = "Channel Request Mask Set Register"]
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pub struct DMA_REQMASKSET {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Channel Request Mask Set Register"]
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pub mod dma_reqmaskset;
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#[doc = "Channel Request Mask Clear Register"]
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pub struct DMA_REQMASKCLR {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Channel Request Mask Clear Register"]
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pub mod dma_reqmaskclr;
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#[doc = "Channel Enable Set Register"]
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pub struct DMA_ENASET {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Channel Enable Set Register"]
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pub mod dma_enaset;
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#[doc = "Channel Enable Clear Register"]
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pub struct DMA_ENACLR {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Channel Enable Clear Register"]
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pub mod dma_enaclr;
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#[doc = "Channel Primary-Alternate Set Register"]
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pub struct DMA_ALTSET {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Channel Primary-Alternate Set Register"]
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pub mod dma_altset;
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#[doc = "Channel Primary-Alternate Clear Register"]
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pub struct DMA_ALTCLR {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Channel Primary-Alternate Clear Register"]
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pub mod dma_altclr;
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#[doc = "Channel Priority Set Register"]
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pub struct DMA_PRIOSET {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Channel Priority Set Register"]
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pub mod dma_prioset;
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#[doc = "Channel Priority Clear Register"]
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pub struct DMA_PRIOCLR {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Channel Priority Clear Register"]
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pub mod dma_prioclr;
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#[doc = "Bus Error Clear Register"]
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pub struct DMA_ERRCLR {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Bus Error Clear Register"]
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pub mod dma_errclr;
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