#[doc = r" Value read from the register"]
pub struct R {
    bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
    bits: u32,
}
impl super::ADC14CTL1 {
    #[doc = r" Modifies the contents of the register"]
    #[inline]
    pub fn modify<F>(&self, f: F)
    where
        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
    {
        let bits = self.register.get();
        let r = R { bits: bits };
        let mut w = W { bits: bits };
        f(&r, &mut w);
        self.register.set(w.bits);
    }
    #[doc = r" Reads the contents of the register"]
    #[inline]
    pub fn read(&self) -> R {
        R {
            bits: self.register.get(),
        }
    }
    #[doc = r" Writes to the register"]
    #[inline]
    pub fn write<F>(&self, f: F)
    where
        F: FnOnce(&mut W) -> &mut W,
    {
        let mut w = W::reset_value();
        f(&mut w);
        self.register.set(w.bits);
    }
    #[doc = r" Writes the reset value to the register"]
    #[inline]
    pub fn reset(&self) {
        self.write(|w| w)
    }
}
#[doc = "Possible values of the field `ADC14PWRMD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC14PWRMDR {
    #[doc = "Regular power mode for use with any resolution setting. Sample rate can be up to 1 Msps."]
    ADC14PWRMD_0,
    #[doc = "Low-power mode for 12-bit, 10-bit, and 8-bit resolution settings. Sample rate must not exceed 200 ksps."]
    ADC14PWRMD_2,
    #[doc = r" Reserved"]
    _Reserved(u8),
}
impl ADC14PWRMDR {
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bits(&self) -> u8 {
        match *self {
            ADC14PWRMDR::ADC14PWRMD_0 => 0,
            ADC14PWRMDR::ADC14PWRMD_2 => 2,
            ADC14PWRMDR::_Reserved(bits) => bits,
        }
    }
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _from(value: u8) -> ADC14PWRMDR {
        match value {
            0 => ADC14PWRMDR::ADC14PWRMD_0,
            2 => ADC14PWRMDR::ADC14PWRMD_2,
            i => ADC14PWRMDR::_Reserved(i),
        }
    }
    #[doc = "Checks if the value of the field is `ADC14PWRMD_0`"]
    #[inline]
    pub fn is_adc14pwrmd_0(&self) -> bool {
        *self == ADC14PWRMDR::ADC14PWRMD_0
    }
    #[doc = "Checks if the value of the field is `ADC14PWRMD_2`"]
    #[inline]
    pub fn is_adc14pwrmd_2(&self) -> bool {
        *self == ADC14PWRMDR::ADC14PWRMD_2
    }
}
#[doc = "Possible values of the field `ADC14REFBURST`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC14REFBURSTR {
    #[doc = "ADC reference buffer on continuously"]
    ADC14REFBURST_0,
    #[doc = "ADC reference buffer on only during sample-and-conversion"]
    ADC14REFBURST_1,
}
impl ADC14REFBURSTR {
    #[doc = r" Returns `true` if the bit is clear (0)"]
    #[inline]
    pub fn bit_is_clear(&self) -> bool {
        !self.bit()
    }
    #[doc = r" Returns `true` if the bit is set (1)"]
    #[inline]
    pub fn bit_is_set(&self) -> bool {
        self.bit()
    }
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bit(&self) -> bool {
        match *self {
            ADC14REFBURSTR::ADC14REFBURST_0 => false,
            ADC14REFBURSTR::ADC14REFBURST_1 => true,
        }
    }
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _from(value: bool) -> ADC14REFBURSTR {
        match value {
            false => ADC14REFBURSTR::ADC14REFBURST_0,
            true => ADC14REFBURSTR::ADC14REFBURST_1,
        }
    }
    #[doc = "Checks if the value of the field is `ADC14REFBURST_0`"]
    #[inline]
    pub fn is_adc14refburst_0(&self) -> bool {
        *self == ADC14REFBURSTR::ADC14REFBURST_0
    }
    #[doc = "Checks if the value of the field is `ADC14REFBURST_1`"]
    #[inline]
    pub fn is_adc14refburst_1(&self) -> bool {
        *self == ADC14REFBURSTR::ADC14REFBURST_1
    }
}
#[doc = "Possible values of the field `ADC14DF`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC14DFR {
    #[doc = "Binary unsigned. Theoretically, for ADC14DIF = 0 and 14-bit mode, the analog input voltage - V(REF) results in 0000h, and the analog input voltage + V(REF) results in 3FFFh"]
    ADC14DF_0,
    #[doc = "Signed binary (2s complement), left aligned. Theoretically, for ADC14DIF = 0 and 14-bit mode, the analog input voltage - V(REF) results in 8000h, and the analog input voltage + V(REF) results in 7FFCh"]
    ADC14DF_1,
}
impl ADC14DFR {
    #[doc = r" Returns `true` if the bit is clear (0)"]
    #[inline]
    pub fn bit_is_clear(&self) -> bool {
        !self.bit()
    }
    #[doc = r" Returns `true` if the bit is set (1)"]
    #[inline]
    pub fn bit_is_set(&self) -> bool {
        self.bit()
    }
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bit(&self) -> bool {
        match *self {
            ADC14DFR::ADC14DF_0 => false,
            ADC14DFR::ADC14DF_1 => true,
        }
    }
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _from(value: bool) -> ADC14DFR {
        match value {
            false => ADC14DFR::ADC14DF_0,
            true => ADC14DFR::ADC14DF_1,
        }
    }
    #[doc = "Checks if the value of the field is `ADC14DF_0`"]
    #[inline]
    pub fn is_adc14df_0(&self) -> bool {
        *self == ADC14DFR::ADC14DF_0
    }
    #[doc = "Checks if the value of the field is `ADC14DF_1`"]
    #[inline]
    pub fn is_adc14df_1(&self) -> bool {
        *self == ADC14DFR::ADC14DF_1
    }
}
#[doc = "Possible values of the field `ADC14RES`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC14RESR {
    #[doc = "8 bit (9 clock cycle conversion time)"]
    ADC14RES_0,
    #[doc = "10 bit (11 clock cycle conversion time)"]
    ADC14RES_1,
    #[doc = "12 bit (14 clock cycle conversion time)"]
    ADC14RES_2,
    #[doc = "14 bit (16 clock cycle conversion time)"]
    ADC14RES_3,
}
impl ADC14RESR {
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bits(&self) -> u8 {
        match *self {
            ADC14RESR::ADC14RES_0 => 0,
            ADC14RESR::ADC14RES_1 => 1,
            ADC14RESR::ADC14RES_2 => 2,
            ADC14RESR::ADC14RES_3 => 3,
        }
    }
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _from(value: u8) -> ADC14RESR {
        match value {
            0 => ADC14RESR::ADC14RES_0,
            1 => ADC14RESR::ADC14RES_1,
            2 => ADC14RESR::ADC14RES_2,
            3 => ADC14RESR::ADC14RES_3,
            _ => unreachable!(),
        }
    }
    #[doc = "Checks if the value of the field is `ADC14RES_0`"]
    #[inline]
    pub fn is_adc14res_0(&self) -> bool {
        *self == ADC14RESR::ADC14RES_0
    }
    #[doc = "Checks if the value of the field is `ADC14RES_1`"]
    #[inline]
    pub fn is_adc14res_1(&self) -> bool {
        *self == ADC14RESR::ADC14RES_1
    }
    #[doc = "Checks if the value of the field is `ADC14RES_2`"]
    #[inline]
    pub fn is_adc14res_2(&self) -> bool {
        *self == ADC14RESR::ADC14RES_2
    }
    #[doc = "Checks if the value of the field is `ADC14RES_3`"]
    #[inline]
    pub fn is_adc14res_3(&self) -> bool {
        *self == ADC14RESR::ADC14RES_3
    }
}
#[doc = r" Value of the field"]
pub struct ADC14CSTARTADDR {
    bits: u8,
}
impl ADC14CSTARTADDR {
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bits(&self) -> u8 {
        self.bits
    }
}
#[doc = "Possible values of the field `ADC14BATMAP`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC14BATMAPR {
    #[doc = "ADC internal 1/2 x AVCC channel is not selected for ADC"]
    ADC14BATMAP_0,
    #[doc = "ADC internal 1/2 x AVCC channel is selected for ADC input channel MAX"]
    ADC14BATMAP_1,
}
impl ADC14BATMAPR {
    #[doc = r" Returns `true` if the bit is clear (0)"]
    #[inline]
    pub fn bit_is_clear(&self) -> bool {
        !self.bit()
    }
    #[doc = r" Returns `true` if the bit is set (1)"]
    #[inline]
    pub fn bit_is_set(&self) -> bool {
        self.bit()
    }
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bit(&self) -> bool {
        match *self {
            ADC14BATMAPR::ADC14BATMAP_0 => false,
            ADC14BATMAPR::ADC14BATMAP_1 => true,
        }
    }
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _from(value: bool) -> ADC14BATMAPR {
        match value {
            false => ADC14BATMAPR::ADC14BATMAP_0,
            true => ADC14BATMAPR::ADC14BATMAP_1,
        }
    }
    #[doc = "Checks if the value of the field is `ADC14BATMAP_0`"]
    #[inline]
    pub fn is_adc14batmap_0(&self) -> bool {
        *self == ADC14BATMAPR::ADC14BATMAP_0
    }
    #[doc = "Checks if the value of the field is `ADC14BATMAP_1`"]
    #[inline]
    pub fn is_adc14batmap_1(&self) -> bool {
        *self == ADC14BATMAPR::ADC14BATMAP_1
    }
}
#[doc = "Possible values of the field `ADC14TCMAP`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC14TCMAPR {
    #[doc = "ADC internal temperature sensor channel is not selected for ADC"]
    ADC14TCMAP_0,
    #[doc = "ADC internal temperature sensor channel is selected for ADC input channel MAX-1"]
    ADC14TCMAP_1,
}
impl ADC14TCMAPR {
    #[doc = r" Returns `true` if the bit is clear (0)"]
    #[inline]
    pub fn bit_is_clear(&self) -> bool {
        !self.bit()
    }
    #[doc = r" Returns `true` if the bit is set (1)"]
    #[inline]
    pub fn bit_is_set(&self) -> bool {
        self.bit()
    }
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bit(&self) -> bool {
        match *self {
            ADC14TCMAPR::ADC14TCMAP_0 => false,
            ADC14TCMAPR::ADC14TCMAP_1 => true,
        }
    }
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _from(value: bool) -> ADC14TCMAPR {
        match value {
            false => ADC14TCMAPR::ADC14TCMAP_0,
            true => ADC14TCMAPR::ADC14TCMAP_1,
        }
    }
    #[doc = "Checks if the value of the field is `ADC14TCMAP_0`"]
    #[inline]
    pub fn is_adc14tcmap_0(&self) -> bool {
        *self == ADC14TCMAPR::ADC14TCMAP_0
    }
    #[doc = "Checks if the value of the field is `ADC14TCMAP_1`"]
    #[inline]
    pub fn is_adc14tcmap_1(&self) -> bool {
        *self == ADC14TCMAPR::ADC14TCMAP_1
    }
}
#[doc = "Possible values of the field `ADC14CH0MAP`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC14CH0MAPR {
    #[doc = "ADC input channel internal 0 is not selected"]
    ADC14CH0MAP_0,
    #[doc = "ADC input channel internal 0 is selected for ADC input channel MAX-2"]
    ADC14CH0MAP_1,
}
impl ADC14CH0MAPR {
    #[doc = r" Returns `true` if the bit is clear (0)"]
    #[inline]
    pub fn bit_is_clear(&self) -> bool {
        !self.bit()
    }
    #[doc = r" Returns `true` if the bit is set (1)"]
    #[inline]
    pub fn bit_is_set(&self) -> bool {
        self.bit()
    }
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bit(&self) -> bool {
        match *self {
            ADC14CH0MAPR::ADC14CH0MAP_0 => false,
            ADC14CH0MAPR::ADC14CH0MAP_1 => true,
        }
    }
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _from(value: bool) -> ADC14CH0MAPR {
        match value {
            false => ADC14CH0MAPR::ADC14CH0MAP_0,
            true => ADC14CH0MAPR::ADC14CH0MAP_1,
        }
    }
    #[doc = "Checks if the value of the field is `ADC14CH0MAP_0`"]
    #[inline]
    pub fn is_adc14ch0map_0(&self) -> bool {
        *self == ADC14CH0MAPR::ADC14CH0MAP_0
    }
    #[doc = "Checks if the value of the field is `ADC14CH0MAP_1`"]
    #[inline]
    pub fn is_adc14ch0map_1(&self) -> bool {
        *self == ADC14CH0MAPR::ADC14CH0MAP_1
    }
}
#[doc = "Possible values of the field `ADC14CH1MAP`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC14CH1MAPR {
    #[doc = "ADC input channel internal 1 is not selected"]
    ADC14CH1MAP_0,
    #[doc = "ADC input channel internal 1 is selected for ADC input channel MAX-3"]
    ADC14CH1MAP_1,
}
impl ADC14CH1MAPR {
    #[doc = r" Returns `true` if the bit is clear (0)"]
    #[inline]
    pub fn bit_is_clear(&self) -> bool {
        !self.bit()
    }
    #[doc = r" Returns `true` if the bit is set (1)"]
    #[inline]
    pub fn bit_is_set(&self) -> bool {
        self.bit()
    }
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bit(&self) -> bool {
        match *self {
            ADC14CH1MAPR::ADC14CH1MAP_0 => false,
            ADC14CH1MAPR::ADC14CH1MAP_1 => true,
        }
    }
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _from(value: bool) -> ADC14CH1MAPR {
        match value {
            false => ADC14CH1MAPR::ADC14CH1MAP_0,
            true => ADC14CH1MAPR::ADC14CH1MAP_1,
        }
    }
    #[doc = "Checks if the value of the field is `ADC14CH1MAP_0`"]
    #[inline]
    pub fn is_adc14ch1map_0(&self) -> bool {
        *self == ADC14CH1MAPR::ADC14CH1MAP_0
    }
    #[doc = "Checks if the value of the field is `ADC14CH1MAP_1`"]
    #[inline]
    pub fn is_adc14ch1map_1(&self) -> bool {
        *self == ADC14CH1MAPR::ADC14CH1MAP_1
    }
}
#[doc = "Possible values of the field `ADC14CH2MAP`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC14CH2MAPR {
    #[doc = "ADC input channel internal 2 is not selected"]
    ADC14CH2MAP_0,
    #[doc = "ADC input channel internal 2 is selected for ADC input channel MAX-4"]
    ADC14CH2MAP_1,
}
impl ADC14CH2MAPR {
    #[doc = r" Returns `true` if the bit is clear (0)"]
    #[inline]
    pub fn bit_is_clear(&self) -> bool {
        !self.bit()
    }
    #[doc = r" Returns `true` if the bit is set (1)"]
    #[inline]
    pub fn bit_is_set(&self) -> bool {
        self.bit()
    }
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bit(&self) -> bool {
        match *self {
            ADC14CH2MAPR::ADC14CH2MAP_0 => false,
            ADC14CH2MAPR::ADC14CH2MAP_1 => true,
        }
    }
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _from(value: bool) -> ADC14CH2MAPR {
        match value {
            false => ADC14CH2MAPR::ADC14CH2MAP_0,
            true => ADC14CH2MAPR::ADC14CH2MAP_1,
        }
    }
    #[doc = "Checks if the value of the field is `ADC14CH2MAP_0`"]
    #[inline]
    pub fn is_adc14ch2map_0(&self) -> bool {
        *self == ADC14CH2MAPR::ADC14CH2MAP_0
    }
    #[doc = "Checks if the value of the field is `ADC14CH2MAP_1`"]
    #[inline]
    pub fn is_adc14ch2map_1(&self) -> bool {
        *self == ADC14CH2MAPR::ADC14CH2MAP_1
    }
}
#[doc = "Possible values of the field `ADC14CH3MAP`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC14CH3MAPR {
    #[doc = "ADC input channel internal 3 is not selected"]
    ADC14CH3MAP_0,
    #[doc = "ADC input channel internal 3 is selected for ADC input channel MAX-5"]
    ADC14CH3MAP_1,
}
impl ADC14CH3MAPR {
    #[doc = r" Returns `true` if the bit is clear (0)"]
    #[inline]
    pub fn bit_is_clear(&self) -> bool {
        !self.bit()
    }
    #[doc = r" Returns `true` if the bit is set (1)"]
    #[inline]
    pub fn bit_is_set(&self) -> bool {
        self.bit()
    }
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bit(&self) -> bool {
        match *self {
            ADC14CH3MAPR::ADC14CH3MAP_0 => false,
            ADC14CH3MAPR::ADC14CH3MAP_1 => true,
        }
    }
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _from(value: bool) -> ADC14CH3MAPR {
        match value {
            false => ADC14CH3MAPR::ADC14CH3MAP_0,
            true => ADC14CH3MAPR::ADC14CH3MAP_1,
        }
    }
    #[doc = "Checks if the value of the field is `ADC14CH3MAP_0`"]
    #[inline]
    pub fn is_adc14ch3map_0(&self) -> bool {
        *self == ADC14CH3MAPR::ADC14CH3MAP_0
    }
    #[doc = "Checks if the value of the field is `ADC14CH3MAP_1`"]
    #[inline]
    pub fn is_adc14ch3map_1(&self) -> bool {
        *self == ADC14CH3MAPR::ADC14CH3MAP_1
    }
}
#[doc = "Values that can be written to the field `ADC14PWRMD`"]
pub enum ADC14PWRMDW {
    #[doc = "Regular power mode for use with any resolution setting. Sample rate can be up to 1 Msps."]
    ADC14PWRMD_0,
    #[doc = "Low-power mode for 12-bit, 10-bit, and 8-bit resolution settings. Sample rate must not exceed 200 ksps."]
    ADC14PWRMD_2,
}
impl ADC14PWRMDW {
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _bits(&self) -> u8 {
        match *self {
            ADC14PWRMDW::ADC14PWRMD_0 => 0,
            ADC14PWRMDW::ADC14PWRMD_2 => 2,
        }
    }
}
#[doc = r" Proxy"]
pub struct _ADC14PWRMDW<'a> {
    w: &'a mut W,
}
impl<'a> _ADC14PWRMDW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: ADC14PWRMDW) -> &'a mut W {
        unsafe { self.bits(variant._bits()) }
    }
    #[doc = "Regular power mode for use with any resolution setting. Sample rate can be up to 1 Msps."]
    #[inline]
    pub fn adc14pwrmd_0(self) -> &'a mut W {
        self.variant(ADC14PWRMDW::ADC14PWRMD_0)
    }
    #[doc = "Low-power mode for 12-bit, 10-bit, and 8-bit resolution settings. Sample rate must not exceed 200 ksps."]
    #[inline]
    pub fn adc14pwrmd_2(self) -> &'a mut W {
        self.variant(ADC14PWRMDW::ADC14PWRMD_2)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        const MASK: u8 = 3;
        const OFFSET: u8 = 0;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `ADC14REFBURST`"]
pub enum ADC14REFBURSTW {
    #[doc = "ADC reference buffer on continuously"]
    ADC14REFBURST_0,
    #[doc = "ADC reference buffer on only during sample-and-conversion"]
    ADC14REFBURST_1,
}
impl ADC14REFBURSTW {
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _bits(&self) -> bool {
        match *self {
            ADC14REFBURSTW::ADC14REFBURST_0 => false,
            ADC14REFBURSTW::ADC14REFBURST_1 => true,
        }
    }
}
#[doc = r" Proxy"]
pub struct _ADC14REFBURSTW<'a> {
    w: &'a mut W,
}
impl<'a> _ADC14REFBURSTW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: ADC14REFBURSTW) -> &'a mut W {
        {
            self.bit(variant._bits())
        }
    }
    #[doc = "ADC reference buffer on continuously"]
    #[inline]
    pub fn adc14refburst_0(self) -> &'a mut W {
        self.variant(ADC14REFBURSTW::ADC14REFBURST_0)
    }
    #[doc = "ADC reference buffer on only during sample-and-conversion"]
    #[inline]
    pub fn adc14refburst_1(self) -> &'a mut W {
        self.variant(ADC14REFBURSTW::ADC14REFBURST_1)
    }
    #[doc = r" Sets the field bit"]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r" Clears the field bit"]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub fn bit(self, value: bool) -> &'a mut W {
        const MASK: bool = true;
        const OFFSET: u8 = 2;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `ADC14DF`"]
pub enum ADC14DFW {
    #[doc = "Binary unsigned. Theoretically, for ADC14DIF = 0 and 14-bit mode, the analog input voltage - V(REF) results in 0000h, and the analog input voltage + V(REF) results in 3FFFh"]
    ADC14DF_0,
    #[doc = "Signed binary (2s complement), left aligned. Theoretically, for ADC14DIF = 0 and 14-bit mode, the analog input voltage - V(REF) results in 8000h, and the analog input voltage + V(REF) results in 7FFCh"]
    ADC14DF_1,
}
impl ADC14DFW {
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _bits(&self) -> bool {
        match *self {
            ADC14DFW::ADC14DF_0 => false,
            ADC14DFW::ADC14DF_1 => true,
        }
    }
}
#[doc = r" Proxy"]
pub struct _ADC14DFW<'a> {
    w: &'a mut W,
}
impl<'a> _ADC14DFW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: ADC14DFW) -> &'a mut W {
        {
            self.bit(variant._bits())
        }
    }
    #[doc = "Binary unsigned. Theoretically, for ADC14DIF = 0 and 14-bit mode, the analog input voltage - V(REF) results in 0000h, and the analog input voltage + V(REF) results in 3FFFh"]
    #[inline]
    pub fn adc14df_0(self) -> &'a mut W {
        self.variant(ADC14DFW::ADC14DF_0)
    }
    #[doc = "Signed binary (2s complement), left aligned. Theoretically, for ADC14DIF = 0 and 14-bit mode, the analog input voltage - V(REF) results in 8000h, and the analog input voltage + V(REF) results in 7FFCh"]
    #[inline]
    pub fn adc14df_1(self) -> &'a mut W {
        self.variant(ADC14DFW::ADC14DF_1)
    }
    #[doc = r" Sets the field bit"]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r" Clears the field bit"]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub fn bit(self, value: bool) -> &'a mut W {
        const MASK: bool = true;
        const OFFSET: u8 = 3;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `ADC14RES`"]
pub enum ADC14RESW {
    #[doc = "8 bit (9 clock cycle conversion time)"]
    ADC14RES_0,
    #[doc = "10 bit (11 clock cycle conversion time)"]
    ADC14RES_1,
    #[doc = "12 bit (14 clock cycle conversion time)"]
    ADC14RES_2,
    #[doc = "14 bit (16 clock cycle conversion time)"]
    ADC14RES_3,
}
impl ADC14RESW {
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _bits(&self) -> u8 {
        match *self {
            ADC14RESW::ADC14RES_0 => 0,
            ADC14RESW::ADC14RES_1 => 1,
            ADC14RESW::ADC14RES_2 => 2,
            ADC14RESW::ADC14RES_3 => 3,
        }
    }
}
#[doc = r" Proxy"]
pub struct _ADC14RESW<'a> {
    w: &'a mut W,
}
impl<'a> _ADC14RESW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: ADC14RESW) -> &'a mut W {
        {
            self.bits(variant._bits())
        }
    }
    #[doc = "8 bit (9 clock cycle conversion time)"]
    #[inline]
    pub fn adc14res_0(self) -> &'a mut W {
        self.variant(ADC14RESW::ADC14RES_0)
    }
    #[doc = "10 bit (11 clock cycle conversion time)"]
    #[inline]
    pub fn adc14res_1(self) -> &'a mut W {
        self.variant(ADC14RESW::ADC14RES_1)
    }
    #[doc = "12 bit (14 clock cycle conversion time)"]
    #[inline]
    pub fn adc14res_2(self) -> &'a mut W {
        self.variant(ADC14RESW::ADC14RES_2)
    }
    #[doc = "14 bit (16 clock cycle conversion time)"]
    #[inline]
    pub fn adc14res_3(self) -> &'a mut W {
        self.variant(ADC14RESW::ADC14RES_3)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub fn bits(self, value: u8) -> &'a mut W {
        const MASK: u8 = 3;
        const OFFSET: u8 = 4;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = r" Proxy"]
pub struct _ADC14CSTARTADDW<'a> {
    w: &'a mut W,
}
impl<'a> _ADC14CSTARTADDW<'a> {
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        const MASK: u8 = 31;
        const OFFSET: u8 = 16;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `ADC14BATMAP`"]
pub enum ADC14BATMAPW {
    #[doc = "ADC internal 1/2 x AVCC channel is not selected for ADC"]
    ADC14BATMAP_0,
    #[doc = "ADC internal 1/2 x AVCC channel is selected for ADC input channel MAX"]
    ADC14BATMAP_1,
}
impl ADC14BATMAPW {
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _bits(&self) -> bool {
        match *self {
            ADC14BATMAPW::ADC14BATMAP_0 => false,
            ADC14BATMAPW::ADC14BATMAP_1 => true,
        }
    }
}
#[doc = r" Proxy"]
pub struct _ADC14BATMAPW<'a> {
    w: &'a mut W,
}
impl<'a> _ADC14BATMAPW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: ADC14BATMAPW) -> &'a mut W {
        {
            self.bit(variant._bits())
        }
    }
    #[doc = "ADC internal 1/2 x AVCC channel is not selected for ADC"]
    #[inline]
    pub fn adc14batmap_0(self) -> &'a mut W {
        self.variant(ADC14BATMAPW::ADC14BATMAP_0)
    }
    #[doc = "ADC internal 1/2 x AVCC channel is selected for ADC input channel MAX"]
    #[inline]
    pub fn adc14batmap_1(self) -> &'a mut W {
        self.variant(ADC14BATMAPW::ADC14BATMAP_1)
    }
    #[doc = r" Sets the field bit"]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r" Clears the field bit"]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub fn bit(self, value: bool) -> &'a mut W {
        const MASK: bool = true;
        const OFFSET: u8 = 22;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `ADC14TCMAP`"]
pub enum ADC14TCMAPW {
    #[doc = "ADC internal temperature sensor channel is not selected for ADC"]
    ADC14TCMAP_0,
    #[doc = "ADC internal temperature sensor channel is selected for ADC input channel MAX-1"]
    ADC14TCMAP_1,
}
impl ADC14TCMAPW {
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _bits(&self) -> bool {
        match *self {
            ADC14TCMAPW::ADC14TCMAP_0 => false,
            ADC14TCMAPW::ADC14TCMAP_1 => true,
        }
    }
}
#[doc = r" Proxy"]
pub struct _ADC14TCMAPW<'a> {
    w: &'a mut W,
}
impl<'a> _ADC14TCMAPW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: ADC14TCMAPW) -> &'a mut W {
        {
            self.bit(variant._bits())
        }
    }
    #[doc = "ADC internal temperature sensor channel is not selected for ADC"]
    #[inline]
    pub fn adc14tcmap_0(self) -> &'a mut W {
        self.variant(ADC14TCMAPW::ADC14TCMAP_0)
    }
    #[doc = "ADC internal temperature sensor channel is selected for ADC input channel MAX-1"]
    #[inline]
    pub fn adc14tcmap_1(self) -> &'a mut W {
        self.variant(ADC14TCMAPW::ADC14TCMAP_1)
    }
    #[doc = r" Sets the field bit"]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r" Clears the field bit"]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub fn bit(self, value: bool) -> &'a mut W {
        const MASK: bool = true;
        const OFFSET: u8 = 23;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `ADC14CH0MAP`"]
pub enum ADC14CH0MAPW {
    #[doc = "ADC input channel internal 0 is not selected"]
    ADC14CH0MAP_0,
    #[doc = "ADC input channel internal 0 is selected for ADC input channel MAX-2"]
    ADC14CH0MAP_1,
}
impl ADC14CH0MAPW {
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _bits(&self) -> bool {
        match *self {
            ADC14CH0MAPW::ADC14CH0MAP_0 => false,
            ADC14CH0MAPW::ADC14CH0MAP_1 => true,
        }
    }
}
#[doc = r" Proxy"]
pub struct _ADC14CH0MAPW<'a> {
    w: &'a mut W,
}
impl<'a> _ADC14CH0MAPW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: ADC14CH0MAPW) -> &'a mut W {
        {
            self.bit(variant._bits())
        }
    }
    #[doc = "ADC input channel internal 0 is not selected"]
    #[inline]
    pub fn adc14ch0map_0(self) -> &'a mut W {
        self.variant(ADC14CH0MAPW::ADC14CH0MAP_0)
    }
    #[doc = "ADC input channel internal 0 is selected for ADC input channel MAX-2"]
    #[inline]
    pub fn adc14ch0map_1(self) -> &'a mut W {
        self.variant(ADC14CH0MAPW::ADC14CH0MAP_1)
    }
    #[doc = r" Sets the field bit"]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r" Clears the field bit"]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub fn bit(self, value: bool) -> &'a mut W {
        const MASK: bool = true;
        const OFFSET: u8 = 24;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `ADC14CH1MAP`"]
pub enum ADC14CH1MAPW {
    #[doc = "ADC input channel internal 1 is not selected"]
    ADC14CH1MAP_0,
    #[doc = "ADC input channel internal 1 is selected for ADC input channel MAX-3"]
    ADC14CH1MAP_1,
}
impl ADC14CH1MAPW {
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _bits(&self) -> bool {
        match *self {
            ADC14CH1MAPW::ADC14CH1MAP_0 => false,
            ADC14CH1MAPW::ADC14CH1MAP_1 => true,
        }
    }
}
#[doc = r" Proxy"]
pub struct _ADC14CH1MAPW<'a> {
    w: &'a mut W,
}
impl<'a> _ADC14CH1MAPW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: ADC14CH1MAPW) -> &'a mut W {
        {
            self.bit(variant._bits())
        }
    }
    #[doc = "ADC input channel internal 1 is not selected"]
    #[inline]
    pub fn adc14ch1map_0(self) -> &'a mut W {
        self.variant(ADC14CH1MAPW::ADC14CH1MAP_0)
    }
    #[doc = "ADC input channel internal 1 is selected for ADC input channel MAX-3"]
    #[inline]
    pub fn adc14ch1map_1(self) -> &'a mut W {
        self.variant(ADC14CH1MAPW::ADC14CH1MAP_1)
    }
    #[doc = r" Sets the field bit"]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r" Clears the field bit"]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub fn bit(self, value: bool) -> &'a mut W {
        const MASK: bool = true;
        const OFFSET: u8 = 25;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `ADC14CH2MAP`"]
pub enum ADC14CH2MAPW {
    #[doc = "ADC input channel internal 2 is not selected"]
    ADC14CH2MAP_0,
    #[doc = "ADC input channel internal 2 is selected for ADC input channel MAX-4"]
    ADC14CH2MAP_1,
}
impl ADC14CH2MAPW {
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _bits(&self) -> bool {
        match *self {
            ADC14CH2MAPW::ADC14CH2MAP_0 => false,
            ADC14CH2MAPW::ADC14CH2MAP_1 => true,
        }
    }
}
#[doc = r" Proxy"]
pub struct _ADC14CH2MAPW<'a> {
    w: &'a mut W,
}
impl<'a> _ADC14CH2MAPW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: ADC14CH2MAPW) -> &'a mut W {
        {
            self.bit(variant._bits())
        }
    }
    #[doc = "ADC input channel internal 2 is not selected"]
    #[inline]
    pub fn adc14ch2map_0(self) -> &'a mut W {
        self.variant(ADC14CH2MAPW::ADC14CH2MAP_0)
    }
    #[doc = "ADC input channel internal 2 is selected for ADC input channel MAX-4"]
    #[inline]
    pub fn adc14ch2map_1(self) -> &'a mut W {
        self.variant(ADC14CH2MAPW::ADC14CH2MAP_1)
    }
    #[doc = r" Sets the field bit"]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r" Clears the field bit"]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub fn bit(self, value: bool) -> &'a mut W {
        const MASK: bool = true;
        const OFFSET: u8 = 26;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `ADC14CH3MAP`"]
pub enum ADC14CH3MAPW {
    #[doc = "ADC input channel internal 3 is not selected"]
    ADC14CH3MAP_0,
    #[doc = "ADC input channel internal 3 is selected for ADC input channel MAX-5"]
    ADC14CH3MAP_1,
}
impl ADC14CH3MAPW {
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _bits(&self) -> bool {
        match *self {
            ADC14CH3MAPW::ADC14CH3MAP_0 => false,
            ADC14CH3MAPW::ADC14CH3MAP_1 => true,
        }
    }
}
#[doc = r" Proxy"]
pub struct _ADC14CH3MAPW<'a> {
    w: &'a mut W,
}
impl<'a> _ADC14CH3MAPW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: ADC14CH3MAPW) -> &'a mut W {
        {
            self.bit(variant._bits())
        }
    }
    #[doc = "ADC input channel internal 3 is not selected"]
    #[inline]
    pub fn adc14ch3map_0(self) -> &'a mut W {
        self.variant(ADC14CH3MAPW::ADC14CH3MAP_0)
    }
    #[doc = "ADC input channel internal 3 is selected for ADC input channel MAX-5"]
    #[inline]
    pub fn adc14ch3map_1(self) -> &'a mut W {
        self.variant(ADC14CH3MAPW::ADC14CH3MAP_1)
    }
    #[doc = r" Sets the field bit"]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r" Clears the field bit"]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub fn bit(self, value: bool) -> &'a mut W {
        const MASK: bool = true;
        const OFFSET: u8 = 27;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
impl R {
    #[doc = r" Value of the register as raw bits"]
    #[inline]
    pub fn bits(&self) -> u32 {
        self.bits
    }
    #[doc = "Bits 0:1 - ADC14 power modes"]
    #[inline]
    pub fn adc14pwrmd(&self) -> ADC14PWRMDR {
        ADC14PWRMDR::_from({
            const MASK: u8 = 3;
            const OFFSET: u8 = 0;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        })
    }
    #[doc = "Bit 2 - ADC14 reference buffer burst"]
    #[inline]
    pub fn adc14refburst(&self) -> ADC14REFBURSTR {
        ADC14REFBURSTR::_from({
            const MASK: bool = true;
            const OFFSET: u8 = 2;
            ((self.bits >> OFFSET) & MASK as u32) != 0
        })
    }
    #[doc = "Bit 3 - ADC14 data read-back format"]
    #[inline]
    pub fn adc14df(&self) -> ADC14DFR {
        ADC14DFR::_from({
            const MASK: bool = true;
            const OFFSET: u8 = 3;
            ((self.bits >> OFFSET) & MASK as u32) != 0
        })
    }
    #[doc = "Bits 4:5 - ADC14 resolution"]
    #[inline]
    pub fn adc14res(&self) -> ADC14RESR {
        ADC14RESR::_from({
            const MASK: u8 = 3;
            const OFFSET: u8 = 4;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        })
    }
    #[doc = "Bits 16:20 - ADC14 conversion start address"]
    #[inline]
    pub fn adc14cstartadd(&self) -> ADC14CSTARTADDR {
        let bits = {
            const MASK: u8 = 31;
            const OFFSET: u8 = 16;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        };
        ADC14CSTARTADDR { bits }
    }
    #[doc = "Bit 22 - Controls 1/2 AVCC ADC input channel selection"]
    #[inline]
    pub fn adc14batmap(&self) -> ADC14BATMAPR {
        ADC14BATMAPR::_from({
            const MASK: bool = true;
            const OFFSET: u8 = 22;
            ((self.bits >> OFFSET) & MASK as u32) != 0
        })
    }
    #[doc = "Bit 23 - Controls temperature sensor ADC input channel selection"]
    #[inline]
    pub fn adc14tcmap(&self) -> ADC14TCMAPR {
        ADC14TCMAPR::_from({
            const MASK: bool = true;
            const OFFSET: u8 = 23;
            ((self.bits >> OFFSET) & MASK as u32) != 0
        })
    }
    #[doc = "Bit 24 - Controls internal channel 0 selection to ADC input channel MAX-2"]
    #[inline]
    pub fn adc14ch0map(&self) -> ADC14CH0MAPR {
        ADC14CH0MAPR::_from({
            const MASK: bool = true;
            const OFFSET: u8 = 24;
            ((self.bits >> OFFSET) & MASK as u32) != 0
        })
    }
    #[doc = "Bit 25 - Controls internal channel 1 selection to ADC input channel MAX-3"]
    #[inline]
    pub fn adc14ch1map(&self) -> ADC14CH1MAPR {
        ADC14CH1MAPR::_from({
            const MASK: bool = true;
            const OFFSET: u8 = 25;
            ((self.bits >> OFFSET) & MASK as u32) != 0
        })
    }
    #[doc = "Bit 26 - Controls internal channel 2 selection to ADC input channel MAX-4"]
    #[inline]
    pub fn adc14ch2map(&self) -> ADC14CH2MAPR {
        ADC14CH2MAPR::_from({
            const MASK: bool = true;
            const OFFSET: u8 = 26;
            ((self.bits >> OFFSET) & MASK as u32) != 0
        })
    }
    #[doc = "Bit 27 - Controls internal channel 3 selection to ADC input channel MAX-5"]
    #[inline]
    pub fn adc14ch3map(&self) -> ADC14CH3MAPR {
        ADC14CH3MAPR::_from({
            const MASK: bool = true;
            const OFFSET: u8 = 27;
            ((self.bits >> OFFSET) & MASK as u32) != 0
        })
    }
}
impl W {
    #[doc = r" Reset value of the register"]
    #[inline]
    pub fn reset_value() -> W {
        W { bits: 48 }
    }
    #[doc = r" Writes raw bits to the register"]
    #[inline]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.bits = bits;
        self
    }
    #[doc = "Bits 0:1 - ADC14 power modes"]
    #[inline]
    pub fn adc14pwrmd(&mut self) -> _ADC14PWRMDW {
        _ADC14PWRMDW { w: self }
    }
    #[doc = "Bit 2 - ADC14 reference buffer burst"]
    #[inline]
    pub fn adc14refburst(&mut self) -> _ADC14REFBURSTW {
        _ADC14REFBURSTW { w: self }
    }
    #[doc = "Bit 3 - ADC14 data read-back format"]
    #[inline]
    pub fn adc14df(&mut self) -> _ADC14DFW {
        _ADC14DFW { w: self }
    }
    #[doc = "Bits 4:5 - ADC14 resolution"]
    #[inline]
    pub fn adc14res(&mut self) -> _ADC14RESW {
        _ADC14RESW { w: self }
    }
    #[doc = "Bits 16:20 - ADC14 conversion start address"]
    #[inline]
    pub fn adc14cstartadd(&mut self) -> _ADC14CSTARTADDW {
        _ADC14CSTARTADDW { w: self }
    }
    #[doc = "Bit 22 - Controls 1/2 AVCC ADC input channel selection"]
    #[inline]
    pub fn adc14batmap(&mut self) -> _ADC14BATMAPW {
        _ADC14BATMAPW { w: self }
    }
    #[doc = "Bit 23 - Controls temperature sensor ADC input channel selection"]
    #[inline]
    pub fn adc14tcmap(&mut self) -> _ADC14TCMAPW {
        _ADC14TCMAPW { w: self }
    }
    #[doc = "Bit 24 - Controls internal channel 0 selection to ADC input channel MAX-2"]
    #[inline]
    pub fn adc14ch0map(&mut self) -> _ADC14CH0MAPW {
        _ADC14CH0MAPW { w: self }
    }
    #[doc = "Bit 25 - Controls internal channel 1 selection to ADC input channel MAX-3"]
    #[inline]
    pub fn adc14ch1map(&mut self) -> _ADC14CH1MAPW {
        _ADC14CH1MAPW { w: self }
    }
    #[doc = "Bit 26 - Controls internal channel 2 selection to ADC input channel MAX-4"]
    #[inline]
    pub fn adc14ch2map(&mut self) -> _ADC14CH2MAPW {
        _ADC14CH2MAPW { w: self }
    }
    #[doc = "Bit 27 - Controls internal channel 3 selection to ADC input channel MAX-5"]
    #[inline]
    pub fn adc14ch3map(&mut self) -> _ADC14CH3MAPW {
        _ADC14CH3MAPW { w: self }
    }
}