Initial commit
commit
205f9411fb
|
|
@ -0,0 +1,33 @@
|
|||
#[target.thumbv7m-none-eabi]
|
||||
# uncomment this to make `cargo run` execute programs on QEMU
|
||||
# runner = "qemu-system-arm -cpu cortex-m3 -machine lm3s6965evb -nographic -semihosting-config enable=on,target=native -kernel"
|
||||
|
||||
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
|
||||
# uncomment ONE of these three option to make `cargo run` start a GDB session
|
||||
# which option to pick depends on your system
|
||||
# runner = "arm-none-eabi-gdb -q -x openocd.gdb"
|
||||
runner = "gdb-multiarch -q -x openocd.gdb"
|
||||
# runner = "gdb -q -x openocd.gdb"
|
||||
|
||||
rustflags = [
|
||||
# LLD (shipped with the Rust toolchain) is used as the default linker
|
||||
"-C", "link-arg=-Tlink.x",
|
||||
|
||||
# if you run into problems with LLD switch to the GNU linker by commenting out
|
||||
# this line
|
||||
# "-C", "linker=arm-none-eabi-ld",
|
||||
|
||||
# if you need to link to pre-compiled C libraries provided by a C toolchain
|
||||
# use GCC as the linker by commenting out both lines above and then
|
||||
# uncommenting the three lines below
|
||||
# "-C", "linker=arm-none-eabi-gcc",
|
||||
# "-C", "link-arg=-Wl,-Tlink.x",
|
||||
# "-C", "link-arg=-nostartfiles",
|
||||
]
|
||||
|
||||
[build]
|
||||
# Pick ONE of these compilation targets
|
||||
# target = "thumbv6m-none-eabi" # Cortex-M0 and Cortex-M0+
|
||||
# target = "thumbv7m-none-eabi" # Cortex-M3
|
||||
# target = "thumbv7em-none-eabi" # Cortex-M4 and Cortex-M7 (no FPU)
|
||||
target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
**/*.rs.bk
|
||||
.#*
|
||||
.gdb_history
|
||||
Cargo.lock
|
||||
target/
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
[package]
|
||||
authors = ["Levi Pearson <levipearson@gmail.com>"]
|
||||
edition = "2018"
|
||||
readme = "README.md"
|
||||
name = "msp432-app"
|
||||
version = "0.1.0"
|
||||
|
||||
[dependencies]
|
||||
cortex-m = "0.5.8"
|
||||
cortex-m-rt = "0.6.5"
|
||||
cortex-m-semihosting = "0.3.2"
|
||||
panic-halt = "0.2.0"
|
||||
panic-semihosting = "*"
|
||||
msp432p401r = { path = "../msp432p401r", features = ["rt"] }
|
||||
|
||||
# Uncomment for the panic example.
|
||||
# panic-itm = "0.4.0"
|
||||
|
||||
# Uncomment for the allocator example.
|
||||
# alloc-cortex-m = "0.3.5"
|
||||
|
||||
# this lets you use `cargo fix`!
|
||||
[[bin]]
|
||||
name = "msp432-app"
|
||||
test = false
|
||||
bench = false
|
||||
|
||||
[profile.release]
|
||||
codegen-units = 1 # better optimizations
|
||||
debug = true # symbols are nice and they don't increase the size on Flash
|
||||
lto = true # better optimizations
|
||||
|
|
@ -0,0 +1,129 @@
|
|||
# `cortex-m-quickstart`
|
||||
|
||||
> A template for building applications for ARM Cortex-M microcontrollers
|
||||
|
||||
This project is developed and maintained by the [Cortex-M team][team].
|
||||
|
||||
## Dependencies
|
||||
|
||||
To build embedded programs using this template you'll need:
|
||||
|
||||
- Rust 1.31, 1.30-beta, nightly-2018-09-13 or a newer toolchain. e.g. `rustup
|
||||
default beta`
|
||||
|
||||
- The `cargo generate` subcommand. [Installation
|
||||
instructions](https://github.com/ashleygwilliams/cargo-generate#installation).
|
||||
|
||||
- `rust-std` components (pre-compiled `core` crate) for the ARM Cortex-M
|
||||
targets. Run:
|
||||
|
||||
``` console
|
||||
$ rustup target add thumbv6m-none-eabi thumbv7m-none-eabi thumbv7em-none-eabi thumbv7em-none-eabihf
|
||||
```
|
||||
|
||||
## Using this template
|
||||
|
||||
**NOTE**: This is the very short version that only covers building programs. For
|
||||
the long version, which additionally covers flashing, running and debugging
|
||||
programs, check [the embedded Rust book][book].
|
||||
|
||||
[book]: https://rust-embedded.github.io/book
|
||||
|
||||
0. Before we begin you need to identify some characteristics of the target
|
||||
device as these will be used to configure the project:
|
||||
|
||||
- The ARM core. e.g. Cortex-M3.
|
||||
|
||||
- Does the ARM core include an FPU? Cortex-M4**F** and Cortex-M7**F** cores do.
|
||||
|
||||
- How much Flash memory and RAM does the target device has? e.g. 256 KiB of
|
||||
Flash and 32 KiB of RAM.
|
||||
|
||||
- Where are Flash memory and RAM mapped in the address space? e.g. RAM is
|
||||
commonly located at address `0x2000_0000`.
|
||||
|
||||
You can find this information in the data sheet or the reference manual of your
|
||||
device.
|
||||
|
||||
In this example we'll be using the STM32F3DISCOVERY. This board contains an
|
||||
STM32F303VCT6 microcontroller. This microcontroller has:
|
||||
|
||||
- A Cortex-M4F core that includes a single precision FPU
|
||||
|
||||
- 256 KiB of Flash located at address 0x0800_0000.
|
||||
|
||||
- 40 KiB of RAM located at address 0x2000_0000. (There's another RAM region but
|
||||
for simplicity we'll ignore it).
|
||||
|
||||
1. Instantiate the template.
|
||||
|
||||
``` console
|
||||
$ cargo generate --git https://github.com/rust-embedded/cortex-m-quickstart
|
||||
Project Name: app
|
||||
Creating project called `app`...
|
||||
Done! New project created /tmp/app
|
||||
|
||||
$ cd app
|
||||
```
|
||||
|
||||
2. Set a default compilation target. There are four options as mentioned at the
|
||||
bottom of `.cargo/config`. For the STM32F303VCT6, which has a Cortex-M4F
|
||||
core, we'll pick the `thumbv7em-none-eabihf` target.
|
||||
|
||||
``` console
|
||||
$ tail -n6 .cargo/config
|
||||
```
|
||||
|
||||
``` toml
|
||||
[build]
|
||||
# Pick ONE of these compilation targets
|
||||
# target = "thumbv6m-none-eabi" # Cortex-M0 and Cortex-M0+
|
||||
# target = "thumbv7m-none-eabi" # Cortex-M3
|
||||
# target = "thumbv7em-none-eabi" # Cortex-M4 and Cortex-M7 (no FPU)
|
||||
target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
|
||||
```
|
||||
|
||||
3. Enter the memory region information into the `memory.x` file.
|
||||
|
||||
``` console
|
||||
$ cat memory.x
|
||||
/* Linker script for the STM32F303VCT6 */
|
||||
MEMORY
|
||||
{
|
||||
/* NOTE 1 K = 1 KiBi = 1024 bytes */
|
||||
FLASH : ORIGIN = 0x08000000, LENGTH = 256K
|
||||
RAM : ORIGIN = 0x20000000, LENGTH = 40K
|
||||
}
|
||||
```
|
||||
|
||||
4. Build the template application or one of the examples.
|
||||
|
||||
``` console
|
||||
$ cargo build
|
||||
```
|
||||
|
||||
# License
|
||||
|
||||
This template is licensed under either of
|
||||
|
||||
- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
|
||||
http://www.apache.org/licenses/LICENSE-2.0)
|
||||
|
||||
- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
|
||||
|
||||
at your option.
|
||||
|
||||
## Contribution
|
||||
|
||||
Unless you explicitly state otherwise, any contribution intentionally submitted
|
||||
for inclusion in the work by you, as defined in the Apache-2.0 license, shall be
|
||||
dual licensed as above, without any additional terms or conditions.
|
||||
|
||||
## Code of Conduct
|
||||
|
||||
Contribution to this crate is organized under the terms of the [Rust Code of
|
||||
Conduct][CoC], the maintainer of this crate, the [Cortex-M team][team], promises
|
||||
to intervene to uphold that code of conduct.
|
||||
|
||||
[CoC]: https://www.rust-lang.org/policies/code-of-conduct
|
||||
[team]: https://github.com/rust-embedded/wg#the-cortex-m-team
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
use std::env;
|
||||
use std::fs::File;
|
||||
use std::io::Write;
|
||||
use std::path::PathBuf;
|
||||
|
||||
fn main() {
|
||||
// Put the linker script somewhere the linker can find it
|
||||
let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
|
||||
File::create(out.join("memory.x"))
|
||||
.unwrap()
|
||||
.write_all(include_bytes!("memory.x"))
|
||||
.unwrap();
|
||||
println!("cargo:rustc-link-search={}", out.display());
|
||||
|
||||
// Only re-run the build script when memory.x is changed,
|
||||
// instead of when any part of the source code changes.
|
||||
println!("cargo:rerun-if-changed=memory.x");
|
||||
}
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
MEMORY
|
||||
{
|
||||
/* NOTE 1 K = 1 KiBi = 1024 bytes */
|
||||
/* Code Zone - 0x00000000 to 0x1FFFFFFF */
|
||||
FLASH : ORIGIN = 0x00000000, LENGTH = 256K
|
||||
RAM_ALIAS : ORIGIN = 0x01000000, LENGTH = 64K
|
||||
ROM : ORIGIN = 0x02000000, LENGTH = 32K
|
||||
/* SRAM Region - 0x00000000 to 0x003FFFFF */
|
||||
RAM : ORIGIN = 0x20000000, LENGTH = 64K
|
||||
RAM_BITBAND : ORIGIN = 0x22000000, LENGTH = 1024K
|
||||
}
|
||||
|
||||
/* This is where the call stack will be allocated. */
|
||||
/* The stack is of the full descending type. */
|
||||
/* You may want to use this variable to locate the call stack and static
|
||||
variables in different memory regions. Below is shown the default value */
|
||||
/* _stack_start = ORIGIN(RAM) + LENGTH(RAM); */
|
||||
|
||||
/* You can use this symbol to customize the location of the .text section */
|
||||
/* If omitted the .text section will be placed right after the .vector_table
|
||||
section */
|
||||
/* This is required only on microcontrollers that store some configuration right
|
||||
after the vector table */
|
||||
/* _stext = ORIGIN(FLASH) + 0x400; */
|
||||
|
||||
/* Example of putting non-initialized variables into custom RAM locations. */
|
||||
/* This assumes you have defined a region RAM2 above, and in the Rust
|
||||
sources added the attribute `#[link_section = ".ram2bss"]` to the data
|
||||
you want to place there. */
|
||||
/* Note that the section will not be zero-initialized by the runtime! */
|
||||
/* SECTIONS {
|
||||
.ram2bss (NOLOAD) : ALIGN(4) {
|
||||
*(.ram2bss);
|
||||
. = ALIGN(4);
|
||||
} > RAM2
|
||||
} INSERT AFTER .bss;
|
||||
*/
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
# OpenOCD configuration for the MSP432P401R LaunchPad
|
||||
|
||||
source [find interface/xds110.cfg]
|
||||
adapter_khz 2500
|
||||
transport select swd
|
||||
source [find target/ti_msp432.cfg]
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
target extended-remote :3333
|
||||
|
||||
# print demangled symbols
|
||||
set print asm-demangle on
|
||||
|
||||
# set backtrace limit to not have infinite backtrace loops
|
||||
set backtrace limit 32
|
||||
|
||||
# detect unhandled exceptions, hard faults and panics
|
||||
break DefaultHandler
|
||||
break HardFault
|
||||
break rust_begin_unwind
|
||||
|
||||
# *try* to stop at the user entry point (it might be gone due to inlining)
|
||||
break main
|
||||
|
||||
monitor arm semihosting enable
|
||||
|
||||
# # send captured ITM to the file itm.fifo
|
||||
# # (the microcontroller SWO pin must be connected to the programmer SWO pin)
|
||||
# # 8000000 must match the core clock frequency
|
||||
# monitor tpiu config internal itm.txt uart off 8000000
|
||||
|
||||
# # OR: make the microcontroller SWO pin output compatible with UART (8N1)
|
||||
# # 8000000 must match the core clock frequency
|
||||
# # 2000000 is the frequency of the SWO pin
|
||||
# monitor tpiu config external uart off 8000000 2000000
|
||||
|
||||
# # enable ITM port 0
|
||||
# monitor itm port 0 on
|
||||
|
||||
#load
|
||||
|
||||
# start the process but immediately halt the processor
|
||||
#stepi
|
||||
|
|
@ -0,0 +1,96 @@
|
|||
//! Debugging a crash (exception)
|
||||
//!
|
||||
//! Most crash conditions trigger a hard fault exception, whose handler is defined via
|
||||
//! `exception!(HardFault, ..)`. The `HardFault` handler has access to the exception frame, a
|
||||
//! snapshot of the CPU registers at the moment of the exception.
|
||||
//!
|
||||
//! This program crashes and the `HardFault` handler prints to the console the contents of the
|
||||
//! `ExceptionFrame` and then triggers a breakpoint. From that breakpoint one can see the backtrace
|
||||
//! that led to the exception.
|
||||
//!
|
||||
//! ``` text
|
||||
//! (gdb) continue
|
||||
//! Program received signal SIGTRAP, Trace/breakpoint trap.
|
||||
//! __bkpt () at asm/bkpt.s:3
|
||||
//! 3 bkpt
|
||||
//!
|
||||
//! (gdb) backtrace
|
||||
//! #0 __bkpt () at asm/bkpt.s:3
|
||||
//! #1 0x080030b4 in cortex_m::asm::bkpt () at $$/cortex-m-0.5.0/src/asm.rs:19
|
||||
//! #2 rust_begin_unwind (args=..., file=..., line=99, col=5) at $$/panic-semihosting-0.2.0/src/lib.rs:87
|
||||
//! #3 0x08001d06 in core::panicking::panic_fmt () at libcore/panicking.rs:71
|
||||
//! #4 0x080004a6 in crash::hard_fault (ef=0x20004fa0) at examples/crash.rs:99
|
||||
//! #5 0x08000548 in UserHardFault (ef=0x20004fa0) at <exception macros>:10
|
||||
//! #6 0x0800093a in HardFault () at asm.s:5
|
||||
//! Backtrace stopped: previous frame identical to this frame (corrupt stack?)
|
||||
//! ```
|
||||
//!
|
||||
//! In the console output one will find the state of the Program Counter (PC) register at the time
|
||||
//! of the exception.
|
||||
//!
|
||||
//! ``` text
|
||||
//! panicked at 'HardFault at ExceptionFrame {
|
||||
//! r0: 0x2fffffff,
|
||||
//! r1: 0x2fffffff,
|
||||
//! r2: 0x080051d4,
|
||||
//! r3: 0x080051d4,
|
||||
//! r12: 0x20000000,
|
||||
//! lr: 0x08000435,
|
||||
//! pc: 0x08000ab6,
|
||||
//! xpsr: 0x61000000
|
||||
//! }', examples/crash.rs:106:5
|
||||
//! ```
|
||||
//!
|
||||
//! This register contains the address of the instruction that caused the exception. In GDB one can
|
||||
//! disassemble the program around this address to observe the instruction that caused the
|
||||
//! exception.
|
||||
//!
|
||||
//! ``` text
|
||||
//! (gdb) disassemble/m 0x08000ab6
|
||||
//! Dump of assembler code for function core::ptr::read_volatile:
|
||||
//! 451 pub unsafe fn read_volatile<T>(src: *const T) -> T {
|
||||
//! 0x08000aae <+0>: sub sp, #16
|
||||
//! 0x08000ab0 <+2>: mov r1, r0
|
||||
//! 0x08000ab2 <+4>: str r0, [sp, #8]
|
||||
//!
|
||||
//! 452 intrinsics::volatile_load(src)
|
||||
//! 0x08000ab4 <+6>: ldr r0, [sp, #8]
|
||||
//! -> 0x08000ab6 <+8>: ldr r0, [r0, #0]
|
||||
//! 0x08000ab8 <+10>: str r0, [sp, #12]
|
||||
//! 0x08000aba <+12>: ldr r0, [sp, #12]
|
||||
//! 0x08000abc <+14>: str r1, [sp, #4]
|
||||
//! 0x08000abe <+16>: str r0, [sp, #0]
|
||||
//! 0x08000ac0 <+18>: b.n 0x8000ac2 <core::ptr::read_volatile+20>
|
||||
//!
|
||||
//! 453 }
|
||||
//! 0x08000ac2 <+20>: ldr r0, [sp, #0]
|
||||
//! 0x08000ac4 <+22>: add sp, #16
|
||||
//! 0x08000ac6 <+24>: bx lr
|
||||
//!
|
||||
//! End of assembler dump.
|
||||
//! ```
|
||||
//!
|
||||
//! `ldr r0, [r0, #0]` caused the exception. This instruction tried to load (read) a 32-bit word
|
||||
//! from the address stored in the register `r0`. Looking again at the contents of `ExceptionFrame`
|
||||
//! we see that the `r0` contained the address `0x2FFF_FFFF` when this instruction was executed.
|
||||
//!
|
||||
//! ---
|
||||
|
||||
#![no_main]
|
||||
#![no_std]
|
||||
|
||||
extern crate panic_halt;
|
||||
|
||||
use core::ptr;
|
||||
|
||||
use cortex_m_rt::entry;
|
||||
|
||||
#[entry]
|
||||
fn main() -> ! {
|
||||
unsafe {
|
||||
// read an address outside of the RAM region; this causes a HardFault exception
|
||||
ptr::read_volatile(0x2FFF_FFFF as *const u32);
|
||||
}
|
||||
|
||||
loop {}
|
||||
}
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
//! Overriding an exception handler
|
||||
//!
|
||||
//! You can override an exception handler using the [`#[exception]`][1] attribute.
|
||||
//!
|
||||
//! [1]: https://rust-embedded.github.io/cortex-m-rt/0.6.1/cortex_m_rt_macros/fn.exception.html
|
||||
//!
|
||||
//! ---
|
||||
|
||||
#![deny(unsafe_code)]
|
||||
#![no_main]
|
||||
#![no_std]
|
||||
|
||||
extern crate panic_halt;
|
||||
|
||||
use cortex_m::peripheral::syst::SystClkSource;
|
||||
use cortex_m::Peripherals;
|
||||
use cortex_m_rt::{entry, exception};
|
||||
use cortex_m_semihosting::hprint;
|
||||
|
||||
#[entry]
|
||||
fn main() -> ! {
|
||||
let p = Peripherals::take().unwrap();
|
||||
let mut syst = p.SYST;
|
||||
|
||||
// configures the system timer to trigger a SysTick exception every second
|
||||
syst.set_clock_source(SystClkSource::Core);
|
||||
syst.set_reload(8_000_000); // period = 1s
|
||||
syst.enable_counter();
|
||||
syst.enable_interrupt();
|
||||
|
||||
loop {}
|
||||
}
|
||||
|
||||
#[exception]
|
||||
fn SysTick() {
|
||||
hprint!(".").unwrap();
|
||||
}
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
//! Prints "Hello, world!" on the host console using semihosting
|
||||
|
||||
#![no_main]
|
||||
#![no_std]
|
||||
|
||||
extern crate panic_halt;
|
||||
|
||||
use cortex_m_rt::entry;
|
||||
use cortex_m_semihosting::{debug, hprintln};
|
||||
|
||||
#[entry]
|
||||
fn main() -> ! {
|
||||
hprintln!("Hello, world!").unwrap();
|
||||
|
||||
// exit QEMU
|
||||
// NOTE do not run this on hardware; it can corrupt OpenOCD state
|
||||
debug::exit(debug::EXIT_SUCCESS);
|
||||
|
||||
loop {}
|
||||
}
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
//! Sends "Hello, world!" through the ITM port 0
|
||||
//!
|
||||
//! ITM is much faster than semihosting. Like 4 orders of magnitude or so.
|
||||
//!
|
||||
//! **NOTE** Cortex-M0 chips don't support ITM.
|
||||
//!
|
||||
//! You'll have to connect the microcontroller's SWO pin to the SWD interface. Note that some
|
||||
//! development boards don't provide this option.
|
||||
//!
|
||||
//! You'll need [`itmdump`] to receive the message on the host plus you'll need to uncomment two
|
||||
//! `monitor` commands in the `.gdbinit` file.
|
||||
//!
|
||||
//! [`itmdump`]: https://docs.rs/itm/0.2.1/itm/
|
||||
//!
|
||||
//! ---
|
||||
|
||||
#![no_main]
|
||||
#![no_std]
|
||||
|
||||
extern crate panic_halt;
|
||||
|
||||
use cortex_m::{iprintln, Peripherals};
|
||||
use cortex_m_rt::entry;
|
||||
|
||||
#[entry]
|
||||
fn main() -> ! {
|
||||
let mut p = Peripherals::take().unwrap();
|
||||
let stim = &mut p.ITM.stim[0];
|
||||
|
||||
iprintln!(stim, "Hello, world!");
|
||||
|
||||
loop {}
|
||||
}
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
//! Changing the panicking behavior
|
||||
//!
|
||||
//! The easiest way to change the panicking behavior is to use a different [panic handler crate][0].
|
||||
//!
|
||||
//! [0]: https://crates.io/keywords/panic-impl
|
||||
|
||||
#![no_main]
|
||||
#![no_std]
|
||||
|
||||
// Pick one of these panic handlers:
|
||||
|
||||
// `panic!` halts execution; the panic message is ignored
|
||||
extern crate panic_halt;
|
||||
|
||||
// Reports panic messages to the host stderr using semihosting
|
||||
// NOTE to use this you need to uncomment the `panic-semihosting` dependency in Cargo.toml
|
||||
// extern crate panic_semihosting;
|
||||
|
||||
// Logs panic messages using the ITM (Instrumentation Trace Macrocell)
|
||||
// NOTE to use this you need to uncomment the `panic-itm` dependency in Cargo.toml
|
||||
// extern crate panic_itm;
|
||||
|
||||
use cortex_m_rt::entry;
|
||||
|
||||
#[entry]
|
||||
fn main() -> ! {
|
||||
panic!("Oops")
|
||||
}
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
//! Conditionally compiling tests with std and our executable with no_std.
|
||||
//!
|
||||
//! Rust's built in unit testing framework requires the standard library,
|
||||
//! but we need to build our final executable with no_std.
|
||||
//! The testing framework also generates a `main` method, so we need to only use the `#[entry]`
|
||||
//! annotation when building our final image.
|
||||
//! For more information on why this example works, see this excellent blog post.
|
||||
//! https://os.phil-opp.com/unit-testing/
|
||||
//!
|
||||
//! Running this example:
|
||||
//!
|
||||
//! Ensure there are no targets specified under `[build]` in `.cargo/config`
|
||||
//! In order to make this work, we lose the convenience of having a default target that isn't the
|
||||
//! host.
|
||||
//!
|
||||
//! cargo build --example test_on_host --target thumbv7m-none-eabi
|
||||
//! cargo test --example test_on_host
|
||||
|
||||
#![cfg_attr(test, allow(unused_imports))]
|
||||
|
||||
#![cfg_attr(not(test), no_std)]
|
||||
#![cfg_attr(not(test), no_main)]
|
||||
|
||||
// pick a panicking behavior
|
||||
#[cfg(not(test))]
|
||||
extern crate panic_halt; // you can put a breakpoint on `rust_begin_unwind` to catch panics
|
||||
// extern crate panic_abort; // requires nightly
|
||||
// extern crate panic_itm; // logs messages over ITM; requires ITM support
|
||||
// extern crate panic_semihosting; // logs messages to the host stderr; requires a debugger
|
||||
|
||||
use cortex_m::asm;
|
||||
use cortex_m_rt::entry;
|
||||
|
||||
#[cfg(not(test))]
|
||||
#[entry]
|
||||
fn main() -> ! {
|
||||
asm::nop(); // To not have main optimize to abort in release mode, remove when you add code
|
||||
|
||||
loop {
|
||||
// your code goes here
|
||||
}
|
||||
}
|
||||
|
||||
fn add(a: i32, b: i32) -> i32 {
|
||||
a + b
|
||||
}
|
||||
|
||||
#[cfg(test)]
|
||||
mod test {
|
||||
use super::*;
|
||||
|
||||
#[test]
|
||||
fn foo() {
|
||||
println!("tests work!");
|
||||
assert!(2 == add(1,1));
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
#![no_std]
|
||||
#![no_main]
|
||||
|
||||
// pick a panicking behavior
|
||||
extern crate panic_halt; // you can put a breakpoint on `rust_begin_unwind` to catch panics
|
||||
// extern crate panic_abort; // requires nightly
|
||||
// extern crate panic_itm; // logs messages over ITM; requires ITM support
|
||||
// extern crate panic_semihosting; // logs messages to the host stderr; requires a debugger
|
||||
|
||||
use cortex_m::{self, peripheral::syst::SystClkSource};
|
||||
use cortex_m_rt::entry;
|
||||
use msp432p401r;
|
||||
|
||||
use core::num::Wrapping;
|
||||
|
||||
const PIN0: u8 = (1u8 << 0);
|
||||
const PIN1: u8 = (1u8 << 1);
|
||||
const PIN2: u8 = (1u8 << 2);
|
||||
//const PIN3: u8 = (1u8 << 3);
|
||||
const PIN4: u8 = (1u8 << 4);
|
||||
//const PIN5: u8 = (1u8 << 5);
|
||||
//const PIN6: u8 = (1u8 << 6);
|
||||
//const PIN7: u8 = (1u8 << 7);
|
||||
|
||||
const WDOG_PWORD: u8 = 0x5a;
|
||||
|
||||
#[entry]
|
||||
fn main() -> ! {
|
||||
let cp = cortex_m::Peripherals::take().unwrap();
|
||||
let p = msp432p401r::Peripherals::take().unwrap();
|
||||
|
||||
let mut syst = cp.SYST;
|
||||
let wdt = p.WDT_A;
|
||||
let dio = p.DIO;
|
||||
|
||||
// disable watchdog timer
|
||||
wdt.wdtctl.write(|w| unsafe {
|
||||
w.wdtpw().bits(WDOG_PWORD)
|
||||
.wdthold().wdthold_1()
|
||||
});
|
||||
|
||||
// configure the system timer to wrap around every ~1 second
|
||||
syst.set_clock_source(SystClkSource::Core);
|
||||
syst.set_reload(20_000);
|
||||
syst.enable_counter();
|
||||
|
||||
// configure digital IO pins
|
||||
dio.padir.modify(|_r, w| unsafe {
|
||||
w.p1dir().bits(PIN0)
|
||||
.p2dir().bits(PIN0 | PIN1 | PIN2)
|
||||
});
|
||||
|
||||
// Enable pull-up on P1.4 switch
|
||||
dio.paren.modify(|_r, w| unsafe { w.p1ren().bits(PIN4) });
|
||||
dio.pads.modify(|_r, w| unsafe { w.p1ds().bits(PIN4) });
|
||||
|
||||
// Turn on LED1 on P1.0 and enable pull-up on P1.1 switch
|
||||
dio.paout.write(|w| unsafe {
|
||||
w.p1out().bits(PIN0 | PIN4)
|
||||
.p2out().bits(0)
|
||||
});
|
||||
|
||||
let mut count: Wrapping<u16> = Wrapping(0);
|
||||
let mut input: u8;
|
||||
loop {
|
||||
while !syst.has_wrapped() {}
|
||||
|
||||
// The button pulls the input to GND
|
||||
input = (dio.pain.read().p1in().bits() & PIN4) >> 4;
|
||||
|
||||
count += Wrapping(1);
|
||||
let _led1: u8 = ((count.0 & 0x0100) >> 8) as u8;
|
||||
let led2: u8 = ((count.0 & 0b0000_0111_0000_0000) >> 8) as u8;
|
||||
|
||||
// toggle LEDs
|
||||
dio.paout.write(|w| unsafe {
|
||||
w.p1out().bits(input | PIN4)
|
||||
.p2out().bits(led2)
|
||||
});
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue