diff --git a/.gdbinit b/.gdbinit index 7c72d4f..e9e5086 100644 --- a/.gdbinit +++ b/.gdbinit @@ -1,6 +1,5 @@ target remote :3333 -monitor arm semihosting enable load step diff --git a/Cargo.toml b/Cargo.toml index a6d3511..da0d85f 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -1,5 +1,5 @@ [package] -name = "blue_pill_base" +name = "blue_pill_rtic" version = "0.1.0" authors = ["Levi Pearson "] description = "Base binary crate for STM32F103 Blue Pill boards" @@ -11,15 +11,17 @@ cortex-m = "0.6.2" cortex-m-rt = "0.6.12" #cortex-m-semihosting = "0.3.5" # alternate panic impls, choose only one! -panic-halt = "0.2.0" +#panic-halt = "0.2.0" #panic-semihosting = "0.5.3" # requires cortex-m-semihosting #panic-itm = "0.4.1" #panic-abort = "0.3.2" #panic-ramdump = "0.1.1" #panic-persist = "0.2.1" +panic-rtt-target = { version = "0.1.0", features = ["cortex-m"] } embedded-hal = "0.2.3" nb = "0.1.2" rtt-target = { version = "0.2.0", features = ["cortex-m"] } +cortex-m-rtic = "0.5.0" [dependencies.stm32f1] version = "0.10.0" @@ -30,7 +32,7 @@ version = "0.5.3" features = ["rt", "stm32f103", "medium"] [[bin]] -name = "blue_pill_base" +name = "blue_pill_rtic" test = false bench = false diff --git a/openocd.cfg b/openocd.cfg index 88b2e9c..6afa9fb 100644 --- a/openocd.cfg +++ b/openocd.cfg @@ -1,5 +1,8 @@ # Sample OpenOCD configuration for the blue pill board +# Some microcontrollers have a different CPU ID; uncomment this if yours is one +set CPUTAPID 0x2ba01477 + # Depending on the hardware revision you got you'll have to pick ONE of these # interfaces. At any time only one interface should be commented out. diff --git a/src/main.rs b/src/main.rs index 504351c..a1b859c 100644 --- a/src/main.rs +++ b/src/main.rs @@ -9,66 +9,127 @@ #![no_std] #![no_main] -//use panic_halt as _; -use core::panic::PanicInfo; use rtt_target::{rprintln, rtt_init_print}; - -use nb::block; +use panic_rtt_target as _; use stm32f1xx_hal::{ prelude::*, - pac, - timer::Timer, + stm32, + timer::{Timer, Event}, }; -use cortex_m_rt::entry; -use embedded_hal::digital::v2::OutputPin; +use core::sync::atomic::{self, Ordering}; -#[entry] -fn main() -> ! { - // Init buffers for debug printing - rtt_init_print!(); - // Get access to the core peripherals from the cortex-m crate - let cp = cortex_m::Peripherals::take().unwrap(); - // Get access to the device specific peripherals from the peripheral access crate - let dp = pac::Peripherals::take().unwrap(); +use stm32f1xx_hal as hal; - // Take ownership over the raw flash and rcc devices and convert them into the corresponding - // HAL structs - let mut flash = dp.FLASH.constrain(); - let mut rcc = dp.RCC.constrain(); +#[rtic::app(device = stm32f1xx_hal::stm32, peripherals = true)] +const APP: () = { + // Defining this struct makes shared resources available to tasks; if + // they can't be statically initialized, they will be initialized by + // the values returned from `init` + struct Resources { + // resources -- these are statically initialized via `init` attributes + #[init(0)] + beat: u8, - // Freeze the configuration of all the clocks in the system and store the frozen frequencies in - // `clocks` - let clocks = rcc.cfgr.freeze(&mut flash.acr); + // late resources -- these must be initialized in the `init` task and + // returned in `init::LateResources` + led1: hal::gpio::gpioc::PC13>, + tmr2: hal::timer::CountDownTimer, + tmr3: hal::timer::CountDownTimer, + } - // Acquire the GPIOC peripheral - let mut gpioc = dp.GPIOC.split(&mut rcc.apb2); + // This task does startup config; the peripherals are passed in thanks to + // `peripherals = true` in the app definition. They are the `device` and + // `core` fields of `init::Context`. + // Any dynamically-configured shared resources in `Resources` must be + // returned as part of `init::LateResources`. + #[init] + fn init(cx: init::Context) -> init::LateResources { + rtt_init_print!(); + rprintln!("init begin"); - // Configure gpio C pin 13 as a push-pull output. The `crh` register is passed to the function - // in order to configure the port. For pins 0-7, crl should be passed instead. - let mut led = gpioc.pc13.into_push_pull_output(&mut gpioc.crh); - // Configure the syst timer to trigger an update every second - let mut timer = Timer::syst(cp.SYST, &clocks).start_count_down(1.hz()); + // Set everything to 8MHz using the external clock + let mut flash = cx.device.FLASH.constrain(); + let mut rcc = cx.device.RCC.constrain(); + let clocks = rcc + .cfgr + .use_hse(8.mhz()) + .sysclk(8.mhz()) + .hclk(8.mhz()) + .pclk1(8.mhz()) + .pclk2(8.mhz()) + .adcclk(8.mhz()) + .freeze(&mut flash.acr); - rprintln!("Hello, Rust!"); - // Wait for the timer to trigger an update and change the state of the LED - let mut i = 0; - loop { - block!(timer.wait()).unwrap(); - led.set_high().unwrap(); - block!(timer.wait()).unwrap(); - led.set_low().unwrap(); - i += 1; - rprintln!("Hello again; I have blinked {} times.", i); - if i == 10 { - panic!("Yow, 10 times is enough!"); + // LED is on pin C13, configure it for output + let mut gpioc = cx.device.GPIOC.split(&mut rcc.apb2); + let led1 = gpioc.pc13.into_push_pull_output(&mut gpioc.crh); + + // Use TIM2 for the beat counter task + let mut tmr2 = Timer::tim2(cx.device.TIM2, &clocks, &mut rcc.apb1) + .start_count_down(1.hz()); + tmr2.listen(Event::Update); + + // Use TIM3 for the LED blinker task + let mut tmr3 = Timer::tim3(cx.device.TIM3, &clocks, &mut rcc.apb1) + .start_count_down(2.hz()); + tmr3.listen(Event::Update); + + rprintln!("init end"); + + init::LateResources { + led1, + tmr2, + tmr3, } } -} -#[inline(never)] -#[panic_handler] -fn panic(info: &PanicInfo) -> ! { - rprintln!("{}", info); - loop {} // You might need a compiler fence in here. -} + #[idle] + fn idle(_: idle::Context) -> ! { + loop { + // The compiler may omit this loop without the following + atomic::compiler_fence(Ordering::SeqCst); + } + } + + // Update the beat counter and periodically display the current count + // on the RTT channel + #[task(resources = [beat])] + fn beat_update(cx: beat_update::Context) { + if *cx.resources.beat % 10 == 0 { + rprintln!("TIM2 beat = {}", *cx.resources.beat); + } + + *cx.resources.beat += 1; + } + + // Interrupt task for TIM2, the beat counter timer + #[task(binds = TIM2, priority = 2, resources = [tmr2], spawn = [beat_update])] + fn tim2(cx: tim2::Context) { + // Delegate the state update to a software task + cx.spawn.beat_update().unwrap(); + + // Restart the timer and clear the interrupt flag + cx.resources.tmr2.start(1.hz()); + cx.resources.tmr2.clear_update_interrupt_flag(); + } + + // Interrupt task for TIM3, the LED blink timer + #[task(binds = TIM3, priority = 1, resources = [led1, tmr3])] + fn tim3(cx: tim3::Context) { + cx.resources.led1.toggle().unwrap(); + cx.resources.tmr3.start(2.hz()); + cx.resources.tmr3.clear_update_interrupt_flag(); + } + + // RTIC requires that unused interrupts are declared in an extern block when + // using software tasks; these free interrupts will be used to dispatch the + // software tasks. + // + // For a list, see: + // https://docs.rs/stm32f1xx-hal/0.6.1/stm32f1xx_hal/stm32/enum.Interrupt.html + extern "C" { + fn TAMPER(); + } +}; +