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# Microcontroller Basics
## CPU
You probably know what a CPU is, but there are some details that are significant to embedded programming.
By itself, a CPU is inert; it needs some things around it to function.
+ clock signal
+ reset signal
+ bus interface(s)
Reset may seem trivial, but it is actually critical; digital circuits as complex as CPUs have many stateful components, and in order to work correctly they have to start at a correct initial state. That is the job of the power-on reset signal.
The clock signal is the heartbeat of stateful digital circuits. Everything transitions at a clock edge, inputs are captured at a clock edge, outputs are asserted at a clock edge. Most CPUs are designed entirely with synchronous logic today and therefore nothing (at the level of logic, anyway) happens between clock cycles.
The ARM Cortex-M3 processor in the STM32F103 has 3 separate bus interfaces that it uses for specific purposes, but in this system they use the same address map, so we will treat them as one interface for now.
The bus interface is critical because a CPU can do very little without instructions, and when it comes out of reset a CPU has none. The first thing it does is to use its bus interface to fetch the top-of-stack address from address 0x00000000, then the location of its first instruction to execute from the next location, 0x00000004. That location is called the "Reset Vector"; it informs the CPU the address of the instructions it should execute when it comes out of reset.
The CPU itself follows instructions from the ARM Thumb-1 and Thumb-2 instruction sets; these are a more compact encoding of classic ARM instructions. It has relatively fast integer multiply and divide instructions, but no floating point unit!
The CPU has an exception-handling mechanism; when an exception condition arises, the CPU switches to "handler mode" and uses the exception vector table to determine what address it should execute from in order to handle the type of exception it received. It has a separate stack pointer for running in handler mode.
## Bus
Most microcontrollers today don't just have a single bus, but a complex hierarchy of different types of buses. But from the CPU's perspective, it appears as a unified address space. Sometimes the details of the bus structure matter, but when starting the simplified view is fine.
The function of the bus is to translate requests from "bus masters" such as the CPU into operations on peripherals that are also connected to the bus. Peripherals are mapped into different regions of the address space, which on a 32-bit addressed bus like the one we are dealing with, is 4GB in size.
Different buses have different protocols for how requests are made and responded to, but generally a master asserts an address and some information about the request, such as whether it is a read request or write request, and whether it is for the full data width of the bus or some subset of it. If the address corresponds to a region mapped to a peripheral, that peripheral is given an enable signal and reads the details of the request from the bus, performs the operation, and signals completion.
Real buses, including the ones on our microcontroller, are far more complex in their protocols, but this description should be good enough to start with.
## RAM
Memory is just a peripheral on the bus that responds to a write operation by storing the data from the bus at the address (suitably translated into its internal addressing scheme) that was on the bus. A subsequent read operation with the same address asserted on the bus will cause the memory to write the same data back to the bus.
In other words, the range of addresses mapped to RAM act just like you would expect memory to act.
## Flash
Flash memory is a form of electrically-erasable read-only memory. It is typically used to store your program's instructions and data. The Flash peripheral has two regions mapped into memory; one region acts as read-only memory, and another region presents a set of read/write control registers that you can manipulate to erase, re-program, and adjust the access latency of the peripheral.
## Peripherals
Peripherals are pieces of hardware, part of the microcontroller chip, that can be controlled by the CPU (or any bus master on their bus, in fact) by manipulating a set of read/write control regions that are mapped into the bus address space. These can include I/O peripherals, co-processors, or different kinds of memories.
## Clock Tree
Just as the CPU needs a clock to function, all of the peripherals need clocks to function as well, and they often need to be running at different clock rates than the CPU or each other.
Clocks can either be generated by oscillating circuits internal to the microcontroller or from external oscillating circuits. There is generally a dedicated peripheral for selecting the source oscillator for core system clocks, controlling clock manipulation circuitry such as dividers, multipliers, or even fancy Phase-Locked-Loop-based clock frequency synthesizers.
Many peripheral register sets will have their own clock logic to pick among several system or external sources for their clocking as well, and may even have their own sets of clock dividers that you can choose from.
Setting up the microcontroller's clock tree properly for the peripherals you need to use and the CPU operating frequency you want can be surprisingly complex!
## Power Management
Because many microcontrollers end up running from batteries, power consumption can be very important, and most have fairly fine-grained power control over parts of the chip. The STM32 we are using is fortunately configured out of reset in a useful configuration, so you should only need to investigate these controls if you want to reduce power consumption.
## Pin Multiplexing
Most microcontrollers have far more I/O peripheral signals than they have pins. This means that most pins on the external package can serve more than one peripheral depending on how you configure things. Sometimes, a peripheral can choose between multiple pins for a signal, so that you can select different sets of pins depending on which other peripherals are in use.
Like clock trees, getting the right pin multiplexing configuration can be tricky!
## I/O & Communication Standards
### Voltage Levels
While digital logic has two states, the voltage level on microcontroller pins varies continuously. There are important things to know:
+ What is the nominal voltage level of the "high" signal?
+ What is the nominal voltage level of the "low" signal?
+ What is the lowest voltage that is reliably considered "high" by an input pin?
+ What is the highest voltage that is reliably considered "low" by an input pin?
+ What is the lowest voltage that a will be driven "high" by an output pin?
+ What is the highest voltage that will be driven "low" by an output pin?
+ What is the highest voltage that can be tolerated without damage?
+ What is the lowest voltage that can be tolerated without damage?
You can usually consider "high" values to be all around the source voltage of the controller, and "low" values to be near 0. You should never expose a pin on a microcontroller to a higher voltage than the source voltage powering the microcontroller unless you are certain that it is tolerant of higher voltages.
The STM32F103 has a 3.3V source voltage, so its nominal logic "high" level is 3.3V and the "low" level is 0V. Unusually, many (but not all!) of its I/O pins are 5V tolerant. They can act as inputs to a 5V signal without damage, but they cannot drive their outputs to 5V; they can only indicate logic "high" to a 5V device that recognizes 3.3V as a logic "high" level. This is true of 5V TTL logic, but not of 5V CMOS logic. A 5V CMOS logic input needs at least 3.7V to sense a "high" level, while a 5V TTL input only requires 2V to see a "high" level.
This is not very important if you keep all devices at the same nominal logic level, but when you need to interface devices at different levels the details will determine which strategies will be available.
### Push/Pull vs. Open Collector
When the input of one device is connected to the output of another, the output usually either pushes current to drive the voltage level high, or it pulls (or sinks) current to drive the voltage low. In this configuration, only one device can drive the wire; anything else connected to the wire must passively sense the voltage level.
It is possible to allow multiple devices to drive a wire if they instead work in "open collector" mode. An open collector output will never push current to the wire, it only sinks current to drive the wire low. The high state of the wire is passively determined by "pulling up" the wire through a high-value resistor to the voltage source. Any number of devices can pull the wire low simultaneously without damaging one another.
### Current Limits/Requirements
Microcontrollers are usually not designed to supply or sink a lot of current to other devices. There is usually both a per-pin limit and a total limit for all pins. Exceeding this limit can damage your microcontroller, so if you want to use a microcontroller to make something happen (drive a motor, turn on a light, etc.) be sure to use appropriate current-limiting resistors and employ some sort of external circuitry to interface with things that require a lot of power.
Plenty of cheap add-on boards are available that have this kind of circuitry in place for driving various kinds of lights, motors, relays, etc. if you don't feel comfortable with the calculations to design it yourself yet.
### Single-Ended vs. Differential
A signal is called "single-ended" if the "high" and "low" voltage levels are determined with respect to a common 0V ground level between endpoints. This is how most low-speed signals on a circuit board work, and how most of the communication protocols supported by peripherals on a STM32F103 work.
Many newer and higher-speed communication protocols use a different technique called "differential" signaling; this uses a pair of driven wires rather than a single driven wire to determine a single signal, but it is much more robust against certain kinds of interference. It works by always driving one of the wires to the opposite level of the other, and measuring the output level by determining which of the wires at the receiver has a higher voltage than the other.
Communication standards that use differential signaling that you may be familiar with are USB, DVI/HDMI, Ethernet, and CAN. The STM32F103 supports both USB and CAN, although you don't need to understand all the signal-level details of those protocols to use them!
### Synchronous vs. Asynchronous
A communication signal is "synchronous" if there is a shared clock signal that the endpoints use to sample the data signal. A communication signal is "asynchronous" if there is no clock, and timing has to be managed independently by sender and receiver according to a pre-arranged data rate.
The most common asynchronous signal you are likely to use is the UART-based serial signal. UART stands for "Universal Asynchronous Receiver/Transmitter". Both ends have to be configured for the same transmission rate, which is measured in "baud" for historical reasons, but this corresponds to bits per second most of the time. Successful communication over a UART link requires both ends to have their sampling clocks running at close enough to the same rate that a full byte can be received before enough drift occurs that data is sampled at the wrong point by the receiver.
Both common protocols for linking a microcontroller to external peripherals, I2C and SPI, are synchronous. One device provides the clock, and both ensure that the data signal is driven or is sampled correctly relative to the clock signal edges.
## Peripheral Types
### GPIO
General Purpose Input/Output
Most of the pins on your microcontroller can be used to do input or output under direct software control. The GPIO peripheral registers allow you to configure whether each pin is to be an input or ouput and whether it is to be under software control or the control of a peripheral.
When under software control, your code can directly read or change the state of a single pin or set of pins in a bank. While this is very flexible, it is often faster and more reliable to take advantage of the I/O peripherals to do complex protocol exchanges. Software-controlled GPIO is often used for scanning a key matrix, lighting a few individual LEDs, or other simple tasks that depend on direct I/O connections rather than a serial communication line to an external peripheral chip.
When you use software-controlled GPIO signals to implement a communication protocol instead of using a peripheral dedicated to that protocol, it is often called "bit-banging" that protocol.
### Timer
Uses a clock to increment or decrement a register on every clock edge. Beyond that common principle, operation and uses can vary a lot!
A basic use for a timer is to create a periodic interrupt for the CPU. All Cortex M3 CPUs have a SysTick timer that can be used as a one-shot or periodic exception that occurs when the timer reaches 0.
Some timers can be used in capture mode, where the register counts continuously and the current value is copied to a capture register when an external (or sometimes internal from another peripheral) signal change occurs. This can be used to measure the rate that some external event occurs, for example.
Some timers can be used in compare mode, where the register counts continuously and causes some action to happen when the timer reaches the value stored on the compare register. There can be multiple compare registers, and different kinds of actions. A common case is for one compare register to toggle the state of a pin, and the other to switch the count direction from up to down. This has the effect of creating a pulse-width modulated signal on the pin.
A special kind of timer called a "watchdog" can be used for production systems to trigger a system reset if your code goes into a fault condition or otherwise becomes unresponsive. To keep this reset from happening, you must "feed" or "pet" the watchdog timer every cycle before it expires.
By arranging for a timer to send a signal to another peripheral instead of an external pin, you can schedule periodic sampling of an analog-to-digital converter, or periodic transfer of a buffer to a communication peripheral by a DMA peripheral.
Clever use of timers with peripherals can take a great deal of load and complexity out of your software and ensure that timing-critical tasks are carried out more precisely than software is easily capable of.
### I2C
Inter-Integrated Circuit
Protocol overview: https://i2c.info/
This is a 2-wire synchronous serial bus protocol. The two signals are named:
+ SCL - Clock (Up to 100kHz in slow mode, up to 400kHz in fast mode)
+ SDA - Data (address and data multiplexed)
It is a multi-master bus protocol; the STM32F103 can function as master or slave. Devices on the bus use open-collector I/O, pulled-up externally to 3.3V. Each device has a unique address, either 7 or 10 bits depending on the mode, but we'll only worry about 7-bit mode for now. Data is sampled on the rising edge of the clock.
A master-mode device initiates a transaction by pulling the data line low for one bit period while leaving the clock line high; this is called the "start" signal.
It then clocks out 7 bits of address, followed by a 1 to indicate a write transaction or a 0 to indicate a read transaction.
After clocking out the 8th bit, it releases the bus and cycles the clock one more time. This is the "ack" cycle, and the receiver pulls the data line low during this clock cycle as an acknowledgment. This "ack" cycle is repeated after every byte of data is transmitted by either party, and the other is responsible for doing the acknowledgment.
If a write transaction was indicated, the master device can continue clocking out bytes, waiting for an "ack" after each one, until it is finished with the transaction. If a read transaction was indicated, the slave device takes over driving the data line while the master cycles the clock and acknowledges the slave bytes. The master can end the transaction by leaving the data line high during the "ack" cycle, which signals "nack".
At the end of a transaction, the master signals that the bus is free by letting the data line transition from low to high while the clock line is high. This makes the "stop" symbol.
Sometimes a devices will require the master to write a value to the slave, then immediately perform a read again. Rather than sending a "stop" followed by a "start", the master can just send "start"; this is known as "repeated start". It still has to follow with the slave address, this time indicating a write transaction. The write-followed-by-read pair is often used when a slave devices has multiple internal registers to read from. The write selects the register, and the read reads its value.
The I2C peripheral also supports the closely related SMBus protocol, which is used on PC motherboards for talking to memory sticks, batteries, temperature sensors, etc.
### SPI
Serial Peripheral Interface
This is another synchronous serial bus protocol with the capability to be full-duplex. It is generally a single-master bus, and each slave requires a dedicated chip select signal. There are too many variations to go into; this is just the basic operation.
Common signals:
+ SCLK - Clock (as fast as both devices and the board layout can support)
+ MISO - Master In, Slave Out Data
+ MOSI - Master Out, Slave In Data
+ CS - Chip Select (one per slave, usually active-low)
The master is in charge of driving the clock. It may clock out one bit of data on MOSI every clock cycle and clock in one bit of data every clock cycle from MISO.
If a slave device's chip select is inactive, it will ignore all other signals. When active, it may clock out one bit of data for every clock cycle on MOSI and clock in one bit of data from MISO.
Depending on the master and slave, it is possible for both to stream bits out continuously on every clock cycle indefinitely without any start/stop bits, parity bits, etc. and without any particular byte or word divisions. In practice, however, both tend to work in chunks of at least 8 bits and have some sort of device-specific interaction protocol that you will have to read the slave device data sheet to determine.
Because of its ability to continuously shift out bits at a precise rate, the SPI peripheral is often put to off-brand use as an arbitrary digital signal generator on the MOSI line.
### DMA
Direct Memory Access
A DMA peripheral is one of the few devices on a bus that can act as a bus master and initiate bus transactions. It is typically used to arrange for a transfer to occur from one bus address to another without the CPU having to be involved.
DMA operations are programmed separately into one of the available DMA channels. The channel gets a source address, destination address, and a transfer size. You can usually arrange for either or both of the addresses to increment by some value after a transfer completes, and sometimes you can arrange for addresses to wrap back to the starting value in order to implement circular buffer operations.
DMA transfers are initiated by a signal called a DMA request, which usually comes from a peripheral, although a control bit can be set by software to manually initiate one. The signal may come from a timer, a communication port, or an analog-to-digital converter; it is up to you to enable the correct signal linkage for the peripheral you want to use DMA with.
The DMA peripheral can signal to software via interrupt at different stages of its transfer operation, in case you need to take some action at those times to ensure that whatever process DMA is enabling continues to run smoothly.
### ADC
Analog to Digital Conversion
This translates a voltage level between 0V and a reference voltage into a digital value, i.e. a number. It has 12 bits of precision, meaning that 4096 discrete values can be reported between 0V and the reference voltage. With a 3.3V reference, that means a measurement precision of under 1 millivolt. A conversion takes a minimum of 1 microsecond to complete, so there is a theoretical maximum sample rate of one million per second.
Conversion channels can be set to sample continuously (re-triggering upon completion) or they can be triggered periodically by a timer signal. Completion of conversion (on some channels, at least) can trigger a DMA transfer. These can be used to collect a circular buffer of captured samples in memory at a precise sample rate.
One of the ADC channels (16) is connected to an internal temperature sensor, and another (17) is connected to an internal voltage reference.
There are a wide variety of analog sensors that can be read with an ADC, and they can also be used for user interface devices. A common use is to adjust some parameter by reading the voltage from the wiper contact of a potentiometer, which can form the basis of a game paddle or joystick axis. You can also read a multi-button control strip by clever use of resistor voltage dividers that get switched in and out of circuit by pressing buttons.
### USART
Universal Synchronous/Asynchronous Receiver/Transmitter
In asynchronous mode, this can be used as a familiar serial port that you can connect to your computer via a serial-to-USB adapter. You can't connect directly to an old RS232 serial port, however–although the signals follow the same pattern, RS232 uses different voltage levels and could damage your microcontroller!
The baud rate generator can run at up to 4.5Mbit/s, and you can select 8 or 9 bit word length (i.e. 0 or 1 parity bits) and 1 or 2 stop bits.
Additional serial protocols supported by this peripheral include LIN (an automotive bus), IrDA SIR (infrared remote control), and Smartcard emulation.
### USB
Universal Serial Bus
The USB peripheral supports USB 2.0 Full Speed, which can operate at up to 12Mbit/s. It functions only as a device (rather than host or on-the-go modes) and supports up to 8 endpoints.
The protocol is too complex to go into much detail about, but Rust libraries exist to help you create HID (keyboards, mice, game controllers), serial, or MIDI endpoints.
### CAN
Controller-Area Network
CAN is a serial bus networking protocol that supports a potentially large number of endpoints on a single twisted-pair differential bus. It has a priority-based bus arbitration scheme and networks can be engineered to meet communication latency and reliability goals.
Use of this automotive/industrial control protocol would require an external transceiver device, and it cannot be used concurrently with USB due to sharing a SRAM buffer, so we will not describe it further. But you may want to explore it if you are interested in how devices within your car communicate, or if you want to create a wired home automation network with numerous communicating sensors and control surfaces.